OpenCores
URL https://opencores.org/ocsvn/a-z80/a-z80/trunk

Subversion Repositories a-z80

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /a-z80/trunk
    from Rev 13 to Rev 14
    ↔ Reverse comparison
  •

Rev 13 → Rev 14

/cpu/alu/alu_flags.bdf
484,6 → 484,22
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(pin
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(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
650,7 → 666,7
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(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
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(drawing
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746,7 → 762,7
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(drawing
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906,7 → 922,7
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938,7 → 954,7
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1295,7 → 1311,7
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(drawing
1328,7 → 1344,7
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(pt 0 16)
(input)
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 14 16))
)
(port
(pt 0 32)
(input)
(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
(line (pt 0 32)(pt 14 32))
)
(port
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 42 24)(pt 64 24))
)
(drawing
(line (pt 14 12)(pt 30 12))
(line (pt 14 37)(pt 31 37))
(line (pt 14 12)(pt 14 37))
(arc (pt 31 37)(pt 30 12)(rect 18 12 43 37))
)
)
(connector
(pt 368 416)
(pt 384 416)
2922,10 → 3002,6
(pt 288 1200)
)
(connector
(pt 464 1232)
(pt 480 1232)
)
(connector
(pt 304 1248)
(pt 256 1248)
)
2934,14 → 3010,6
(pt 232 592)
)
(connector
(pt 200 1312)
(pt 400 1312)
)
(connector
(pt 368 1328)
(pt 400 1328)
)
(connector
(pt 288 1200)
(pt 288 1176)
)
3193,14 → 3261,6
(pt 304 1264)
)
(connector
(pt 200 1360)
(pt 304 1360)
)
(connector
(pt 304 1360)
(pt 440 1360)
)
(connector
(pt 920 1416)
(pt 936 1416)
)
3641,30 → 3701,6
(pt 592 632)
)
(connector
(pt 480 1232)
(pt 480 1288)
)
(connector
(pt 480 1288)
(pt 504 1288)
)
(connector
(pt 464 1320)
(pt 504 1320)
)
(connector
(pt 440 1360)
(pt 440 1448)
)
(connector
(pt 504 1448)
(pt 440 1448)
)
(connector
(pt 568 1416)
(pt 632 1416)
)
(connector
(pt 232 1432)
(pt 288 1432)
)
3685,10 → 3721,6
(pt 232 1432)
)
(connector
(pt 400 1416)
(pt 504 1416)
)
(connector
(pt 200 1464)
(pt 288 1464)
)
3801,14 → 3833,6
(pt 624 576)
)
(connector
(pt 632 1400)
(pt 600 1400)
)
(connector
(pt 600 1288)
(pt 600 1400)
)
(connector
(pt 200 1576)
(pt 744 1576)
)
3833,65 → 3857,149
(pt 840 1424)
)
(connector
(pt 248 1392)
(pt 248 1416)
)
(connector
(text "sel[0]" (rect 206 1376 233 1388)(font "Arial" ))
(pt 200 1392)
(pt 248 1392)
)
(connector
(text "sel[1]" (rect 204 1400 231 1412)(font "Arial" ))
(pt 200 1416)
(pt 248 1416)
)
(connector
(text "sel[1..0]" (rect 251 1400 291 1412)(font "Arial" ))
(pt 288 1416)
(pt 248 1416)
(bus)
)
(connector
(pt 200 1648)
(pt 208 1648)
)
(connector
(pt 632 1400)
(pt 616 1400)
)
(connector
(pt 616 1288)
(pt 616 1400)
)
(connector
(pt 200 1552)
(pt 600 1552)
(pt 616 1552)
)
(connector
(pt 600 1432)
(pt 600 1552)
(pt 616 1432)
(pt 616 1552)
)
(connector
(pt 632 1432)
(pt 600 1432)
(pt 616 1432)
)
(connector
(pt 480 1528)
(pt 600 1288)
(pt 616 1288)
)
(connector
(pt 616 1288)
(pt 912 1288)
)
(connector
(pt 632 1416)
(pt 600 1416)
)
(connector
(pt 400 1416)
(pt 536 1416)
)
(connector
(pt 200 1360)
(pt 304 1360)
)
(connector
(pt 304 1360)
(pt 408 1360)
)
(connector
(pt 536 1304)
(pt 520 1304)
)
(connector
(pt 520 1432)
(pt 536 1432)
)
(connector
(pt 200 1528)
(pt 520 1528)
)
(connector
(pt 504 1432)
(pt 480 1432)
(pt 520 1304)
(pt 520 1432)
)
(connector
(pt 480 1528)
(pt 480 1432)
(pt 520 1432)
(pt 520 1528)
)
(connector
(pt 480 1432)
(pt 480 1304)
(pt 464 1232)
(pt 520 1232)
)
(connector
(pt 504 1304)
(pt 480 1304)
(pt 520 1232)
(pt 520 1288)
)
(connector
(pt 568 1288)
(pt 600 1288)
(pt 536 1288)
(pt 520 1288)
)
(connector
(pt 600 1288)
(pt 912 1288)
(pt 536 1448)
(pt 504 1448)
)
(connector
(pt 248 1392)
(pt 248 1416)
(pt 408 1360)
(pt 408 1440)
)
(connector
(text "sel[0]" (rect 206 1376 233 1388)(font "Arial" ))
(pt 200 1392)
(pt 248 1392)
(pt 408 1440)
(pt 440 1440)
)
(connector
(text "sel[1]" (rect 204 1400 231 1412)(font "Arial" ))
(pt 200 1416)
(pt 248 1416)
(pt 536 1320)
(pt 504 1320)
)
(connector
(text "sel[1..0]" (rect 251 1400 291 1412)(font "Arial" ))
(pt 288 1416)
(pt 248 1416)
(bus)
(pt 200 1312)
(pt 440 1312)
)
(connector
(pt 368 1328)
(pt 440 1328)
)
(connector
(pt 424 1456)
(pt 440 1456)
)
(connector
(pt 424 1456)
(pt 424 1648)
)
(connector
(pt 440 1320)
(pt 424 1320)
)
(connector
(pt 424 1320)
(pt 424 1456)
)
(connector
(pt 256 1648)
(pt 424 1648)
)
(junction (pt 816 568))
(junction (pt 840 640))
(junction (pt 496 504))
3941,9 → 4049,10
(junction (pt 872 1096))
(junction (pt 728 1072))
(junction (pt 520 576))
(junction (pt 600 1288))
(junction (pt 480 1432))
(junction (pt 248 1416))
(junction (pt 616 1288))
(junction (pt 520 1432))
(junction (pt 424 1456))
(text "Connect flags directly to other modules" (rect 912 128 1133 142)(font "Arial" (font_size 8)))
(text "Carry Flag" (rect 512 1184 582 1200)(font "Arial" (font_size 10)))
(text "Parity Flag" (rect 512 904 586 920)(font "Arial" (font_size 10)))
3955,16 → 4064,16
(text "H Flag" (rect 512 528 556 544)(font "Arial" (font_size 10)))
(text "Force set" (rect 768 1440 822 1454)(font "Arial" (font_size 8)))
(text "Force complement" (rect 856 1448 959 1462)(font "Arial" (font_size 8)))
(text "Primary latch" (rect 504 1240 577 1254)(font "Arial" (font_size 8)))
(text "Secondary latch" (rect 496 1368 589 1382)(font "Arial" (font_size 8)))
(text "Primary latch" (rect 536 1240 609 1254)(font "Arial" (font_size 8)))
(text "Secondary latch" (rect 528 1368 621 1382)(font "Arial" (font_size 8)))
(title_block
(rect 872 1568 1129 1620)
(rect 808 1624 1065 1676)
(name "title-custom-small")
(section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "June 21, 2014, 2016" (rect 56 3 171 17)(font "Arial" (font_size 8)))(border))
(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "alu_flags" (rect 43 2 104 17)(font "Arial" (font_size 9)(bold)))(border))
(section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border))
(section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.6" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border))
(section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.7" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border))
(drawing
)
)
/cpu/alu/alu_flags.bsf
20,9 → 20,9
*/
(header "symbol" (version "1.2"))
(symbol
(rect 16 16 280 528)
(rect 16 16 280 560)
(text "alu_flags" (rect 5 0 56 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 496 25 508)(font "Arial" ))
(text "inst" (rect 8 528 25 540)(font "Arial" ))
(port
(pt 0 32)
(input)
227,6 → 227,13
(line (pt 0 480)(pt 16 480))
)
(port
(pt 0 496)
(input)
(text "hold_clk_wait" (rect 0 0 77 14)(font "Arial" (font_size 8)))
(text "hold_clk_wait" (rect 21 491 98 505)(font "Arial" (font_size 8)))
(line (pt 0 496)(pt 16 496))
)
(port
(pt 264 48)
(output)
(text "flags_sf" (rect 0 0 47 14)(font "Arial" (font_size 8)))
290,6 → 297,6
(line (pt 264 32)(pt 248 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 248 496))
(rectangle (rect 16 16 248 528))
)
)
/cpu/alu/alu_flags.v
14,7 → 14,7
 
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Tue Feb 23 22:17:29 2016"
// CREATED "Fri Dec 09 21:55:51 2016"
 
module alu_flags(
ctl_flags_oe,
46,6 → 46,7
clk,
ctl_flags_cf2_sel_shift,
ctl_flags_cf2_sel_daa,
hold_clk_wait,
flags_sf,
flags_zf,
flags_hf,
87,6 → 88,7
input wire clk;
input wire ctl_flags_cf2_sel_shift;
input wire ctl_flags_cf2_sel_daa;
input wire hold_clk_wait;
output wire flags_sf;
output wire flags_zf;
output wire flags_hf;
100,8 → 102,8
reg flags_xf;
reg flags_yf;
wire [1:0] sel;
reg DFFE_inst_latch_hf;
wire SYNTHESIZED_WIRE_0;
reg DFFE_inst_latch_hf;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
109,10 → 111,9
wire SYNTHESIZED_WIRE_5;
wire SYNTHESIZED_WIRE_6;
wire SYNTHESIZED_WIRE_7;
wire SYNTHESIZED_WIRE_8;
reg SYNTHESIZED_WIRE_38;
reg SYNTHESIZED_WIRE_41;
wire SYNTHESIZED_WIRE_42;
wire SYNTHESIZED_WIRE_9;
wire SYNTHESIZED_WIRE_10;
wire SYNTHESIZED_WIRE_11;
wire SYNTHESIZED_WIRE_12;
wire SYNTHESIZED_WIRE_13;
125,103 → 126,110
wire SYNTHESIZED_WIRE_20;
wire SYNTHESIZED_WIRE_21;
wire SYNTHESIZED_WIRE_22;
wire SYNTHESIZED_WIRE_23;
wire SYNTHESIZED_WIRE_24;
reg DFFE_inst_latch_sf;
wire SYNTHESIZED_WIRE_23;
wire SYNTHESIZED_WIRE_25;
reg DFFE_inst_latch_pf;
reg DFFE_inst_latch_nf;
wire SYNTHESIZED_WIRE_24;
wire SYNTHESIZED_WIRE_25;
wire SYNTHESIZED_WIRE_26;
wire SYNTHESIZED_WIRE_27;
wire SYNTHESIZED_WIRE_28;
wire SYNTHESIZED_WIRE_39;
wire SYNTHESIZED_WIRE_29;
wire SYNTHESIZED_WIRE_30;
wire SYNTHESIZED_WIRE_31;
wire SYNTHESIZED_WIRE_32;
wire SYNTHESIZED_WIRE_33;
wire SYNTHESIZED_WIRE_43;
wire SYNTHESIZED_WIRE_34;
wire SYNTHESIZED_WIRE_35;
wire SYNTHESIZED_WIRE_36;
wire SYNTHESIZED_WIRE_37;
wire SYNTHESIZED_WIRE_38;
wire SYNTHESIZED_WIRE_39;
reg DFFE_inst_latch_cf;
reg DFFE_inst_latch_cf2;
wire SYNTHESIZED_WIRE_37;
wire SYNTHESIZED_WIRE_40;
 
assign flags_sf = DFFE_inst_latch_sf;
assign flags_zf = SYNTHESIZED_WIRE_38;
assign flags_hf = SYNTHESIZED_WIRE_23;
assign flags_zf = SYNTHESIZED_WIRE_41;
assign flags_hf = SYNTHESIZED_WIRE_25;
assign flags_pf = DFFE_inst_latch_pf;
assign flags_cf = SYNTHESIZED_WIRE_24;
assign flags_cf = SYNTHESIZED_WIRE_26;
assign flags_nf = DFFE_inst_latch_nf;
assign flags_cf_latch = DFFE_inst_latch_cf;
assign SYNTHESIZED_WIRE_37 = 0;
assign SYNTHESIZED_WIRE_40 = 0;
 
 
 
assign SYNTHESIZED_WIRE_27 = ctl_flags_cf_we & SYNTHESIZED_WIRE_0;
assign SYNTHESIZED_WIRE_12 = db[7] & ctl_flags_bus;
 
assign SYNTHESIZED_WIRE_10 = db[7] & ctl_flags_bus;
assign SYNTHESIZED_WIRE_19 = alu_xf_out & ctl_flags_alu;
 
assign SYNTHESIZED_WIRE_17 = alu_xf_out & ctl_flags_alu;
assign SYNTHESIZED_WIRE_22 = db[2] & ctl_flags_bus;
 
assign SYNTHESIZED_WIRE_20 = db[2] & ctl_flags_bus;
assign SYNTHESIZED_WIRE_21 = pf_sel & ctl_flags_alu;
 
assign SYNTHESIZED_WIRE_19 = pf_sel & ctl_flags_alu;
assign SYNTHESIZED_WIRE_2 = db[1] & ctl_flags_bus;
 
assign SYNTHESIZED_WIRE_3 = db[1] & ctl_flags_bus;
assign SYNTHESIZED_WIRE_25 = DFFE_inst_latch_hf ^ ctl_flags_hf_cpl;
 
assign SYNTHESIZED_WIRE_23 = DFFE_inst_latch_hf ^ ctl_flags_hf_cpl;
assign SYNTHESIZED_WIRE_24 = db[0] & ctl_flags_bus;
 
assign SYNTHESIZED_WIRE_22 = db[0] & ctl_flags_bus;
assign SYNTHESIZED_WIRE_23 = ctl_flags_alu & alu_core_cf_out;
 
assign SYNTHESIZED_WIRE_21 = ctl_flags_alu & alu_core_cf_out;
assign SYNTHESIZED_WIRE_9 = ~ctl_flags_cf2_we;
 
assign SYNTHESIZED_WIRE_0 = ~ctl_flags_cf2_we;
assign SYNTHESIZED_WIRE_26 = SYNTHESIZED_WIRE_0 ^ ctl_flags_cf_cpl;
 
assign SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_1 ^ ctl_flags_cf_cpl;
assign SYNTHESIZED_WIRE_1 = alu_sf_out & ctl_flags_alu;
 
assign SYNTHESIZED_WIRE_2 = alu_sf_out & ctl_flags_alu;
assign SYNTHESIZED_WIRE_11 = alu_sf_out & ctl_flags_alu;
 
assign SYNTHESIZED_WIRE_9 = alu_sf_out & ctl_flags_alu;
assign SYNTHESIZED_WIRE_5 = ctl_flags_nf_set | SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;
 
assign SYNTHESIZED_WIRE_6 = ctl_flags_nf_set | SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3;
assign SYNTHESIZED_WIRE_39 = SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_4;
 
assign SYNTHESIZED_WIRE_36 = SYNTHESIZED_WIRE_4 & SYNTHESIZED_WIRE_5;
 
assign SYNTHESIZED_WIRE_34 = SYNTHESIZED_WIRE_5 & SYNTHESIZED_WIRE_6;
 
assign SYNTHESIZED_WIRE_31 = SYNTHESIZED_WIRE_6 & SYNTHESIZED_WIRE_7;
assign SYNTHESIZED_WIRE_6 = ~ctl_flags_nf_clr;
 
assign SYNTHESIZED_WIRE_7 = ~ctl_flags_nf_clr;
assign SYNTHESIZED_WIRE_7 = ~ctl_alu_zero_16bit;
 
assign SYNTHESIZED_WIRE_8 = ~ctl_alu_zero_16bit;
assign SYNTHESIZED_WIRE_4 = SYNTHESIZED_WIRE_7 | SYNTHESIZED_WIRE_41;
 
assign SYNTHESIZED_WIRE_5 = SYNTHESIZED_WIRE_8 | SYNTHESIZED_WIRE_38;
assign SYNTHESIZED_WIRE_42 = ~hold_clk_wait;
 
assign SYNTHESIZED_WIRE_12 = db[6] & ctl_flags_bus;
assign SYNTHESIZED_WIRE_29 = ctl_flags_cf_we & SYNTHESIZED_WIRE_42 & SYNTHESIZED_WIRE_9;
 
assign SYNTHESIZED_WIRE_33 = SYNTHESIZED_WIRE_9 | SYNTHESIZED_WIRE_10;
assign SYNTHESIZED_WIRE_31 = ctl_flags_cf2_we & SYNTHESIZED_WIRE_42;
 
assign SYNTHESIZED_WIRE_4 = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12;
assign SYNTHESIZED_WIRE_14 = db[6] & ctl_flags_bus;
 
assign SYNTHESIZED_WIRE_35 = SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14;
assign SYNTHESIZED_WIRE_36 = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12;
 
assign SYNTHESIZED_WIRE_39 = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;
assign SYNTHESIZED_WIRE_3 = SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14;
 
assign SYNTHESIZED_WIRE_34 = SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18;
assign SYNTHESIZED_WIRE_38 = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;
 
assign SYNTHESIZED_WIRE_32 = SYNTHESIZED_WIRE_19 | SYNTHESIZED_WIRE_20;
assign SYNTHESIZED_WIRE_43 = SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18;
 
assign SYNTHESIZED_WIRE_11 = alu_zero & ctl_flags_alu;
assign SYNTHESIZED_WIRE_37 = SYNTHESIZED_WIRE_19 | SYNTHESIZED_WIRE_20;
 
assign SYNTHESIZED_WIRE_26 = SYNTHESIZED_WIRE_21 | SYNTHESIZED_WIRE_22;
assign SYNTHESIZED_WIRE_35 = SYNTHESIZED_WIRE_21 | SYNTHESIZED_WIRE_22;
 
assign SYNTHESIZED_WIRE_13 = alu_zero & ctl_flags_alu;
 
assign SYNTHESIZED_WIRE_28 = SYNTHESIZED_WIRE_23 | SYNTHESIZED_WIRE_24;
 
assign db[7] = ctl_flags_oe ? DFFE_inst_latch_sf : 1'bz;
 
assign SYNTHESIZED_WIRE_14 = db[5] & ctl_flags_bus;
assign SYNTHESIZED_WIRE_16 = db[5] & ctl_flags_bus;
 
assign db[6] = ctl_flags_oe ? SYNTHESIZED_WIRE_38 : 1'bz;
assign db[6] = ctl_flags_oe ? SYNTHESIZED_WIRE_41 : 1'bz;
 
assign db[5] = ctl_flags_oe ? flags_yf : 1'bz;
 
assign db[4] = ctl_flags_oe ? SYNTHESIZED_WIRE_23 : 1'bz;
assign db[4] = ctl_flags_oe ? SYNTHESIZED_WIRE_25 : 1'bz;
 
assign db[3] = ctl_flags_oe ? flags_xf : 1'bz;
 
229,24 → 237,24
 
assign db[1] = ctl_flags_oe ? DFFE_inst_latch_nf : 1'bz;
 
assign db[0] = ctl_flags_oe ? SYNTHESIZED_WIRE_24 : 1'bz;
assign db[0] = ctl_flags_oe ? SYNTHESIZED_WIRE_26 : 1'bz;
 
assign SYNTHESIZED_WIRE_13 = alu_yf_out & ctl_flags_alu;
assign SYNTHESIZED_WIRE_15 = alu_yf_out & ctl_flags_alu;
 
assign SYNTHESIZED_WIRE_1 = ctl_flags_cf_set | SYNTHESIZED_WIRE_25;
assign SYNTHESIZED_WIRE_0 = ctl_flags_cf_set | SYNTHESIZED_WIRE_27;
 
assign SYNTHESIZED_WIRE_16 = db[4] & ctl_flags_bus;
assign SYNTHESIZED_WIRE_18 = db[4] & ctl_flags_bus;
 
assign SYNTHESIZED_WIRE_15 = alu_core_cf_out & ctl_flags_alu;
assign SYNTHESIZED_WIRE_17 = alu_core_cf_out & ctl_flags_alu;
 
assign SYNTHESIZED_WIRE_18 = db[3] & ctl_flags_bus;
assign SYNTHESIZED_WIRE_20 = db[3] & ctl_flags_bus;
 
 
always@(posedge clk)
begin
if (SYNTHESIZED_WIRE_27)
if (SYNTHESIZED_WIRE_29)
begin
DFFE_inst_latch_cf <= SYNTHESIZED_WIRE_26;
DFFE_inst_latch_cf <= SYNTHESIZED_WIRE_28;
end
end
 
253,9 → 261,9
 
always@(posedge clk)
begin
if (ctl_flags_cf2_we)
if (SYNTHESIZED_WIRE_31)
begin
DFFE_inst_latch_cf2 <= SYNTHESIZED_WIRE_28;
DFFE_inst_latch_cf2 <= SYNTHESIZED_WIRE_30;
end
end
 
264,7 → 272,7
begin
if (ctl_flags_hf_we)
begin
DFFE_inst_latch_hf <= SYNTHESIZED_WIRE_39;
DFFE_inst_latch_hf <= SYNTHESIZED_WIRE_43;
end
end
 
273,7 → 281,7
begin
if (ctl_flags_hf2_we)
begin
flags_hf2 <= SYNTHESIZED_WIRE_39;
flags_hf2 <= SYNTHESIZED_WIRE_43;
end
end
 
282,7 → 290,7
begin
if (ctl_flags_nf_we)
begin
DFFE_inst_latch_nf <= SYNTHESIZED_WIRE_31;
DFFE_inst_latch_nf <= SYNTHESIZED_WIRE_34;
end
end
 
291,7 → 299,7
begin
if (ctl_flags_pf_we)
begin
DFFE_inst_latch_pf <= SYNTHESIZED_WIRE_32;
DFFE_inst_latch_pf <= SYNTHESIZED_WIRE_35;
end
end
 
300,7 → 308,7
begin
if (ctl_flags_sz_we)
begin
DFFE_inst_latch_sf <= SYNTHESIZED_WIRE_33;
DFFE_inst_latch_sf <= SYNTHESIZED_WIRE_36;
end
end
 
309,7 → 317,7
begin
if (ctl_flags_xy_we)
begin
flags_xf <= SYNTHESIZED_WIRE_34;
flags_xf <= SYNTHESIZED_WIRE_37;
end
end
 
318,7 → 326,7
begin
if (ctl_flags_xy_we)
begin
flags_yf <= SYNTHESIZED_WIRE_35;
flags_yf <= SYNTHESIZED_WIRE_38;
end
end
 
327,7 → 335,7
begin
if (ctl_flags_sz_we)
begin
SYNTHESIZED_WIRE_38 <= SYNTHESIZED_WIRE_36;
SYNTHESIZED_WIRE_41 <= SYNTHESIZED_WIRE_39;
end
end
 
336,7 → 344,7
.in0(DFFE_inst_latch_cf),
.in1(DFFE_inst_latch_cf2),
.sel1(ctl_flags_use_cf2),
.out(SYNTHESIZED_WIRE_25));
.out(SYNTHESIZED_WIRE_27));
 
 
alu_mux_4 b2v_inst_mux_cf2(
343,9 → 351,9
.in0(alu_core_cf_out),
.in1(shift_cf_out),
.in2(daa_cf_out),
.in3(SYNTHESIZED_WIRE_37),
.in3(SYNTHESIZED_WIRE_40),
.sel(sel),
.out(SYNTHESIZED_WIRE_28));
.out(SYNTHESIZED_WIRE_30));
 
assign sel[0] = ctl_flags_cf2_sel_shift;
assign sel[1] = ctl_flags_cf2_sel_daa;
/cpu/toplevel/coremodules.vh
391,6 → 391,7
.clk (clk),
.ctl_flags_cf2_sel_shift (ctl_flags_cf2_sel_shift),
.ctl_flags_cf2_sel_daa (ctl_flags_cf2_sel_daa),
.hold_clk_wait (hold_clk_wait),
.flags_sf (flags_sf),
.flags_zf (flags_zf),
.flags_hf (flags_hf),
/host/common/uart.v
22,7 → 22,7
 
// Calculate UART clock based on the input clock
reg [28:0] d;
wire [28:0] inc = d[28] ? (BAUD) : (BAUD - IN_CLOCK);
wire [28:0] inc = d[28] ? 29'(BAUD) : 29'(BAUD - IN_CLOCK);
wire [28:0] delta = d + inc;
 
always @(posedge clk)
48,7 → 48,9
begin
if (wr & ~busy)
begin
// synopsys translate_off
$strobe("[UART] %c", data[7:0]);
// synopsys translate_on
shifter <= { data[7:0], 1'h0 };
bitcount <= 4'd11; // 1 + 8 + 2
end

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