OpenCores
URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 208 to Rev 209
    ↔ Reverse comparison
  •

Rev 208 → Rev 209

/aemb/trunk/rtl/verilog/aeMB2_edk63.v
132,6 → 132,7
wire [4:0] ra_of; // From ctrl0 of aeMB2_ctrl.v
wire [4:0] rd_ex; // From ctrl0 of aeMB2_ctrl.v
wire [4:0] rd_of; // From ctrl0 of aeMB2_ctrl.v
wire [31:2] rpc_ex; // From iwbif0 of aeMB2_iwbif.v
wire [31:2] rpc_if; // From iwbif0 of aeMB2_iwbif.v
wire [31:2] rpc_mx; // From iwbif0 of aeMB2_iwbif.v
wire [3:0] sel_mx; // From memif0 of aeMB2_memif.v
205,6 → 206,7
.ich_adr (ich_adr[AEMB_IWB-1:2]),
.fet_fb (fet_fb),
.rpc_if (rpc_if[31:2]),
.rpc_ex (rpc_ex[31:2]),
.rpc_mx (rpc_mx[31:2]),
.exc_iwb (exc_iwb),
// Inputs
300,6 → 302,7
.exc_ill (exc_ill),
// Inputs
.dena (dena),
.exc_dwb (exc_dwb[1:0]),
.gclk (gclk),
.gpha (gpha),
.grst (grst),
309,7 → 312,8
.opc_of (opc_of[5:0]),
.opd_of (opd_of[31:0]),
.ra_of (ra_of[4:0]),
.rd_of (rd_of[4:0]));
.rd_of (rd_of[4:0]),
.rpc_ex (rpc_ex[31:2]));
aeMB2_memif
#(/*AUTOINSTPARAM*/
/aemb/trunk/rtl/verilog/aeMB2_intu.v
31,8 → 31,8
// Outputs
mem_ex, bpc_ex, alu_ex, alu_mx, msr_ex, sfr_mx,
// Inputs
opc_of, opa_of, opb_of, opd_of, imm_of, rd_of, ra_of, gclk, grst,
dena, gpha
exc_dwb, exc_ill, rpc_ex, opc_of, opa_of, opb_of, opd_of, imm_of,
rd_of, ra_of, gclk, grst, dena, gpha
);
parameter AEMB_DWB = 32;
parameter AEMB_IWB = 32;
44,6 → 44,11
output [31:0] alu_ex,
alu_mx;
 
input [1:0] exc_dwb;
input exc_ill;
 
input [31:2] rpc_ex;
//input [2:0] mux_of;
input [5:0] opc_of;
input [31:0] opa_of;
90,6 → 95,11
rMSR_IE,
rMSR_BE;
reg [31:0] rEAR,
rEAR_C;
reg [1:0] rESR,
rESR_C;
// Infer a ADD with carry cell because ADDSUB cannot be inferred
// across technologies.
173,6 → 183,8
30 - HTE (hardware thread enabled)
29 - PHA (current phase)
9 - EIP (exception in progress)
8 - EE (exception enable)
7 - DTE (data cache enable)
5 - ITE (instruction cache enable)
4 - MTX (hardware mutex bit)
219,32 → 231,51
wire fMOV = (opc_of == 6'o45);
wire fMTS = fMOV & &imm_of[15:14];
wire fMOP = fMOV & ~|imm_of[15:14];
wire fMOP = fMOV & ~|imm_of[15:14];
wire fMFS = fMOV & imm_of[15] & !imm_of[14];
reg [31:0] sfr_ex;
reg [31:0] sfr_ex;
reg [2:0] sfr_sel;
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rMSR_BE <= 1'h0;
rMSR_BIP <= 1'h0;
rMSR_DTE <= 1'h0;
rMSR_EE <= 1'h0;
rMSR_EIP <= 1'h0;
rMSR_IE <= 1'h0;
rMSR_ITE <= 1'h0;
rMSR_MTX <= 1'h0;
sfr_ex <= 32'h0;
sfr_mx <= 32'h0;
sfr_sel <= 3'h0;
// End of automatics
end else if (dena) begin // if (grst)
sfr_mx <= #1 sfr_ex;
end else if (dena) begin
case (sfr_sel[2:0])
//3'o0: sfr_mx <= #1 {rpc_ex[31:2], 2'o0};
3'o5: sfr_mx <= #1 {30'd0, rESR_C};
3'o3: sfr_mx <= #1 rEAR_C;
3'o1: sfr_mx <= #1 {rMSR_C,
AEMB_HTX[0],
gpha,
19'd0,
rMSR_EIP,
rMSR_EE,
rMSR_DTE,
1'b0,
rMSR_ITE,
rMSR_MTX,
rMSR_BIP,
rMSR_C,
rMSR_IE,
rMSR_BE
};
default: sfr_mx <= #1 sfr_ex;
endcase // case (imm_of[2:0])
sfr_ex <= #1
{rMSR_CC,
AEMB_HTX[0],
gpha,
21'd0,
19'd0,
rMSR_EIP,
rMSR_EE,
rMSR_DTE,
1'b0,
rMSR_ITE,
254,7 → 285,25
rMSR_IE,
rMSR_BE
};
sfr_sel <= #1 imm_of[2:0];
end
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rMSR_BE <= 1'h0;
rMSR_BIP <= 1'h0;
rMSR_DTE <= 1'h0;
rMSR_EE <= 1'h0;
rMSR_EIP <= 1'h0;
rMSR_IE <= 1'h0;
rMSR_ITE <= 1'h0;
rMSR_MTX <= 1'h0;
// End of automatics
end else if (dena) begin // if (grst)
rMSR_DTE <= #1
(fMTS) ? opa_of[7] :
(fMOP) ? wRES[7] :
303,45 → 352,6
(fMOP) ? wRES[9] :
rMSR_EIP;
/*
case ({fMTS, fMOP})
2'o2: {rMSR_DTE,
rMSR_ITE,
rMSR_MTX,
rMSR_BE} <= #1 {opa_of[7],
opa_of[5],
opa_of[4],
opa_of[0]};
2'o1: {rMSR_DTE,
rMSR_ITE,
rMSR_MTX,
rMSR_BE} <= #1 {wRES[7],
wRES[5],
wRES[4],
wRES[0]};
default: {rMSR_DTE,
rMSR_ITE,
rMSR_MTX,
rMSR_BE} <= #1 {rMSR_DTE,
rMSR_ITE,
rMSR_MTX,
rMSR_BE};
endcase // case ({fMTS, fMOP})
 
case ({fMTS, fMOP})
2'o2: {rMSR_BIP,
rMSR_IE} <= #1 {opa_of[3],
opa_of[1]};
2'o1: {rMSR_BIP,
rMSR_IE} <= #1 {wRES[3],
wRES[1]};
default: begin
rMSR_BIP <= #1 (fBRKB | fRTBD) ? !rMSR_BIP : rMSR_BIP;
rMSR_IE <= #1 (fBRKI | fRTID) ? !rMSR_IE : rMSR_IE;
end
endcase // case ({fMTS, fMOP})
*/
end // if (dena)
 
// BARREL C
352,7 → 362,16
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rEAR_C <= 32'h0;
rESR_C <= 2'h0;
rMSR_CC <= 1'h0;
// End of automatics
end else if (dena) begin
rEAR_C <= #1 rEAR;
rESR_C <= #1 rESR;
rMSR_CC <= #1 rMSR_C;
//sfr_mx <= #1 sfr_ex;
end
always @(posedge gclk)
359,12 → 378,16
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rEAR <= 32'h0;
rESR <= 2'h0;
rMSR_C <= 1'h0;
rMSR_CC <= 1'h0;
// End of automatics
end else if (dena) begin
rMSR_CC <= #1 rMSR_C;
rEAR <= #1 (exc_dwb[1]) ? {mem_ex, 2'o0} : rEAR_C; // LXX/SXX
rESR <= #1 (exc_ill | exc_dwb[1]) ?
{exc_ill, exc_dwb[1]} : rESR_C; // ESR
rMSR_C <= #1
(fMTS) ? opa_of[2] :
(fMOP) ? wRES[2] :
372,16 → 395,7
(fADDSUB) ? add_c : // ADD/SUB/ADDC/SUBC
rMSR_CC;
/*
case ({fMTS,fMOP,fSHIFT,fADDSUB})
4'h8: rMSR_C <= #1 opa_of[2];
4'h4: rMSR_C <= #1 wRES[2];
4'h2: rMSR_C <= #1 opa_of[0];
4'h1: rMSR_C <= #1 add_c;
default: rMSR_C <= #1 rMSR_CC;
endcase // case ({fMTS,fMOP,fSHIFT,fADDSUB})
*/
end
end // if (dena)
endmodule // aeMB2_intu
 
/aemb/trunk/rtl/verilog/aeMB2_exec.v
34,8 → 34,8
sfr_mx, mul_mx, msr_ex, mem_ex, bsf_mx, bpc_ex, alu_mx, alu_ex,
exc_ill,
// Inputs
rd_of, ra_of, opd_of, opc_of, opb_of, opa_of, imm_of, grst, gpha,
gclk, dena
rpc_ex, rd_of, ra_of, opd_of, opc_of, opb_of, opa_of, imm_of, grst,
gpha, gclk, exc_dwb, dena
);
parameter AEMB_IWB = 32;
parameter AEMB_DWB = 32;
57,6 → 57,7
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input dena; // To bsft0 of aeMB2_bsft.v, ...
input [1:0] exc_dwb; // To intu0 of aeMB2_intu.v
input gclk; // To bsft0 of aeMB2_bsft.v, ...
input gpha; // To bsft0 of aeMB2_bsft.v, ...
input grst; // To bsft0 of aeMB2_bsft.v, ...
67,6 → 68,7
input [31:0] opd_of; // To intu0 of aeMB2_intu.v
input [4:0] ra_of; // To intu0 of aeMB2_intu.v
input [4:0] rd_of; // To intu0 of aeMB2_intu.v
input [31:2] rpc_ex; // To intu0 of aeMB2_intu.v
// End of automatics
/*AUTOWIRE*/
 
144,6 → 146,9
.msr_ex (msr_ex[9:0]),
.sfr_mx (sfr_mx[31:0]),
// Inputs
.exc_dwb (exc_dwb[1:0]),
.exc_ill (exc_ill),
.rpc_ex (rpc_ex[31:2]),
.opc_of (opc_of[5:0]),
.opa_of (opa_of[31:0]),
.opb_of (opb_of[31:0]),
/aemb/trunk/rtl/verilog/aeMB2_iwbif.v
31,10 → 31,10
module aeMB2_iwbif (/*AUTOARG*/
// Outputs
iwb_adr_o, iwb_stb_o, iwb_sel_o, iwb_wre_o, iwb_cyc_o, iwb_tag_o,
ich_adr, fet_fb, rpc_if, rpc_mx, exc_iwb,
ich_adr, fet_fb, rpc_if, rpc_ex, rpc_mx, exc_iwb,
// Inputs
iwb_ack_i, iwb_dat_i, ich_hit, msr_ex, hzd_bpc, hzd_fwd,
bra_ex, bpc_ex, gclk, grst, dena, iena, gpha
iwb_ack_i, iwb_dat_i, ich_hit, msr_ex, hzd_bpc, hzd_fwd, bra_ex,
bpc_ex, gclk, grst, dena, iena, gpha
);
parameter AEMB_IWB = 32;
parameter AEMB_HTX = 1;
58,6 → 58,7
output fet_fb;
output [31:2] rpc_if,
rpc_ex,
rpc_mx;
 
input [7:5] msr_ex;
/aemb/trunk/sw/cc/corefunc.hh
37,23 → 37,29
 
volatile int exce = 0;
 
void exceptionHandler()
volatile void _hw_exception_handler()
{
exce++; // flag the exception service routine
}
int resr;
asm volatile ("mfs %0, resr" : "=r"(resr));
 
 
volatile void _hw_exception_handler()
{
//exceptionHandler();
exce++;
asm volatile (//"lwi r15,r1,0\n"
"rted r17, 0\n"
switch (resr)
{
case 1: // unaligned
--exce;
break;
case 2: // illegal
++exce;
break;
default:
exce = 0;
break;
}
asm volatile ("rted r17, 0\n"
"nop\n");
//"addik r1,r1,28\n");
}
 
/**
/**
EXCEPTION TEST ROUTINE
*/
 
60,11 → 66,14
int exceptionTest(int timeout)
{
volatile int *toggle = (int *)0xFFFFFFE2;
 
// enable exceptions
asm volatile (".long 0xDEADC0DE"); // define illegal instruction (1 error)
 
*toggle = *toggle; // test unaligned memory access (2 errors)
// disable exceptions
return (exce != 3) ? EXIT_FAILURE : EXIT_SUCCESS;
 
return (exce != -1) ? EXIT_FAILURE : EXIT_SUCCESS;
}
 
volatile int intr = 0;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.