OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

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Rev 41 → Rev 42

/doc/ProNoC_User_manual.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/mpsoc/change.log
1,5 → 1,15
All notable changes to this project will be documented in this file.
 
##[1.8.2] -13-12-2018
## Added
- add latency standard deviation to simulation results graphs
- add Simple message passing demo on 4×4 MPSoC
- add some error flags to NI
## changed
- fix some bugs in NI
- Enable Verilator simulation on MPSoC
 
 
##[1.8.1] - 30-7-2018
## Added
- GUI for setting Linux variables
/mpsoc/perl_gui/ProNoC.pl
26,7 → 26,7
use File::Basename;
 
 
our $VERSION = '1.8.1';
our $VERSION = '1.8.2';
 
sub main{
# check if envirement variables are defined
/mpsoc/perl_gui/lib/interface/snoop.ITC
0,0 → 1,49
#######################################################################
## File: snoop.ITC
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.8.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$HashRef = bless( {
'connection_num' => 'multi connection',
'category' => 'wishbone',
'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/bus/wishbone_bus.v',
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'type' => 'socket',
'name' => 'snoop',
'ports' => {
'snoop_adr_o' => {
'connect_type' => 'input',
'default_out' => 'Active low',
'range' => 'Aw-1:0',
'connect_range' => 'Aw-1:0',
'outport_type' => 'concatenate',
'type' => 'output',
'connect_name' => 'snoop_adr_i',
'name' => 'snoop_adr_o'
},
'snoop_en_o' => {
'connect_range' => '',
'connect_type' => 'input',
'range' => '',
'default_out' => 'Active low',
'type' => 'output',
'connect_name' => 'snoop_en_i',
'name' => 'snoop_en_o',
'outport_type' => 'concatenate'
}
},
'module_name' => 'wishbone_bus',
'modules' => {
'wishbone_bus' => {},
'bus_arbiter' => {}
}
}, 'intfc_gen' );
/mpsoc/perl_gui/lib/ip/Bus/wishbone_bus.IP
3,368 → 3,390
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.6.0
## This file is part of ProNoC 1.8.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$wishbone_bus = bless( {
'description' => 'wishbone bus',
'parameters_order' => [
'M',
'S',
'Dw',
'Aw',
'SELw',
'TAGw',
'CTIw',
'BTEw'
],
'ports_order' => [
's_adr_o_all',
's_dat_o_all',
's_sel_o_all',
's_tag_o_all',
's_we_o_all',
's_cyc_o_all',
's_stb_o_all',
's_cti_o_all',
's_bte_o_all',
's_dat_i_all',
's_ack_i_all',
's_err_i_all',
's_rty_i_all',
'm_dat_o_all',
'm_ack_o_all',
'm_err_o_all',
'm_rty_o_all',
'm_adr_i_all',
'm_dat_i_all',
'm_sel_i_all',
'm_tag_i_all',
'm_we_i_all',
'm_stb_i_all',
'm_cyc_i_all',
'm_cti_i_all',
'm_bte_i_all',
'm_grant_addr',
's_sel_one_hot',
'clk',
'reset'
],
'plugs' => {
'clk' => {
'clk' => {},
'0' => {
'name' => 'clk'
},
'type' => 'num',
'value' => 1
},
'reset' => {
'value' => 1,
'0' => {
'name' => 'reset'
},
'reset' => {},
'type' => 'num'
}
},
'unused' => undef,
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/bus/wishbone_bus.v',
'modules' => {
'bus_arbiter' => {},
'wishbone_bus' => {}
},
'ip_name' => 'wishbone_bus',
'category' => 'Bus',
'version' => 0,
'module_name' => 'wishbone_bus',
'sockets' => {
'wb_addr_map' => {
'connection_num' => 'single connection',
'value' => 1,
'type' => 'num',
'wb_addr_map' => {},
'0' => {
'name' => 'wb_addr_map'
}
},
'wb_slave' => {
'connection_num' => 'single connection',
'value' => 'S',
'type' => 'param',
'wb_slave' => {},
'0' => {
'name' => 'wb_slave'
}
},
'wb_master' => {
'connection_num' => 'single connection',
'value' => 'M',
'wb_master' => {},
'type' => 'param',
'0' => {
'name' => 'wb_master'
}
}
},
'parameters' => {
'Aw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '4,128,1',
'info' => 'The wishbone Bus address width',
'type' => 'Spin-button',
'default' => '32'
$ipgen = bless( {
'unused' => undef,
'plugs' => {
'reset' => {
'0' => {
'name' => 'reset'
},
'M' => {
'global_param' => 'Localparam',
'content' => '1,256,1',
'redefine_param' => 1,
'type' => 'Spin-button',
'info' => 'Number of wishbone master interface',
'default' => ' 4'
'reset' => {},
'value' => 1,
'type' => 'num'
},
'clk' => {
'0' => {
'name' => 'clk'
},
'value' => 1,
'clk' => {},
'type' => 'num'
}
},
'ip_name' => 'wishbone_bus',
'ports' => {
'm_rty_o_all' => {
'intfc_port' => 'rty_o',
'type' => 'output',
'intfc_name' => 'socket:wb_master[array]',
'range' => 'M-1 : 0'
},
's_dat_o_all' => {
'range' => 'Dw*S-1 : 0',
'intfc_name' => 'socket:wb_slave[array]',
'type' => 'output',
'intfc_port' => 'dat_o'
},
's_sel_one_hot' => {
'intfc_name' => 'socket:wb_addr_map[0]',
'range' => 'S-1 : 0',
'type' => 'input',
'intfc_port' => 'sel_one_hot'
},
'TAGw' => {
'default' => '3',
'type' => 'Fixed',
'info' => undef,
'redefine_param' => 1,
'content' => '',
'global_param' => 'Localparam'
},
'BTEw' => {
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'info' => undef,
'default' => '2 '
},
'S' => {
'content' => '1,256,1',
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '4',
'info' => 'Number of wishbone slave interface',
'type' => 'Spin-button'
's_rty_i_all' => {
'intfc_port' => 'rty_i',
'type' => 'input',
'range' => 'S-1 : 0',
'intfc_name' => 'socket:wb_slave[array]'
},
's_bte_o_all' => {
'intfc_port' => 'bte_o',
'type' => 'output',
'range' => 'BTEw*S-1 : 0',
'intfc_name' => 'socket:wb_slave[array]'
},
's_err_i_all' => {
'range' => 'S-1 : 0',
'intfc_name' => 'socket:wb_slave[array]',
'type' => 'input',
'intfc_port' => 'err_i'
},
'm_err_o_all' => {
'intfc_name' => 'socket:wb_master[array]',
'range' => 'M-1 : 0',
'intfc_port' => 'err_o',
'type' => 'output'
},
's_tag_o_all' => {
'intfc_port' => 'tag_o',
'type' => 'output',
'range' => 'TAGw*S-1 : 0',
'intfc_name' => 'socket:wb_slave[array]'
},
's_sel_o_all' => {
'type' => 'output',
'intfc_port' => 'sel_o',
'range' => 'SELw*S-1 : 0',
'intfc_name' => 'socket:wb_slave[array]'
},
's_ack_i_all' => {
'intfc_port' => 'ack_i',
'type' => 'input',
'range' => 'S-1 : 0',
'intfc_name' => 'socket:wb_slave[array]'
},
'm_bte_i_all' => {
'intfc_name' => 'socket:wb_master[array]',
'range' => 'BTEw*M-1 : 0',
'intfc_port' => 'bte_i',
'type' => 'input'
},
'm_dat_i_all' => {
'type' => 'input',
'intfc_port' => 'dat_i',
'range' => 'Dw*M-1 : 0',
'intfc_name' => 'socket:wb_master[array]'
},
'm_grant_addr' => {
'intfc_name' => 'socket:wb_addr_map[0]',
'range' => 'Aw-1 : 0',
'type' => 'output',
'intfc_port' => 'grant_addr'
},
'm_adr_i_all' => {
'range' => 'Aw*M-1 : 0',
'intfc_name' => 'socket:wb_master[array]',
'type' => 'input',
'intfc_port' => 'adr_i'
},
's_stb_o_all' => {
'range' => 'S-1 : 0',
'intfc_name' => 'socket:wb_slave[array]',
'intfc_port' => 'stb_o',
'type' => 'output'
},
'm_stb_i_all' => {
'intfc_port' => 'stb_i',
'type' => 'input',
'range' => 'M-1 : 0',
'intfc_name' => 'socket:wb_master[array]'
},
'm_dat_o_all' => {
'type' => 'output',
'intfc_port' => 'dat_o',
'range' => 'Dw*M-1 : 0',
'intfc_name' => 'socket:wb_master[array]'
},
'm_tag_i_all' => {
'intfc_name' => 'socket:wb_master[array]',
'range' => 'TAGw*M-1 : 0',
'intfc_port' => 'tag_i',
'type' => 'input'
},
'reset' => {
'type' => 'input',
'intfc_port' => 'reset_i',
'range' => '',
'intfc_name' => 'plug:reset[0]'
},
'm_sel_i_all' => {
'intfc_name' => 'socket:wb_master[array]',
'range' => 'SELw*M-1 : 0',
'type' => 'input',
'intfc_port' => 'sel_i'
},
'm_cyc_i_all' => {
'intfc_port' => 'cyc_i',
'type' => 'input',
'intfc_name' => 'socket:wb_master[array]',
'range' => 'M-1 : 0'
},
'clk' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'clk_i'
},
'm_ack_o_all' => {
'intfc_port' => 'ack_o',
'type' => 'output',
'intfc_name' => 'socket:wb_master[array]',
'range' => 'M-1 : 0'
},
'm_we_i_all' => {
'intfc_port' => 'we_i',
'type' => 'input',
'intfc_name' => 'socket:wb_master[array]',
'range' => 'M-1 : 0'
},
'snoop_en_o' => {
'type' => 'output',
'intfc_port' => 'snoop_en_o',
'intfc_name' => 'socket:snoop[0]',
'range' => ''
},
'm_cti_i_all' => {
'intfc_port' => 'cti_i',
'type' => 'input',
'intfc_name' => 'socket:wb_master[array]',
'range' => 'CTIw*M-1 : 0'
},
's_we_o_all' => {
'type' => 'output',
'intfc_port' => 'we_o',
'intfc_name' => 'socket:wb_slave[array]',
'range' => 'S-1 : 0'
},
's_cyc_o_all' => {
'intfc_name' => 'socket:wb_slave[array]',
'range' => 'S-1 : 0',
'intfc_port' => 'cyc_o',
'type' => 'output'
},
's_cti_o_all' => {
'intfc_name' => 'socket:wb_slave[array]',
'range' => 'CTIw*S-1 : 0',
'type' => 'output',
'intfc_port' => 'cti_o'
},
's_dat_i_all' => {
'type' => 'input',
'intfc_port' => 'dat_i',
'intfc_name' => 'socket:wb_slave[array]',
'range' => 'Dw*S-1 : 0'
},
'snoop_adr_o' => {
'intfc_name' => 'socket:snoop[0]',
'range' => 'Aw-1 : 0',
'intfc_port' => 'snoop_adr_o',
'type' => 'output'
},
's_adr_o_all' => {
'type' => 'output',
'intfc_port' => 'adr_o',
'range' => 'Aw*S-1 : 0',
'intfc_name' => 'socket:wb_slave[array]'
}
},
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'modules' => {
'wishbone_bus' => {},
'bus_arbiter' => {}
},
'module_name' => 'wishbone_bus',
'version' => 1,
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/bus/wishbone_bus.v',
'parameters' => {
'Aw' => {
'redefine_param' => 1,
'content' => '4,128,1',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'info' => 'The wishbone Bus address width',
'default' => '32'
},
'CTIw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '',
'info' => undef,
'default' => '3'
},
'TAGw' => {
'info' => undef,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '3'
},
'Dw' => {
'default' => '32',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'content' => '8,512,8',
'redefine_param' => 1,
'info' => 'The wishbone Bus data width in bits.'
},
'BTEw' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => '2 '
},
'S' => {
'info' => 'Number of wishbone slave interface',
'redefine_param' => 1,
'content' => '1,256,1',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'default' => '4'
},
'SELw' => {
'default' => 'Dw/8',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '',
'info' => undef
},
'M' => {
'info' => 'Number of wishbone master interface',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'content' => '1,256,1',
'redefine_param' => 1,
'default' => ' 4'
}
},
'description' => 'wishbone bus',
'sockets' => {
'wb_addr_map' => {
'0' => {
'name' => 'wb_addr_map'
},
'value' => 1,
'connection_num' => 'single connection',
'wb_addr_map' => {},
'type' => 'num'
},
'Dw' => {
'content' => '8,512,8',
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '32',
'type' => 'Spin-button',
'info' => 'The wishbone Bus data width in bits.'
'snoop' => {
'0' => {
'name' => 'snoop'
},
'CTIw' => {
'type' => 'Fixed',
'info' => undef,
'default' => '3',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1
},
'SELw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'info' => undef,
'default' => 'Dw/8'
}
},
'hdl_files' => [
'/mpsoc/src_peripheral/bus/wishbone_bus.v',
'/mpsoc/src_noc/main_comp.v',
'/mpsoc/src_noc/arbiter.v'
'value' => 1,
'connection_num' => 'single connection',
'type' => 'num'
},
'wb_master' => {
'type' => 'param',
'connection_num' => 'single connection',
'value' => 'M',
'0' => {
'name' => 'wb_master'
},
'wb_master' => {}
},
'wb_slave' => {
'type' => 'param',
'connection_num' => 'single connection',
'wb_slave' => {},
'value' => 'S',
'0' => {
'name' => 'wb_slave'
}
}
},
'category' => 'Bus',
'hdl_files' => [
'/mpsoc/src_peripheral/bus/wishbone_bus.v',
'/mpsoc/src_noc/main_comp.v',
'/mpsoc/src_noc/arbiter.v'
],
'parameters_order' => [
'M',
'S',
'Dw',
'Aw',
'SELw',
'TAGw',
'CTIw',
'BTEw'
],
'gui_status' => {
'timeout' => 0,
'status' => 'ideal'
},
'ports' => {
's_sel_one_hot' => {
'type' => 'input',
'range' => 'S-1 : 0',
'intfc_name' => 'socket:wb_addr_map[0]',
'intfc_port' => 'sel_one_hot'
},
'reset' => {
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:reset[0]',
'intfc_port' => 'reset_i'
},
'm_cti_i_all' => {
'type' => 'input',
'range' => 'CTIw*M-1 : 0',
'intfc_name' => 'socket:wb_master[array]',
'intfc_port' => 'cti_i'
},
's_dat_i_all' => {
'intfc_name' => 'socket:wb_slave[array]',
'intfc_port' => 'dat_i',
'type' => 'input',
'range' => 'Dw*S-1 : 0'
},
'm_ack_o_all' => {
'intfc_port' => 'ack_o',
'intfc_name' => 'socket:wb_master[array]',
'range' => 'M-1 : 0',
'type' => 'output'
},
's_ack_i_all' => {
'range' => 'S-1 : 0',
'type' => 'input',
'intfc_port' => 'ack_i',
'intfc_name' => 'socket:wb_slave[array]'
},
'clk' => {
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i'
},
's_cyc_o_all' => {
'intfc_port' => 'cyc_o',
'intfc_name' => 'socket:wb_slave[array]',
'range' => 'S-1 : 0',
'type' => 'output'
},
'm_stb_i_all' => {
'type' => 'input',
'range' => 'M-1 : 0',
'intfc_name' => 'socket:wb_master[array]',
'intfc_port' => 'stb_i'
},
'm_dat_i_all' => {
'range' => 'Dw*M-1 : 0',
'type' => 'input',
'intfc_port' => 'dat_i',
'intfc_name' => 'socket:wb_master[array]'
},
's_sel_o_all' => {
'range' => 'SELw*S-1 : 0',
'type' => 'output',
'intfc_port' => 'sel_o',
'intfc_name' => 'socket:wb_slave[array]'
},
's_adr_o_all' => {
'intfc_name' => 'socket:wb_slave[array]',
'intfc_port' => 'adr_o',
'type' => 'output',
'range' => 'Aw*S-1 : 0'
},
'm_sel_i_all' => {
'range' => 'SELw*M-1 : 0',
'type' => 'input',
'intfc_port' => 'sel_i',
'intfc_name' => 'socket:wb_master[array]'
},
'm_adr_i_all' => {
'type' => 'input',
'range' => 'Aw*M-1 : 0',
'intfc_name' => 'socket:wb_master[array]',
'intfc_port' => 'adr_i'
},
's_tag_o_all' => {
'range' => 'TAGw*S-1 : 0',
'type' => 'output',
'intfc_port' => 'tag_o',
'intfc_name' => 'socket:wb_slave[array]'
},
's_cti_o_all' => {
'type' => 'output',
'range' => 'CTIw*S-1 : 0',
'intfc_name' => 'socket:wb_slave[array]',
'intfc_port' => 'cti_o'
},
'm_bte_i_all' => {
'intfc_port' => 'bte_i',
'intfc_name' => 'socket:wb_master[array]',
'range' => 'BTEw*M-1 : 0',
'type' => 'input'
},
'm_dat_o_all' => {
'intfc_name' => 'socket:wb_master[array]',
'intfc_port' => 'dat_o',
'type' => 'output',
'range' => 'Dw*M-1 : 0'
},
's_err_i_all' => {
'type' => 'input',
'range' => 'S-1 : 0',
'intfc_name' => 'socket:wb_slave[array]',
'intfc_port' => 'err_i'
},
's_we_o_all' => {
'range' => 'S-1 : 0',
'type' => 'output',
'intfc_port' => 'we_o',
'intfc_name' => 'socket:wb_slave[array]'
},
'm_tag_i_all' => {
'intfc_name' => 'socket:wb_master[array]',
'intfc_port' => 'tag_i',
'type' => 'input',
'range' => 'TAGw*M-1 : 0'
},
'm_rty_o_all' => {
'intfc_port' => 'rty_o',
'intfc_name' => 'socket:wb_master[array]',
'range' => 'M-1 : 0',
'type' => 'output'
},
'm_cyc_i_all' => {
'intfc_port' => 'cyc_i',
'intfc_name' => 'socket:wb_master[array]',
'range' => 'M-1 : 0',
'type' => 'input'
},
'm_grant_addr' => {
'type' => 'output',
'range' => 'Aw-1 : 0',
'intfc_name' => 'socket:wb_addr_map[0]',
'intfc_port' => 'grant_addr'
},
's_stb_o_all' => {
'type' => 'output',
'range' => 'S-1 : 0',
'intfc_name' => 'socket:wb_slave[array]',
'intfc_port' => 'stb_o'
},
's_rty_i_all' => {
'type' => 'input',
'range' => 'S-1 : 0',
'intfc_name' => 'socket:wb_slave[array]',
'intfc_port' => 'rty_i'
},
'm_we_i_all' => {
'intfc_name' => 'socket:wb_master[array]',
'intfc_port' => 'we_i',
'type' => 'input',
'range' => 'M-1 : 0'
},
'm_err_o_all' => {
'intfc_name' => 'socket:wb_master[array]',
'intfc_port' => 'err_o',
'type' => 'output',
'range' => 'M-1 : 0'
},
's_bte_o_all' => {
'intfc_name' => 'socket:wb_slave[array]',
'intfc_port' => 'bte_o',
'type' => 'output',
'range' => 'BTEw*S-1 : 0'
},
's_dat_o_all' => {
'range' => 'Dw*S-1 : 0',
'type' => 'output',
'intfc_port' => 'dat_o',
'intfc_name' => 'socket:wb_slave[array]'
}
}
}, 'ip_gen' );
'ports_order' => [
's_adr_o_all',
's_dat_o_all',
's_sel_o_all',
's_tag_o_all',
's_we_o_all',
's_cyc_o_all',
's_stb_o_all',
's_cti_o_all',
's_bte_o_all',
's_dat_i_all',
's_ack_i_all',
's_err_i_all',
's_rty_i_all',
'm_dat_o_all',
'm_ack_o_all',
'm_err_o_all',
'm_rty_o_all',
'm_adr_i_all',
'm_dat_i_all',
'm_sel_i_all',
'm_tag_i_all',
'm_we_i_all',
'm_stb_i_all',
'm_cyc_i_all',
'm_cti_i_all',
'm_bte_i_all',
'm_grant_addr',
's_sel_one_hot',
'snoop_adr_o',
'snoop_en_o',
'clk',
'reset'
]
}, 'ip_gen' );
/mpsoc/perl_gui/lib/ip/NoC/ni_master.IP
3,7 → 3,7
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.8.0
## This file is part of ProNoC 1.8.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
10,54 → 10,223
################################################################################
 
$ipgen = bless( {
'description' => '',
'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/ni/ni_master.v',
'plugs' => {
'wb_master' => {
'value' => 2,
'1' => {
'name' => 'wb_receive'
},
'wb_master' => {},
'0' => {
'name' => 'wb_send'
},
'type' => 'num'
'ports' => {
's_cti_i' => {
'type' => 'input',
'intfc_port' => 'cti_i',
'range' => 'TAGw-1 : 0',
'intfc_name' => 'plug:wb_slave[0]'
},
'm_send_sel_o' => {
'intfc_port' => 'sel_o',
'type' => 'output',
'range' => 'SELw-1 : 0',
'intfc_name' => 'plug:wb_master[0]'
},
'm_receive_cyc_o' => {
'intfc_port' => 'cyc_o',
'type' => 'output',
'range' => '',
'intfc_name' => 'plug:wb_master[1]'
},
'm_send_ack_i' => {
'intfc_port' => 'ack_i',
'type' => 'input',
'intfc_name' => 'plug:wb_master[0]',
'range' => ''
},
'flit_out_wr' => {
'range' => '',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out_wr',
'type' => 'output'
},
'm_send_stb_o' => {
'intfc_port' => 'stb_o',
'type' => 'output',
'range' => '',
'intfc_name' => 'plug:wb_master[0]'
},
'm_receive_addr_o' => {
'range' => 'M_Aw-1 : 0',
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'adr_o',
'type' => 'output'
},
'flit_in' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'Fw-1 : 0',
'intfc_port' => 'flit_in',
'type' => 'input'
},
'reset' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'intfc_port' => 'reset_i',
'type' => 'input'
},
's_dat_o' => {
'type' => 'output',
'intfc_port' => 'dat_o',
'range' => 'Dw-1 : 0',
'intfc_name' => 'plug:wb_slave[0]'
},
's_stb_i' => {
'intfc_port' => 'stb_i',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]',
'range' => ''
},
'current_x' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'Xw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_x'
},
'interrupt_peripheral' => {
'value' => 1,
'interrupt_peripheral' => {},
'type' => 'num',
'0' => {
'name' => 'interrupt'
}
},
'wb_slave' => {
'wb_slave' => {},
'value' => 1,
'0' => {
'name' => 'wb_slave',
'width' => 10,
'addr' => '0xb800_0000 0xbfff_ffff custom devices'
},
'type' => 'num'
'm_receive_cti_o' => {
'type' => 'output',
'intfc_port' => 'cti_o',
'range' => 'TAGw-1 : 0',
'intfc_name' => 'plug:wb_master[1]'
},
's_we_i' => {
'intfc_port' => 'we_i',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]',
'range' => ''
},
'm_receive_we_o' => {
'type' => 'output',
'intfc_port' => 'we_o',
'range' => '',
'intfc_name' => 'plug:wb_master[1]'
},
'm_send_dat_i' => {
'type' => 'input',
'intfc_port' => 'dat_i',
'range' => 'Dw-1 : 0',
'intfc_name' => 'plug:wb_master[0]'
},
'flit_in_wr' => {
'type' => 'input',
'intfc_port' => 'flit_in_wr',
'range' => '',
'intfc_name' => 'socket:ni[0]'
},
's_sel_i' => {
'range' => 'SELw-1 : 0',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input',
'intfc_port' => 'sel_i'
},
'm_send_we_o' => {
'intfc_name' => 'plug:wb_master[0]',
'range' => '',
'type' => 'output',
'intfc_port' => 'we_o'
},
'flit_out' => {
'intfc_port' => 'flit_out',
'type' => 'output',
'intfc_name' => 'socket:ni[0]',
'range' => 'Fw-1 : 0'
},
'm_send_cti_o' => {
'range' => 'TAGw-1 : 0',
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'cti_o',
'type' => 'output'
},
'm_receive_stb_o' => {
'type' => 'output',
'intfc_port' => 'stb_o',
'range' => '',
'intfc_name' => 'plug:wb_master[1]'
},
'm_send_cyc_o' => {
'type' => 'output',
'intfc_port' => 'cyc_o',
'range' => '',
'intfc_name' => 'plug:wb_master[0]'
},
's_cyc_i' => {
'intfc_port' => 'cyc_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:wb_slave[0]'
},
'm_send_addr_o' => {
'range' => 'M_Aw-1 : 0',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output',
'intfc_port' => 'adr_o'
},
'm_receive_dat_o' => {
'intfc_name' => 'plug:wb_master[1]',
'range' => 'Dw-1 : 0',
'type' => 'output',
'intfc_port' => 'dat_o'
},
's_dat_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'Dw-1 : 0',
'type' => 'input',
'intfc_port' => 'dat_i'
},
'm_receive_sel_o' => {
'intfc_port' => 'sel_o',
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]',
'range' => 'SELw-1 : 0'
},
'clk' => {
'value' => 1,
'0' => {
'name' => 'clk'
},
'type' => 'num',
'clk' => {}
'intfc_port' => 'clk_i',
'type' => 'input',
'intfc_name' => 'plug:clk[0]',
'range' => ''
},
'reset' => {
'type' => 'num',
'0' => {
'name' => 'reset'
},
'reset' => {},
'value' => 1
}
'current_y' => {
'type' => 'input',
'intfc_port' => 'current_y',
'range' => 'Yw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'm_receive_ack_i' => {
'range' => '',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'input',
'intfc_port' => 'ack_i'
},
's_addr_i' => {
'intfc_port' => 'adr_i',
'type' => 'input',
'range' => 'S_Aw-1 : 0',
'intfc_name' => 'plug:wb_slave[0]'
},
'credit_out' => {
'range' => 'V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_out',
'type' => 'output'
},
's_ack_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'output',
'intfc_port' => 'ack_o'
},
'irq' => {
'type' => 'output',
'intfc_port' => 'int_o',
'range' => '',
'intfc_name' => 'plug:interrupt_peripheral[0]'
},
'credit_in' => {
'type' => 'input',
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'V-1 : 0'
}
},
'ports_order' => [
'reset',
97,6 → 266,18
'm_receive_ack_i',
'irq'
],
'sockets' => {
'ni' => {
'0' => {
'name' => 'ni'
},
'value' => 1,
'ni' => {},
'type' => 'num',
'connection_num' => 'single connection'
}
},
'module_name' => 'ni_master',
'hdl_files' => [
'/mpsoc/src_noc/arbiter.v',
'/mpsoc/src_noc/flit_buffer.v',
110,446 → 291,313
'/mpsoc/src_peripheral/ni/ni_master.v',
'/mpsoc/src_peripheral/ni/ni_crc32.v'
],
'unused' => {
'plug:wb_slave[0]' => [
'err_o',
'rty_o',
'tag_i',
'bte_i'
],
'plug:wb_master[1]' => [
'tag_o',
'rty_i',
'bte_o',
'err_i',
'dat_i'
],
'plug:wb_master[0]' => [
'tag_o',
'rty_i',
'dat_o',
'bte_o',
'err_i'
]
},
'description_pdf' => '/mpsoc/src_peripheral/ni/NI.pdf',
'parameters' => {
'C' => {
'content' => '',
'info' => 'Parameter',
'default' => ' 4',
'global_param' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1
},
'Dw' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'default' => '32',
'info' => 'wishbone_bus data width in bits.',
'content' => '32,256,8',
'redefine_param' => 1
},
'SRC_ADR_HDR_WIDTH' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'default' => '8',
'info' => 'Parameter',
'redefine_param' => 1
},
'SELw' => {
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => 'Parameter',
'default' => '4',
'content' => ''
},
'DEBUG_EN' => {
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => ' 1',
'info' => 'Parameter',
'content' => ''
},
'NY' => {
'content' => '',
'info' => 'Parameter',
'default' => ' 4',
'global_param' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1
},
'TOPOLOGY' => {
'default' => '"MESH"',
'redefine_param' => 1,
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => ''
'redefine_param' => 1
},
'MAX_BURST_SIZE' => {
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'type' => 'Combo-box',
'info' => 'Maximum burst size in words.
The NI release wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all desired data is transferred. ',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '16'
},
'ROUTING_HDR_WIDTH' => {
'content' => '',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '8'
},
'CLASS_HDR_WIDTH' => {
'redefine_param' => 1,
'default' => '8',
'content' => '',
'type' => 'Fixed',
'info' => 'Parameter',
'global_param' => 'Localparam'
},
'Fpay' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => ' 32',
'content' => '',
'redefine_param' => 1
},
'S_Aw' => {
'content' => '',
'default' => '8',
'info' => 'Parameter',
'global_param' => 'Localparam',
'info' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'default' => '8'
'redefine_param' => 1
},
'ROUTE_TYPE' => {
'redefine_param' => 1,
'default' => ' ',
'content' => '',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'CLASS_HDR_WIDTH' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'default' => '8',
'info' => 'Parameter'
},
'DST_ADR_HDR_WIDTH' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '8',
'info' => 'Parameter',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '8'
'content' => ''
},
'NX' => {
'default' => ' 4',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'global_param' => 'Parameter',
'content' => ''
'default' => ' 4',
'content' => '',
'redefine_param' => 1
},
'SRC_ADR_HDR_WIDTH' => {
'default' => '8',
'redefine_param' => 1,
'type' => 'Fixed',
'info' => 'Parameter',
'global_param' => 'Localparam',
'content' => ''
},
'ROUTE_NAME' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '"XY" ',
'content' => '',
'default' => '"XY" ',
'redefine_param' => 1
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'Xw' => {
'redefine_param' => 0,
'default' => 'log2(NX)',
'MAX_BURST_SIZE' => {
'type' => 'Combo-box',
'global_param' => 'Localparam',
'default' => '16',
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'redefine_param' => 1
},
'M_Aw' => {
'default' => '32',
'info' => 'Parameter',
'content' => 'Dw',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'Fw' => {
'content' => '',
'default' => '2+V+Fpay',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed',
'global_param' => 'Localparam'
'redefine_param' => 0
},
'TAGw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'info' => 'Parameter',
'global_param' => 'Localparam',
'content' => '',
'default' => '3',
'redefine_param' => 1
},
'DEBUG_EN' => {
'content' => '',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'default' => ' 1'
},
'B' => {
'redefine_param' => 1,
'default' => ' 4',
'content' => '',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'Dw' => {
'redefine_param' => 1,
'default' => '32',
'content' => '32,256,8',
'info' => 'wishbone_bus data width in bits.',
'ROUTING_HDR_WIDTH' => {
'redefine_param' => 1,
'default' => '8',
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'Xw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'type' => 'Spin-button'
'info' => undef,
'default' => 'log2(NX)',
'content' => '',
'redefine_param' => 0
},
'Fpay' => {
'default' => ' 32',
'redefine_param' => 1,
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => ''
},
'NY' => {
'redefine_param' => 1,
'default' => ' 4',
'CRC_EN' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Combo-box',
'content' => '"YES","NO"',
'default' => '"NO"',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. '
},
'Yw' => {
'redefine_param' => 0,
'content' => '',
'global_param' => 'Parameter',
'info' => 'Parameter',
'info' => undef,
'default' => 'log2(NY)',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'P' => {
'V' => {
'content' => '',
'default' => '4',
'info' => 'Parameter',
'global_param' => 'Parameter',
'info' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'default' => '5',
'redefine_param' => 1
},
'SELw' => {
'redefine_param' => 1,
'default' => '4',
'content' => '',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'V' => {
'redefine_param' => 1,
'default' => '4',
'B' => {
'content' => '',
'info' => 'Parameter',
'default' => ' 4',
'global_param' => 'Parameter',
'type' => 'Fixed'
'type' => 'Fixed',
'redefine_param' => 1
},
'CRC_EN' => {
'type' => 'Combo-box',
'global_param' => 'Localparam',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'content' => '"YES","NO"',
'default' => '"NO"',
'redefine_param' => 1
},
'Yw' => {
'default' => 'log2(NY)',
'redefine_param' => 0,
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'content' => ''
},
'M_Aw' => {
'redefine_param' => 1,
'default' => '32',
'content' => 'Dw',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'Fw' => {
'type' => 'Fixed',
'info' => undef,
'global_param' => 'Localparam',
'content' => '',
'default' => '2+V+Fpay',
'redefine_param' => 0
},
'MAX_TRANSACTION_WIDTH' => {
'content' => '4,32,1',
'default' => '13',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
'content' => '4,32,1',
'default' => '13',
'redefine_param' => 1
},
'C' => {
'default' => ' 4',
'redefine_param' => 1,
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => ''
}
}
},
'ports' => {
's_dat_o' => {
'intfc_port' => 'dat_o',
'range' => 'Dw-1 : 0',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'output'
},
's_stb_i' => {
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'intfc_port' => 'stb_i'
},
'm_receive_sel_o' => {
'range' => 'SELw-1 : 0',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output',
'intfc_port' => 'sel_o'
},
'm_receive_ack_i' => {
'intfc_port' => 'ack_i',
'range' => '',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'input'
},
's_cyc_i' => {
'intfc_port' => 'cyc_i',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]',
'range' => ''
},
'm_send_addr_o' => {
'intfc_port' => 'adr_o',
'range' => 'M_Aw-1 : 0',
'type' => 'output',
'intfc_name' => 'plug:wb_master[0]'
},
'm_send_we_o' => {
'range' => '',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output',
'intfc_port' => 'we_o'
},
'current_x' => {
'intfc_port' => 'current_x',
'range' => 'Xw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input'
},
'modules' => {
'vc_wb_slave_registers' => {},
'ovc_status' => {},
'header_flit_generator' => {},
'ni_master' => {},
'ni_vc_dma' => {}
},
'category' => 'NoC',
'parameters_order' => [
'CLASS_HDR_WIDTH',
'ROUTING_HDR_WIDTH',
'DST_ADR_HDR_WIDTH',
'SRC_ADR_HDR_WIDTH',
'TOPOLOGY',
'ROUTE_NAME',
'NX',
'NY',
'C',
'V',
'B',
'Fpay',
'MAX_TRANSACTION_WIDTH',
'MAX_BURST_SIZE',
'DEBUG_EN',
'Dw',
'S_Aw',
'M_Aw',
'TAGw',
'SELw',
'Xw',
'Yw',
'Fw',
'CRC_EN'
],
'plugs' => {
'clk' => {
'type' => 'input',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'intfc_port' => 'clk_i'
'0' => {
'name' => 'clk'
},
'clk' => {},
'type' => 'num',
'value' => 1
},
'm_receive_addr_o' => {
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]',
'range' => 'M_Aw-1 : 0',
'intfc_port' => 'adr_o'
},
's_dat_i' => {
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'Dw-1 : 0',
'intfc_port' => 'dat_i'
},
'm_receive_dat_o' => {
'intfc_port' => 'dat_o',
'range' => 'Dw-1 : 0',
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]'
},
's_sel_i' => {
'intfc_port' => 'sel_i',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'SELw-1 : 0'
},
's_ack_o' => {
'intfc_port' => 'ack_o',
'range' => '',
'type' => 'output',
'intfc_name' => 'plug:wb_slave[0]'
},
'm_receive_stb_o' => {
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]',
'range' => '',
'intfc_port' => 'stb_o'
},
'flit_out_wr' => {
'intfc_name' => 'socket:ni[0]',
'type' => 'output',
'range' => '',
'intfc_port' => 'flit_out_wr'
},
'current_y' => {
'intfc_port' => 'current_y',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'range' => 'Yw-1 : 0'
},
'm_send_cti_o' => {
'range' => 'TAGw-1 : 0',
'type' => 'output',
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'cti_o'
},
'm_receive_we_o' => {
'range' => '',
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'we_o'
'reset' => {
'0' => {
'name' => 'reset'
},
'flit_in' => {
'range' => 'Fw-1 : 0',
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in'
},
'flit_out' => {
'range' => 'Fw-1 : 0',
'type' => 'output',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out'
'type' => 'num',
'reset' => {},
'value' => 1
},
'wb_slave' => {
'wb_slave' => {},
'type' => 'num',
'value' => 1,
'0' => {
'name' => 'wb_slave',
'width' => 10,
'addr' => '0xb800_0000 0xbfff_ffff custom devices'
}
},
's_addr_i' => {
'intfc_port' => 'adr_i',
'range' => 'S_Aw-1 : 0',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input'
},
'm_send_stb_o' => {
'type' => 'output',
'intfc_name' => 'plug:wb_master[0]',
'range' => '',
'intfc_port' => 'stb_o'
},
's_we_i' => {
'intfc_port' => 'we_i',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input',
'range' => ''
},
'm_receive_cti_o' => {
'intfc_port' => 'cti_o',
'range' => 'TAGw-1 : 0',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output'
},
's_cti_i' => {
'intfc_port' => 'cti_i',
'range' => 'TAGw-1 : 0',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input'
},
'm_send_cyc_o' => {
'type' => 'output',
'intfc_name' => 'plug:wb_master[0]',
'range' => '',
'intfc_port' => 'cyc_o'
},
'm_send_sel_o' => {
'intfc_port' => 'sel_o',
'range' => 'SELw-1 : 0',
'type' => 'output',
'intfc_name' => 'plug:wb_master[0]'
},
'reset' => {
'range' => '',
'type' => 'input',
'intfc_name' => 'plug:reset[0]',
'intfc_port' => 'reset_i'
},
'credit_in' => {
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'V-1 : 0',
'intfc_port' => 'credit_in'
},
'm_send_dat_i' => {
'intfc_port' => 'dat_i',
'type' => 'input',
'intfc_name' => 'plug:wb_master[0]',
'range' => 'Dw-1 : 0'
},
'credit_out' => {
'range' => 'V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'output',
'intfc_port' => 'credit_out'
},
'm_receive_cyc_o' => {
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output',
'range' => '',
'intfc_port' => 'cyc_o'
},
'm_send_ack_i' => {
'intfc_port' => 'ack_i',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'input',
'range' => ''
},
'irq' => {
'range' => '',
'type' => 'output',
'intfc_name' => 'plug:interrupt_peripheral[0]',
'intfc_port' => 'int_o'
},
'flit_in_wr' => {
'range' => '',
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in_wr'
}
'interrupt_peripheral' => {
'value' => 1,
'type' => 'num',
'0' => {
'name' => 'interrupt'
},
'interrupt_peripheral' => {}
},
'wb_master' => {
'0' => {
'name' => 'wb_send'
},
'wb_master' => {},
'type' => 'num',
'value' => 2,
'1' => {
'name' => 'wb_receive'
}
}
},
'description_pdf' => '/mpsoc/src_peripheral/ni/NI.pdf',
'category' => 'NoC',
'gui_status' => {
'timeout' => 0,
'status' => 'ideal'
},
'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/ni/ni_master.v',
'version' => 40,
'ip_name' => 'ni_master',
'system_h' => ' /* NI wb registers addresses
0 : STATUS1_WB_ADDR // status1: {send_enable_binarry,receive_enable_binarry,send_vc_is_busy,receive_vc_is_busy,receive_vc_got_packet}
1 : STATUS2_WB_ADDR // status2:
0 : STATUS1_WB_ADDR // status1: {send_vc_is_busy,receive_vc_is_busy,receive_vc_packet_is_saved,receive_vc_got_packet};
1 : STATUS2_WB_ADDR // status2: {send_enable_binary,receive_enable_binary,vc_got_error,any_error_isr,got_pck_isr, save_done_isr,send_done_isr,any_error_int_en,got_pck_int_en, save_done_int_en,send_done_int_en};
2 : BURST_SIZE_WB_ADDR // The busrt size in words
3 : SEND_DATA_SIZE_WB_ADDR, // The size of data to be sent in byte
562,11 → 610,18
9 : RECEIVE_SRC_WB_ADDR // The source router (the router which is sent this packet).
10 : RECEIVE_CTRL_WB_ADDR // The NI reciever control register
11 : RECEIVE_MAX_BUFF_SIZ // The receiver\'s allocated buffer size in words. If the packet size is bigger tha the buffer size the rest of will be discarred
12 : ERROR_FLAGS // errors: {crc_miss_match,burst_size_error,send_data_size_error,rcive_buff_ovrflw_err};
*/
#define CORID ${CORE_ID}
#define MAX_X_ADDR ${NX}
#define MAX_Y_ADDR ${NY}
 
#define Y_ADDR (CORID / MAX_X_ADDR)
#define X_ADDR (CORID % MAX_X_ADDR)
 
 
 
#define ${IP}_STATUS1_REG (*((volatile unsigned int *) ($BASE))) //0
#define ${IP}_STATUS2_REG (*((volatile unsigned int *) ($BASE+4))) //1
#define ${IP}_BURST_SIZE_REG (*((volatile unsigned int *) ($BASE+8))) //2
581,14 → 636,15
 
#define ${IP}_RECEIVE_DATA_SIZE_REG(v) (*((volatile unsigned int *) ($BASE+28+(v<<6)))) //7
#define ${IP}_RECEIVE_STRT_ADDR_REG(v) (*((volatile unsigned int *) ($BASE+32+(v<<6)))) //8
#define ${IP}_RECEIVE_CTRL_REG(v) (*((volatile unsigned int *) ($BASE+36+(v<<6)))) //9
#define ${IP}_RECEIVE_MAX_BUFF_SIZ_REG(v) (*((volatile unsigned int *) ($BASE+40+(v<<6)))) //10
#define ${IP}_RECEIVE_CRC_MATCH_REG(v) (*((volatile unsigned int *) ($BASE+44+(v<<6)))) //11
#define ${IP}_RECEIVE_SRC_REG(v) (*((volatile unsigned int *) ($BASE+36+(v<<6)))) //9
#define ${IP}_RECEIVE_CTRL_REG(v) (*((volatile unsigned int *) ($BASE+40+(v<<6)))) //10
#define ${IP}_RECEIVE_MAX_BUFF_SIZ_REG(v) (*((volatile unsigned int *) ($BASE+44+(v<<6)))) //11
#define ${IP}_ERROR_FLAGS_REG(v) (*((volatile unsigned int *) ($BASE+48+(v<<6)))) //12
 
 
 
// assign status1= {send_vc_is_busy,receive_vc_is_busy,receive_vc_packet_is_saved,receive_vc_got_packet};
// assign status2= {send_enable_binarry,receive_enable_binarry,crc_miss_match,got_pck_isr, save_done_isr,send_done_isr,got_pck_int_en, save_done_int_en,send_done_int_en};
// assign status2= {send_enable_binary,receive_enable_binary,vc_got_error,any_error_isr,got_pck_isr, save_done_isr,send_done_isr,any_error_int_en,got_pck_int_en, save_done_int_en,send_done_int_en};
 
#define ${IP}_got_packet(v) ((${IP}_STATUS1_REG >> (v)) & 0x1)
595,14 → 651,76
#define ${IP}_packet_is_saved(v) ((${IP}_STATUS1_REG >> (${V}+v)) & 0x1)
#define ${IP}_receive_is_busy(v) ((${IP}_STATUS1_REG >> (2*${V}+v)) & 0x1)
#define ${IP}_send_is_busy(v) ((${IP}_STATUS1_REG >> (3*${V}+v)) & 0x1)
#define ${IP}_got_any_error(v) ((${IP}_STATUS2_REG >> (8+v)) & 0x1)
 
#define SEND_DONE_INT_EN (1<<0)
#define SAVE_DONE_INT_EN (1<<1)
#define GOT_PCK_INT_EN (1<<2)
#define ERRORS_INT_EN (1<<3)
#define ALL_INT_EN (SEND_DONE_INT_EN | SAVE_DONE_INT_EN | GOT_PCK_INT_EN | ERRORS_INT_EN)
 
#define SEND_DONE_ISR (1<<4)
#define SAVE_DONE_ISR (1<<5)
#define GOT_PCK_ISR (1<<6)
#define ERRORS_ISR (1<<7)
 
void ${IP}_initial (unsigned int burst_size) {
${IP}_BURST_SIZE_REG = burst_size;
 
 
//errors = {crc_miss_match,illegal_send_req,burst_size_error,send_data_size_error,rcive_buff_ovrflw_err};
#define BUFF_OVER_FLOW_ERR (1<<0) // This error happens when the receiver allocated buffer size is smaller than the received packet size
#define SEND_DATA_SIZE_ERR (1<<1) // This error happens when the send data size is not set
#define BURST_SIZE_ERR (1<<2) // This error happens when the burst size is not set
#define ILLEGAL_SEND_REQ (1<<3) // This error happens when a new send request is received while the DMA is still busy sending previous packet
#define CRC_MISS_MATCH (1<<4) // This error happens when the received packet CRC miss match
 
//ack intrrupts functions
#define ${IP}_ack_send_done_isr() (${IP}_STATUS2_REG &= (ALL_INT_EN |SEND_DONE_ISR))
#define ${IP}_ack_save_done_isr() (${IP}_STATUS2_REG &= (ALL_INT_EN | SAVE_DONE_ISR))
#define ${IP}_ack_got_pck_isr() (${IP}_STATUS2_REG &= (ALL_INT_EN | GOT_PCK_ISR))
#define ${IP}_ack_errors_isr() (${IP}_STATUS2_REG &= (ALL_INT_EN | ERRORS_ISR))
 
#define ${IP}_ack_all_isr() (${IP}_STATUS2_REG = ${IP}_STATUS2_REG)
 
 
struct SRC_INFOS{
unsigned char r; // reserved
unsigned char c; // message class
unsigned char y; //y address
unsigned char x ; //x address
} ;
 
inline struct SRC_INFOS get_src_info(unsigned char v){
struct SRC_INFOS src_info =*(struct SRC_INFOS *) (&ni_RECEIVE_SRC_REG(v));
return src_info;
}
 
/*
The NI initializing function.
The burst_size must be <= $MAX_BURST_SIZE
send_int_en :1: enable the intrrupt when a packet is sent 0 : This intrrupt is disabled
save_int_en : 1: enable the intrrupt when a recived packet is saved on internal buffer 0 : This intrrupt is disabled
got_pck_int_en : 1: enable the intrrupt when a packet is recived in NI. 0 : This intrrupt is disabled
 
*/
void ${IP}_initial (unsigned int burst_size, unsigned char errors_int_en, unsigned char send_int_en, unsigned char save_int_en, unsigned char got_pck_int_en) {
${IP}_BURST_SIZE_REG = burst_size;
if(errors_int_en) ${IP}_STATUS2_REG |= ERRORS_INT_EN;
if(send_int_en) ${IP}_STATUS2_REG |= SEND_DONE_INT_EN;
if(save_int_en) ${IP}_STATUS2_REG |= SAVE_DONE_INT_EN;
if(got_pck_int_en) ${IP}_STATUS2_REG |= GOT_PCK_INT_EN;
}
 
/*
The NI message sent function:
v: virtual channel number which this packet should be sent to
class_num: message class number. Diffrent message classes can be sent via isolated network resources to avoid protocol deadlock
data_start_addr : The address pointer to the start location of the packet to be sent in the memory
data_size: the message data size in words
dest_x: the x address of destination core
dest_y: the y address of destination core
 
*/
 
void ${IP}_transfer (unsigned int v, unsigned int class_num, unsigned int data_start_addr, unsigned int data_size, unsigned int dest_x,unsigned int dest_y){
while (${IP}_send_is_busy(v)); // wait until VC is busy sending previous packet
 
612,6 → 730,13
}
 
/*
The NI message receiver function:
v: virtual channel number of the received packet
data_start_addr : The address pointer to the start location of the memory where the newly arrived packet must be stored by NI in.
max_buffer_size : The allocated receive-memory buffer size in words.
*/
 
void ${IP}_receive (unsigned int v, unsigned int data_start_addr, unsigned int max_buffer_size){
while (${IP}_receive_is_busy(v)); // wait until VC is busy saving previous packet
 
621,73 → 746,9
 
}',
'modules' => {
'header_flit_generator' => {},
'vc_wb_slave_registers' => {},
'ni_vc_dma' => {},
'ovc_status' => {},
'ni_master' => {}
},
'version' => 38,
'parameters_order' => [
'CLASS_HDR_WIDTH',
'ROUTING_HDR_WIDTH',
'DST_ADR_HDR_WIDTH',
'SRC_ADR_HDR_WIDTH',
'TOPOLOGY',
'ROUTE_NAME',
'NX',
'NY',
'C',
'V',
'B',
'Fpay',
'MAX_TRANSACTION_WIDTH',
'MAX_BURST_SIZE',
'DEBUG_EN',
'Dw',
'S_Aw',
'M_Aw',
'TAGw',
'SELw',
'Xw',
'Yw',
'Fw',
'CRC_EN'
],
'unused' => {
'plug:wb_master[0]' => [
'dat_o',
'err_i',
'bte_o',
'rty_i',
'tag_o'
],
'plug:wb_slave[0]' => [
'rty_o',
'bte_i',
'err_o',
'tag_i'
],
'plug:wb_master[1]' => [
'err_i',
'bte_o',
'rty_i',
'dat_i',
'tag_o'
]
},
'sockets' => {
'ni' => {
'value' => 1,
'ni' => {},
'type' => 'num',
'connection_num' => 'single connection',
'0' => {
'name' => 'ni'
}
}
},
'module_name' => 'ni_master',
'ip_name' => 'ni_master'
'description' => '',
'gui_status' => {
'timeout' => 0,
'status' => 'ideal'
}
}, 'ip_gen' );
/mpsoc/perl_gui/lib/ip/NoC/ni_slave.IP
3,7 → 3,7
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.8.0
## This file is part of ProNoC 1.8.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
10,318 → 10,257
################################################################################
 
$ipgen = bless( {
'category' => 'NoC',
'plugs' => {
'wb_slave' => {
'0' => {
'width' => 10,
'addr' => '0xb800_0000 0xbfff_ffff custom devices',
'name' => 'wb_ctrl'
},
'type' => 'num',
'1' => {
'width' => 'IN_MEM_BYTEw',
'addr' => '0xb800_0000 0xbfff_ffff custom devices',
'name' => 'wb_in'
},
'wb_slave' => {},
'value' => 3,
'2' => {
'name' => 'wb_out',
'addr' => '0xb800_0000 0xbfff_ffff custom devices',
'width' => 'OUT_MEM_BYTEw'
}
},
'reset' => {
'reset' => {},
'type' => 'num',
'0' => {
'name' => 'reset'
},
'value' => 1
},
'interrupt_peripheral' => {
'0' => {
'name' => 'interrupt'
},
'type' => 'num',
'interrupt_peripheral' => {},
'value' => 1
'modules' => {
'ni_slave' => {}
},
'parameters' => {
'DST_ADR_HDR_WIDTH' => {
'type' => 'Fixed',
'content' => '',
'default' => '8',
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => 'Parameter'
},
'Fw' => {
'content' => '',
'default' => '2+V+Fpay',
'global_param' => 'Localparam',
'redefine_param' => 0,
'info' => undef,
'type' => 'Fixed'
},
'ROUTING_HDR_WIDTH' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '8',
'content' => '',
'type' => 'Fixed'
},
'Xw' => {
'info' => undef,
'redefine_param' => 0,
'global_param' => 'Localparam',
'default' => 'log2(NX)',
'content' => '',
'type' => 'Fixed'
},
'S_Aw' => {
'content' => '',
'default' => '8',
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'TOPOLOGY' => {
'default' => '"MESH"',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'info' => 'Parameter',
'type' => 'Fixed'
},
'B' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => ' 4',
'content' => ''
},
'Yw' => {
'type' => 'Fixed',
'content' => '',
'default' => 'log2(NY)',
'global_param' => 'Localparam',
'redefine_param' => 0,
'info' => undef
},
'DEBUG_EN' => {
'type' => 'Fixed',
'content' => '',
'default' => ' 1',
'info' => 'Parameter',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'MAX_TRANSACTION_WIDTH' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
'content' => '4,32,1',
'default' => '13'
},
'ROUTE_NAME' => {
'type' => 'Fixed',
'info' => 'Parameter',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => '',
'default' => '"XY" '
},
'Fpay' => {
'default' => ' 32',
'content' => '',
'info' => 'Parameter',
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed'
},
'CLASS_HDR_WIDTH' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => 'Parameter',
'content' => '',
'default' => '8',
'type' => 'Fixed'
},
'clk' => {
'0' => {
'name' => 'clk'
'OUT_MEM_BYTEw' => {
'type' => 'Fixed',
'content' => '',
'default' => 'OUTPUT_MEM_Aw+(Dw/8)',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Don\'t include'
},
'WEIGHTw' => {
'type' => 'Fixed',
'content' => '',
'default' => '4',
'info' => undef,
'global_param' => 'Parameter',
'redefine_param' => 1
},
'type' => 'num',
'clk' => {},
'value' => 1
}
},
'parameters_order' => [
'INPUT_MEM_Aw',
'OUTPUT_MEM_Aw',
'MAX_TRANSACTION_WIDTH',
'MAX_BURST_SIZE',
'DEBUG_EN',
'CLASS_HDR_WIDTH',
'ROUTING_HDR_WIDTH',
'DST_ADR_HDR_WIDTH',
'SRC_ADR_HDR_WIDTH',
'TOPOLOGY',
'ROUTE_NAME',
'NX',
'NY',
'C',
'V',
'B',
'Fpay',
'CRC_EN',
'SWA_ARBITER_TYPE',
'WEIGHTw',
'Dw',
'S_Aw',
'M_Aw',
'TAGw',
'SELw',
'IN_MEM_BYTEw',
'OUT_MEM_BYTEw'
],
'description_pdf' => '/mpsoc/src_peripheral/ni/NI.pdf',
'ports' => {
'ctrl_cti_i' => {
'range' => 'TAGw-1 : 0',
'intfc_port' => 'cti_i',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]'
},
'ctrl_dat_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'output',
'intfc_port' => 'dat_o',
'range' => 'Dw-1 : 0'
},
'ctrl_addr_i' => {
'intfc_port' => 'adr_i',
'range' => 'S_Aw-1 : 0',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]'
},
'current_x' => {
'type' => 'input',
'intfc_port' => 'current_x',
'range' => 'Xw-1 : 0',
'intfc_name' => 'socket:ni[0]'
'MAX_BURST_SIZE' => {
'type' => 'Combo-box',
'info' => 'Maximum burst size in words.
The NI release wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all desired data is transferred. ',
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '16',
'content' => '2,4,8,16,32,64,128,256,512,1024,2048'
},
'SELw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => 'Parameter',
'default' => '4',
'content' => '',
'type' => 'Fixed'
},
'out_cyc_i' => {
'intfc_port' => 'cyc_i',
'range' => '',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[2]'
'INPUT_MEM_Aw' => {
'type' => 'Spin-button',
'content' => '4,32,1',
'default' => ' 10',
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'Dw' => {
'default' => '32',
'content' => '32,256,8',
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => 'wishbone_bus data width in bits.',
'type' => 'Spin-button'
},
'TAGw' => {
'type' => 'Fixed',
'default' => '3',
'content' => '',
'info' => 'Parameter',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'in_sel_i' => {
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'sel_i',
'range' => 'SELw-1 : 0',
'type' => 'input'
},
'in_cti_i' => {
'intfc_port' => 'cti_i',
'range' => 'TAGw-1 : 0',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[1]'
},
'flit_in_wr' => {
'intfc_name' => 'socket:ni[0]',
'range' => '',
'intfc_port' => 'flit_in_wr',
'type' => 'input'
},
'in_dat_i' => {
'intfc_name' => 'plug:wb_slave[1]',
'type' => 'input',
'range' => 'Dw-1 : 0',
'intfc_port' => 'dat_i'
},
'out_we_i' => {
'type' => 'input',
'intfc_port' => 'we_i',
'range' => '',
'intfc_name' => 'plug:wb_slave[2]'
},
'clk' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'intfc_port' => 'clk_i',
'type' => 'input'
},
'in_dat_o' => {
'type' => 'output',
'range' => 'Dw-1 : 0',
'intfc_port' => 'dat_o',
'intfc_name' => 'plug:wb_slave[1]'
},
'out_sel_i' => {
'intfc_port' => 'sel_i',
'range' => 'SELw-1 : 0',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[2]'
'OUTPUT_MEM_Aw' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => ' 10',
'content' => '4,32,1',
'type' => 'Spin-button'
},
'M_Aw' => {
'default' => '32',
'content' => 'Dw',
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => 'Parameter',
'type' => 'Fixed'
},
'out_dat_i' => {
'intfc_name' => 'plug:wb_slave[2]',
'type' => 'input',
'range' => 'Dw-1 : 0',
'intfc_port' => 'dat_i'
},
'flit_out_wr' => {
'intfc_name' => 'socket:ni[0]',
'range' => '',
'intfc_port' => 'flit_out_wr',
'type' => 'output'
},
'ctrl_ack_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'intfc_port' => 'ack_o',
'type' => 'output'
},
'ctrl_dat_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input',
'intfc_port' => 'dat_i',
'range' => 'Dw-1 : 0'
},
'ctrl_sel_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'sel_i',
'range' => 'SELw-1 : 0',
'type' => 'input'
},
'out_cti_i' => {
'intfc_name' => 'plug:wb_slave[2]',
'range' => 'TAGw-1 : 0',
'intfc_port' => 'cti_i',
'type' => 'input'
},
'credit_out' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'V-1 : 0',
'intfc_port' => 'credit_out',
'type' => 'output'
},
'out_stb_i' => {
'intfc_name' => 'plug:wb_slave[2]',
'type' => 'input',
'intfc_port' => 'stb_i',
'range' => ''
},
'in_addr_i' => {
'intfc_port' => 'adr_i',
'range' => 'S_Aw-1 : 0',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[1]'
},
'in_cyc_i' => {
'intfc_name' => 'plug:wb_slave[1]',
'type' => 'input',
'intfc_port' => 'cyc_i',
'range' => ''
},
'flit_out' => {
'range' => 'Fw-1 : 0',
'intfc_port' => 'flit_out',
'type' => 'output',
'intfc_name' => 'socket:ni[0]'
},
'ctrl_cyc_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'cyc_i',
'range' => '',
'type' => 'input'
},
'in_ack_o' => {
'intfc_name' => 'plug:wb_slave[1]',
'type' => 'output',
'intfc_port' => 'ack_o',
'range' => ''
},
'out_dat_o' => {
'intfc_name' => 'plug:wb_slave[2]',
'type' => 'output',
'range' => 'Dw-1 : 0',
'intfc_port' => 'dat_o'
},
'in_stb_i' => {
'intfc_name' => 'plug:wb_slave[1]',
'range' => '',
'intfc_port' => 'stb_i',
'type' => 'input'
},
'out_addr_i' => {
'type' => 'input',
'range' => 'S_Aw-1 : 0',
'intfc_port' => 'adr_i',
'intfc_name' => 'plug:wb_slave[2]'
},
'in_we_i' => {
'intfc_name' => 'plug:wb_slave[1]',
'range' => '',
'intfc_port' => 'we_i',
'type' => 'input'
'IN_MEM_BYTEw' => {
'type' => 'Fixed',
'global_param' => 'Don\'t include',
'redefine_param' => 1,
'info' => undef,
'default' => 'INPUT_MEM_Aw+(Dw/8)',
'content' => ''
},
'NX' => {
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter',
'info' => 'Parameter',
'content' => '',
'default' => ' 4'
},
'flit_in' => {
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'range' => 'Fw-1 : 0',
'intfc_port' => 'flit_in'
'NY' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => 'Parameter',
'content' => '',
'default' => ' 4'
},
'credit_in' => {
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_in',
'range' => 'V-1 : 0',
'type' => 'input'
},
'current_y' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'Yw-1 : 0',
'intfc_port' => 'current_y',
'type' => 'input'
},
'ctrl_we_i' => {
'type' => 'input',
'intfc_port' => 'we_i',
'range' => '',
'intfc_name' => 'plug:wb_slave[0]'
},
'reset' => {
'type' => 'input',
'intfc_port' => 'reset_i',
'range' => '',
'intfc_name' => 'plug:reset[0]'
},
'out_ack_o' => {
'intfc_name' => 'plug:wb_slave[2]',
'type' => 'output',
'intfc_port' => 'ack_o',
'range' => ''
},
'ctrl_stb_i' => {
'range' => '',
'intfc_port' => 'stb_i',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]'
},
'irq' => {
'intfc_name' => 'plug:interrupt_peripheral[0]',
'intfc_port' => 'int_o',
'range' => '',
'type' => 'output'
}
},
'module_name' => 'ni_slave',
'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/ni/ni_slave.v',
'V' => {
'default' => '4',
'content' => '',
'info' => 'Parameter',
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed'
},
'C' => {
'type' => 'Fixed',
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter',
'default' => ' 4',
'content' => ''
},
'CRC_EN' => {
'type' => 'Combo-box',
'content' => '"YES","NO"',
'default' => '"NO"',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'SRC_ADR_HDR_WIDTH' => {
'info' => 'Parameter',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '',
'default' => '8',
'type' => 'Fixed'
},
'SWA_ARBITER_TYPE' => {
'default' => '"RRA"',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'info' => undef,
'type' => 'Fixed'
}
},
'system_h' => ' /* NI wb registers addresses
0 : STATUS1_WB_ADDR // status1: {send_enable_binarry,receive_enable_binarry,send_vc_is_busy,receive_vc_is_busy,receive_vc_got_packet}
1 : STATUS2_WB_ADDR // status2:
0 : STATUS1_WB_ADDR // status1: {send_vc_is_busy,receive_vc_is_busy,receive_vc_packet_is_saved,receive_vc_got_packet};
1 : STATUS2_WB_ADDR // status2: {send_enable_binary,receive_enable_binary,vc_got_error,any_error_isr,got_pck_isr, save_done_isr,send_done_isr,any_error_int_en,got_pck_int_en, save_done_int_en,send_done_int_en};
2 : BURST_SIZE_WB_ADDR // The busrt size in words
3 : SEND_DATA_SIZE_WB_ADDR, // The size of data to be sent in byte
334,33 → 273,41
9 : RECEIVE_SRC_WB_ADDR // The source router (the router which is sent this packet).
10 : RECEIVE_CTRL_WB_ADDR // The NI reciever control register
11 : RECEIVE_MAX_BUFF_SIZ // The receiver\'s allocated buffer size in words. If the packet size is bigger tha the buffer size the rest of will be discarred
12 : ERROR_FLAGS // errors: {crc_miss_match,burst_size_error,send_data_size_error,rcive_buff_ovrflw_err};
*/
#define CORID ${CORE_ID}
#define MAX_X_ADDR ${NX}
#define MAX_Y_ADDR ${NY}
 
#define Y_ADDR (CORID / MAX_X_ADDR)
#define X_ADDR (CORID % MAX_X_ADDR)
 
 
#define ${IP}_STATUS1_REG (*((volatile unsigned int *) ($BASE))) //0
#define ${IP}_STATUS2_REG (*((volatile unsigned int *) ($BASE+4))) //1
#define ${IP}_BURST_SIZE_REG (*((volatile unsigned int *) ($BASE+8))) //2
 
#define ${IP}_STATUS1_REG (*((volatile unsigned int *) ($BASE0))) //0
#define ${IP}_STATUS2_REG (*((volatile unsigned int *) ($BASE0+4))) //1
#define ${IP}_BURST_SIZE_REG (*((volatile unsigned int *) ($BASE0+8))) //2
 
 
#define ${IP}_NUM_VCs ${V}
 
#define ${IP}_SEND_DATA_SIZE_REG(v) (*((volatile unsigned int *) ($BASE+12+(v<<6)))) //3
#define ${IP}_SEND_START_ADDR_REG(v) (*((volatile unsigned int *) ($BASE+16+(v<<6)))) //4
#define ${IP}_SEND_DEST_REG(v) (*((volatile unsigned int *) ($BASE+20+(v<<6)))) //5
#define ${IP}_SEND_CTRL_REG(v) (*((volatile unsigned int *) ($BASE+24+(v<<6)))) //6
#define ${IP}_SEND_DATA_SIZE_REG(v) (*((volatile unsigned int *) ($BASE0+12+(v<<6)))) //3
#define ${IP}_SEND_START_ADDR_REG(v) (*((volatile unsigned int *) ($BASE0+16+(v<<6)))) //4
#define ${IP}_SEND_DEST_REG(v) (*((volatile unsigned int *) ($BASE0+20+(v<<6)))) //5
#define ${IP}_SEND_CTRL_REG(v) (*((volatile unsigned int *) ($BASE0+24+(v<<6)))) //6
 
#define ${IP}_RECEIVE_DATA_SIZE_REG(v) (*((volatile unsigned int *) ($BASE+28+(v<<6)))) //7
#define ${IP}_RECEIVE_STRT_ADDR_REG(v) (*((volatile unsigned int *) ($BASE+32+(v<<6)))) //8
#define ${IP}_RECEIVE_CTRL_REG(v) (*((volatile unsigned int *) ($BASE+36+(v<<6)))) //9
#define ${IP}_RECEIVE_MAX_BUFF_SIZ_REG(v) (*((volatile unsigned int *) ($BASE+40+(v<<6)))) //10
#define ${IP}_RECEIVE_CRC_MATCH_REG(v) (*((volatile unsigned int *) ($BASE+44+(v<<6)))) //11
#define ${IP}_RECEIVE_DATA_SIZE_REG(v) (*((volatile unsigned int *) ($BASE0+28+(v<<6)))) //7
#define ${IP}_RECEIVE_STRT_ADDR_REG(v) (*((volatile unsigned int *) ($BASE0+32+(v<<6)))) //8
#define ${IP}_RECEIVE_SRC_REG(v) (*((volatile unsigned int *) ($BASE0+36+(v<<6)))) //9
#define ${IP}_RECEIVE_CTRL_REG(v) (*((volatile unsigned int *) ($BASE0+40+(v<<6)))) //10
#define ${IP}_RECEIVE_MAX_BUFF_SIZ_REG(v) (*((volatile unsigned int *) ($BASE0+44+(v<<6)))) //11
#define ${IP}_ERROR_FLAGS_REG(v) (*((volatile unsigned int *) ($BASE0+48+(v<<6)))) //12
 
 
 
// assign status1= {send_vc_is_busy,receive_vc_is_busy,receive_vc_packet_is_saved,receive_vc_got_packet};
// assign status2= {send_enable_binarry,receive_enable_binarry,crc_miss_match,got_pck_isr, save_done_isr,send_done_isr,got_pck_int_en, save_done_int_en,send_done_int_en};
// assign status2= {send_enable_binary,receive_enable_binary,vc_got_error,any_error_isr,got_pck_isr, save_done_isr,send_done_isr,any_error_int_en,got_pck_int_en, save_done_int_en,send_done_int_en};
 
#define ${IP}_got_packet(v) ((${IP}_STATUS1_REG >> (v)) & 0x1)
367,50 → 314,386
#define ${IP}_packet_is_saved(v) ((${IP}_STATUS1_REG >> (${V}+v)) & 0x1)
#define ${IP}_receive_is_busy(v) ((${IP}_STATUS1_REG >> (2*${V}+v)) & 0x1)
#define ${IP}_send_is_busy(v) ((${IP}_STATUS1_REG >> (3*${V}+v)) & 0x1)
#define ${IP}_got_any_error(v) ((${IP}_STATUS2_REG >> (8+v)) & 0x1)
 
#define SEND_DONE_INT_EN (1<<0)
#define SAVE_DONE_INT_EN (1<<1)
#define GOT_PCK_INT_EN (1<<2)
#define ERRORS_INT_EN (1<<3)
#define ALL_INT_EN (SEND_DONE_INT_EN | SAVE_DONE_INT_EN | GOT_PCK_INT_EN | ERRORS_INT_EN)
 
#define SEND_DONE_ISR (1<<4)
#define SAVE_DONE_ISR (1<<5)
#define GOT_PCK_ISR (1<<6)
#define ERRORS_ISR (1<<7)
 
void ${IP}_initial (unsigned int burst_size) {
${IP}_BURST_SIZE_REG = burst_size;
 
 
//errors = {crc_miss_match,illegal_send_req,burst_size_error,send_data_size_error,rcive_buff_ovrflw_err};
#define BUFF_OVER_FLOW_ERR (1<<0) // This error happens when the receiver allocated buffer size is smaller than the received packet size
#define SEND_DATA_SIZE_ERR (1<<1) // This error happens when the send data size is not set
#define BURST_SIZE_ERR (1<<2) // This error happens when the burst size is not set
#define ILLEGAL_SEND_REQ (1<<3) // This error happens when a new send request is received while the DMA is still busy sending previous packet
#define CRC_MISS_MATCH (1<<4) // This error happens when the received packet CRC miss match
 
//ack intrrupts functions
#define ${IP}_ack_send_done_isr() (${IP}_STATUS2_REG &= (ALL_INT_EN |SEND_DONE_ISR))
#define ${IP}_ack_save_done_isr() (${IP}_STATUS2_REG &= (ALL_INT_EN | SAVE_DONE_ISR))
#define ${IP}_ack_got_pck_isr() (${IP}_STATUS2_REG &= (ALL_INT_EN | GOT_PCK_ISR))
#define ${IP}_ack_errors_isr() (${IP}_STATUS2_REG &= (ALL_INT_EN | ERRORS_ISR))
 
#define ${IP}_ack_all_isr() (${IP}_STATUS2_REG = ${IP}_STATUS2_REG)
 
 
struct SRC_INFOS{
unsigned char r; // reserved
unsigned char c; // message class
unsigned char y; //y address
unsigned char x ; //x address
} ;
 
inline struct SRC_INFOS get_src_info(unsigned char v){
struct SRC_INFOS src_info =*(struct SRC_INFOS *) (&ni_RECEIVE_SRC_REG(v));
return src_info;
}
 
/*
The NI initializing function.
The burst_size must be <= $MAX_BURST_SIZE
send_int_en :1: enable the intrrupt when a packet is sent 0 : This intrrupt is disabled
save_int_en : 1: enable the intrrupt when a recived packet is saved on internal buffer 0 : This intrrupt is disabled
got_pck_int_en : 1: enable the intrrupt when a packet is recived in NI. 0 : This intrrupt is disabled
 
*/
void ${IP}_initial (unsigned int burst_size, unsigned char errors_int_en, unsigned char send_int_en, unsigned char save_int_en, unsigned char got_pck_int_en) {
${IP}_BURST_SIZE_REG = burst_size;
if(errors_int_en) ${IP}_STATUS2_REG |= ERRORS_INT_EN;
if(send_int_en) ${IP}_STATUS2_REG |= SEND_DONE_INT_EN;
if(save_int_en) ${IP}_STATUS2_REG |= SAVE_DONE_INT_EN;
if(got_pck_int_en) ${IP}_STATUS2_REG |= GOT_PCK_INT_EN;
}
 
/*
The NI message sent function:
v: virtual channel number which this packet should be sent to
class_num: message class number. Diffrent message classes can be sent via isolated network resources to avoid protocol deadlock
data_start_addr : The address pointer to the start location of the packet inside the NI internal buffer
data_size: the message data size in words
dest_x: the x address of destination core
dest_y: the y address of destination core
 
*/
 
void ${IP}_transfer (unsigned int v, unsigned int class_num, unsigned int data_start_addr, unsigned int data_size, unsigned int dest_x,unsigned int dest_y){
while (${IP}_send_is_busy(v)); // wait until VC is busy sending previous packet
 
${IP}_SEND_DATA_SIZE_REG(v) = data_size;
${IP}_SEND_START_ADDR_REG(v) = data_start_addr;
${IP}_SEND_START_ADDR_REG(v) = $BASE1 + data_start_addr;
${IP}_SEND_DEST_REG(v) = dest_x | (dest_y<<4)| (class_num<<8) ;
}
 
/*
The NI message receiver function:
v: virtual channel number of the received packet
data_start_addr : The address pointer to the start location of the memory where the newly arrived packet must be stored by NI in.
max_buffer_size : The allocated receive-memory buffer size in words.
*/
 
void ${IP}_receive (unsigned int v, unsigned int data_start_addr, unsigned int max_buffer_size){
while (${IP}_receive_is_busy(v)); // wait until VC is busy saving previous packet
 
${IP}_RECEIVE_STRT_ADDR_REG(v) = data_start_addr;
${IP}_RECEIVE_STRT_ADDR_REG(v) = $BASE2 + data_start_addr;
${IP}_RECEIVE_MAX_BUFF_SIZ_REG(v) = max_buffer_size;
${IP}_RECEIVE_CTRL_REG(v) = 1;
 
}',
'ip_name' => 'ni_slave',
'description_pdf' => '/mpsoc/src_peripheral/ni/NI.pdf',
'ports' => {
'flit_in' => {
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'range' => 'Fw-1 : 0',
'intfc_port' => 'flit_in'
},
'in_we_i' => {
'intfc_name' => 'plug:wb_slave[1]',
'type' => 'input',
'range' => '',
'intfc_port' => 'we_i'
},
'current_y' => {
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_y',
'type' => 'input',
'range' => 'Yw-1 : 0'
},
'out_stb_i' => {
'intfc_name' => 'plug:wb_slave[2]',
'intfc_port' => 'stb_i',
'type' => 'input',
'range' => ''
},
'out_addr_i' => {
'intfc_name' => 'plug:wb_slave[2]',
'intfc_port' => 'adr_i',
'range' => 'S_Aw-1 : 0',
'type' => 'input'
},
'out_dat_i' => {
'intfc_name' => 'plug:wb_slave[2]',
'intfc_port' => 'dat_i',
'range' => 'Dw-1 : 0',
'type' => 'input'
},
'ctrl_sel_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'SELw-1 : 0',
'type' => 'input',
'intfc_port' => 'sel_i'
},
'reset' => {
'type' => 'input',
'intfc_port' => 'reset_i',
'range' => '',
'intfc_name' => 'plug:reset[0]'
},
'out_dat_o' => {
'intfc_name' => 'plug:wb_slave[2]',
'type' => 'output',
'range' => 'Dw-1 : 0',
'intfc_port' => 'dat_o'
},
'ctrl_cyc_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input',
'range' => '',
'intfc_port' => 'cyc_i'
},
'flit_out' => {
'intfc_port' => 'flit_out',
'type' => 'output',
'range' => 'Fw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'out_we_i' => {
'intfc_name' => 'plug:wb_slave[2]',
'intfc_port' => 'we_i',
'type' => 'input',
'range' => ''
},
'in_dat_i' => {
'intfc_name' => 'plug:wb_slave[1]',
'range' => 'Dw-1 : 0',
'intfc_port' => 'dat_i',
'type' => 'input'
},
'clk' => {
'intfc_port' => 'clk_i',
'range' => '',
'type' => 'input',
'intfc_name' => 'plug:clk[0]'
},
'in_addr_i' => {
'intfc_name' => 'plug:wb_slave[1]',
'range' => 'S_Aw-1 : 0',
'intfc_port' => 'adr_i',
'type' => 'input'
},
'out_cti_i' => {
'intfc_name' => 'plug:wb_slave[2]',
'intfc_port' => 'cti_i',
'type' => 'input',
'range' => 'TAGw-1 : 0'
},
'credit_in' => {
'range' => 'V-1 : 0',
'type' => 'input',
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]'
},
'ctrl_stb_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input',
'range' => '',
'intfc_port' => 'stb_i'
},
'flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'range' => '',
'type' => 'output',
'intfc_name' => 'socket:ni[0]'
},
'irq' => {
'intfc_port' => 'int_o',
'type' => 'output',
'range' => '',
'intfc_name' => 'plug:interrupt_peripheral[0]'
},
'in_stb_i' => {
'intfc_port' => 'stb_i',
'range' => '',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[1]'
},
'in_ack_o' => {
'type' => 'output',
'range' => '',
'intfc_port' => 'ack_o',
'intfc_name' => 'plug:wb_slave[1]'
},
'ctrl_cti_i' => {
'range' => 'TAGw-1 : 0',
'type' => 'input',
'intfc_port' => 'cti_i',
'intfc_name' => 'plug:wb_slave[0]'
},
'in_sel_i' => {
'intfc_name' => 'plug:wb_slave[1]',
'range' => 'SELw-1 : 0',
'type' => 'input',
'intfc_port' => 'sel_i'
},
'ctrl_we_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'we_i',
'type' => 'input',
'range' => ''
},
'in_dat_o' => {
'type' => 'output',
'intfc_port' => 'dat_o',
'range' => 'Dw-1 : 0',
'intfc_name' => 'plug:wb_slave[1]'
},
'current_x' => {
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'range' => 'Xw-1 : 0',
'intfc_port' => 'current_x'
},
'ctrl_dat_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input',
'intfc_port' => 'dat_i',
'range' => 'Dw-1 : 0'
},
'in_cyc_i' => {
'intfc_port' => 'cyc_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:wb_slave[1]'
},
'in_cti_i' => {
'type' => 'input',
'range' => 'TAGw-1 : 0',
'intfc_port' => 'cti_i',
'intfc_name' => 'plug:wb_slave[1]'
},
'ctrl_addr_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'S_Aw-1 : 0',
'intfc_port' => 'adr_i',
'type' => 'input'
},
'out_ack_o' => {
'intfc_port' => 'ack_o',
'type' => 'output',
'range' => '',
'intfc_name' => 'plug:wb_slave[2]'
},
'credit_out' => {
'type' => 'output',
'range' => 'V-1 : 0',
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]'
},
'ctrl_ack_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'output',
'range' => '',
'intfc_port' => 'ack_o'
},
'ctrl_dat_o' => {
'range' => 'Dw-1 : 0',
'type' => 'output',
'intfc_port' => 'dat_o',
'intfc_name' => 'plug:wb_slave[0]'
},
'flit_in_wr' => {
'type' => 'input',
'intfc_port' => 'flit_in_wr',
'range' => '',
'intfc_name' => 'socket:ni[0]'
},
'out_cyc_i' => {
'range' => '',
'intfc_port' => 'cyc_i',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[2]'
},
'out_sel_i' => {
'intfc_name' => 'plug:wb_slave[2]',
'intfc_port' => 'sel_i',
'range' => 'SELw-1 : 0',
'type' => 'input'
}
},
'description' => '',
'sockets' => {
'ni' => {
'connection_num' => 'single connection',
'ni' => {},
'value' => 1,
'type' => 'num',
'0' => {
'name' => 'ni'
}
}
},
'parameters_order' => [
'INPUT_MEM_Aw',
'OUTPUT_MEM_Aw',
'MAX_TRANSACTION_WIDTH',
'MAX_BURST_SIZE',
'DEBUG_EN',
'CLASS_HDR_WIDTH',
'ROUTING_HDR_WIDTH',
'DST_ADR_HDR_WIDTH',
'SRC_ADR_HDR_WIDTH',
'TOPOLOGY',
'ROUTE_NAME',
'NX',
'NY',
'C',
'V',
'B',
'Fpay',
'CRC_EN',
'SWA_ARBITER_TYPE',
'WEIGHTw',
'Dw',
'S_Aw',
'M_Aw',
'TAGw',
'SELw',
'IN_MEM_BYTEw',
'OUT_MEM_BYTEw'
],
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'version' => 45,
'unused' => {
'plug:wb_slave[0]' => [
'tag_i',
'rty_o',
'err_o',
'bte_i'
],
'plug:wb_slave[1]' => [
'tag_i',
'rty_o',
'err_o',
'bte_i'
],
'plug:wb_slave[2]' => [
'tag_i',
'rty_o',
'err_o',
'bte_i'
]
},
'ports_order' => [
'reset',
'clk',
451,6 → 734,55
'out_ack_o',
'irq'
],
'version' => 47,
'module_name' => 'ni_slave',
'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/ni/ni_slave.v',
'plugs' => {
'reset' => {
'reset' => {},
'type' => 'num',
'value' => 1,
'0' => {
'name' => 'reset'
}
},
'wb_slave' => {
'type' => 'num',
'wb_slave' => {},
'value' => 3,
'0' => {
'name' => 'wb_ctrl',
'width' => 10,
'addr' => '0xb800_0000 0xbfff_ffff custom devices'
},
'2' => {
'addr' => '0xb800_0000 0xbfff_ffff custom devices',
'width' => 'OUT_MEM_BYTEw',
'name' => 'wb_out'
},
'1' => {
'addr' => '0xb800_0000 0xbfff_ffff custom devices',
'width' => 'IN_MEM_BYTEw',
'name' => 'wb_in'
}
},
'clk' => {
'clk' => {},
'type' => 'num',
'value' => 1,
'0' => {
'name' => 'clk'
}
},
'interrupt_peripheral' => {
'interrupt_peripheral' => {},
'0' => {
'name' => 'interrupt'
},
'value' => 1,
'type' => 'num'
}
},
'hdl_files' => [
'/mpsoc/src_noc/arbiter.v',
'/mpsoc/src_noc/flit_buffer.v',
469,288 → 801,17
'/mpsoc/src_peripheral/ram/wb_dual_port_ram.v',
'/mpsoc/src_peripheral/ram/wb_single_port_ram.v'
],
'unused' => {
'plug:wb_slave[0]' => [
'rty_o',
'tag_i',
'bte_i',
'err_o'
],
'plug:wb_slave[1]' => [
'rty_o',
'tag_i',
'bte_i',
'err_o'
],
'plug:wb_slave[2]' => [
'rty_o',
'tag_i',
'bte_i',
'err_o'
]
},
'parameters' => {
'S_Aw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'content' => '',
'default' => '8',
'info' => 'Parameter',
'redefine_param' => 1
},
'SELw' => {
'type' => 'Fixed',
'default' => '4',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => 'Parameter'
},
'Fw' => {
'info' => undef,
'redefine_param' => 0,
'global_param' => 'Localparam',
'content' => '',
'default' => '2+V+Fpay',
'type' => 'Fixed'
},
'V' => {
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter',
'content' => '',
'default' => '4',
'type' => 'Fixed'
},
'INPUT_MEM_Aw' => {
'redefine_param' => 1,
'info' => 'Parameter',
'default' => ' 10',
'content' => '4,32,1',
'global_param' => 'Parameter',
'type' => 'Spin-button'
},
'B' => {
'global_param' => 'Parameter',
'content' => '',
'default' => ' 4',
'type' => 'Fixed',
'info' => 'Parameter',
'redefine_param' => 1
},
'MAX_TRANSACTION_WIDTH' => {
'type' => 'Spin-button',
'content' => '4,32,1',
'global_param' => 'Localparam',
'default' => '13',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
'redefine_param' => 1
},
'Xw' => {
'redefine_param' => 0,
'info' => undef,
'default' => 'log2(NX)',
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ROUTE_NAME' => {
'type' => 'Fixed',
'default' => '"XY" ',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'info' => 'Parameter'
},
'OUT_MEM_BYTEw' => {
'type' => 'Fixed',
'default' => 'OUTPUT_MEM_Aw+(Dw/8)',
'content' => '',
'global_param' => 'Don\'t include',
'redefine_param' => 1,
'info' => undef
},
'Dw' => {
'global_param' => 'Localparam',
'content' => '32,256,8',
'default' => '32',
'type' => 'Spin-button',
'info' => 'wishbone_bus data width in bits.',
'redefine_param' => 1
},
'SRC_ADR_HDR_WIDTH' => {
'redefine_param' => 1,
'info' => 'Parameter',
'type' => 'Fixed',
'default' => '8',
'content' => '',
'global_param' => 'Localparam'
},
'M_Aw' => {
'global_param' => 'Localparam',
'content' => 'Dw',
'default' => '32',
'type' => 'Fixed',
'info' => 'Parameter',
'redefine_param' => 1
},
'C' => {
'info' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed',
'content' => '',
'global_param' => 'Parameter',
'default' => ' 4'
},
'CRC_EN' => {
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'redefine_param' => 1,
'type' => 'Combo-box',
'content' => '"YES","NO"',
'global_param' => 'Localparam',
'default' => '"NO"'
},
'NX' => {
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter',
'content' => '',
'default' => ' 4',
'type' => 'Fixed'
},
'MAX_BURST_SIZE' => {
'type' => 'Combo-box',
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'global_param' => 'Localparam',
'default' => '16',
'info' => 'Maximum burst size in words.
The NI release wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all desired data is transferred. ',
'redefine_param' => 1
},
'CLASS_HDR_WIDTH' => {
'default' => '8',
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed',
'redefine_param' => 1,
'info' => 'Parameter'
},
'Fpay' => {
'default' => ' 32',
'global_param' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1,
'info' => 'Parameter'
},
'ROUTE_TYPE' => {
'type' => 'Fixed',
'default' => ' ',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => 'Parameter'
},
'IN_MEM_BYTEw' => {
'redefine_param' => 1,
'info' => undef,
'type' => 'Fixed',
'default' => 'INPUT_MEM_Aw+(Dw/8)',
'global_param' => 'Don\'t include',
'content' => ''
},
'SWA_ARBITER_TYPE' => {
'redefine_param' => 1,
'info' => undef,
'type' => 'Fixed',
'default' => '"RRA"',
'content' => '',
'global_param' => 'Parameter'
},
'WEIGHTw' => {
'default' => '4',
'global_param' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1,
'info' => undef
},
'OUTPUT_MEM_Aw' => {
'type' => 'Spin-button',
'default' => ' 10',
'content' => '4,32,1',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => 'Parameter'
},
'DEBUG_EN' => {
'redefine_param' => 1,
'info' => 'Parameter',
'default' => ' 1',
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed'
'sockets' => {
'ni' => {
'type' => 'num',
'connection_num' => 'single connection',
'0' => {
'name' => 'ni'
},
'TOPOLOGY' => {
'info' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'default' => '"MESH"'
},
'DST_ADR_HDR_WIDTH' => {
'type' => 'Fixed',
'default' => '8',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => 'Parameter'
},
'ROUTING_HDR_WIDTH' => {
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '8',
'global_param' => 'Localparam',
'content' => '',
'type' => 'Fixed'
},
'P' => {
'default' => '5',
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'info' => 'Parameter'
},
'TAGw' => {
'default' => '3',
'global_param' => 'Localparam',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1,
'info' => 'Parameter'
},
'Yw' => {
'content' => '',
'global_param' => 'Localparam',
'default' => 'log2(NY)',
'type' => 'Fixed',
'info' => undef,
'redefine_param' => 0
},
'NY' => {
'type' => 'Fixed',
'content' => '',
'global_param' => 'Parameter',
'default' => ' 4',
'info' => 'Parameter',
'redefine_param' => 1
}
},
'modules' => {
'ni_slave' => {}
}
'ni' => {},
'value' => 1
}
},
'ip_name' => 'ni_slave',
'category' => 'NoC'
}, 'ip_gen' );
/mpsoc/perl_gui/lib/ip/Processor/mor1kx.IP
3,7 → 3,7
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.8.0
## This file is part of ProNoC 1.8.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
10,190 → 10,86
################################################################################
 
$ipgen = bless( {
'gui_status' => {
'timeout' => 0,
'status' => 'ideal'
},
'modules' => {
'mor1k' => {}
},
'hdl_files' => [
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_branch_prediction.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_bus_if_avalon.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_bus_if_wb32.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cache_lru.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cfgrs.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu_espresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu_prontoespresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ctrl_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ctrl_espresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ctrl_prontoespresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_dcache.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_decode.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_decode_execute_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx-defines.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_dmmu.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_execute_alu.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_execute_ctrl_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_espresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_prontoespresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_tcm_prontoespresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_icache.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_immu.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_lsu_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_lsu_espresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_pic.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_rf_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_rf_espresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_simple_dpram_sclk.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx-sprs.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_store_buffer.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ticktimer.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_true_dpram_sclk.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_utils.vh',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_wb_mux_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_wb_mux_espresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/mor1k.v'
],
'module_name' => 'mor1k',
'parameters_order' => [
'OPTION_OPERAND_WIDTH',
'IRQ_NUM'
'IRQ_NUM',
'OPTION_DCACHE_SNOOP',
'FEATURE_INSTRUCTIONCACHE',
'FEATURE_DATACACHE',
'FEATURE_IMMU',
'FEATURE_DMMU'
],
'sw_files' => [
'/mpsoc/src_processor/mor1kx-3.1/sw/link.ld',
'/mpsoc/src_processor/mor1kx-3.1/sw/Makefile',
'/mpsoc/src_processor/mor1kx-3.1/sw/mor1kx',
'/mpsoc/src_processor/src_lib/simple-printf',
'/mpsoc/src_processor/mor1kx-3.1/sw/define_printf.h'
],
'version' => 17,
'sockets' => {
'interrupt_peripheral' => {
'type' => 'param',
'value' => 'IRQ_NUM',
'0' => {
'name' => 'interrupt_peripheral'
},
'connection_num' => 'single connection',
'type' => 'param'
'connection_num' => 'single connection'
}
},
'ports' => {
'dwbm_dat_i' => {
'intfc_name' => 'plug:wb_master[1]',
'range' => '31:0',
'intfc_port' => 'dat_i',
'type' => 'input'
},
'dwbm_cyc_o' => {
'intfc_name' => 'plug:wb_master[1]',
'range' => '',
'intfc_port' => 'cyc_o',
'type' => 'output'
},
'iwbm_rty_i' => {
'range' => '',
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'rty_i',
'type' => 'input'
},
'iwbm_adr_o' => {
'intfc_port' => 'adr_o',
'type' => 'output',
'range' => '31:0',
'intfc_name' => 'plug:wb_master[0]'
},
'iwbm_dat_i' => {
'intfc_name' => 'plug:wb_master[0]',
'range' => '31:0',
'type' => 'input',
'intfc_port' => 'dat_i'
},
'rst' => {
'range' => '',
'intfc_name' => 'plug:reset[0]',
'type' => 'input',
'intfc_port' => 'reset_i'
},
'irq_i' => {
'type' => 'input',
'intfc_port' => 'int_i',
'intfc_name' => 'socket:interrupt_peripheral[array]',
'range' => '31:0'
},
'iwbm_bte_o' => {
'intfc_name' => 'plug:wb_master[0]',
'range' => '1:0',
'type' => 'output',
'intfc_port' => 'bte_o'
},
'dwbm_ack_i' => {
'intfc_port' => 'ack_i',
'type' => 'input',
'intfc_name' => 'plug:wb_master[1]',
'range' => ''
},
'iwbm_dat_o' => {
'type' => 'output',
'intfc_port' => 'dat_o',
'intfc_name' => 'plug:wb_master[0]',
'range' => '31:0'
},
'iwbm_cyc_o' => {
'range' => '',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output',
'intfc_port' => 'cyc_o'
},
'iwbm_we_o' => {
'intfc_name' => 'plug:wb_master[0]',
'range' => '',
'type' => 'output',
'intfc_port' => 'we_o'
},
'dwbm_rty_i' => {
'intfc_name' => 'plug:wb_master[1]',
'range' => '',
'type' => 'input',
'intfc_port' => 'rty_i'
},
'dwbm_cti_o' => {
'intfc_port' => 'cti_o',
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]',
'range' => '2:0'
},
'dwbm_adr_o' => {
'intfc_port' => 'adr_o',
'type' => 'output',
'range' => '31:0',
'intfc_name' => 'plug:wb_master[1]'
},
'dwbm_err_i' => {
'type' => 'input',
'intfc_port' => 'err_i',
'range' => '',
'intfc_name' => 'plug:wb_master[1]'
},
'clk' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'clk_i'
},
'iwbm_ack_i' => {
'intfc_name' => 'plug:wb_master[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'ack_i'
},
'dwbm_dat_o' => {
'intfc_name' => 'plug:wb_master[1]',
'range' => '31:0',
'type' => 'output',
'intfc_port' => 'dat_o'
},
'iwbm_sel_o' => {
'range' => '3:0',
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'sel_o',
'type' => 'output'
},
'dwbm_stb_o' => {
'type' => 'output',
'intfc_port' => 'stb_o',
'intfc_name' => 'plug:wb_master[1]',
'range' => ''
},
'cpu_en' => {
'range' => '',
'intfc_name' => 'plug:enable[0]',
'type' => 'input',
'intfc_port' => 'enable_i'
},
'dwbm_we_o' => {
'type' => 'output',
'intfc_port' => 'we_o',
'range' => '',
'intfc_name' => 'plug:wb_master[1]'
},
'iwbm_err_i' => {
'intfc_port' => 'err_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:wb_master[0]'
},
'iwbm_cti_o' => {
'intfc_port' => 'cti_o',
'type' => 'output',
'range' => '2:0',
'intfc_name' => 'plug:wb_master[0]'
},
'dwbm_sel_o' => {
'intfc_port' => 'sel_o',
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]',
'range' => '3:0'
},
'iwbm_stb_o' => {
'intfc_name' => 'plug:wb_master[0]',
'range' => '',
'type' => 'output',
'intfc_port' => 'stb_o'
},
'dwbm_bte_o' => {
'type' => 'output',
'intfc_port' => 'bte_o',
'intfc_name' => 'plug:wb_master[1]',
'range' => '1:0'
}
},
'ip_name' => 'mor1kx',
'category' => 'Processor',
'file_name' => '/home/alireza/mywork/mpsoc/src_processor/mor1kx-3.1/rtl/mor1k.v',
'unused' => {
'plug:wb_master[1]' => [
'tag_o'
202,50 → 98,86
'tag_o'
]
},
'modules' => {
'mor1k' => {}
},
'parameters' => {
'FEATURE_IMMU' => {
'content' => '"NONE","ENABLED"',
'type' => 'Combo-box',
'default' => '"ENABLED"',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => ''
},
'OPTION_OPERAND_WIDTH' => {
'type' => 'Fixed',
'default' => '32',
'content' => '',
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'FEATURE_DMMU' => {
'info' => '',
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Combo-box',
'default' => '"ENABLED"',
'content' => '"NONE","ENABLED"'
},
'FEATURE_INSTRUCTIONCACHE' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'info' => '',
'content' => '"NONE","ENABLED"',
'default' => '"ENABLED"',
'type' => 'Combo-box'
},
'OPTION_DCACHE_SNOOP' => {
'info' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'default' => '"NONE"',
'type' => 'Combo-box',
'content' => '"NONE","ENABLED"'
},
'FEATURE_DATACACHE' => {
'content' => '"NONE","ENABLED"',
'default' => '"ENABLED"',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Parameter',
'info' => ''
},
'IRQ_NUM' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '32',
'redefine_param' => 1,
'global_param' => 'Parameter',
'info' => undef
},
'OPTION_OPERAND_WIDTH' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => '32',
'global_param' => 'Parameter',
'type' => 'Fixed'
}
}
},
'category' => 'Processor',
'plugs' => {
'reset' => {
'type' => 'num',
'0' => {
'name' => 'reset'
},
'value' => 1
'value' => 1,
'type' => 'num'
},
'clk' => {
'0' => {
'name' => 'clk'
},
'value' => 1,
'type' => 'num'
},
'enable' => {
'type' => 'num',
'value' => 1,
'0' => {
'name' => 'enable'
},
'type' => 'num'
}
},
'clk' => {
'type' => 'num',
'value' => 1,
'0' => {
'name' => 'clk'
}
},
'wb_master' => {
'1' => {
'name' => 'dwb'
255,12 → 187,21
},
'value' => 2,
'type' => 'num'
}
},
'snoop' => {
'type' => 'num',
'0' => {
'name' => 'snoop'
},
'value' => 1
}
},
'ports_order' => [
'clk',
'rst',
'cpu_en',
'snoop_adr_i',
'snoop_en_i',
'iwbm_adr_o',
'iwbm_stb_o',
'iwbm_cyc_o',
287,55 → 228,6
'dwbm_rty_i',
'irq_i'
],
'ip_name' => 'mor1kx',
'module_name' => 'mor1k',
'version' => 13,
'hdl_files' => [
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_branch_prediction.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_bus_if_avalon.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_bus_if_wb32.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cache_lru.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cfgrs.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu_espresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu_prontoespresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ctrl_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ctrl_espresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ctrl_prontoespresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_dcache.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_decode.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_decode_execute_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx-defines.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_dmmu.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_execute_alu.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_execute_ctrl_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_espresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_prontoespresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_tcm_prontoespresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_icache.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_immu.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_lsu_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_lsu_espresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_pic.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_rf_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_rf_espresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_simple_dpram_sclk.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx-sprs.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_store_buffer.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ticktimer.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_true_dpram_sclk.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_utils.vh',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_wb_mux_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_wb_mux_espresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/mor1k.v'
],
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'system_h' => ' #include "mor1kx/system.h"
 
inline void nop (){
367,12 → 259,186
}
}
*******************************/',
'sw_files' => [
'/mpsoc/src_processor/mor1kx-3.1/sw/link.ld',
'/mpsoc/src_processor/mor1kx-3.1/sw/Makefile',
'/mpsoc/src_processor/mor1kx-3.1/sw/mor1kx',
'/mpsoc/src_processor/src_lib/simple-printf',
'/mpsoc/src_processor/mor1kx-3.1/sw/define_printf.h'
],
'file_name' => '/home/alireza/mywork/mpsoc/src_processor/mor1kx-3.1/rtl/mor1k.v'
'ports' => {
'iwbm_stb_o' => {
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output',
'intfc_port' => 'stb_o',
'range' => ''
},
'dwbm_sel_o' => {
'intfc_port' => 'sel_o',
'type' => 'output',
'range' => '3:0',
'intfc_name' => 'plug:wb_master[1]'
},
'iwbm_sel_o' => {
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'sel_o',
'type' => 'output',
'range' => '3:0'
},
'dwbm_stb_o' => {
'intfc_name' => 'plug:wb_master[1]',
'range' => '',
'intfc_port' => 'stb_o',
'type' => 'output'
},
'iwbm_adr_o' => {
'intfc_name' => 'plug:wb_master[0]',
'range' => '31:0',
'intfc_port' => 'adr_o',
'type' => 'output'
},
'iwbm_err_i' => {
'type' => 'input',
'intfc_port' => 'err_i',
'range' => '',
'intfc_name' => 'plug:wb_master[0]'
},
'dwbm_cyc_o' => {
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output',
'range' => '',
'intfc_port' => 'cyc_o'
},
'clk' => {
'range' => '',
'intfc_port' => 'clk_i',
'type' => 'input',
'intfc_name' => 'plug:clk[0]'
},
'dwbm_err_i' => {
'range' => '',
'intfc_port' => 'err_i',
'type' => 'input',
'intfc_name' => 'plug:wb_master[1]'
},
'iwbm_rty_i' => {
'intfc_name' => 'plug:wb_master[0]',
'type' => 'input',
'intfc_port' => 'rty_i',
'range' => ''
},
'dwbm_dat_o' => {
'type' => 'output',
'intfc_port' => 'dat_o',
'range' => '31:0',
'intfc_name' => 'plug:wb_master[1]'
},
'cpu_en' => {
'intfc_name' => 'plug:enable[0]',
'type' => 'input',
'intfc_port' => 'enable_i',
'range' => ''
},
'iwbm_bte_o' => {
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output',
'intfc_port' => 'bte_o',
'range' => '1:0'
},
'iwbm_ack_i' => {
'intfc_name' => 'plug:wb_master[0]',
'range' => '',
'intfc_port' => 'ack_i',
'type' => 'input'
},
'dwbm_rty_i' => {
'type' => 'input',
'intfc_port' => 'rty_i',
'range' => '',
'intfc_name' => 'plug:wb_master[1]'
},
'dwbm_ack_i' => {
'type' => 'input',
'intfc_port' => 'ack_i',
'range' => '',
'intfc_name' => 'plug:wb_master[1]'
},
'snoop_en_i' => {
'intfc_name' => 'plug:snoop[0]',
'intfc_port' => 'snoop_en_i',
'range' => '',
'type' => 'input'
},
'dwbm_adr_o' => {
'intfc_name' => 'plug:wb_master[1]',
'range' => '31:0',
'intfc_port' => 'adr_o',
'type' => 'output'
},
'iwbm_cyc_o' => {
'intfc_port' => 'cyc_o',
'range' => '',
'type' => 'output',
'intfc_name' => 'plug:wb_master[0]'
},
'dwbm_bte_o' => {
'intfc_name' => 'plug:wb_master[1]',
'range' => '1:0',
'type' => 'output',
'intfc_port' => 'bte_o'
},
'dwbm_dat_i' => {
'range' => '31:0',
'type' => 'input',
'intfc_port' => 'dat_i',
'intfc_name' => 'plug:wb_master[1]'
},
'irq_i' => {
'intfc_name' => 'socket:interrupt_peripheral[array]',
'type' => 'input',
'intfc_port' => 'int_i',
'range' => '31:0'
},
'snoop_adr_i' => {
'intfc_name' => 'plug:snoop[0]',
'intfc_port' => 'snoop_adr_i',
'range' => '31:0',
'type' => 'input'
},
'dwbm_cti_o' => {
'intfc_port' => 'cti_o',
'range' => '2:0',
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]'
},
'iwbm_dat_o' => {
'intfc_name' => 'plug:wb_master[0]',
'range' => '31:0',
'intfc_port' => 'dat_o',
'type' => 'output'
},
'iwbm_dat_i' => {
'type' => 'input',
'intfc_port' => 'dat_i',
'range' => '31:0',
'intfc_name' => 'plug:wb_master[0]'
},
'iwbm_we_o' => {
'intfc_port' => 'we_o',
'type' => 'output',
'range' => '',
'intfc_name' => 'plug:wb_master[0]'
},
'iwbm_cti_o' => {
'intfc_name' => 'plug:wb_master[0]',
'range' => '2:0',
'intfc_port' => 'cti_o',
'type' => 'output'
},
'dwbm_we_o' => {
'intfc_port' => 'we_o',
'type' => 'output',
'range' => '',
'intfc_name' => 'plug:wb_master[1]'
},
'rst' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'intfc_port' => 'reset_i',
'type' => 'input'
}
}
}, 'ip_gen' );
/mpsoc/perl_gui/lib/mpsoc/mor1k_mpsoc.MPSOC
0,0 → 1,2976
#######################################################################
## File: mor1k_mpsoc.MPSOC
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.8.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$mor1k_mpsoc = bless( {
'file_name' => undef,
'mpsoc_name' => 'mor1k_mpsoc',
'gui_status' => {
'timeout' => 0,
'status' => 'save_project'
},
'tile' => {
'1' => {
'param_setting' => 'Default'
},
'2' => {
'param_setting' => 'Default'
},
'3' => {
'param_setting' => 'Default'
},
'0' => {
'param_setting' => 'Default'
}
},
'noc_indept_param' => {},
'class_param' => {
'Cn_0' => '2\'b01',
'Cn_1' => '2\'b10'
},
'socs' => {
'mor1k_tile' => {
'tile_nums' => [
0,
1,
2,
3
],
'top' => bless( {
'parameters' => {
'cpu_OPTION_OPERAND_WIDTH' => '32',
'cpu_FEATURE_DMMU' => '"ENABLED"',
'cpu_FEATURE_IMMU' => '"ENABLED"',
'timer_PRESCALER_WIDTH' => '8',
'cpu_FEATURE_DATACACHE' => '"ENABLED"',
'cpu_IRQ_NUM' => '32',
'ram_Dw' => '32',
'cpu_OPTION_DCACHE_SNOOP' => '"ENABLED"',
'ram_Aw' => 14,
'cpu_FEATURE_INSTRUCTIONCACHE' => '"ENABLED"'
},
'ports' => {
'ss_clk_in' => {
'instance_name' => 'clk_source0',
'intfc_port' => 'clk_i',
'type' => 'input',
'intfc_name' => 'plug:clk[0]',
'range' => ''
},
'ni_flit_out_wr' => {
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'intfc_port' => 'flit_out_wr'
},
'ni_credit_in' => {
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'input',
'intfc_port' => 'credit_in'
},
'ni_flit_out' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'output',
'intfc_port' => 'flit_out'
},
'ni_credit_out' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'credit_out',
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'output'
},
'ni_flit_in' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
},
'cpu_cpu_en' => {
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'range' => '',
'type' => 'input',
'instance_name' => 'mor1kx0'
},
'ni_flit_in_wr' => {
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'intfc_port' => 'flit_in_wr',
'instance_name' => 'ni_master0'
},
'ni_current_y' => {
'type' => 'input',
'range' => 'ni_Yw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_y',
'instance_name' => 'ni_master0'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Xw-1 : 0',
'type' => 'input',
'instance_name' => 'ni_master0'
},
'ss_reset_in' => {
'instance_name' => 'clk_source0',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:reset[0]',
'intfc_port' => 'reset_i'
}
},
'interface' => {
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'instance_name' => 'clk_source0',
'intfc_port' => 'reset_i',
'type' => 'input',
'range' => ''
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'range' => '',
'instance_name' => 'clk_source0'
}
}
},
'plug:enable[0]' => {
'ports' => {
'cpu_cpu_en' => {
'range' => '',
'type' => 'input',
'intfc_port' => 'enable_i',
'instance_name' => 'mor1kx0'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_current_x' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'current_x',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ni_flit_in_wr' => {
'range' => '',
'type' => 'input',
'intfc_port' => 'flit_in_wr',
'instance_name' => 'ni_master0'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'range' => 'ni_Yw-1 : 0',
'type' => 'input',
'instance_name' => 'ni_master0'
},
'ni_flit_in' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'flit_in',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
},
'ni_flit_out_wr' => {
'instance_name' => 'ni_master0',
'type' => 'output',
'range' => '',
'intfc_port' => 'flit_out_wr'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'type' => 'output',
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0'
},
'ni_credit_out' => {
'range' => 'ni_V-1 : 0',
'type' => 'output',
'intfc_port' => 'credit_out',
'instance_name' => 'ni_master0'
},
'ni_credit_in' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'credit_in',
'type' => 'input',
'range' => 'ni_V-1 : 0'
}
}
}
},
'instance_ids' => {
'wishbone_bus0' => {
'localparam' => {
'bus_M' => {
'content' => '1,256,1',
'info' => 'Number of wishbone master interface',
'default' => ' 4',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button'
},
'bus_CTIw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'default' => '3',
'info' => undef
},
'bus_BTEw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '2 ',
'info' => undef,
'content' => ''
},
'bus_Aw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Spin-button',
'default' => '32',
'info' => 'The wishbone Bus address width',
'content' => '4,128,1'
},
'bus_TAGw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '3',
'info' => undef,
'content' => ''
},
'bus_SELw' => {
'content' => '',
'default' => 'bus_Dw/8',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'bus_S' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button',
'content' => '1,256,1',
'info' => 'Number of wishbone slave interface',
'default' => '4'
},
'bus_Dw' => {
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '8,512,8',
'default' => '32',
'info' => 'The wishbone Bus data width in bits.'
}
},
'module_name' => 'wishbone_bus',
'instance' => 'bus',
'module' => 'wishbone_bus',
'category' => 'Bus'
},
'single_port_ram0' => {
'category' => 'RAM',
'parameters' => {
'ram_Dw' => {
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Parameter',
'content' => '8,1024,1',
'info' => 'Memory data width in Bits.',
'default' => '32'
},
'ram_Aw' => {
'info' => 'Memory address width',
'default' => 14,
'content' => '4,31,1',
'type' => 'Spin-button',
'global_param' => 'Parameter',
'redefine_param' => 1
}
},
'module' => 'single_port_ram',
'instance' => 'ram',
'module_name' => 'wb_single_port_ram',
'localparam' => {
'ram_BURST_MODE' => {
'default' => '"ENABLED"',
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'content' => '"DISABLED","ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ram_MEM_CONTENT_FILE_NAME' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Entry',
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
bin: raw binary format . It will be used by JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'default' => '"ram0"',
'content' => ''
},
'ram_SELw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'info' => 'Parameter',
'default' => 'ram_Dw/8'
},
'ram_FPGA_VENDOR' => {
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"ALTERA","GENERIC"',
'info' => '',
'default' => '"ALTERA"'
},
'ram_INIT_FILE_PATH' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => 'SW_LOC',
'info' => undef,
'content' => ''
},
'ram_BYTE_WR_EN' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Combo-box',
'content' => '"YES","NO"',
'default' => '"YES"',
'info' => 'Byte enable'
},
'ram_CTIw' => {
'info' => 'Parameter',
'default' => '3',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ram_TAGw' => {
'content' => '',
'info' => 'Parameter',
'default' => '3',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ram_JTAG_CONNECT' => {
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
'default' => '"DISABLED"',
'content' => '"DISABLED", "JTAG_WB" , "ALTERA_IMCE"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Combo-box'
},
'ram_BTEw' => {
'default' => '2',
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ram_INITIAL_EN' => {
'content' => '"YES","NO"',
'default' => '"YES"',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_JTAG_INDEX' => {
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
',
'default' => 'CORE_ID',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Entry'
}
}
},
'jtag_uart0' => {
'localparam' => {
'uart_SIM_BUFFER_SIZE' => {
'content' => '10,10000,1',
'info' => 'Internal buffer size.
This parameter is valid only in simulation.
If internal buffer overflows, the buffer content are displayed on simulator terminal.',
'default' => 1000,
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'uart_FPGA_VENDOR' => {
'info' => 'FPGA VENDOR name. Only Altera FPGA is supported. Currently the Generic serial port is not supported. ',
'default' => ' "ALTERA"',
'content' => ' "ALTERA"',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'uart_SIM_WAIT_COUNT' => {
'info' => 'This parameter is valid only in simulation.
If internal buffer has a data, the internal timer incremented by one in each clock cycle. If the timer reaches the WAIT_COUNT value, it writes the buffer value on the simulator terminal.',
'default' => '1000',
'content' => '2,100000,1',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1
}
},
'module_name' => 'jtag_uart_wb',
'instance' => 'uart',
'module' => 'jtag_uart',
'category' => 'Communication'
},
'clk_source0' => {
'module' => 'clk_source',
'instance' => 'ss',
'module_name' => 'clk_source',
'category' => 'Source',
'ports' => {
'ss_clk_in' => {
'range' => '',
'intfc_name' => 'plug:clk[0]',
'type' => 'input',
'intfc_port' => 'clk_i'
},
'ss_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
}
}
},
'ni_master0' => {
'localparam' => {
'ni_MAX_TRANSACTION_WIDTH' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '13',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
'content' => '4,32,1'
},
'ni_ROUTING_HDR_WIDTH' => {
'content' => '',
'default' => '8',
'info' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ni_CLASS_HDR_WIDTH' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '8',
'info' => 'Parameter',
'content' => ''
},
'ni_MAX_BURST_SIZE' => {
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
'default' => '16',
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ni_Dw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button',
'content' => '32,256,8',
'default' => '32',
'info' => 'wishbone_bus data width in bits.'
},
'ni_Yw' => {
'redefine_param' => 0,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'default' => 'log2(ni_NY)',
'info' => undef
},
'ni_M_Aw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '32',
'info' => 'Parameter',
'content' => 'Dw'
},
'ni_SRC_ADR_HDR_WIDTH' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '8',
'content' => ''
},
'ni_Fw' => {
'type' => 'Fixed',
'redefine_param' => 0,
'global_param' => 'Localparam',
'content' => '',
'default' => '2+ni_V+ni_Fpay',
'info' => undef
},
'ni_SELw' => {
'info' => 'Parameter',
'default' => '4',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_Xw' => {
'content' => '',
'default' => 'log2(ni_NX)',
'info' => undef,
'redefine_param' => 0,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ni_TAGw' => {
'content' => '',
'info' => 'Parameter',
'default' => '3',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ni_S_Aw' => {
'content' => '',
'info' => 'Parameter',
'default' => '8',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ni_DST_ADR_HDR_WIDTH' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'info' => 'Parameter',
'default' => '8'
},
'ni_CRC_EN' => {
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'default' => '"NO"',
'content' => '"YES","NO"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Combo-box'
}
},
'module_name' => 'ni_master',
'instance' => 'ni',
'module' => 'ni_master',
'parameters' => {
'ni_C' => {
'content' => '',
'info' => 'Parameter',
'default' => 2,
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ni_V' => {
'info' => 'Parameter',
'default' => '2',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_Fpay' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'info' => 'Parameter',
'default' => '32'
},
'ni_TOPOLOGY' => {
'default' => '"MESH"',
'info' => 'Parameter',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_B' => {
'default' => '4',
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'ni_NY' => {
'default' => ' 2',
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'ni_NX' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'info' => 'Parameter',
'default' => 2
},
'ni_DEBUG_EN' => {
'default' => '1',
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'ni_ROUTE_NAME' => {
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter',
'content' => '',
'info' => 'Parameter',
'default' => '"XY"'
}
},
'category' => 'NoC',
'ports' => {
'ni_credit_out' => {
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'output',
'intfc_port' => 'credit_out'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'type' => 'output',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0'
},
'ni_credit_in' => {
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'intfc_port' => 'credit_in'
},
'ni_flit_out_wr' => {
'type' => 'output',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'intfc_port' => 'flit_out_wr'
},
'ni_flit_in' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_current_y' => {
'type' => 'input',
'range' => 'ni_Yw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_y'
},
'ni_flit_in_wr' => {
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'flit_in_wr'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'type' => 'input',
'range' => 'ni_Xw-1 : 0',
'intfc_name' => 'socket:ni[0]'
}
}
},
'mor1kx0' => {
'parameters' => {
'cpu_IRQ_NUM' => {
'content' => '',
'info' => undef,
'default' => '32',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'cpu_OPTION_DCACHE_SNOOP' => {
'content' => '"NONE","ENABLED"',
'default' => '"ENABLED"',
'info' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Combo-box'
},
'cpu_FEATURE_DATACACHE' => {
'content' => '"NONE","ENABLED"',
'default' => '"ENABLED"',
'info' => '',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'cpu_FEATURE_INSTRUCTIONCACHE' => {
'default' => '"ENABLED"',
'info' => '',
'content' => '"NONE","ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'cpu_OPTION_OPERAND_WIDTH' => {
'content' => '',
'info' => 'Parameter',
'default' => '32',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'cpu_FEATURE_IMMU' => {
'default' => '"ENABLED"',
'info' => '',
'content' => '"NONE","ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'cpu_FEATURE_DMMU' => {
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Parameter',
'content' => '"NONE","ENABLED"',
'info' => '',
'default' => '"ENABLED"'
}
},
'category' => 'Processor',
'ports' => {
'cpu_cpu_en' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:enable[0]'
}
},
'module_name' => 'mor1k',
'instance' => 'cpu',
'module' => 'mor1kx'
},
'timer0' => {
'module_name' => 'timer',
'localparam' => {
'timer_Aw' => {
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => undef,
'default' => '3'
},
'timer_TAGw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => undef,
'default' => '3',
'content' => ''
},
'timer_SELw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => undef,
'default' => '4',
'content' => ''
},
'timer_Dw' => {
'default' => '32',
'info' => undef,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'timer_CNTw' => {
'content' => '',
'info' => undef,
'default' => '32 ',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
}
},
'module' => 'timer',
'instance' => 'timer',
'parameters' => {
'timer_PRESCALER_WIDTH' => {
'content' => '1,32,1',
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
 
 
',
'default' => '8',
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Parameter'
}
},
'category' => 'Timer'
}
}
}, 'ip_gen' )
},
'aemb_tile' => {
'tile_nums' => [],
'top' => bless( {
'parameters' => {
'ram_Dw' => '32',
'ram_Aw' => 14
},
'ports' => {
'ni_irq' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'int_o',
'type' => 'output',
'range' => '',
'intfc_name' => 'plug:interrupt_peripheral[0]'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Yw-1 : 0',
'instance_name' => 'ni_master0'
},
'ni_flit_in' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'input',
'intfc_port' => 'flit_in',
'instance_name' => 'ni_master0'
},
'uart_RxD_wr_sim' => {
'instance_name' => 'jtag_uart0',
'intfc_port' => 'RxD_wr_sim',
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '',
'type' => 'input'
},
'uart_RxD_ready_sim' => {
'instance_name' => 'jtag_uart0',
'range' => '',
'intfc_name' => 'socket:RxD_sim[0]',
'type' => 'output',
'intfc_port' => 'RxD_ready_sim'
},
'ni_credit_in' => {
'instance_name' => 'ni_master0',
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'intfc_port' => 'credit_in'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'range' => '',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0'
},
'ss_clk_in' => {
'range' => '',
'intfc_name' => 'plug:clk[0]',
'type' => 'input',
'intfc_port' => 'clk_i',
'instance_name' => 'clk_source0'
},
'ss_reset_in' => {
'instance_name' => 'clk_source0',
'intfc_port' => 'reset_i',
'range' => '',
'intfc_name' => 'plug:reset[0]',
'type' => 'input'
},
'uart_RxD_din_sim' => {
'intfc_port' => 'RxD_din_sim',
'range' => '7:0 ',
'intfc_name' => 'socket:RxD_sim[0]',
'type' => 'input',
'instance_name' => 'jtag_uart0'
},
'uart_irq' => {
'type' => 'output',
'range' => '',
'intfc_name' => 'plug:interrupt_peripheral[0]',
'intfc_port' => 'int_o',
'instance_name' => 'jtag_uart0'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'type' => 'input',
'range' => 'ni_Xw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0'
},
'cpu_sys_int_i' => {
'instance_name' => 'aeMB0',
'type' => 'input',
'intfc_name' => 'socket:interrupt_cpu[0]',
'range' => '',
'intfc_port' => 'int_i'
},
'ni_flit_in_wr' => {
'type' => 'input',
'range' => '',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in_wr',
'instance_name' => 'ni_master0'
},
'cpu_sys_ena_i' => {
'instance_name' => 'aeMB0',
'intfc_port' => 'enable_i',
'type' => 'input',
'intfc_name' => 'plug:enable[0]',
'range' => ''
},
'ni_flit_out' => {
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'output',
'intfc_port' => 'flit_out'
},
'ni_credit_out' => {
'type' => 'output',
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_out',
'instance_name' => 'ni_master0'
}
},
'interface' => {
'socket:interrupt_cpu[0]' => {
'ports' => {
'cpu_sys_int_i' => {
'instance_name' => 'aeMB0',
'range' => '',
'type' => 'input',
'intfc_port' => 'int_i'
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'range' => '',
'instance_name' => 'clk_source0'
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'instance_name' => 'clk_source0',
'type' => 'input',
'range' => '',
'intfc_port' => 'reset_i'
}
}
},
'plug:interrupt_peripheral[0]' => {
'ports' => {
'ni_irq' => {
'intfc_port' => 'int_o',
'type' => 'output',
'range' => '',
'instance_name' => 'ni_master0'
},
'uart_irq' => {
'intfc_port' => 'int_o',
'type' => 'output',
'range' => '',
'instance_name' => 'jtag_uart0'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_current_x' => {
'range' => 'ni_Xw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_x',
'instance_name' => 'ni_master0'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'range' => '',
'type' => 'input',
'instance_name' => 'ni_master0'
},
'ni_current_y' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'current_y',
'type' => 'input',
'range' => 'ni_Yw-1 : 0'
},
'ni_flit_in' => {
'type' => 'input',
'range' => 'ni_Fw-1 : 0',
'intfc_port' => 'flit_in',
'instance_name' => 'ni_master0'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'range' => '',
'type' => 'output',
'instance_name' => 'ni_master0'
},
'ni_credit_out' => {
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'type' => 'output',
'intfc_port' => 'credit_out'
},
'ni_flit_out' => {
'type' => 'output',
'range' => 'ni_Fw-1 : 0',
'intfc_port' => 'flit_out',
'instance_name' => 'ni_master0'
},
'ni_credit_in' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'credit_in',
'type' => 'input',
'range' => 'ni_V-1 : 0'
}
}
},
'socket:RxD_sim[0]' => {
'ports' => {
'uart_RxD_ready_sim' => {
'type' => 'output',
'range' => '',
'intfc_port' => 'RxD_ready_sim',
'instance_name' => 'jtag_uart0'
},
'uart_RxD_din_sim' => {
'range' => '7:0 ',
'type' => 'input',
'intfc_port' => 'RxD_din_sim',
'instance_name' => 'jtag_uart0'
},
'uart_RxD_wr_sim' => {
'range' => '',
'type' => 'input',
'intfc_port' => 'RxD_wr_sim',
'instance_name' => 'jtag_uart0'
}
}
},
'plug:enable[0]' => {
'ports' => {
'cpu_sys_ena_i' => {
'instance_name' => 'aeMB0',
'intfc_port' => 'enable_i',
'range' => '',
'type' => 'input'
}
}
}
},
'instance_ids' => {
'clk_source0' => {
'instance' => 'ss',
'module' => 'clk_source',
'module_name' => 'clk_source',
'category' => 'Source',
'ports' => {
'ss_reset_in' => {
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:reset[0]',
'intfc_port' => 'reset_i'
},
'ss_clk_in' => {
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i'
}
}
},
'ni_master0' => {
'instance' => 'ni',
'module' => 'ni_master',
'module_name' => 'ni_master',
'localparam' => {
'ni_SRC_ADR_HDR_WIDTH' => {
'info' => 'Parameter',
'default' => '8',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ni_M_Aw' => {
'content' => 'Dw',
'info' => 'Parameter',
'default' => '32',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ni_TAGw' => {
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'default' => '3',
'info' => 'Parameter'
},
'ni_Xw' => {
'global_param' => 'Localparam',
'redefine_param' => 0,
'type' => 'Fixed',
'default' => 'log2(ni_NX)',
'info' => undef,
'content' => ''
},
'ni_SELw' => {
'info' => 'Parameter',
'default' => '4',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_Fw' => {
'default' => '2+ni_V+ni_Fpay',
'info' => undef,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 0
},
'ni_MAX_BURST_SIZE' => {
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
'default' => '16',
'content' => '2,4,8,16,32,64,128,256,512,1024,2048'
},
'ni_Dw' => {
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '32,256,8',
'info' => 'wishbone_bus data width in bits.',
'default' => '32'
},
'ni_CLASS_HDR_WIDTH' => {
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => 'Parameter',
'default' => '8'
},
'ni_MAX_TRANSACTION_WIDTH' => {
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
'default' => '13',
'content' => '4,32,1',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ni_ROUTING_HDR_WIDTH' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '8',
'info' => 'Parameter',
'content' => ''
},
'ni_Yw' => {
'global_param' => 'Localparam',
'redefine_param' => 0,
'type' => 'Fixed',
'info' => undef,
'default' => 'log2(ni_NY)',
'content' => ''
},
'ni_CRC_EN' => {
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"YES","NO"',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'default' => '"NO"'
},
'ni_DST_ADR_HDR_WIDTH' => {
'info' => 'Parameter',
'default' => '8',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_S_Aw' => {
'info' => 'Parameter',
'default' => '8',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1
}
},
'parameters' => {
'ni_DEBUG_EN' => {
'info' => 'Parameter',
'default' => '1',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'ni_ROUTE_NAME' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'default' => '"XY"',
'info' => 'Parameter',
'content' => ''
},
'ni_C' => {
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter',
'content' => '',
'default' => 2,
'info' => 'Parameter'
},
'ni_V' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '2',
'info' => 'Parameter',
'content' => ''
},
'ni_Fpay' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'default' => '32',
'info' => 'Parameter',
'content' => ''
},
'ni_TOPOLOGY' => {
'content' => '',
'default' => '"MESH"',
'info' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ni_NY' => {
'info' => 'Parameter',
'default' => ' 2',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'ni_NX' => {
'content' => '',
'info' => 'Parameter',
'default' => 2,
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ni_B' => {
'content' => '',
'default' => '4',
'info' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter'
}
},
'category' => 'NoC',
'ports' => {
'ni_flit_in' => {
'type' => 'input',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'output'
},
'ni_flit_out' => {
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'output',
'intfc_port' => 'flit_out'
},
'ni_credit_out' => {
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'output',
'intfc_port' => 'credit_out'
},
'ni_credit_in' => {
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'credit_in'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'range' => 'ni_Xw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input'
},
'ni_flit_in_wr' => {
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'intfc_port' => 'flit_in_wr'
},
'ni_irq' => {
'intfc_port' => 'int_o',
'type' => 'output',
'range' => '',
'intfc_name' => 'plug:interrupt_peripheral[0]'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Yw-1 : 0'
}
}
},
'wishbone_bus0' => {
'module_name' => 'wishbone_bus',
'localparam' => {
'bus_BTEw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => undef,
'default' => '2 ',
'content' => ''
},
'bus_Aw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Spin-button',
'default' => '32',
'info' => 'The wishbone Bus address width',
'content' => '4,128,1'
},
'bus_TAGw' => {
'default' => '3',
'info' => undef,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'bus_SELw' => {
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => undef,
'default' => 'bus_Dw/8'
},
'bus_Dw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button',
'content' => '8,512,8',
'info' => 'The wishbone Bus data width in bits.',
'default' => '32'
},
'bus_S' => {
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '1,256,1',
'info' => 'Number of wishbone slave interface',
'default' => 3
},
'bus_CTIw' => {
'content' => '',
'info' => undef,
'default' => '3',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'bus_M' => {
'info' => 'Number of wishbone master interface',
'default' => ' 4',
'content' => '1,256,1',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Spin-button'
}
},
'module' => 'wishbone_bus',
'instance' => 'bus',
'category' => 'Bus'
},
'single_port_ram0' => {
'localparam' => {
'ram_MEM_CONTENT_FILE_NAME' => {
'content' => '',
'default' => '"ram0"',
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
bin: raw binary format . It will be used by JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Entry'
},
'ram_BURST_MODE' => {
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'default' => '"ENABLED"',
'content' => '"DISABLED","ENABLED"'
},
'ram_FPGA_VENDOR' => {
'content' => '"ALTERA","GENERIC"',
'default' => '"ALTERA"',
'info' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Combo-box'
},
'ram_SELw' => {
'default' => 'ram_Dw/8',
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ram_CTIw' => {
'content' => '',
'info' => 'Parameter',
'default' => '3',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ram_TAGw' => {
'default' => '3',
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ram_BYTE_WR_EN' => {
'content' => '"YES","NO"',
'default' => '"YES"',
'info' => 'Byte enable',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_INIT_FILE_PATH' => {
'content' => '',
'default' => 'SW_LOC',
'info' => undef,
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_JTAG_INDEX' => {
'content' => '',
'default' => 'CORE_ID',
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Entry'
},
'ram_BTEw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '2',
'info' => 'Parameter',
'content' => ''
},
'ram_JTAG_CONNECT' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Combo-box',
'content' => '"DISABLED", "JTAG_WB" , "ALTERA_IMCE"',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
'default' => '"DISABLED"'
},
'ram_INITIAL_EN' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Combo-box',
'default' => '"YES"',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
'content' => '"YES","NO"'
}
},
'module_name' => 'wb_single_port_ram',
'instance' => 'ram',
'module' => 'single_port_ram',
'category' => 'RAM',
'parameters' => {
'ram_Dw' => {
'type' => 'Spin-button',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => 'Memory data width in Bits.',
'default' => '32',
'content' => '8,1024,1'
},
'ram_Aw' => {
'content' => '4,31,1',
'info' => 'Memory address width',
'default' => 14,
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Spin-button'
}
}
},
'jtag_uart0' => {
'module' => 'jtag_uart',
'instance' => 'uart',
'localparam' => {
'uart_SIM_BUFFER_SIZE' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button',
'content' => '10,10000,1',
'default' => '100',
'info' => 'Internal buffer size.
This parameter is valid only in simulation.
If internal buffer overflows, the buffer content are displayed on simulator terminal.'
},
'uart_FPGA_VENDOR' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Combo-box',
'content' => ' "ALTERA"',
'info' => 'FPGA VENDOR name. Only Altera FPGA is supported. Currently the Generic serial port is not supported. ',
'default' => ' "ALTERA"'
},
'uart_SIM_WAIT_COUNT' => {
'default' => '1000',
'info' => 'This parameter is valid only in simulation.
If internal buffer has a data, the internal timer incremented by one in each clock cycle. If the timer reaches the WAIT_COUNT value, it writes the buffer value on the simulator terminal.',
'content' => '2,100000,1',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Spin-button'
}
},
'module_name' => 'jtag_uart_wb',
'category' => 'Communication',
'ports' => {
'uart_RxD_wr_sim' => {
'intfc_port' => 'RxD_wr_sim',
'range' => '',
'intfc_name' => 'socket:RxD_sim[0]',
'type' => 'input'
},
'uart_RxD_din_sim' => {
'type' => 'input',
'range' => '7:0 ',
'intfc_name' => 'socket:RxD_sim[0]',
'intfc_port' => 'RxD_din_sim'
},
'uart_irq' => {
'intfc_port' => 'int_o',
'range' => '',
'intfc_name' => 'plug:interrupt_peripheral[0]',
'type' => 'output'
},
'uart_RxD_ready_sim' => {
'intfc_port' => 'RxD_ready_sim',
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '',
'type' => 'output'
}
}
},
'aeMB0' => {
'localparam' => {
'cpu_AEMB_IDX' => {
'default' => ' 6',
'info' => undef,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'cpu_AEMB_BSF' => {
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => undef,
'default' => ' 1'
},
'cpu_AEMB_XWB' => {
'default' => ' 7',
'info' => undef,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'cpu_AEMB_DWB' => {
'info' => undef,
'default' => ' 32',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'cpu_AEMB_ICH' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'info' => undef,
'default' => ' 11'
},
'cpu_AEMB_IWB' => {
'content' => '',
'info' => undef,
'default' => ' 32',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'cpu_AEMB_MUL' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'info' => undef,
'default' => ' 1',
'content' => ''
}
},
'module_name' => 'aeMB_top',
'instance' => 'cpu',
'module' => 'aeMB',
'ports' => {
'cpu_sys_ena_i' => {
'type' => 'input',
'intfc_name' => 'plug:enable[0]',
'range' => '',
'intfc_port' => 'enable_i'
},
'cpu_sys_int_i' => {
'range' => '',
'intfc_name' => 'socket:interrupt_cpu[0]',
'type' => 'input',
'intfc_port' => 'int_i'
}
},
'category' => 'Processor'
}
}
}, 'ip_gen' )
},
'ni_slave_single_buffer' => {
'top' => bless( {
'instance_ids' => {
'ni_master0' => {
'parameters' => {
'ni_TOPOLOGY' => {
'content' => '',
'info' => 'Parameter',
'default' => '"MESH"',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_B' => {
'info' => 'Parameter',
'default' => ' 4',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'ni_NY' => {
'content' => '',
'default' => ' 4',
'info' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ni_NX' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'default' => ' 4',
'info' => 'Parameter'
},
'ni_C' => {
'content' => '',
'default' => ' 4',
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_Fpay' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'default' => ' 32',
'info' => 'Parameter'
},
'ni_V' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '4',
'info' => 'Parameter',
'content' => ''
},
'ni_DEBUG_EN' => {
'info' => 'Parameter',
'default' => ' 1',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_ROUTE_NAME' => {
'info' => 'Parameter',
'default' => '"XY" ',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed'
}
},
'ports' => {
'ni_flit_in' => {
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'intfc_port' => 'flit_in'
},
'ni_reset' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:reset[0]'
},
'ni_credit_in' => {
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'intfc_port' => 'credit_in'
},
'ni_flit_out' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'output',
'intfc_port' => 'flit_out'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'type' => 'output',
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'intfc_name' => 'socket:ni[0]',
'range' => ''
},
'ni_clk' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'type' => 'input',
'range' => 'ni_Xw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_current_y' => {
'range' => 'ni_Yw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'current_y'
},
'ni_irq' => {
'range' => '',
'intfc_name' => 'plug:interrupt_peripheral[0]',
'type' => 'output',
'intfc_port' => 'int_o'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'type' => 'input',
'range' => '',
'intfc_name' => 'socket:ni[0]'
}
},
'category' => 'NoC',
'module_name' => 'ni_master',
'localparam' => {
'ni_SELw' => {
'content' => '',
'default' => '4',
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ni_TAGw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '3',
'info' => 'Parameter',
'content' => ''
},
'ni_Xw' => {
'default' => 'log2(ni_NX)',
'info' => undef,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 0
},
'ni_Fw' => {
'default' => '2+ni_V+ni_Fpay',
'info' => undef,
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 0,
'type' => 'Fixed'
},
'ni_M_Aw' => {
'info' => 'Parameter',
'default' => '32',
'content' => 'Dw',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ni_SRC_ADR_HDR_WIDTH' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '8',
'info' => 'Parameter',
'content' => ''
},
'ni_Yw' => {
'info' => undef,
'default' => 'log2(ni_NY)',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 0
},
'ni_CLASS_HDR_WIDTH' => {
'content' => '',
'default' => '8',
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ni_Dw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Spin-button',
'default' => '32',
'info' => 'wishbone_bus data width in bits.',
'content' => '32,256,8'
},
'ni_MAX_BURST_SIZE' => {
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '16',
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
'content' => '2,4,8,16,32,64,128,256,512,1024,2048'
},
'ni_ROUTING_HDR_WIDTH' => {
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => 'Parameter',
'default' => '8'
},
'ni_MAX_TRANSACTION_WIDTH' => {
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '4,32,1',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
'default' => '13'
},
'ni_CRC_EN' => {
'content' => '"YES","NO"',
'default' => '"NO"',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Combo-box'
},
'ni_DST_ADR_HDR_WIDTH' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '8',
'info' => 'Parameter',
'content' => ''
},
'ni_S_Aw' => {
'content' => '',
'default' => '8',
'info' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
}
},
'instance' => 'ni',
'module' => 'ni_master'
},
'dual_port_ram0' => {
'ports' => {
'ram_sb_addr_i' => {
'type' => 'input',
'intfc_name' => 'plug:wb_slave[1]',
'range' => 'ram_Aw-1 : 0',
'intfc_port' => 'adr_i'
},
'ram_sb_err_o' => {
'intfc_name' => 'plug:wb_slave[1]',
'range' => '',
'type' => 'output',
'intfc_port' => 'err_o'
},
'ram_sb_stb_i' => {
'range' => '',
'intfc_name' => 'plug:wb_slave[1]',
'type' => 'input',
'intfc_port' => 'stb_i'
},
'ram_sb_rty_o' => {
'intfc_port' => 'rty_o',
'range' => '',
'intfc_name' => 'plug:wb_slave[1]',
'type' => 'output'
},
'ram_reset' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
},
'ram_sb_cti_i' => {
'intfc_port' => 'cti_i',
'type' => 'input',
'range' => 'ram_CTIw-1 : 0',
'intfc_name' => 'plug:wb_slave[1]'
},
'ram_sb_tag_i' => {
'range' => 'ram_TAGw-1 : 0',
'intfc_name' => 'plug:wb_slave[1]',
'type' => 'input',
'intfc_port' => 'tag_i'
},
'ram_sb_dat_i' => {
'intfc_port' => 'dat_i',
'range' => 'ram_Dw-1 : 0',
'intfc_name' => 'plug:wb_slave[1]',
'type' => 'input'
},
'ram_sb_bte_i' => {
'type' => 'input',
'intfc_name' => 'plug:wb_slave[1]',
'range' => 'ram_BTEw-1 : 0',
'intfc_port' => 'bte_i'
},
'ram_clk' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input'
},
'ram_sb_sel_i' => {
'intfc_port' => 'sel_i',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[1]',
'range' => 'ram_SELw-1 : 0'
},
'ram_sb_ack_o' => {
'intfc_port' => 'ack_o',
'type' => 'output',
'intfc_name' => 'plug:wb_slave[1]',
'range' => ''
},
'ram_sb_dat_o' => {
'range' => 'ram_Dw-1 : 0',
'intfc_name' => 'plug:wb_slave[1]',
'type' => 'output',
'intfc_port' => 'dat_o'
},
'ram_sb_we_i' => {
'type' => 'input',
'intfc_name' => 'plug:wb_slave[1]',
'range' => '',
'intfc_port' => 'we_i'
},
'ram_sb_cyc_i' => {
'intfc_name' => 'plug:wb_slave[1]',
'range' => '',
'type' => 'input',
'intfc_port' => 'cyc_i'
}
},
'category' => 'RAM',
'module_name' => 'wb_dual_port_ram',
'localparam' => {
'ram_FPGA_VENDOR' => {
'content' => '"ALTERA","GENERIC"',
'default' => '"GENERIC"',
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Combo-box'
},
'ram_Aw' => {
'content' => '2,31,1',
'default' => '12',
'info' => 'Ram address width',
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_PORT_B_BURST_MODE' => {
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => 'wisbone bus burst mode ebable/disable on port B',
'default' => '"ENABLED"',
'content' => '"DISABLED","ENABLED"'
},
'ram_SELw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'info' => 'Parameter',
'default' => 'ram_Dw/8'
},
'ram_MEM_CONTENT_FILE_NAME' => {
'type' => 'Entry',
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'default' => '"ram0"',
'content' => ''
},
'ram_PORT_A_BURST_MODE' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Combo-box',
'info' => ' wisbone bus burst mode enable/disable on port A',
'default' => '"ENABLED"',
'content' => '"DISABLED","ENABLED"'
},
'ram_Dw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Spin-button',
'info' => 'Ram data width in Bits',
'default' => '32',
'content' => '4,1024,1'
},
'ram_BTEw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '2',
'content' => ''
},
'ram_INITIAL_EN' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Combo-box',
'content' => '"YES","NO"',
'default' => '"NO"',
'info' => 'If selected as "YES", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.'
},
'ram_RAM_INDEX' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Entry',
'default' => 'CORE_ID',
'info' => 'RAM_INDEX is a unique number which will be used for initialing the memory content only.
 
',
'content' => ''
},
'ram_TAGw' => {
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => 'Parameter',
'default' => '3'
},
'ram_CTIw' => {
'content' => '',
'default' => '3',
'info' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_BYTE_WR_EN' => {
'content' => '"YES","NO"',
'info' => 'Parameter',
'default' => '"YES"',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam'
}
},
'module' => 'dual_port_ram',
'instance' => 'ram'
},
'wishbone_bus0' => {
'category' => 'Bus',
'ports' => {
'bus_clk' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input'
},
'bus_reset' => {
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:reset[0]',
'intfc_port' => 'reset_i'
},
'bus_snoop_en_o' => {
'type' => 'output',
'range' => '',
'intfc_name' => 'socket:snoop[0]',
'intfc_port' => 'snoop_en_o'
},
'bus_snoop_adr_o' => {
'intfc_port' => 'snoop_adr_o',
'type' => 'output',
'range' => 'bus_Aw-1 : 0',
'intfc_name' => 'socket:snoop[0]'
}
},
'module' => 'wishbone_bus',
'instance' => 'bus',
'module_name' => 'wishbone_bus',
'localparam' => {
'bus_SELw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'info' => undef,
'default' => 'bus_Dw/8'
},
'bus_S' => {
'default' => 2,
'info' => 'Number of wishbone slave interface',
'content' => '1,256,1',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'bus_Dw' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '32',
'info' => 'The wishbone Bus data width in bits.',
'content' => '8,512,8'
},
'bus_BTEw' => {
'default' => '2 ',
'info' => undef,
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed'
},
'bus_Aw' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => 'The wishbone Bus address width',
'default' => '32',
'content' => '4,128,1'
},
'bus_TAGw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => undef,
'default' => '3',
'content' => ''
},
'bus_M' => {
'content' => '1,256,1',
'info' => 'Number of wishbone master interface',
'default' => 2,
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button'
},
'bus_CTIw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'default' => '3',
'info' => undef
}
}
}
},
'interface' => {
'plug:clk[0]' => {
'ports' => {
'ram_clk' => {
'instance_name' => 'dual_port_ram0',
'intfc_port' => 'clk_i',
'range' => '',
'type' => 'input'
},
'ni_clk' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'clk_i',
'type' => 'input',
'range' => ''
},
'bus_clk' => {
'type' => 'input',
'range' => '',
'intfc_port' => 'clk_i',
'instance_name' => 'wishbone_bus0'
}
}
},
'plug:reset[0]' => {
'ports' => {
'ni_reset' => {
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i',
'instance_name' => 'ni_master0'
},
'bus_reset' => {
'instance_name' => 'wishbone_bus0',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
},
'ram_reset' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'range' => '',
'instance_name' => 'dual_port_ram0'
}
}
},
'plug:wb_slave[1]' => {
'ports' => {
'ram_sb_tag_i' => {
'intfc_port' => 'tag_i',
'type' => 'input',
'range' => 'ram_TAGw-1 : 0',
'instance_name' => 'dual_port_ram0'
},
'ram_sb_dat_i' => {
'instance_name' => 'dual_port_ram0',
'intfc_port' => 'dat_i',
'type' => 'input',
'range' => 'ram_Dw-1 : 0'
},
'ram_sb_bte_i' => {
'intfc_port' => 'bte_i',
'type' => 'input',
'range' => 'ram_BTEw-1 : 0',
'instance_name' => 'dual_port_ram0'
},
'ram_sb_addr_i' => {
'intfc_port' => 'adr_i',
'range' => 'ram_Aw-1 : 0',
'type' => 'input',
'instance_name' => 'dual_port_ram0'
},
'ram_sb_err_o' => {
'instance_name' => 'dual_port_ram0',
'intfc_port' => 'err_o',
'range' => '',
'type' => 'output'
},
'ram_sb_stb_i' => {
'instance_name' => 'dual_port_ram0',
'intfc_port' => 'stb_i',
'range' => '',
'type' => 'input'
},
'ram_sb_rty_o' => {
'type' => 'output',
'range' => '',
'intfc_port' => 'rty_o',
'instance_name' => 'dual_port_ram0'
},
'ram_sb_cti_i' => {
'instance_name' => 'dual_port_ram0',
'intfc_port' => 'cti_i',
'range' => 'ram_CTIw-1 : 0',
'type' => 'input'
},
'ram_sb_we_i' => {
'instance_name' => 'dual_port_ram0',
'intfc_port' => 'we_i',
'range' => '',
'type' => 'input'
},
'ram_sb_cyc_i' => {
'instance_name' => 'dual_port_ram0',
'type' => 'input',
'range' => '',
'intfc_port' => 'cyc_i'
},
'ram_sb_sel_i' => {
'instance_name' => 'dual_port_ram0',
'intfc_port' => 'sel_i',
'type' => 'input',
'range' => 'ram_SELw-1 : 0'
},
'ram_sb_ack_o' => {
'range' => '',
'type' => 'output',
'intfc_port' => 'ack_o',
'instance_name' => 'dual_port_ram0'
},
'ram_sb_dat_o' => {
'instance_name' => 'dual_port_ram0',
'intfc_port' => 'dat_o',
'range' => 'ram_Dw-1 : 0',
'type' => 'output'
}
}
},
'socket:snoop[0]' => {
'ports' => {
'bus_snoop_en_o' => {
'range' => '',
'type' => 'output',
'intfc_port' => 'snoop_en_o',
'instance_name' => 'wishbone_bus0'
},
'bus_snoop_adr_o' => {
'instance_name' => 'wishbone_bus0',
'intfc_port' => 'snoop_adr_o',
'range' => 'bus_Aw-1 : 0',
'type' => 'output'
}
}
},
'plug:interrupt_peripheral[0]' => {
'ports' => {
'ni_irq' => {
'instance_name' => 'ni_master0',
'type' => 'output',
'range' => '',
'intfc_port' => 'int_o'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_credit_in' => {
'instance_name' => 'ni_master0',
'type' => 'input',
'range' => 'ni_V-1 : 0',
'intfc_port' => 'credit_in'
},
'ni_flit_out' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'flit_out',
'range' => 'ni_Fw-1 : 0',
'type' => 'output'
},
'ni_credit_out' => {
'range' => 'ni_V-1 : 0',
'type' => 'output',
'intfc_port' => 'credit_out',
'instance_name' => 'ni_master0'
},
'ni_flit_out_wr' => {
'instance_name' => 'ni_master0',
'type' => 'output',
'range' => '',
'intfc_port' => 'flit_out_wr'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'type' => 'input',
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0'
},
'ni_current_y' => {
'type' => 'input',
'range' => 'ni_Yw-1 : 0',
'intfc_port' => 'current_y',
'instance_name' => 'ni_master0'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'range' => '',
'type' => 'input',
'instance_name' => 'ni_master0'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'type' => 'input',
'range' => 'ni_Xw-1 : 0',
'instance_name' => 'ni_master0'
}
}
}
},
'ports' => {
'ni_flit_out_wr' => {
'range' => '',
'intfc_name' => 'socket:ni[0]',
'type' => 'output',
'intfc_port' => 'flit_out_wr',
'instance_name' => 'ni_master0'
},
'bus_snoop_adr_o' => {
'intfc_port' => 'snoop_adr_o',
'type' => 'output',
'range' => 'bus_Aw-1 : 0',
'intfc_name' => 'socket:snoop[0]',
'instance_name' => 'wishbone_bus0'
},
'ram_sb_bte_i' => {
'instance_name' => 'dual_port_ram0',
'intfc_port' => 'bte_i',
'type' => 'input',
'range' => 'ram_BTEw-1 : 0',
'intfc_name' => 'plug:wb_slave[1]'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'input',
'instance_name' => 'ni_master0'
},
'ram_clk' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input',
'instance_name' => 'dual_port_ram0'
},
'ram_sb_dat_i' => {
'instance_name' => 'dual_port_ram0',
'intfc_port' => 'dat_i',
'intfc_name' => 'plug:wb_slave[1]',
'range' => 'ram_Dw-1 : 0',
'type' => 'input'
},
'ram_sb_stb_i' => {
'intfc_port' => 'stb_i',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[1]',
'range' => '',
'instance_name' => 'dual_port_ram0'
},
'ni_reset' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'reset_i',
'type' => 'input',
'intfc_name' => 'plug:reset[0]',
'range' => ''
},
'bus_reset' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'instance_name' => 'wishbone_bus0'
},
'ram_sb_addr_i' => {
'intfc_port' => 'adr_i',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[1]',
'range' => 'ram_Aw-1 : 0',
'instance_name' => 'dual_port_ram0'
},
'ram_sb_cti_i' => {
'instance_name' => 'dual_port_ram0',
'intfc_name' => 'plug:wb_slave[1]',
'range' => 'ram_CTIw-1 : 0',
'type' => 'input',
'intfc_port' => 'cti_i'
},
'ram_reset' => {
'instance_name' => 'dual_port_ram0',
'intfc_port' => 'reset_i',
'range' => '',
'intfc_name' => 'plug:reset[0]',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'instance_name' => 'ni_master0'
},
'ram_sb_we_i' => {
'instance_name' => 'dual_port_ram0',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'we_i'
},
'ni_current_y' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Yw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_y',
'instance_name' => 'ni_master0'
},
'ni_irq' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'int_o',
'range' => '',
'intfc_name' => 'plug:interrupt_peripheral[0]',
'type' => 'output'
},
'ram_sb_dat_o' => {
'intfc_port' => 'dat_o',
'intfc_name' => 'plug:wb_slave[1]',
'range' => 'ram_Dw-1 : 0',
'type' => 'output',
'instance_name' => 'dual_port_ram0'
},
'bus_clk' => {
'instance_name' => 'wishbone_bus0',
'intfc_port' => 'clk_i',
'range' => '',
'intfc_name' => 'plug:clk[0]',
'type' => 'input'
},
'ram_sb_ack_o' => {
'intfc_port' => 'ack_o',
'range' => '',
'intfc_name' => 'plug:wb_slave[1]',
'type' => 'output',
'instance_name' => 'dual_port_ram0'
},
'ram_sb_tag_i' => {
'instance_name' => 'dual_port_ram0',
'intfc_port' => 'tag_i',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[1]',
'range' => 'ram_TAGw-1 : 0'
},
'bus_snoop_en_o' => {
'range' => '',
'intfc_name' => 'socket:snoop[0]',
'type' => 'output',
'intfc_port' => 'snoop_en_o',
'instance_name' => 'wishbone_bus0'
},
'ni_credit_out' => {
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'output',
'intfc_port' => 'credit_out'
},
'ni_flit_out' => {
'type' => 'output',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'intfc_port' => 'flit_out',
'instance_name' => 'ni_master0'
},
'ram_sb_rty_o' => {
'range' => '',
'intfc_name' => 'plug:wb_slave[1]',
'type' => 'output',
'intfc_port' => 'rty_o',
'instance_name' => 'dual_port_ram0'
},
'ram_sb_err_o' => {
'intfc_port' => 'err_o',
'type' => 'output',
'intfc_name' => 'plug:wb_slave[1]',
'range' => '',
'instance_name' => 'dual_port_ram0'
},
'ni_flit_in_wr' => {
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'flit_in_wr',
'instance_name' => 'ni_master0'
},
'ram_sb_cyc_i' => {
'intfc_port' => 'cyc_i',
'range' => '',
'intfc_name' => 'plug:wb_slave[1]',
'type' => 'input',
'instance_name' => 'dual_port_ram0'
},
'ram_sb_sel_i' => {
'intfc_port' => 'sel_i',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[1]',
'range' => 'ram_SELw-1 : 0',
'instance_name' => 'dual_port_ram0'
},
'ni_current_x' => {
'type' => 'input',
'range' => 'ni_Xw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_x',
'instance_name' => 'ni_master0'
},
'ni_clk' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'clk_i',
'instance_name' => 'ni_master0'
}
}
}, 'ip_gen' )
}
},
'noc_type' => {
'ROUTER_TYPE' => '"VC_BASED"'
},
'compile' => {
'modelsim_bin' => '/home/alireza/altera/modeltech/bin',
'board' => 'DE2_115',
'compilers' => 'QuartusII,Verilator,Modelsim',
'type' => 'Modelsim',
'quartus_bin' => '/home/alireza/intelFPGA_lite/17.1/quartus/bin'
},
'top_ip' => bless( {
'interface' => {
'plug:enable[0]' => {
'ports' => {
'processors_en' => {
'intfc_port' => 'enable_i',
'range' => '',
'type' => 'input',
'instance_name' => 'IO'
}
}
},
'plug:clk[0]' => {
'ports' => {
'clk' => {
'range' => '',
'type' => 'input',
'intfc_port' => 'clk_i',
'instance_name' => 'IO'
}
}
},
'plug:reset[0]' => {
'ports' => {
'reset' => {
'instance_name' => 'IO',
'intfc_port' => 'reset_i',
'type' => 'input',
'range' => ''
}
}
}
},
'instance_ids' => {
'IO' => {
'ports' => {
'reset' => {
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:reset[0]',
'intfc_port' => 'reset_i'
},
'processors_en' => {
'range' => '',
'intfc_name' => 'plug:enable[0]',
'type' => 'input',
'intfc_port' => 'enable_i'
},
'clk' => {
'range' => '',
'intfc_name' => 'plug:clk[0]',
'type' => 'input',
'intfc_port' => 'clk_i'
}
}
}
},
'ports' => {
'clk' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:clk[0]',
'instance_name' => 'IO'
},
'processors_en' => {
'instance_name' => 'IO',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:enable[0]',
'intfc_port' => 'enable_i'
},
'reset' => {
'instance_name' => 'IO',
'intfc_port' => 'reset_i',
'type' => 'input',
'intfc_name' => 'plug:reset[0]',
'range' => ''
}
}
}, 'ip_gen' ),
'compile_pin_range_lsb' => {
'reset' => '0'
},
'verilator' => {
'libs' => {
'Vrouter' => 'router_verilator.v',
'Vtile2' => 'tile_2.v',
'Vnoc' => 'noc_connection.sv',
'Vtile3' => 'tile_3.v',
'Vtile0' => 'tile_0.v',
'Vtile1' => 'tile_1.v'
}
},
'compile_pin_range_hsb' => {},
'compile_pin_pos' => {
'clk' => [
4,
0
],
'processors_en' => [
2,
0
],
'reset' => [
13,
0
]
},
'compile_pin' => {
'processors_en' => '*VCC',
'reset' => 'KEY',
'clk' => 'CLOCK_50'
},
'parameters_order' => {
'class_param' => [
'Cn_0',
'Cn_1'
],
'noc_param' => [
'TOPOLOGY',
'NX',
'NY',
'V',
'B',
'Fpay',
'ROUTE_NAME',
'SSA_EN',
'CONGESTION_INDEX',
'ESCAP_VC_MASK',
'VC_REALLOCATION_TYPE',
'COMBINATION_TYPE',
'MUX_TYPE',
'C',
'DEBUG_EN',
'ADD_PIPREG_AFTER_CROSSBAR',
'FIRST_ARBITER_EXT_P_EN',
'SWA_ARBITER_TYPE',
'WEIGHTw',
'AVC_ATOMIC_EN',
'ROUTE_SUBFUNC'
],
'noc_type' => [
'ROUTER_TYPE'
]
},
'setting' => {
'show_tile_setting' => 1,
'soc_path' => 'lib/soc',
'show_adv_setting' => 1,
'show_noc_setting' => 0
},
'compile_assign_type' => {
'reset' => 'Negate(~)',
'processors_en' => 'Direct',
'clk' => 'Direct'
},
'noc_param' => {
'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
'DEBUG_EN' => '1',
'Fpay' => '32',
'ROUTE_NAME' => '"XY"',
'FIRST_ARBITER_EXT_P_EN' => 1,
'V' => '2',
'SSA_EN' => '"NO"',
'C' => 2,
'WEIGHTw' => '4',
'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
'CONGESTION_INDEX' => 3,
'COMBINATION_TYPE' => '"COMB_NONSPEC"',
'TOPOLOGY' => '"MESH"',
'MUX_TYPE' => '"BINARY"',
'ESCAP_VC_MASK' => '2\'b01',
'NX' => 2,
'NY' => ' 2',
'ROUTE_SUBFUNC' => '"XY"',
'AVC_ATOMIC_EN' => 0,
'SWA_ARBITER_TYPE' => '"RRA"',
'B' => '4'
}
}, 'mpsoc' );
/mpsoc/perl_gui/lib/perl/compile.pl
764,9 → 764,25
 
my $board_name=$self->object_get_attribute('compile','board');
#copy board jtag_intfc.sh file
my ($fname,$fpath,$fsuffix) = fileparse("$top",qr"\..[^.]*$");
copy("../boards/$board_name/jtag_intfc.sh","${fpath}../sw/jtag_intfc.sh");
copy("../boards/$board_name/jtag_intfc.sh","${fpath}../sw/jtag_intfc.sh");
my $n= $self->object_get_attribute('soc_name',undef);
if(!defined $n){ # we are compiling a complete NoC-based mpsoc
my $nx= $self->object_get_attribute('noc_param',"NX");
my $ny= $self->object_get_attribute('noc_param',"NY");
for (my $y=0;$y<$ny;$y++){for (my $x=0; $x<$nx;$x++){
my $tile_num= $y*$nx+$x;
#print "$tile_num\n";
my ($soc_name,$num)= $self->mpsoc_get_tile_soc_name($tile_num);
next if(!defined $soc_name);
copy("../boards/$board_name/jtag_intfc.sh","${fpath}../sw/tile$tile_num/jtag_intfc.sh");
}}
}
 
#copy board program_device.sh file
copy("../boards/$board_name/program_device.sh","${fpath}../program_device.sh");
818,11 → 834,13
if (length($portrange)!=0){
#replace parameter with their values
my @a= split (/\b/,$portrange);
foreach my $l (@a){
my $value=$param{$l};
if(defined $value){
chomp $value;
($portrange=$portrange)=~ s/\b$l\b/$value/g if(defined $param{$l});
# print"($portrange=$portrange)=~ s/\b$l\b/$value/g if(defined $param{$l})\n";
}
}
$portrange = "[ $portrange ]" ;
1149,6 → 1167,7
add_info(\$tview,"creat Modelsim dir in $target_dir\n");
my $model="$target_dir/Modelsim";
rmtree("$model");
rmtree("$target_dir/rtl_work");
mkpath("$model/rtl_work",1,01777);
#create modelsim.tcl file
1193,6 → 1212,7
$app->do_save();
my $modelsim_bin= $self->object_get_attribute('compile','modelsim_bin');
my $cmd="cd $target_dir; $modelsim_bin/vsim -do $model/run.tcl";
add_info(\$tview,"$cmd\n");
my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
if(length $stderr>1){
1228,7 → 1248,7
add_info(\$outtext,"Copy all verilog files in rtl_work folder\n");
my @files = File::Find::Rule->file()
->name( '*.v','*.V','*.sv','*.vh')
->in( "$target_dir/src_verilog" );
->in( "$target_dir/src_verilog","$target_dir/src_verilator" );
foreach my $file (@files) {
copy($file,"$verilator/rtl_work/");
}
1235,7 → 1255,7
@files = File::Find::Rule->file()
->name( '*.sv','*.vh' )
->in( "$target_dir/src_verilog" );
->in( "$target_dir/src_verilog","$target_dir/src_verilator" );
foreach my $file (@files) {
copy($file,"$verilator/processed_rtl");
}
1253,12 → 1273,13
$split->write_files();
$split->read_and_split(glob("$verilator/rtl_work/*.sv"));
$split->write_files();
#run verilator
#my $cmd= "cd \"$verilator/processed_rtl\" \n xterm -e sh -c ' verilator --cc $name.v --profile-cfuncs --prefix \"Vtop\" -O3 -CFLAGS -O3'";
foreach my $top (sort keys %tops) {
my $cmd= "cd \"$verilator/processed_rtl\" \n verilator --cc $tops{$top} --profile-cfuncs --prefix \"$top\" -O3 -CFLAGS -O3";
add_colored_info(\$outtext,"Generate $top Verilator model from $tops{$top} file\n",'green');
my $cmd= "cd \"$verilator/processed_rtl\" \n verilator --cc $tops{$top} --prefix \"$top\" -O3 -CFLAGS -O3";
add_info(\$outtext,"$cmd\n");
my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
if(length $stderr>1){
1272,13 → 1293,14
#check if verilator model has been generated
foreach my $top (sort keys %tops) {
if (-f "$verilator/processed_rtl/obj_dir/$top.cpp"){#succsess
#generate makefile
gen_verilator_makefile($top_ref,"$verilator/processed_rtl/obj_dir/Makefile");
}else {
return 0;
}
}
#generate makefile
gen_verilator_makefile($top_ref,"$verilator/processed_rtl/obj_dir/Makefile");
return 1;
}
 
1290,11 → 1312,15
my $q='';
my $h='';
my $l;
my $lib_num=0;
my $all_lib="";
foreach my $top (sort keys %tops) {
$p = "$p ${top}__ALL.a ";
$q = "$q\t\$(MAKE) -f ${top}.mk\n";
$q = $q."lib$lib_num:\n\t\$(MAKE) -f ${top}.mk\n";
$h = "$h ${top}.h ";
$l = $top;
$all_lib=$all_lib." lib$lib_num";
$lib_num++;
}
1306,7 → 1332,8
 
include $l.mk
 
lib:
lib: $all_lib
 
$q
 
 
1329,7 → 1356,7
testbench.o: testbench.cpp $h
 
clean:
rm *.o *.a main
rm *.o *.a testbench
";
 
 
1371,9 → 1398,27
verilator_testbench($self,$name,$top,$target_dir);
});
my %tops;
$tops{"Vtop"}= "$name.v";
my $result = verilator_compilation (\%tops,$target_dir,$outtext);
 
$window->add ($mtable);
$window->show_all();
 
my $result;
my $n= $self->object_get_attribute('soc_name',undef);
if(defined $n){ #we are compiling a single tile as SoC
my %tops;
$tops{"Vtop"}= "$name.v";
$result = verilator_compilation (\%tops,$target_dir,$outtext);
$self->object_add_attribute('verilator','libs',\%tops);
}
else { # we are compiling a complete NoC-based mpsoc
$result = gen_mpsoc_verilator_model ($self,$name,$top,$target_dir,$outtext);
}
 
#check if verilator model has been generated
if ($result){
add_colored_info(\$outtext,"Veriator model has been generated successfully!",'blue');
1385,8 → 1430,7
 
 
$window->add ($mtable);
$window->show_all();
 
 
 
1394,11 → 1438,126
 
 
 
 
 
sub gen_mpsoc_verilator_model{
my ($self,$name,$top,$target_dir,$outtext)=@_;
my $dir = Cwd::getcwd();
my $project_dir = abs_path("$dir/..");
my $src_verilator_dir="$project_dir/src_verilator";
my $sw_dir = "$target_dir/sw";
#copy src_verilator files
add_info(\$outtext,"Copy verilator files\n");
my @files=(
"$src_verilator_dir/noc_connection.sv",
"$src_verilator_dir/router_verilator.v"
);
if (-d "$target_dir/src_verilator/"==0){
mkpath("$target_dir/src_verilator/",1,01777);
}
copy_file_and_folders (\@files,$project_dir,"$target_dir/src_verilator");
#create each tile top module
my $nx= $self->object_get_attribute('noc_param',"NX");
my $ny= $self->object_get_attribute('noc_param',"NY");
my $processors_en=0;
my $mpsoc=$self;
my $lisence= get_license_header("verilator_tiles");
my $warning=autogen_warning();
my $verilator=$lisence.$warning;
# generate NoC parameter file
my ($noc_param,$pass_param)=gen_noc_param_v($self);
my $noc_param_v= " \`ifdef INCLUDE_PARAM \n \n
$noc_param
/* verilator lint_off WIDTH */
localparam P=(TOPOLOGY==\"RING\" || TOPOLOGY==\"LINE\")? 3 : 5;
localparam ROUTE_TYPE = (ROUTE_NAME == \"XY\" || ROUTE_NAME == \"TRANC_XY\" )? \"DETERMINISTIC\" :
(ROUTE_NAME == \"DUATO\" || ROUTE_NAME == \"TRANC_DUATO\" )? \"FULL_ADAPTIVE\": \"PAR_ADAPTIVE\";
/* verilator lint_on WIDTH */
//simulation parameter
\n \n \`endif" ;
save_file("$target_dir/src_verilator/parameter.v",$noc_param_v);
my %tops = (
"Vrouter" => "router_verilator.v",
"Vnoc" => "noc_connection.sv"
);
for (my $y=0;$y<$ny;$y++){
for (my $x=0; $x<$nx;$x++){
my $tile_num= $y*$nx+$x;
#print "$tile_num\n";
my ($soc_name,$num)= $mpsoc->mpsoc_get_tile_soc_name($tile_num);
if(!defined $soc_name){
#this tile is not connected to any ip. the noc input ports will be connected to ground
my $soc_v="\n\n // Tile:$tile_num (x=$x,y=$y) is not assigned to any ip\n";
$soc_v="$soc_v
assign ni_credit_out[$tile_num]={V{1'b0}};
assign ni_flit_out[$tile_num]={Fw{1'b0}};
assign ni_flit_out_wr[$tile_num]=1'b0;
";
next;
}
my $soc=eval_soc($mpsoc,$soc_name,$outtext);
my $top=$mpsoc->mpsoc_get_soc($soc_name);
my $soc_num= $y*$nx+$x;
#update core id
$soc->object_add_attribute('global_param','CORE_ID',$tile_num);
#update NoC param
#my %nocparam = %{$mpsoc->object_get_attribute('noc_param',undef)};
my $nocparam =$mpsoc->object_get_attribute('noc_param',undef);
my @nis=get_NI_instance_list($top);
$soc->soc_add_instance_param($nis[0] ,$nocparam );
my $tile=($nx*$y)+ $x;
my $setting=$mpsoc->mpsoc_get_tile_param_setting($tile);
my %params;
if ($setting eq 'Custom'){
%params= $top->top_get_custom_soc_param($tile);
}else{
%params=$top->top_get_default_soc_param();
}
my $sw_path = "$sw_dir/tile$tile_num";
$verilator = $verilator.soc_generate_verilatore ($soc,$sw_path,"tile_$tile",\%params);
$tops{"Vtile$tile_num"}= "tile_$tile.v";
}}
save_file ("$target_dir/src_verilator/verilator_tiles.v",$verilator);
my $result = verilator_compilation (\%tops,$target_dir,$outtext);
$self->object_add_attribute('verilator','libs',\%tops);
return $result;
 
}
 
 
sub gen_verilator_soc_testbench {
my ($self,$name,$top,$target_dir)=@_;
my $verilator="$target_dir/verilator";
my $dir="$verilator/";
my $soc_top= $self->soc_get_top ();
my @intfcs=$soc_top->top_get_intfc_list();
my %PP;
my $top_port_info="IO type\t port_size\t port_name\n";
1487,7 → 1646,383
 
}
 
sub eval_soc{
my ($mpsoc,$soc_name,$outtext)=@_;
my $path=$mpsoc->object_get_attribute('setting','soc_path');
$path=~ s/ /\\ /g;
my $p = "$path/$soc_name.SOC";
my $soc = eval { do $p };
if ($@ || !defined $soc){
show_info(\$outtext,"**Error reading $p file: $@\n");
next;
}
return $soc;
}
 
 
sub gen_verilator_mpsoc_testbench {
my ($mpsoc,$name,$top,$target_dir,$tview)=@_;
my $verilator="$target_dir/verilator";
my $dir="$verilator/";
#my $soc_top= $self->soc_get_top ();
my $nx= $mpsoc->object_get_attribute('noc_param',"NX");
my $ny= $mpsoc->object_get_attribute('noc_param',"NY");
my $libh="";
my $inst= "";
my $newinst="";
my $tile_x="";
my $tile_y="";
my $tile_flit_in="";
my $tile_flit_in_l="";
my $tile_credit="";
my $noc_credit="";
my $noc_flit_in="";
my $noc_flit_in_l="";
my $noc_flit_in_wr="";
my $noc_flit_in_wr_l="";
my $tile_flit_in_wr="";
my $tile_flit_in_wr_l="";
my $tile_eval="";
my $tile_final="";
my $tile_reset="";
my $tile_clk="";
my $tile_en="";
my $top_port_info="IO type\t port_size\t port_name\n";
my $no_connected='';
for (my $y=0;$y<$ny;$y++){for (my $x=0; $x<$nx;$x++){
my $t= $y*$nx+$x;
my ($soc_name,$num)= $mpsoc->mpsoc_get_tile_soc_name($t);
if(defined $soc_name) {#we have a conncted tile
#get ni instance name
my $ni_name;
my $soc=eval_soc($mpsoc,$soc_name,$tview);
my $soc_top=$soc->object_get_attribute('top_ip',undef);
my @intfcs=$soc_top->top_get_intfc_list();
my @instances=$soc->soc_get_all_instances();
foreach my $id (@instances){
my $category = $soc->soc_get_category($id);
if ($category eq 'NoC') {
$ni_name= $soc->soc_get_instance_name($id);
}
}
$libh=$libh."#include \"Vtile${t}.h\"\n";
$inst=$inst."Vtile${t}\t*tile${t};\t // Instantiation of tile${t}\n";
$newinst = $newinst."\ttile${t}\t=\tnew Vtile${t};\n";
$tile_flit_in = $tile_flit_in . "\ttile${t}->${ni_name}_flit_in = noc->ni_flit_out [${t}];\n";
$tile_flit_in_l = $tile_flit_in_l . "\t\ttile${t}->${ni_name}_flit_in[j] = noc->ni_flit_out [${t}][j];\n";
$tile_credit= $tile_credit."\ttile${t}->${ni_name}_credit_in= noc->ni_credit_out[${t}];\n";
$noc_credit= $noc_credit."\tnoc->ni_credit_in[${t}] = tile${t}->${ni_name}_credit_out;\n";
$noc_flit_in=$noc_flit_in."\tnoc->ni_flit_in [${t}] = tile${t}->${ni_name}_flit_out;\n";
$noc_flit_in_l=$noc_flit_in_l."\t\t\tnoc->ni_flit_in [${t}][j] = tile${t}->${ni_name}_flit_out[j];\n";
$noc_flit_in_wr= $noc_flit_in_wr."\tif(tile${t}->${ni_name}_flit_out_wr) noc->ni_flit_in_wr = noc->ni_flit_in_wr | ((vluint64_t)1<<${t});\n";
$tile_flit_in_wr=$tile_flit_in_wr."\ttile${t}->${ni_name}_flit_in_wr= ((noc->ni_flit_out_wr >> ${t}) & 0x01);\n";
$noc_flit_in_wr_l= $noc_flit_in_wr_l."\tif(tile${t}->${ni_name}_flit_out_wr) MY_VL_SETBIT_W(noc->ni_flit_in_wr ,${t});\n";
$tile_flit_in_wr_l=$tile_flit_in_wr_l."\ttile${t}->${ni_name}_flit_in_wr= (VL_BITISSET_W(noc->ni_flit_out_wr,${t})>0);\n";
$tile_eval=$tile_eval."\ttile${t}->eval();\n";
$tile_final=$tile_final."\ttile${t}->final();\n";
foreach my $intfc (@intfcs){
my $key=($intfc eq 'plug:clk[0]')? 'clk' :
($intfc eq 'plug:reset[0]')? 'reset':
($intfc eq 'plug:enable[0]')? 'en' :
'other';
my @ports=$soc_top->top_get_intfc_ports_list($intfc);
foreach my $p (@ports){
my($inst,$range,$type,$intfc_name,$intfc_port)= $soc_top->top_get_port($p);
$tile_reset=$tile_reset."\t\ttile${t}->$p=reset;\n" if $key eq 'reset';
$tile_clk=$tile_clk."\t\ttile${t}->$p=clk;\n" if $key eq 'clk';
$tile_en=$tile_en."\t\ttile${t}->$p=enable;\n" if $key eq 'en'; ;
$top_port_info="$top_port_info $type $range tile${t}->$p \n";
}#ports
}#interface
$tile_x= $tile_x."\ttile${t}->${ni_name}_current_x=$x;\n";
$tile_y= $tile_y."\ttile${t}->${ni_name}_current_y=$y;\n";
}else{
#this tile is not connected to any ip. the noc input ports will be connected to ground
$no_connected=$no_connected."\n // Tile:$t (x=$x,y=$y) is not assigned to any ip\n";
$no_connected=$no_connected."\t\tnoc->ni_credit_in[${t}]=0; \n";
}
}}
my $main_c=get_license_header("testbench.cpp");
$main_c="$main_c
#include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#include <string.h>
#include <verilated.h> // Defines common routines
 
#include \"Vnoc.h\"
#include \"Vrouter.h\"
$libh
 
 
/*
$top_port_info
*/
 
 
#ifndef NX
#define NX $nx
#endif
 
#ifndef NY
#define NY $ny
#endif
 
#ifndef NC
#define NC ($nx*$ny)
#endif
 
 
Vrouter *router[NC]; // Instantiation of router
Vnoc *noc;
$inst
 
 
int reset,clk,enable;
unsigned int main_time = 0; // Current simulation time
 
void update_all_instances_inputs(void);
 
 
int main(int argc, char** argv) {
int i,j,x,y;
Verilated::commandArgs(argc, argv); // Remember args
for(i=0;i<NC;i++) router[i] = new Vrouter; // Create instance
noc = new Vnoc;
$newinst
/********************
* initialize input
*********************/
 
reset=1;
enable=1;
$no_connected
for(x=0;x<NX;x++)for(y=0;y<NY;y++){
i=(y*NX)+x;
router[i]->current_x = x;
router[i]->current_y = y;
}
$tile_x
$tile_y
 
main_time=0;
printf(\"Start Simulation\\n\");
while (!Verilated::gotFinish()) {
if (main_time >= 10 ) {
reset=0;
}
 
 
if ((main_time % 5) == 0) {
clk = 1; // Toggle clock
// you can change the inputs and read the outputs here in case they are captured at posedge of clock
}
else{
clk = 0; // Toggle clock
update_all_instances_inputs();
}
 
 
//clk,reset,enable
noc-> clk = clk;
noc-> reset = reset;
$tile_reset
$tile_clk
$tile_en
for(i=0;i<NC;i++){
router[i]->reset= reset;
router[i]->clk= clk;
}
 
//eval instances
noc->eval();
for(i=0;i<NC;i++) {
router[i]->eval();
}
$tile_eval
 
main_time++;
 
}//while
// Simulation is dne
for(i=0;i<NC;i++) {
router[i]->final();
}
noc->final();
$tile_final
}
 
double sc_time_stamp () { // Called by \$time in Verilog
return main_time;
}
 
 
void update_all_instances_inputs(void){
int x,y,i,j;
int flit_out_all_size = sizeof(router[0]->flit_out_all)/sizeof(router[0]->flit_out_all[0]);
 
#if (NC<=64)
noc->ni_flit_in_wr =0;
#else
for(j=0;j<(sizeof(noc->ni_flit_in_wr)/sizeof(noc->ni_flit_in_wr[0])); j++) noc->ni_flit_in_wr[j]=0;
#endif
for(x=0;x<NX;x++)for(y=0;y<NY;y++){
i=(y*NX)+x;
router[i]->flit_in_we_all = noc->router_flit_out_we_all[i];
router[i]->credit_in_all = noc->router_credit_out_all[i];
router[i]->congestion_in_all = noc->router_congestion_out_all[i];
for(j=0;j<flit_out_all_size;j++) router[i]->flit_in_all[j] = noc->router_flit_out_all[i][j];
noc->router_flit_in_we_all[i] = router[i]->flit_out_we_all ;
noc->router_credit_in_all[i] = router[i]->credit_out_all;
noc->router_congestion_in_all[i]= router[i]->congestion_out_all;
for(j=0;j<flit_out_all_size;j++) noc->router_flit_in_all[i][j] = router[i]->flit_out_all[j] ;
} //for
 
#if (Fpay<=32)
//tile[i]->flit_in = noc->ni_flit_out [i];
$tile_flit_in
#else
for(j=0;j<(sizeof(traffic[i]->flit_out)/sizeof(traffic[i]->flit_out[0])); j++){
//traffic[i]->flit_in[j] = noc->ni_flit_out [i][j];
$tile_flit_in_l
}
#endif
//traffic[i]->credit_in= noc->ni_credit_out[i];
$tile_credit
//noc->ni_credit_in[i] = traffic[i]->credit_out;
$noc_credit
#if (Fpay<=32)
//noc->ni_flit_in [i] = traffic[i]->flit_out;
$noc_flit_in
#else
for(j=0;j<(sizeof(traffic[i]->flit_out)/sizeof(traffic[i]->flit_out[0])); j++){
//noc->ni_flit_in [i][j] = traffic[i]->flit_out[j];
$noc_flit_in_l
}
#endif
 
 
#if (NC<=64)
//if(traffic[i]->flit_out_wr) noc->ni_flit_in_wr = noc->ni_flit_in_wr | ((vluint64_t)1<<i);
$noc_flit_in_wr
//traffic[i]->flit_in_wr= ((noc->ni_flit_out_wr >> i) & 0x01);
$tile_flit_in_wr
#else
//if(traffic[i]->flit_out_wr) MY_VL_SETBIT_W(noc->ni_flit_in_wr ,i);
$noc_flit_in_wr_l
//traffic[i]->flit_in_wr= (VL_BITISSET_W(noc->ni_flit_out_wr,i)>0);
$tile_flit_in_wr_l
#endif
}
";
 
save_file("$dir/testbench.cpp",$main_c);
 
}
 
 
 
sub soc_get_all_parameters {
my $soc=shift;
my @instances=$soc->soc_get_all_instances();
my %all_param;
foreach my $id (@instances){
my $module =$soc->soc_get_module($id);
my $category =$soc->soc_get_category($id);
my $inst = $soc->soc_get_instance_name($id);
my %params = $soc->soc_get_module_param($id);
my $ip = ip->lib_new ();
my @param_order=$soc->soc_get_instance_param_order($id);
foreach my $p (sort keys %params){
my $inst_param= "$inst\_$p";
#add instance name to parameter value
$params{$p}=add_instantc_name_to_parameters(\%params,$inst,$params{$p});
my ($default,$type,$content,$info,$vfile_param_type,$redefine_param)= $ip->ip_get_parameter($category,$module,$p);
$vfile_param_type= "Don't include" if (!defined $vfile_param_type );
$vfile_param_type= "Parameter" if ($vfile_param_type eq 1);
$vfile_param_type= "Localparam" if ($vfile_param_type eq 0);
$all_param{ $inst_param} = $params{ $p} if($vfile_param_type eq "Parameter" || $vfile_param_type eq "Localparam" );
print"$all_param{ $inst_param} = $params{ $p} if($vfile_param_type eq \"Parameter\" || $vfile_param_type eq \"Localparam\" ); \n";
}
}
return %all_param;
}
 
sub soc_get_all_parameters_order {
my $soc=shift;
my @instances=$soc->soc_get_all_instances();
my $ip = ip->lib_new ();
my @all_order;
foreach my $id (@instances){
my $module =$soc->soc_get_module($id);
my $category =$soc->soc_get_category($id);
my $inst = $soc->soc_get_instance_name($id);
my @order = $soc->soc_get_instance_param_order($id);
foreach my $p ( @order){
my $inst_param= "$inst\_$p";
my ($default,$type,$content,$info,$vfile_param_type,$redefine_param)= $ip->ip_get_parameter($category,$module,$p);
$vfile_param_type= "Don't include" if (!defined $vfile_param_type );
$vfile_param_type= "Parameter" if ($vfile_param_type eq 1);
$vfile_param_type= "Localparam" if ($vfile_param_type eq 0);
push(@all_order, $inst_param) if($vfile_param_type eq "Parameter" || $vfile_param_type eq "Localparam" );
}
}
return @all_order;
}
 
 
 
sub gen_modelsim_soc_testbench {
my ($self,$name,$top,$target_dir)=@_;
my $dir="$target_dir/src_verilog";
1498,15 → 2033,39
my $pin_assign;
my $rst_inputs='';
 
#read port list
my $vdb=read_verilog_file($top);
my %param = $vdb->get_modules_parameters("${name}_top");
#add functions
my $d = Cwd::getcwd();
open my $file1, "<", "$d/lib/verilog/functions.v" or die;
my $functions_all='';
while (my $f1 = readline ($file1)) {
$functions_all="$functions_all $f1 ";
}
close($file1);
#get parameters
my $params_v="";
my $n= $self->object_get_attribute('soc_name',undef);
if(defined $n){ #we are compiling a single tile as SoC
my $core_id= $self->object_get_attribute('global_param','CORE_ID');
my $sw_loc = $self->object_get_attribute('global_param','SW_LOC');
$params_v="\tlocalparam\tCORE_ID=$core_id;
\tlocalparam\tSW_LOC=\"$sw_loc\";\n";
my %params=soc_get_all_parameters($self);
my @order= soc_get_all_parameters_order($self);
foreach my $p (@order){
add_text_to_string(\$params_v,"\tlocalparam $p = $params{$p};\n") if(defined $params{$p} );
}
}else{ # we are simulating a mpsoc
$params_v= gen_socs_param($self);
}
 
 
 
 
foreach my $intfc (@intfcs){
my $key= ( $intfc eq 'plug:clk[0]')? 'clk' :
( $intfc eq 'plug:reset[0]')? 'reset':
1524,20 → 2083,24
 
 
if (length($range)!=0){
#replace parameter with their values
my @a= split (/\b/,$range);
foreach my $l (@a){
my $value=$param{$l};
if(defined $value){
chomp $value;
($range=$range)=~ s/\b$l\b/$value/g if(defined $param{$l});
}
}
# #replace parameter with their values #
# my @a= split (/\b/,$range);
# print "a=@a\n";
# foreach my $l (@a){
# my $value=$params{$l};
# if(defined $value){
# chomp $value;
# ($range=$range)=~ s/\b$l\b/$value/g if(defined $params{$l});
# print "($range=$range)=~ s/\b$l\b/$value/g if(defined $params{$l}); \n";
# }
# }
$range = "[ $range ]" ;
}
 
 
 
 
 
if($type eq 'input'){
$top_port_def="$top_port_def reg $range $p;\n"
}else{
1558,6 → 2121,10
 
module testbench;
 
$functions_all
 
$params_v
 
$top_port_def
 
 
1603,12 → 2170,23
my ($self,$name,$top,$target_dir)=@_;
my $verilator="$target_dir/verilator";
my $dir="$verilator";
gen_verilator_soc_testbench (@_) if((-f "$dir/testbench.cpp")==0);
my ($app,$table,$tview,$window) = software_main($dir,'testbench.cpp');
my $n= $self->object_get_attribute('soc_name',undef);
if(defined $n){ #we are compiling a single tile as SoC
gen_verilator_soc_testbench (@_) if((-f "$dir/testbench.cpp")==0);
}
else { # we are compiling a complete NoC-based mpsoc
gen_verilator_mpsoc_testbench (@_,$tview) if((-f "$dir/testbench.cpp")==0);
}
#copy makefile
#copy("../script/verilator_soc_make", "$verilator/processed_rtl/obj_dir/Makefile");
 
my ($app,$table,$tview,$window) = software_main($dir,'testbench.cpp');
 
 
my $make = def_image_button('icons/gen.png','Compile');
1636,7 → 2214,15
"Are you sure you want to regenaret the testbench.cpp file? Note that any changes you have made will be lost");
my $response = $dialog->run;
if ($response eq 'yes') {
gen_verilator_soc_testbench ($self,$name,$top,$target_dir);
my $n= $self->object_get_attribute('soc_name',undef);
if(defined $n){ #we are compiling a single tile as SoC
gen_verilator_soc_testbench ($self,$name,$top,$target_dir);
}
else { # we are compiling a complete NoC-based mpsoc
gen_verilator_mpsoc_testbench ($self,$name,$top,$target_dir,$tview);
}
$app->load_source("$dir/testbench.cpp");
}
$dialog->destroy;
1647,7 → 2233,16
$make -> signal_connect("clicked" => sub{
$app->do_save();
copy("$dir/testbench.cpp", "$verilator/processed_rtl/obj_dir/testbench.cpp");
run_make_file("$verilator/processed_rtl/obj_dir/",$tview);
my $tops_ref=$self->object_get_attribute('verilator','libs');
my %tops=%{$tops_ref};
my $lib_num=0;
foreach my $top (sort keys %tops) {
run_make_file("$verilator/processed_rtl/obj_dir/",$tview,"lib$lib_num");
$lib_num++;
}
run_make_file("$verilator/processed_rtl/obj_dir/",$tview,"sim");
 
});
 
/mpsoc/perl_gui/lib/perl/emulator.pl
1168,7 → 1168,7
);
 
my @charts = (
{ type=>"2D_line", page_num=>0, graph_name=> "Latency", result_name => "latency_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Latency (clock)', Z_Title=>undef, Y_Max=>100},
{ type=>"2D_line", page_num=>0, graph_name=> "Latency", result_name => "latency_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Avg. Latency (clock)', Z_Title=>undef, Y_Max=>100},
{ type=>"2D_line", page_num=>0, graph_name=> "Throughput", result_name => "throughput_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Avg. Throughput (flits/clock (%))', Z_Title=>undef},
{ type=>"3D_bar", page_num=>1, graph_name=> "Received", result_name => "packet_rsvd_result", X_Title=>'Core ID' , Y_Title=>'Received Packets Per Router', Z_Title=>undef},
{ type=>"3D_bar", page_num=>1, graph_name=> "Sent", result_name => "packet_sent_result", X_Title=>'Core ID' , Y_Title=>'Sent Packets Per Router', Z_Title=>undef},
/mpsoc/perl_gui/lib/perl/graph.pl
331,12 → 331,12
my $scale= $self->object_get_attribute("${graph_id}_graph_scale",undef);
$scale = 5 if(!defined $scale);
$minues -> signal_connect("clicked" => sub{
$self->object_add_attribute("${graph_id}_graph_scale",undef,$scale+0.5);
$self->object_add_attribute("${graph_id}_graph_scale",undef,$scale*1.05);
set_gui_status($self,"ref",1);
});
 
$plus -> signal_connect("clicked" => sub{
$self->object_add_attribute("${graph_id}_graph_scale",undef,$scale-0.5) if( $scale>0.5);
$self->object_add_attribute("${graph_id}_graph_scale",undef,$scale*0.95) if( $scale>0.5);
set_gui_status($self,"ref",5);
});
 
595,13 → 595,13
 
$minues -> signal_connect("clicked" => sub{
$self->object_add_attribute("${graph_id}_graph_scale",undef,$scale+0.5);
$self->object_add_attribute("${graph_id}_graph_scale",undef,$scale*1.05);
set_gui_status($self,"ref",1);
});
set_tip($minues, "Zoom out");
 
$plus -> signal_connect("clicked" => sub{
$self->object_add_attribute("${graph_id}_graph_scale",undef,$scale-0.5) if( $scale>0.5);
$self->object_add_attribute("${graph_id}_graph_scale",undef,$scale*0.95) if( $scale>0.5);
set_gui_status($self,"ref",5);
});
set_tip($plus, "Zoom in");
/mpsoc/perl_gui/lib/perl/ip_gen.pm
529,6 → 529,17
$self->{instance_ids}{$inst}{parameters}{$parameter}{redefine_param}=$redefine;
}
 
sub top_add_localparam{
my ($self,$inst,$parameter,$default,$type,$content,$info,$global_param,$redefine)=@_;
$self->{instance_ids}{$inst}{localparam}{$parameter}{"default"}=$default;
$self->{instance_ids}{$inst}{localparam}{$parameter}{type}=$type;
$self->{instance_ids}{$inst}{localparam}{$parameter}{content}=$content;
$self->{instance_ids}{$inst}{localparam}{$parameter}{info}=$info;
$self->{instance_ids}{$inst}{localparam}{$parameter}{global_param}=$global_param;
$self->{instance_ids}{$inst}{localparam}{$parameter}{redefine_param}=$redefine;
}
 
 
sub top_get_parameter{
my ($self,$inst,$parameter)=@_;
my ($default,$type,$content,$info,$global_param,$redefine);
550,6 → 561,9
return @l;
}
 
 
 
 
sub top_add_default_soc_param{
my ($self,$param_ref)=@_;
my %l=%{$param_ref};
588,6 → 602,8
}
 
 
 
 
sub top_get_intfc_ports_list{
my($self,$intfc_name)=@_;
my @ports;
/mpsoc/perl_gui/lib/perl/mpsoc_gen.pl
482,24 → 482,6
my $ok = def_image_button('icons/select.png','OK');
my $okbox=def_hbox(TRUE,0);
$okbox->pack_start($ok, FALSE, FALSE,0);
825,7 → 807,7
$row= noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$show_noc,'noc_param',undef);
#packet payload width
$label='payload width';
$label='Payload width';
$param='Fpay';
$default='32';
$content='32,256,32';
1003,10 → 985,21
$default="1\'b0";
$info="If enabeled it adds a pipline register at the output port of the router.";
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$adv_set,'noc_param');
#MAX_SBP_NUM = 4 //
$label="Number of multiple router bypassing ";
$param="MAX_SBP_NUM ";
$type='Spin-button';
$content='0,1,1';
$default=0;
$info="maximum number of routers which a packet can by pass during one clock cycle. Define it as zero will disable bypassing.";
#$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$adv_set,'noc_param');
#FIRST_ARBITER_EXT_P_EN
$label='Swich allocator first level
arbiters extenal priority enable';
arbiters external priority enable';
$param='FIRST_ARBITER_EXT_P_EN';
$default= 1;
$info='If set as 1 then the switch allocator\'s input (first) arbiters\' priority registers are enabled only when a request get both input and output arbiters\' grants';
1016,7 → 1009,7
#Arbiter type
$label='SW allocator arbiteration type';
$label='SW allocator arbitration type';
$param='SWA_ARBITER_TYPE';
$default='"RRA"';
$content='"RRA","WRRA"'; #,"WRRA_CLASSIC"';
1202,9 → 1195,13
#remove old rtl files that were copied by ProNoC
my $old_file_ref= eval { do "$hw_dir/file_list" };
if (defined $old_file_ref){
remove_file_and_folders($old_file_ref,$target_dir);
}
my @generated_tiles;
unlink "$hw_dir/file_list";
#print "nx=$nx,ny=$ny\n";
for (my $y=0;$y<$ny;$y++){for (my $x=0; $x<$nx;$x++){
1212,6 → 1209,9
my $tile_num= $y*$nx+$x;
#print "$tile_num\n";
my ($soc_name,$num)= $mpsoc->mpsoc_get_tile_soc_name($tile_num);
next if(!defined $soc_name);
my $path=$mpsoc->object_get_attribute('setting','soc_path');
$path=~ s/ /\\ /g;
my $p = "$path/$soc_name.SOC";
1240,7 → 1240,9
generate_soc($soc,$info,$target_dir,$hw_dir,$sw_path,0,0);
}else{
generate_soc($soc,$info,$target_dir,$hw_dir,$sw_path,0,1);
move ("$hw_dir/$soc_name.v","$hw_dir/tiles/");
move ("$hw_dir/$soc_name.v","$hw_dir/tiles/");
my @tmp= ("$hw_dir/tiles/$soc_name.v");
add_to_project_file_list(\@tmp,"$hw_dir/tiles",$hw_dir);
}
1302,9 → 1304,18
}
show_info(\$info,$warnings) if(defined $warnings);
show_info(\$info,$warnings) if(defined $warnings);
#save project hdl file/folder list
my @new_file_ref;
foreach my $f(@{$hdl_ref}){
my ($name,$path,$suffix) = fileparse("$f",qr"\..[^.]*$");
push(@new_file_ref,"$target_dir/src_verilog/lib/$name$suffix");
}
open(FILE, ">$target_dir/src_verilog/file_list") || die "Can not open: $!";
print FILE Data::Dumper->Dump([\@new_file_ref],['files']);
close(FILE) || die "Error closing file: $!";
#my @pathes=("$dir/../src_peripheral","$dir/../src_noc","$dir/../src_processor");
#foreach my $p(@pathes){
# find(
1359,7 → 1370,7
#################
 
sub generate_mpsoc{
my ($mpsoc,$info)=@_;
my ($mpsoc,$info,$show_sucess_msg)=@_;
my $name=$mpsoc->object_get_attribute('mpsoc_name');
my $error = check_verilog_identifier_syntax($name);
if ( defined $error ){
1430,7 → 1441,7
message_dialog("SoC \"$name\" has been created successfully at $target_dir/ " );
message_dialog("MPSoC \"$name\" has been created successfully at $target_dir/ " ) if($show_sucess_msg);
1482,6 → 1493,7
 
#programe the memory
for i in $(ls -d */); do
echo "Enter ${i%%/}"
cd ${i%%/}
sh write_memory.sh
cd ..
1635,7 → 1647,7
my @list=(' ',@socs);
my $pos=(defined $soc_name)? get_scolar_pos($soc_name,@list): 0;
my $combo=gen_combo(\@list, $pos);
my $lable=gen_label_in_left(" SoC name:");
my $lable=gen_label_in_left(" Processing tile name:");
$table->attach_defaults($lable,0,3,$row,$row+1);
$table->attach_defaults($combo,3,7,$row,$row+1);$row++;
my $separator1 = Gtk2::HSeparator->new;
1767,18 → 1779,21
message_dialog("Please define the MPSoC name!");
return ;
}
my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$name/sw";
my $sw = "$target_dir";
my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$name";
my $sw = "$target_dir/sw";
my ($app,$table,$tview) = software_main($sw);
 
 
 
my $make = def_image_button('icons/gen.png','Compile');
my $prog= def_image_button('icons/write.png','Program the memories');
$table->attach ($make,9, 10, 1,2,'shrink','shrink',0,0);
$table->attach ($make,5, 6, 1,2,'shrink','shrink',0,0);
$table->attach ($prog,9, 10, 1,2,'shrink','shrink',0,0);
 
$make -> signal_connect("clicked" => sub{
$app->do_save();
1786,7 → 1801,46
run_make_file($sw,$tview);
 
});
#Programe the board
$prog-> signal_connect("clicked" => sub{
my $error = 0;
my $bash_file="$sw/program.sh";
my $jtag_intfc="$sw/jtag_intfc.sh";
add_info(\$tview,"Programe the board using quartus_pgm and $bash_file file\n");
#check if the programming file exists
unless (-f $bash_file) {
add_colored_info(\$tview,"\tThe $bash_file does not exists! \n", 'red');
$error=1;
}
#check if the jtag_intfc.sh file exists
unless (-f $jtag_intfc) {
add_colored_info(\$tview,"\tThe $jtag_intfc does not exists!. Press the compile button and select your FPGA board first to generate $jtag_intfc file\n", 'red');
$error=1;
}
return if($error);
my $command = "cd $sw; sh program.sh";
add_info(\$tview,"$command\n");
my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($command);
if(length $stderr>1){
add_colored_info(\$tview,"$stderr\n",'red');
add_colored_info(\$tview,"Memory was not programed successfully!\n",'red');
}else {
 
if($exit){
add_colored_info(\$tview,"$stdout\n",'red');
add_colored_info(\$tview,"Memory was not programed successfully!\n",'red');
}else{
add_info(\$tview,"$stdout\n");
add_colored_info(\$tview,"Memory is programed successfully!\n",'blue');
 
}
}
});
 
}
 
 
1946,7 → 2000,7
$generate-> signal_connect("clicked" => sub{
generate_mpsoc($mpsoc,$info);
generate_mpsoc($mpsoc,$info,1);
set_gui_status($mpsoc,"refresh_soc",1);
 
});
1969,6 → 2023,7
my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$name";
my $top_file = "$target_dir/src_verilog/${name}_top.v";
if (-f $top_file){
generate_mpsoc($mpsoc,$info,0);
select_compiler($mpsoc,$name,$top_file,$target_dir);
} else {
message_dialog("Cannot find $top_file file. Please run RTL Generator first!");
/mpsoc/perl_gui/lib/perl/mpsoc_verilog_gen.pl
46,7 → 46,7
#functions
my $functions=get_functions();
my $mpsoc_v = (defined $param_as_in_v )? "module $mpsoc_name #(\n $param_as_in_v\n)(\n$io_v\n);\n": "module $mpsoc_name (\n$io_v\n);\n";
my $mpsoc_v = (defined $param_as_in_v )? "`timescale 1ns/1ps\nmodule $mpsoc_name #(\n $param_as_in_v\n)(\n$io_v\n);\n": "`timescale 1ns/1ps\nmodule $mpsoc_name (\n$io_v\n);\n";
add_text_to_string (\$mpsoc_v,$noc_param);
add_text_to_string (\$mpsoc_v,$functions);
add_text_to_string (\$mpsoc_v,$socs_param);
56,7 → 56,8
add_text_to_string (\$mpsoc_v,$socs_v);
add_text_to_string (\$mpsoc_v,"\nendmodule\n");
my $top_v = (defined $param_as_in_v )? "module ${mpsoc_name}_top #(\n $param_as_in_v\n)(\n$io_v\n);\n": "module ${mpsoc_name}_top (\n $io_v\n);\n";
my $top_v = (defined $param_as_in_v )? "`timescale 1ns/1ps\nmodule ${mpsoc_name}_top #(\n $param_as_in_v\n)(\n$io_v\n);\n": "`timescale 1ns/1ps\nmodule ${mpsoc_name}_top (\n $io_v\n);\n";
add_text_to_string (\$top_v,$socs_param);
add_text_to_string (\$top_v,$io_def_v);
add_text_to_string(\$top_v,"
579,6 → 580,7
}
#enable
elsif( $intfc eq 'plug:enable[0]'){
my @ports=$top->top_get_intfc_ports_list($intfc);
foreach my $p (@ports){
592,6 → 594,18
}
#RxD_sim
elsif( $intfc eq 'socket:RxD_sim[0]'){
#This interface is for simulation only donot include it in top module
my @ports=$top->top_get_intfc_ports_list($intfc);
foreach my $p (@ports){
add_text_to_string(\$soc_v,',') if ($i);
add_text_to_string(\$soc_v,"\n\t\t.$p( )");
$i=1;
}
}
else {
#other interface
my @ports=$top->top_get_intfc_ports_list($intfc);
/mpsoc/perl_gui/lib/perl/simulator.pl
757,6 → 757,7
#@q =split (/\n/,$d);
#my $avg=$q[0];
my $avg_latency =capture_number_after("average latency =",$stdout);
my $sd_latency =capture_number_after("standard_dev =",$stdout);
my $avg_thput =capture_number_after("Avg throughput is:",$stdout);
my $total_time =capture_number_after("simulation clock cycles:",$stdout);
769,6 → 770,7
next if (!defined $avg_latency);
update_result($simulate,$sample,"latency_result",$ratio_in,$avg_latency);
update_result($simulate,$sample,"sd_latency_result",$ratio_in,$sd_latency);
update_result($simulate,$sample,"throughput_result",$ratio_in,$avg_thput);
update_result($simulate,$sample,"exe_time_result",$ratio_in,$total_time);
foreach my $p (sort keys %packet_rsvd_per_core){
825,6 → 827,7
#@q =split (/\n/,$d);
#my $avg=$q[0];
my $avg_latency =capture_number_after("average latency =",$stdout);
my $sd_latency =capture_number_after("standard_dev =",$stdout);
my $avg_thput =capture_number_after("Avg throughput is:",$stdout);
my %packet_rsvd_per_core = capture_cores_data("total number of received packets:",$stdout);
my %worst_rsvd_delay_per_core = capture_cores_data('worst-case-delay of received pckets \(clks\):',$stdout);
836,6 → 839,7
next if (!defined $avg_latency);
update_result($simulate,$sample,"latency_result",$i,$avg_latency);
update_result($simulate,$sample,"sd_latency_result",$i,$sd_latency);
update_result($simulate,$sample,"throughput_result",$i,$avg_thput);
update_result($simulate,$sample,"exe_time_result",$i,$total_time);
foreach my $p (sort keys %packet_rsvd_per_core){
926,8 → 930,9
 
 
my @charts = (
{ type=>"2D_line", page_num=>0, graph_name=> "Latency", result_name => "latency_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Latency (clock)', Z_Title=>undef, Y_Max=>100},
{ type=>"2D_line", page_num=>0, graph_name=> "Throughput", result_name => "throughput_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Avg. Throughput (flits/clock (%))', Z_Title=>undef},
{ type=>"2D_line", page_num=>0, graph_name=> "Throughput", result_name => "throughput_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Avg. Throughput (flits/clock (%))', Z_Title=>undef},
{ type=>"2D_line", page_num=>0, graph_name=> "Avg. Latency", result_name => "latency_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Avg. Latency (clock)', Z_Title=>undef, Y_Max=>100},
{ type=>"2D_line", page_num=>0, graph_name=> "SD latency", result_name => "sd_latency_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Latency Standard Deviation (clock)', Z_Title=>undef},
{ type=>"3D_bar", page_num=>1, graph_name=> "Received", result_name => "packet_rsvd_result", X_Title=>'Core ID' , Y_Title=>'Received Packets Per Router', Z_Title=>undef},
{ type=>"3D_bar", page_num=>1, graph_name=> "Sent", result_name => "packet_sent_result", X_Title=>'Core ID' , Y_Title=>'Sent Packets Per Router', Z_Title=>undef},
{ type=>"3D_bar", page_num=>2, graph_name=> "Received", result_name => "worst_delay_rsvd_result",X_Title=>'Core ID' , Y_Title=>'Worst-Case Delay (clk)', Z_Title=>undef},
/mpsoc/perl_gui/lib/perl/soc.pm
786,4 → 786,7
}
 
 
 
 
 
1
/mpsoc/perl_gui/lib/perl/soc_gen.pl
941,6 → 941,30
return \@files,$warnings;
}
 
 
sub add_to_project_file_list{
my ($files_ref,$files_path,$list_path )=@_;
my @new_file_ref;
foreach my $f(@{$files_ref}){
my ($name,$path,$suffix) = fileparse("$f",qr"\..[^.]*$");
push(@new_file_ref,"$files_path/$name$suffix");
}
my $old_file_ref= eval { do "$list_path/file_list" };
if (defined $old_file_ref){
foreach my $f(@{$old_file_ref}){
unless ( grep( /^$f$/, @new_file_ref ) ){
push(@new_file_ref,$f);
}
 
}
}
open(FILE, ">$list_path/file_list") || die "Can not open: $!";
print FILE Data::Dumper->Dump([\@new_file_ref],['files']);
close(FILE) || die "Error closing file: $!";
}
 
 
 
################
# generate_soc
#################
984,7 → 1008,7
close(FILE) || die "Error closing file: $!";
 
#generate prog_mem
open(FILE, ">lib/verilog/program.sh") || die "Can not open: $!";
open(FILE, ">lib/verilog/program.sh") || die "Can not open: $!";
print FILE soc_mem_prog();
close(FILE) || die "Error closing file: $!";
 
998,18 → 1022,26
my $hw_lib="$hw_path/lib";
mkpath("$hw_lib/",1,01777);
mkpath("$sw_path/",1,01777);
#remove old rtl files that were copied by ProNoC
my $old_file_ref= eval { do "$hw_path/file_list" };
if (defined $old_file_ref){
remove_file_and_folders($old_file_ref,$target_dir);
}
#copy hdl codes in src_verilog
my ($file_ref,$warnings)= get_all_files_list($soc,"hdl_files");
#copy hdl codes in src_verilog
my ($file_ref,$warnings)= get_all_files_list($soc,"hdl_files");
copy_file_and_folders($file_ref,$project_dir,$hw_lib);
show_info(\$info,$warnings) if(defined $warnings);
show_info(\$info,$warnings) if(defined $warnings);
add_to_project_file_list($file_ref,$hw_lib,$hw_path);
#copy jtag control files
my @jtags=(("/mpsoc/src_peripheral/jtag/jtag_wb"),("jtag"));
copy_file_and_folders(\@jtags,$project_dir,$hw_lib);
copy_file_and_folders(\@jtags,$project_dir,$hw_lib);
add_to_project_file_list(\@jtags,$hw_lib,$hw_path);
move ("$dir/lib/verilog/$name.v","$hw_path/");
move ("$dir/lib/verilog/${name}_top.v","$hw_path/");
move ("$dir/lib/verilog/README" ,"$sw_path/");
1017,10 → 1049,29
move ("$dir/lib/verilog/program.sh" ,"$sw_path/");
}
#remove old software files that were copied by ProNoC
my $old_file_ref= eval { do "$sw_path/file_list" };
if (defined $old_file_ref){
remove_file_and_folders($old_file_ref,$project_dir);
}
# Copy Software files
my ($file_ref,$warnings)= get_all_files_list($soc,"sw_files");
copy_file_and_folders($file_ref,$project_dir,$sw_path);
my @new_file_ref;
foreach my $f(@{$file_ref}){
my ($name,$path,$suffix) = fileparse("$f",qr"\..[^.]*$");
push(@new_file_ref,"$sw_path/$name$suffix");
}
push(@new_file_ref,"$sw_path/$name.h");
open(FILE, ">$sw_path/file_list") || die "Can not open: $!";
print FILE Data::Dumper->Dump([\@new_file_ref],['files']);
close(FILE) || die "Error closing file: $!";
# Write system.h and Software gen files
generate_header_file($soc,$project_dir,$sw_path,$hw_path,$dir);
1121,7 → 1172,75
 
 
 
#############
# set_unset_infc
#############
 
sub set_unset_infc{
my $soc =shift;
my $window = def_popwin_size(40,60,"Unconnected Socket Interfaces",'percent');
my $table = def_table(10,4, FALSE);
my $scrolled_win = new Gtk2::ScrolledWindow (undef, undef);
$scrolled_win->set_policy( "automatic", "automatic" );
$scrolled_win->add_with_viewport($table);
my $row=0;
my $column=0;
my $ip = ip->lib_new ();
my @instances=$soc->soc_get_all_instances();
foreach my $id (@instances){
my $module =$soc->soc_get_module($id);
my $module_name =$soc->soc_get_module_name($id);
my $category =$soc->soc_get_category($id);
my $inst = $soc->soc_get_instance_name($id);
my @ports=$ip->ip_list_ports($category,$module);
foreach my $port (@ports){
my ($type,$range,$intfc_name,$i_port)=$ip->ip_get_port($category,$module,$port);
my($i_type,$i_name,$i_num) =split("[:\[ \\]]", $intfc_name);
if($i_type eq 'socket' && $i_name ne'wb_addr_map' ){
my ($ref1,$ref2)= $soc->soc_get_modules_plug_connected_to_socket($id,$i_name,$i_num);
my %connected_plugs=%$ref1;
my %connected_plug_nums=%$ref2;
if(!%connected_plugs ){
my ($s_type,$s_value,$s_connection_num)=$soc->soc_get_socket_of_instance($id,$i_name);
my $v=$soc->soc_get_module_param_value($id,$s_value);
if ( length( $v || '' ) || $category eq 'NoC' ){ }
else {
($row,$column)=add_param_widget ($soc,"$inst->$port","$inst-$port", 'IO','Combo-box',"IO,NC",undef, $table,$row,$column,1,"Unset-intfc",undef,undef,"vertical");
if($column == 0){
$column = 4;
$row= $row-1;
}else{
$column = 0;
}
}
}
}
}
}
my $box1=def_hbox(FALSE, 1);
$box1->pack_start( Gtk2::VSeparator->new, FALSE, FALSE, 3);
$table->attach($box1,3,4,0,$row+1,'expand','fill',2,2);
my $ok = def_image_button('icons/select.png','OK');
$ok->signal_connect ( 'clicked'=> sub {
$window->destroy;
});
my $mtable = def_table(10, 1, FALSE);
$mtable->attach_defaults($scrolled_win,0,1,0,9);
$mtable->attach($ok,0,1,9,10,'expand','fill',2,2);
$window->add ($mtable);
$window->show_all;
}
 
 
 
1291,7 → 1410,7
$window->destroy;
}else{
message_dialog("Invalid address !");
message_dialog("Invalid address!");
}
1298,14 → 1417,14
});
$table->attach ($refbox,2,3,$row,$row+1,'expand','shrink',2,2);
$table->attach ($ok,3,4,$row,$row+1,'expand','shrink',2,2);
$window->add($scrolled_win);
my $mtable = def_table(10, 2, FALSE);
$mtable->attach_defaults($scrolled_win,0,2,0,9);
$mtable->attach ($refbox,0,1,9,10,'expand','shrink',2,2);
$mtable->attach($ok,1,2,9,10,'expand','fill',2,2);
$window->add ($mtable);
$window->show_all;
1605,6 → 1724,7
$prog-> signal_connect("clicked" => sub{
my $error = 0;
my $bash_file="$target_dir/sw/program.sh";
my $jtag_intfc="$sw/jtag_intfc.sh";
 
add_info(\$tview,"Programe the board using quartus_pgm and $bash_file file\n");
#check if the programming file exists
1612,6 → 1732,11
add_colored_info(\$tview,"\tThe $bash_file does not exists! \n", 'red');
$error=1;
}
#check if the jtag_intfc.sh file exists
unless (-f $jtag_intfc) {
add_colored_info(\$tview,"\tThe $jtag_intfc does not exists!. Press the compile button and select your FPGA board first to generate $jtag_intfc file\n", 'red');
$error=1;
}
return if($error);
my $command = "cd $target_dir/sw; sh program.sh";
1719,6 → 1844,8
my $compile = def_image_button('icons/gate.png','Compile RTL');
my $software = def_image_button('icons/binary.png','Software');
my $diagram = def_image_button('icons/diagram.png','Diagram');
my $unset = def_image_button('icons/intfc.png','Unset Intfc.');
my $ram = def_image_button('icons/RAM.png','Memory');
 
1726,7 → 1853,7
 
 
my $wb = def_image_button('icons/setting.png','Wishbone-bus addr');
my $wb = def_image_button('icons/setting.png','WB addr');
1755,8 → 1882,10
 
 
$main_table->attach ($open,0, 2, 19,20,'expand','shrink',2,2);
$main_table->attach_defaults ($entrybox,2, 4, 19,20);
$main_table->attach ($open,0, 1, 19,20,'expand','shrink',2,2);
$main_table->attach_defaults ($entrybox,1, 3, 19,20);
$main_table->attach ($unset, 3,4, 19,20,'expand','shrink',2,2);
$main_table->attach ($wb, 4,6, 19,20,'expand','shrink',2,2);
$main_table->attach ($diagram, 6, 7, 19,20,'expand','shrink',2,2);
$main_table->attach ($generate, 7, 8, 19,20,'expand','shrink',2,2);
1795,6 → 1924,9
my $sw_path = "$target_dir/sw";
$soc->object_add_attribute('global_param','CORE_ID',0);
$soc->object_add_attribute('global_param','SW_LOC',$sw_path);
unlink "$hw_dir/file_list";
generate_soc($soc,$info,$target_dir,$hw_dir,$sw_path,1,1);
#message_dialog("SoC \"$name\" has been created successfully at $target_dir/ " );
my $has_ni= check_for_ni($soc);
1823,6 → 1955,10
software_edit_soc($soc);
 
});
$unset-> signal_connect("clicked" => sub{
set_unset_infc($soc);
});
 
$ram-> signal_connect("clicked" => sub{
get_ram_init($soc);
1842,6 → 1978,7
my $sw_path = "$target_dir/sw";
my $top = "$target_dir/src_verilog/${name}_top.v";
if (-f $top){
unlink "$hw_dir/file_list";
generate_soc($soc,$info,$target_dir,$hw_dir,$sw_path,1,1);
select_compiler($soc,$name,$top,$target_dir);
} else {
/mpsoc/perl_gui/lib/perl/software_editor.pl
88,51 → 88,16
$vpaned-> pack2 ($scwin_info, TRUE, TRUE);
 
 
my ($tree_view,$tree_store) =$self->build_tree_view($sw);
 
 
# Directory name, full path
my $tree_store = Gtk2::TreeStore->new('Glib::String', 'Glib::String');
my $tree_view = Gtk2::TreeView->new($tree_store);
my $column = Gtk2::TreeViewColumn->new_with_attributes('', Gtk2::CellRendererText->new(), text => "0");
$tree_view->append_column($column);
$tree_view->set_headers_visible(FALSE);
$tree_view->signal_connect (button_release_event => sub{
my $tree_model = $tree_view->get_model();
my $selection = $tree_view->get_selection();
my $iter = $selection->get_selected();
if(defined $iter){
my $path = $tree_model->get($iter, 1) ;
$path= substr $path, 0, -1;
$self->load_source($path) if(-f $path);
}
return;
});
 
 
$tree_view->signal_connect ('row-expanded' => sub {
my ($tree_view, $iter, $tree_path) = @_;
my $tree_model = $tree_view->get_model();
my ($dir, $path) = $tree_model->get($iter);
$scwin_dirs -> add($tree_view);
 
# for each of $iter's children add any subdirectories
my $child = $tree_model->iter_children ($iter);
while ($child) {
my ($dir, $path) = $tree_model->get($child, 0, 1);
add_to_tree($tree_view,$tree_store, $child, $dir, $path);
$child = $tree_model->iter_next ($child);
}
return;
});
 
 
$scwin_dirs -> add($tree_view);
 
 
 
my $child = $tree_store->append(undef);
$tree_store->set($child, 0, $sw, 1, '/');
add_to_tree($tree_view,$tree_store, $child, '/', "$sw/");
#print "$sw/\n";
 
#my $window = Gtk2::Window->new();
143,7 → 108,7
my $vbox = Gtk2::VBox->new(FALSE, 0);
$scwin_text->add_with_viewport($vbox);
 
$vbox->pack_start($self->build_menu, FALSE, FALSE, 0);
$vbox->pack_start($self->build_menu("$sw/",$window,$tree_view,$tree_store,$scwin_dirs), FALSE, FALSE, 0);
$vbox->pack_start($self->build_search_box, FALSE, FALSE, 0);
 
my $scroll = Gtk2::ScrolledWindow->new();
213,6 → 178,56
}
 
 
 
 
sub build_tree_view{
my ($self,$sw)=@_;
 
# Directory name, full path
my $tree_store = Gtk2::TreeStore->new('Glib::String', 'Glib::String');
my $tree_view = Gtk2::TreeView->new($tree_store);
my $column = Gtk2::TreeViewColumn->new_with_attributes('', Gtk2::CellRendererText->new(), text => "0");
$tree_view->append_column($column);
$tree_view->set_headers_visible(FALSE);
$tree_view->signal_connect (button_release_event => sub{
my $tree_model = $tree_view->get_model();
my $selection = $tree_view->get_selection();
my $iter = $selection->get_selected();
if(defined $iter){
my $path = $tree_model->get($iter, 1) ;
$path= substr $path, 0, -1;
$self->do_save();
#print "open $path\n";
$self->load_source($path) if(-f $path);
}
return;
});
 
 
$tree_view->signal_connect ('row-expanded' => sub {
my ($tree_view, $iter, $tree_path) = @_;
my $tree_model = $tree_view->get_model();
my ($dir, $path) = $tree_model->get($iter);
 
# for each of $iter's children add any subdirectories
my $child = $tree_model->iter_children ($iter);
while ($child) {
my ($dir, $path) = $tree_model->get($child, 0, 1);
add_to_tree($tree_view,$tree_store, $child, $dir, $path);
$child = $tree_model->iter_next ($child);
}
return;
});
 
my $child = $tree_store->append(undef);
$tree_store->set($child, 0, $sw, 1, '/');
add_to_tree($tree_view,$tree_store, $child, '/', "$sw/");
return ($tree_view,$tree_store);
 
}
 
 
 
sub build_search_box {
my $self = shift;
 
434,8 → 449,9
 
 
sub do_file_new {
my $self = shift;
my ($self,$sw,$window,$tree_view,$tree_store,$scwin_dirs) = @_;
my $buffer = $self->buffer;
 
# Set no language
$buffer->set_language(undef);
450,6 → 466,7
 
$self->filename('');
$self->window->set_title("Untitled - $NAME");
$self->do_save_as($sw,$window,$tree_view,$tree_store,$scwin_dirs);
}
 
 
534,13 → 551,13
 
 
sub do_quit {
my $self = shift;
Gtk2->main_quit();
my ($self,$window) = @_;
$window->destroy;
}
 
 
sub do_save_as {
my $self = shift;
my ($self,$sw,$window,$tree_view,$tree_store,$scwin_dirs) = @_;
 
# If no file is associated with the editor then ask the user for a file where
# to save the contents of the buffer.
549,13 → 566,28
'gtk-cancel' => 'cancel',
'gtk-save' => 'ok',
);
if(defined $sw){
$dialog->set_current_folder ($sw);
#print "open_in:$sw\n";
}
 
my $response = $dialog->run();
if ($response eq 'ok') {
$self->filename($dialog->get_filename);
my $file=$dialog->get_filename;
$self->filename($file);
$self->do_save();
$tree_view->destroy;
($tree_view,$tree_store) =$self->build_tree_view($sw);
$scwin_dirs->add($tree_view);
$scwin_dirs->show_all;
$self->load_source($file);
}
$dialog->destroy();
 
}
 
 
566,7 → 598,7
 
# If there's no file then do a save as...
if (! $filename) {
$self->do_save_as();
#$self->do_save_as();
return;
}
 
581,8 → 613,11
}
 
 
 
 
 
sub build_menu {
my $self = shift;
my ($self,$sw,$window,$tree_view,$tree_store,$scwin_dirs) = @_;
 
my $entries = [
# name, stock id, label
597,7 → 632,7
"_New",
"<control>N",
"Create a new file",
sub { $self->do_file_new(@_) }
sub { $self->do_file_new($sw,$window,$tree_view,$tree_store,$scwin_dirs) }
],
[
"Open",
621,7 → 656,7
"Save _As...",
"<control><shift>S",
"Save to a file",
sub { $self->do_save_as(@_) }
sub { $self->do_save_as($sw,$window,$tree_view,$tree_store,$scwin_dirs) }
],
[
"Quit",
629,7 → 664,7
"_Quit",
"<control>Q",
"Quit",
sub { $self->do_quit() }
sub { $self->do_quit($window) }
],
[
"About",
/mpsoc/perl_gui/lib/perl/verilog_gen.pl
171,7 → 171,13
if(!%connected_plugs ){
my ($s_type,$s_value,$s_connection_num)=$soc->soc_get_socket_of_instance($id,$i_name);
my $v=$soc->soc_get_module_param_value($id,$s_value);
if ( length( $v || '' )){ $IO='no';} else {$IO='yes';}
if ( length( $v || '' )){ $IO='no';} else {
my $con= $soc->object_get_attribute("Unset-intfc" ,"$inst-$port");
if(!defined $con){ $IO='yes';}
else{
$IO='yes' if $con eq 'IO';
}
}
}
}
363,6 → 369,7
if($vfile_param_type eq "Localparam"){
$local_param_v="$local_param_v\tlocalparam\t$inst_param=$params{$param};\n";
$top_ip->top_add_localparam($id,$inst_param,$params{$param},$type,$content,$info,$vfile_param_type,$redefine_param);
}
elsif($vfile_param_type eq "Parameter"){
$param_v="$param_v\tparameter\t$inst_param=$params{$param};\n";
657,13 → 664,62
 
 
 
sub gen_soc_instance_v_no_modfy{
my ($soc,$soc_name,$param_pass_v)=@_;
my $soc_v;
my $processor_en=0;
 
my $mm="$soc_name #(\n $param_pass_v \n\t)the_${soc_name}(\n";
 
my $top=$soc->soc_get_top();
my @intfcs=$top->top_get_intfc_list();
my $i=0;
 
my $ss="";
my $ww="";
foreach my $intfc (@intfcs){
my @ports=$top->top_get_intfc_ports_list($intfc);
foreach my $p (@ports){
my($inst,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
$mm="$mm," if ($i);
$mm="$mm\n\t\t.$p($p)";
$i=1;
}
}
$mm="$mm\n\t);";
add_text_to_string(\$soc_v,"$ww\n");
add_text_to_string(\$soc_v,"$mm\n");
add_text_to_string(\$soc_v,"$ss\n");
add_text_to_string(\$soc_v,"\n endmodule\n");
return $soc_v;
 
}
 
 
 
 
 
 
 
 
sub gen_system_info {
my ($soc,$param)=@_;
my ($wb_slaves,$wb_masters,$other,$jtag);
759,8 → 815,8
}elsif ($jtag_connect eq 'ALTERA_IMCE'){
#TODO add later
$prog= "$prog echo \"ALTERA_IMCE runtime programming is not supported yet for programming $instance_id\"\n";
} else{
#disabled check if its connected to jtag_wb via the bus
my $connect_id = $ram{$instance_id}{'connect'};
775,9 → 831,15
$prog= "$prog \$JTAG_INTFC -n $JTAG_INDEX -s \"$OFSSET\" -e \"$BOUNDRY\" -i \"$BINFILE\" -c";
#print "prog= $prog\n";
}
}else{
$prog= "$prog echo \"JTAG runtime programming is not enabled in $instance_id\"\n";
}
}else{
$prog= "$prog echo \"JTAG runtime programming is not enabled in $instance_id\"\n";
}
}
845,14 → 907,112
 
 
 
######################
# soc_generate_verilog
#####################
 
sub soc_generate_verilatore{
my ($soc,$sw_path,$name,$params_ref)= @_;
my $soc_name=$soc->object_get_attribute('soc_name');
my $top_ip=ip_gen->top_gen_new();
if(!defined $soc_name){$soc_name='soc'};
my @instances=$soc->soc_get_all_instances();
my $io_sim_v;
my $io_top_sim_v;
my $core_id= $soc->object_get_attribute('global_param','CORE_ID');
$core_id= 0 if(!defined $core_id);
my $param_as_in_v="\tparameter\tCORE_ID=$core_id,
\tparameter\tSW_LOC=\"$sw_path\"\n,";
 
my $param_pass_v="\t.CORE_ID(CORE_ID),\n\t.SW_LOC(SW_LOC)";
my $body_v;
my ($param_v_all, $local_param_v_all, $wire_def_v_all, $inst_v_all, $plugs_assign_v_all, $sockets_assign_v_all,$io_full_v_all,$io_top_full_v_all);
my $wires=soc->new_wires();
my $intfc=interface->interface_new();
foreach my $id (@instances){
my ($param_v, $local_param_v, $wire_def_v, $inst_v, $plugs_assign_v, $sockets_assign_v,$io_full_v,$io_top_full_v)=gen_module_inst($id,$soc,\$io_sim_v,\$io_top_sim_v,\$param_as_in_v,$top_ip,$intfc,$wires,\$param_pass_v);
my $inst = $soc->soc_get_instance_name($id);
add_text_to_string(\$body_v,"/*******************\n*\n*\t$inst\n*\n*\n*********************/\n");
add_text_to_string(\$local_param_v_all,"$local_param_v\n") if(defined($local_param_v));
add_text_to_string(\$wire_def_v_all,"$wire_def_v\n") if(defined($wire_def_v));
add_text_to_string(\$inst_v_all,$inst_v) if(defined($inst_v));
add_text_to_string(\$plugs_assign_v_all,"$plugs_assign_v\n") if(defined($plugs_assign_v));
add_text_to_string(\$sockets_assign_v_all,"$sockets_assign_v\n")if(defined($sockets_assign_v));
add_text_to_string(\$io_full_v_all,"$io_full_v\n") if(defined($io_full_v));
add_text_to_string(\$io_top_full_v_all,"$io_top_full_v\n") if(defined($io_top_full_v));
#print "$param_v $local_param_v $wire_def_v $inst_v $plugs_assign_v $sockets_assign_v $io_full_v";
}
my ($addr_map,$addr_localparam,$module_addr_localparam)= generate_address_cmp($soc,$wires);
 
#add functions
my $dir = Cwd::getcwd();
open my $file1, "<", "$dir/lib/verilog/functions.v" or die;
my $functions_all='';
while (my $f1 = readline ($file1)) {
$functions_all="$functions_all $f1 ";
}
close($file1);
my $unused_wiers_v=assign_unconnected_wires($wires,$intfc);
 
$soc->object_add_attribute('top_ip',undef,$top_ip);
#print @assigned_wires;
 
#generate topmodule
my $params_v="
\tparameter\tCORE_ID=$core_id;
\tparameter\tSW_LOC=\"$sw_path\";\n";
my %all_param=soc_get_all_parameters($soc);
my @order= soc_get_all_parameters_order($soc);
#replace global parameters
my @list=sort keys%{$params_ref};
foreach my $p (@list){
my %hash=%{$params_ref};
$all_param{$p}= $hash{$p};
}
foreach my $p (@order){
add_text_to_string(\$params_v,"\tlocalparam $p = $all_param{$p};\n") if(defined $all_param{$p} );
}
my $verilator_v = "
/*********************
${name}
*********************/
module ${name} (\n $io_top_sim_v\n);\n";
my $ins= gen_soc_instance_v_no_modfy($soc,$soc_name,$param_pass_v);
add_text_to_string(\$verilator_v,$functions_all);
add_text_to_string(\$verilator_v,$params_v."\n".$io_top_full_v_all);
add_text_to_string(\$verilator_v,$ins);
my ($readme,$prog)=gen_system_info($soc,$param_as_in_v);
return ($verilator_v);
 
 
}
 
 
 
 
 
 
 
1;
 
 
/mpsoc/perl_gui/lib/perl/widget.pl
1018,6 → 1018,26
 
}
 
 
sub remove_file_and_folders{
my ($file_ref,$project_dir)=@_;
 
foreach my $f(@{$file_ref}){
my $name= basename($f);
my $n="$project_dir$f";
if (-f "$n") { #copy file
unlink ("$n");
}elsif(-f "$f" ){
unlink ("$f");
}elsif (-d "$n") {#copy folder
rmtree ("$n");
}elsif(-d "$f" ){
rmtree ("$f");
}
}
 
}
 
sub read_file_cntent {
my ($f,$project_dir)=@_;
my $n="$project_dir$f";
/mpsoc/perl_gui/lib/simulate/custom-traffic/hot100
0,0 → 1,16
% source id , destination id, injection ratio , average packet size, minimum packet size, maximum packet size, packet num, initial weight
0, 15, 90, 4, 4, 4, 2000, 1
1, 15, 90, 4, 4, 4, 2000, 1
2, 15, 90, 4, 4, 4, 2000, 1
3, 15, 90, 4, 4, 4, 2000, 1
4, 15, 90, 4, 4, 4, 2000, 1
5, 15, 90, 4, 4, 4, 2000, 1
6, 15, 90, 4, 4, 4, 2000, 1
7, 15, 90, 4, 4, 4, 2000, 1
8, 15, 90, 4, 4, 4, 2000, 1
9, 15, 90, 4, 4, 4, 2000, 1
10, 15, 90, 4, 4, 4, 2000, 1
11, 15, 90, 4, 4, 4, 2000, 1
12, 15, 90, 4, 4, 4, 2000, 1
13, 15, 90, 4, 4, 4, 2000, 1
14, 15, 90, 4, 4, 4, 2000, 1
/mpsoc/perl_gui/lib/simulate/embedded_app_graphs/test.app
2,8 → 2,18
5
 
# task_i (to) task_j bandwidth_requirement (Mbps, unidirection)
0 1 30
0 2 10
1 3 40
1 4 5
2 4 20
0 8 10
1 8 10
2 8 10
3 8 10
4 8 10
5 8 10
6 8 10
7 14 10
8 14 10
9 14 10
10 14 10
11 14 10
12 14 10
13 14 10
 
/mpsoc/perl_gui/lib/soc/tutorial.SOC File deleted
/mpsoc/perl_gui/lib/soc/Tutorial_lm32.SOC
0,0 → 1,1133
#######################################################################
## File: Tutorial_lm32.SOC
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.8.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$soc = bless( {
'global_param' => {
'CORE_ID' => 0
},
'clk_source0' => {},
'compile_pin_range_lsb' => {
'hex1_port_o' => '0',
'source_reset_in' => '0',
'ext_int_ext_int_i' => '1',
'hex0_port_o' => '0'
},
'compile' => {
'type' => 'Modelsim',
'quartus_bin' => '/home/alireza/altera/13.0sp1/quartus/bin',
'board' => 'DE2_115',
'modelsim_bin' => '/home/alireza/altera/modeltech/bin'
},
'hdl_files' => undef,
'dual_port_ram0' => {
'version' => 6
},
'wishbone_bus0' => {},
'gpo0' => {},
'gpo1' => {},
'ext_int0' => {},
'compile_pin' => {
'hex0_port_o' => 'HEX0',
'ext_int_ext_int_i' => 'KEY',
'source_clk_in' => 'CLOCK_50',
'hex1_port_o' => 'HEX1',
'source_reset_in' => 'KEY',
'lm32_en_i' => '*VCC'
},
'top_ip' => bless( {
'interface' => {
'plug:clk[0]' => {
'ports' => {
'source_clk_in' => {
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'clk_i',
'range' => ''
}
}
},
'plug:reset[0]' => {
'ports' => {
'source_reset_in' => {
'intfc_port' => 'reset_i',
'range' => '',
'type' => 'input',
'instance_name' => 'clk_source0'
}
}
},
'plug:enable[0]' => {
'ports' => {
'lm32_en_i' => {
'type' => 'input',
'instance_name' => 'lm320',
'intfc_port' => 'enable_i',
'range' => ''
}
}
},
'IO' => {
'ports' => {
'hex0_port_o' => {
'instance_name' => 'gpo0',
'type' => 'output',
'range' => 'hex0_PORT_WIDTH-1 : 0',
'intfc_port' => 'IO'
},
'hex1_port_o' => {
'type' => 'output',
'instance_name' => 'gpo1',
'range' => 'hex1_PORT_WIDTH-1 : 0',
'intfc_port' => 'IO'
},
'ext_int_ext_int_i' => {
'type' => 'input',
'instance_name' => 'ext_int0',
'intfc_port' => 'IO',
'range' => 'ext_int_EXT_INT_NUM-1 : 0'
}
}
}
},
'ports' => {
'lm32_en_i' => {
'intfc_port' => 'enable_i',
'range' => '',
'intfc_name' => 'plug:enable[0]',
'type' => 'input',
'instance_name' => 'lm320'
},
'hex1_port_o' => {
'range' => 'hex1_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO',
'intfc_port' => 'IO',
'instance_name' => 'gpo1',
'type' => 'output'
},
'source_reset_in' => {
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'intfc_port' => 'reset_i'
},
'ext_int_ext_int_i' => {
'type' => 'input',
'instance_name' => 'ext_int0',
'range' => 'ext_int_EXT_INT_NUM-1 : 0',
'intfc_name' => 'IO',
'intfc_port' => 'IO'
},
'source_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'intfc_port' => 'clk_i',
'instance_name' => 'clk_source0',
'type' => 'input'
},
'hex0_port_o' => {
'type' => 'output',
'instance_name' => 'gpo0',
'intfc_name' => 'IO',
'range' => 'hex0_PORT_WIDTH-1 : 0',
'intfc_port' => 'IO'
}
},
'instance_ids' => {
'clk_source0' => {
'category' => 'Source',
'ports' => {
'source_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'intfc_port' => 'clk_i',
'type' => 'input'
},
'source_reset_in' => {
'type' => 'input',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'intfc_port' => 'reset_i'
}
},
'module_name' => 'clk_source',
'module' => 'clk_source',
'instance' => 'source'
},
'ext_int0' => {
'instance' => 'ext_int',
'module' => 'ext_int',
'category' => 'Interrupt',
'module_name' => 'ext_int',
'ports' => {
'ext_int_ext_int_i' => {
'range' => 'ext_int_EXT_INT_NUM-1 : 0',
'intfc_name' => 'IO',
'intfc_port' => 'IO',
'type' => 'input'
}
}
},
'timer0' => {
'instance' => 'timer',
'module' => 'timer',
'module_name' => 'timer',
'category' => 'Timer'
},
'dual_port_ram0' => {
'category' => 'RAM',
'module_name' => 'wb_dual_port_ram',
'module' => 'dual_port_ram',
'instance' => 'ram'
},
'wishbone_bus0' => {
'module' => 'wishbone_bus',
'instance' => 'bus',
'category' => 'Bus',
'module_name' => 'wishbone_bus'
},
'gpo0' => {
'ports' => {
'hex0_port_o' => {
'intfc_port' => 'IO',
'range' => 'hex0_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO',
'type' => 'output'
}
},
'parameters' => {
'hex0_PORT_WIDTH' => {
'info' => 'output port width',
'default' => 7,
'type' => 'Spin-button',
'global_param' => 'Parameter',
'content' => '1,32,1',
'redefine_param' => 1
}
},
'module_name' => 'gpo',
'category' => 'GPIO',
'module' => 'gpo',
'instance' => 'hex0'
},
'lm320' => {
'module_name' => 'lm32',
'ports' => {
'lm32_en_i' => {
'range' => '',
'intfc_name' => 'plug:enable[0]',
'intfc_port' => 'enable_i',
'type' => 'input'
}
},
'category' => 'Processor',
'instance' => 'lm32',
'module' => 'lm32'
},
'jtag_wb0' => {
'instance' => 'jtag_wb',
'module' => 'jtag_wb',
'module_name' => 'vjtag_wb',
'category' => 'JTAG'
},
'gpo1' => {
'category' => 'GPIO',
'module_name' => 'gpo',
'parameters' => {
'hex1_PORT_WIDTH' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'content' => '1,32,1',
'default' => 7,
'type' => 'Spin-button',
'info' => 'output port width'
}
},
'ports' => {
'hex1_port_o' => {
'intfc_name' => 'IO',
'range' => 'hex1_PORT_WIDTH-1 : 0',
'intfc_port' => 'IO',
'type' => 'output'
}
},
'instance' => 'hex1',
'module' => 'gpo'
}
}
}, 'ip_gen' ),
'timer0' => {},
'gui_status' => {
'status' => 'save_project',
'timeout' => 0
},
'instance_order' => [
'clk_source0',
'wishbone_bus0',
'gpo0',
'gpo1',
'ext_int0',
'timer0',
'jtag_wb0',
'lm320',
'dual_port_ram0'
],
'modules' => {},
'compile_pin_range_hsb' => {
'hex0_port_o' => '6',
'ext_int_ext_int_i' => '2',
'hex1_port_o' => '6'
},
'lm320' => {},
'compile_pin_pos' => {
'hex0_port_o' => [
7,
0
],
'hex1_port_o' => [
8,
0
],
'source_reset_in' => [
13,
0
],
'ext_int_ext_int_i' => [
13,
0
],
'source_clk_in' => [
4,
0
],
'lm32_en_i' => [
2,
0
]
},
'jtag_wb0' => {},
'soc_name' => 'Tutorial_lm32',
'compile_assign_type' => {
'source_reset_in' => 'Negate(~)',
'ext_int_ext_int_i' => 'Direct',
'source_clk_in' => 'Direct',
'lm32_en_i' => 'Direct'
},
'instances' => {
'gpo1' => {
'module_name' => 'gpo',
'instance_name' => 'hex1',
'plugs' => {
'wb_slave' => {
'nums' => {
'0' => {
'end' => 2432696383,
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O',
'base' => 2432696352,
'connect_socket' => 'wb_slave',
'connect_socket_num' => '1',
'name' => 'wb',
'connect_id' => 'wishbone_bus0',
'width' => 5
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
},
'clk' => {
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_socket' => 'clk',
'name' => 'clk',
'connect_id' => 'clk_source0'
}
},
'connection_num' => undef,
'value' => 1,
'type' => 'num'
},
'reset' => {
'nums' => {
'0' => {
'name' => 'reset',
'connect_socket' => 'reset',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0'
}
},
'connection_num' => undef,
'value' => 1,
'type' => 'num'
}
},
'sockets' => {},
'parameters_order' => [
'PORT_WIDTH',
'Aw',
'TAGw',
'SELw',
'Dw'
],
'category' => 'GPIO',
'gpo1' => {},
'parameters' => {
'TAGw' => {
'value' => ' 3'
},
'SELw' => {
'value' => ' 4'
},
'Dw' => {
'value' => 'PORT_WIDTH'
},
'PORT_WIDTH' => {
'value' => 7
},
'Aw' => {
'value' => ' 2'
}
},
'module' => 'gpo'
},
'jtag_wb0' => {
'plugs' => {
'reset' => {
'nums' => {
'0' => {
'name' => 'reset',
'connect_socket_num' => '0',
'connect_socket' => 'reset',
'connect_id' => 'clk_source0'
}
},
'value' => 1,
'connection_num' => undef,
'type' => 'num'
},
'wb_master' => {
'type' => 'num',
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_id' => 'wishbone_bus0',
'connect_socket' => 'wb_master',
'connect_socket_num' => '0',
'name' => 'wbm'
}
}
},
'clk' => {
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'connect_socket' => 'clk',
'name' => 'clk'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
}
},
'instance_name' => 'jtag_wb',
'module_name' => 'vjtag_wb',
'parameters_order' => [
'DW',
'AW',
'S_Aw',
'M_Aw',
'TAGw',
'SELw',
'VJTAG_INDEX'
],
'sockets' => {},
'module' => 'jtag_wb',
'category' => 'JTAG',
'parameters' => {
'SELw' => {
'value' => ' 4'
},
'S_Aw' => {
'value' => ' 7'
},
'AW' => {
'value' => '32'
},
'TAGw' => {
'value' => ' 3'
},
'DW' => {
'value' => '32'
},
'VJTAG_INDEX' => {
'value' => 'CORE_ID'
},
'M_Aw' => {
'value' => ' 32'
}
},
'jtag_wb0' => {}
},
'lm320' => {
'parameters_order' => [
'INTR_NUM',
'CFG_PL_MULTIPLY',
'CFG_PL_BARREL_SHIFT',
'CFG_SIGN_EXTEND',
'CFG_MC_DIVIDE'
],
'sockets' => {
'interrupt_peripheral' => {
'nums' => {
'0' => {
'name' => 'interrupt_peripheral'
}
},
'value' => 'INTR_NUM',
'connection_num' => 'single connection',
'type' => 'param'
}
},
'plugs' => {
'reset' => {
'type' => 'num',
'value' => 1,
'connection_num' => undef,
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'connect_socket' => 'reset',
'name' => 'reset'
}
}
},
'enable' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'IO',
'name' => 'enable',
'connect_socket_num' => undef,
'connect_socket' => undef
}
}
},
'wb_master' => {
'type' => 'num',
'connection_num' => undef,
'value' => 2,
'nums' => {
'1' => {
'connect_id' => 'wishbone_bus0',
'name' => 'dwb',
'connect_socket_num' => '2',
'connect_socket' => 'wb_master'
},
'0' => {
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '1',
'connect_socket' => 'wb_master',
'name' => 'iwb'
}
}
},
'clk' => {
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_socket' => 'clk',
'name' => 'clk',
'connect_id' => 'clk_source0'
}
},
'connection_num' => undef,
'value' => 1,
'type' => 'num'
}
},
'instance_name' => 'lm32',
'module_name' => 'lm32',
'lm320' => {},
'parameters' => {
'CFG_PL_MULTIPLY' => {
'value' => '"ENABLED"'
},
'CFG_PL_BARREL_SHIFT' => {
'value' => '"ENABLED"'
},
'CFG_MC_DIVIDE' => {
'value' => '"DISABLED"'
},
'INTR_NUM' => {
'value' => '32'
},
'CFG_SIGN_EXTEND' => {
'value' => '"ENABLED"'
}
},
'category' => 'Processor',
'module' => 'lm32'
},
'gpo0' => {
'category' => 'GPIO',
'parameters' => {
'TAGw' => {
'value' => ' 3'
},
'SELw' => {
'value' => ' 4'
},
'Dw' => {
'value' => 'PORT_WIDTH'
},
'PORT_WIDTH' => {
'value' => 7
},
'Aw' => {
'value' => ' 2'
}
},
'module' => 'gpo',
'gpo0' => {},
'sockets' => {},
'parameters_order' => [
'PORT_WIDTH',
'Aw',
'TAGw',
'SELw',
'Dw'
],
'instance_name' => 'hex0',
'module_name' => 'gpo',
'plugs' => {
'reset' => {
'nums' => {
'0' => {
'name' => 'reset',
'connect_socket_num' => '0',
'connect_socket' => 'reset',
'connect_id' => 'clk_source0'
}
},
'value' => 1,
'connection_num' => undef,
'type' => 'num'
},
'clk' => {
'type' => 'num',
'value' => 1,
'connection_num' => undef,
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'name' => 'clk',
'connect_socket_num' => '0',
'connect_socket' => 'clk'
}
}
},
'wb_slave' => {
'nums' => {
'0' => {
'name' => 'wb',
'connect_socket' => 'wb_slave',
'connect_socket_num' => '0',
'base' => 2432696320,
'end' => 2432696351,
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O',
'width' => 5,
'connect_id' => 'wishbone_bus0'
}
},
'value' => 1,
'connection_num' => undef,
'type' => 'num'
}
}
},
'wishbone_bus0' => {
'sockets' => {
'wb_master' => {
'nums' => {
'0' => {
'name' => 'wb_master'
}
},
'value' => 'M',
'connection_num' => 'single connection',
'type' => 'param'
},
'wb_addr_map' => {
'nums' => {
'0' => {
'name' => 'wb_addr_map'
}
},
'value' => 1,
'connection_num' => 'single connection',
'type' => 'num'
},
'wb_slave' => {
'connection_num' => 'single connection',
'value' => 'S',
'type' => 'param',
'nums' => {
'0' => {
'name' => 'wb_slave'
}
}
}
},
'parameters_order' => [
'M',
'S',
'Dw',
'Aw',
'SELw',
'TAGw',
'CTIw',
'BTEw'
],
'instance_name' => 'bus',
'module_name' => 'wishbone_bus',
'plugs' => {
'clk' => {
'type' => 'num',
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'name' => 'clk',
'connect_socket' => 'clk',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0'
}
}
},
'reset' => {
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket' => 'reset',
'connect_socket_num' => '0',
'name' => 'reset'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
}
},
'category' => 'Bus',
'parameters' => {
'TAGw' => {
'value' => '3'
},
'SELw' => {
'value' => 'Dw/8'
},
'Aw' => {
'value' => '32'
},
'M' => {
'value' => 3
},
'Dw' => {
'value' => '32'
},
'BTEw' => {
'value' => '2 '
},
'CTIw' => {
'value' => '3'
},
'S' => {
'value' => 6
}
},
'wishbone_bus0' => {},
'module' => 'wishbone_bus'
},
'dual_port_ram0' => {
'instance_name' => 'ram',
'module_name' => 'wb_dual_port_ram',
'plugs' => {
'reset' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'reset',
'connect_socket' => 'reset',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0'
}
}
},
'clk' => {
'type' => 'num',
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_socket' => 'clk',
'name' => 'clk',
'connect_id' => 'clk_source0'
}
}
},
'wb_slave' => {
'type' => 'num',
'value' => 2,
'connection_num' => undef,
'nums' => {
'0' => {
'addr' => '0x0000_0000 0x3fff_ffff RAM',
'end' => 16383,
'base' => 0,
'name' => 'wb_a',
'connect_socket_num' => '4',
'connect_socket' => 'wb_slave',
'connect_id' => 'wishbone_bus0',
'width' => 'WB_Aw'
},
'1' => {
'addr' => '0x0000_0000 0x3fff_ffff RAM',
'end' => 32767,
'base' => 16384,
'connect_socket' => 'wb_slave',
'connect_socket_num' => '5',
'name' => 'wb_b',
'connect_id' => 'wishbone_bus0',
'width' => 'WB_Aw'
}
}
}
},
'sockets' => {},
'parameters_order' => [
'Dw',
'Aw',
'BYTE_WR_EN',
'FPGA_VENDOR',
'TAGw',
'SELw',
'CTIw',
'BTEw',
'WB_Aw',
'RAM_INDEX',
'PORT_A_BURST_MODE',
'PORT_B_BURST_MODE',
'INITIAL_EN',
'MEM_CONTENT_FILE_NAME',
'INIT_FILE_PATH'
],
'module' => 'dual_port_ram',
'dual_port_ram0' => {},
'parameters' => {
'PORT_B_BURST_MODE' => {
'value' => '"ENABLED"'
},
'Dw' => {
'value' => '32'
},
'INITIAL_EN' => {
'value' => '"YES"'
},
'BYTE_WR_EN' => {
'value' => '"YES"'
},
'CTIw' => {
'value' => '3'
},
'FPGA_VENDOR' => {
'value' => '"GENERIC"'
},
'RAM_INDEX' => {
'value' => 'CORE_ID'
},
'BTEw' => {
'value' => '2'
},
'WB_Aw' => {
'value' => 'Aw+2'
},
'MEM_CONTENT_FILE_NAME' => {
'value' => '"ram0"'
},
'SELw' => {
'value' => 'Dw/8'
},
'Aw' => {
'value' => '12'
},
'PORT_A_BURST_MODE' => {
'value' => '"ENABLED"'
},
'TAGw' => {
'value' => '3'
},
'INIT_FILE_PATH' => {
'value' => 'SW_LOC'
}
},
'category' => 'RAM'
},
'timer0' => {
'instance_name' => 'timer',
'module_name' => 'timer',
'plugs' => {
'interrupt_peripheral' => {
'value' => 1,
'connection_num' => undef,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'lm320',
'name' => 'interrupt_peripheral',
'connect_socket' => 'interrupt_peripheral',
'connect_socket_num' => '1'
}
}
},
'clk' => {
'nums' => {
'0' => {
'name' => 'clk',
'connect_socket_num' => '0',
'connect_socket' => 'clk',
'connect_id' => 'clk_source0'
}
},
'connection_num' => undef,
'value' => 1,
'type' => 'num'
},
'reset' => {
'type' => 'num',
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_socket' => 'reset',
'name' => 'reset',
'connect_id' => 'clk_source0'
}
}
},
'wb_slave' => {
'nums' => {
'0' => {
'end' => 2516582431,
'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl',
'base' => 2516582400,
'name' => 'wb',
'connect_socket' => 'wb_slave',
'connect_socket_num' => '3',
'connect_id' => 'wishbone_bus0',
'width' => 5
}
},
'type' => 'num',
'connection_num' => undef,
'value' => 1
}
},
'sockets' => {},
'timer0' => {},
'parameters_order' => [
'CNTw',
'Dw',
'Aw',
'TAGw',
'SELw'
],
'module' => 'timer',
'parameters' => {
'CNTw' => {
'value' => '32 '
},
'TAGw' => {
'value' => '3'
},
'Dw' => {
'value' => ' 32'
},
'Aw' => {
'value' => ' 3'
},
'SELw' => {
'value' => ' 4'
}
},
'category' => 'Timer'
},
'ext_int0' => {
'module' => 'ext_int',
'category' => 'Interrupt',
'parameters' => {
'EXT_INT_NUM' => {
'value' => 2
},
'TAGw' => {
'value' => '3'
},
'Dw' => {
'value' => '32'
},
'Aw' => {
'value' => '3'
},
'SELw' => {
'value' => '4'
}
},
'ext_int0' => {},
'instance_name' => 'ext_int',
'module_name' => 'ext_int',
'plugs' => {
'wb_slave' => {
'value' => 1,
'connection_num' => undef,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket' => 'wb_slave',
'connect_socket_num' => '2',
'name' => 'wb',
'base' => 2650800128,
'end' => 2650800159,
'addr' => '0x9e00_0000 0x9eff_ffff IDE Controller',
'width' => 5,
'connect_id' => 'wishbone_bus0'
}
}
},
'clk' => {
'value' => 1,
'connection_num' => undef,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_socket' => 'clk',
'name' => 'clk',
'connect_id' => 'clk_source0'
}
}
},
'interrupt_peripheral' => {
'nums' => {
'0' => {
'connect_id' => 'lm320',
'connect_socket' => 'interrupt_peripheral',
'connect_socket_num' => '0',
'name' => 'interrupt'
}
},
'connection_num' => undef,
'value' => 1,
'type' => 'num'
},
'reset' => {
'type' => 'num',
'value' => 1,
'connection_num' => undef,
'nums' => {
'0' => {
'name' => 'reset',
'connect_socket_num' => '0',
'connect_socket' => 'reset',
'connect_id' => 'clk_source0'
}
}
}
},
'sockets' => {},
'parameters_order' => [
'Dw',
'Aw',
'TAGw',
'SELw',
'EXT_INT_NUM'
]
},
'clk_source0' => {
'parameters' => {},
'category' => 'Source',
'module' => 'clk_source',
'module_name' => 'clk_source',
'instance_name' => 'source',
'plugs' => {
'reset' => {
'nums' => {
'0' => {
'connect_socket' => undef,
'connect_socket_num' => undef,
'name' => 'reset',
'connect_id' => 'IO'
}
},
'type' => 'num',
'connection_num' => undef,
'value' => 1
},
'clk' => {
'value' => 1,
'connection_num' => undef,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'IO',
'connect_socket_num' => undef,
'connect_socket' => undef,
'name' => 'clk'
}
}
}
},
'sockets' => {
'clk' => {
'nums' => {
'0' => {
'name' => 'clk'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => 'multi connection'
},
'reset' => {
'nums' => {
'0' => {
'name' => 'reset'
}
},
'type' => 'num',
'connection_num' => 'multi connection',
'value' => 1
}
},
'parameters_order' => [],
'clk_source0' => {}
}
}
}, 'soc' );
/mpsoc/perl_gui/lib/soc/aemb_tile.SOC
0,0 → 1,1692
#######################################################################
## File: aemb_tile.SOC
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.8.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$soc = bless( {
'dma0' => {
'version' => 4
},
'modules' => {},
'mor1kx0' => {
'version' => 13
},
'ni_master0' => {
'version' => 38
},
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'single_port_ram0' => {
'version' => 22
},
'hdl_files' => undef,
'clk_source0' => {
'version' => 0
},
'top_ip' => bless( {
'instance_ids' => {
'aeMB0' => {
'module' => 'aeMB',
'localparam' => {
'cpu_AEMB_ICH' => {
'default' => ' 11',
'info' => undef,
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'cpu_AEMB_XWB' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'default' => ' 7',
'info' => undef
},
'cpu_AEMB_DWB' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'content' => '',
'info' => undef,
'default' => ' 32'
},
'cpu_AEMB_IDX' => {
'info' => undef,
'default' => ' 6',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'cpu_AEMB_IWB' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'default' => ' 32',
'info' => undef
},
'cpu_AEMB_BSF' => {
'info' => undef,
'default' => ' 1',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'content' => ''
},
'cpu_AEMB_MUL' => {
'info' => undef,
'default' => ' 1',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'type' => 'Fixed'
}
},
'category' => 'Processor',
'ports' => {
'cpu_sys_ena_i' => {
'type' => 'input',
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'range' => ''
},
'cpu_sys_int_i' => {
'intfc_port' => 'int_i',
'intfc_name' => 'socket:interrupt_cpu[0]',
'type' => 'input',
'range' => ''
}
},
'instance' => 'cpu',
'module_name' => 'aeMB_top'
},
'single_port_ram0' => {
'category' => 'RAM',
'parameters' => {
'ram_Aw' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Spin-button',
'content' => '4,31,1',
'info' => 'Memory address width',
'default' => 14
},
'ram_Dw' => {
'info' => 'Memory data width in Bits.',
'default' => '32',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => '8,1024,1',
'type' => 'Spin-button'
}
},
'localparam' => {
'ram_JTAG_CONNECT' => {
'type' => 'Combo-box',
'content' => '"DISABLED", "JTAG_WB" , "ALTERA_IMCE"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '"DISABLED"',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. '
},
'ram_BURST_MODE' => {
'content' => '"DISABLED","ENABLED"',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'default' => '"ENABLED"'
},
'ram_JTAG_INDEX' => {
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
',
'default' => 'CORE_ID',
'content' => '',
'type' => 'Entry',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_INIT_FILE_PATH' => {
'default' => 'SW_LOC',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => ''
},
'ram_INITIAL_EN' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Combo-box',
'content' => '"YES","NO"',
'default' => '"YES"',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.'
},
'ram_BTEw' => {
'default' => '2',
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => ''
},
'ram_CTIw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'content' => '',
'info' => 'Parameter',
'default' => '3'
},
'ram_BYTE_WR_EN' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"YES","NO"',
'type' => 'Combo-box',
'info' => 'Byte enable',
'default' => '"YES"'
},
'ram_FPGA_VENDOR' => {
'default' => '"ALTERA"',
'info' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Combo-box',
'content' => '"ALTERA","GENERIC"'
},
'ram_MEM_CONTENT_FILE_NAME' => {
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
bin: raw binary format . It will be used by JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'default' => '"ram0"',
'type' => 'Entry',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_TAGw' => {
'info' => 'Parameter',
'default' => '3',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_SELw' => {
'type' => 'Fixed',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => 'ram_Dw/8',
'info' => 'Parameter'
}
},
'module' => 'single_port_ram',
'module_name' => 'wb_single_port_ram',
'instance' => 'ram'
},
'clk_source0' => {
'instance' => 'ss',
'module_name' => 'clk_source',
'ports' => {
'ss_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i',
'type' => 'input',
'range' => ''
},
'ss_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'intfc_port' => 'reset_i',
'type' => 'input',
'range' => ''
}
},
'category' => 'Source',
'module' => 'clk_source'
},
'ni_master0' => {
'localparam' => {
'ni_SELw' => {
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '4'
},
'ni_CLASS_HDR_WIDTH' => {
'info' => 'Parameter',
'default' => '8',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'type' => 'Fixed'
},
'ni_S_Aw' => {
'default' => '8',
'info' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ni_CRC_EN' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"YES","NO"',
'type' => 'Combo-box',
'default' => '"NO"',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. '
},
'ni_ROUTING_HDR_WIDTH' => {
'default' => '8',
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ni_MAX_TRANSACTION_WIDTH' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button',
'content' => '4,32,1',
'default' => '13',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.'
},
'ni_DST_ADR_HDR_WIDTH' => {
'info' => 'Parameter',
'default' => '8',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'type' => 'Fixed'
},
'ni_Xw' => {
'info' => undef,
'default' => 'log2(ni_NX)',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 0,
'global_param' => 'Localparam'
},
'ni_SRC_ADR_HDR_WIDTH' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'default' => '8',
'info' => 'Parameter'
},
'ni_TAGw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'type' => 'Fixed',
'default' => '3',
'info' => 'Parameter'
},
'ni_Fw' => {
'redefine_param' => 0,
'global_param' => 'Localparam',
'content' => '',
'type' => 'Fixed',
'info' => undef,
'default' => '2+ni_V+ni_Fpay'
},
'ni_Yw' => {
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 0,
'default' => 'log2(ni_NY)',
'info' => undef
},
'ni_M_Aw' => {
'info' => 'Parameter',
'default' => '32',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => 'Dw'
},
'ni_Dw' => {
'content' => '32,256,8',
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '32',
'info' => 'wishbone_bus data width in bits.'
},
'ni_MAX_BURST_SIZE' => {
'type' => 'Combo-box',
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '16',
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. '
}
},
'parameters' => {
'ni_DEBUG_EN' => {
'info' => 'Parameter',
'default' => '1',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ni_NX' => {
'default' => 2,
'info' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ni_C' => {
'default' => 2,
'info' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ni_V' => {
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '2'
},
'ni_ROUTE_NAME' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed',
'content' => '',
'info' => 'Parameter',
'default' => '"XY"'
},
'ni_Fpay' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'default' => '32',
'info' => 'Parameter'
},
'ni_NY' => {
'default' => ' 2',
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ni_B' => {
'default' => '4',
'info' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'ni_TOPOLOGY' => {
'default' => '"MESH"',
'info' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1
}
},
'category' => 'NoC',
'module' => 'ni_master',
'ports' => {
'ni_flit_out' => {
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out',
'type' => 'output',
'range' => 'ni_Fw-1 : 0'
},
'ni_credit_out' => {
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_out',
'type' => 'output'
},
'ni_credit_in' => {
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_in',
'range' => 'ni_V-1 : 0'
},
'ni_current_x' => {
'range' => 'ni_Xw-1 : 0',
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_x'
},
'ni_current_y' => {
'range' => 'ni_Yw-1 : 0',
'intfc_port' => 'current_y',
'intfc_name' => 'socket:ni[0]',
'type' => 'input'
},
'ni_irq' => {
'intfc_name' => 'plug:interrupt_peripheral[0]',
'intfc_port' => 'int_o',
'type' => 'output',
'range' => ''
},
'ni_flit_in' => {
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in',
'type' => 'input'
},
'ni_flit_out_wr' => {
'type' => 'output',
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'range' => ''
},
'ni_flit_in_wr' => {
'range' => '',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in_wr',
'type' => 'input'
}
},
'instance' => 'ni',
'module_name' => 'ni_master'
},
'jtag_uart0' => {
'instance' => 'uart',
'module_name' => 'jtag_uart_wb',
'ports' => {
'uart_RxD_ready_sim' => {
'range' => '',
'intfc_port' => 'RxD_ready_sim',
'intfc_name' => 'socket:RxD_sim[0]',
'type' => 'output'
},
'uart_irq' => {
'type' => 'output',
'intfc_name' => 'plug:interrupt_peripheral[0]',
'intfc_port' => 'int_o',
'range' => ''
},
'uart_RxD_wr_sim' => {
'intfc_port' => 'RxD_wr_sim',
'intfc_name' => 'socket:RxD_sim[0]',
'type' => 'input',
'range' => ''
},
'uart_RxD_din_sim' => {
'range' => '7:0 ',
'intfc_name' => 'socket:RxD_sim[0]',
'intfc_port' => 'RxD_din_sim',
'type' => 'input'
}
},
'module' => 'jtag_uart',
'category' => 'Communication',
'localparam' => {
'uart_FPGA_VENDOR' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => ' "ALTERA"',
'type' => 'Combo-box',
'info' => 'FPGA VENDOR name. Only Altera FPGA is supported. Currently the Generic serial port is not supported. ',
'default' => ' "ALTERA"'
},
'uart_SIM_WAIT_COUNT' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button',
'content' => '2,100000,1',
'default' => '1000',
'info' => 'This parameter is valid only in simulation.
If internal buffer has a data, the internal timer incremented by one in each clock cycle. If the timer reaches the WAIT_COUNT value, it writes the buffer value on the simulator terminal.'
},
'uart_SIM_BUFFER_SIZE' => {
'info' => 'Internal buffer size.
This parameter is valid only in simulation.
If internal buffer overflows, the buffer content are displayed on simulator terminal.',
'default' => '100',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Spin-button',
'content' => '10,10000,1'
}
}
},
'wishbone_bus0' => {
'instance' => 'bus',
'module_name' => 'wishbone_bus',
'localparam' => {
'bus_Dw' => {
'content' => '8,512,8',
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '32',
'info' => 'The wishbone Bus data width in bits.'
},
'bus_Aw' => {
'info' => 'The wishbone Bus address width',
'default' => '32',
'type' => 'Spin-button',
'content' => '4,128,1',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'bus_CTIw' => {
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '3',
'info' => undef
},
'bus_TAGw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'info' => undef,
'default' => '3'
},
'bus_M' => {
'info' => 'Number of wishbone master interface',
'default' => ' 4',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Spin-button',
'content' => '1,256,1'
},
'bus_BTEw' => {
'info' => undef,
'default' => '2 ',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'content' => ''
},
'bus_S' => {
'default' => 3,
'info' => 'Number of wishbone slave interface',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button',
'content' => '1,256,1'
},
'bus_SELw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'info' => undef,
'default' => 'bus_Dw/8'
}
},
'category' => 'Bus',
'module' => 'wishbone_bus'
}
},
'interface' => {
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'range' => '',
'instance_name' => 'clk_source0'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_flit_in_wr' => {
'range' => '',
'intfc_port' => 'flit_in_wr',
'type' => 'input',
'instance_name' => 'ni_master0'
},
'ni_flit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_flit_out_wr' => {
'instance_name' => 'ni_master0',
'range' => '',
'intfc_port' => 'flit_out_wr',
'type' => 'output'
},
'ni_current_y' => {
'instance_name' => 'ni_master0',
'type' => 'input',
'intfc_port' => 'current_y',
'range' => 'ni_Yw-1 : 0'
},
'ni_credit_in' => {
'range' => 'ni_V-1 : 0',
'intfc_port' => 'credit_in',
'type' => 'input',
'instance_name' => 'ni_master0'
},
'ni_current_x' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'current_x',
'type' => 'input',
'range' => 'ni_Xw-1 : 0'
},
'ni_credit_out' => {
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'credit_out',
'range' => 'ni_V-1 : 0'
},
'ni_flit_out' => {
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'flit_out',
'range' => 'ni_Fw-1 : 0'
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'clk_i',
'range' => ''
}
}
},
'socket:RxD_sim[0]' => {
'ports' => {
'uart_RxD_ready_sim' => {
'type' => 'output',
'intfc_port' => 'RxD_ready_sim',
'range' => '',
'instance_name' => 'jtag_uart0'
},
'uart_RxD_din_sim' => {
'range' => '7:0 ',
'intfc_port' => 'RxD_din_sim',
'type' => 'input',
'instance_name' => 'jtag_uart0'
},
'uart_RxD_wr_sim' => {
'type' => 'input',
'intfc_port' => 'RxD_wr_sim',
'range' => '',
'instance_name' => 'jtag_uart0'
}
}
},
'socket:interrupt_cpu[0]' => {
'ports' => {
'cpu_sys_int_i' => {
'type' => 'input',
'intfc_port' => 'int_i',
'range' => '',
'instance_name' => 'aeMB0'
}
}
},
'plug:interrupt_peripheral[0]' => {
'ports' => {
'uart_irq' => {
'instance_name' => 'jtag_uart0',
'range' => '',
'type' => 'output',
'intfc_port' => 'int_o'
},
'ni_irq' => {
'instance_name' => 'ni_master0',
'range' => '',
'intfc_port' => 'int_o',
'type' => 'output'
}
}
},
'plug:enable[0]' => {
'ports' => {
'cpu_sys_ena_i' => {
'range' => '',
'intfc_port' => 'enable_i',
'type' => 'input',
'instance_name' => 'aeMB0'
}
}
}
},
'ports' => {
'ni_flit_out_wr' => {
'range' => '',
'type' => 'output',
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0'
},
'ni_flit_in' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'range' => 'ni_Fw-1 : 0'
},
'uart_RxD_ready_sim' => {
'instance_name' => 'jtag_uart0',
'intfc_port' => 'RxD_ready_sim',
'intfc_name' => 'socket:RxD_sim[0]',
'type' => 'output',
'range' => ''
},
'uart_RxD_wr_sim' => {
'type' => 'input',
'intfc_name' => 'socket:RxD_sim[0]',
'intfc_port' => 'RxD_wr_sim',
'range' => '',
'instance_name' => 'jtag_uart0'
},
'ni_current_x' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Xw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_x',
'type' => 'input'
},
'ni_credit_in' => {
'range' => 'ni_V-1 : 0',
'type' => 'input',
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0'
},
'ni_flit_out' => {
'range' => 'ni_Fw-1 : 0',
'type' => 'output',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out',
'instance_name' => 'ni_master0'
},
'ss_clk_in' => {
'range' => '',
'type' => 'input',
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i',
'instance_name' => 'clk_source0'
},
'ni_flit_in_wr' => {
'instance_name' => 'ni_master0',
'range' => '',
'type' => 'input',
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]'
},
'cpu_sys_int_i' => {
'instance_name' => 'aeMB0',
'range' => '',
'type' => 'input',
'intfc_name' => 'socket:interrupt_cpu[0]',
'intfc_port' => 'int_i'
},
'ni_irq' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'int_o',
'intfc_name' => 'plug:interrupt_peripheral[0]',
'type' => 'output',
'range' => ''
},
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'type' => 'input',
'range' => '',
'instance_name' => 'clk_source0'
},
'uart_irq' => {
'instance_name' => 'jtag_uart0',
'intfc_port' => 'int_o',
'intfc_name' => 'plug:interrupt_peripheral[0]',
'type' => 'output',
'range' => ''
},
'ni_current_y' => {
'range' => 'ni_Yw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_y',
'type' => 'input',
'instance_name' => 'ni_master0'
},
'uart_RxD_din_sim' => {
'instance_name' => 'jtag_uart0',
'range' => '7:0 ',
'type' => 'input',
'intfc_port' => 'RxD_din_sim',
'intfc_name' => 'socket:RxD_sim[0]'
},
'cpu_sys_ena_i' => {
'range' => '',
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'type' => 'input',
'instance_name' => 'aeMB0'
},
'ni_credit_out' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'type' => 'output',
'range' => 'ni_V-1 : 0'
}
}
}, 'ip_gen' ),
'soc_name' => 'aemb_tile',
'instances' => {
'clk_source0' => {
'parameters_order' => [],
'sockets' => {
'clk' => {
'connection_num' => 'multi connection',
'type' => 'num',
'nums' => {
'0' => {
'name' => 'clk'
}
},
'value' => 1
},
'reset' => {
'value' => 1,
'nums' => {
'0' => {
'name' => 'reset'
}
},
'type' => 'num',
'connection_num' => 'multi connection'
}
},
'description_pdf' => undef,
'module' => 'clk_source',
'plugs' => {
'reset' => {
'nums' => {
'0' => {
'connect_id' => 'IO',
'name' => 'reset',
'connect_socket_num' => undef,
'connect_socket' => undef
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
},
'clk' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_id' => 'IO',
'name' => 'clk',
'connect_socket_num' => undef,
'connect_socket' => undef
}
},
'type' => 'num'
}
},
'parameters' => {},
'category' => 'Source',
'instance_name' => 'ss',
'module_name' => 'clk_source'
},
'aeMB0' => {
'module_name' => 'aeMB_top',
'instance_name' => 'cpu',
'category' => 'Processor',
'parameters' => {
'AEMB_ICH' => {
'value' => ' 11'
},
'AEMB_MUL' => {
'value' => ' 1'
},
'AEMB_DWB' => {
'value' => ' 32'
},
'AEMB_BSF' => {
'value' => ' 1'
},
'AEMB_IWB' => {
'value' => ' 32'
},
'HEAP_SIZE' => {
'value' => '0x400'
},
'AEMB_XWB' => {
'value' => ' 7'
},
'STACK_SIZE' => {
'value' => '0x400'
},
'AEMB_IDX' => {
'value' => ' 6'
}
},
'plugs' => {
'clk' => {
'nums' => {
'0' => {
'connect_socket' => 'clk',
'connect_id' => 'clk_source0',
'name' => 'clk',
'connect_socket_num' => '0'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
},
'wb_master' => {
'value' => 2,
'nums' => {
'0' => {
'connect_socket_num' => '2',
'connect_id' => 'wishbone_bus0',
'name' => 'iwb',
'connect_socket' => 'wb_master'
},
'1' => {
'name' => 'dwb',
'connect_socket_num' => '3',
'connect_id' => 'wishbone_bus0',
'connect_socket' => 'wb_master'
}
},
'type' => 'num',
'connection_num' => undef
},
'enable' => {
'nums' => {
'0' => {
'connect_socket_num' => undef,
'connect_id' => 'IO',
'name' => 'enable',
'connect_socket' => undef
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
},
'reset' => {
'connection_num' => undef,
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'reset',
'connect_socket' => 'reset'
}
},
'type' => 'num',
'value' => 1
}
},
'module' => 'aeMB',
'sockets' => {
'interrupt_cpu' => {
'value' => 1,
'nums' => {
'0' => {
'name' => 'interrupt_cpu'
}
},
'type' => 'num',
'connection_num' => 'single connection'
}
},
'description_pdf' => undef,
'parameters_order' => [
'AEMB_IWB',
'AEMB_DWB',
'AEMB_XWB',
'AEMB_ICH',
'AEMB_IDX',
'AEMB_BSF',
'AEMB_MUL',
'STACK_SIZE',
'HEAP_SIZE'
]
},
'single_port_ram0' => {
'instance_name' => 'ram',
'module_name' => 'wb_single_port_ram',
'description_pdf' => '/mpsoc/src_peripheral/ram/RAM.pdf',
'sockets' => {},
'parameters_order' => [
'Dw',
'Aw',
'BYTE_WR_EN',
'FPGA_VENDOR',
'JTAG_CONNECT',
'JTAG_INDEX',
'TAGw',
'SELw',
'CTIw',
'BTEw',
'WB_Aw',
'BURST_MODE',
'MEM_CONTENT_FILE_NAME',
'INITIAL_EN',
'INIT_FILE_PATH'
],
'module' => 'single_port_ram',
'category' => 'RAM',
'parameters' => {
'Aw' => {
'value' => 14
},
'FPGA_VENDOR' => {
'value' => '"ALTERA"'
},
'INIT_FILE_PATH' => {
'value' => 'SW_LOC'
},
'SELw' => {
'value' => 'Dw/8'
},
'BURST_MODE' => {
'value' => '"ENABLED"'
},
'BTEw' => {
'value' => '2'
},
'CTIw' => {
'value' => '3'
},
'WB_Aw' => {
'value' => 'Aw+2'
},
'MEM_CONTENT_FILE_NAME' => {
'value' => '"ram0"'
},
'TAGw' => {
'value' => '3'
},
'INITIAL_EN' => {
'value' => '"YES"'
},
'JTAG_INDEX' => {
'value' => 'CORE_ID'
},
'JTAG_CONNECT' => {
'value' => '"DISABLED"'
},
'Dw' => {
'value' => '32'
},
'BYTE_WR_EN' => {
'value' => '"YES"'
}
},
'plugs' => {
'clk' => {
'connection_num' => undef,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'clk',
'connect_socket' => 'clk'
}
},
'value' => 1
},
'reset' => {
'type' => 'num',
'nums' => {
'0' => {
'connect_socket' => 'reset',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'reset'
}
},
'value' => 1,
'connection_num' => undef
},
'wb_slave' => {
'type' => 'num',
'nums' => {
'0' => {
'base' => 0,
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '2',
'end' => 65535,
'name' => 'wb',
'connect_socket' => 'wb_slave',
'width' => 'WB_Aw',
'addr' => '0x0000_0000 0x3fff_ffff RAM'
}
},
'value' => 1,
'connection_num' => undef
}
}
},
'ni_master0' => {
'parameters_order' => [
'CLASS_HDR_WIDTH',
'ROUTING_HDR_WIDTH',
'DST_ADR_HDR_WIDTH',
'SRC_ADR_HDR_WIDTH',
'TOPOLOGY',
'ROUTE_NAME',
'NX',
'NY',
'C',
'V',
'B',
'Fpay',
'MAX_TRANSACTION_WIDTH',
'MAX_BURST_SIZE',
'DEBUG_EN',
'Dw',
'S_Aw',
'M_Aw',
'TAGw',
'SELw',
'Xw',
'Yw',
'Fw',
'CRC_EN'
],
'description_pdf' => '/mpsoc/src_peripheral/ni/NI.pdf',
'sockets' => {
'ni' => {
'value' => 1,
'nums' => {
'0' => {
'name' => 'ni'
}
},
'type' => 'num',
'connection_num' => 'single connection'
}
},
'module' => 'ni_master',
'parameters' => {
'Yw' => {
'value' => 'log2(NY)'
},
'DEBUG_EN' => {
'value' => '1'
},
'M_Aw' => {
'value' => '32'
},
'CRC_EN' => {
'value' => '"NO"'
},
'WEIGHTw' => {
'value' => '4'
},
'MAX_TRANSACTION_WIDTH' => {
'value' => '13'
},
'SSA_EN' => {
'value' => '"NO"'
},
'VC_REALLOCATION_TYPE' => {
'value' => '"NONATOMIC"'
},
'SELw' => {
'value' => '4'
},
'CONGESTION_INDEX' => {
'value' => 3
},
'ROUTE_NAME' => {
'value' => '"XY"'
},
'B' => {
'value' => '4'
},
'CLASS_HDR_WIDTH' => {
'value' => '8'
},
'Fw' => {
'value' => '2+V+Fpay'
},
'Dw' => {
'value' => '32'
},
'FIRST_ARBITER_EXT_P_EN' => {
'value' => 1
},
'MUX_TYPE' => {
'value' => '"BINARY"'
},
'TAGw' => {
'value' => '3'
},
'AVC_ATOMIC_EN' => {
'value' => 0
},
'SWA_ARBITER_TYPE' => {
'value' => '"RRA"'
},
'ESCAP_VC_MASK' => {
'value' => '2\'b01'
},
'Fpay' => {
'value' => '32'
},
'NX' => {
'value' => 2
},
'TOPOLOGY' => {
'value' => '"MESH"'
},
'Xw' => {
'value' => 'log2(NX)'
},
'DST_ADR_HDR_WIDTH' => {
'value' => '8'
},
'SRC_ADR_HDR_WIDTH' => {
'value' => '8'
},
'C' => {
'value' => 2
},
'ADD_PIPREG_AFTER_CROSSBAR' => {
'value' => '1\'b0'
},
'NY' => {
'value' => ' 2'
},
'ROUTING_HDR_WIDTH' => {
'value' => '8'
},
'V' => {
'value' => '2'
},
'MAX_BURST_SIZE' => {
'value' => '16'
},
'COMBINATION_TYPE' => {
'value' => '"COMB_NONSPEC"'
},
'ROUTE_SUBFUNC' => {
'value' => '"XY"'
},
'S_Aw' => {
'value' => '8'
},
'MAX_SBP_NUM ' => {
'value' => 0
}
},
'plugs' => {
'interrupt_peripheral' => {
'nums' => {
'0' => {
'name' => 'interrupt',
'connect_socket_num' => undef,
'connect_id' => 'IO',
'connect_socket' => undef
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
},
'clk' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'name' => 'clk',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'connect_socket' => 'clk'
}
},
'type' => 'num'
},
'reset' => {
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'reset',
'connect_socket' => 'reset'
}
},
'connection_num' => undef
},
'wb_master' => {
'type' => 'num',
'nums' => {
'1' => {
'connect_socket_num' => '1',
'name' => 'wb_receive',
'connect_id' => 'wishbone_bus0',
'connect_socket' => 'wb_master'
},
'0' => {
'connect_id' => 'wishbone_bus0',
'name' => 'wb_send',
'connect_socket_num' => '0',
'connect_socket' => 'wb_master'
}
},
'value' => 2,
'connection_num' => undef
},
'wb_slave' => {
'nums' => {
'0' => {
'connect_socket' => 'wb_slave',
'end' => 3087008767,
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '0',
'name' => 'wb_slave',
'base' => 3087007744,
'width' => 10,
'addr' => '0xb800_0000 0xbfff_ffff custom devices'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
}
},
'category' => 'NoC',
'instance_name' => 'ni',
'module_name' => 'ni_master'
},
'jtag_uart0' => {
'parameters_order' => [
'FPGA_VENDOR',
'SIM_BUFFER_SIZE',
'SIM_WAIT_COUNT'
],
'sockets' => {
'RxD_sim' => {
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'RxD_sim'
}
},
'connection_num' => 'single connection'
}
},
'description_pdf' => undef,
'plugs' => {
'interrupt_peripheral' => {
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'IO',
'name' => 'interrupt_peripheral',
'connect_socket_num' => undef,
'connect_socket' => undef
}
},
'value' => 1,
'connection_num' => undef
},
'clk' => {
'value' => 1,
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'clk',
'connect_socket' => 'clk'
}
},
'type' => 'num',
'connection_num' => undef
},
'reset' => {
'nums' => {
'0' => {
'connect_socket' => 'reset',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'reset'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
},
'wb_slave' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket' => 'wb_slave',
'name' => 'wb_slave',
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '1',
'base' => 2415919104,
'end' => 2415919135,
'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller',
'width' => 5
}
},
'type' => 'num'
}
},
'parameters' => {
'FPGA_VENDOR' => {
'value' => ' "ALTERA"'
},
'SIM_WAIT_COUNT' => {
'value' => '1000'
},
'SIM_BUFFER_SIZE' => {
'value' => '100'
}
},
'category' => 'Communication',
'module' => 'jtag_uart',
'module_name' => 'jtag_uart_wb',
'instance_name' => 'uart'
},
'wishbone_bus0' => {
'module' => 'wishbone_bus',
'category' => 'Bus',
'plugs' => {
'reset' => {
'nums' => {
'0' => {
'connect_socket' => 'reset',
'name' => 'reset',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
},
'clk' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket' => 'clk',
'name' => 'clk',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0'
}
},
'type' => 'num'
}
},
'parameters' => {
'S' => {
'value' => 3
},
'TAGw' => {
'value' => '3'
},
'Dw' => {
'value' => '32'
},
'CTIw' => {
'value' => '3'
},
'M' => {
'value' => ' 4'
},
'BTEw' => {
'value' => '2 '
},
'SELw' => {
'value' => 'Dw/8'
},
'Aw' => {
'value' => '32'
}
},
'description_pdf' => undef,
'sockets' => {
'wb_slave' => {
'connection_num' => 'single connection',
'nums' => {
'0' => {
'name' => 'wb_slave'
}
},
'type' => 'param',
'value' => 'S'
},
'wb_addr_map' => {
'connection_num' => 'single connection',
'type' => 'num',
'nums' => {
'0' => {
'name' => 'wb_addr_map'
}
},
'value' => 1
},
'wb_master' => {
'connection_num' => 'single connection',
'nums' => {
'0' => {
'name' => 'wb_master'
}
},
'type' => 'param',
'value' => 'M'
}
},
'parameters_order' => [
'M',
'S',
'Dw',
'Aw',
'SELw',
'TAGw',
'CTIw',
'BTEw'
],
'instance_name' => 'bus',
'module_name' => 'wishbone_bus'
}
},
'compile' => {
'quartus_bin' => '/home/alireza/intelFPGA_lite/17.1/quartus/bin',
'type' => 'Verilator',
'compilers' => 'QuartusII,Verilator,Modelsim',
'board' => 'DE2_115',
'modelsim_bin' => '/home/alireza/intelFPGA_lite/17.1/modelsim_ase/bin'
},
'sim_uart0' => {
'version' => 7
},
'instance_order' => [
'wishbone_bus0',
'single_port_ram0',
'clk_source0',
'jtag_uart0',
'ni_master0',
'aeMB0'
],
'aeMB0' => {
'version' => 2
},
'wishbone_bus0' => {
'version' => 0
},
'verilator' => {
'libs' => {
'Vtop' => 'aemb_tile.v'
}
},
'jtag_uart0' => {
'version' => 14
},
'tile_diagram' => {
'show_clk' => 1,
'show_unused' => 1,
'show_reset' => 1
},
'global_param' => {
'CORE_ID' => 0,
'SW_LOC' => '/home/alireza/mywork/mpsoc_work/SOC/aemb_tile/sw'
}
}, 'soc' );
/mpsoc/perl_gui/lib/soc/mor1k_tile.SOC
0,0 → 1,1762
#######################################################################
## File: mor1k_tile.SOC
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.8.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$soc = bless( {
'Unset-intfc' => {
'bus-snoop_en_o' => 'NC',
'bus-snoop_adr_o' => 'NC',
'uart-RxD_ready_sim' => 'NC',
'uart-RxD_wr_sim' => 'NC',
'uart-RxD_din_sim' => 'NC'
},
'mor1kx0' => {
'version' => 17
},
'wishbone_bus0' => {
'version' => 1
},
'sim_uart0' => {
'version' => 7
},
'single_port_ram0' => {
'version' => 22
},
'global_param' => {
'SW_LOC' => '/home/alireza/mywork/mpsoc_work/SOC/mor1k_tile/sw',
'CORE_ID' => 3
},
'clk_source0' => {
'version' => 0
},
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'ni_master0' => {
'version' => 40
},
'timer0' => {
'version' => 9
},
'instances' => {
'wishbone_bus0' => {
'parameters_order' => [
'M',
'S',
'Dw',
'Aw',
'SELw',
'TAGw',
'CTIw',
'BTEw'
],
'category' => 'Bus',
'description_pdf' => undef,
'module' => 'wishbone_bus',
'instance_name' => 'bus',
'parameters' => {
'BTEw' => {
'value' => '2 '
},
'Dw' => {
'value' => '32'
},
'SELw' => {
'value' => 'Dw/8'
},
'Aw' => {
'value' => '32'
},
'CTIw' => {
'value' => '3'
},
'TAGw' => {
'value' => '3'
},
'S' => {
'value' => '4'
},
'M' => {
'value' => ' 4'
}
},
'plugs' => {
'reset' => {
'type' => 'num',
'nums' => {
'0' => {
'name' => 'reset',
'connect_socket' => 'reset',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0'
}
},
'value' => 1,
'connection_num' => undef
},
'clk' => {
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'connect_socket' => 'clk',
'name' => 'clk'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
}
},
'sockets' => {
'wb_slave' => {
'connection_num' => 'single connection',
'value' => 'S',
'nums' => {
'0' => {
'name' => 'wb_slave'
}
},
'type' => 'param'
},
'wb_master' => {
'nums' => {
'0' => {
'name' => 'wb_master'
}
},
'type' => 'param',
'value' => 'M',
'connection_num' => 'single connection'
},
'wb_addr_map' => {
'connection_num' => 'single connection',
'value' => 1,
'nums' => {
'0' => {
'name' => 'wb_addr_map'
}
},
'type' => 'num'
},
'snoop' => {
'connection_num' => 'single connection',
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'snoop'
}
}
}
},
'module_name' => 'wishbone_bus'
},
'single_port_ram0' => {
'parameters' => {
'JTAG_CONNECT' => {
'value' => '"DISABLED"'
},
'Aw' => {
'value' => 14
},
'SELw' => {
'value' => 'Dw/8'
},
'BURST_MODE' => {
'value' => '"ENABLED"'
},
'INITIAL_EN' => {
'value' => '"YES"'
},
'MEM_CONTENT_FILE_NAME' => {
'value' => '"ram0"'
},
'BTEw' => {
'value' => '2'
},
'Dw' => {
'value' => '32'
},
'BYTE_WR_EN' => {
'value' => '"YES"'
},
'INIT_FILE_PATH' => {
'value' => 'SW_LOC'
},
'FPGA_VENDOR' => {
'value' => '"ALTERA"'
},
'WB_Aw' => {
'value' => 'Aw+2'
},
'JTAG_INDEX' => {
'value' => 'CORE_ID'
},
'TAGw' => {
'value' => '3'
},
'CTIw' => {
'value' => '3'
}
},
'plugs' => {
'reset' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'reset',
'connect_socket' => 'reset'
}
}
},
'wb_slave' => {
'nums' => {
'0' => {
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '0',
'name' => 'wb',
'connect_socket' => 'wb_slave',
'base' => 0,
'addr' => '0x0000_0000 0x3fff_ffff RAM',
'end' => 65535,
'width' => 'WB_Aw'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
},
'clk' => {
'value' => 1,
'connection_num' => undef,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'clk',
'connect_socket' => 'clk'
}
}
}
},
'module_name' => 'wb_single_port_ram',
'sockets' => {},
'parameters_order' => [
'Dw',
'Aw',
'BYTE_WR_EN',
'FPGA_VENDOR',
'JTAG_CONNECT',
'JTAG_INDEX',
'TAGw',
'SELw',
'CTIw',
'BTEw',
'WB_Aw',
'BURST_MODE',
'MEM_CONTENT_FILE_NAME',
'INITIAL_EN',
'INIT_FILE_PATH'
],
'description_pdf' => '/mpsoc/src_peripheral/ram/RAM.pdf',
'category' => 'RAM',
'module' => 'single_port_ram',
'instance_name' => 'ram'
},
'jtag_uart0' => {
'plugs' => {
'wb_slave' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket_num' => '1',
'connect_id' => 'wishbone_bus0',
'width' => 5,
'end' => 2415919135,
'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller',
'base' => 2415919104,
'connect_socket' => 'wb_slave',
'name' => 'wb_slave'
}
},
'type' => 'num'
},
'reset' => {
'value' => 1,
'connection_num' => undef,
'nums' => {
'0' => {
'name' => 'reset',
'connect_socket' => 'reset',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0'
}
},
'type' => 'num'
},
'interrupt_peripheral' => {
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'NC',
'connect_socket_num' => undef,
'name' => 'interrupt_peripheral',
'connect_socket' => undef
}
},
'value' => 1,
'connection_num' => undef
},
'clk' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket' => 'clk',
'name' => 'clk',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0'
}
}
}
},
'parameters' => {
'SIM_BUFFER_SIZE' => {
'value' => 1000
},
'SIM_WAIT_COUNT' => {
'value' => '1000'
},
'FPGA_VENDOR' => {
'value' => ' "ALTERA"'
}
},
'sockets' => {
'RxD_sim' => {
'connection_num' => 'single connection',
'value' => 1,
'nums' => {
'0' => {
'name' => 'RxD_sim'
}
},
'type' => 'num'
}
},
'module_name' => 'jtag_uart_wb',
'category' => 'Communication',
'description_pdf' => undef,
'parameters_order' => [
'FPGA_VENDOR',
'SIM_BUFFER_SIZE',
'SIM_WAIT_COUNT'
],
'module' => 'jtag_uart',
'instance_name' => 'uart'
},
'clk_source0' => {
'description_pdf' => undef,
'category' => 'Source',
'parameters_order' => [],
'module' => 'clk_source',
'instance_name' => 'ss',
'plugs' => {
'clk' => {
'value' => 1,
'connection_num' => undef,
'nums' => {
'0' => {
'name' => 'clk',
'connect_socket' => undef,
'connect_socket_num' => undef,
'connect_id' => 'IO'
}
},
'type' => 'num'
},
'reset' => {
'type' => 'num',
'nums' => {
'0' => {
'connect_socket_num' => undef,
'connect_id' => 'IO',
'connect_socket' => undef,
'name' => 'reset'
}
},
'connection_num' => undef,
'value' => 1
}
},
'parameters' => {},
'sockets' => {
'clk' => {
'nums' => {
'0' => {
'name' => 'clk'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => 'multi connection'
},
'reset' => {
'nums' => {
'0' => {
'name' => 'reset'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => 'multi connection'
}
},
'module_name' => 'clk_source'
},
'ni_master0' => {
'sockets' => {
'ni' => {
'connection_num' => 'single connection',
'value' => 1,
'nums' => {
'0' => {
'name' => 'ni'
}
},
'type' => 'num'
}
},
'module_name' => 'ni_master',
'parameters' => {
'WEIGHTw' => {
'value' => '4'
},
'COMBINATION_TYPE' => {
'value' => '"COMB_NONSPEC"'
},
'MUX_TYPE' => {
'value' => '"BINARY"'
},
'SELw' => {
'value' => '4'
},
'ESCAP_VC_MASK' => {
'value' => '2\'b01'
},
'MAX_TRANSACTION_WIDTH' => {
'value' => '13'
},
'ROUTING_HDR_WIDTH' => {
'value' => '8'
},
'NX' => {
'value' => 2
},
'NY' => {
'value' => ' 2'
},
'DST_ADR_HDR_WIDTH' => {
'value' => '8'
},
'S_Aw' => {
'value' => '8'
},
'B' => {
'value' => '4'
},
'MAX_SBP_NUM ' => {
'value' => 0
},
'M_Aw' => {
'value' => '32'
},
'Yw' => {
'value' => 'log2(NY)'
},
'DEBUG_EN' => {
'value' => '1'
},
'SSA_EN' => {
'value' => '"NO"'
},
'Xw' => {
'value' => 'log2(NX)'
},
'ADD_PIPREG_AFTER_CROSSBAR' => {
'value' => '1\'b0'
},
'CONGESTION_INDEX' => {
'value' => 3
},
'TOPOLOGY' => {
'value' => '"MESH"'
},
'Dw' => {
'value' => '32'
},
'MAX_BURST_SIZE' => {
'value' => '16'
},
'ROUTE_SUBFUNC' => {
'value' => '"XY"'
},
'AVC_ATOMIC_EN' => {
'value' => 0
},
'SWA_ARBITER_TYPE' => {
'value' => '"RRA"'
},
'VC_REALLOCATION_TYPE' => {
'value' => '"NONATOMIC"'
},
'SRC_ADR_HDR_WIDTH' => {
'value' => '8'
},
'CLASS_HDR_WIDTH' => {
'value' => '8'
},
'Fpay' => {
'value' => '32'
},
'Fw' => {
'value' => '2+V+Fpay'
},
'FIRST_ARBITER_EXT_P_EN' => {
'value' => 1
},
'ROUTE_NAME' => {
'value' => '"XY"'
},
'V' => {
'value' => '2'
},
'CRC_EN' => {
'value' => '"NO"'
},
'TAGw' => {
'value' => '3'
},
'C' => {
'value' => 2
}
},
'plugs' => {
'wb_slave' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket_num' => '3',
'connect_id' => 'wishbone_bus0',
'width' => 10,
'end' => 3087008767,
'base' => 3087007744,
'addr' => '0xb800_0000 0xbfff_ffff custom devices',
'name' => 'wb_slave',
'connect_socket' => 'wb_slave'
}
},
'type' => 'num'
},
'wb_master' => {
'nums' => {
'1' => {
'connect_socket' => 'wb_master',
'name' => 'wb_receive',
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '1'
},
'0' => {
'name' => 'wb_send',
'connect_socket' => 'wb_master',
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '0'
}
},
'type' => 'num',
'value' => 2,
'connection_num' => undef
},
'reset' => {
'value' => 1,
'connection_num' => undef,
'nums' => {
'0' => {
'name' => 'reset',
'connect_socket' => 'reset',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0'
}
},
'type' => 'num'
},
'interrupt_peripheral' => {
'type' => 'num',
'nums' => {
'0' => {
'name' => 'interrupt',
'connect_socket' => 'interrupt_peripheral',
'connect_socket_num' => '0',
'connect_id' => 'mor1kx0'
}
},
'value' => 1,
'connection_num' => undef
},
'clk' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket' => 'clk',
'name' => 'clk',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0'
}
}
}
},
'module' => 'ni_master',
'instance_name' => 'ni',
'parameters_order' => [
'CLASS_HDR_WIDTH',
'ROUTING_HDR_WIDTH',
'DST_ADR_HDR_WIDTH',
'SRC_ADR_HDR_WIDTH',
'TOPOLOGY',
'ROUTE_NAME',
'NX',
'NY',
'C',
'V',
'B',
'Fpay',
'MAX_TRANSACTION_WIDTH',
'MAX_BURST_SIZE',
'DEBUG_EN',
'Dw',
'S_Aw',
'M_Aw',
'TAGw',
'SELw',
'Xw',
'Yw',
'Fw',
'CRC_EN'
],
'category' => 'NoC',
'description_pdf' => '/mpsoc/src_peripheral/ni/NI.pdf'
},
'mor1kx0' => {
'module' => 'mor1kx',
'instance_name' => 'cpu',
'parameters_order' => [
'OPTION_OPERAND_WIDTH',
'IRQ_NUM',
'OPTION_DCACHE_SNOOP',
'FEATURE_INSTRUCTIONCACHE',
'FEATURE_DATACACHE',
'FEATURE_IMMU',
'FEATURE_DMMU'
],
'description_pdf' => undef,
'category' => 'Processor',
'sockets' => {
'interrupt_peripheral' => {
'connection_num' => 'single connection',
'value' => 'IRQ_NUM',
'nums' => {
'0' => {
'name' => 'interrupt_peripheral'
}
},
'type' => 'param'
}
},
'module_name' => 'mor1k',
'parameters' => {
'IRQ_NUM' => {
'value' => '32'
},
'OPTION_OPERAND_WIDTH' => {
'value' => '32'
},
'FEATURE_DMMU' => {
'value' => '"ENABLED"'
},
'FEATURE_DATACACHE' => {
'value' => '"ENABLED"'
},
'FEATURE_INSTRUCTIONCACHE' => {
'value' => '"ENABLED"'
},
'FEATURE_IMMU' => {
'value' => '"ENABLED"'
},
'OPTION_DCACHE_SNOOP' => {
'value' => '"ENABLED"'
}
},
'plugs' => {
'wb_master' => {
'connection_num' => undef,
'value' => 2,
'nums' => {
'1' => {
'connect_socket' => 'wb_master',
'name' => 'dwb',
'connect_socket_num' => '3',
'connect_id' => 'wishbone_bus0'
},
'0' => {
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '2',
'connect_socket' => 'wb_master',
'name' => 'iwb'
}
},
'type' => 'num'
},
'enable' => {
'type' => 'num',
'nums' => {
'0' => {
'name' => 'enable',
'connect_socket' => undef,
'connect_socket_num' => undef,
'connect_id' => 'IO'
}
},
'value' => 1,
'connection_num' => undef
},
'snoop' => {
'nums' => {
'0' => {
'name' => 'snoop',
'connect_socket' => 'snoop',
'connect_socket_num' => '0',
'connect_id' => 'wishbone_bus0'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
},
'reset' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'reset',
'connect_socket' => 'reset'
}
}
},
'clk' => {
'type' => 'num',
'nums' => {
'0' => {
'connect_socket' => 'clk',
'name' => 'clk',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0'
}
},
'value' => 1,
'connection_num' => undef
}
}
},
'timer0' => {
'instance_name' => 'timer',
'module' => 'timer',
'category' => 'Timer',
'description_pdf' => '/mpsoc/src_peripheral/timer/timer.pdf',
'parameters_order' => [
'CNTw',
'Dw',
'Aw',
'TAGw',
'SELw',
'PRESCALER_WIDTH'
],
'sockets' => {},
'module_name' => 'timer',
'plugs' => {
'interrupt_peripheral' => {
'type' => 'num',
'nums' => {
'0' => {
'name' => 'intrp',
'connect_socket' => 'interrupt_peripheral',
'connect_socket_num' => '1',
'connect_id' => 'mor1kx0'
}
},
'value' => 1,
'connection_num' => undef
},
'clk' => {
'type' => 'num',
'nums' => {
'0' => {
'name' => 'clk',
'connect_socket' => 'clk',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0'
}
},
'value' => 1,
'connection_num' => undef
},
'wb_slave' => {
'nums' => {
'0' => {
'connect_socket' => 'wb_slave',
'name' => 'wb',
'end' => 2516582431,
'width' => 5,
'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl',
'base' => 2516582400,
'connect_socket_num' => '2',
'connect_id' => 'wishbone_bus0'
}
},
'type' => 'num',
'connection_num' => undef,
'value' => 1
},
'reset' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket' => 'reset',
'name' => 'reset',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0'
}
},
'type' => 'num'
}
},
'parameters' => {
'Aw' => {
'value' => '3'
},
'TAGw' => {
'value' => '3'
},
'SELw' => {
'value' => '4'
},
'Dw' => {
'value' => '32'
},
'CNTw' => {
'value' => '32 '
},
'PRESCALER_WIDTH' => {
'value' => '8'
}
}
}
},
'verilator' => {
'libs' => {
'Vtop' => 'mor1k_tile.v'
}
},
'compile' => {
'board' => 'DE10_Nano_VB2',
'modelsim_bin' => '/home/alireza/intelFPGA_lite/17.1/modelsim_ase/bin',
'compilers' => 'QuartusII,Verilator,Modelsim',
'type' => 'Verilator',
'quartus_bin' => '/home/alireza/intelFPGA_lite/17.1/quartus/bin'
},
'top_ip' => bless( {
'ports' => {
'ss_clk_in' => {
'instance_name' => 'clk_source0',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i'
},
'ni_flit_out_wr' => {
'type' => 'output',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'intfc_port' => 'flit_out_wr',
'instance_name' => 'ni_master0'
},
'ni_flit_out' => {
'type' => 'output',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out',
'instance_name' => 'ni_master0'
},
'ni_credit_out' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'output',
'intfc_port' => 'credit_out',
'instance_name' => 'ni_master0'
},
'ni_credit_in' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ni_flit_in' => {
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'flit_in',
'instance_name' => 'ni_master0'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input',
'instance_name' => 'ni_master0'
},
'cpu_cpu_en' => {
'intfc_port' => 'enable_i',
'range' => '',
'intfc_name' => 'plug:enable[0]',
'type' => 'input',
'instance_name' => 'mor1kx0'
},
'ni_current_y' => {
'range' => 'ni_Yw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'current_y',
'instance_name' => 'ni_master0'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'type' => 'input',
'range' => 'ni_Xw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0'
},
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'instance_name' => 'clk_source0'
}
},
'instance_ids' => {
'mor1kx0' => {
'module' => 'mor1kx',
'instance' => 'cpu',
'module_name' => 'mor1k',
'ports' => {
'cpu_cpu_en' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'intfc_name' => 'plug:enable[0]',
'range' => ''
}
},
'category' => 'Processor',
'parameters' => {
'cpu_OPTION_OPERAND_WIDTH' => {
'info' => 'Parameter',
'default' => '32',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed'
},
'cpu_FEATURE_DMMU' => {
'content' => '"NONE","ENABLED"',
'info' => '',
'default' => '"ENABLED"',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Combo-box'
},
'cpu_FEATURE_IMMU' => {
'default' => '"ENABLED"',
'info' => '',
'content' => '"NONE","ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'cpu_FEATURE_DATACACHE' => {
'content' => '"NONE","ENABLED"',
'info' => '',
'default' => '"ENABLED"',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Combo-box'
},
'cpu_OPTION_DCACHE_SNOOP' => {
'content' => '"NONE","ENABLED"',
'info' => '',
'default' => '"ENABLED"',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Combo-box'
},
'cpu_IRQ_NUM' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'info' => undef,
'default' => '32'
},
'cpu_FEATURE_INSTRUCTIONCACHE' => {
'info' => '',
'default' => '"ENABLED"',
'content' => '"NONE","ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'redefine_param' => 1
}
}
},
'timer0' => {
'module' => 'timer',
'instance' => 'timer',
'localparam' => {
'timer_SELw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '4',
'info' => undef,
'content' => ''
},
'timer_Aw' => {
'default' => '3',
'info' => undef,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'timer_TAGw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'info' => undef,
'default' => '3',
'content' => ''
},
'timer_CNTw' => {
'info' => undef,
'default' => '32 ',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed'
},
'timer_Dw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '32',
'info' => undef,
'content' => ''
}
},
'module_name' => 'timer',
'category' => 'Timer',
'parameters' => {
'timer_PRESCALER_WIDTH' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Spin-button',
'content' => '1,32,1',
'default' => '8',
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
 
 
'
}
}
},
'clk_source0' => {
'instance' => 'ss',
'module' => 'clk_source',
'module_name' => 'clk_source',
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input'
},
'ss_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
}
},
'category' => 'Source'
},
'ni_master0' => {
'parameters' => {
'ni_B' => {
'content' => '',
'default' => '4',
'info' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ni_NX' => {
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter',
'content' => '',
'info' => 'Parameter',
'default' => 2
},
'ni_NY' => {
'content' => '',
'default' => ' 2',
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_TOPOLOGY' => {
'content' => '',
'default' => '"MESH"',
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_V' => {
'content' => '',
'default' => '2',
'info' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ni_Fpay' => {
'default' => '32',
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'ni_C' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'default' => 2,
'info' => 'Parameter',
'content' => ''
},
'ni_ROUTE_NAME' => {
'info' => 'Parameter',
'default' => '"XY"',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_DEBUG_EN' => {
'default' => '1',
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1
}
},
'category' => 'NoC',
'ports' => {
'ni_flit_out_wr' => {
'range' => '',
'intfc_name' => 'socket:ni[0]',
'type' => 'output',
'intfc_port' => 'flit_out_wr'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'type' => 'output',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'type' => 'output',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
},
'ni_flit_in_wr' => {
'range' => '',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'flit_in_wr'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'type' => 'input',
'range' => 'ni_Yw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_current_x' => {
'range' => 'ni_Xw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'current_x'
}
},
'module_name' => 'ni_master',
'localparam' => {
'ni_DST_ADR_HDR_WIDTH' => {
'default' => '8',
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ni_CRC_EN' => {
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '"NO"',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'content' => '"YES","NO"'
},
'ni_S_Aw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '8',
'info' => 'Parameter',
'content' => ''
},
'ni_M_Aw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '32',
'info' => 'Parameter',
'content' => 'Dw'
},
'ni_SRC_ADR_HDR_WIDTH' => {
'content' => '',
'info' => 'Parameter',
'default' => '8',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ni_Fw' => {
'type' => 'Fixed',
'redefine_param' => 0,
'global_param' => 'Localparam',
'content' => '',
'default' => '2+ni_V+ni_Fpay',
'info' => undef
},
'ni_Xw' => {
'global_param' => 'Localparam',
'redefine_param' => 0,
'type' => 'Fixed',
'default' => 'log2(ni_NX)',
'info' => undef,
'content' => ''
},
'ni_TAGw' => {
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'default' => '3',
'info' => 'Parameter'
},
'ni_SELw' => {
'content' => '',
'info' => 'Parameter',
'default' => '4',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ni_ROUTING_HDR_WIDTH' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '8',
'content' => ''
},
'ni_MAX_TRANSACTION_WIDTH' => {
'default' => '13',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
'content' => '4,32,1',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ni_MAX_BURST_SIZE' => {
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
'default' => '16'
},
'ni_Dw' => {
'content' => '32,256,8',
'info' => 'wishbone_bus data width in bits.',
'default' => '32',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button'
},
'ni_CLASS_HDR_WIDTH' => {
'default' => '8',
'info' => 'Parameter',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_Yw' => {
'default' => 'log2(ni_NY)',
'info' => undef,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 0
}
},
'module' => 'ni_master',
'instance' => 'ni'
},
'jtag_uart0' => {
'category' => 'Communication',
'module_name' => 'jtag_uart_wb',
'localparam' => {
'uart_FPGA_VENDOR' => {
'default' => ' "ALTERA"',
'info' => 'FPGA VENDOR name. Only Altera FPGA is supported. Currently the Generic serial port is not supported. ',
'content' => ' "ALTERA"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Combo-box'
},
'uart_SIM_BUFFER_SIZE' => {
'info' => 'Internal buffer size.
This parameter is valid only in simulation.
If internal buffer overflows, the buffer content are displayed on simulator terminal.',
'default' => 1000,
'content' => '10,10000,1',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'uart_SIM_WAIT_COUNT' => {
'content' => '2,100000,1',
'info' => 'This parameter is valid only in simulation.
If internal buffer has a data, the internal timer incremented by one in each clock cycle. If the timer reaches the WAIT_COUNT value, it writes the buffer value on the simulator terminal.',
'default' => '1000',
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Localparam'
}
},
'module' => 'jtag_uart',
'instance' => 'uart'
},
'wishbone_bus0' => {
'module' => 'wishbone_bus',
'instance' => 'bus',
'localparam' => {
'bus_CTIw' => {
'default' => '3',
'info' => undef,
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed'
},
'bus_M' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button',
'content' => '1,256,1',
'default' => ' 4',
'info' => 'Number of wishbone master interface'
},
'bus_BTEw' => {
'content' => '',
'default' => '2 ',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'bus_Aw' => {
'default' => '32',
'info' => 'The wishbone Bus address width',
'content' => '4,128,1',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Spin-button'
},
'bus_TAGw' => {
'content' => '',
'info' => undef,
'default' => '3',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'bus_S' => {
'content' => '1,256,1',
'default' => '4',
'info' => 'Number of wishbone slave interface',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button'
},
'bus_Dw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Spin-button',
'info' => 'The wishbone Bus data width in bits.',
'default' => '32',
'content' => '8,512,8'
},
'bus_SELw' => {
'content' => '',
'default' => 'bus_Dw/8',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed'
}
},
'module_name' => 'wishbone_bus',
'category' => 'Bus'
},
'single_port_ram0' => {
'category' => 'RAM',
'parameters' => {
'ram_Dw' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Spin-button',
'default' => '32',
'info' => 'Memory data width in Bits.',
'content' => '8,1024,1'
},
'ram_Aw' => {
'default' => 14,
'info' => 'Memory address width',
'content' => '4,31,1',
'type' => 'Spin-button',
'global_param' => 'Parameter',
'redefine_param' => 1
}
},
'module_name' => 'wb_single_port_ram',
'localparam' => {
'ram_SELw' => {
'content' => '',
'default' => 'ram_Dw/8',
'info' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_FPGA_VENDOR' => {
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"ALTERA","GENERIC"',
'info' => '',
'default' => '"ALTERA"'
},
'ram_BURST_MODE' => {
'content' => '"DISABLED","ENABLED"',
'default' => '"ENABLED"',
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_MEM_CONTENT_FILE_NAME' => {
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
bin: raw binary format . It will be used by JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'default' => '"ram0"',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Entry'
},
'ram_INITIAL_EN' => {
'content' => '"YES","NO"',
'default' => '"YES"',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_BTEw' => {
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'default' => '2',
'info' => 'Parameter'
},
'ram_JTAG_CONNECT' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Combo-box',
'default' => '"DISABLED"',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
'content' => '"DISABLED", "JTAG_WB" , "ALTERA_IMCE"'
},
'ram_JTAG_INDEX' => {
'type' => 'Entry',
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
',
'default' => 'CORE_ID',
'content' => ''
},
'ram_INIT_FILE_PATH' => {
'info' => undef,
'default' => 'SW_LOC',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ram_BYTE_WR_EN' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Combo-box',
'content' => '"YES","NO"',
'info' => 'Byte enable',
'default' => '"YES"'
},
'ram_TAGw' => {
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => 'Parameter',
'default' => '3'
},
'ram_CTIw' => {
'content' => '',
'default' => '3',
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed'
}
},
'instance' => 'ram',
'module' => 'single_port_ram'
}
},
'interface' => {
'socket:ni[0]' => {
'ports' => {
'ni_current_x' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Xw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_x'
},
'ni_flit_in_wr' => {
'type' => 'input',
'range' => '',
'intfc_port' => 'flit_in_wr',
'instance_name' => 'ni_master0'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'range' => 'ni_Yw-1 : 0',
'type' => 'input',
'instance_name' => 'ni_master0'
},
'ni_flit_in' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'flit_in',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
},
'ni_flit_out_wr' => {
'range' => '',
'type' => 'output',
'intfc_port' => 'flit_out_wr',
'instance_name' => 'ni_master0'
},
'ni_credit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'type' => 'input',
'intfc_port' => 'credit_in'
},
'ni_credit_out' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'credit_out',
'range' => 'ni_V-1 : 0',
'type' => 'output'
},
'ni_flit_out' => {
'instance_name' => 'ni_master0',
'type' => 'output',
'range' => 'ni_Fw-1 : 0',
'intfc_port' => 'flit_out'
}
}
},
'plug:enable[0]' => {
'ports' => {
'cpu_cpu_en' => {
'instance_name' => 'mor1kx0',
'intfc_port' => 'enable_i',
'type' => 'input',
'range' => ''
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i',
'instance_name' => 'clk_source0'
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'range' => '',
'instance_name' => 'clk_source0'
}
}
}
}
}, 'ip_gen' ),
'tile_diagram' => {
'show_unused' => 1,
'show_clk' => 1,
'show_reset' => 1
},
'soc_name' => 'mor1k_tile',
'instance_order' => [
'single_port_ram0',
'clk_source0',
'jtag_uart0',
'timer0',
'ni_master0',
'wishbone_bus0',
'mor1kx0'
],
'compile_pin_pos' => {},
'jtag_uart0' => {
'version' => 14
},
'hdl_files' => undef,
'parameters_order' => {
'Unset-intfc' => [
'uart-RxD_din_sim',
'uart-RxD_ready_sim',
'uart-RxD_wr_sim',
'bus-snoop_adr_o',
'bus-snoop_en_o'
]
},
'compile_assign_type' => {
'ss_clk_in' => 'Direct',
'ni_credit_in' => 'Direct',
'ni_flit_in' => 'Direct',
'ni_flit_in_wr' => 'Direct',
'cpu_cpu_en' => 'Direct',
'ni_current_y' => 'Direct',
'ni_current_x' => 'Direct',
'ss_reset_in' => 'Direct'
},
'dma0' => {
'version' => 4
},
'modules' => {}
}, 'soc' );
/mpsoc/perl_gui/lib/verilog/functions.v
11,8 → 11,8
function [15:0]i2s;
input integer c; integer i; integer tmp; begin
tmp =0;
for (i=0; i<2; i=i+1'b1) begin
tmp = tmp + (((c % 10) + 6'd48) << i*8);
for (i=0; i<2; i=i+1) begin
tmp = tmp + (((c % 10) + 48) << i*8);
c = c/10;
end
i2s = tmp[15:0];
/mpsoc/script/transcript
20,7 → 20,7
# Modifying modelsim.ini
###################################################################
##---- 3. Compile the Design
# 1518690625
# 1542618941
# 0
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module crossbar
326,7 → 326,7
# pseudo_hotspot_no_core
# pseudo_hotspot
# pseudo_random_gen
# 1518690625
# 1542618941
###################################################################
## END OF COMPILATION
###################################################################
363,10 → 363,12
# Loading work.nonspec_sw_alloc
# Loading work.one_hot_mux
# Loading work.add_sw_loc_one_hot
# Loading work.wrra_contention_gen
# Loading work.weights_update
# Loading work.arbiter
# Loading work.xy_mesh_routing
# Loading work.xy_line_routing
# Loading work.one_hot_to_bin
# Loading work.two_dimention_pck_dst_gen
# Loading work.one_dimention_pck_dst_gen
# Loading work.deterministic_look_ahead_routing
# Loading work.next_router_addr_predictor
# Loading work.next_router_inport_predictor
375,6 → 377,7
# Loading work.flit_update_dtrmn
# Loading work.class_ovc_table
# Loading work.fwft_fifo
# Loading work.weight_control
# Loading work.flit_buffer
# Loading work.inport_module
# Loading work.one_hot_demux
383,17 → 386,28
# Loading work.check_ovc
# Loading work.swa_input_port_arbiter
# Loading work.swa_output_port_arbiter
# Loading work.wrra_inputport_destports_sum
# Loading work.accumulator
# Loading work.weight_update_per_port
# Loading work.my_one_hot_arbiter
# Loading work.weight_counter
# Loading work.fifo_ram
# Loading work.PC_15_4
# Loading work.PC_7_3
# Loading work.CS_GEN
# Loading work.PC_7_3
# Loading work.arbiter_priority_en
# Loading work.arbiter_2_one_hot
# Loading work.my_one_hot_arbiter_priority_en
# Loading work.arbiter_4_one_hot
# ** Warning: Design size of 61 instances exceeds ModelSim ALTERA recommended capacity.
# ** Warning: Design size of 66 instances exceeds ModelSim ALTERA recommended capacity.
# This may because you are loading cell libraries which are not recommended with
# the ModelSim Altera version. Expect performance to be adversely affected.
# file18
do /home/alireza/mywork/mpsoc_work/modelsim/wave.do
run
restart
# ** Warning: Design size of 0 instances exceeds ModelSim ALTERA recommended capacity.
# This may because you are loading cell libraries which are not recommended with
# the ModelSim Altera version. Expect performance to be adversely affected.
run
# Break key hit
# Simulation stop requested.
run
/mpsoc/src_modelsim/testbench_modelsim.v
89,9 → 89,9
 
module testbench_sub #(
parameter V=2,
parameter B=2,
parameter NX=8,
parameter NY=8,
parameter B=4,
parameter NX=15,
parameter NY=1,
parameter C=1,
parameter Fpay=32,
parameter MUX_TYPE="ONE_HOT",
98,7 → 98,7
parameter VC_REALLOCATION_TYPE="NONATOMIC",
parameter COMBINATION_TYPE="COMB_NONSPEC",
parameter FIRST_ARBITER_EXT_P_EN=1,
parameter TOPOLOGY="MESH",
parameter TOPOLOGY="LINE",
parameter ROUTE_NAME="XY",
parameter CONGESTION_INDEX=7,
parameter ROUTE_SUBFUNC= "XY",
108,8 → 108,8
parameter [CVw-1: 0] CLASS_SETTING = 4'b1111, // shows how each class can use VCs
parameter [V-1 : 0] ESCAP_VC_MASK = 2'b10, // mask scape vc, valid only for full adaptive
parameter SSA_EN= "NO",//"YES", // "YES" , "NO"
parameter SWA_ARBITER_TYPE = "RRA",//"RRA","WRRA". SWA: Switch Allocator. RRA: Round Robin Arbiter. WRRA Weighted Round Robin Arbiter
parameter WEIGHTw=6, // WRRA weights' max width
parameter SWA_ARBITER_TYPE = "WRRA",//"RRA","WRRA". SWA: Switch Allocator. RRA: Round Robin Arbiter. WRRA Weighted Round Robin Arbiter
parameter WEIGHTw=7, // WRRA weights' max width
parameter C0_p=100,
parameter C1_p=0,
116,9 → 116,9
parameter C2_p=0,
parameter C3_p=0,
// parameter TRAFFIC="HOTSPOT",
parameter TRAFFIC="TRANSPOSE1",
// parameter TRAFFIC="TRANSPOSE1",
//parameter TRAFFIC="RANDOM",
// parameter TRAFFIC="CUSTOM",
parameter TRAFFIC="CUSTOM",
parameter HOTSPOT_PERCENTAGE=100,
parameter HOTSPOT_NUM=1,
parameter HOTSPOT_CORE_1=0,
/mpsoc/src_modelsim/traffic_pattern.v
580,15 → 580,15
always @(*) begin
valid_dst_reg=1'b0;
if( current_x>=0 && current_x<=6 ) begin
if( current_x>=0 && current_x<=6 ) begin
dest_x_reg= 8; valid_dst_reg=1'b1;
end
if((current_x==7) ) begin
dest_x_reg= 10; valid_dst_reg=1'b1;
end
// if((current_x==7) ) begin
// dest_x_reg= 10; valid_dst_reg=1'b1;
// end
if((current_x>=8 && current_x<=14 ) ) begin
if((current_x>=7 && current_x<=14 ) ) begin
dest_x_reg= 14; valid_dst_reg=1'b1;
end
end
/mpsoc/src_noc/router.v
72,6 → 72,9
 
);
 
localparam WRRA_CONFIG_INDEX = 0;
 
 
function integer log2;
input integer number; begin
log2=(number <=1) ? 1: 0;
188,7 → 191,7
.SSA_EN(SSA_EN),
.SWA_ARBITER_TYPE (SWA_ARBITER_TYPE),
.WEIGHTw(WEIGHTw),
.WRRA_CONFIG_INDEX(0)
.WRRA_CONFIG_INDEX(WRRA_CONFIG_INDEX)
)
the_inout_ports
305,7 → 308,7
wrra_contention_gen #(
.WEIGHTw(WEIGHTw),
.WRRA_CONFIG_INDEX(0),
.WRRA_CONFIG_INDEX(WRRA_CONFIG_INDEX),
.V(V),
.P(P)
)
327,7 → 330,7
.P(P),
.Fpay(Fpay),
.WEIGHTw(WEIGHTw),
.WRRA_CONFIG_INDEX(0),
.WRRA_CONFIG_INDEX(WRRA_CONFIG_INDEX),
.C(C),
.ADD_PIPREG_AFTER_CROSSBAR(ADD_PIPREG_AFTER_CROSSBAR),
.CLASS_HDR_WIDTH(CLASS_HDR_WIDTH),
/mpsoc/src_noc/wrra.v
28,6 → 28,16
** weight sending packet to the same output ports.
** Swich allocator's output arbters' priority is lucked until the winner's
** input weight is not consumed. A weight is consumed when a packet is sent.
 
PROPOGATE_EQUALL = (WRRA_CONFIG_INDEX==0 );
PROPOGATE_LIMITED = (WRRA_CONFIG_INDEX==1 );
PROPOGATE_NEQ1 = (WRRA_CONFIG_INDEX==2 );
PROPOGATE_NEQ2 = (WRRA_CONFIG_INDEX==3 );
 
 
 
******************************************************************/
 
 
338,11 → 348,13
WP = W * P,
P_1 = P-1;
localparam
[W-1 : 0] INIT_WEIGHT = 1;
localparam [W-1 : 0] INIT_WEIGHT = 1;
localparam [W-1 : 0] MAX_WEIGHT = {W{1'b1}}-1'b1;
localparam PROPOGATE_EQUALL = (WRRA_CONFIG_INDEX==0 ),
PROPOGATE_LIMITED = (WRRA_CONFIG_INDEX==1 );
localparam PROPOGATE_EQUALL = (WRRA_CONFIG_INDEX==0 ),
PROPOGATE_LIMITED = (WRRA_CONFIG_INDEX==1 ),
PROPOGATE_NEQ1 = (WRRA_CONFIG_INDEX==2 ),
PROPOGATE_NEQ2 = (WRRA_CONFIG_INDEX==3 );
 
390,7 → 402,7
end
end //for
end else begin :neq
end else if (PROPOGATE_NEQ1) begin :neq1
always @(*)begin
oport_weight_counter[0]= {W{1'b0}};// the output port weight of local port is useless. hence fix it as zero.
432,9 → 444,74
end //for
end
end else begin : neq2 //if (PROPOGATE_NEQ1) :neq1
for (i=0;i<P;i=i+1)begin : port
if(i==0) begin : local_p
always @ (posedge clk)begin
oport_weight_counter[i]<= {W{1'b0}};// the output port weight of local port is useless. hence fix it as zero.
oport_weight[i]<= {W{1'b0}};
end//always
end//local_p
 
else if(i==SW_LOC) begin : if1
always @ (posedge clk)begin
oport_weight_counter[i]<= {W{1'b0}};// The loopback injection is forbiden hence it will be always as zero.
oport_weight[i]<= {W{1'b0}};
end
assign oports_weight [(i+1)*W-1 : i*W] = {W{1'b0}};
end else begin :else1
always @ (posedge clk or posedge reset) begin
if(reset) begin
oport_weight_counter[i]<= INIT_WEIGHT;
end else begin
if (weight_dcrease_en && counter_is_reset) oport_weight_counter[i]<= INIT_WEIGHT;
else if (weight_dcrease_en && dest_port[i] && oport_weight_counter[i] <MAX_WEIGHT )oport_weight_counter[i]<= oport_weight_counter[i] +1'b1;
end
end //always
always @ (posedge clk or posedge reset) begin
if(reset) begin
oport_weight[i]<={W{1'b0}};
end else begin
if(oport_weight[i]>iport_weight) oport_weight[i]<=iport_weight;// weight counter should always be smaller than iport weight
else if (weight_dcrease_en)begin
if( counter_is_reset ) begin
oport_weight[i]<= (oport_weight_counter[i]>0)? oport_weight_counter[i]: 1;
end//counter_reset
else begin
if (oport_weight_counter[i]>0 && oport_weight[i] < oport_weight_counter[i]) oport_weight[i]<= oport_weight_counter[i];
 
end
end//weight_dcr
end//else reset
end //always
assign oports_weight [(i+1)*W-1 : i*W] = oport_weight[i];
end //else
end //for
end
 
 
 
 
 
 
 
 
 
 
 
/* verilator lint_off WIDTH */
if(ARBITER_TYPE == "WRRA_CLASSIC") begin : wrra_classic
/* verilator lint_on WIDTH */
/mpsoc/src_peripheral/bus/wishbone_bus.v
88,6 → 88,11
//address compar
m_grant_addr,
s_sel_one_hot,
//snoop_interface
snoop_adr_o,
snoop_en_o,
//system signals
167,6 → 172,12
//
output [Aw-1 : 0] m_grant_addr;
input [S-1 : 0] s_sel_one_hot;
//snoop interface
output [Aw-1 : 0] snoop_adr_o;
output snoop_en_o;
//system signals
input clk, reset;
196,6 → 207,8
wire s_we_o;
wire s_cyc_o;
wire [Dw-1 : 0] m_dat_o;
 
 
assign s_adr_o_all = {S{s_adr_o}};
222,6 → 235,12
assign s_we_o = m_grant_we;
assign s_cyc_o = m_grant_cyc;
assign s_stb_o_all = s_sel_one_hot & {S{m_grant_stb & m_grant_cyc}};
//snoop address comes directly from master bus
assign snoop_adr_o = m_grant_addr;
//snoop on ack and write.mask with strobe
assign snoop_en_o = any_s_ack & m_grant_stb & m_grant_we;
 
 
//wire [ADDR_PERFIX-1 : 0] m_perfix_addr;
/mpsoc/src_peripheral/jtag/jtag_uart/altera_simulator_UART.v
99,6 → 99,16
reg [CNTw-1 : 0]counter,counter_next;
reg [7 : 0 ] buffer [ BUFFER_SIZE-1 : 0];
wire [BUFFER_SIZE*8-1:0] string_wire;
genvar k;
generate
for(k=0;k<BUFFER_SIZE;k=k+1)begin
assign string_wire[(BUFFER_SIZE-k)*8-1 : (BUFFER_SIZE-k-1)*8] = buffer[k];
end
endgenerate
 
 
reg [Bw-1 : 0] ptr,ptr_next;
always @(posedge clk)begin
166,12 → 176,24
if(reset) begin
counter<=0;
ptr<=0;
for(i=0;i<BUFFER_SIZE;i=i+1) buffer[i]=0;
end else begin
counter<=counter_next;
ptr <= ptr_next;
if( buff_en ) buffer[ptr]<=s_dat_i[7:0];
if (print_en) for(i=0;i< ptr;i=i+1) $write("%c",buffer[i]);
if( buff_en )begin
buffer[ptr]=s_dat_i[7:0];
if(ptr<BUFFER_SIZE-1) buffer[ptr+1]=0;
end
if (print_en) for(i=0;i< ptr;i=i+1) $write("%c",buffer[i]);
/*
if (print_en)begin
$write("%s",string_wire);
for(i=0;i< BUFFER_SIZE ;i=i+1) buffer[i]=0;
end
*/
end
 
end
 
 
/mpsoc/src_peripheral/ni/NI.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/mpsoc/src_peripheral/ni/ni_master.v
119,9 → 119,11
irq
 
);
/* verilator lint_off WIDTH */
localparam P= (TOPOLOGY=="RING" || TOPOLOGY=="LINE")? 3 : 5;
localparam ROUTE_TYPE = (ROUTE_NAME == "XY" || ROUTE_NAME == "TRANC_XY" )? "DETERMINISTIC" :
(ROUTE_NAME == "DUATO" || ROUTE_NAME == "TRANC_DUATO" )? "FULL_ADAPTIVE": "PAR_ADAPTIVE";
/* verilator lint_on WIDTH */
 
function integer log2;
input integer number; begin
196,28 → 198,28
localparam
CHw=log2(V),
BURST_SIZE_w= log2(MAX_BURST_SIZE);
BURST_SIZE_w= log2(MAX_BURST_SIZE+1);
/* wishbone slave adderess :
/* wishbone slave adderess :
[3:0]
0 : STATUS1_WB_ADDR // status1: {send_enable_binary,receive_enable_binary,send_vc_is_busy,receive_vc_is_busy,receive_vc_got_packet}
1 : STATUS2_WB_ADDR // status2:
2 : BURST_SIZE_WB_ADDR // The busrt size in words
0 : STATUS1_WB_ADDR // status1: {send_vc_is_busy,receive_vc_is_busy,receive_vc_packet_is_saved,receive_vc_got_packet};
1 : STATUS2_WB_ADDR // status2: {send_enable_binary,receive_enable_binary,vc_got_error,any_error_isr,got_pck_isr, save_done_isr,send_done_isr,any_error_int_en,got_pck_int_en, save_done_int_en,send_done_int_en};
2 : BURST_SIZE_WB_ADDR // The busrt size in words
3 : SEND_DATA_SIZE_WB_ADDR, // The size of data to be sent in byte
4 : SEND_STRT_WB_ADDR, // The address of data to be sent in byte
5 : SEND_DEST_WB_ADDR // The destination router address
6 : SEND_CTRL_WB_ADDR
3 : SEND_DATA_SIZE_WB_ADDR, // The size of data to be sent in byte
4 : SEND_STRT_WB_ADDR, // The address of data to be sent in byte
5 : SEND_DEST_WB_ADDR // The destination router address
6 : SEND_CTRL_WB_ADDR
7 : RECEIVE_DATA_SIZE_WB_ADDR // The size of recieved data in byte
8 : RECEIVE_STRT_WB_ADDR // The address pointer of reciever memory in byte
9 : RECEIVE_SRC_WB_ADDR // The source router (the router which is sent this packet).
10 : RECEIVE_CTRL_WB_ADDR // The NI reciever control register
11 : RECEIVE_MAX_BUFF_SIZ // The reciver allocated buffer size in words. If the packet size is bigger tha the buffer size the rest of will be discarred
7 : RECEIVE_DATA_SIZE_WB_ADDR // The size of recieved data in byte
8 : RECEIVE_STRT_WB_ADDR // The address pointer of reciever memory in byte
9 : RECEIVE_SRC_WB_ADDR // The source router (the router which is sent this packet).
10 : RECEIVE_CTRL_WB_ADDR // The NI reciever control register
11 : RECEIVE_MAX_BUFF_SIZ // The reciver allocated buffer size in words. If the packet size is bigger than the buffer size the rest of ot will be discarred
12 : ERROR_FLAGS // errors: {burst_size_error,send_data_size_error,crc_miss_match,rcive_buff_ovrflw_err};
[4+Vw:4]
: Virtual channel num
236,11 → 238,25
STATUS2_WB_ADDR = 1, // status
BURST_SIZE_WB_ADDR = 2, // The busrt size in words
RECEIVE_DATA_SIZE_WB_ADDR = 7, // The size of recieved data in byte
RECEIVE_SRC_WB_ADDR =9; // The source router (the router which is sent this packet).
RECEIVE_SRC_WB_ADDR =9, // The source router (the router which is sent this packet).
ERRORS_FLAGS_WB_ADDR=12;
localparam
STATUS1w= 4 * V,
STATUS2w= 2 * CHw + V + 8,
ERRw= 5;
localparam
SEND_DONE_INT_EN_LOC=0,
SAVE_DONE_INT_EN_LOC=1,
GOT_PCK_INT_EN_LOC=2,
ERRORS_INT_EN_LOC=3,
SEND_DONE_ISR_LOC=4,
SAVE_DONE_ISR_LOC=5,
GOT_PCK_ISR_LOC=6,
ERRORS_ISR_LOC=7;
reg [BURST_SIZE_w-1 : 0] burst_size, burst_size_next,burst_counter,burst_counter_next;
282,6 → 298,7
wire [MAX_TRANSACTION_WIDTH-1 : 0] receive_vc_max_buff_siz [V-1 : 0];
wire [V-1 : 0] send_vc_start, receive_vc_start;
wire received_flit_is_tail,received_flit_is_hdr;
wire [Xw-1 : 0] vc_dest_x [V-1 : 0];
wire [Yw-1 : 0] vc_dest_y [V-1 : 0];
316,35 → 333,33
reg [Xw-1 : 0] x_src_in [V-1 : 0];
reg [Yw-1 : 0] y_src_in [V-1 : 0];
reg [V-1 : 0] crc_miss_match;
reg reset_errors, reset_errors_next;
wire [V-1 : 0] burst_size_error,send_data_size_error,rcive_buff_ovrflw_err, illegal_send_req;
wire [V-1 : 0] vc_got_error;
wire any_vc_got_error = | vc_got_error;
reg got_pck_isr, save_done_isr, send_done_isr,got_pck_int_en, save_done_int_en,send_done_int_en;
reg got_pck_isr_next, save_done_isr_next,send_done_isr_next,got_pck_int_en_next, save_done_int_en_next,send_done_int_en_next;
reg any_error_isr, got_pck_isr, save_done_isr, send_done_isr;
reg any_error_isr_next,got_pck_isr_next, save_done_isr_next,send_done_isr_next;
reg any_error_int_en, got_pck_int_en, save_done_int_en,send_done_int_en;
reg any_error_int_en_next, got_pck_int_en_next, save_done_int_en_next,send_done_int_en_next;
localparam
STATUS1w= 4 * V,
STATUS2w= 2 * CHw + V + 6;
localparam
SEND_DONE_INT_EN_LOC=0,
SAVE_DONE_INT_EN_LOC=1,
GOT_PCK_INT_EN_LOC=2,
SAVE_DONE_ISR_LOC=3,
SEND_DONE_ISR_LOC=4,
GOT_PCK_ISR_LOC=5;
wire [STATUS1w-1 :0] status1;
wire [STATUS2w-1 :0] status2;
wire [STATUS2w-1 :0] status2;
wire [ERRw-1 : 0] errors [V-1 : 0];
assign status1= {send_vc_is_busy,receive_vc_is_busy,receive_vc_packet_is_saved,receive_vc_got_packet};
assign status2= {send_enable_binary,receive_enable_binary,crc_miss_match,got_pck_isr, save_done_isr,send_done_isr,got_pck_int_en, save_done_int_en,send_done_int_en};
assign status2= {send_enable_binary,receive_enable_binary,vc_got_error,any_error_isr,got_pck_isr, save_done_isr,send_done_isr,any_error_int_en,got_pck_int_en, save_done_int_en,send_done_int_en};
assign irq =(any_error_isr & any_error_int_en) | (got_pck_isr & got_pck_int_en) | (save_done_isr & save_done_int_en) | (send_done_isr & send_done_int_en);
assign irq = (got_pck_isr & got_pck_int_en) | (save_done_isr & save_done_int_en) | (send_done_isr & send_done_int_en);
//read wb registers
361,10 → 376,13
s_dat_o [MAX_TRANSACTION_WIDTH-1 : 0] = receive_counter[vc_addr];
end
RECEIVE_SRC_WB_ADDR: begin
s_dat_o[Xw-1 : 0] = x_src_in[vc_addr];
s_dat_o[(DST_ADR_HDR_WIDTH/2)+Yw-1: DST_ADR_HDR_WIDTH/2] = y_src_in[vc_addr];
s_dat_o[Cw+DST_ADR_HDR_WIDTH-1 : DST_ADR_HDR_WIDTH] = class_in[vc_addr];
end
s_dat_o[Xw-1: 0] = x_src_in[vc_addr]; // first byte
s_dat_o[Yw+7: 8] = y_src_in[vc_addr]; // second byte
s_dat_o[Cw+15: 16] = class_in[vc_addr]; //third byte
end
ERRORS_FLAGS_WB_ADDR: begin
s_dat_o[ERRw-1 : 0] = errors[vc_addr];
end
default: begin
s_dat_o = {{(Dw-STATUS1w){1'b0}}, status1};
end
372,12 → 390,13
end
reg all_save_done_reg_rst;
//write wb registers
always @ (*)begin
burst_counter_next=burst_counter;
burst_size_next= burst_size;
reset_errors_next = 1'b0;
if(burst_counter_ld) burst_counter_next = burst_size;
if(burst_counter_dec) burst_counter_next= burst_counter- 1'b1;
385,14 → 404,15
got_pck_int_en_next = got_pck_int_en;
save_done_int_en_next= save_done_int_en;
send_done_int_en_next= send_done_int_en;
any_error_int_en_next= any_error_int_en;
got_pck_isr_next = got_pck_isr;
save_done_isr_next= save_done_isr;
send_done_isr_next= send_done_isr;
any_error_isr_next= any_error_isr;
all_save_done_reg_rst=1'b0;
// all_got_pck_reg_rst=1'b0;
// all_send_done_reg_rst=1'b0;
if(any_vc_got_pck) got_pck_isr_next = 1'b1;
if(any_vc_save_done) save_done_isr_next = 1'b1;
if(any_vc_send_done) send_done_isr_next = 1'b1;
if(s_stb_i & s_we_i) begin
case(vc_s_addr_i)
BURST_SIZE_WB_ADDR: begin
402,16 → 422,35
got_pck_int_en_next = s_dat_i[GOT_PCK_INT_EN_LOC];
save_done_int_en_next = s_dat_i[SAVE_DONE_INT_EN_LOC];
send_done_int_en_next = s_dat_i[SEND_DONE_INT_EN_LOC];
any_error_int_en_next = s_dat_i[ERRORS_INT_EN_LOC];
// reset isr register by writting one on them
if (s_dat_i[GOT_PCK_ISR_LOC]) got_pck_isr_next = 1'b0;
if (s_dat_i[SAVE_DONE_ISR_LOC]) save_done_isr_next = 1'b0;
if (s_dat_i[SEND_DONE_ISR_LOC]) send_done_isr_next = 1'b0;
if (s_dat_i[GOT_PCK_ISR_LOC]) begin
got_pck_isr_next = 1'b0;
//all_got_pck_reg_rst=1'b1;
end
if (s_dat_i[SAVE_DONE_ISR_LOC]) begin
save_done_isr_next = 1'b0;
all_save_done_reg_rst=1'b1;
end
if (s_dat_i[SEND_DONE_ISR_LOC]) begin
send_done_isr_next = 1'b0;
//all_send_done_reg_rst=1'b1;
end
if (s_dat_i[ERRORS_ISR_LOC]) begin
any_error_isr_next = 1'b0;
reset_errors_next = 1'b1;
end
end //STATUS2_WB_ADDR
default begin
 
end
endcase
end
end else begin
if(any_vc_got_pck) got_pck_isr_next = 1'b1;
if(any_vc_save_done) save_done_isr_next = 1'b1;
if(any_vc_send_done) send_done_isr_next = 1'b1;
if(any_vc_got_error) any_error_isr_next = 1'b1;
end
end
424,9 → 463,13
got_pck_int_en <= 1'b0;
save_done_int_en <= 1'b0;
send_done_int_en <= 1'b0;
any_error_int_en <= 1'b0;
got_pck_isr <= 1'b0;
save_done_isr <= 1'b0;
send_done_isr <= 1'b0;
any_error_isr <= 1'b0;
reset_errors<= 1'b0;
end else begin
burst_counter<= burst_counter_next;
burst_size <= burst_size_next;
434,9 → 477,13
got_pck_int_en <= got_pck_int_en_next;
save_done_int_en <= save_done_int_en_next;
send_done_int_en <= send_done_int_en_next;
any_error_int_en <= any_error_int_en_next;
got_pck_isr <= got_pck_isr_next;
save_done_isr <= save_done_isr_next;
send_done_isr <= send_done_isr_next;
send_done_isr <= send_done_isr_next;
any_error_isr <= any_error_isr_next;
reset_errors <= reset_errors_next;
end
end
458,10 → 505,12
generate
for (i=0;i<V; i=i+1) begin : vc_
assign errors[i] = {crc_miss_match[i],illegal_send_req[i],burst_size_error[i],send_data_size_error[i],rcive_buff_ovrflw_err[i]};
assign vc_got_error[i] = | errors[i];
ni_vc_wb_slave_regs #(
.MAX_TRANSACTION_WIDTH(MAX_TRANSACTION_WIDTH),
.DST_ADR_HDR_WIDTH(DST_ADR_HDR_WIDTH),
.DEBUG_EN(DEBUG_EN),
.NX(NX),
.NY(NY),
.C(C),
471,6 → 520,12
)
wb_slave_registers
(
//synthesis translate_off
//synopsys translate_off
.current_x(current_x),
.current_y(current_y),
//synthesis translate_on
//synopsys translate_on
.clk(clk),
.reset(reset),
.state_reg_enable(vc_state_reg_enable[i]),
489,7 → 544,11
.send_start(send_vc_start[i]),
.receive_start(receive_vc_start[i]),
.receive_vc_got_packet(receive_vc_got_packet[i]),
.s_dat_i(s_dat_i),
.all_save_done_reg_rst(all_save_done_reg_rst),
//.all_got_pck_reg_rst(all_got_pck_reg_rst),
// .all_send_done_reg_rst(all_send_done_reg_rst),
.s_dat_i(s_dat_i),
.s_addr_i(s_addr_i[CHANNEL_REGw-1:0]),
.s_stb_i(s_stb_i),
.s_cyc_i(s_cyc_i),
550,8 → 609,13
.receive_fifo_empty(vc_fifo_empty[i]),
.receive_fifo_rd(vc_fifo_rd[i]),
//errors
.reset_errors(reset_errors),
.burst_size_error(burst_size_error[i]),
.send_data_size_error(send_data_size_error[i]),
.rcive_buff_ovrflw_err(rcive_buff_ovrflw_err[i]),
.illegal_send_req(illegal_send_req[i]),
//
.m_send_sel_o(vc_m_send_sel_o[i]),
.m_send_addr_o(vc_m_send_addr_o[i]),
586,10 → 650,12
end
end//always
end // for loop for channel
end // for loop vc_
/* verilator lint_off WIDTH */
if( CRC_EN == "YES") begin :crc_blk
/* verilator lint_on WIDTH */
reg fifo_rd_delayed;
always @(posedge clk or posedge reset)begin
if(reset) fifo_rd_delayed <=1'b0;
646,7 → 712,8
assign tail_flit_out[31 : 0] = send_crc_out;
end else begin : no_crc
assign tail_flit_out = m_send_dat_i [Fpay-1 : 0];
always @ ( *) crc_miss_match = {V{1'b0}};
//always @(*) crc_miss_match = {V{1'b0}};
always @(posedge clk) crc_miss_match <= {V{1'b0}};
end
842,12 → 909,13
.weight_o()
);
assign m_receive_dat_o = fifo_dout[Dw-1 : 0];
assign received_flit_is_tail = fifo_dout[Fw-2];
assign received_flit_is_hdr = fifo_dout[Fw-1];
assign any_vc_got_pck = received_flit_is_hdr & flit_in_wr;
assign any_vc_got_pck = |receive_vc_got_packet;
localparam [1:0]
HDR_FLAG = 2'b10,
931,6 → 999,7
end
endfunction // log2
/* verilator lint_off WIDTH */
localparam ADDR_DIMENTION = (TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") ? 2 : 1, // "RING" and FULLY_CONNECT
ALL_DATA_HDR_WIDTH = CLASS_HDR_WIDTH+ROUTING_HDR_WIDTH+DST_ADR_HDR_WIDTH+SRC_ADR_HDR_WIDTH,
P_1 = P-1 ,
939,7 → 1008,7
Yw = log2(NY),
Cw = (C>1)? log2(C): 1,
HDR_FLAG = 2'b10;
/* verilator lint_on WIDTH */
output [Fw-1 : 0] flit_out;
/mpsoc/src_peripheral/ni/ni_slave.v
35,8 → 35,8
 
module ni_slave #(
parameter MAX_TRANSACTION_WIDTH=10, // Maximum transaction size will be 2 power of MAX_DMA_TRANSACTION_WIDTH words
parameter INPUT_MEM_Aw = 10, // input mmeory address width
parameter OUTPUT_MEM_Aw = 10, // input mmeory address width
parameter INPUT_MEM_Aw = 10, // input memory address width
parameter OUTPUT_MEM_Aw = 10, // input memory address width
parameter MAX_BURST_SIZE =256, // in words
parameter DEBUG_EN = 1,
//NoC parameters
/mpsoc/src_peripheral/ni/ni_vc_dma.v
95,7 → 95,12
burst_counter_dec,
burst_size_is_set,
 
//errors
reset_errors,
burst_size_error,
send_data_size_error,
rcive_buff_ovrflw_err,
illegal_send_req,
//wishbone master rd interface signals
m_send_sel_o,
162,7 → 167,7
 
 
input reset,clk,send_enable,receive_enable;
output reg send_is_busy, receive_is_busy;
output send_is_busy, receive_is_busy;
output reg burst_counter_ld, burst_counter_dec;
input burst_size_is_set;
input last_burst;
187,12 → 192,14
output reg send_fifo_wr, receive_fifo_rd;
input send_fifo_full, send_fifo_nearly_full,send_fifo_rd, receive_fifo_empty;
//errors
input reset_errors;
output reg burst_size_error;
output reg send_data_size_error;
output reg rcive_buff_ovrflw_err;
output reg illegal_send_req;
 
//wishbone read master interface signals
output [SELw-1 : 0] m_send_sel_o;
output [M_Aw-1 : 0] m_send_addr_o;
217,17 → 224,19
reg [MAX_TRANSACTION_WIDTH-1 : 0] send_counter, send_counter_next;
reg [MAX_TRANSACTION_WIDTH-1 : 0] receive_counter_next;
reg burst_size_error_next, send_data_size_error_next;
reg rcive_buff_ovrflw_err_next, illegal_send_req_next;
wire last_data = (send_counter == send_data_size-1'b1);
wire receive_overflow= (send_counter == max_receive_buff_siz);
wire receive_overflow= (receive_counter == max_receive_buff_siz);
reg [SEND_ST_NUM-1 :0] send_ps,send_ns; // read peresent state, read next sate
reg [RECEIVE_ST_NUM-1 :0] receive_ps,receive_ns; // read peresent state, read next sate
reg receive_is_busy_next, send_is_busy_next;
//reg receive_is_busy_next, send_is_busy_next;
assign status= {receive_ps,send_ps};
234,14 → 243,18
// assign s_dat_o={{(Dw-STATUSw){1'b0}}, status};
reg send_crc;
/* verilator lint_off WIDTH */
assign send_tail = ( CRC_EN == "NO") ? last_data : send_crc;
/* verilator lint_on WIDTH */
assign send_fsm_is_ideal = (send_ps== SEND_IDEAL);
assign receive_fsm_is_ideal = (receive_ps== RECEIVE_IDEAL);
assign m_send_addr_o = send_start_addr + send_counter;
assign m_receive_addr_o = receive_start_addr + receive_counter;
/* verilator lint_off WIDTH */
assign m_send_addr_o = send_start_addr + send_counter;
assign m_receive_addr_o = receive_start_addr + receive_counter;
/* verilator lint_on WIDTH */
assign m_send_stb_o = m_send_cyc_o;
assign m_receive_stb_o = m_receive_cyc_o;
assign m_receive_we_o = 1'b1;
266,6 → 279,17
send_hdr = 1'b0;
send_crc = 1'b0;
active_st_next = active_st;
burst_size_error_next=burst_size_error;
send_data_size_error_next=send_data_size_error;
illegal_send_req_next = illegal_send_req;
// the send req must be asserted only when the Ni_send_DMA(v) is in ideal status
if( (send_ps != SEND_IDEAL && send_ps != SEND_HDR) & send_start) illegal_send_req_next=1'b1;
if(reset_errors) begin
burst_size_error_next=1'b0;
send_data_size_error_next=1'b0;
illegal_send_req_next=1'b0;
end
case(send_ps)
SEND_IDEAL: begin
if(send_start) begin
274,6 → 298,8
burst_counter_ld=1'b1;
send_ns = SEND_HDR;
end else begin // set error reg
if(!burst_size_is_set) burst_size_error_next=1'b1;
else send_data_size_error_next=1'b1;
end
end
end // SEND_IDEAL
286,8 → 312,7
send_ns = SEND_WAIT;
end else begin
send_fifo_wr=1'b1;
send_ns = SEND_BODY;
send_ns = SEND_BODY;
end
end
382,7 → 407,8
receive_is_active =1'b0;
hdr_flit_is_received_next=hdr_flit_is_received;
save_hdr_info=1'b0;
rcive_buff_ovrflw_err_next = rcive_buff_ovrflw_err;
if(reset_errors) rcive_buff_ovrflw_err_next=1'b0;
case(receive_ps)
RECEIVE_IDEAL: begin
404,17 → 430,20
RECEIVE_ACTIVE: begin
receive_is_active =1'b1; // this signal sends request to the receive_arbiter, the granted signal is receive_enable
if(receive_enable) begin
if(CRC_EN == "YES")begin
if(received_flit_is_tail)begin
m_receive_cyc_o = 1'b0;// make sre do not save crc on data memory
receive_ns = RECEIVE_IDEAL;
m_receive_cti_o= END_OF_BURST;
receive_done=1'b1;
end else begin
m_receive_cyc_o=1'b1;
end
end else m_receive_cyc_o=1'b1; //CRC_EN == "NO"
if(receive_enable) begin
/* verilator lint_off WIDTH */
// if(CRC_EN == "YES")begin
/* verilator lint_on WIDTH */
// if(received_flit_is_tail)begin
// m_receive_cyc_o = 1'b0;// make sure do not save crc on data memory
// receive_ns = RECEIVE_IDEAL;
// m_receive_cti_o= END_OF_BURST;
// receive_done=1'b1;
// end else begin
// m_receive_cyc_o=1'b1;
// end
// end else
m_receive_cyc_o=1'b1; //CRC_EN == "NO"
if (receive_fifo_empty) begin
m_receive_cti_o= END_OF_BURST;
end
422,6 → 451,7
hdr_flit_is_received_next=1'b1;
if(! hdr_flit_is_received) save_hdr_info=1'b1;
if(! receive_overflow && hdr_flit_is_received) receive_counter_next=receive_counter +1'b1; //Donot save hedaer flit in memory
if( receive_overflow) rcive_buff_ovrflw_err_next = 1'b1;//set error
if (received_flit_is_tail) begin
receive_ns = RECEIVE_IDEAL;
m_receive_cti_o= END_OF_BURST;
449,20 → 479,23
end//alays
/*
always @(*)begin
send_is_busy_next= send_is_busy;
if(send_start) send_is_busy_next =1'b1;
else if(send_done) send_is_busy_next=1'b0;
end
*/
assign send_is_busy = (send_ps != SEND_IDEAL);
assign receive_is_busy = (receive_ps != RECEIVE_IDEAL);
/*
always @(*)begin
receive_is_busy_next= receive_is_busy;
if(receive_done) receive_is_busy_next =1'b0;
else if(receive_start) receive_is_busy_next=1'b1;
end
*/
474,10 → 507,14
receive_ps <= RECEIVE_IDEAL;
send_counter <= {MAX_TRANSACTION_WIDTH{1'b0}};
receive_counter <= {MAX_TRANSACTION_WIDTH{1'b0}};
send_is_busy<= 1'b0;
receive_is_busy<= 1'b0;
// send_is_busy<= 1'b0;
// receive_is_busy<= 1'b0;
hdr_flit_is_received<=1'b0;
active_st <= 2'd0;
burst_size_error<=1'b0;
send_data_size_error<=1'b0;
rcive_buff_ovrflw_err <=1'b0;
illegal_send_req <=1'b0;
end else begin
485,10 → 522,14
receive_ps <= receive_ns;
send_counter <= send_counter_next;
receive_counter <= receive_counter_next;
send_is_busy <=send_is_busy_next;
receive_is_busy <=receive_is_busy_next;
// send_is_busy <=send_is_busy_next;
// receive_is_busy <=receive_is_busy_next;
hdr_flit_is_received<=hdr_flit_is_received_next;
active_st <= active_st_next;
burst_size_error<=burst_size_error_next;
send_data_size_error<=send_data_size_error_next;
rcive_buff_ovrflw_err <= rcive_buff_ovrflw_err_next;
illegal_send_req <= illegal_send_req_next;
end
end
/mpsoc/src_peripheral/ni/ni_vc_wb_slave_regs.v
36,6 → 36,7
parameter MAX_TRANSACTION_WIDTH =10,
//NoC parameter
parameter DEBUG_EN=1,
parameter DST_ADR_HDR_WIDTH =8,
parameter NX = 4, // number of node in x axis
parameter NY = 4, // number of node in y axis
56,7 → 57,9
receive_done,
receive_vc_got_packet,
receive_packet_is_saved,
all_save_done_reg_rst,
 
send_start_addr,
receive_start_addr,
send_data_size,
72,9 → 75,18
s_stb_i,
s_cyc_i,
s_we_i,
 
//synthesis translate_off
//synopsys translate_off
current_x,
current_y,
//synthesis translate_on
//synopsys translate_on
reset,
clk
clk
 
 
);
124,6 → 136,7
output reg [Dw-1 : 0] send_start_addr;
output reg [Dw-1 : 0] receive_start_addr;
output reg receive_packet_is_saved;
input all_save_done_reg_rst;
output reg [MAX_TRANSACTION_WIDTH-1 : 0] send_data_size;
output reg [MAX_TRANSACTION_WIDTH-1 : 0] max_receive_buff_siz;
131,6 → 144,13
output reg [Yw-1 : 0] dest_y;
output reg [Cw-1 : 0] pck_class;
output reg send_start, receive_start;
 
//synthesis translate_off
//synopsys translate_off
input [Xw-1 : 0] current_x;
input [Yw-1 : 0] current_y;
//synthesis translate_on
//synopsys translate_on
179,7 → 199,9
receive_en_next = receive_en;
receive_packet_is_saved_next = receive_packet_is_saved;
max_receive_buff_siz_next = max_receive_buff_siz;
if (receive_fsm_is_ideal & receive_vc_got_packet & receive_en ) begin
if(all_save_done_reg_rst) receive_packet_is_saved_next=1'b0;
 
if (receive_vc_got_packet & receive_en ) begin
receive_en_next = 1'b0;
end
if(receive_done) begin
191,12 → 213,21
if (send_fsm_is_ideal) send_start_addr_next={{OFFSET_w{1'b0}},s_dat_i [Dw-1 : OFFSET_w]};
end //SEND_STRT_WB_ADDR
SEND_DATA_SIZE_WB_ADDR: begin
if (send_fsm_is_ideal) send_data_size_next=s_dat_i [MAX_TRANSACTION_WIDTH+OFFSET_w-1 : OFFSET_w];
if (send_fsm_is_ideal) send_data_size_next=s_dat_i [MAX_TRANSACTION_WIDTH-1 : 0];
end //DATA_SIZE_WB_ADDR
SEND_DEST_WB_ADDR: begin
if (send_fsm_is_ideal) begin
dest_x_next = s_dat_i[Xw-1 : 0];
dest_y_next = s_dat_i [(DST_ADR_HDR_WIDTH/2)+Yw-1 : DST_ADR_HDR_WIDTH/2];
dest_y_next = s_dat_i [(DST_ADR_HDR_WIDTH/2)+Yw-1 : DST_ADR_HDR_WIDTH/2];
//synthesis translate_off
//synopsys translate_off
if(DEBUG_EN)begin
if((s_dat_i[Xw-1 : 0] == current_x) && (s_dat_i [(DST_ADR_HDR_WIDTH/2)+Yw-1 : DST_ADR_HDR_WIDTH/2] == current_y))begin
$display("%t: ERROR: source destination address are identical in: %m",$time);
end
end
//synthesis translate_on
//synopsys translate_on
pck_class_next= s_dat_i[Cw+DST_ADR_HDR_WIDTH-1 : DST_ADR_HDR_WIDTH];
send_start_next = 1'b1;
end
/mpsoc/src_peripheral/ram/wb_single_port_ram.v
233,8 → 233,8
function [15:0]i2s;
input integer c; integer i; integer tmp; begin
tmp =0;
for (i=0; i<2; i=i+1'b1) begin
tmp = tmp + (((c % 10) + 6'd48) << i*8);
for (i=0; i<2; i=i+1) begin
tmp = tmp + (((c % 10) + 48) << i*8);
c = c/10;
end
i2s = tmp[15:0];
/mpsoc/src_processor/mor1kx-3.1/rtl/mor1k.v
1,5 → 1,11
`timescale 1ns/1ps
 
module mor1k #(
parameter OPTION_DCACHE_SNOOP = "ENABLED",// "NONE","ENABLED"
parameter FEATURE_INSTRUCTIONCACHE ="ENABLED",// "NONE","ENABLED"
parameter FEATURE_DATACACHE ="ENABLED",// "NONE","ENABLED"
parameter FEATURE_IMMU ="ENABLED",// "NONE","ENABLED"
parameter FEATURE_DMMU="ENABLED",// "NONE","ENABLED"
parameter OPTION_OPERAND_WIDTH=32,
parameter IRQ_NUM=32
 
8,6 → 14,11
clk,
rst,
cpu_en,
//snoop_interface
snoop_adr_i,
snoop_en_i,
 
// Wishbone interface
iwbm_adr_o,
44,6 → 55,10
 
input clk;
input rst;
input [31:0] snoop_adr_i;
input snoop_en_i;
 
// Wishbone interface
output [31:0] iwbm_adr_o;
88,28 → 103,34
// wire du_stall_o,
wire [31:0] dadr_o,iadr_o;
wire [31:0] snoop_adr_i_byte;
assign iwbm_adr_o= {2'b00,iadr_o[31:2]};
assign dwbm_adr_o= {2'b00,dadr_o[31:2]};
assign snoop_adr_i_byte= {snoop_adr_i[29:0],2'b00};
 
 
 
 
 
mor1kx #(
.OPTION_DCACHE_SNOOP(OPTION_DCACHE_SNOOP),
.FEATURE_DEBUGUNIT("ENABLED"),
.FEATURE_CMOV("ENABLED"),
.FEATURE_INSTRUCTIONCACHE("ENABLED"),
.FEATURE_INSTRUCTIONCACHE(FEATURE_INSTRUCTIONCACHE),
.OPTION_ICACHE_BLOCK_WIDTH(5),
.OPTION_ICACHE_SET_WIDTH(8),
.OPTION_ICACHE_WAYS(2),
.OPTION_ICACHE_LIMIT_WIDTH(32),
.FEATURE_IMMU("ENABLED"),
.FEATURE_DATACACHE("ENABLED"),
.FEATURE_IMMU(FEATURE_IMMU),
.FEATURE_DATACACHE(FEATURE_DATACACHE),
.OPTION_DCACHE_BLOCK_WIDTH(5),
.OPTION_DCACHE_SET_WIDTH(8),
.OPTION_DCACHE_WAYS(2),
.OPTION_DCACHE_LIMIT_WIDTH(31),
.FEATURE_DMMU("ENABLED"),
.FEATURE_DMMU(FEATURE_DMMU),
.OPTION_PIC_TRIGGER("LATCHED_LEVEL"),
 
.IBUS_WB_TYPE("B3_REGISTERED_FEEDBACK"),
.DBUS_WB_TYPE("B3_REGISTERED_FEEDBACK"),
180,8 → 201,8
.multicore_coreid_i (32'd0),
.multicore_numcores_i (32'd0),
 
.snoop_adr_i (32'd0),
.snoop_en_i (1'b0),
.snoop_adr_i (snoop_adr_i_byte),
.snoop_en_i (snoop_en_i),
 
.du_addr_i(du_addr_i),
.du_stb_i(du_stb_i),
/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx-defines.v
1,3 → 1,4
`timescale 1ns/1ps
/* ****************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cache_lru.v
82,6 → 82,7
// .lru_pre (lru_pre[NUMWAYS-1:0]),
// .lru_post (lru_post[NUMWAYS-1:0]));
 
`timescale 1ns/1ps
 
module mor1kx_cache_lru(/*AUTOARG*/
// Outputs
/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_simple_dpram_sclk.v
11,6 → 11,7
Copyright (C) 2012 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
 
******************************************************************************/
`timescale 1ns/1ps
 
module mor1kx_simple_dpram_sclk
#(
/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_true_dpram_sclk.v
9,7 → 9,7
Copyright (C) 2013 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
 
******************************************************************************/
 
`timescale 1ns/1ps
module mor1kx_true_dpram_sclk
#(
parameter ADDR_WIDTH = 32,
/mpsoc/src_verilator/parameter.v
20,22 → 20,22
localparam C=0;
localparam DEBUG_EN=0;
localparam ADD_PIPREG_AFTER_CROSSBAR=1'b0;
localparam FIRST_ARBITER_EXT_P_EN=1;
localparam SWA_ARBITER_TYPE="RRA";
localparam FIRST_ARBITER_EXT_P_EN=1;
localparam WEIGHTw=4;
localparam AVC_ATOMIC_EN=0;
localparam ROUTE_SUBFUNC="XY";
localparam MAX_SBP_NUM =0;
localparam CLASS_SETTING={V{1'b1}};
localparam CVw=(C==0)? V : C * V;
/* verilator lint_off WIDTH */
localparam P=(TOPOLOGY=="RING" || TOPOLOGY=="LINE")? 3 : 5;
localparam ROUTE_TYPE = (ROUTE_NAME == "XY" || ROUTE_NAME == "TRANC_XY" )? "DETERMINISTIC" :
(ROUTE_NAME == "DUATO" || ROUTE_NAME == "TRANC_DUATO" )? "FULL_ADAPTIVE": "PAR_ADAPTIVE";
/* verilator lint_on WIDTH */
//simulation parameter
//simulation parameter
localparam MAX_PCK_NUM = 100000000;
localparam MAX_PCK_SIZ = 16383;
localparam MAX_SIM_CLKs= 100000000;
localparam TIMSTMP_FIFO_NUM = 16;
 
`endif
/mpsoc/src_verilator/simulator.cpp
30,9 → 30,9
 
#include "traffic_task_graph.h"
 
#define STND_DEV_EN 1
 
 
 
//Vrouter *router;
Vrouter *router[NC]; // Instantiation of module
Vnoc *noc;
81,9 → 81,17
 
 
#if (STND_DEV_EN)
#include <math.h>
//#include <math.h>
double sqroot (double s){
int i;
double root = s/3;
if (s<=0) return 0;
for(i=0;i<32;i++) root = (root +s/root)/2;
return root;
}
double sum_clk_pow2=0;
double sum_clk_pow2_per_class[C]={0};
double sum_clk_pow2_per_class[C];
double standard_dev( double , unsigned int, double);
#endif
 
615,6 → 623,8
if(ratio==RATIO_INIT) first_avg_latency_flit=avg_latency_flit;
#if (STND_DEV_EN)
std_dev= standard_dev( sum_clk_pow2,total_pck_num, avg_latency_flit);
printf(" standard_dev = %f\n",std_dev);
// sprintf(file_name,"%s_std.txt",out_file_name);
//update_file( file_name,avg_throughput,std_dev);
 
776,15 → 786,30
* ******************/
 
#if (STND_DEV_EN)
/************************
* std_dev = sqrt[(B-A^2/N)/N] = sqrt [(B/N)- (A/N)^2] = sqrt [B/N - mean^2]
* A = sum of the values
* B = sum of the squarded values
* *************/
 
 
double standard_dev( double sum_pow2, unsigned int total_num, double average){
double std_dev;
/*
double A, B, N;
N= total_num;
A= average * N;
B= sum_pow2;
 
std_dev = sum_pow2/(double)total_num;
std_dev -= (average*average);
A=(A*A)/N;
std_dev = (B-A)/N;
std_dev = sqrt(std_dev);
*/
 
std_dev = sum_pow2/(double)total_num; //B/N
std_dev -= (average*average);// (B/N) - mean^2
std_dev = sqroot(std_dev);// sqrt [B/N - mean^2]
 
return std_dev;
 
}

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