URL
https://opencores.org/ocsvn/aor3000/aor3000/trunk
Subversion Repositories aor3000
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Rev 2 → Rev 3
/aor3000/trunk/README.md
116,7 → 116,7
- an Altera SDRAM controller; |
- a simple time interrupt device; |
- onchip memory for the boot code of the aoR3000; |
- a Altera JTAG to Avalon Master Bridge to upload the Linux kernel; |
- an Altera JTAG to Avalon Master Bridge to upload the Linux kernel; |
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The SoC is designed for the Terasic DE2-115 board. |
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