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+`include "discipline.h"
+`include "constants.h"
+
+module inv1x (out, in, vdd, vss, vsub);
+
+output out; voltage out;
+input in; voltage in;
+input vdd, vss, vsub; voltage vdd, vss, vsub;
+parameter real vh = 1.3; // output voltage in high state
+parameter real vl = 0; // output voltage in low state
+parameter real vth = 0.65; // threshold voltage at inputs
+parameter real td = 300e-12 from [0:inf); // delay to start of output transition
+parameter real tt = 300e-12 from [0:inf); // transition time of output signals
+
+integer in_logic;
+
+
+analog begin
+ @(cross(V(in) -vth,0)) in_logic = (V(in) -vth);
+// @(cross(V(in) - 0.3,-1)) in_logic = 0;
+
+
+ V(out) <+ transition( !(in_logic) ? vh : vl, td, tt );
+end
+endmodule
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+module nand2 (out, in1,in2,vdd,vss,vsub);
+output out;
+input in1,in2;
+input vdd, vss, vsub;
+nand(out, in1,in2);
+endmodule
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+`include "discipline.h"
+`include "constants.h"
+// Simple logic gates
+//
+// Version 1a, 24 November 2006
+//
+// Ken Kundert
+//
+// Downloaded from The Designer's Guide (www.designers-guide.org).
+// Post any questions to www.designers-guide.org/Forum
+
+//
+// 2-input Nand gate
+//
+
+module nand2 (out, in1, in2, vdd, vss, vsub);
+
+output out; voltage out;
+input in1, in2; voltage in1, in2;
+input vdd, vss, vsub; voltage vdd, vss, vsub;
+parameter real vh = 1.5; // output voltage in high state
+parameter real vl = 0; // output voltage in low state
+parameter real vth = 0.65; // threshold voltage at inputs
+parameter real td = 1e-9 from [0:inf); // delay to start of output transition
+parameter real tt = 1e-9 from [0:inf); // transition time of output signals
+
+integer in1_logic, in2_logic;
+integer val_logic;
+real vout;
+analog begin
+ @(cross(V(in1) - vth)) in1_logic = (V(in1) > vth);
+ @(cross(V(in2) - vth)) in2_logic = (V(in2) > vth);
+ val_logic = (in1_logic + 2*in2_logic) ;
+
+ case (val_logic)
+ 0: vout = vh;
+ 1: vout = vh;
+ 2: vout = vl;
+ 3: vout = vl;
+ default: vout = -vh;
+ endcase
+
+ V(out) <+ transition( vout, td, tt );
+end
+endmodule
+
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+`include "discipline.h"
+`include "constants.h"
+
+module osc (vsub,vss,clk,vdd,en_osc,t );
+ input vsub;
+ input vss;
+ output clk;
+ input vdd;
+ input en_osc;
+ output t;
+
+electrical vsub, vss, clk, vdd, en_osc;
+electrical t;
+
+parameter real vth = 0.65; // threshold voltage at inputs
+parameter real td = 1e-9 from [0:inf); // delay to start of output transition
+parameter real tt = 1e-9 from [0:inf); // transition time of output signals
+parameter real per = 252e-9;
+parameter real pw = 16e-9;
+integer en_osc_logic, clk_count;
+
+real t_start;
+real t_pw;
+analog begin
+
+ @(cross(V(en_osc) - vth)) begin
+ en_osc_logic = (V(en_osc) > vth);
+ clk_count = 0;
+ t_start = 0.0;
+ t_pw = (en_osc_logic) ? $abstime + 3.5*pw : 0.0;
+ // ensure the next step is not chosen after the timer expired!
+ $bound_step(pw);
+ end
+
+ @(timer(t_start, t_pw, 1e-9)) begin
+ if (en_osc_logic) begin
+ t_start = $abstime;
+ t_pw = pw;
+ clk_count = (clk_count >= 7) ? 0 : clk_count+1;
+ end
+ end
+
+ // determine duty-cycle: clk_count>0 (max), clk_count>7 (mid), clk_count==15 (min)
+ V(clk,vss) <+ V(vdd,vss)*transition( (clk_count>0) & en_osc_logic , td, tt ) ;
+ V(t) <+ 0; // transition( t_start+t_pw, td, tt); // test output for debug
+end
+
+endmodule
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