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/trunk/incrementer.v
0,0 → 1,9
module incrementer(in, out);
parameter dw = 8;
input [dw-1:0] in;
output [dw-1:0] out;
assign out = in + 1;
endmodule
/trunk/mux2.v
0,0 → 1,16
module mux2( mux_out, data_0, data_1, select);
 
parameter dw = 8;
input [dw-1:0] data_1, data_0;
input [0:0] select;
output reg [dw-1:0] mux_out;
// choose between the two inputs
always @ ( data_1 or data_0 or select)
case (select)// (* synthesis parallel_case *)
1'd0: mux_out = data_0;
1'd1: mux_out = data_1;
default: mux_out = {dw{1'bx}};
endcase
endmodule
/trunk/reg_file.v
0,0 → 1,18
module reg_file (Read_Addr_1, Data_Out_1, Clock);
 
parameter aw = 8; //address bus width
parameter dw = 48; //size of each memory element
parameter size = (1<<aw);
output [dw-1:0] Data_Out_1;
input [aw-1:0] Read_Addr_1;
input Clock;
reg [dw-1:0] Reg_File [0:size-1];
/*
always @ (posedge Clock) begin
Data_Out_1 <= Reg_File[Read_Addr_1];
end
*/
//assign Data_Out_a = {{dw-aw{1'b0}}, Read_Addr_1};
endmodule
/trunk/mux2r.v
0,0 → 1,24
module mux2r( mux_out, data_0, data_1, select, reset_n);
 
parameter dw = 8;
input [dw-1:0] data_1, data_0;
input [0:0] select;
input reset_n;
output reg [dw-1:0] mux_out;
// choose between the two inputs
always @ ( data_1 or data_0 or select or reset_n)
if(!reset_n)
begin
mux_out = 0;
end
else
begin
case (select)// (* synthesis parallel_case *)
1'd0: mux_out = data_0;
1'd1: mux_out = data_1;
default: mux_out = {dw{1'bx}};
endcase
end
endmodule
/trunk/mux4.v
0,0 → 1,18
module mux4( mux_out, data_0, data_1, data_2, data_3, select);
 
parameter dw = 32;
input [dw-1:0] data_3, data_2, data_1, data_0;
input [1:0] select;
output reg [dw-1:0] mux_out;
// choose between the four inputs
always @ ( data_3 or data_2 or data_1 or data_0 or select)
case (select)// (* synthesis parallel_case *)
2'd0: mux_out = data_0;
2'd1: mux_out = data_1;
2'd2: mux_out = data_2;
2'd3: mux_out = data_3;
default: mux_out = {dw{1'bx}};
endcase
endmodule
/trunk/mux8.v
0,0 → 1,22
module mux8( mux_out, data_0, data_1, data_2, data_3, data_4, data_5, data_6, data_7, select);
 
parameter dw = 8;
input [dw-1:0] data_0, data_1, data_2, data_3, data_4, data_5, data_6, data_7;
input [2:0] select;
output reg [dw-1:0] mux_out;
// choose between the two inputs
always @ ( data_0 or data_1 or data_2 or data_3 or data_4 or data_5 or data_6 or data_7 or select)
case (select)// (* synthesis parallel_case *)
3'd0: mux_out = data_0;
3'd1: mux_out = data_1;
3'd2: mux_out = data_2;
3'd3: mux_out = data_3;
3'd4: mux_out = data_4;
3'd5: mux_out = data_5;
3'd6: mux_out = data_6;
3'd7: mux_out = data_7;
default: mux_out = {dw{1'bx}};
endcase
endmodule
/trunk/brisc.v
0,0 → 1,63
module trisc(cond, out_sig, clk, reset_n);
 
//independent parameters
parameter ncs = 3; //number of bits to select cw+1 inputs i.e 2^ncs = (cw+1)
parameter aw = 8; //address width
parameter dw = 20; //data width for internal control
parameter ow = 28; //control output size
 
//dependant parameters (based on independant parameters
parameter cw = (1<<ncs)-1; //number of conditional inputs (cw+1 must be a power of 2)
parameter pms = (1<<aw); // program memory size. depends on address width ( pms = 2 ^ aw )
 
// ow + dw defines the width of one memory block of program memory
 
input [cw-1:0] cond; // one conditional input is from down counter
input [0:0] clk, reset_n;
output [ow-1:0] out_sig;
 
//output of program memory
wire [aw-1:0] prog_ctr_a; // program counte address
wire [aw-1:0] sub_a; // subroutine address
wire [aw-1:0] branch_a; // branch address
wire [ncs-1:0] cond_sel;
wire [3:0] nal_sel;
wire [0:0] pp; // push/pop_n
wire [0:0] cl; //count/load_n
wire [0:0] ce; //counter enable
wire [0:0] sse; // subroutine stack enable
wire [0:0] cse; // counter stack enable
 
wire [0:0] cc; // output of conditinal select mux
 
//output of NAL
wire [aw-1:0] next_inst_a; //address of next instruction to execute
 
wire [aw:0] dc; // down counter
wire [aw:0] lc; // output of loop counter lifo
wire [aw:0] cm; // output of counter mux
wire [aw:0] ctr_o; // output of down counter register
 
wire [aw-1:0] inc_o; // output of incrementer
 
// program memory
prog_mem mem (.addr(next_inst_a),.clk(clk),.dout({out_sig, nal_sel, cond_sel, cse, sse, ce, cl, pp, branch_a}));
 
nal #(.dw(aw)) next_addr(next_inst_a, ctr_o[aw-1:0], branch_a, sub_a, prog_ctr_a, cc, nal_sel[1:0], nal_sel[3:2], reset_n);
 
 
lifo #(.dw(aw+1)) loop_cnt(ctr_o, lc, clk, cse, pp, reset_n);
mux2 #(.dw(aw+1)) counter_m(cm, {1'b0, branch_a}, lc, cl);
 
down_counter #(.dw(aw+1)) dn_ctr(cm, dc);
register_e #(.dw(aw+1)) ctr(dc, ctr_o, clk, reset_n, ce);
 
mux8 #(.dw(1)) cond_m(cc, ctr_o[aw], cond[0], cond[1], cond[2], cond[3], cond[4], cond[5], cond[6], cond_sel);
 
 
incrementer #(.dw(aw)) inc(next_inst_a, inc_o);
register #(.dw(aw)) prog_ctr(inc_o, prog_ctr_a, clk, reset_n);
 
lifo #(.dw(aw)) sub(prog_ctr_a, sub_a, clk, sse, pp, reset_n);
 
endmodule
/trunk/register.v
0,0 → 1,20
module register(in, out, clk, reset_n);
 
parameter dw = 8;
 
input [dw-1:0] in;
input clk;
input reset_n;
 
output reg [dw-1:0] out;
 
 
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
out <= 0;
else
out <= in;
end
 
endmodule
/trunk/prog_mem.v
0,0 → 1,108
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2006 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synopsys directives "translate_off/translate_on" specified below are
// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
 
// You must compile the wrapper file prog_mem.v when simulating
// the core, prog_mem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
 
`timescale 1ns/1ps
 
module prog_mem(
addr,
clk,
dout);
 
 
input [7 : 0] addr;
input clk;
output [47 : 0] dout;
 
// synopsys translate_off
 
BLKMEMSP_V6_2 #(
8, // c_addr_width
"0", // c_default_data
256, // c_depth
0, // c_enable_rlocs
0, // c_has_default_data
0, // c_has_din
0, // c_has_en
0, // c_has_limit_data_pitch
0, // c_has_nd
0, // c_has_rdy
0, // c_has_rfd
0, // c_has_sinit
0, // c_has_we
18, // c_limit_data_pitch
"prog_mem.mif", // c_mem_init_file
0, // c_pipe_stages
0, // c_reg_inputs
"0", // c_sinit_value
48, // c_width
0, // c_write_mode
"0", // c_ybottom_addr
1, // c_yclk_is_rising
1, // c_yen_is_high
"hierarchy1", // c_yhierarchy
0, // c_ymake_bmm
"16kx1", // c_yprimitive_type
1, // c_ysinit_is_high
"1024", // c_ytop_addr
0, // c_yuse_single_primitive
1, // c_ywe_is_high
1) // c_yydisable_warnings
inst (
.ADDR(addr),
.CLK(clk),
.DOUT(dout),
.DIN(),
.EN(),
.ND(),
.RFD(),
.RDY(),
.SINIT(),
.WE());
 
 
// synopsys translate_on
 
// FPGA Express black box declaration
// synopsys attribute fpga_dont_touch "true"
// synthesis attribute fpga_dont_touch of prog_mem is "true"
 
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of prog_mem is "black_box"
 
endmodule
 
/trunk/down_counter.v
0,0 → 1,8
module down_counter(in, out);
parameter dw = 8;
input [dw-1:0] in;
output [dw-1:0] out;
assign out = in - 1;
endmodule
/trunk/register_e.v
0,0 → 1,22
module register_e(in, out, clk, reset_n, enable);
 
parameter dw = 8 ;
 
input [dw-1:0] in;
input clk;
input reset_n;
input enable;
 
output reg [dw-1:0] out;
 
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
out <= 0;
else if (enable)
out <= in;
// else
// out <= {dw{1'bx}};
end
 
endmodule
/trunk/lifo.v
0,0 → 1,25
// List in First out (LIFO)
module lifo(din, dout, clk, enable, push_pop, reset_n);
parameter dw = 8; // data width
input [dw-1: 0] din;
output wire [dw-1: 0] dout;
input clk;
input enable;
input push_pop; // high to push, low to pop
input reset_n;
wire [dw-1:0] m1o, m2o, m3o, r2o, r3o;
mux2 #(.dw(dw)) mux3(m3o, {dw{1'b0}}, r2o, push_pop);
register_e #(.dw(dw)) reg3(m3o, r3o, clk, reset_n, enable);
mux2 #(.dw(dw)) mux2(m2o, r3o, dout, push_pop);
register_e #(.dw(dw)) reg2(m2o, r2o, clk, reset_n, enable);
mux2 #(.dw(dw)) mux1(m1o, r2o, din, push_pop);
register_e #(.dw(dw)) reg1(m1o, dout, clk, reset_n, enable);
 
endmodule
/trunk/stimulus_trisc.v
0,0 → 1,35
module stimulus_trisc();
 
parameter ncs = 3;
parameter cw = (1<<ncs)-1; //number of conditional inputs (cw+1 must be a power of 2)
 
parameter ow = 28; //control output size
 
reg [cw-1:0] cond;
wire [ow-1:0] out_sig;
reg clk;
reg reset_n;
 
trisc processor(cond, out_sig, clk, reset_n);
 
initial
begin
clk = 0;
reset_n = 1;
cond = 0;
#1
reset_n = 0;
 
#1
reset_n = 1;
 
cond = 1;
end
 
always
#5 clk = ~clk;
 
 
 
endmodule
/trunk/nal.v
0,0 → 1,18
module nal(out, in1, in2, in3, in4, cond, sel1, sel2, reset_n);
 
parameter dw = 8;
 
input [dw-1:0] in1, in2, in3, in4;
input cond;
input [1:0] sel1, sel2;
input reset_n;
 
output [dw-1:0] out;
 
wire [dw-1:0] m1o, m2o;
 
mux4 #(.dw(dw)) mux1(m1o, in1, in2, in3, in4, sel1);
mux4 #(.dw(dw)) mux2(m2o, in1, in2, in3, in4, sel2);
mux2r #(.dw(dw)) mux3(out, m1o, m2o, cond, reset_n);
 
endmodule

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