URL
https://opencores.org/ocsvn/brsfmnce/brsfmnce/trunk
Subversion Repositories brsfmnce
Compare Revisions
- This comparison shows the changes necessary to convert path
/brsfmnce
- from Rev 2 to Rev 3
- ↔ Reverse comparison
Rev 2 → Rev 3
/trunk/RTL/BRSFmnCE.v
32,16 → 32,16
// 1.10 13H12 MAM Prepared for release on Opencores.com. Converted to |
// Verilog-2001 format. |
// |
// Additional Comments: |
// |
// Note: Initialization of the FIFO memory contents only occurs once. If |
// Reset is reasserted, current implementation cannot reinitialize |
// memory contents unless Reset also causes reload of the configuration |
// Additional Comments: |
// |
// Note: Initialization of the FIFO memory contents only occurs once. If |
// Reset is reasserted, current implementation cannot reinitialize |
// memory contents unless Reset also causes reload of the configuration |
// image of the SRAM-based FPGA. |
// |
//////////////////////////////////////////////////////////////////////////////// |
|
module BRSFmnCE ( |
module BRSFmnCE #( |
parameter pAddr = 10, // Number of Address Bits |
parameter pWidth = 8, // Number of Data Bits |
parameter pRAMInitSize = 128, // Amount Data to Init into FIFO RAM |
48,23 → 48,23
parameter pFRAM_Init = "RAMINIT.mif" // RAM Memory Initialization File |
)( |
input Rst, // System Reset - Synchronous |
input Clk, // System Clock |
input Clk, // System Clock |
|
input Clr, // FIFO Clear |
|
|
input WE, // FIFO Write Enable |
input [(pWidth - 1):0] DI, // FIFO Input Data |
|
|
input RE, // FIFO Read Enable |
output reg [(pWidth - 1):0] DO, // FIFO Output Data |
output reg ACK, // FIFO Read Acknowledge |
|
|
output reg FF, // FIFO Full Flag |
output reg AF, // FIFO Almost Full Flag (Full - 1) |
output HF, // FIFO Half Full Flag |
output reg AE, // FIFO Almost Empty Flag (Count == 1) |
output reg EF, // FIFO Empty Flag (Count == 0) |
|
|
output [pAddr:0] Cnt // FIFO Word Count |
); |
|
221,7 → 221,7
// |
|
initial |
$readmemh(pFRAM_Init, FRAM); |
$readmemh(pFRAM_Init, FRAM, 0, ((1 << pAddr) - 1)); |
|
always @(posedge Clk) |
begin |
/trunk/RTL/RAMINIT.mif
1,7 → 1,3
/////////////////////////////////////////////////////////////////////////////// |
// |
// Block RAM Initialization File |
// |
31 |
37 |
30 |
19,17 → 15,17
55 |
41 |
52 |
54 |
20 |
52 |
65 |
76 |
3A |
20 |
31 |
2E |
32 |
2E |
54 |
20 |
52 |
65 |
76 |
3A |
20 |
31 |
2E |
32 |
2E |
30 |
0A |
A9 |
42,15 → 38,15
41 |
6C |
6C |
20 |
52 |
69 |
67 |
68 |
74 |
73 |
20 |
52 |
69 |
67 |
68 |
74 |
73 |
20 |
52 |
65 |
73 |
65 |
130,5 → 126,899
30 |
35 |
0A |
|
|
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
/trunk/Sim/tb_BRSFmnCE.v
16,12 → 16,12
// |
// Dependencies: None |
// |
// Revision: |
// |
// 1.00 08F27 MAM File Created |
// |
// Revision: |
// |
// 1.00 08F27 MAM File Created |
// |
// 1.10 13G12 MAM Prepared for release on Opencore.com. |
// |
// |
// Additional Comments: |
// |
//////////////////////////////////////////////////////////////////////////////// |
29,43 → 29,49
module tb_BRSFmnCE; |
|
// Inputs |
reg Rst; |
reg Clk; |
reg WE; |
reg RE; |
reg [7:0] DI; |
reg Rst; |
reg Clk; |
|
reg Clr; |
|
reg WE; |
reg [7:0] DI; |
|
reg RE; |
wire [7:0] DO; |
wire ACK; |
|
wire FF; |
wire AF; |
wire HF; |
wire AE; |
wire EF; |
|
wire [10:0] Cnt; |
|
// Outputs |
wire [7:0] DO; |
wire ACK; |
wire FF; |
wire AF; |
wire HF; |
wire AE; |
wire EF; |
wire [10:0] Cnt; |
|
integer i; |
|
// Instantiate the Unit Under Test (UUT) |
|
|
BRSFmnCE uut ( |
.Rst(Rst), |
.Clk(Clk), |
|
.Clr(Clr), |
|
.WE(WE), |
.DI(DI), |
|
|
.RE(RE), |
.DO(DO), |
.ACK(ACK), |
|
|
.FF(FF), |
.AF(AF), |
.HF(HF), |
.AE(AE), |
.EF(EF), |
|
|
.Cnt(Cnt) |
); |
|
72,18 → 78,19
initial begin |
// Initialize Inputs |
Rst = 1; |
Clk = 1; |
WE = 0; |
RE = 0; |
DI = $random(5); |
Clk = 1; |
Clr = 0; |
WE = 0; |
RE = 0; |
DI = $random(5); |
|
i = 0; |
i = 0; |
|
// Wait 100 ns for global reset to finish |
#106 Rst = 0; |
#101 Rst = 0; |
|
// Add stimulus here |
|
// Add stimulus here |
|
while (AF != 1) begin |
@(posedge Clk) #1; |
if(AF != 1) begin |
113,15 → 120,15
@(posedge Clk) #1; RE = 0; i = i - 1; |
|
end |
|
//////////////////////////////////////////////////////////////////////////////// |
// |
// Clock |
// |
|
//////////////////////////////////////////////////////////////////////////////// |
// |
// Clock |
// |
|
always #5 Clk = ~Clk; |
|
//////////////////////////////////////////////////////////////////////////////// |
|
//////////////////////////////////////////////////////////////////////////////// |
|
endmodule |
|