URL
https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk
Subversion Repositories bustap-jtag
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 24 to Rev 25
- ↔ Reverse comparison
Rev 24 → Rev 25
/bustap-jtag/trunk/rtl/xilinx/vivado_ip/component.xml
0,0 → 1,1417
<?xml version="1.0" encoding="UTF-8"?> |
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> |
<spirit:vendor>OpenCores</spirit:vendor> |
<spirit:library>user</spirit:library> |
<spirit:name>bustap_jtag_v1_0</spirit:name> |
<spirit:version>1.0</spirit:version> |
<spirit:busInterfaces> |
<spirit:busInterface> |
<spirit:name>s00_axi</spirit:name> |
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/> |
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/> |
<spirit:slave> |
<spirit:memoryMapRef spirit:memoryMapRef="s00_axi"/> |
</spirit:slave> |
<spirit:portMaps> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>AWADDR</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s00_axi_awaddr</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>AWPROT</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s00_axi_awprot</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>AWVALID</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s00_axi_awvalid</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>AWREADY</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s00_axi_awready</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>WDATA</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s00_axi_wdata</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>WSTRB</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s00_axi_wstrb</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>WVALID</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s00_axi_wvalid</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>WREADY</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s00_axi_wready</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>BRESP</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s00_axi_bresp</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>BVALID</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s00_axi_bvalid</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>BREADY</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s00_axi_bready</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>ARADDR</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s00_axi_araddr</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>ARPROT</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s00_axi_arprot</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>ARVALID</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s00_axi_arvalid</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>ARREADY</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s00_axi_arready</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>RDATA</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s00_axi_rdata</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>RRESP</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s00_axi_rresp</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>RVALID</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s00_axi_rvalid</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>RREADY</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s00_axi_rready</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
</spirit:portMaps> |
</spirit:busInterface> |
<spirit:busInterface> |
<spirit:name>m00_axi</spirit:name> |
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/> |
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/> |
<spirit:master/> |
<spirit:portMaps> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>AWADDR</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>m00_axi_awaddr</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>AWPROT</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>m00_axi_awprot</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>AWVALID</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>m00_axi_awvalid</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>AWREADY</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>m00_axi_awready</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>WDATA</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>m00_axi_wdata</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>WSTRB</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>m00_axi_wstrb</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>WVALID</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>m00_axi_wvalid</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>WREADY</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>m00_axi_wready</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>BRESP</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>m00_axi_bresp</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>BVALID</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>m00_axi_bvalid</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>BREADY</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>m00_axi_bready</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>ARADDR</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>m00_axi_araddr</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>ARPROT</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>m00_axi_arprot</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>ARVALID</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>m00_axi_arvalid</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>ARREADY</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>m00_axi_arready</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>RDATA</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>m00_axi_rdata</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>RRESP</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>m00_axi_rresp</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>RVALID</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>m00_axi_rvalid</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>RREADY</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>m00_axi_rready</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
</spirit:portMaps> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>FREQ_HZ</spirit:name> |
<spirit:value spirit:id="BUSIFPARAM_VALUE.M00_AXI.FREQ_HZ"/> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:busInterface> |
<spirit:busInterface> |
<spirit:name>s00_axi_signal_clock</spirit:name> |
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/> |
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/> |
<spirit:slave/> |
<spirit:portMaps> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>CLK</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s00_axi_aclk</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
</spirit:portMaps> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>ASSOCIATED_BUSIF</spirit:name> |
<spirit:value spirit:format="string" spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.S00_AXI_SIGNAL_CLOCK.ASSOCIATED_BUSIF">s00_axi</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:busInterface> |
<spirit:busInterface> |
<spirit:name>s00_axi_signal_reset</spirit:name> |
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/> |
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/> |
<spirit:slave/> |
<spirit:portMaps> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>RST</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>s00_axi_aresetn</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
</spirit:portMaps> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>POLARITY</spirit:name> |
<spirit:value spirit:format="string" spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.S00_AXI_SIGNAL_RESET.POLARITY" spirit:choiceRef="choices_2">ACTIVE_LOW</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:busInterface> |
<spirit:busInterface> |
<spirit:name>m00_axi_signal_clock</spirit:name> |
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/> |
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/> |
<spirit:master/> |
<spirit:portMaps> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>CLK</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>m00_axi_aclk</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
</spirit:portMaps> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>ASSOCIATED_BUSIF</spirit:name> |
<spirit:value spirit:format="string" spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.M00_AXI_SIGNAL_CLOCK.ASSOCIATED_BUSIF">m00_axi</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:busInterface> |
<spirit:busInterface> |
<spirit:name>m00_axi_signal_reset</spirit:name> |
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/> |
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/> |
<spirit:master/> |
<spirit:portMaps> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>RST</spirit:name> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>m00_axi_aresetn</spirit:name> |
</spirit:physicalPort> |
</spirit:portMap> |
</spirit:portMaps> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>POLARITY</spirit:name> |
<spirit:value spirit:format="string" spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.M00_AXI_SIGNAL_RESET.POLARITY" spirit:choiceRef="choices_4">ACTIVE_LOW</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:busInterface> |
</spirit:busInterfaces> |
<spirit:memoryMaps> |
<spirit:memoryMap> |
<spirit:name>s00_axi</spirit:name> |
<spirit:addressBlock> |
<spirit:name>reg0</spirit:name> |
<spirit:baseAddress spirit:format="bitString" spirit:resolve="user" spirit:bitStringLength="32">0</spirit:baseAddress> |
<spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="pow(2,(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH')) - 1) + 1)">16</spirit:range> |
<spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH')) - 1) + 1">32</spirit:width> |
<spirit:usage>register</spirit:usage> |
</spirit:addressBlock> |
</spirit:memoryMap> |
</spirit:memoryMaps> |
<spirit:model> |
<spirit:views> |
<spirit:view> |
<spirit:name>xilinx_verilogsynthesis</spirit:name> |
<spirit:displayName>Verilog Synthesis</spirit:displayName> |
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier> |
<spirit:language>verilog</spirit:language> |
<spirit:modelName>bustap_jtag_v1_0</spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName> |
</spirit:fileSetRef> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>viewChecksum</spirit:name> |
<spirit:value>bbdb8244</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:view> |
<spirit:view> |
<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name> |
<spirit:displayName>Verilog Simulation</spirit:displayName> |
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier> |
<spirit:language>verilog</spirit:language> |
<spirit:modelName>bustap_jtag_v1_0</spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName> |
</spirit:fileSetRef> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>viewChecksum</spirit:name> |
<spirit:value>eae1c910</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:view> |
<spirit:view> |
<spirit:name>xilinx_xpgui</spirit:name> |
<spirit:displayName>UI Layout</spirit:displayName> |
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier> |
<spirit:fileSetRef> |
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName> |
</spirit:fileSetRef> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>viewChecksum</spirit:name> |
<spirit:value>593ee5d6</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:view> |
<spirit:view> |
<spirit:name>xilinx_utilityxitfiles</spirit:name> |
<spirit:displayName>Utility XIT/TTCL</spirit:displayName> |
<spirit:envIdentifier>:vivado.xilinx.com:xit.util</spirit:envIdentifier> |
<spirit:fileSetRef> |
<spirit:localName>xilinx_utilityxitfiles_view_fileset</spirit:localName> |
</spirit:fileSetRef> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>viewChecksum</spirit:name> |
<spirit:value>698ee63a</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
</spirit:view> |
</spirit:views> |
<spirit:ports> |
<spirit:port> |
<spirit:name>s00_axi_aclk</spirit:name> |
<spirit:wire> |
<spirit:direction>in</spirit:direction> |
<spirit:wireTypeDefs> |
<spirit:wireTypeDef> |
<spirit:typeName>wire</spirit:typeName> |
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> |
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> |
</spirit:wireTypeDef> |
</spirit:wireTypeDefs> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
<spirit:name>s00_axi_aresetn</spirit:name> |
<spirit:wire> |
<spirit:direction>in</spirit:direction> |
<spirit:wireTypeDefs> |
<spirit:wireTypeDef> |
<spirit:typeName>wire</spirit:typeName> |
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> |
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> |
</spirit:wireTypeDef> |
</spirit:wireTypeDefs> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
<spirit:name>s00_axi_awaddr</spirit:name> |
<spirit:wire> |
<spirit:direction>in</spirit:direction> |
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<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH')) - 1)">3</spirit:left> |
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right> |
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<spirit:wireTypeDefs> |
<spirit:wireTypeDef> |
<spirit:typeName>wire</spirit:typeName> |
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> |
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> |
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</spirit:wireTypeDefs> |
<spirit:driver> |
<spirit:defaultValue>0</spirit:defaultValue> |
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<spirit:port> |
<spirit:name>s00_axi_awprot</spirit:name> |
<spirit:wire> |
<spirit:direction>in</spirit:direction> |
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</spirit:vector> |
<spirit:wireTypeDefs> |
<spirit:wireTypeDef> |
<spirit:typeName>wire</spirit:typeName> |
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> |
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> |
</spirit:wireTypeDef> |
</spirit:wireTypeDefs> |
<spirit:driver> |
<spirit:defaultValue>0</spirit:defaultValue> |
</spirit:driver> |
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<spirit:port> |
<spirit:name>s00_axi_awvalid</spirit:name> |
<spirit:wire> |
<spirit:direction>in</spirit:direction> |
<spirit:wireTypeDefs> |
<spirit:wireTypeDef> |
<spirit:typeName>wire</spirit:typeName> |
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> |
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> |
</spirit:wireTypeDef> |
</spirit:wireTypeDefs> |
<spirit:driver> |
<spirit:defaultValue>0</spirit:defaultValue> |
</spirit:driver> |
</spirit:wire> |
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<spirit:port> |
<spirit:name>s00_axi_awready</spirit:name> |
<spirit:wire> |
<spirit:direction>out</spirit:direction> |
<spirit:wireTypeDefs> |
<spirit:wireTypeDef> |
<spirit:typeName>wire</spirit:typeName> |
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> |
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> |
</spirit:wireTypeDef> |
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</spirit:wire> |
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<spirit:port> |
<spirit:name>s00_axi_wdata</spirit:name> |
<spirit:wire> |
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH">32</spirit:value> |
</spirit:modelParameter> |
<spirit:modelParameter spirit:dataType="integer"> |
<spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name> |
<spirit:displayName>C S00 Axi Addr Width</spirit:displayName> |
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH">4</spirit:value> |
</spirit:modelParameter> |
<spirit:modelParameter spirit:dataType="integer"> |
<spirit:name>C_M00_AXI_DATA_WIDTH</spirit:name> |
<spirit:displayName>C M00 Axi Data Width</spirit:displayName> |
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M00_AXI_DATA_WIDTH">32</spirit:value> |
</spirit:modelParameter> |
<spirit:modelParameter spirit:dataType="integer"> |
<spirit:name>C_M00_AXI_ADDR_WIDTH</spirit:name> |
<spirit:displayName>C M00 Axi Addr Width</spirit:displayName> |
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M00_AXI_ADDR_WIDTH">4</spirit:value> |
</spirit:modelParameter> |
</spirit:modelParameters> |
</spirit:model> |
<spirit:choices> |
<spirit:choice> |
<spirit:name>choices_0</spirit:name> |
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration> |
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration> |
</spirit:choice> |
<spirit:choice> |
<spirit:name>choices_1</spirit:name> |
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration> |
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration> |
</spirit:choice> |
<spirit:choice> |
<spirit:name>choices_2</spirit:name> |
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration> |
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration> |
</spirit:choice> |
<spirit:choice> |
<spirit:name>choices_3</spirit:name> |
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration> |
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration> |
</spirit:choice> |
<spirit:choice> |
<spirit:name>choices_4</spirit:name> |
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration> |
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration> |
</spirit:choice> |
</spirit:choices> |
<spirit:fileSets> |
<spirit:fileSet> |
<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name> |
<spirit:file> |
<spirit:name>../../xilinx/coregen/scfifo.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
</spirit:file> |
<spirit:file> |
<spirit:name>../../xilinx/coregen/scfifo.ngc</spirit:name> |
<spirit:userFileType>ngc</spirit:userFileType> |
<spirit:userFileType>core</spirit:userFileType> |
</spirit:file> |
<spirit:file> |
<spirit:name>../../xilinx/coregen/chipscope_vio_trig.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
</spirit:file> |
<spirit:file> |
<spirit:name>../../xilinx/coregen/chipscope_vio_trig.ngc</spirit:name> |
<spirit:userFileType>ngc</spirit:userFileType> |
<spirit:userFileType>core</spirit:userFileType> |
</spirit:file> |
<spirit:file> |
<spirit:name>../../xilinx/coregen/chipscope_vio_mask.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
</spirit:file> |
<spirit:file> |
<spirit:name>../../xilinx/coregen/chipscope_vio_mask.ngc</spirit:name> |
<spirit:userFileType>ngc</spirit:userFileType> |
<spirit:userFileType>core</spirit:userFileType> |
</spirit:file> |
<spirit:file> |
<spirit:name>../../xilinx/coregen/chipscope_vio_fifo.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
</spirit:file> |
<spirit:file> |
<spirit:name>../../xilinx/coregen/chipscope_vio_fifo.ngc</spirit:name> |
<spirit:userFileType>ngc</spirit:userFileType> |
<spirit:userFileType>core</spirit:userFileType> |
</spirit:file> |
<spirit:file> |
<spirit:name>../../xilinx/coregen/chipscope_icon.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
</spirit:file> |
<spirit:file> |
<spirit:name>../../xilinx/coregen/chipscope_icon.ngc</spirit:name> |
<spirit:userFileType>ngc</spirit:userFileType> |
<spirit:userFileType>core</spirit:userFileType> |
</spirit:file> |
<spirit:file> |
<spirit:name>../../xilinx/chipscope_vio_addr_mask.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
</spirit:file> |
<spirit:file> |
<spirit:name>../../xilinx/chipscope_vio_adda_trig.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
</spirit:file> |
<spirit:file> |
<spirit:name>../../xilinx/chipscope_vio_adda_fifo.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
</spirit:file> |
<spirit:file> |
<spirit:name>hdl/vendor.h</spirit:name> |
<spirit:fileType>cSource</spirit:fileType> |
</spirit:file> |
<spirit:file> |
<spirit:name>../../up_monitor.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
</spirit:file> |
<spirit:file> |
<spirit:name>hdl/bustap_jtag_v1_0.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
<spirit:userFileType>CHECKSUM_97adde16</spirit:userFileType> |
</spirit:file> |
</spirit:fileSet> |
<spirit:fileSet> |
<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name> |
<spirit:file> |
<spirit:name>../../xilinx/coregen/scfifo.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
</spirit:file> |
<spirit:file> |
<spirit:name>../../xilinx/coregen/chipscope_vio_trig.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
</spirit:file> |
<spirit:file> |
<spirit:name>../../xilinx/coregen/chipscope_vio_mask.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
</spirit:file> |
<spirit:file> |
<spirit:name>../../xilinx/coregen/chipscope_vio_fifo.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
</spirit:file> |
<spirit:file> |
<spirit:name>../../xilinx/coregen/chipscope_icon.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
</spirit:file> |
<spirit:file> |
<spirit:name>../../xilinx/chipscope_vio_addr_mask.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
</spirit:file> |
<spirit:file> |
<spirit:name>../../xilinx/chipscope_vio_adda_trig.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
</spirit:file> |
<spirit:file> |
<spirit:name>../../xilinx/chipscope_vio_adda_fifo.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
</spirit:file> |
<spirit:file> |
<spirit:name>hdl/vendor.h</spirit:name> |
<spirit:fileType>cSource</spirit:fileType> |
</spirit:file> |
<spirit:file> |
<spirit:name>../../up_monitor.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
</spirit:file> |
<spirit:file> |
<spirit:name>hdl/bustap_jtag_v1_0.v</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType> |
</spirit:file> |
</spirit:fileSet> |
<spirit:fileSet> |
<spirit:name>xilinx_xpgui_view_fileset</spirit:name> |
<spirit:file> |
<spirit:name>xgui/bustap_jtag_v1_0_v1_0.tcl</spirit:name> |
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType> |
<spirit:fileType>tclSource</spirit:fileType> |
<spirit:userFileType>CHECKSUM_593ee5d6</spirit:userFileType> |
</spirit:file> |
</spirit:fileSet> |
<spirit:fileSet> |
<spirit:name>xilinx_utilityxitfiles_view_fileset</spirit:name> |
</spirit:fileSet> |
</spirit:fileSets> |
<spirit:description>bustap_jtag_v1_0</spirit:description> |
<spirit:parameters> |
<spirit:parameter> |
<spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name> |
<spirit:displayName>C S00 Axi Addr Width</spirit:displayName> |
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_ADDR_WIDTH" spirit:order="1100">4</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name> |
<spirit:displayName>C S00 Axi Data Width</spirit:displayName> |
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_DATA_WIDTH" spirit:order="1200">32</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>Component_Name</spirit:name> |
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bustap_jtag_v1_0_v1_0</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>C_M00_AXI_DATA_WIDTH</spirit:name> |
<spirit:displayName>C M00 Axi Data Width</spirit:displayName> |
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M00_AXI_DATA_WIDTH">32</spirit:value> |
</spirit:parameter> |
<spirit:parameter> |
<spirit:name>C_M00_AXI_ADDR_WIDTH</spirit:name> |
<spirit:displayName>C M00 Axi Addr Width</spirit:displayName> |
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M00_AXI_ADDR_WIDTH">4</spirit:value> |
</spirit:parameter> |
</spirit:parameters> |
<spirit:vendorExtensions> |
<xilinx:coreExtensions> |
<xilinx:supportedFamilies> |
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family> |
</xilinx:supportedFamilies> |
<xilinx:taxonomies> |
<xilinx:taxonomy>/Debug_&_Verification</xilinx:taxonomy> |
</xilinx:taxonomies> |
<xilinx:displayName>bustap_jtag_v1_0</xilinx:displayName> |
<xilinx:vendorDisplayName>OpenCores</xilinx:vendorDisplayName> |
<xilinx:vendorURL>http://www.opencores.org</xilinx:vendorURL> |
<xilinx:coreRevision>12</xilinx:coreRevision> |
<xilinx:upgrades> |
<xilinx:canUpgradeFrom>lenovo.com:user:bustap_jtag_v1_0:1.0</xilinx:canUpgradeFrom> |
</xilinx:upgrades> |
<xilinx:coreCreationDateTime>2014-09-23T06:53:29Z</xilinx:coreCreationDateTime> |
<xilinx:tags> |
<xilinx:tag xilinx:name="nopcore"/> |
<xilinx:tag xilinx:name="lenovo.com:user:bustap_jtag_v1_0:1.0_ARCHIVE_LOCATION">../../xilinx/vivado_ip</xilinx:tag> |
<xilinx:tag xilinx:name="OpenCores:user:bustap_jtag_v1_0:1.0_ARCHIVE_LOCATION">D:/work/deviser/vivado_zynq</xilinx:tag> |
</xilinx:tags> |
</xilinx:coreExtensions> |
<xilinx:packagingInfo> |
<xilinx:xilinxVersion>2014.2</xilinx:xilinxVersion> |
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="30cf5bd8"/> |
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="76a91312"/> |
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4a31fdbf"/> |
<xilinx:checksum xilinx:scope="ports" xilinx:value="49fb262f"/> |
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="0d4ae548"/> |
<xilinx:checksum xilinx:scope="parameters" xilinx:value="cb6a4201"/> |
</xilinx:packagingInfo> |
</spirit:vendorExtensions> |
</spirit:component> |
/bustap-jtag/trunk/rtl/xilinx/vivado_ip/hdl/vendor.h
0,0 → 1,2
`define XILINX |
//`define AXI_IP |
/bustap-jtag/trunk/rtl/xilinx/vivado_ip/hdl/bustap_jtag_v1_0.v
0,0 → 1,152
//************************************************************** |
// Module : bustap_jtag_v1_0.v |
// Platform : Ubuntu 14.04 |
// Simulator : Modelsim 6.5b |
// Synthesizer : Vivado 2014.2 |
// Place and Route : Vivado 2014.2 |
// Targets device : Zynq 7000 |
// Author : Bibo Yang (ash_riple@hotmail.com) |
// Organization : www.opencores.org |
// Revision : 2.4 |
// Date : 2014/09/22 |
// Description : axi interface to pipelined access |
// interface converter. axi pass through |
// @Note: AXI-Lite is supported. |
//************************************************************** |
|
`timescale 1ns/1ns |
|
module bustap_jtag_v1_0 # |
( |
parameter integer C_S00_AXI_DATA_WIDTH = 32, |
parameter integer C_S00_AXI_ADDR_WIDTH = 32, |
parameter integer C_M00_AXI_DATA_WIDTH = 32, |
parameter integer C_M00_AXI_ADDR_WIDTH = 32 |
) |
( |
// AXI Slave Interface |
input wire s00_axi_aclk, |
input wire s00_axi_aresetn, |
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr, |
input wire [2 : 0] s00_axi_awprot, |
input wire s00_axi_awvalid, |
output wire s00_axi_awready, |
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata, |
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb, |
input wire s00_axi_wvalid, |
output wire s00_axi_wready, |
output wire [1 : 0] s00_axi_bresp, |
output wire s00_axi_bvalid, |
input wire s00_axi_bready, |
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr, |
input wire [2 : 0] s00_axi_arprot, |
input wire s00_axi_arvalid, |
output wire s00_axi_arready, |
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata, |
output wire [1 : 0] s00_axi_rresp, |
output wire s00_axi_rvalid, |
input wire s00_axi_rready, |
|
// AXI Master Interface |
input wire m00_axi_aclk, |
input wire m00_axi_aresetn, |
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr, |
output wire [2 : 0] m00_axi_awprot, |
output wire m00_axi_awvalid, |
input wire m00_axi_awready, |
output wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_wdata, |
output wire [(C_M00_AXI_DATA_WIDTH/8)-1 : 0] m00_axi_wstrb, |
output wire m00_axi_wvalid, |
input wire m00_axi_wready, |
input wire [1 : 0] m00_axi_bresp, |
input wire m00_axi_bvalid, |
output wire m00_axi_bready, |
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr, |
output wire [2 : 0] m00_axi_arprot, |
output wire m00_axi_arvalid, |
input wire m00_axi_arready, |
input wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata, |
input wire [1 : 0] m00_axi_rresp, |
input wire m00_axi_rvalid, |
output wire m00_axi_rready |
); |
|
// Pass Through |
assign m00_axi_awaddr = s00_axi_awaddr; |
assign m00_axi_awprot = s00_axi_awprot; |
assign m00_axi_awvalid = s00_axi_awvalid; |
assign s00_axi_awready = m00_axi_awready; |
assign m00_axi_wdata = s00_axi_wdata; |
assign m00_axi_wstrb = s00_axi_wstrb; |
assign m00_axi_wvalid = s00_axi_wvalid; |
assign s00_axi_wready = m00_axi_wready; |
assign s00_axi_bresp = m00_axi_bresp; |
assign s00_axi_bvalid = m00_axi_bvalid; |
assign m00_axi_bready = s00_axi_bready; |
assign m00_axi_araddr = s00_axi_araddr; |
assign m00_axi_arprot = s00_axi_arprot; |
assign m00_axi_arvalid = s00_axi_arvalid; |
assign s00_axi_arready = m00_axi_arready; |
assign s00_axi_rdata = m00_axi_rdata; |
assign s00_axi_rresp = m00_axi_rresp; |
assign s00_axi_rvalid = m00_axi_rvalid; |
assign m00_axi_rready = s00_axi_rready; |
|
// latch address and data, does not support simultaneous read and write |
reg [C_S00_AXI_ADDR_WIDTH-1:0] addr_latch; |
always @(posedge s00_axi_aclk) begin |
if (s00_axi_awvalid && s00_axi_awready) |
addr_latch <= s00_axi_awaddr; |
else if (s00_axi_arvalid && s00_axi_arready) |
addr_latch <= s00_axi_araddr; |
else |
addr_latch <= addr_latch; |
end |
|
reg [C_S00_AXI_DATA_WIDTH-1:0] data_latch; |
always @(posedge s00_axi_aclk) begin |
if (s00_axi_wvalid && s00_axi_wready) |
data_latch <= s00_axi_wdata; |
else if (s00_axi_rvalid && s00_axi_rready) |
data_latch <= s00_axi_rdata; |
else |
data_latch <= data_latch; |
end |
|
// generate wr/rd pulse |
reg wr_pulse; |
always @(posedge s00_axi_aclk or negedge s00_axi_aresetn) begin |
if (!s00_axi_aresetn) |
wr_pulse <= 1'b0; |
else if (s00_axi_wvalid && s00_axi_wready) |
wr_pulse <= 1'b1; |
else |
wr_pulse <= 1'b0; |
end |
|
reg rd_pulse; |
always @(posedge s00_axi_aclk or negedge s00_axi_aresetn) begin |
if (!s00_axi_aresetn) |
rd_pulse <= 1'b0; |
else if (s00_axi_rvalid && s00_axi_rready) |
rd_pulse <= 1'b1; |
else |
rd_pulse <= 1'b0; |
end |
|
// map to pipelined access interface |
wire clk = s00_axi_aclk; |
wire wr_en = wr_pulse; |
wire rd_en = rd_pulse; |
wire [31:0] addr_in = addr_latch[31:0]; |
wire [31:0] data_in = data_latch; |
|
up_monitor inst ( |
.clk(clk), |
.wr_en(wr_en), |
.rd_en(rd_en), |
.addr_in(addr_in), |
.data_in(data_in) |
); |
|
endmodule |
/bustap-jtag/trunk/rtl/xilinx/vivado_ip/xgui/bustap_jtag_v1_0_v1_0.tcl
0,0 → 1,67
# Definitional proc to organize widgets for parameters. |
proc init_gui { IPINST } { |
set Page0 [ipgui::add_page $IPINST -name "Page 0" -layout vertical] |
set Component_Name [ipgui::add_param $IPINST -parent $Page0 -name Component_Name] |
set C_M00_AXI_DATA_WIDTH [ipgui::add_param $IPINST -parent $Page0 -name C_M00_AXI_DATA_WIDTH] |
set C_M00_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -parent $Page0 -name C_M00_AXI_ADDR_WIDTH] |
set C_S00_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -parent $Page0 -name C_S00_AXI_ADDR_WIDTH] |
set C_S00_AXI_DATA_WIDTH [ipgui::add_param $IPINST -parent $Page0 -name C_S00_AXI_DATA_WIDTH] |
} |
|
proc update_PARAM_VALUE.C_M00_AXI_DATA_WIDTH { PARAM_VALUE.C_M00_AXI_DATA_WIDTH } { |
# Procedure called to update C_M00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change |
} |
|
proc validate_PARAM_VALUE.C_M00_AXI_DATA_WIDTH { PARAM_VALUE.C_M00_AXI_DATA_WIDTH } { |
# Procedure called to validate C_M00_AXI_DATA_WIDTH |
return true |
} |
|
proc update_PARAM_VALUE.C_M00_AXI_ADDR_WIDTH { PARAM_VALUE.C_M00_AXI_ADDR_WIDTH } { |
# Procedure called to update C_M00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change |
} |
|
proc validate_PARAM_VALUE.C_M00_AXI_ADDR_WIDTH { PARAM_VALUE.C_M00_AXI_ADDR_WIDTH } { |
# Procedure called to validate C_M00_AXI_ADDR_WIDTH |
return true |
} |
|
proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { |
# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change |
} |
|
proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { |
# Procedure called to validate C_S00_AXI_ADDR_WIDTH |
return true |
} |
|
proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { |
# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change |
} |
|
proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { |
# Procedure called to validate C_S00_AXI_DATA_WIDTH |
return true |
} |
|
|
proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { |
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value |
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH} |
} |
|
proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { |
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value |
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH} |
} |
|
proc update_MODELPARAM_VALUE.C_M00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_M00_AXI_DATA_WIDTH PARAM_VALUE.C_M00_AXI_DATA_WIDTH } { |
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value |
set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_DATA_WIDTH} |
} |
|
proc update_MODELPARAM_VALUE.C_M00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_M00_AXI_ADDR_WIDTH PARAM_VALUE.C_M00_AXI_ADDR_WIDTH } { |
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value |
set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_ADDR_WIDTH} |
} |
|
/bustap-jtag/trunk/cmd/xilinx/chipscope_vio_console.bat
1,3 → 1,4
echo %XILINX% |
set path=%XILINX%\lib\nt;%XILINX%\bin\nt;%path% |
wish chipscope_vio_console.tcl |
pause |