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URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

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Rev 1 → Rev 2

/rtl/up_monitor.v
0,0 → 1,113
 
module up_monitor (up_clk,up_wbe,up_csn,up_addr,up_data_io);
 
input up_clk,up_wbe,up_csn;
input [15:2] up_addr;
input [31:0] up_data_io;
 
reg up_csn_d1, up_csn_d2, up_csn_d3, up_csn_d4;
wire up_csn_neg_pulse;
wire [47:0] up_bus_content;
 
wire [49:0] trig_condition;
wire trig_en = trig_condition[49];
wire trig_set = trig_condition[48];
wire [15:0] trig_addr = trig_condition[47:32];
wire [31:0] trig_data = trig_condition[31:0];
reg trig_condition_ok;
 
wire [31:0] addr_mask0,addr_mask1,addr_mask2,addr_mask3,addr_mask4,addr_mask5,addr_mask6,addr_mask7,
addr_mask8,addr_mask9,addr_mask10,addr_mask11,addr_mask12,addr_mask13,addr_mask14,addr_mask15;
reg addr_mask_ok;
 
always @(posedge up_clk)
begin
up_csn_d1 <= up_csn || up_wbe;
up_csn_d2 <= up_csn_d1;
up_csn_d3 <= up_csn_d2;
up_csn_d4 <= up_csn_d3;
end
 
always @(posedge up_clk)
begin
if (( (up_addr[15:2]<=addr_mask0[31:18] && up_addr[15:2]>=addr_mask0[15:2]) ||
(up_addr[15:2]<=addr_mask1[31:18] && up_addr[15:2]>=addr_mask1[15:2]) ||
(up_addr[15:2]<=addr_mask2[31:18] && up_addr[15:2]>=addr_mask2[15:2]) ||
(up_addr[15:2]<=addr_mask3[31:18] && up_addr[15:2]>=addr_mask3[15:2]) ||
(up_addr[15:2]<=addr_mask4[31:18] && up_addr[15:2]>=addr_mask4[15:2]) ||
(up_addr[15:2]<=addr_mask5[31:18] && up_addr[15:2]>=addr_mask5[15:2]) ||
(up_addr[15:2]<=addr_mask6[31:18] && up_addr[15:2]>=addr_mask6[15:2]) ||
(up_addr[15:2]<=addr_mask7[31:18] && up_addr[15:2]>=addr_mask7[15:2])
) //inclusive address set
&&
( (up_addr[15:2]>addr_mask8 [31:18] || up_addr[15:2]<addr_mask8 [15:2]) &&
(up_addr[15:2]>addr_mask9 [31:18] || up_addr[15:2]<addr_mask9 [15:2]) &&
(up_addr[15:2]>addr_mask10[31:18] || up_addr[15:2]<addr_mask10[15:2]) &&
(up_addr[15:2]>addr_mask11[31:18] || up_addr[15:2]<addr_mask11[15:2]) &&
(up_addr[15:2]>addr_mask12[31:18] || up_addr[15:2]<addr_mask12[15:2]) &&
(up_addr[15:2]>addr_mask13[31:18] || up_addr[15:2]<addr_mask13[15:2]) &&
(up_addr[15:2]>addr_mask14[31:18] || up_addr[15:2]<addr_mask14[15:2]) &&
(up_addr[15:2]>addr_mask15[31:18] || up_addr[15:2]<addr_mask15[15:2])
) //exclusive address set
)
addr_mask_ok <= 1;
else
addr_mask_ok <= 0;
end
 
always @(posedge up_clk)
begin
if (trig_en==0)
trig_condition_ok <= 1;
else if (trig_set==0)
trig_condition_ok <= 0;
else if (up_csn_d1==0 && up_csn_d2==1)
if (trig_addr[15:2]==up_addr[15:2] && trig_data==up_data_io)
trig_condition_ok <= 1;
end
 
assign up_csn_neg_pulse = !up_csn_d3 && up_csn_d4 && addr_mask_ok && trig_condition_ok;
assign up_bus_content = {up_addr[15:2],2'b0,up_data_io[31:0]};
 
virtual_jtag_adda_fifo u_virtual_jtag_adda_fifo (
.clk(up_clk),
.wr_en(up_csn_neg_pulse),
.data_in(up_bus_content)
);
defparam
u_virtual_jtag_adda_fifo.data_width = 48,
u_virtual_jtag_adda_fifo.fifo_depth = 512,
u_virtual_jtag_adda_fifo.addr_width = 9,
u_virtual_jtag_adda_fifo.al_full_val = 511,
u_virtual_jtag_adda_fifo.al_empt_val = 0;
 
virtual_jtag_addr_mask u_virtual_jtag_addr_mask (
.mask_out0(addr_mask0),
.mask_out1(addr_mask1),
.mask_out2(addr_mask2),
.mask_out3(addr_mask3),
.mask_out4(addr_mask4),
.mask_out5(addr_mask5),
.mask_out6(addr_mask6),
.mask_out7(addr_mask7),
.mask_out8(addr_mask8),
.mask_out9(addr_mask9),
.mask_out10(addr_mask10),
.mask_out11(addr_mask11),
.mask_out12(addr_mask12),
.mask_out13(addr_mask13),
.mask_out14(addr_mask14),
.mask_out15(addr_mask15)
);
defparam
u_virtual_jtag_addr_mask.addr_width = 32,
u_virtual_jtag_addr_mask.mask_index = 4,
u_virtual_jtag_addr_mask.mask_num = 16;
 
virtual_jtag_adda_trig u_virtual_jtag_adda_trig (
.trig_out(trig_condition)
);
defparam
u_virtual_jtag_adda_trig.trig_width = 50;
 
endmodule
/rtl/altera/virtual_jtag_addr_mask.v
0,0 → 1,154
module virtual_jtag_addr_mask(mask_out0,mask_out1,mask_out2,mask_out3,
mask_out4,mask_out5,mask_out6,mask_out7,
mask_out8,mask_out9,mask_out10,mask_out11,
mask_out12,mask_out13,mask_out14,mask_out15
);
 
parameter addr_width = 32,
mask_index = 4, //2**mask_index=mask_num
mask_num = 16;
 
output [addr_width-1:0] mask_out0;
output [addr_width-1:0] mask_out1;
output [addr_width-1:0] mask_out2;
output [addr_width-1:0] mask_out3;
output [addr_width-1:0] mask_out4;
output [addr_width-1:0] mask_out5;
output [addr_width-1:0] mask_out6;
output [addr_width-1:0] mask_out7;
output [addr_width-1:0] mask_out8;
output [addr_width-1:0] mask_out9;
output [addr_width-1:0] mask_out10;
output [addr_width-1:0] mask_out11;
output [addr_width-1:0] mask_out12;
output [addr_width-1:0] mask_out13;
output [addr_width-1:0] mask_out14;
output [addr_width-1:0] mask_out15;
 
reg [addr_width-1:0] mask_out0;
reg [addr_width-1:0] mask_out1;
reg [addr_width-1:0] mask_out2;
reg [addr_width-1:0] mask_out3;
reg [addr_width-1:0] mask_out4;
reg [addr_width-1:0] mask_out5;
reg [addr_width-1:0] mask_out6;
reg [addr_width-1:0] mask_out7;
reg [addr_width-1:0] mask_out8;
reg [addr_width-1:0] mask_out9;
reg [addr_width-1:0] mask_out10;
reg [addr_width-1:0] mask_out11;
reg [addr_width-1:0] mask_out12;
reg [addr_width-1:0] mask_out13;
reg [addr_width-1:0] mask_out14;
reg [addr_width-1:0] mask_out15;
 
wire tdi, tck, cdr, cir, e1dr, e2dr, pdr, sdr, udr, uir;
reg tdo;
reg [mask_index+addr_width-1:0] mask_instr_reg;
reg bypass_reg;
 
wire [1:0] ir_in;
wire mask_instr = ~ir_in[1] & ir_in[0]; // 1
 
wire [mask_index-1:0] mask_id = mask_instr_reg[(mask_index+addr_width-1):addr_width];
wire [addr_width-1:0] mask_is = mask_instr_reg[(addr_width-1):0];
 
always @(posedge tck)
begin
if (mask_instr && e1dr)
case (mask_id)
4'd0 :
mask_out0 <= mask_is;
4'd1 :
mask_out1 <= mask_is;
4'd2 :
mask_out2 <= mask_is;
4'd3 :
mask_out3 <= mask_is;
4'd4 :
mask_out4 <= mask_is;
4'd5 :
mask_out5 <= mask_is;
4'd6 :
mask_out6 <= mask_is;
4'd7 :
mask_out7 <= mask_is;
4'd8 :
mask_out8 <= mask_is;
4'd9 :
mask_out9 <= mask_is;
4'd10 :
mask_out10 <= mask_is;
4'd11 :
mask_out11 <= mask_is;
4'd12 :
mask_out12 <= mask_is;
4'd13 :
mask_out13 <= mask_is;
4'd14 :
mask_out14 <= mask_is;
4'd15 :
mask_out15 <= mask_is;
endcase
end
 
/* mask_instr Instruction Handler */
always @ (posedge tck)
if ( mask_instr && cdr )
mask_instr_reg <= mask_instr_reg;
else if ( mask_instr && sdr )
mask_instr_reg <= {tdi, mask_instr_reg[mask_index+addr_width-1:1]};
 
/* Bypass register */
always @ (posedge tck)
bypass_reg = tdi;
 
/* Node TDO Output */
always @ ( mask_instr, mask_instr_reg, bypass_reg )
begin
if (mask_instr)
tdo <= mask_instr_reg[0];
else
tdo <= bypass_reg;// Used to maintain the continuity of the scan chain.
end
 
sld_virtual_jtag sld_virtual_jtag_component (
.ir_in (ir_in),
.ir_out (2'b0),
.tdo (tdo),
.tdi (tdi),
.tms (),
.tck (tck),
.virtual_state_cir (cir),
.virtual_state_pdr (pdr),
.virtual_state_uir (uir),
.virtual_state_sdr (sdr),
.virtual_state_cdr (cdr),
.virtual_state_udr (udr),
.virtual_state_e1dr (e1dr),
.virtual_state_e2dr (e2dr),
.jtag_state_rti (),
.jtag_state_e1dr (),
.jtag_state_e2dr (),
.jtag_state_pir (),
.jtag_state_tlr (),
.jtag_state_sir (),
.jtag_state_cir (),
.jtag_state_uir (),
.jtag_state_pdr (),
.jtag_state_sdrs (),
.jtag_state_sdr (),
.jtag_state_cdr (),
.jtag_state_udr (),
.jtag_state_sirs (),
.jtag_state_e1ir (),
.jtag_state_e2ir ());
defparam
sld_virtual_jtag_component.sld_auto_instance_index = "NO",
sld_virtual_jtag_component.sld_instance_index = 1,
sld_virtual_jtag_component.sld_ir_width = 2,
sld_virtual_jtag_component.sld_sim_action = "((1,1,1,2))",
sld_virtual_jtag_component.sld_sim_n_scan = 1,
sld_virtual_jtag_component.sld_sim_total_length = 2;
endmodule
/rtl/altera/virtual_jtag_adda_fifo.v
0,0 → 1,155
module virtual_jtag_adda_fifo(clk,wr_en,data_in);
 
parameter data_width = 32,
fifo_depth = 256,
addr_width = 8,
al_full_val = 255,
al_empt_val = 0;
 
input clk;
input wr_en;
input [data_width-1:0] data_in;
 
wire tdi, tck, cdr, cir, e1dr, e2dr, pdr, sdr, udr, uir;
reg tdo;
reg [addr_width-1:0] usedw_instr_reg;
reg reset_instr_reg;
reg [data_width-1:0] read_instr_reg;
reg bypass_reg;
 
wire [1:0] ir_in;
wire usedw_instr = ~ir_in[1] & ir_in[0]; // 1
wire reset_instr = ir_in[1] & ~ir_in[0]; // 2
wire read_instr = ir_in[1] & ir_in[0]; // 3
 
wire reset = reset_instr && e1dr;
 
wire [addr_width-1:0] usedw;
wire [data_width-1:0] data_out;
wire full;
wire al_full;
 
reg read_instr_d1;
reg read_instr_d2;
reg read_instr_d3;
wire rd_en = read_instr_d2 & !read_instr_d3;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
read_instr_d1 <= 1'b0;
read_instr_d2 <= 1'b0;
read_instr_d3 <= 1'b0;
end
else
begin
read_instr_d1 <= read_instr;
read_instr_d2 <= read_instr_d1;
read_instr_d3 <= read_instr_d2;
end
end
 
scfifo jtag_fifo (
.aclr (reset),
.clock (clk),
.wrreq (wr_en & !al_full),
.data (data_in),
.rdreq (rd_en),
.q (data_out),
.full (full),
.almost_full (al_full),
.empty (),
.almost_empty (),
.usedw (usedw),
.sclr ());
defparam
jtag_fifo.lpm_width = data_width,
jtag_fifo.lpm_numwords = fifo_depth,
jtag_fifo.lpm_widthu = addr_width,
jtag_fifo.intended_device_family = "Stratix II",
jtag_fifo.almost_full_value = al_full_val,
jtag_fifo.almost_empty_value = al_empt_val,
jtag_fifo.lpm_type = "scfifo",
jtag_fifo.lpm_showahead = "OFF",
jtag_fifo.overflow_checking = "ON",
jtag_fifo.underflow_checking = "ON",
jtag_fifo.use_eab = "ON",
jtag_fifo.add_ram_output_register = "ON";
 
/* usedw_instr Instruction Handler */
always @ (posedge tck)
if ( usedw_instr && cdr )
usedw_instr_reg <= usedw;
else if ( usedw_instr && sdr )
usedw_instr_reg <= {tdi, usedw_instr_reg[addr_width-1:1]};
 
/* reset_instr Instruction Handler */
always @ (posedge tck)
if ( reset_instr && sdr )
reset_instr_reg <= tdi;//{tdi, reset_instr_reg[data_width-1:1]};
 
/* read_instr Instruction Handler */
always @ (posedge tck)
if ( read_instr && cdr )
read_instr_reg <= data_out;
else if ( read_instr && sdr )
read_instr_reg <= {tdi, read_instr_reg[data_width-1:1]};
 
/* Bypass register */
always @ (posedge tck)
bypass_reg = tdi;
 
/* Node TDO Output */
always @ ( usedw_instr, reset_instr, read_instr, usedw_instr_reg[0], reset_instr_reg/*[0]*/, read_instr_reg[0], bypass_reg )
begin
if (usedw_instr)
tdo <= usedw_instr_reg[0];
else if (reset_instr)
tdo <= reset_instr_reg/*[0]*/;
else if (read_instr)
tdo <= read_instr_reg[0];
else
tdo <= bypass_reg; // Used to maintain the continuity of the scan chain.
end
 
sld_virtual_jtag sld_virtual_jtag_component (
.ir_in (ir_in),
.ir_out (2'b0),
.tdo (tdo),
.tdi (tdi),
.tms (),
.tck (tck),
.virtual_state_cir (cir),
.virtual_state_pdr (pdr),
.virtual_state_uir (uir),
.virtual_state_sdr (sdr),
.virtual_state_cdr (cdr),
.virtual_state_udr (udr),
.virtual_state_e1dr (e1dr),
.virtual_state_e2dr (e2dr),
.jtag_state_rti (),
.jtag_state_e1dr (),
.jtag_state_e2dr (),
.jtag_state_pir (),
.jtag_state_tlr (),
.jtag_state_sir (),
.jtag_state_cir (),
.jtag_state_uir (),
.jtag_state_pdr (),
.jtag_state_sdrs (),
.jtag_state_sdr (),
.jtag_state_cdr (),
.jtag_state_udr (),
.jtag_state_sirs (),
.jtag_state_e1ir (),
.jtag_state_e2ir ());
defparam
sld_virtual_jtag_component.sld_auto_instance_index = "NO",
sld_virtual_jtag_component.sld_instance_index = 0,
sld_virtual_jtag_component.sld_ir_width = 2,
sld_virtual_jtag_component.sld_sim_action = "((1,1,1,2))",
sld_virtual_jtag_component.sld_sim_n_scan = 1,
sld_virtual_jtag_component.sld_sim_total_length = 2;
endmodule
/rtl/altera/virtual_jtag_adda_trig.v
0,0 → 1,82
module virtual_jtag_adda_trig(trig_out);
 
parameter trig_width = 32;
 
output [trig_width-1:0] trig_out;
 
reg [trig_width-1:0] trig_out;
 
wire tdi, tck, cdr, cir, e1dr, e2dr, pdr, sdr, udr, uir;
reg tdo;
reg [trig_width-1:0] trig_instr_reg;
reg bypass_reg;
 
wire [1:0] ir_in;
wire trig_instr = ~ir_in[1] & ir_in[0]; // 1
 
always @(posedge tck)
begin
if (trig_instr && e1dr)
trig_out <= trig_instr_reg;
end
 
/* trig_instr Instruction Handler */
always @ (posedge tck)
if ( trig_instr && cdr )
trig_instr_reg <= trig_instr_reg;
else if ( trig_instr && sdr )
trig_instr_reg <= {tdi, trig_instr_reg[trig_width-1:1]};
 
/* Bypass register */
always @ (posedge tck)
bypass_reg <= tdi;
 
/* Node TDO Output */
always @ ( trig_instr, trig_instr_reg, bypass_reg )
begin
if (trig_instr)
tdo <= trig_instr_reg[0];
else
tdo <= bypass_reg;// Used to maintain the continuity of the scan chain.
end
 
sld_virtual_jtag sld_virtual_jtag_component (
.ir_in (ir_in),
.ir_out (2'b0),
.tdo (tdo),
.tdi (tdi),
.tms (),
.tck (tck),
.virtual_state_cir (cir),
.virtual_state_pdr (pdr),
.virtual_state_uir (uir),
.virtual_state_sdr (sdr),
.virtual_state_cdr (cdr),
.virtual_state_udr (udr),
.virtual_state_e1dr (e1dr),
.virtual_state_e2dr (e2dr),
.jtag_state_rti (),
.jtag_state_e1dr (),
.jtag_state_e2dr (),
.jtag_state_pir (),
.jtag_state_tlr (),
.jtag_state_sir (),
.jtag_state_cir (),
.jtag_state_uir (),
.jtag_state_pdr (),
.jtag_state_sdrs (),
.jtag_state_sdr (),
.jtag_state_cdr (),
.jtag_state_udr (),
.jtag_state_sirs (),
.jtag_state_e1ir (),
.jtag_state_e2ir ());
defparam
sld_virtual_jtag_component.sld_auto_instance_index = "NO",
sld_virtual_jtag_component.sld_instance_index = 2,
sld_virtual_jtag_component.sld_ir_width = 2,
sld_virtual_jtag_component.sld_sim_action = "((1,1,1,2))",
sld_virtual_jtag_component.sld_sim_n_scan = 1,
sld_virtual_jtag_component.sld_sim_total_length = 2;
endmodule
/rtl/up_monitor.vhd
0,0 → 1,198
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity up_monitor is
port (
up_clk : in std_logic;
up_wbe : in std_logic;
up_csn : in std_logic;
up_addr : in std_logic_vector(15 downto 2);
up_data_io : in std_logic_vector(31 downto 0)
);
end up_monitor;
 
architecture synth of up_monitor is
 
component virtual_jtag_adda_fifo is
generic(
data_width : integer;
fifo_depth : integer;
addr_width : integer;
al_full_val : integer;
al_empt_val : integer
);
port(
clk : in std_logic;
wr_en : in std_logic;
data_in : in std_logic_vector(data_width-1 downto 0)
);
end component virtual_jtag_adda_fifo;
 
signal up_csn_d1, up_csn_d2, up_csn_d3, up_csn_d4 : std_logic;
signal up_csn_neg_pulse : std_logic;
signal up_bus_content : std_logic_vector(47 downto 0);
 
type addr_array is array (15 downto 0) of std_logic_vector (31 downto 0);
 
component virtual_jtag_addr_mask is
generic(
addr_width : integer;
mask_index : integer;
mask_num : integer
);
port(
mask_out0 : out std_logic_vector (31 downto 0);
mask_out1 : out std_logic_vector (31 downto 0);
mask_out2 : out std_logic_vector (31 downto 0);
mask_out3 : out std_logic_vector (31 downto 0);
mask_out4 : out std_logic_vector (31 downto 0);
mask_out5 : out std_logic_vector (31 downto 0);
mask_out6 : out std_logic_vector (31 downto 0);
mask_out7 : out std_logic_vector (31 downto 0);
mask_out8 : out std_logic_vector (31 downto 0);
mask_out9 : out std_logic_vector (31 downto 0);
mask_out10 : out std_logic_vector (31 downto 0);
mask_out11 : out std_logic_vector (31 downto 0);
mask_out12 : out std_logic_vector (31 downto 0);
mask_out13 : out std_logic_vector (31 downto 0);
mask_out14 : out std_logic_vector (31 downto 0);
mask_out15 : out std_logic_vector (31 downto 0)
);
end component virtual_jtag_addr_mask;
 
signal addr_mask : addr_array;
signal addr_mask_ok : std_logic;
 
component virtual_jtag_adda_trig is
generic(
trig_width : integer
);
port(
trig_out : out std_logic_vector(trig_width-1 downto 0)
);
end component virtual_jtag_adda_trig;
 
signal trig_condition : std_logic_vector(49 downto 0);
alias trig_en : std_logic is trig_condition(49);
alias trig_set : std_logic is trig_condition(48);
alias trig_addr : std_logic_vector(15 downto 0) is trig_condition(47 downto 32);
alias trig_data : std_logic_vector(31 downto 0) is trig_condition(31 downto 0);
signal trig_condition_ok : std_logic;
 
begin
 
process (up_clk)
begin
if (up_clk'event and up_clk='1') then
up_csn_d1 <= up_csn or up_wbe;
up_csn_d2 <= up_csn_d1;
up_csn_d3 <= up_csn_d2;
up_csn_d4 <= up_csn_d3;
end if;
end process;
 
 
process (up_clk)
begin
if (up_clk'event and up_clk='1') then
if (( (up_addr(15 downto 2)<=addr_mask(0)(31 downto 18) and up_addr(15 downto 2)>=addr_mask(0)(15 downto 2)) or
(up_addr(15 downto 2)<=addr_mask(1)(31 downto 18) and up_addr(15 downto 2)>=addr_mask(1)(15 downto 2)) or
(up_addr(15 downto 2)<=addr_mask(2)(31 downto 18) and up_addr(15 downto 2)>=addr_mask(2)(15 downto 2)) or
(up_addr(15 downto 2)<=addr_mask(3)(31 downto 18) and up_addr(15 downto 2)>=addr_mask(3)(15 downto 2)) or
(up_addr(15 downto 2)<=addr_mask(4)(31 downto 18) and up_addr(15 downto 2)>=addr_mask(4)(15 downto 2)) or
(up_addr(15 downto 2)<=addr_mask(5)(31 downto 18) and up_addr(15 downto 2)>=addr_mask(5)(15 downto 2)) or
(up_addr(15 downto 2)<=addr_mask(6)(31 downto 18) and up_addr(15 downto 2)>=addr_mask(6)(15 downto 2)) or
(up_addr(15 downto 2)<=addr_mask(7)(31 downto 18) and up_addr(15 downto 2)>=addr_mask(7)(15 downto 2))
) --inclusive address set
and
( (up_addr(15 downto 2)>addr_mask(8) (31 downto 18) or up_addr(15 downto 2)<addr_mask(8) (15 downto 2)) and
(up_addr(15 downto 2)>addr_mask(9) (31 downto 18) or up_addr(15 downto 2)<addr_mask(9) (15 downto 2)) and
(up_addr(15 downto 2)>addr_mask(10)(31 downto 18) or up_addr(15 downto 2)<addr_mask(10)(15 downto 2)) and
(up_addr(15 downto 2)>addr_mask(11)(31 downto 18) or up_addr(15 downto 2)<addr_mask(11)(15 downto 2)) and
(up_addr(15 downto 2)>addr_mask(12)(31 downto 18) or up_addr(15 downto 2)<addr_mask(12)(15 downto 2)) and
(up_addr(15 downto 2)>addr_mask(13)(31 downto 18) or up_addr(15 downto 2)<addr_mask(13)(15 downto 2)) and
(up_addr(15 downto 2)>addr_mask(14)(31 downto 18) or up_addr(15 downto 2)<addr_mask(14)(15 downto 2)) and
(up_addr(15 downto 2)>addr_mask(15)(31 downto 18) or up_addr(15 downto 2)<addr_mask(15)(15 downto 2))
) --exclusive address set
) then
addr_mask_ok <= '1';
else
addr_mask_ok <= '0';
end if;
end if;
end process;
 
process (up_clk)
begin
if (up_clk'event and up_clk='1') then
if (trig_en='0') then
trig_condition_ok <= '1';
elsif (trig_set='0') then
trig_condition_ok <= '0';
elsif (up_csn_d1='0' and up_csn_d2='1') then
if (trig_addr(15 downto 2)=up_addr(15 downto 2) and trig_data=up_data_io) then
trig_condition_ok <= '1';
end if;
end if;
end if;
end process;
 
up_csn_neg_pulse <= (not up_csn_d3) and up_csn_d4 and addr_mask_ok and trig_condition_ok;
up_bus_content <= up_addr(15 downto 2) & "00" & up_data_io(31 downto 0);
 
u_virtual_jtag_adda_fifo : virtual_jtag_adda_fifo
generic map
(
data_width => 48,
fifo_depth => 512,
addr_width => 9,
al_full_val => 511,
al_empt_val => 0
)
port map
(
clk => up_clk,
wr_en => up_csn_neg_pulse,
data_in => up_bus_content
);
 
u_virtual_jtag_addr_mask : virtual_jtag_addr_mask
generic map
(
addr_width => 32,
mask_index => 4,
mask_num => 16
)
port map
(
mask_out0 => addr_mask(0),
mask_out1 => addr_mask(1),
mask_out2 => addr_mask(2),
mask_out3 => addr_mask(3),
mask_out4 => addr_mask(4),
mask_out5 => addr_mask(5),
mask_out6 => addr_mask(6),
mask_out7 => addr_mask(7),
mask_out8 => addr_mask(8),
mask_out9 => addr_mask(9),
mask_out10 => addr_mask(10),
mask_out11 => addr_mask(11),
mask_out12 => addr_mask(12),
mask_out13 => addr_mask(13),
mask_out14 => addr_mask(14),
mask_out15 => addr_mask(15)
);
 
u_virtual_jtag_adda_trig : virtual_jtag_adda_trig
generic map
(
trig_width => 50
)
port map
(
trig_out => trig_condition
);
 
end synth;
/par/altera/up_monitor.qpf
0,0 → 1,23
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
 
 
 
QUARTUS_VERSION = "6.1"
DATE = "18:33:38 June 01, 2009"
 
 
# Revisions
 
PROJECT_REVISION = "up_monitor"
/par/altera/up_monitor.qsf
0,0 → 1,45
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
 
 
# The default values for assignments are stored in the file
# up_monitor_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
# assignment_defaults.qdf
 
# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
 
 
set_global_assignment -name DEVICE Auto
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name TOP_LEVEL_ENTITY up_monitor
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:33:38 JUNE 01, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION "10.1 SP1"
set_global_assignment -name ENABLE_ADVANCED_IO_TIMING OFF
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output
 
set_global_assignment -name VHDL_FILE ../../rtl/up_monitor.vhd
#set_global_assignment -name VERILOG_FILE ../../rtl/up_monitor.v
set_global_assignment -name VERILOG_FILE ../../rtl/altera/virtual_jtag_addr_mask.v
set_global_assignment -name VERILOG_FILE ../../rtl/altera/virtual_jtag_adda_fifo.v
set_global_assignment -name VERILOG_FILE ../../rtl/altera/virtual_jtag_adda_trig.v
 
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
/cmd/altera/virtual_jtag_console.bat
0,0 → 1,2
quartus_stp -t virtual_jtag_console.tcl
pause
/cmd/altera/virtual_jtag_console.tcl
0,0 → 1,332
proc reset_fifo {{jtag_index_0 0}} {
device_lock -timeout 10000
device_virtual_ir_shift -instance_index $jtag_index_0 -ir_value 2 -no_captured_ir_value
device_virtual_dr_shift -instance_index $jtag_index_0 -length 32 -dr_value 00000000 -value_in_hex -no_captured_dr_value
device_unlock
return 0
}
 
proc query_usedw {{jtag_index_0 0}} {
global fifoUsedw
device_lock -timeout 10000
device_virtual_ir_shift -instance_index $jtag_index_0 -ir_value 1 -no_captured_ir_value
set usedw [device_virtual_dr_shift -instance_index $jtag_index_0 -length 9 -value_in_hex]
device_unlock
set tmp 0x
append tmp $usedw
set usedw [format "%i" $tmp]
set fifoUsedw $usedw
return $usedw
}
 
proc read_fifo {{jtag_index_0 0}} {
device_lock -timeout 10000
device_virtual_ir_shift -instance_index $jtag_index_0 -ir_value 1 -no_captured_ir_value
device_virtual_ir_shift -instance_index $jtag_index_0 -ir_value 3 -no_captured_ir_value
set fifo_data [device_virtual_dr_shift -instance_index $jtag_index_0 -length 48 -value_in_hex]
device_unlock
return $fifo_data
}
 
proc config_addr {{jtag_index_1 1} {mask_1 100000000}} {
device_lock -timeout 10000
device_virtual_ir_shift -instance_index $jtag_index_1 -ir_value 1 -no_captured_ir_value
set addr_mask [device_virtual_dr_shift -instance_index $jtag_index_1 -dr_value $mask_1 -length 36 -value_in_hex]
device_unlock
return $addr_mask
}
 
proc config_trig {{jtag_index_2 2} {trig_1 0000000000000}} {
device_lock -timeout 10000
device_virtual_ir_shift -instance_index $jtag_index_2 -ir_value 1 -no_captured_ir_value
set addr_trig [device_virtual_dr_shift -instance_index $jtag_index_2 -dr_value $trig_1 -length 50 -value_in_hex]
device_unlock
return $addr_trig
}
 
proc open_jtag_device {{test_cable "USB-Blaster [USB-0]"} {test_device "@2: EP2SGX90 (0x020E30DD)"}} {
open_device -hardware_name $test_cable -device_name $test_device
# Retrieve device id code.
device_lock -timeout 10000
device_ir_shift -ir_value 6 -no_captured_ir_value
set idcode "0x[device_dr_shift -length 32 -value_in_hex]"
device_unlock
return $idcode
}
 
proc close_jtag_device {} {
close_device
}
 
proc scan_chain {} {
global log
$log insert end "JTAG Chain Scanning report:\n"
$log insert end "****************************************\n"
set blaster_cables [get_hardware_names]
set cable_num 0
foreach blaster_cable $blaster_cables {
incr cable_num
$log insert end "@$cable_num: $blaster_cable\n"
}
$log insert end "\n****************************************\n"
global device_list
set device_list ""
foreach blaster_cable $blaster_cables {
$log insert end "$blaster_cable:\n"
lappend device_list $blaster_cable
if [catch {get_device_names -hardware_name $blaster_cable} error_msg] {
$log insert end $error_msg
lappend device_list $error_msg
} else {
foreach test_device [get_device_names -hardware_name $blaster_cable] {
$log insert end "$test_device\n"
}
lappend device_list [get_device_names -hardware_name $blaster_cable]
}
}
}
 
proc select_device {{cableNum 1} {deviceNum 1}} {
global log
global device_list
$log insert end "\n****************************************\n"
set test_cable [lindex $device_list [expr 2*$cableNum-2]]
$log insert end "Selected Cable : $test_cable\n"
set test_device [lindex [lindex $device_list [expr 2*$cableNum-1]] [expr $deviceNum-1]]
$log insert end "Selected Device: $test_device\n"
set jtagIdCode [open_jtag_device $test_cable $test_device]
$log insert end "Device ID code : $jtagIdCode\n"
updateAddrConfig
reset_fifo 0
query_usedw 0
}
 
proc inclusiveAddrConfig {} {
global address_span1
global address_span2
global address_span3
global address_span4
global address_span5
global address_span6
global address_span7
global address_span8
for {set i 1} {$i<=8} {incr i} {
set mask [format "%1X" [expr $i-1]]
append mask [set address_span$i]
config_addr 1 $mask
}
}
 
proc exclusiveAddrConfig {} {
global address_span9
global address_span10
global address_span11
global address_span12
global address_span13
global address_span14
global address_span15
global address_span16
for {set i 9} {$i<=16} {incr i} {
set mask [format "%1X" [expr $i-1]]
append mask [set address_span$i]
config_addr 1 $mask
}
}
 
proc updateAddrConfig {} {
global log
global address_span1
global address_span2
global address_span3
global address_span4
global address_span5
global address_span6
global address_span7
global address_span8
global address_span9
global address_span10
global address_span11
global address_span12
global address_span13
global address_span14
global address_span15
global address_span16
for {set i 1} {$i<=8} {incr i} {
set address_span$i ffff0000
}
for {set i 9} {$i<=16} {incr i} {
set address_span$i 00000000
}
}
 
proc enableTrigger {} {
global triggerAddr
global triggerData
# enable but stop triggering
set triggerValue 2
append triggerValue $triggerAddr
append triggerValue $triggerData
config_trig 2 $triggerValue
}
 
proc disableTrigger {} {
global triggerAddr
global triggerData
# disable and stop triggering
set triggerValue 0
append triggerValue $triggerAddr
append triggerValue $triggerData
config_trig 2 $triggerValue
}
 
proc startTrigger {} {
global triggerAddr
global triggerData
# enable and start triggering
set triggerValue 3
append triggerValue $triggerAddr
append triggerValue $triggerData
config_trig 2 $triggerValue
}
 
proc stopTrigger {} {
global triggerAddr
global triggerData
# enable and stop triggering
set triggerValue 2
append triggerValue $triggerAddr
append triggerValue $triggerData
config_trig 2 $triggerValue
}
 
proc reset_fifo_ptr {} {
reset_fifo 0
query_usedw 0
}
 
proc query_fifo_usedw {} {
query_usedw 0
}
 
proc read_fifo_content {} {
global log
global fifoUsedw
$log insert end "\n****************************************\n"
for {set i 0} {$i<$fifoUsedw} {incr i} {
set fifoContent [read_fifo 0]
$log insert end "wr [string range $fifoContent 0 3] [string range $fifoContent 4 11]\n"
}
query_usedw 0
}
 
proc clear_log {} {
global log
$log delete insert end
}
 
proc quit {} {
global exit_console
destroy .console
set exit_console 1
}
 
# set the QuartusII special Tk command
init_tk
set exit_console 0
 
# set the main window
toplevel .console
wm title .console "Virtual JTAG: uP transaction monitor"
pack propagate .console true
 
# set the JTAG utility
frame .console.fig -bg white
pack .console.fig -expand true -fill both
 
button .console.fig.scan -text {Scan JTAG Chain} -command {scan_chain}
button .console.fig.select -text {Select JTAG Device :} -command {select_device $cableNum $deviceNum}
button .console.fig.deselect -text {DeSelect JTAG Device} -command {close_jtag_device}
label .console.fig.cable -text {Cable No.}
label .console.fig.devic -text {Device No.}
entry .console.fig.cable_num -textvariable cableNum -width 2
entry .console.fig.devic_num -textvariable deviceNum -width 2
pack .console.fig.scan .console.fig.select \
.console.fig.cable .console.fig.cable_num \
.console.fig.devic .console.fig.devic_num \
.console.fig.deselect \
-side left -ipadx 10
 
# set the inclusive address entries
frame .console.f1 -relief groove -borderwidth 5
pack .console.f1
entry .console.f1.address_span1 -textvariable address_span1 -width 5
entry .console.f1.address_span2 -textvariable address_span2 -width 5
entry .console.f1.address_span3 -textvariable address_span3 -width 5
entry .console.f1.address_span4 -textvariable address_span4 -width 5
entry .console.f1.address_span5 -textvariable address_span5 -width 5
entry .console.f1.address_span6 -textvariable address_span6 -width 5
entry .console.f1.address_span7 -textvariable address_span7 -width 5
entry .console.f1.address_span8 -textvariable address_span8 -width 5
button .console.f1.config -text {Included Address Filter} -command {inclusiveAddrConfig}
pack .console.f1.address_span1 .console.f1.address_span2 .console.f1.address_span3 .console.f1.address_span4 \
.console.f1.address_span5 .console.f1.address_span6 .console.f1.address_span7 .console.f1.address_span8 \
.console.f1.config -side left -ipadx 10
 
# set the exclusive address entries
frame .console.f2 -relief groove -borderwidth 5
pack .console.f2
entry .console.f2.address_span9 -textvariable address_span9 -width 5
entry .console.f2.address_span10 -textvariable address_span10 -width 5
entry .console.f2.address_span11 -textvariable address_span11 -width 5
entry .console.f2.address_span12 -textvariable address_span12 -width 5
entry .console.f2.address_span13 -textvariable address_span13 -width 5
entry .console.f2.address_span14 -textvariable address_span14 -width 5
entry .console.f2.address_span15 -textvariable address_span15 -width 5
entry .console.f2.address_span16 -textvariable address_span16 -width 5
button .console.f2.config -text {Excluded Address Filter} -command {exclusiveAddrConfig}
pack .console.f2.address_span9 .console.f2.address_span10 .console.f2.address_span11 .console.f2.address_span12 \
.console.f2.address_span13 .console.f2.address_span14 .console.f2.address_span15 .console.f2.address_span16 \
.console.f2.config -side left -ipadx 10
 
# set the transaction trigger controls
frame .console.f3 -relief groove -borderwidth 5
pack .console.f3
button .console.f3.enabletrig -text {Enable Trigger} -command {enableTrigger}
button .console.f3.disabletrig -text {Disable Trigger} -command {disableTrigger}
button .console.f3.starttrig -text {Start Trigger} -command {startTrigger}
button .console.f3.stoptrig -text {Stop Trigger} -command {stopTrigger}
entry .console.f3.trigvalue_addr -textvar triggerAddr -width 2
set triggerAddr ffff
entry .console.f3.trigvalue_data -textvar triggerData -width 6
set triggerData a5a5a5a5
label .console.f3.trigaddr -text {@Address :}
label .console.f3.trigdata -text {@Data :}
pack .console.f3.enabletrig .console.f3.starttrig .console.f3.trigaddr .console.f3.trigvalue_addr \
.console.f3.trigdata .console.f3.trigvalue_data .console.f3.stoptrig .console.f3.disabletrig \
-side left -ipadx 8
 
# set the control buttons
frame .console.f0 -relief groove -borderwidth 5
pack .console.f0
button .console.f0.reset -text {Reset FIFO} -command {reset_fifo_ptr}
button .console.f0.loop -text {Query Used Word} -command {query_fifo_usedw}
label .console.f0.usedw -textvariable fifoUsedw -relief sunken
button .console.f0.read -text {Read FIFO} -command {read_fifo_content}
button .console.f0.clear -text {Clear Log} -command {clear_log}
button .console.f0.quit -text {Quit} -command {quit}
pack .console.f0.reset .console.f0.loop .console.f0.usedw .console.f0.read .console.f0.clear .console.f0.quit \
-side left -ipadx 10
 
# set the log window
frame .console.log -relief groove -borderwidth 5
set log [text .console.log.text -width 80 -height 40 \
-borderwidth 2 -relief sunken -setgrid true \
-yscrollcommand {.console.log.scroll set}]
scrollbar .console.log.scroll -command {.console.log.text yview}
pack .console.log.scroll -side right -fill y
pack .console.log.text -side left -fill both -expand true
pack .console.log -side top -fill both -expand true
 
# make the program wait for exit signal
vwait exit_console
 

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