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URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

Subversion Repositories bustap-jtag

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  • This comparison shows the changes necessary to convert path 
    /bustap-jtag/trunk
    from Rev 11 to Rev 12
    ↔ Reverse comparison
  •

Rev 11 → Rev 12

/rtl/up_monitor.v
52,7 → 52,7
wire [31:0] trig_data = trig_cond[31:0];
reg trig_cond_ok,trig_cond_ok_d1;
// for capture storage
wire [49:0] capture_in;
wire [81:0] capture_in;
wire capture_wr;
// for pretrigger capture
wire [9:0] pretrig_num;
60,6 → 60,8
wire pretrig_full;
wire pretrig_wr;
reg pretrig_wr_d1,pretrig_rd;
// for inter capture timer
reg [31:0] inter_cap_cnt;
 
/////////////////////////////////////////////////
// Capture logic main
125,7 → 127,7
wire trig_cond_ok_pulse = trig_cond_ok & !trig_cond_ok_d1;
 
// generate capture wr_in
assign capture_in = {trig_cond_ok_pulse,wr_en_d1,addr_in_d1[15:2],2'b00,data_in_d1[31:0]};
assign capture_in = {trig_cond_ok_pulse,wr_en_d1,inter_cap_cnt,addr_in_d1[15:2],2'b00,data_in_d1[31:0]};
assign capture_wr = trig_cond_ok_pulse | (addr_mask_ok & trig_cond_ok);
 
// generate pre-trigger wr_in
150,6 → 152,17
end
end
 
// generate interval counter
always @(posedge clk)
begin
if (capture_wr || pretrig_wr)
inter_cap_cnt <= 32'd0;
else if (inter_cap_cnt[31])
inter_cap_cnt <= 32'd3000000000;
else
inter_cap_cnt <= inter_cap_cnt + 32'd1;
end
 
/////////////////////////////////////////////////
// Instantiate vendor specific JTAG functions
/////////////////////////////////////////////////
162,7 → 175,7
.rd_in(pretrig_rd)
);
defparam
u_virtual_jtag_adda_fifo.data_width = 50,
u_virtual_jtag_adda_fifo.data_width = 82,
u_virtual_jtag_adda_fifo.fifo_depth = 512,
u_virtual_jtag_adda_fifo.addr_width = 9,
u_virtual_jtag_adda_fifo.al_full_val = 511,
/cmd/altera/virtual_jtag_console.tcl
33,7 → 33,7
device_lock -timeout 5
device_virtual_ir_shift -instance_index $jtag_index_0 -ir_value 1 -no_captured_ir_value
device_virtual_ir_shift -instance_index $jtag_index_0 -ir_value 3 -no_captured_ir_value
set fifo_data [device_virtual_dr_shift -instance_index $jtag_index_0 -length 50 -value_in_hex]
set fifo_data [device_virtual_dr_shift -instance_index $jtag_index_0 -length 82 -value_in_hex]
device_unlock
return $fifo_data
}
261,15 → 261,16
set fifoContent [read_fifo 0]
set ok_trig [expr [format "%d" 0x[string index $fifoContent 0]]/2]
set wr_cptr [expr [format "%d" 0x[string index $fifoContent 0]]%2]
set ad_cptr [string range $fifoContent 1 4]
set da_cptr [string range $fifoContent 5 12]
set tm_cptr [format "%d" 0x[string range $fifoContent 1 8]]
set ad_cptr [string range $fifoContent 9 12]
set da_cptr [string range $fifoContent 13 20]
if $ok_trig {
$log insert end "@@@@@@@@@@@@@@@@@@@@\n"
}
if $wr_cptr {
$log insert end "wr $ad_cptr $da_cptr\n"
$log insert end "wr $ad_cptr $da_cptr @$tm_cptr\n"
} else {
$log insert end "rd $ad_cptr $da_cptr\n"
$log insert end "rd $ad_cptr $da_cptr @$tm_cptr\n"
}
}
query_usedw 0
/sim/altera/virtual_jtag_stimulus.tcl
64,7 → 64,7
#device_lock -timeout 5
#device_virtual_ir_shift -instance_index $jtag_index_0 -ir_value 1 -no_captured_ir_value
#device_virtual_ir_shift -instance_index $jtag_index_0 -ir_value 3 -no_captured_ir_value
#set fifo_data [device_virtual_dr_shift -instance_index $jtag_index_0 -length 50 -value_in_hex]
#set fifo_data [device_virtual_dr_shift -instance_index $jtag_index_0 -length 82 -value_in_hex]
#device_unlock
global sim_started
if {$sim_started==0} {
77,10 → 77,10
append fifo_sim_act (0,1,3,[format "%X" 2]),
set fifo_sim_num [expr $fifo_sim_num+1]
set fifo_sim_len [expr $fifo_sim_len+2]
append fifo_sim_act (0,2,0,[format "%X" 50]),
append fifo_sim_act (0,2,0,[format "%X" 82]),
set fifo_sim_num [expr $fifo_sim_num+1]
set fifo_sim_len [expr $fifo_sim_len+50]
return 0000000000000
set fifo_sim_len [expr $fifo_sim_len+82]
return 000000000000000000000
} else {
force -freeze /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/rd_en 1 -cancel 10ns
run 20ns
337,15 → 337,16
set fifoContent [read_fifo 0]
set ok_trig [expr [format "%d" 0x[string index $fifoContent 0]]/2]
set wr_cptr [expr [format "%d" 0x[string index $fifoContent 0]]%2]
set ad_cptr [string range $fifoContent 1 4]
set da_cptr [string range $fifoContent 5 12]
set tm_cptr [format "%d" 0x[string range $fifoContent 1 8]]
set ad_cptr [string range $fifoContent 9 12]
set da_cptr [string range $fifoContent 13 20]
if $ok_trig {
$log insert end "@@@@@@@@@@@@@@@@@@@@\n"
}
if $wr_cptr {
$log insert end "wr $ad_cptr $da_cptr\n"
$log insert end "wr $ad_cptr $da_cptr @$tm_cptr\n"
} else {
$log insert end "rd $ad_cptr $da_cptr\n"
$log insert end "rd $ad_cptr $da_cptr @$tm_cptr\n"
}
}
query_usedw 0
/sim/altera/wave.do
1,71 → 1,73
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {CPU BFM}
add wave -noupdate -format Logic /up_monitor_tb/CPU/up_clk
add wave -noupdate -format Logic /up_monitor_tb/CPU/up_csn
add wave -noupdate -format Logic /up_monitor_tb/CPU/up_wbe
add wave -noupdate -format Literal /up_monitor_tb/CPU/up_addr
add wave -noupdate -format Literal /up_monitor_tb/CPU/up_data_io
add wave -noupdate -divider {REG BFM}
add wave -noupdate -format Logic /up_monitor_tb/REG/up_clk
add wave -noupdate -format Logic /up_monitor_tb/REG/up_csn
add wave -noupdate -format Logic /up_monitor_tb/REG/up_wbe
add wave -noupdate -format Literal /up_monitor_tb/REG/up_addr
add wave -noupdate -format Literal /up_monitor_tb/REG/up_data_io
add wave -noupdate -divider MON_LO
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/up_wbe
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/up_csn
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/up_addr
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/up_data_io
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/up_clk
add wave -noupdate -divider pin-to-transaction
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/wr_en
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/rd_en
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/addr_in
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/data_in
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/wr_en_d1
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/rd_en_d1
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/addr_in_d1
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/data_in_d1
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/addr_mask_ok
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/trig_cond_ok_d1
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/capture_wr
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/capture_in
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/clk
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/wr_en
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/data_in
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/reset
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/usedw
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/rd_en
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/data_out
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/pretrig_num
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/pretrig_cnt
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/pretrig_full
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/pretrig_wr
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/pretrig_rd
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/sld_virtual_jtag_component/user_input/vj_sim_done
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_trig/sld_virtual_jtag_component/user_input/vj_sim_done
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/u_virtual_jtag_addr_mask/sld_virtual_jtag_component/user_input/vj_sim_done
add wave -noupdate -divider {New Divider}
add wave -noupdate -divider {New Divider}
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {11169937 ps} 0}
configure wave -namecolwidth 147
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {10500 ns}
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {CPU BFM}
add wave -noupdate -format Logic /up_monitor_tb/CPU/up_clk
add wave -noupdate -format Logic /up_monitor_tb/CPU/up_csn
add wave -noupdate -format Logic /up_monitor_tb/CPU/up_wbe
add wave -noupdate -format Literal /up_monitor_tb/CPU/up_addr
add wave -noupdate -format Literal /up_monitor_tb/CPU/up_data_io
add wave -noupdate -divider {REG BFM}
add wave -noupdate -format Logic /up_monitor_tb/REG/up_clk
add wave -noupdate -format Logic /up_monitor_tb/REG/up_csn
add wave -noupdate -format Logic /up_monitor_tb/REG/up_wbe
add wave -noupdate -format Literal /up_monitor_tb/REG/up_addr
add wave -noupdate -format Literal /up_monitor_tb/REG/up_data_io
add wave -noupdate -divider MON_LO
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/up_wbe
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/up_csn
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/up_addr
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/up_data_io
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/up_clk
add wave -noupdate -divider pin-to-transaction
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/wr_en
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/rd_en
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/addr_in
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/data_in
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/wr_en_d1
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/rd_en_d1
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/addr_in_d1
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/data_in_d1
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/addr_mask_ok
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/trig_cond_ok_d1
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/capture_wr
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/capture_in
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/clk
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/wr_en
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/data_in
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/reset
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/usedw
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/rd_en
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/data_out
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/pretrig_num
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/pretrig_cnt
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/pretrig_full
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/pretrig_wr
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/pretrig_rd
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Literal -radix unsigned /up_monitor_tb/MON_LO/inst/inter_cap_cnt
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/sld_virtual_jtag_component/user_input/vj_sim_done
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_trig/sld_virtual_jtag_component/user_input/vj_sim_done
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/u_virtual_jtag_addr_mask/sld_virtual_jtag_component/user_input/vj_sim_done
add wave -noupdate -divider {New Divider}
add wave -noupdate -divider {New Divider}
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {8603967 ps} 0}
configure wave -namecolwidth 147
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {10500 ns}
/sim/altera/sim.do
6,8 → 6,8
set sim_started 0
 
# compile vendor independent files
vlog -work work ../../rtl/up_monitor.v
vlog -work work ../../rtl/up_monitor_wrapper.v
vlog -work work ../../rtl/up_monitor.v +initreg+0
vlog -work work ../../rtl/up_monitor_wrapper.v +initreg+0
 
# compile altera virtual jtag files
source virtual_jtag_stimulus.tcl

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