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Rev 23 → Rev 24

/rtl/altera/qsys/bustap_jtag_hw.tcl
0,0 → 1,168
# TCL File Generated by Component Editor 13.1
# Wed Sep 03 12:38:07 CST 2014
# DO NOT MODIFY
 
 
#
# bustap_jtag "bustap_jtag" v1.0
# 2014.09.03.12:38:07
#
#
 
#
# request TCL package from ACDS 13.1
#
package require -exact qsys 13.1
 
 
#
# module bustap_jtag
#
set_module_property DESCRIPTION ""
set_module_property NAME bustap_jtag
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP System
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME bustap_jtag
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL AUTO
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
 
 
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL bustap_jtag
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
add_fileset_file jtag_sim_define.h OTHER PATH ../jtag_sim_define.h
add_fileset_file vendor.h OTHER PATH ../../../par/altera/vendor.h
add_fileset_file bustap_jtag.v VERILOG PATH bustap_jtag.v TOP_LEVEL_FILE
add_fileset_file up_monitor.v VERILOG PATH ../../up_monitor.v
add_fileset_file virtual_jtag_adda_fifo.v VERILOG PATH ../virtual_jtag_adda_fifo.v
add_fileset_file virtual_jtag_adda_trig.v VERILOG PATH ../virtual_jtag_adda_trig.v
add_fileset_file virtual_jtag_addr_mask.v VERILOG PATH ../virtual_jtag_addr_mask.v
 
 
#
# parameters
#
add_parameter addr_width INTEGER 32
set_parameter_property addr_width DEFAULT_VALUE 32
set_parameter_property addr_width DISPLAY_NAME addr_width
set_parameter_property addr_width TYPE INTEGER
set_parameter_property addr_width UNITS None
set_parameter_property addr_width HDL_PARAMETER true
 
 
#
# display items
#
 
 
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
 
add_interface_port clock gls_clk clk Input 1
 
 
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""
 
add_interface_port reset gls_reset reset Input 1
 
 
#
# connection point s1
#
add_interface s1 avalon end
set_interface_property s1 addressUnits SYMBOLS
set_interface_property s1 associatedClock clock
set_interface_property s1 associatedReset reset
set_interface_property s1 bitsPerSymbol 8
set_interface_property s1 burstOnBurstBoundariesOnly false
set_interface_property s1 burstcountUnits SYMBOLS
set_interface_property s1 explicitAddressSpan 0
set_interface_property s1 holdTime 0
set_interface_property s1 linewrapBursts false
set_interface_property s1 maximumPendingReadTransactions 0
set_interface_property s1 readLatency 0
set_interface_property s1 readWaitTime 1
set_interface_property s1 setupTime 0
set_interface_property s1 timingUnits Cycles
set_interface_property s1 writeWaitTime 0
set_interface_property s1 ENABLED true
set_interface_property s1 EXPORT_OF ""
set_interface_property s1 PORT_NAME_MAP ""
set_interface_property s1 CMSIS_SVD_VARIABLES ""
set_interface_property s1 SVD_ADDRESS_GROUP ""
 
add_interface_port s1 avs_s1_chipselect chipselect Input 1
add_interface_port s1 avs_s1_address address Input addr_width
add_interface_port s1 avs_s1_read read Input 1
add_interface_port s1 avs_s1_readdata readdata Output 32
add_interface_port s1 avs_s1_write write Input 1
add_interface_port s1 avs_s1_writedata writedata Input 32
add_interface_port s1 avs_s1_byteenable byteenable Input 4
add_interface_port s1 avs_s1_waitrequest waitrequest Output 1
set_interface_assignment s1 embeddedsw.configuration.isFlash 0
set_interface_assignment s1 embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment s1 embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment s1 embeddedsw.configuration.isPrintableDevice 0
 
 
#
# connection point m1
#
add_interface m1 avalon start
set_interface_property m1 addressUnits SYMBOLS
set_interface_property m1 associatedClock clock
set_interface_property m1 associatedReset reset
set_interface_property m1 bitsPerSymbol 8
set_interface_property m1 burstOnBurstBoundariesOnly false
set_interface_property m1 burstcountUnits SYMBOLS
set_interface_property m1 doStreamReads false
set_interface_property m1 doStreamWrites false
set_interface_property m1 holdTime 0
set_interface_property m1 linewrapBursts false
set_interface_property m1 maximumPendingReadTransactions 0
set_interface_property m1 readLatency 0
set_interface_property m1 readWaitTime 1
set_interface_property m1 setupTime 0
set_interface_property m1 timingUnits Cycles
set_interface_property m1 writeWaitTime 0
set_interface_property m1 ENABLED true
set_interface_property m1 EXPORT_OF ""
set_interface_property m1 PORT_NAME_MAP ""
set_interface_property m1 CMSIS_SVD_VARIABLES ""
set_interface_property m1 SVD_ADDRESS_GROUP ""
 
add_interface_port m1 avm_m1_waitrequest waitrequest Input 1
add_interface_port m1 avm_m1_address address Output addr_width
add_interface_port m1 avm_m1_read read Output 1
add_interface_port m1 avm_m1_readdata readdata Input 32
add_interface_port m1 avm_m1_write write Output 1
add_interface_port m1 avm_m1_writedata writedata Output 32
add_interface_port m1 avm_m1_byteenable byteenable Output 4
 
/rtl/altera/qsys/bustap_jtag.v
0,0 → 1,91
 
module bustap_jtag(
gls_clk,
gls_reset,
// slave interface signals
avs_s1_chipselect,
avs_s1_address,
avs_s1_read,
avs_s1_readdata,
avs_s1_write,
avs_s1_writedata,
avs_s1_byteenable,
avs_s1_waitrequest,
// master interface signals
avm_m1_waitrequest,
avm_m1_address,
avm_m1_read,
avm_m1_readdata,
avm_m1_write,
avm_m1_writedata,
avm_m1_byteenable);
 
parameter addr_width = 32;
 
input gls_clk,gls_reset;
// slave interface signals
input avs_s1_chipselect;
output avs_s1_waitrequest;
input [addr_width-1:0]avs_s1_address;
input avs_s1_read,avs_s1_write;
output [31:0]avs_s1_readdata;
input [31:0]avs_s1_writedata;
input [3:0]avs_s1_byteenable;
// master interface signals
input avm_m1_waitrequest;
output [addr_width-1:0]avm_m1_address;
output avm_m1_read,avm_m1_write;
input [31:0]avm_m1_readdata;
output [31:0]avm_m1_writedata;
output [3:0]avm_m1_byteenable;
 
// bypass avalon bus signals
assign avs_s1_waitrequest = avm_m1_waitrequest;
assign avm_m1_address = avs_s1_address;
assign avm_m1_read = avs_s1_read && avs_s1_chipselect;
assign avm_m1_write = avs_s1_write && avs_s1_chipselect;
assign avs_s1_readdata = avm_m1_readdata;
assign avm_m1_writedata = avs_s1_writedata;
assign avm_m1_byteenable = avs_s1_byteenable;
 
// capture avalon bus signals
reg wr_en_latch, rd_en_latch;
reg [31:0] addr_latch;
reg [31:0] data_latch;
 
always @(posedge gls_clk) begin
wr_en_latch <= avs_s1_chipselect && avs_s1_write && !avs_s1_waitrequest;
end
 
always @(posedge gls_clk) begin
rd_en_latch <= avs_s1_chipselect && avs_s1_read && !avs_s1_waitrequest;
end
 
always @(posedge gls_clk) begin
if (avs_s1_chipselect && (avs_s1_read || avs_s1_write) && !avs_s1_waitrequest)
addr_latch <= {{(32-addr_width){1'b0}}, avs_s1_address};
end
 
always @(posedge gls_clk) begin
if (avs_s1_chipselect && avs_s1_read && !avs_s1_waitrequest)
data_latch <= avs_s1_readdata;
if (avs_s1_chipselect && avs_s1_write && !avs_s1_waitrequest)
data_latch <= avs_s1_writedata;
end
 
// map to avalon access interface
wire clk = gls_clk;
wire wr_en = wr_en_latch;
wire rd_en = rd_en_latch;
wire [31:0] addr_in = addr_latch;
wire [31:0] data_in = data_latch;
 
up_monitor inst (
.clk(clk),
.wr_en(wr_en),
.rd_en(rd_en),
.addr_in(addr_in),
.data_in(data_in)
);
 
endmodule

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