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Rev 5 → Rev 6

/rtl/up_monitor.v
7,8 → 7,8
// Targets device : Cyclone III
// Author : Bibo Yang (ash_riple@hotmail.com)
// Organization : www.opencores.org
// Revision : 2.0
// Date : 2012/03/12
// Revision : 2.1
// Date : 2012/03/15
// Description : Top level glue logic to group together
// the JTAG input and output modules.
//**************************************************************
22,24 → 22,43
input [31:0] data_in
);
 
reg wr_en_d1,rd_en_d1;
reg [15:2] addr_in_d1;
reg [31:0] data_in_d1;
/////////////////////////////////////////////////
// Registers and wires announcment
/////////////////////////////////////////////////
 
wire [31:0] addr_mask0,addr_mask1,addr_mask2,addr_mask3,addr_mask4,addr_mask5,addr_mask6,addr_mask7,
addr_mask8,addr_mask9,addr_mask10,addr_mask11,addr_mask12,addr_mask13,addr_mask14,addr_mask15;
// for CPU bus signal buffer
reg wr_en_d1,rd_en_d1;
reg [15:2] addr_in_d1;
reg [31:0] data_in_d1;
// for capture address mask
wire [35:0] addr_mask0,addr_mask1,addr_mask2 ,addr_mask3 ,addr_mask4 ,addr_mask5 ,addr_mask6 ,addr_mask7 , // inclusive
addr_mask8,addr_mask9,addr_mask10,addr_mask11,addr_mask12,addr_mask13,addr_mask14,addr_mask15; // exclusive
wire [15:0] addr_mask_en = {addr_mask15[32],addr_mask14[32],addr_mask13[32],addr_mask12[32],
addr_mask11[32],addr_mask10[32],addr_mask9 [32],addr_mask8 [32],
addr_mask7 [32],addr_mask6 [32],addr_mask5 [32],addr_mask4 [32],
addr_mask3 [32],addr_mask2 [32],addr_mask1 [32],addr_mask0 [32]};
wire addr_wren = addr_mask15[35];
wire addr_rden = addr_mask15[34];
reg addr_mask_ok;
 
wire [49:0] trig_cond;
// for capture address+data trigger
wire [55:0] trig_cond;
wire trig_aden = trig_cond[55];
wire trig_daen = trig_cond[54];
wire trig_wren = trig_cond[51];
wire trig_rden = trig_cond[50];
wire trig_en = trig_cond[49];
wire trig_set = trig_cond[48];
wire [15:0] trig_addr = trig_cond[47:32];
wire [31:0] trig_data = trig_cond[31:0];
reg trig_cond_ok;
 
wire [47:0] capture_in;
reg trig_cond_ok,trig_cond_ok_d1;
// for capture storage
wire [49:0] capture_in;
wire capture_wr;
 
/////////////////////////////////////////////////
// Capture logic main
/////////////////////////////////////////////////
 
// bus input pipeline, allowing back-to-back/continuous bus access
always @(posedge clk)
begin
52,49 → 71,77
// address range based capture enable
always @(posedge clk)
begin
if (((addr_in[15:2]<=addr_mask0[31:18] && addr_in[15:2]>=addr_mask0[15:2]) ||
(addr_in[15:2]<=addr_mask1[31:18] && addr_in[15:2]>=addr_mask1[15:2]) ||
(addr_in[15:2]<=addr_mask2[31:18] && addr_in[15:2]>=addr_mask2[15:2]) ||
(addr_in[15:2]<=addr_mask3[31:18] && addr_in[15:2]>=addr_mask3[15:2]) ||
(addr_in[15:2]<=addr_mask4[31:18] && addr_in[15:2]>=addr_mask4[15:2]) ||
(addr_in[15:2]<=addr_mask5[31:18] && addr_in[15:2]>=addr_mask5[15:2]) ||
(addr_in[15:2]<=addr_mask6[31:18] && addr_in[15:2]>=addr_mask6[15:2]) ||
(addr_in[15:2]<=addr_mask7[31:18] && addr_in[15:2]>=addr_mask7[15:2])
) //inclusive address range set: addr_mask 0 - 7
if (((addr_in[15:2]<=addr_mask0[31:18] && addr_in[15:2]>=addr_mask0[15:2] && addr_mask_en[ 0]) ||
(addr_in[15:2]<=addr_mask1[31:18] && addr_in[15:2]>=addr_mask1[15:2] && addr_mask_en[ 1]) ||
(addr_in[15:2]<=addr_mask2[31:18] && addr_in[15:2]>=addr_mask2[15:2] && addr_mask_en[ 2]) ||
(addr_in[15:2]<=addr_mask3[31:18] && addr_in[15:2]>=addr_mask3[15:2] && addr_mask_en[ 3]) ||
(addr_in[15:2]<=addr_mask4[31:18] && addr_in[15:2]>=addr_mask4[15:2] && addr_mask_en[ 4]) ||
(addr_in[15:2]<=addr_mask5[31:18] && addr_in[15:2]>=addr_mask5[15:2] && addr_mask_en[ 5]) ||
(addr_in[15:2]<=addr_mask6[31:18] && addr_in[15:2]>=addr_mask6[15:2] && addr_mask_en[ 6]) ||
(addr_in[15:2]<=addr_mask7[31:18] && addr_in[15:2]>=addr_mask7[15:2] && addr_mask_en[ 7])
) //inclusive address range set with individual enable: addr_mask 0 - 7
&&
((addr_in[15:2]>addr_mask8 [31:18] || addr_in[15:2]<addr_mask8 [15:2]) &&
(addr_in[15:2]>addr_mask9 [31:18] || addr_in[15:2]<addr_mask9 [15:2]) &&
(addr_in[15:2]>addr_mask10[31:18] || addr_in[15:2]<addr_mask10[15:2]) &&
(addr_in[15:2]>addr_mask11[31:18] || addr_in[15:2]<addr_mask11[15:2]) &&
(addr_in[15:2]>addr_mask12[31:18] || addr_in[15:2]<addr_mask12[15:2]) &&
(addr_in[15:2]>addr_mask13[31:18] || addr_in[15:2]<addr_mask13[15:2]) &&
(addr_in[15:2]>addr_mask14[31:18] || addr_in[15:2]<addr_mask14[15:2]) &&
(addr_in[15:2]>addr_mask15[31:18] || addr_in[15:2]<addr_mask15[15:2])
) //exclusive address range set: addr_mask 8 - 15
((addr_in[15:2]>addr_mask8 [31:18] || addr_in[15:2]<addr_mask8 [15:2] || !addr_mask_en[ 8]) &&
(addr_in[15:2]>addr_mask9 [31:18] || addr_in[15:2]<addr_mask9 [15:2] || !addr_mask_en[ 9]) &&
(addr_in[15:2]>addr_mask10[31:18] || addr_in[15:2]<addr_mask10[15:2] || !addr_mask_en[10]) &&
(addr_in[15:2]>addr_mask11[31:18] || addr_in[15:2]<addr_mask11[15:2] || !addr_mask_en[11]) &&
(addr_in[15:2]>addr_mask12[31:18] || addr_in[15:2]<addr_mask12[15:2] || !addr_mask_en[12]) &&
(addr_in[15:2]>addr_mask13[31:18] || addr_in[15:2]<addr_mask13[15:2] || !addr_mask_en[13]) &&
(addr_in[15:2]>addr_mask14[31:18] || addr_in[15:2]<addr_mask14[15:2] || !addr_mask_en[14]) &&
(addr_in[15:2]>addr_mask15[31:18] || addr_in[15:2]<addr_mask15[15:2] || !addr_mask_en[15])
) //exclusive address range set with individual enable: addr_mask 8 - 15
)
addr_mask_ok <= wr_en;
addr_mask_ok <= (addr_rden && rd_en) || (addr_wren && wr_en);
else
addr_mask_ok <= 0;
end
 
// address-data based capture trigger
// address+data based capture trigger
always @(posedge clk)
begin
if (trig_en==0) // trigger not enabled, trigger gate forced open
trig_cond_ok <= 1;
else if (trig_set==0) // trigger enabled and trigger stopped, trigger gate forced close
trig_cond_ok <= 0;
else // trigger enabled and trigger started, trigger gate conditional open
if (trig_addr[15:2]==addr_in[15:2] && trig_data==data_in)
trig_cond_ok <= wr_en;// trigger gate kept open until trigger stoped
if (trig_en==0) begin // trigger not enabled, trigger gate forced open
trig_cond_ok <= 1;
trig_cond_ok_d1 <= 1;
end
else if (trig_set==0) begin // trigger enabled and trigger stopped, trigger gate forced close
trig_cond_ok <= 0;
trig_cond_ok_d1 <= 0;
end
else begin // trigger enabled and trigger started, trigger gate conditional open
if ((trig_aden? trig_addr[15:2]==addr_in[15:2]: 1) && (trig_daen? trig_data==data_in: 1) &&
(trig_wren? wr_en : 1) && (trig_rden? rd_en : 1) &&
(rd_en || wr_en))
trig_cond_ok <= 1;
trig_cond_ok_d1 <= trig_cond_ok;
end
// trigger gate kept open until trigger stoped
end
wire trig_cond_ok_pulse = trig_cond_ok & !trig_cond_ok_d1;
 
// generate capture wr-in
assign capture_in = {addr_in_d1[15:2],2'b0,data_in_d1[31:0]};
assign capture_wr = wr_en_d1 && addr_mask_ok && trig_cond_ok;
assign capture_in = {trig_cond_ok_pulse,wr_en_d1,addr_in_d1[15:2],2'b00,data_in_d1[31:0]};
assign capture_wr = trig_cond_ok_pulse | (addr_mask_ok & trig_cond_ok);
 
// instantiate capture mask, as input
/////////////////////////////////////////////////
// Instantiate vendor specific JTAG functions
/////////////////////////////////////////////////
 
// index 0, instantiate capture fifo, as output
virtual_jtag_adda_fifo u_virtual_jtag_adda_fifo (
.clk(clk),
.wr_en(capture_wr),
.data_in(capture_in)
);
defparam
u_virtual_jtag_adda_fifo.data_width = 50,
u_virtual_jtag_adda_fifo.fifo_depth = 512,
u_virtual_jtag_adda_fifo.addr_width = 9,
u_virtual_jtag_adda_fifo.al_full_val = 511,
u_virtual_jtag_adda_fifo.al_empt_val = 0;
 
// index 1, instantiate capture mask, as input
virtual_jtag_addr_mask u_virtual_jtag_addr_mask (
// inclusive
.mask_out0(addr_mask0),
.mask_out1(addr_mask1),
.mask_out2(addr_mask2),
103,6 → 150,7
.mask_out5(addr_mask5),
.mask_out6(addr_mask6),
.mask_out7(addr_mask7),
// exclusive
.mask_out8(addr_mask8),
.mask_out9(addr_mask9),
.mask_out10(addr_mask10),
113,28 → 161,15
.mask_out15(addr_mask15)
);
defparam
u_virtual_jtag_addr_mask.addr_width = 32,
u_virtual_jtag_addr_mask.mask_index = 4,
u_virtual_jtag_addr_mask.mask_num = 16;
u_virtual_jtag_addr_mask.mask_enabl = 4,
u_virtual_jtag_addr_mask.addr_width = 32;
 
// instantiate capture trigger, as input
// index 2, instantiate capture trigger, as input
virtual_jtag_adda_trig u_virtual_jtag_adda_trig (
.trig_out(trig_cond)
);
defparam
u_virtual_jtag_adda_trig.trig_width = 50;
u_virtual_jtag_adda_trig.trig_width = 56;
 
// instantiate capture fifo, as output
virtual_jtag_adda_fifo u_virtual_jtag_adda_fifo (
.clk(clk),
.wr_en(capture_wr),
.data_in(capture_in)
);
defparam
u_virtual_jtag_adda_fifo.data_width = 48,
u_virtual_jtag_adda_fifo.fifo_depth = 512,
u_virtual_jtag_adda_fifo.addr_width = 9,
u_virtual_jtag_adda_fifo.al_full_val = 511,
u_virtual_jtag_adda_fifo.al_empt_val = 0;
 
endmodule
/rtl/up_monitor_wrapper.v
7,10 → 7,11
// Targets device : Cyclone III
// Author : Bibo Yang (ash_riple@hotmail.com)
// Organization : www.opencores.org
// Revision : 2.0
// Date : 2012/03/12
// Revision : 2.1
// Date : 2012/03/15
// Description : Common CPU interface to pipelined access
// interface converter.
// @Note: Implementation dependent.
//**************************************************************
 
`timescale 1ns/1ns
19,32 → 20,50
 
// common CPU bus interface
input up_clk;
input up_wbe,up_csn;
input up_wbe,up_csn; // negative logic
input [15:2] up_addr;
input [31:0] up_data_io;
 
// prepare for generating wr_en pulse
reg up_wr_d1, up_wr_d2, up_wr_d3;
// filter out glitches on the line with extra 4 clocks
reg up_wbe_d1, up_wbe_d2, up_wbe_d3, up_wbe_d4;
reg up_csn_d1, up_csn_d2, up_csn_d3, up_csn_d4;
always @(posedge up_clk) begin
up_wr_d1 <= !up_wbe & !up_csn;
up_wr_d2 <= up_wr_d1;
up_wr_d3 <= up_wr_d2;
up_wbe_d1 <= up_wbe;
up_wbe_d2 <= up_wbe_d1;
up_wbe_d3 <= up_wbe_d2;
up_wbe_d4 <= up_wbe_d3;
up_csn_d1 <= up_csn;
up_csn_d2 <= up_csn_d1;
up_csn_d3 <= up_csn_d2;
up_csn_d4 <= up_csn_d3;
end
 
// prepare for generating rd_en pulse
reg up_rd_d1, up_rd_d2, up_rd_d3;
reg wr_en_filtered, wr_en_filtered_d1;
always @(posedge up_clk) begin
up_rd_d1 <= up_wbe & !up_csn;
up_rd_d2 <= up_rd_d1;
up_rd_d3 <= up_rd_d2;
// negative logic changed to positive logic, with filter
wr_en_filtered <= (!up_wbe_d2 & !up_wbe_d3 & !up_wbe_d4) & (!up_csn_d2 & !up_csn_d3 & !up_csn_d4);
wr_en_filtered_d1 <= wr_en_filtered;
end
reg rd_en_filtered, rd_en_filtered_d1;
always @(posedge up_clk) begin
// negative logic changed to positive logic, with filter
rd_en_filtered <= (up_wbe_d2 & up_wbe_d3 & up_wbe_d4) & (!up_csn_d2 & !up_csn_d3 & !up_csn_d4);
rd_en_filtered_d1 <= rd_en_filtered;
end
 
// latch the data at rising edge of up_csn(negative logic)
reg [15:2] up_addr_latch;
reg [31:0] up_data_latch;
always @(posedge up_csn) begin
up_addr_latch <= up_addr;
up_data_latch <= up_data_io;
end
 
// map to pipelined access interface
wire clk = up_clk;
wire wr_en = up_wr_d2 & !up_wr_d3;
wire rd_en = up_rd_d2 & !up_rd_d3;
wire [15:2] addr_in = up_addr;
wire [31:0] data_in = up_data_io;
wire wr_en = !wr_en_filtered & wr_en_filtered_d1; // falling edge of write_enable(positive logic)
wire rd_en = !rd_en_filtered & rd_en_filtered_d1; // falling edge of read_enable(positive logic)
wire [15:2] addr_in = up_addr_latch;
wire [31:0] data_in = up_data_latch;
 
up_monitor inst (
.clk(clk),
/rtl/altera/virtual_jtag_addr_mask.v
7,8 → 7,8
// Targets device : Cyclone III
// Author : Bibo Yang (ash_riple@hotmail.com)
// Organization : www.opencores.org
// Revision : 2.0
// Date : 2012/03/12
// Revision : 2.1
// Date : 2012/03/15
// Description : addr mask input from debug host via
// Virtual JTAG.
//**************************************************************
21,54 → 21,54
mask_out12,mask_out13,mask_out14,mask_out15
);
 
parameter addr_width = 32,
mask_index = 4, //2**mask_index=mask_num
mask_num = 16;
parameter mask_index = 4, //2**mask_index=mask_num
mask_enabl = 4,
addr_width = 32;
 
output [addr_width-1:0] mask_out0;
output [addr_width-1:0] mask_out1;
output [addr_width-1:0] mask_out2;
output [addr_width-1:0] mask_out3;
output [addr_width-1:0] mask_out4;
output [addr_width-1:0] mask_out5;
output [addr_width-1:0] mask_out6;
output [addr_width-1:0] mask_out7;
output [addr_width-1:0] mask_out8;
output [addr_width-1:0] mask_out9;
output [addr_width-1:0] mask_out10;
output [addr_width-1:0] mask_out11;
output [addr_width-1:0] mask_out12;
output [addr_width-1:0] mask_out13;
output [addr_width-1:0] mask_out14;
output [addr_width-1:0] mask_out15;
output [mask_enabl+addr_width-1:0] mask_out0;
output [mask_enabl+addr_width-1:0] mask_out1;
output [mask_enabl+addr_width-1:0] mask_out2;
output [mask_enabl+addr_width-1:0] mask_out3;
output [mask_enabl+addr_width-1:0] mask_out4;
output [mask_enabl+addr_width-1:0] mask_out5;
output [mask_enabl+addr_width-1:0] mask_out6;
output [mask_enabl+addr_width-1:0] mask_out7;
output [mask_enabl+addr_width-1:0] mask_out8;
output [mask_enabl+addr_width-1:0] mask_out9;
output [mask_enabl+addr_width-1:0] mask_out10;
output [mask_enabl+addr_width-1:0] mask_out11;
output [mask_enabl+addr_width-1:0] mask_out12;
output [mask_enabl+addr_width-1:0] mask_out13;
output [mask_enabl+addr_width-1:0] mask_out14;
output [mask_enabl+addr_width-1:0] mask_out15;
 
reg [addr_width-1:0] mask_out0;
reg [addr_width-1:0] mask_out1;
reg [addr_width-1:0] mask_out2;
reg [addr_width-1:0] mask_out3;
reg [addr_width-1:0] mask_out4;
reg [addr_width-1:0] mask_out5;
reg [addr_width-1:0] mask_out6;
reg [addr_width-1:0] mask_out7;
reg [addr_width-1:0] mask_out8;
reg [addr_width-1:0] mask_out9;
reg [addr_width-1:0] mask_out10;
reg [addr_width-1:0] mask_out11;
reg [addr_width-1:0] mask_out12;
reg [addr_width-1:0] mask_out13;
reg [addr_width-1:0] mask_out14;
reg [addr_width-1:0] mask_out15;
reg [mask_enabl+addr_width-1:0] mask_out0;
reg [mask_enabl+addr_width-1:0] mask_out1;
reg [mask_enabl+addr_width-1:0] mask_out2;
reg [mask_enabl+addr_width-1:0] mask_out3;
reg [mask_enabl+addr_width-1:0] mask_out4;
reg [mask_enabl+addr_width-1:0] mask_out5;
reg [mask_enabl+addr_width-1:0] mask_out6;
reg [mask_enabl+addr_width-1:0] mask_out7;
reg [mask_enabl+addr_width-1:0] mask_out8;
reg [mask_enabl+addr_width-1:0] mask_out9;
reg [mask_enabl+addr_width-1:0] mask_out10;
reg [mask_enabl+addr_width-1:0] mask_out11;
reg [mask_enabl+addr_width-1:0] mask_out12;
reg [mask_enabl+addr_width-1:0] mask_out13;
reg [mask_enabl+addr_width-1:0] mask_out14;
reg [mask_enabl+addr_width-1:0] mask_out15;
 
wire tdi, tck, cdr, cir, e1dr, e2dr, pdr, sdr, udr, uir;
reg tdo;
reg [mask_index+addr_width-1:0] mask_instr_reg;
reg [mask_index+mask_enabl+addr_width-1:0] mask_instr_reg;
reg bypass_reg;
 
wire [1:0] ir_in;
wire mask_instr = ~ir_in[1] & ir_in[0]; // 1
 
wire [mask_index-1:0] mask_id = mask_instr_reg[(mask_index+addr_width-1):addr_width];
wire [addr_width-1:0] mask_is = mask_instr_reg[(addr_width-1):0];
wire [mask_index-1 :0] mask_id = mask_instr_reg[(mask_index+mask_enabl+addr_width-1):(mask_enabl+addr_width)];
wire [mask_enabl+addr_width-1:0] mask_is = mask_instr_reg[ (mask_enabl+addr_width-1):0];
 
always @(posedge tck)
begin
114,7 → 114,7
if ( mask_instr && cdr )
mask_instr_reg <= mask_instr_reg;
else if ( mask_instr && sdr )
mask_instr_reg <= {tdi, mask_instr_reg[mask_index+addr_width-1:1]};
mask_instr_reg <= {tdi, mask_instr_reg[mask_index+mask_enabl+addr_width-1:1]};
 
/* Bypass register */
always @ (posedge tck)
/rtl/altera/virtual_jtag_adda_fifo.v
7,8 → 7,8
// Targets device : Cyclone III
// Author : Bibo Yang (ash_riple@hotmail.com)
// Organization : www.opencores.org
// Revision : 2.0
// Date : 2012/03/12
// Revision : 2.1
// Date : 2012/03/15
// Description : addr/data capture output to debug host
// via Virtual JTAG.
//**************************************************************
/rtl/altera/virtual_jtag_adda_trig.v
7,8 → 7,8
// Targets device : Cyclone III
// Author : Bibo Yang (ash_riple@hotmail.com)
// Organization : www.opencores.org
// Revision : 2.0
// Date : 2012/03/12
// Revision : 2.1
// Date : 2012/03/15
// Description : addr/data trigger input from debug host
// via Virtual JTAG.
//**************************************************************
/cmd/altera/virtual_jtag_console.tcl
1,5 → 1,15
##**************************************************************
## Module : virtual_jtag_consile.tcl
## Platform : Windows xp sp2
## Author : Bibo Yang (ash_riple@hotmail.com)
## Organization : www.opencores.org
## Revision : 2.1
## Date : 2012/03/15
## Description : Tcl/Tk GUI for the up_monitor
##**************************************************************
 
proc reset_fifo {{jtag_index_0 0}} {
device_lock -timeout 10000
device_lock -timeout 5
device_virtual_ir_shift -instance_index $jtag_index_0 -ir_value 2 -no_captured_ir_value
device_virtual_dr_shift -instance_index $jtag_index_0 -length 32 -dr_value 00000000 -value_in_hex -no_captured_dr_value
device_unlock
8,7 → 18,7
 
proc query_usedw {{jtag_index_0 0}} {
global fifoUsedw
device_lock -timeout 10000
device_lock -timeout 5
device_virtual_ir_shift -instance_index $jtag_index_0 -ir_value 1 -no_captured_ir_value
set usedw [device_virtual_dr_shift -instance_index $jtag_index_0 -length 9 -value_in_hex]
device_unlock
20,26 → 30,26
}
 
proc read_fifo {{jtag_index_0 0}} {
device_lock -timeout 10000
device_lock -timeout 5
device_virtual_ir_shift -instance_index $jtag_index_0 -ir_value 1 -no_captured_ir_value
device_virtual_ir_shift -instance_index $jtag_index_0 -ir_value 3 -no_captured_ir_value
set fifo_data [device_virtual_dr_shift -instance_index $jtag_index_0 -length 48 -value_in_hex]
set fifo_data [device_virtual_dr_shift -instance_index $jtag_index_0 -length 50 -value_in_hex]
device_unlock
return $fifo_data
}
 
proc config_addr {{jtag_index_1 1} {mask_1 100000000}} {
device_lock -timeout 10000
proc config_addr {{jtag_index_1 1} {mask_1 0100000000}} {
device_lock -timeout 5
device_virtual_ir_shift -instance_index $jtag_index_1 -ir_value 1 -no_captured_ir_value
set addr_mask [device_virtual_dr_shift -instance_index $jtag_index_1 -dr_value $mask_1 -length 36 -value_in_hex]
set addr_mask [device_virtual_dr_shift -instance_index $jtag_index_1 -dr_value $mask_1 -length 40 -value_in_hex]
device_unlock
return $addr_mask
}
 
proc config_trig {{jtag_index_2 2} {trig_1 0000000000000}} {
device_lock -timeout 10000
proc config_trig {{jtag_index_2 2} {trig_1 00000000000000}} {
device_lock -timeout 5
device_virtual_ir_shift -instance_index $jtag_index_2 -ir_value 1 -no_captured_ir_value
set addr_trig [device_virtual_dr_shift -instance_index $jtag_index_2 -dr_value $trig_1 -length 50 -value_in_hex]
set addr_trig [device_virtual_dr_shift -instance_index $jtag_index_2 -dr_value $trig_1 -length 56 -value_in_hex]
device_unlock
return $addr_trig
}
47,7 → 57,7
proc open_jtag_device {{test_cable "USB-Blaster [USB-0]"} {test_device "@2: EP2SGX90 (0x020E30DD)"}} {
open_device -hardware_name $test_cable -device_name $test_device
# Retrieve device id code.
device_lock -timeout 10000
device_lock -timeout 5
device_ir_shift -ir_value 6 -no_captured_ir_value
set idcode "0x[device_dr_shift -length 32 -value_in_hex]"
device_unlock
96,12 → 106,11
$log insert end "Selected Device: $test_device\n"
set jtagIdCode [open_jtag_device $test_cable $test_device]
$log insert end "Device ID code : $jtagIdCode\n"
updateAddrConfig
reset_fifo 0
query_usedw 0
}
 
proc inclusiveAddrConfig {} {
proc updateAddrConfig {} {
global address_span1
global address_span2
global address_span3
110,14 → 119,6
global address_span6
global address_span7
global address_span8
for {set i 1} {$i<=8} {incr i} {
set mask [format "%1X" [expr $i-1]]
append mask [set address_span$i]
config_addr 1 $mask
}
}
 
proc exclusiveAddrConfig {} {
global address_span9
global address_span10
global address_span11
126,14 → 127,33
global address_span14
global address_span15
global address_span16
for {set i 9} {$i<=16} {incr i} {
set mask [format "%1X" [expr $i-1]]
global address_span_en1
global address_span_en2
global address_span_en3
global address_span_en4
global address_span_en5
global address_span_en6
global address_span_en7
global address_span_en8
global address_span_en9
global address_span_en10
global address_span_en11
global address_span_en12
global address_span_en13
global address_span_en14
global address_span_en15
global address_span_en16
global addr_wren
global addr_rden
for {set i 1} {$i<=16} {incr i} {
set mask [format "%1X" [expr $i-1]]
append mask [format "%1X" [expr $addr_wren*8+$addr_rden*4+[set address_span_en$i]]]
append mask [set address_span$i]
config_addr 1 $mask
}
}
 
proc updateAddrConfig {} {
proc initAddrConfig {} {
global log
global address_span1
global address_span2
159,46 → 179,36
}
}
 
proc enableTrigger {} {
proc updateTrigger {{trigCmd 0}} {
global triggerAddr
global triggerData
# enable but stop triggering
set triggerValue 2
global trig_wren
global trig_rden
global trig_aden
global trig_daen
set triggerValue [format "%1X" [expr $trig_aden*8+$trig_daen*4+0]]
append triggerValue [format "%1X" [expr $trig_wren*8+$trig_rden*4+$trigCmd]]
append triggerValue $triggerAddr
append triggerValue $triggerData
config_trig 2 $triggerValue
}
 
proc disableTrigger {} {
global triggerAddr
global triggerData
# disable and stop triggering
set triggerValue 0
append triggerValue $triggerAddr
append triggerValue $triggerData
config_trig 2 $triggerValue
}
 
proc startTrigger {} {
global triggerAddr
global triggerData
# enable and start triggering
set triggerValue 3
append triggerValue $triggerAddr
append triggerValue $triggerData
config_trig 2 $triggerValue
global trig_wren
global trig_rden
global trig_aden
global trig_daen
set trigEnable [expr $trig_wren+$trig_rden+$trig_aden+$trig_daen]
if {$trigEnable>0} {
updateTrigger 2
reset_fifo 0
query_usedw 0
updateTrigger 3
} else {
updateTrigger 0
}
}
 
proc stopTrigger {} {
global triggerAddr
global triggerData
# enable and stop triggering
set triggerValue 2
append triggerValue $triggerAddr
append triggerValue $triggerData
config_trig 2 $triggerValue
}
 
proc reset_fifo_ptr {} {
reset_fifo 0
query_usedw 0
214,7 → 224,18
$log insert end "\n****************************************\n"
for {set i 0} {$i<$fifoUsedw} {incr i} {
set fifoContent [read_fifo 0]
$log insert end "wr [string range $fifoContent 0 3] [string range $fifoContent 4 11]\n"
set ok_trig [expr [format "%d" 0x[string index $fifoContent 0]]/2]
set wr_cptr [expr [format "%d" 0x[string index $fifoContent 0]]%2]
set ad_cptr [string range $fifoContent 1 4]
set da_cptr [string range $fifoContent 5 12]
if $ok_trig {
$log insert end "@@@@@@@@@@@@@@@@@@@@\n"
}
if $wr_cptr {
$log insert end "wr $ad_cptr $da_cptr\n"
} else {
$log insert end "rd $ad_cptr $da_cptr\n"
}
}
query_usedw 0
}
236,90 → 257,138
 
# set the main window
toplevel .console
wm title .console "Virtual JTAG: uP transaction monitor"
wm title .console "www.OpenCores.org: uP Transaction Monitor"
pack propagate .console true
 
# set the JTAG utility
# set the www.OpenCores.org logo
frame .console.fig -bg white
pack .console.fig -expand true -fill both
image create photo logo -format gif -file "../common/OpenCores.gif"
label .console.fig.logo -image logo -bg white
pack .console.fig.logo
 
button .console.fig.scan -text {Scan JTAG Chain} -command {scan_chain}
button .console.fig.select -text {Select JTAG Device :} -command {select_device $cableNum $deviceNum}
button .console.fig.deselect -text {DeSelect JTAG Device} -command {close_jtag_device}
label .console.fig.cable -text {Cable No.}
label .console.fig.devic -text {Device No.}
entry .console.fig.cable_num -textvariable cableNum -width 2
entry .console.fig.devic_num -textvariable deviceNum -width 2
pack .console.fig.scan .console.fig.select \
.console.fig.cable .console.fig.cable_num \
.console.fig.devic .console.fig.devic_num \
.console.fig.deselect \
-side left -ipadx 10
# set the JTAG utility
frame .console.jtag -relief groove -borderwidth 5
pack .console.jtag
button .console.jtag.scan -text {Scan JTAG Chain} -command {scan_chain}
button .console.jtag.select -text {Select JTAG Device :} -command {select_device $cableNum $deviceNum}
button .console.jtag.deselect -text {DeSelect JTAG Device} -command {close_jtag_device}
label .console.jtag.cable -text {Cable @}
label .console.jtag.devic -text {Device @}
entry .console.jtag.cable_num -textvariable cableNum -width 5
entry .console.jtag.devic_num -textvariable deviceNum -width 5
pack .console.jtag.scan .console.jtag.select \
.console.jtag.cable .console.jtag.cable_num \
.console.jtag.devic .console.jtag.devic_num \
.console.jtag.deselect \
-side left -ipadx 0
 
# set the inclusive address entries
frame .console.f1 -relief groove -borderwidth 5
pack .console.f1
entry .console.f1.address_span1 -textvariable address_span1 -width 5
entry .console.f1.address_span2 -textvariable address_span2 -width 5
entry .console.f1.address_span3 -textvariable address_span3 -width 5
entry .console.f1.address_span4 -textvariable address_span4 -width 5
entry .console.f1.address_span5 -textvariable address_span5 -width 5
entry .console.f1.address_span6 -textvariable address_span6 -width 5
entry .console.f1.address_span7 -textvariable address_span7 -width 5
entry .console.f1.address_span8 -textvariable address_span8 -width 5
button .console.f1.config -text {Included Address Filter} -command {inclusiveAddrConfig}
pack .console.f1.address_span1 .console.f1.address_span2 .console.f1.address_span3 .console.f1.address_span4 \
.console.f1.address_span5 .console.f1.address_span6 .console.f1.address_span7 .console.f1.address_span8 \
.console.f1.config -side left -ipadx 10
label .console.f1.incl_addr -text {Inclusive Addr:}
entry .console.f1.address_span1 -textvariable address_span1 -width 8
entry .console.f1.address_span2 -textvariable address_span2 -width 8
entry .console.f1.address_span3 -textvariable address_span3 -width 8
entry .console.f1.address_span4 -textvariable address_span4 -width 8
entry .console.f1.address_span5 -textvariable address_span5 -width 8
entry .console.f1.address_span6 -textvariable address_span6 -width 8
entry .console.f1.address_span7 -textvariable address_span7 -width 8
entry .console.f1.address_span8 -textvariable address_span8 -width 8
checkbutton .console.f1.address_span_en1 -variable address_span_en1
checkbutton .console.f1.address_span_en2 -variable address_span_en2
checkbutton .console.f1.address_span_en3 -variable address_span_en3
checkbutton .console.f1.address_span_en4 -variable address_span_en4
checkbutton .console.f1.address_span_en5 -variable address_span_en5
checkbutton .console.f1.address_span_en6 -variable address_span_en6
checkbutton .console.f1.address_span_en7 -variable address_span_en7
checkbutton .console.f1.address_span_en8 -variable address_span_en8
pack .console.f1.incl_addr \
.console.f1.address_span_en1 .console.f1.address_span1 \
.console.f1.address_span_en2 .console.f1.address_span2 \
.console.f1.address_span_en3 .console.f1.address_span3 \
.console.f1.address_span_en4 .console.f1.address_span4 \
.console.f1.address_span_en5 .console.f1.address_span5 \
.console.f1.address_span_en6 .console.f1.address_span6 \
.console.f1.address_span_en7 .console.f1.address_span7 \
.console.f1.address_span_en8 .console.f1.address_span8 \
-side left -ipadx 0
 
# set the exclusive address entries
frame .console.f2 -relief groove -borderwidth 5
pack .console.f2
entry .console.f2.address_span9 -textvariable address_span9 -width 5
entry .console.f2.address_span10 -textvariable address_span10 -width 5
entry .console.f2.address_span11 -textvariable address_span11 -width 5
entry .console.f2.address_span12 -textvariable address_span12 -width 5
entry .console.f2.address_span13 -textvariable address_span13 -width 5
entry .console.f2.address_span14 -textvariable address_span14 -width 5
entry .console.f2.address_span15 -textvariable address_span15 -width 5
entry .console.f2.address_span16 -textvariable address_span16 -width 5
button .console.f2.config -text {Excluded Address Filter} -command {exclusiveAddrConfig}
pack .console.f2.address_span9 .console.f2.address_span10 .console.f2.address_span11 .console.f2.address_span12 \
.console.f2.address_span13 .console.f2.address_span14 .console.f2.address_span15 .console.f2.address_span16 \
.console.f2.config -side left -ipadx 10
label .console.f2.excl_addr -text {Exclusive Addr:}
entry .console.f2.address_span9 -textvariable address_span9 -width 8
entry .console.f2.address_span10 -textvariable address_span10 -width 8
entry .console.f2.address_span11 -textvariable address_span11 -width 8
entry .console.f2.address_span12 -textvariable address_span12 -width 8
entry .console.f2.address_span13 -textvariable address_span13 -width 8
entry .console.f2.address_span14 -textvariable address_span14 -width 8
entry .console.f2.address_span15 -textvariable address_span15 -width 8
entry .console.f2.address_span16 -textvariable address_span16 -width 8
checkbutton .console.f2.address_span_en9 -variable address_span_en9
checkbutton .console.f2.address_span_en10 -variable address_span_en10
checkbutton .console.f2.address_span_en11 -variable address_span_en11
checkbutton .console.f2.address_span_en12 -variable address_span_en12
checkbutton .console.f2.address_span_en13 -variable address_span_en13
checkbutton .console.f2.address_span_en14 -variable address_span_en14
checkbutton .console.f2.address_span_en15 -variable address_span_en15
checkbutton .console.f2.address_span_en16 -variable address_span_en16
pack .console.f2.excl_addr \
.console.f2.address_span_en9 .console.f2.address_span9 \
.console.f2.address_span_en10 .console.f2.address_span10 \
.console.f2.address_span_en11 .console.f2.address_span11 \
.console.f2.address_span_en12 .console.f2.address_span12 \
.console.f2.address_span_en13 .console.f2.address_span13 \
.console.f2.address_span_en14 .console.f2.address_span14 \
.console.f2.address_span_en15 .console.f2.address_span15 \
.console.f2.address_span_en16 .console.f2.address_span16 \
-side left -ipadx 0
 
initAddrConfig
 
# set the address configuration buttons
frame .console.addr_cnfg -relief groove -borderwidth 5
pack .console.addr_cnfg
checkbutton .console.addr_cnfg.wren -text {WR} -variable addr_wren
checkbutton .console.addr_cnfg.rden -text {RD} -variable addr_rden
button .console.addr_cnfg.config -text {Apply Address Filter} -command {updateAddrConfig}
pack .console.addr_cnfg.wren .console.addr_cnfg.rden .console.addr_cnfg.config \
-side left -ipadx 0
 
# set the transaction trigger controls
frame .console.f3 -relief groove -borderwidth 5
pack .console.f3
button .console.f3.enabletrig -text {Enable Trigger} -command {enableTrigger}
button .console.f3.disabletrig -text {Disable Trigger} -command {disableTrigger}
button .console.f3.starttrig -text {Start Trigger} -command {startTrigger}
button .console.f3.stoptrig -text {Stop Trigger} -command {stopTrigger}
entry .console.f3.trigvalue_addr -textvar triggerAddr -width 2
frame .console.trig -relief groove -borderwidth 5
pack .console.trig
button .console.trig.starttrig -text {Apply Trigger Condition} -command {startTrigger}
entry .console.trig.trigvalue_addr -textvar triggerAddr -width 4
set triggerAddr ffff
entry .console.f3.trigvalue_data -textvar triggerData -width 6
entry .console.trig.trigvalue_data -textvar triggerData -width 8
set triggerData a5a5a5a5
label .console.f3.trigaddr -text {@Address :}
label .console.f3.trigdata -text {@Data :}
pack .console.f3.enabletrig .console.f3.starttrig .console.f3.trigaddr .console.f3.trigvalue_addr \
.console.f3.trigdata .console.f3.trigvalue_data .console.f3.stoptrig .console.f3.disabletrig \
-side left -ipadx 8
checkbutton .console.trig.trigaddr -text {@Addr:} -variable trig_aden
checkbutton .console.trig.trigdata -text {@Data:} -variable trig_daen
checkbutton .console.trig.wren -text {@WR} -variable trig_wren
checkbutton .console.trig.rden -text {@RD} -variable trig_rden
pack .console.trig.wren .console.trig.rden \
.console.trig.trigaddr .console.trig.trigvalue_addr \
.console.trig.trigdata .console.trig.trigvalue_data \
.console.trig.starttrig \
-side left -ipadx 0
 
# set the control buttons
frame .console.f0 -relief groove -borderwidth 5
pack .console.f0
button .console.f0.reset -text {Reset FIFO} -command {reset_fifo_ptr}
button .console.f0.loop -text {Query Used Word} -command {query_fifo_usedw}
label .console.f0.usedw -textvariable fifoUsedw -relief sunken
button .console.f0.read -text {Read FIFO} -command {read_fifo_content}
button .console.f0.clear -text {Clear Log} -command {clear_log}
button .console.f0.quit -text {Quit} -command {quit}
pack .console.f0.reset .console.f0.loop .console.f0.usedw .console.f0.read .console.f0.clear .console.f0.quit \
-side left -ipadx 10
frame .console.fifo -relief groove -borderwidth 5
pack .console.fifo
button .console.fifo.reset -text {Reset FIFO} -command {reset_fifo_ptr}
button .console.fifo.loop -text {Query Used Word} -command {query_fifo_usedw}
label .console.fifo.usedw -textvariable fifoUsedw -relief sunken -width 4
button .console.fifo.read -text {Read FIFO} -command {read_fifo_content}
button .console.fifo.clear -text {Clear Log} -command {clear_log}
button .console.fifo.quit -text {Quit} -command {quit}
pack .console.fifo.reset .console.fifo.loop .console.fifo.usedw .console.fifo.read .console.fifo.clear .console.fifo.quit \
-side left -ipadx 0
 
# set the log window
frame .console.log -relief groove -borderwidth 5
set log [text .console.log.text -width 80 -height 40 \
set log [text .console.log.text -width 80 -height 25 \
-borderwidth 2 -relief sunken -setgrid true \
-yscrollcommand {.console.log.scroll set}]
scrollbar .console.log.scroll -command {.console.log.text yview}
/cmd/common/OpenCores.gif Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/cmd/common/OpenCores.gif
cmd/common/OpenCores.gif Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: doc/Revision History.txt =================================================================== --- doc/Revision History.txt (nonexistent) +++ doc/Revision History.txt (revision 6) @@ -0,0 +1,7 @@ + +1.0 Code base as published on EDN. + +2.0 Code base for 2.x development. Added pipelined bus access capture support. + +2.1 Added new features: 1. Multiple address filter selection; 2. Read access capture support; 3. Full trigger condition support; 4. Updated GUI; 5. Updated wrapper example with glitch filter and stable address/data capture. +

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