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/trunk/vhdl_src/wrapper.vhd
0,0 → 1,367
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity edge_sobel_wrapper is
generic (
data_width : integer := 8
);
Port ( clk : in STD_LOGIC;
rstn : in STD_LOGIC;
fsync_in : in STD_LOGIC;
pdata_in : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
fsync_out : out STD_LOGIC;
pdata_out : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end entity edge_sobel_wrapper;
 
architecture Structural of edge_sobel_wrapper is
 
constant GRAD_WIDTH : integer := 32;
constant GDIR_WIDTH : integer := 2;
constant NO_OF_COLS : integer := 640;
constant NO_OF_ROWS : integer := 480;
constant ROW_BITS : integer := 9;
constant COL_BITS : integer := 10;
 
signal RowsCounter_r, RowsCounter_x : STD_LOGIC_VECTOR(ROW_BITS-1 downto 0);
signal ColsCounter_r, ColsCounter_x : STD_LOGIC_VECTOR(COL_BITS-1 downto 0);
 
signal pdata_1_1 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal pdata_2_1 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal pdata_3_1 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal pdata_4_1 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal pdata_5_1 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal pdata_6_1 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal pdata_7_1 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal pdata_8_1 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal pdata_9_1 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal fsync_o_1 : std_logic;
--
signal Xdata_o_2 : std_logic_vector(GRAD_WIDTH-1 downto 0);
signal Ydata_o_2 : std_logic_vector(GRAD_WIDTH-1 downto 0);
signal fsync_o_2 : std_logic;
--
signal pdata_1_3x : std_logic_vector(GRAD_WIDTH-1 downto 0);
signal pdata_2_3x : std_logic_vector(GRAD_WIDTH-1 downto 0);
signal pdata_3_3x : std_logic_vector(GRAD_WIDTH-1 downto 0);
signal pdata_4_3x : std_logic_vector(GRAD_WIDTH-1 downto 0);
signal pdata_5_3x : std_logic_vector(GRAD_WIDTH-1 downto 0);
signal pdata_6_3x : std_logic_vector(GRAD_WIDTH-1 downto 0);
signal pdata_7_3x : std_logic_vector(GRAD_WIDTH-1 downto 0);
signal pdata_8_3x : std_logic_vector(GRAD_WIDTH-1 downto 0);
signal pdata_9_3x : std_logic_vector(GRAD_WIDTH-1 downto 0);
--
signal pdata_1_3y : std_logic_vector(GRAD_WIDTH-1 downto 0);
signal pdata_2_3y : std_logic_vector(GRAD_WIDTH-1 downto 0);
signal pdata_3_3y : std_logic_vector(GRAD_WIDTH-1 downto 0);
signal pdata_4_3y : std_logic_vector(GRAD_WIDTH-1 downto 0);
signal pdata_5_3y : std_logic_vector(GRAD_WIDTH-1 downto 0);
signal pdata_6_3y : std_logic_vector(GRAD_WIDTH-1 downto 0);
signal pdata_7_3y : std_logic_vector(GRAD_WIDTH-1 downto 0);
signal pdata_8_3y : std_logic_vector(GRAD_WIDTH-1 downto 0);
signal pdata_9_3y : std_logic_vector(GRAD_WIDTH-1 downto 0);
signal fsync_o_3 : std_logic;
--
signal Mdata_o_4 : std_logic_vector(GRAD_WIDTH-1-16 downto 0);
signal Ddata_o_4 : std_logic_vector(1 downto 0);
signal fsync_o_4 : std_logic;
--
signal pdata_1_5 : std_logic_vector(GRAD_WIDTH-1-16 downto 0);
signal pdata_2_5 : std_logic_vector(GRAD_WIDTH-1-16 downto 0);
signal pdata_3_5 : std_logic_vector(GRAD_WIDTH-1-16 downto 0);
signal pdata_4_5 : std_logic_vector(GRAD_WIDTH-1-16 downto 0);
signal pdata_5_5 : std_logic_vector(GRAD_WIDTH-1-16 downto 0);
signal pdata_6_5 : std_logic_vector(GRAD_WIDTH-1-16 downto 0);
signal pdata_7_5 : std_logic_vector(GRAD_WIDTH-1-16 downto 0);
signal pdata_8_5 : std_logic_vector(GRAD_WIDTH-1-16 downto 0);
signal pdata_9_5 : std_logic_vector(GRAD_WIDTH-1-16 downto 0);
signal dData_o_5 : std_logic_vector(1 downto 0);
signal fsync_o_5 : std_logic;
--
signal fsync_o_6 : std_logic;
signal pdata_o_6 : std_logic_vector(DATA_WIDTH-1 downto 0);
--
signal counter_x : std_logic_vector(18 downto 0);
signal counter_r : std_logic_vector(18 downto 0);
signal counter1_x : std_logic_vector(15 downto 0);
signal counter1_r : std_logic_vector(15 downto 0);
signal fsync_temp : std_logic;
signal fsync_out_a : std_logic;
signal tail_x : std_logic;
signal tail_r : std_logic;
--
constant LATENCY : integer := 5+5+5+3+(5*NO_OF_COLS)+7+2;
signal fsync_store : std_logic_vector(LATENCY - 1 downto 0); -- clock cycles delay to compensate for latency
 
begin
 
CacheSystem : entity work.CacheSystem
generic map (
DATA_WIDTH => DATA_WIDTH,
WINDOW_SIZE => 9,
ROW_BITS => 9,
COL_BITS => 10,
NO_OF_ROWS => NO_OF_ROWS,
NO_OF_COLS => NO_OF_COLS
)
port map(
clk => clk,
fsync_in => fsync_out_a,
pdata_in => pdata_in,
--fsync_out => fsync_o_1,
pdata_out1 => pdata_1_1,
pdata_out2 => pdata_2_1,
pdata_out3 => pdata_3_1,
pdata_out4 => pdata_4_1,
pdata_out5 => pdata_5_1,
pdata_out6 => pdata_6_1,
pdata_out7 => pdata_7_1,
pdata_out8 => pdata_8_1,
pdata_out9 => pdata_9_1
);
filterH: entity work.filterH
generic map (
DATA_WIDTH => DATA_WIDTH,
GRAD_WIDTH => GRAD_WIDTH
)
port map(
clk => clk,
fsync => fsync_out_a,
pData1 => pData_1_1,
pData2 => pData_2_1,
pData3 => pData_3_1,
pData4 => pData_4_1,
pData5 => pData_5_1,
pData6 => pData_6_1,
pData7 => pData_7_1,
pData8 => pData_8_1,
pData9 => pData_9_1,
--fsync_o => fsync_o_2,
Xdata_o => Xdata_o_2, -- x gradient partial filtering product
Ydata_o => Ydata_o_2 -- y gradient partial filtering product
);
-- rowbuffer
CacheSystem2 : entity work.CacheSystem2
generic map (
DATA_WIDTH => GRAD_WIDTH,
WINDOW_SIZE =>9,
ROW_BITS => ROW_BITS,
COL_BITS => COL_BITS,
NO_OF_ROWS => NO_OF_ROWS,
NO_OF_COLS => NO_OF_COLS
)
port map(
clk => clk,
fsync_in => fsync_out_a,
Xdata_in => Xdata_o_2,
Ydata_in => Ydata_o_2,
--fsync_out => fsync_o_3,
--
pdata_out1x => pdata_1_3x,
pdata_out2x => pdata_2_3x,
pdata_out3x => pdata_3_3x,
pdata_out4x => pdata_4_3x,
pdata_out5x => pdata_5_3x,
pdata_out6x => pdata_6_3x,
pdata_out7x => pdata_7_3x,
pdata_out8x => pdata_8_3x,
pdata_out9x => pdata_9_3x,
--
pdata_out1y => pdata_1_3y,
pdata_out2y => pdata_2_3y,
pdata_out3y => pdata_3_3y,
pdata_out4y => pdata_4_3y,
pdata_out5y => pdata_5_3y,
pdata_out6y => pdata_6_3y,
pdata_out7y => pdata_7_3y,
pdata_out8y => pdata_8_3y,
pdata_out9y => pdata_9_3y
);
 
filterV: entity work.filterV
generic map (
DATA_WIDTH => GRAD_WIDTH,
GRAD_WIDTH => GRAD_WIDTH
)
port map(
clk => clk,
fsync => fsync_out_a,
pData1x => pData_1_3x,
pData2x => pData_2_3x,
pData3x => pData_3_3x,
pData4x => pData_4_3x,
pData5x => pData_5_3x,
pData6x => pData_6_3x,
pData7x => pData_7_3x,
pData8x => pData_8_3x,
pData9x => pData_9_3x,
--
pData1y => pData_1_3y,
pData2y => pData_2_3y,
pData3y => pData_3_3y,
pData4y => pData_4_3y,
pData5y => pData_5_3y,
pData6y => pData_6_3y,
pData7y => pData_7_3y,
pData8y => pData_8_3y,
pData9y => pData_9_3y,
--fsync_o => fsync_o_4,
Mdata_o => Mdata_o_4,
Ddata_o => Ddata_o_4
);
CacheSystem3 : entity work.CacheSystem3
generic map (
DATA_WIDTH => GRAD_WIDTH-16,
WINDOW_SIZE => 3,
ROW_BITS => ROW_BITS,
COL_BITS => COL_BITS,
NO_OF_ROWS => NO_OF_ROWS,
NO_OF_COLS => NO_OF_COLS
)
port map(
clk => clk,
fsync_in => fsync_out_a,
mdata_in => mdata_o_4,
dData_in => Ddata_o_4,
--fsync_out => fsync_o_5,
pdata_out1 => pdata_1_5,
pdata_out2 => pdata_2_5,
pdata_out3 => pdata_3_5,
pdata_out4 => pdata_4_5,
pdata_out5 => pdata_5_5,
pdata_out6 => pdata_6_5,
pdata_out7 => pdata_7_5,
pdata_out8 => pdata_8_5,
pdata_out9 => pdata_9_5,
dData_out => dData_o_5
);
 
krnl2: entity work.nmax_supp
generic map (
DATA_WIDTH => DATA_WIDTH,
GRAD_WIDTH => GRAD_WIDTH-16
)
port map(
clk => clk,
fsync => fsync_out_a,
mData1 => pData_1_5,
mData2 => pData_2_5,
mData3 => pData_3_5,
mData4 => pData_4_5,
mData5 => pData_5_5,
mData6 => pData_6_5,
mData7 => pData_7_5,
mData8 => pData_8_5,
mData9 => pData_9_5,
dData => dData_o_5,
--fsync_o => fsync_o_6,
pdata_o => pdata_o_6
);
--fsync_out <= fsync_o_4;
--pdata_out <= mdata_o_4(7 downto 0);
pdata_out <= pdata_o_6;-- when RowsCounter_r > std_logic_vector(to_unsigned(3, RowsCounter_r'length)) AND
-- ColsCounter_r > std_logic_vector(to_unsigned(3, ColsCounter_r'length)) AND
-- RowsCounter_r < std_logic_vector(to_unsigned(NO_OF_ROWS-4, RowsCounter_r'length)) AND
-- ColsCounter_r < std_logic_vector(to_unsigned(NO_OF_COLS-4, ColsCounter_r'length)) ELSE
-- (others => '0');
 
-- fsync_out <= fsync_temp;
fsync_out_a <= fsync_temp OR fsync_in;
fsync_out <= fsync_temp;
 
---- fsync_temp is the delayed version (LATENCY) of fsync_out
-- fsync_delayer : process (clk)
-- begin
-- if rising_edge(clk) then
-- fsync_store <= fsync_store(LATENCY-2 downto 0) & fsync_in;
-- fsync_temp <= fsync_store(LATENCY-1);
-- end if;
-- end process fsync_delayer;
-- if (fsync_in) = '1' AND counter_r /= std_logic_vector(to_unsigned(5+5+5+3+(5*NO_OF_COLS)+7+2, counter_r'length)) then
f_sync_delayer1: process (counter_r, counter1_r, fsync_in, tail_r) -- nmaxsupp
begin
counter_x <= counter_r;
counter1_x <= counter1_r;
tail_x <= tail_r;
if fsync_in = '1' then
if counter_r /= std_logic_vector(to_unsigned(NO_OF_ROWS*NO_OF_COLS-1, counter_r'length)) then
counter_x <= counter_r + 1;
else
counter_x <= (others => '0');
tail_x <= '1';
end if;
end if;
if tail_r = '0' then
if counter_r < std_logic_vector(to_unsigned(5+5+5+4+(5*NO_OF_COLS)+7+2, counter_r'length)) then
fsync_temp <= '0';
else
fsync_temp <= fsync_in;
end if;
else
fsync_temp <= '1';
end if;
if tail_r ='1' then
if counter1_r < std_logic_vector(to_unsigned(5+5+5+3+(5*NO_OF_COLS)+7+2, counter_r'length)) then
counter1_x <= counter1_r + 1;
else
counter1_x <= (others => '0');
tail_x <= '0';
end if;
end if;
end process f_sync_delayer1;
update_reg : process (clk)
begin
if rising_edge(clk) then
if rstn = '0' then
RowsCounter_r <= (others => '0');
ColsCounter_r <= (others => '0');
counter_r <= (others => '0');
counter1_r <= (others => '0');
tail_r <= '0';
else
RowsCounter_r <= RowsCounter_x;
ColsCounter_r <= ColsCounter_x;
counter_r <= counter_x;
counter1_r <= counter1_x;
tail_r <= tail_x;
end if;
end if;
end process update_reg;
counter : process (fsync_o_6, ColsCounter_r, RowsCounter_r, fsync_in)
begin
RowsCounter_x <= RowsCounter_r;
ColsCounter_x <= ColsCounter_r;
--if rising_edge(clk) then
if(fsync_in = '1') then
if RowsCounter_r = std_logic_vector(to_unsigned(NO_OF_ROWS-1, ROW_BITS)) AND
ColsCounter_r = std_logic_vector(to_unsigned(NO_OF_COLS-1, COL_BITS)) then
ColsCounter_x <= (others => '0');
RowsCounter_x <= (others => '0');
elsif RowsCounter_r /= std_logic_vector(to_unsigned(NO_OF_ROWS-1, ROW_BITS)) AND
ColsCounter_r = std_logic_vector(to_unsigned(NO_OF_COLS-1, COL_BITS)) then
ColsCounter_x <= ColsCounter_r + 1;
RowsCounter_x <= RowsCounter_r;
else
ColsCounter_x <= ColsCounter_r + 1;
RowsCounter_x <= RowsCounter_r;
end if;
end if;
--end if;
end process counter;
end Structural;
/trunk/vhdl_src/kernel.vhd
0,0 → 1,230
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.math_real."log2";
 
entity filterH is
generic (
DATA_WIDTH : integer := 8;
GRAD_WIDTH : integer := 16
);
port (
clk : in std_logic;
fsync : in std_logic;
pData1 : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
pData2 : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
pData3 : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
pData4 : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
pData5 : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
pData6 : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
pData7 : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
pData8 : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
pData9 : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
--fsync_o : out std_logic;
Xdata_o : out std_logic_vector(GRAD_WIDTH-1 downto 0); -- X gradient
Ydata_o : out std_logic_vector(GRAD_WIDTH-1 downto 0) -- Y gradient
);
end entity filterH;
architecture Behavioral of filterH is
 
signal p1x,p2x,p3x,p4x,p5x,p6x,p7x,p8x,p9x : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
signal p1xa,p2xa,p3xa,p4xa,p5xa,p6xa,p7xa,p8xa,p9xa : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
signal p1xb,p2xb,p3xb,p4xb,p5xb,p6xb,p7xb,p8xb,p9xb : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
 
signal p1y,p2y,p3y,p4y,p5y,p6y,p7y,p8y,p9y : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
signal p1ya,p2ya,p3ya,p4ya,p5ya,p6ya,p7ya,p8ya,p9ya : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
signal p1yb,p2yb,p3yb,p4yb,p5yb,p6yb,p7yb,p8yb,p9yb : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
 
signal sX1,sX2,sY1,sY2 : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
signal SX1c, sX2c, sYc : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
signal sX1a,sX1b,sX2a,sX2b : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
signal sY1a,sY1b,sY2a,sY2b : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
 
begin
 
--1----------------------------------------
prod1 : process (clk) -- for the frame sync signal
begin
if rising_edge(clk) then
if fsync ='1' then
-------------------------------------------------------------------GRAD_X_hardwired multipliers
 
p1xa <=((GRAD_WIDTH-1 downto (8+7) => '0') & pData1 & (7-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+4) => '0') & pData1 & (4-1 downto 0 => '0'));
p1xb <=((GRAD_WIDTH-1 downto (8+0) => '0') & pData1);
p2xa <=((GRAD_WIDTH-1 downto (8+8) => '0') & pData2 & (8-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+7) => '0') & pData2 & (7-1 downto 0 => '0'));
p2xb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData2 & (5-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+4) => '0') & pData2 & (4-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+2) => '0') & pData2 & (2-1 downto 0 => '0'));
p3xa <=((GRAD_WIDTH-1 downto (8+9) => '0') & pData3 & (9-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+7) => '0') & pData3 & (7-1 downto 0 => '0'));
p3xb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData3 & (5-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+3) => '0') & pData3 & (3-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+1) => '0') & pData3 & (1-1 downto 0 => '0'));
p4xa <=((GRAD_WIDTH-1 downto (8+8) => '0') & pData4 & (8-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+6) => '0') & pData4 & (6-1 downto 0 => '0'));
p4xb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData4 & (5-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+4) => '0') & pData4 & (4-1 downto 0 => '0'));
p5xb <= (others => '0');
p5xa <= (others => '0');
--p5xa <= x"000000" & pData5;--------DEBUG-------------
p6xa <=((GRAD_WIDTH-1 downto (8+8) => '0') & pData6 & (8-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+6) => '0') & pData6 & (6-1 downto 0 => '0'));
p6xb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData6 & (5-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+4) => '0') & pData6 & (4-1 downto 0 => '0'));
p7xa <=((GRAD_WIDTH-1 downto (8+9) => '0') & pData7 & (9-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+7) => '0') & pData7 & (7-1 downto 0 => '0'));
p7xb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData7 & (5-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+3) => '0') & pData7 & (3-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+1) => '0') & pData7 & (1-1 downto 0 => '0'));
p8xa <=((GRAD_WIDTH-1 downto (8+8) => '0') & pData8 & (8-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+7) => '0') & pData8 & (7-1 downto 0 => '0'));
p8xb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData8 & (5-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+4) => '0') & pData8 & (4-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+2) => '0') & pData8 & (2-1 downto 0 => '0'));
p9xa <=((GRAD_WIDTH-1 downto (8+7) => '0') & pData9 & (7-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+4) => '0') & pData9 & (4-1 downto 0 => '0'));
p9xb <=((GRAD_WIDTH-1 downto (8+0) => '0') & pData9);
-------------------------------------------------------------------GRAD_Y_hardwired multipliers
 
p1ya <=((GRAD_WIDTH-1 downto (8+4) => '0') & pData1 & (4-1 downto 0 => '0'));
p1yb <=(others=>'0');
p2ya <=((GRAD_WIDTH-1 downto (8+6) => '0') & pData2 & (6-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+4) => '0') & pData2 & (4-1 downto 0 => '0'));
p2yb <=((GRAD_WIDTH-1 downto (8+2) => '0') & pData2 & (2-1 downto 0 => '0'));
p3ya <=((GRAD_WIDTH-1 downto (8+8) => '0') & pData3 & (8-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+5) => '0') & pData3 & (5-1 downto 0 => '0'));
p3yb <=((GRAD_WIDTH-1 downto (8+3) => '0') & pData3 & (3-1 downto 0 => '0'));
p4ya <=((GRAD_WIDTH-1 downto (8+9) => '0') & pData4 & (9-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+6) => '0') & pData4 & (6-1 downto 0 => '0'));
p4yb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData4 & (5-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+4) => '0') & pData4 & (4-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+1) => '0') & pData4 & (1-1 downto 0 => '0'));
p5ya <=((GRAD_WIDTH-1 downto (8+9) => '0') & pData5 & (9-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+8) => '0') & pData5 & (8-1 downto 0 => '0'));
p5yb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData5 & (5-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+2) => '0') & pData5 & (2-1 downto 0 => '0'));
 
p6ya <=((GRAD_WIDTH-1 downto (8+9) => '0') & pData6 & (9-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+6) => '0') & pData6 & (6-1 downto 0 => '0'));
p6yb <=((GRAD_WIDTH-1 downto (8+5) => '0') & pData6 & (5-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+4) => '0') & pData6 & (4-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+1) => '0') & pData6 & (1-1 downto 0 => '0'));
 
p7ya <=((GRAD_WIDTH-1 downto (8+8) => '0') & pData7 & (8-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+5) => '0') & pData7 & (5-1 downto 0 => '0'));
p7yb <=((GRAD_WIDTH-1 downto (8+3) => '0') & pData7 & (3-1 downto 0 => '0'));
 
p8ya <=((GRAD_WIDTH-1 downto (8+6) => '0') & pData8 & (6-1 downto 0 => '0')) +
((GRAD_WIDTH-1 downto (8+4) => '0') & pData8 & (4-1 downto 0 => '0'));
p8yb <=((GRAD_WIDTH-1 downto (8+2) => '0') & pData8 & (2-1 downto 0 => '0'));
 
p9ya <=((GRAD_WIDTH-1 downto (8+4) => '0') & pData9 & (4-1 downto 0 => '0'));
p9yb <=(others=>'0');
end if;
end if;
end process prod1;
--2----------------------------------------
prod2 : process (clk) -- for the frame sync signal
begin
if rising_edge(clk) then
if fsync ='1' then
p1x <= p1xa + p1xb;
p2x <= p2xa + p2xb;
p3x <= p3xa + p3xb;
p4x <= p4xa + p4xb;
p5x <= p5xa + p5xb;
p6x <= p6xa + p6xb;
p7x <= p7xa + p7xb;
p8x <= p8xa + p8xb;
p9x <= p9xa + p9xb;
--
p1y <= p1ya + p1yb;
p2y <= p2ya + p2yb;
p3y <= p3ya + p3yb;
p4y <= p4ya + p4yb;
p5y <= p5ya + p5yb;
p6y <= p6ya + p6yb;
p7y <= p7ya + p7yb;
p8y <= p8ya + p8yb;
p9y <= p9ya + p9yb;
end if;
end if;
end process prod2;
 
--3----------------------------------------
sum1 : process (clk)
begin
if rising_edge(clk) then
if fsync ='1' then
--sX1a <= p5x; ----DEBUG-----------
sX1a <= p1x+p2x;
sX1b <= p3x+p4x;
sX2a <= p6x+p7x;
sX2b <= p8x+p9x;
sY1a <= p1y+p2y;
sY1b <= p3y+p4y;
sY2a <= p5y+p6y;
sY2b <= p7y+p8y+p9y;
end if;
end if;
end process sum1;
 
--4----------------------------------------
sum2 : process (clk)
begin
if rising_edge(clk) then
if fsync ='1' then
--sX1 <= sX1a; ----DEBUG-----------
sX1 <= sX1a+sX1b;
sX2 <= sX2a+sX2b;
sY1 <= sY1a+sY1b;
sY2 <= sY2a+sY2b;
end if;
end if;
end process sum2;
 
--5----------------------------------------
sum3 : process (clk)
begin
if rising_edge(clk) then
if fsync ='1' then
sX2c <= (not sX2) + 1;
sX1c <= sX1;
sYc <= sY1+sY2;
end if;
end if;
end process sum3;
 
--6----------------------------------------
outp : process (clk)
begin
if rising_edge(clk) then
if fsync ='1' then
--Xdata_o <= sX1c; -------DEBUG-------
Xdata_o <= sX1c+sX2c;
Ydata_o <= (not sYc) + 1;
end if;
end if;
end process outp;
 
end Behavioral;
/trunk/vhdl_src/top.vhd
0,0 → 1,44
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
entity top is
port(
clk : in std_logic;
rstn : in std_logic;
data_in : in std_logic_vector(7 downto 0);
fsync_in : in std_logic;
fsync_out : out std_logic;
data_out : out std_logic_vector(7 downto 0)
);
end entity top;
 
architecture structure of top is
signal data_in_r : std_logic_vector(7 downto 0);
signal fsync_in_r : std_logic;
begin
 
-- registering inputs
reg : process(clk)
begin
if rising_edge(clk) then
data_in_r <= data_in;
fsync_in_r <= fsync_in;
end if;
end process reg;
edge : entity work.edge_sobel_wrapper
port map (
clk => clk,
rstn => rstn,
pdata_in => data_in_r,
fsync_in => fsync_in_r,
fsync_out => fsync_out,
pdata_out => data_out
);
 
end architecture structure;
/trunk/vhdl_src/FIFOLineBuffer.vhd
0,0 → 1,66
PACKAGE TYPES IS
subtype SMALL_INTEGER is INTEGER range 0 to 639;
END PACKAGE;
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.TYPES.all;
 
entity FIFOLineBuffer is
generic (
DATA_WIDTH : integer := 8;
NO_OF_COLS : integer := 640 );
port(
clk : in std_logic;
fsync : in std_logic;
pdata_in : in std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out : buffer std_logic_vector(DATA_WIDTH -1 downto 0)
);
end FIFOLineBuffer;
 
architecture Behavioral of FIFOLineBuffer is
 
type ram_type is array (NO_OF_COLS downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal ram_array : ram_type; -- := (others => "00000000");
--signal clk2 : std_logic;
signal rIndex : SMALL_INTEGER := 1;
signal wIndex : SMALL_INTEGER := 0;
 
begin
 
-- clk <= NOT clk;
p : process(clk)
begin
if clk'event and clk='1' then
if fsync = '1' then
pdata_out <= ram_array(rIndex);
if rIndex < NO_OF_COLS-1 then
rIndex <= rIndex+1;
else
rIndex <= 0;
end if;
end if;
end if;
end process;
-- writing into the memory
 
p2 : process (clk)
begin
if clk'event and clk='1' then
if fsync = '1' then
ram_array(wIndex) <= pdata_in;
if wIndex < NO_OF_COLS-1 then
wIndex <= wIndex+1;
else
wIndex <= 0;
end if;
--else
--wIndex <= 0;
end if; -- fsync
end if; -- clk2
end process p2;
end Behavioral;
/trunk/vhdl_src/krnl2.vhd
0,0 → 1,152
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;
 
 
entity nmax_supp is
generic (
DATA_WIDTH : integer := 8;
GRAD_WIDTH : integer := 16
);
port (
clk : in std_logic;
fsync : in std_logic;
mData1 : in STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
mData2 : in STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
mData3 : in STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
mData4 : in STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
mData5 : in STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
mData6 : in STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
mData7 : in STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
mData8 : in STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
mData9 : in STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
dData : in STD_LOGIC_VECTOR(1 downto 0);
--fsync_o : out std_logic;
pdata_o : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end entity nmax_supp;
 
-- WARNING UNSIGNED STD_LOGIC_VECTOR in this KERNEL
architecture Behavioral of nmax_supp is
 
constant UP_THRES : integer := 50;
 
signal cdata1,cdata2,cdata3 : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
--signal fsync_ia : STD_LOGIC;
 
--constant LATENCY : integer := 1;
--signal fsync_store : std_logic; -- clock cycles delay to compensate for latency
 
begin
 
-- latency_comp: process (clk) -- for the frame sync signal
-- begin
-- if rising_edge(clk) then
-- fsync_store <= fsync_i;
-- fsync_o <= fsync_store;
-- end if;
-- end process latency_comp;
--1
--------------------------------------------------------
-- nonmax_supp: process (clk) -- nmaxsupp
-- begin
-- if rising_edge(clk) then
-- --fsync_o <= fsync_i;
-- --pdata_o <= mdata7(GRAD_WIDTH-1 downto GRAD_WIDTH-8); ------------DEBUG-------------
-- if dData = "00" then -- VERTICAL gradient
--
-- -- The gradient is from top to bottom. This means the edge is from left to right.
-- -- So you check gradient magnitudes against the pixels right above and below.
-- if mData5 >= mData2 AND mData5 > mData8 then
-- --pdata_o <= x"3F";
-- pdata_o <= mData5(GRAD_WIDTH-1 downto GRAD_WIDTH-8);
-- else
-- pdata_o <= (others => '0');
-- end if;
-- elsif dData = "01" then -- HORIZONTAL gradient
-- -- The gradient is horizontal. So the edge is vertical.
-- -- So you check the pixels to the left and right.
-- if mData5 >= mData4 AND mData5 > mData6 then
-- pdata_o <= mData5(GRAD_WIDTH-1 downto GRAD_WIDTH-8);
-- --pdata_o <= x"7E";--mData5;
-- else
-- pdata_o <= (others => '0');
-- end if;
-- elsif dData = "11" then -- 45R gradient
--
-- -- from the bottom left corner to the up right corner.
-- -- This means the edge lies from the bottom right corner to up left
-- if mData5 > mData3 AND mData5 >= mData7 then
-- pdata_o <= mData5(GRAD_WIDTH-1 downto GRAD_WIDTH-8);
-- --pdata_o <= x"BD";--mData5;
-- else
-- pdata_o <= (others => '0');
-- end if;
-- elsif dData = "10" then-- 45F gradient
--
-- -- from the top left corner to the down right corner.
-- -- This means the edge lies from the top right corner to down left
-- if mData5 >= mData1 AND mData5 > mData9 then
-- pdata_o <= mData5(GRAD_WIDTH-1 downto GRAD_WIDTH-8);
-- --pdata_o <= x"FF";--mData5;
-- else
-- pdata_o <= (others => '0');
-- end if;
-- end if;
-- end if;
-- end process nonmax_supp;
--1
--------------------------------------------------------
nonmax_supp1: process (clk) -- nmaxsupp
begin
if rising_edge(clk) then
if fsync ='1' then
--fsync_ia <= fsync_i;
cData2 <= mData5;
-- pdata_o <= mdata5; ------------DEBUG-------------
if dData = "00" then -- VERTICAL gradient
cData1 <= mData2;
cData3 <= mData8;
elsif dData = "01" then -- HORIZONTAL
cData1 <= mData4;
cData3 <= mData6;
elsif dData = "11" then -- 45R gradient
cData1 <= mData7;
cData3 <= mData3;
else -- 45F gradient
cData1 <= mData1;
cData3 <= mData9;
end if;
end if;
end if;
end process nonmax_supp1;
--2
--------------------------------------------------------
nonmax_supp2: process (clk) -- nmaxsupp
begin
if rising_edge(clk) then
if fsync ='1' then
-- pdata_o <= cData2(GRAD_WIDTH-1 downto 8); ---------DEBUG
if cData2 >= cData1 AND cData2 > cData3 then
if cData2(GRAD_WIDTH-1 downto 8) > x"000A" then -- THRESHOLD
pdata_o <= (others => '1');
else
pdata_o <= cData2(GRAD_WIDTH-1-2 downto 8-2); -- or set weak edges to 0 if preferred (others => '0');
end if;
else
pdata_o <= (others => '0');
end if;
end if;
end if;
end process nonmax_supp2;
 
 
 
end Behavioral;
/trunk/vhdl_src/buffer.vhd
0,0 → 1,164
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity CacheSystem is
generic (
DATA_WIDTH : integer := 8;
WINDOW_SIZE : integer := 9;
ROW_BITS : integer := 9;
COL_BITS : integer := 10;
NO_OF_ROWS : integer := 480;
NO_OF_COLS : integer := 640
);
port(
clk : in std_logic;
fsync_in : in std_logic;
pdata_in : in std_logic_vector(DATA_WIDTH -1 downto 0);
--fsync_out : out std_logic;
pdata_out1 : out std_logic_vector(DATA_WIDTH -1 downto 0);--primo pixel a sx
pdata_out2 : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out3 : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out4 : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out5 : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out6 : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out7 : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out8 : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out9 : out std_logic_vector(DATA_WIDTH -1 downto 0) -- ultimo px a destra
);
end CacheSystem;
architecture CacheSystem of CacheSystem is
 
signal cache1 : std_logic_vector((WINDOW_SIZE*DATA_WIDTH) -1 downto 0);
 
begin
--
-- fsync_out <= fsync_temp;
-- fsync_buffer <= fsync_in OR fsync_temp;
--
-- fsync_delayer : process (clk)
-- begin
-- if rising_edge(clk) then
-- fsync_store <= fsync_store(LATENCY-2 downto 0) & fsync_in;
-- fsync_temp <= fsync_store(LATENCY-1);
-- end if;
-- end process fsync_delayer;
 
-- update_reg : process (clk)
-- begin
-- if rising_edge(clk) then
-- RowsCounter_r <= RowsCounter_x;
-- ColsCounter_r <= ColsCounter_x;
-- end if;
-- end process update_reg;
--
-- counter : process (clk, fsync_temp)
-- begin
-- --RowsCounter_x <= RowsCounter_r;
-- --ColsCounter_x <= ColsCounter_r;
-- if(fsync_temp = '0') then
-- RowsCounter_x <= (others => '0');
-- ColsCounter_x <= (others => '0');
-- elsif(clk'event and clk = '1') then
-- if ColsCounter_r /= std_logic_vector(to_unsigned(NO_OF_COLS-1, COL_BITS)) then
-- ColsCounter_x <= ColsCounter_r + 1;
-- else
-- RowsCounter_x <= RowsCounter_r + 1;
-- ColsCounter_x <= (others => '0');
-- end if;
-- end if;
-- end process counter;
ShiftingProcess : process (clk, fsync_in)
begin
 
if rising_edge(clk) then
if fsync_in = '1' then
cache1(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto 0) <= cache1(((WINDOW_SIZE-0)*DATA_WIDTH-1) downto (DATA_WIDTH));
cache1(((WINDOW_SIZE-0)*DATA_WIDTH-1) downto ((WINDOW_SIZE-1)*DATA_WIDTH)) <= pdata_in;
end if; -- clk
end if;
end process ShiftingProcess;
EmittingProcess : process (clk)
begin
if rising_edge(clk) then
if fsync_in = '1' then
--
-- -- 1 top left
-- if ColsCounter_r = "0000000000" OR ColsCounter_r = std_logic_vector(to_unsigned(NO_OF_COLS-1, COL_BITS)) then
-- pdata_out9 <= cache1(((WINDOW_SIZE-0)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-1)*DATA_WIDTH));
-- pdata_out8 <= cache1(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-2)*DATA_WIDTH));
-- pdata_out7 <= cache1(((WINDOW_SIZE-2)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-3)*DATA_WIDTH));
-- pdata_out6 <= cache1(((WINDOW_SIZE-3)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-4)*DATA_WIDTH));
-- pdata_out5 <= cache1(((WINDOW_SIZE-4)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-5)*DATA_WIDTH));
-- pdata_out4 <= cache1(((WINDOW_SIZE-4)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-5)*DATA_WIDTH));
-- pdata_out3 <= cache1(((WINDOW_SIZE-4)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-5)*DATA_WIDTH));
-- pdata_out2 <= cache1(((WINDOW_SIZE-4)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-5)*DATA_WIDTH));
-- pdata_out1 <= cache1(((WINDOW_SIZE-4)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-5)*DATA_WIDTH));
--
-- elsif ColsCounter_r = "0000000001" OR ColsCounter_r = std_logic_vector(to_unsigned(NO_OF_COLS-2, COL_BITS)) then
-- pdata_out9 <= cache1(((WINDOW_SIZE-0)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-1)*DATA_WIDTH));
-- pdata_out8 <= cache1(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-2)*DATA_WIDTH));
-- pdata_out7 <= cache1(((WINDOW_SIZE-2)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-3)*DATA_WIDTH));
-- pdata_out6 <= cache1(((WINDOW_SIZE-3)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-4)*DATA_WIDTH));
-- pdata_out5 <= cache1(((WINDOW_SIZE-4)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-5)*DATA_WIDTH));
-- pdata_out4 <= cache1(((WINDOW_SIZE-5)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-6)*DATA_WIDTH));
-- pdata_out3 <= cache1(((WINDOW_SIZE-4)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-5)*DATA_WIDTH));
-- pdata_out2 <= cache1(((WINDOW_SIZE-4)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-5)*DATA_WIDTH));
-- pdata_out1 <= cache1(((WINDOW_SIZE-4)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-5)*DATA_WIDTH));
--
-- elsif ColsCounter_r = "0000000010" OR ColsCounter_r = std_logic_vector(to_unsigned(NO_OF_COLS-3, COL_BITS)) then
-- pdata_out9 <= cache1(((WINDOW_SIZE-0)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-1)*DATA_WIDTH));
-- pdata_out8 <= cache1(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-2)*DATA_WIDTH));
-- pdata_out7 <= cache1(((WINDOW_SIZE-2)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-3)*DATA_WIDTH));
-- pdata_out6 <= cache1(((WINDOW_SIZE-3)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-4)*DATA_WIDTH));
-- pdata_out5 <= cache1(((WINDOW_SIZE-4)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-5)*DATA_WIDTH));
-- pdata_out4 <= cache1(((WINDOW_SIZE-5)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-6)*DATA_WIDTH));
-- pdata_out3 <= cache1(((WINDOW_SIZE-6)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-7)*DATA_WIDTH));
-- pdata_out2 <= cache1(((WINDOW_SIZE-4)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-5)*DATA_WIDTH));
-- pdata_out1 <= cache1(((WINDOW_SIZE-4)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-5)*DATA_WIDTH));
--
-- elsif ColsCounter_r = "0000000011" OR ColsCounter_r = std_logic_vector(to_unsigned(NO_OF_COLS-4, COL_BITS)) then
-- pdata_out9 <= cache1(((WINDOW_SIZE-0)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-1)*DATA_WIDTH));
-- pdata_out8 <= cache1(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-2)*DATA_WIDTH));
-- pdata_out7 <= cache1(((WINDOW_SIZE-2)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-3)*DATA_WIDTH));
-- pdata_out6 <= cache1(((WINDOW_SIZE-3)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-4)*DATA_WIDTH));
-- pdata_out5 <= cache1(((WINDOW_SIZE-4)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-5)*DATA_WIDTH));
-- pdata_out4 <= cache1(((WINDOW_SIZE-5)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-6)*DATA_WIDTH));
-- pdata_out3 <= cache1(((WINDOW_SIZE-6)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-7)*DATA_WIDTH));
-- pdata_out2 <= cache1(((WINDOW_SIZE-7)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-8)*DATA_WIDTH));
-- pdata_out1 <= cache1(((WINDOW_SIZE-4)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-5)*DATA_WIDTH));
--
-- else
pdata_out9 <= cache1(((WINDOW_SIZE-0)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-1)*DATA_WIDTH));
pdata_out8 <= cache1(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-2)*DATA_WIDTH));
pdata_out7 <= cache1(((WINDOW_SIZE-2)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-3)*DATA_WIDTH));
pdata_out6 <= cache1(((WINDOW_SIZE-3)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-4)*DATA_WIDTH));
pdata_out5 <= cache1(((WINDOW_SIZE-4)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-5)*DATA_WIDTH));
pdata_out4 <= cache1(((WINDOW_SIZE-5)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-6)*DATA_WIDTH));
pdata_out3 <= cache1(((WINDOW_SIZE-6)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-7)*DATA_WIDTH));
pdata_out2 <= cache1(((WINDOW_SIZE-7)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-8)*DATA_WIDTH));
pdata_out1 <= cache1(((WINDOW_SIZE-8)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-9)*DATA_WIDTH));
end if;
--
-- end if; -- RowsCounter_r and ColsCounter_r
-- else
-- pdata_out1 <= (others =>'0');
-- pdata_out2 <= (others =>'0');
-- pdata_out3 <= (others =>'0');
-- pdata_out4 <= (others =>'0');
-- pdata_out5 <= (others =>'0');
-- pdata_out6 <= (others =>'0');
-- pdata_out7 <= (others =>'0');
-- pdata_out8 <= (others =>'0');
-- pdata_out9 <= (others =>'0');
-- end if; --rsync_temp
end if; -- clk
end process EmittingProcess;
end CacheSystem;
/trunk/vhdl_src/CacheSystem2.vhd
0,0 → 1,354
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
entity CacheSystem2 is
generic (
DATA_WIDTH : integer := 8;
WINDOW_SIZE : integer := 3;
ROW_BITS : integer := 9;
COL_BITS : integer := 10;
NO_OF_ROWS : integer := 480;
NO_OF_COLS : integer := 640
);
port(
clk : in std_logic;
fsync_in : in std_logic;
Xdata_in : in std_logic_vector(DATA_WIDTH -1 downto 0);
Ydata_in : in std_logic_vector(DATA_WIDTH -1 downto 0);
--fsync_out : out std_logic;
pdata_out1x : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out2x : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out3x : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out4x : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out5x : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out6x : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out7x : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out8x : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out9x : out std_logic_vector(DATA_WIDTH -1 downto 0);
--
pdata_out1y : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out2y : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out3y : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out4y : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out5y : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out6y : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out7y : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out8y : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out9y : out std_logic_vector(DATA_WIDTH -1 downto 0)
);
end CacheSystem2;
architecture CacheSystem2 of CacheSystem2 is
 
--COMPONENT Counter is
-- generic (
-- n : POSITIVE
-- );
-- port (
-- clk : in STD_LOGIC;
-- en : in STD_LOGIC;
-- reset : in STD_LOGIC; -- Active Low
-- output : out STD_LOGIC_VECTOR(n-1 downto 0)
-- );
--end COMPONENT;
 
COMPONENT nineFiFOLineBuffer is
generic (
DATA_WIDTH : integer := DATA_WIDTH;
NO_OF_COLS : integer := 640
);
port(
clk : in std_logic;
fsync : in std_logic;
pdata_in : in std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out1 : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out2 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out3 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out4 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out5 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out6 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out7 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out8 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out9 : buffer std_logic_vector(DATA_WIDTH -1 downto 0)
);
end COMPONENT;
 
--COMPONENT SyncSignalsDelayer
-- generic (
-- ROW_BITS : integer := 9;
-- COL_BITS : integer := 10;
-- NO_OF_ROWS : integer := 480;
-- NO_OF_COLS : integer := 640
-- );
-- port(
-- clk : IN std_logic;
-- fsync_in : IN std_logic;
-- fsync_out : OUT std_logic
-- );
--end COMPONENT;
 
--signal RowsCounter_r, RowsCounter_x : STD_LOGIC_VECTOR(ROW_BITS-1 downto 0);
--signal ColsCounter_r, ColsCounter_x : STD_LOGIC_VECTOR(COL_BITS-1 downto 0);
--
signal dout1x : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout2x : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout3x : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout4x : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout5x : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout6x : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout7x : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout8x : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout9x : std_logic_vector(DATA_WIDTH -1 downto 0);
--
signal dout1y : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout2y : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout3y : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout4y : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout5y : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout6y : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout7y : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout8y : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout9y : std_logic_vector(DATA_WIDTH -1 downto 0);
--
--signal fsync_temp : std_logic;
--
--constant LATENCY : integer := NO_OF_COLS*4;
--signal fsync_store : std_logic_vector(LATENCY - 1 downto 0); -- clock cycles delay to compensate for latency
 
 
begin
 
--fsync_out <= fsync_temp;
-- fsync_delayer : FIFOLineBuffer
-- generic map (
-- DATA_WIDTH => 1,
-- NO_OF_COLS => NO_OF_COLS*4
-- )
-- port map(
-- clk => clk,
-- fsync => fsync_buffer,
-- pdata_in(0) => fsync_in,
-- pdata_out(0) => fsync_temp
-- );
 
-- fsync_delayer : process (clk)
-- begin
-- if rising_edge(clk) then
-- fsync_store <= fsync_store(LATENCY-2 downto 0) & fsync_in;
-- fsync_temp <= fsync_store(LATENCY-1);
-- end if;
-- end process fsync_delayer;
--
-- fsync_buffer <= fsync_in OR fsync_temp;
 
nineLineBufferX: nineFiFOLineBuffer
generic map (
DATA_WIDTH => DATA_WIDTH,
NO_OF_COLS => NO_OF_COLS
)
port map (
clk => clk,
fsync => fsync_in,
pdata_in => xdata_in,
pdata_out1 => dout1x,
pdata_out2 => dout2x,
pdata_out3 => dout3x,
pdata_out4 => dout4x,
pdata_out5 => dout5x,
pdata_out6 => dout6x,
pdata_out7 => dout7x,
pdata_out8 => dout8x,
pdata_out9 => dout9x
);
nineLineBufferY: nineFiFOLineBuffer
generic map (
DATA_WIDTH => DATA_WIDTH,
NO_OF_COLS => NO_OF_COLS
)
port map (
clk => clk,
fsync => fsync_in,
pdata_in => ydata_in,
pdata_out1 => dout1y,
pdata_out2 => dout2y,
pdata_out3 => dout3y,
pdata_out4 => dout4y,
pdata_out5 => dout5y,
pdata_out6 => dout6y,
pdata_out7 => dout7y,
pdata_out8 => dout8y,
pdata_out9 => dout9y
);
-- update_reg : process (clk)
-- begin
-- if rising_edge(clk) then
-- RowsCounter_r <= RowsCounter_x;
-- ColsCounter_r <= ColsCounter_x;
-- end if;
-- end process update_reg;
--
-- counter : process (clk, fsync_temp)
-- begin
-- --RowsCounter_x <= RowsCounter_r;
-- --ColsCounter_x <= ColsCounter_r;
-- if(clk'event and clk = '1') then
-- if(fsync_temp = '0') then
-- RowsCounter_x <= (others => '0');
-- ColsCounter_x <= (others => '0');
-- elsif ColsCounter_r /= std_logic_vector(to_unsigned(NO_OF_COLS-1, COL_BITS)) then
-- ColsCounter_x <= ColsCounter_r + 1;
-- else
-- RowsCounter_x <= RowsCounter_r + 1;
-- ColsCounter_x <= (others => '0');
-- end if;
-- end if;
-- end process counter;
EmittingProcess : process (clk)
begin
 
if rising_edge(clk) then
if fsync_in = '1' then
 
 
-- if RowsCounter_r = "0000000000" OR RowsCounter_r = std_logic_vector(to_unsigned(NO_OF_ROWS-1, ROW_BITS)) then
-- pdata_out1x <= dout5x;
-- pdata_out2x <= dout5x;
-- pdata_out3x <= dout5x;
-- pdata_out4x <= dout5x;
-- pdata_out5x <= dout5x;
-- pdata_out6x <= dout4x;
-- pdata_out7x <= dout3x;
-- pdata_out8x <= dout2x;
-- pdata_out9x <= dout1x;
-- --
-- pdata_out1y <= dout5y;
-- pdata_out2y <= dout5y;
-- pdata_out3y <= dout5y;
-- pdata_out4y <= dout5y;
-- pdata_out5y <= dout5y;
-- pdata_out6y <= dout4y;
-- pdata_out7y <= dout3y;
-- pdata_out8y <= dout2y;
-- pdata_out9y <= dout1y;
--
-- elsif RowsCounter_r = "0000000001" OR RowsCounter_r = std_logic_vector(to_unsigned(NO_OF_ROWS-2, ROW_BITS)) then
-- pdata_out1x <= dout6x;
-- pdata_out2x <= dout6x;
-- pdata_out3x <= dout6x;
-- pdata_out4x <= dout6x;
-- pdata_out5x <= dout5x;
-- pdata_out6x <= dout4x;
-- pdata_out7x <= dout3x;
-- pdata_out8x <= dout2x;
-- pdata_out9x <= dout1x;
-- --
-- pdata_out1y <= dout6y;
-- pdata_out2y <= dout6y;
-- pdata_out3y <= dout6y;
-- pdata_out4y <= dout6y;
-- pdata_out5y <= dout5y;
-- pdata_out6y <= dout4y;
-- pdata_out7y <= dout3y;
-- pdata_out8y <= dout2y;
-- pdata_out9y <= dout1y;
--
-- elsif RowsCounter_r = "0000000010" OR RowsCounter_r = std_logic_vector(to_unsigned(NO_OF_ROWS-3, ROW_BITS)) then
-- pdata_out1x <= dout7x;
-- pdata_out2x <= dout7x;
-- pdata_out3x <= dout7x;
-- pdata_out4x <= dout6x;
-- pdata_out5x <= dout5x;
-- pdata_out6x <= dout4x;
-- pdata_out7x <= dout3x;
-- pdata_out8x <= dout2x;
-- pdata_out9x <= dout1x;
-- --
-- pdata_out1y <= dout7y;
-- pdata_out2y <= dout7y;
-- pdata_out3y <= dout7y;
-- pdata_out4y <= dout6y;
-- pdata_out5y <= dout5y;
-- pdata_out6y <= dout4y;
-- pdata_out7y <= dout3y;
-- pdata_out8y <= dout2y;
-- pdata_out9y <= dout1y;
--
-- elsif RowsCounter_r = "0000000011" OR RowsCounter_r = std_logic_vector(to_unsigned(NO_OF_ROWS-4, ROW_BITS)) then
-- pdata_out1x <= dout8x;
-- pdata_out2x <= dout8x;
-- pdata_out3x <= dout7x;
-- pdata_out4x <= dout6x;
-- pdata_out5x <= dout5x;
-- pdata_out6x <= dout4x;
-- pdata_out7x <= dout3x;
-- pdata_out8x <= dout2x;
-- pdata_out9x <= dout1x;
-- --
-- pdata_out1y <= dout8y;
-- pdata_out2y <= dout8y;
-- pdata_out3y <= dout7y;
-- pdata_out4y <= dout6y;
-- pdata_out5y <= dout5y;
-- pdata_out6y <= dout4y;
-- pdata_out7y <= dout3y;
-- pdata_out8y <= dout2y;
-- pdata_out9y <= dout1y;
--
-- else
pdata_out1x <= dout9x;
pdata_out2x <= dout8x;
pdata_out3x <= dout7x;
pdata_out4x <= dout6x;
pdata_out5x <= dout5x;
pdata_out6x <= dout4x;
pdata_out7x <= dout3x;
pdata_out8x <= dout2x;
pdata_out9x <= dout1x;
--
pdata_out1y <= dout9y;
pdata_out2y <= dout8y;
pdata_out3y <= dout7y;
pdata_out4y <= dout6y;
pdata_out5y <= dout5y;
pdata_out6y <= dout4y;
pdata_out7y <= dout3y;
pdata_out8y <= dout2y;
pdata_out9y <= dout1y;
end if;
 
--else
-- pdata_out1x <= (others =>'0');
-- pdata_out2x <= (others =>'0');
-- pdata_out3x <= (others =>'0');
-- pdata_out4x <= (others =>'0');
-- pdata_out5x <= (others =>'0');
-- pdata_out6x <= (others =>'0');
-- pdata_out7x <= (others =>'0');
-- pdata_out8x <= (others =>'0');
-- pdata_out9x <= (others =>'0');
-- --
-- pdata_out1y <= (others =>'0');
-- pdata_out2y <= (others =>'0');
-- pdata_out3y <= (others =>'0');
-- pdata_out4y <= (others =>'0');
-- pdata_out5y <= (others =>'0');
-- pdata_out6y <= (others =>'0');
-- pdata_out7y <= (others =>'0');
-- pdata_out8y <= (others =>'0');
-- pdata_out9y <= (others =>'0');
end if; --clk
--end if; --rsync_temp
end process EmittingProcess;
end CacheSystem2;
/trunk/vhdl_src/CacheSystem3.vhd
0,0 → 1,303
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
entity CacheSystem3 is
generic (
DATA_WIDTH : integer := 8;
WINDOW_SIZE : integer := 3;
ROW_BITS : integer := 9;
COL_BITS : integer := 10;
NO_OF_ROWS : integer := 480;
NO_OF_COLS : integer := 640
);
port(
clk : in std_logic;
fsync_in : in std_logic;
mData_in : in std_logic_vector(DATA_WIDTH -1 downto 0);
dData_in : in std_logic_vector(1 downto 0);
--fsync_out : out std_logic;
pdata_out1 : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out2 : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out3 : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out4 : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out5 : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out6 : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out7 : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out8 : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out9 : out std_logic_vector(DATA_WIDTH -1 downto 0);
dData_out : out std_logic_vector(1 downto 0)
);
end CacheSystem3;
architecture CacheSystem3 of CacheSystem3 is
 
 
COMPONENT DoubleFiFOLineBuffer is
generic (
DATA_WIDTH : integer := 8;
NO_OF_COLS : integer := 640
);
port(
clk : in std_logic;
fsync : in std_logic;
pdata_in : in std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out1 : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out2 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out3 : buffer std_logic_vector(DATA_WIDTH -1 downto 0)
);
end COMPONENT;
 
component FIFOLineBuffer is
generic (
DATA_WIDTH : integer := 8;
NO_OF_COLS : integer := 640
);
port(
clk : in std_logic;
fsync : in std_logic;
pdata_in : in std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out : buffer std_logic_vector(DATA_WIDTH -1 downto 0));
end component;
 
--signal RowsCounter_r, RowsCounter_x : STD_LOGIC_VECTOR(ROW_BITS-1 downto 0);
--signal ColsCounter_r, ColsCounter_x : STD_LOGIC_VECTOR(COL_BITS-1 downto 0);
 
signal dout1 : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout2 : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout3 : std_logic_vector(DATA_WIDTH -1 downto 0);
 
signal dData_temp : std_logic_vector(1 downto 0);
 
 
signal cache1 : std_logic_vector((WINDOW_SIZE*DATA_WIDTH) -1 downto 0);
signal cache2 : std_logic_vector((WINDOW_SIZE*DATA_WIDTH) -1 downto 0);
signal cache3 : std_logic_vector((WINDOW_SIZE*DATA_WIDTH) -1 downto 0);
 
--constant LATENCY : integer := NO_OF_COLS+2;
--signal fsync_store : std_logic_vector(LATENCY - 1 downto 0); -- clock cycles delay to compensate for latency
 
begin
 
--
-- fsync_out <= fsync_temp;
-- --fsync_buffer <= fsync_in OR fsync_temp;
--
-- fsync_delayer : process (clk)
-- begin
-- if rising_edge(clk) then
-- fsync_store <= fsync_store(LATENCY-2 downto 0) & fsync_in;
-- fsync_temp <= fsync_store(LATENCY-1);
-- end if;
-- end process fsync_delayer;
DoubleLineBufferMag: DoubleFiFOLineBuffer
generic map (
DATA_WIDTH => DATA_WIDTH,
NO_OF_COLS => NO_OF_COLS
)
port map (
clk => clk,
fsync => fsync_in,--fsync_buffer,
pdata_in => mdata_in,
pdata_out1 => dout1,
pdata_out2 => dout2,
pdata_out3 => dout3
);
dDataBuffer1 : FIFOLineBuffer
generic map (
DATA_WIDTH => 2,
NO_OF_COLS => NO_OF_COLS+2+1
)
port map(clk, fsync_in, dData_in, dData_temp);
 
-- update_reg : process (clk)
-- begin
-- if(clk'event and clk = '1') then
-- RowsCounter_r <= RowsCounter_x;
-- ColsCounter_r <= ColsCounter_x;
-- end if;
-- end process update_reg;
--
-- counter : process (clk, fsync_temp)
-- begin
-- --RowsCounter_x <= RowsCounter_r;
-- --ColsCounter_x <= ColsCounter_r;
-- if(clk'event and clk = '1') then
-- if(fsync_temp = '0') then
-- RowsCounter_x <= (others => '0');
-- ColsCounter_x <= (others => '0');
-- elsif ColsCounter_r /= std_logic_vector(to_unsigned(NO_OF_COLS-1, COL_BITS)) then
-- ColsCounter_x <= ColsCounter_r + 1;
-- else
-- RowsCounter_x <= RowsCounter_r + 1;
-- ColsCounter_x <= (others => '0');
-- end if;
-- end if;
-- end process counter;
--fsync_out <= fsync_temp;
ShiftingProcess : process (clk, fsync_in)
begin
 
if rising_edge(clk) then
if fsync_in = '1' then
-- the pixel in the middle part is copied into the low part
cache1(DATA_WIDTH-1 downto 0) <= cache1(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto ((WINDOW_SIZE-2)*DATA_WIDTH));
cache2(DATA_WIDTH-1 downto 0) <= cache2(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto ((WINDOW_SIZE-2)*DATA_WIDTH));
cache3(DATA_WIDTH-1 downto 0) <= cache3(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto ((WINDOW_SIZE-2)*DATA_WIDTH));
-- the pixel in the high part is copied into the middle part
cache1(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto ((WINDOW_SIZE-2)*DATA_WIDTH) ) <= cache1((WINDOW_SIZE*DATA_WIDTH)-1 downto ((WINDOW_SIZE-1)*DATA_WIDTH));
cache2(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto ((WINDOW_SIZE-2)*DATA_WIDTH) ) <= cache2((WINDOW_SIZE*DATA_WIDTH)-1 downto ((WINDOW_SIZE-1)*DATA_WIDTH));
cache3(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto ((WINDOW_SIZE-2)*DATA_WIDTH) ) <= cache3((WINDOW_SIZE*DATA_WIDTH)-1 downto ((WINDOW_SIZE-1)*DATA_WIDTH));
-- the output of the ram is put in the high part of the variable
cache1((WINDOW_SIZE*DATA_WIDTH)-1 downto ((WINDOW_SIZE-1)*DATA_WIDTH)) <= dout1;
cache2((WINDOW_SIZE*DATA_WIDTH)-1 downto ((WINDOW_SIZE-1)*DATA_WIDTH)) <= dout2;
cache3((WINDOW_SIZE*DATA_WIDTH)-1 downto ((WINDOW_SIZE-1)*DATA_WIDTH)) <= dout3;
end if; -- clk
end if;
end process ShiftingProcess;
EmittingProcess : process (clk)
begin
if rising_edge(clk) then
if fsync_in = '1' then
dData_out <= dData_temp;
-- 1 top left
-- if RowsCounter_r = "000000000" and ColsCounter_r = "0000000000" then
-- pdata_out1 <= (others => '0');
-- pdata_out2 <= (others => '0');
-- pdata_out3 <= (others => '0');
-- pdata_out4 <= (others => '0');
-- pdata_out5 <= cache2(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto ((WINDOW_SIZE-2)*DATA_WIDTH));
-- pdata_out6 <= cache2(((WINDOW_SIZE)*DATA_WIDTH-1) downto ((WINDOW_SIZE-1)*DATA_WIDTH));
-- pdata_out7 <= (others => '0');
-- pdata_out8 <= cache1(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto ((WINDOW_SIZE-2)*DATA_WIDTH));
-- pdata_out9 <= cache1(((WINDOW_SIZE)*DATA_WIDTH-1) downto ((WINDOW_SIZE-1)*DATA_WIDTH));
--
-- -- counter2>0 and counter2<639 (2) top
-- elsif RowsCounter_r = "000000000" and ColsCounter_r > "0000000000" and ColsCounter_r < "1001111111" then
-- pdata_out1 <= (others => '0');
-- pdata_out2 <= (others => '0');
-- pdata_out3 <= (others => '0');
-- pdata_out4 <= cache2((DATA_WIDTH-1) downto 0);
-- pdata_out5 <= cache2(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto ((WINDOW_SIZE-2)*DATA_WIDTH));
-- pdata_out6 <= cache2(((WINDOW_SIZE)*DATA_WIDTH-1) downto ((WINDOW_SIZE-1)*DATA_WIDTH));
-- pdata_out7 <= cache1((DATA_WIDTH-1) downto 0);
-- pdata_out8 <= cache1(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto ((WINDOW_SIZE-2)*DATA_WIDTH));
-- pdata_out9 <= cache1(((WINDOW_SIZE)*DATA_WIDTH-1) downto ((WINDOW_SIZE-1)*DATA_WIDTH));
-- -- counter2=639
--
-- --3 top right
-- elsif RowsCounter_r = "000000000" and ColsCounter_r = "1001111111" then
-- pdata_out1 <= (others => '0');
-- pdata_out2 <= (others => '0');
-- pdata_out3 <= (others => '0');
-- pdata_out4 <= cache2((DATA_WIDTH-1) downto 0 );
-- pdata_out5 <= cache2(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto DATA_WIDTH);
-- pdata_out6 <= (others => '0');
-- pdata_out7 <= cache1((DATA_WIDTH-1) downto 0 );
-- pdata_out8 <= cache1(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto DATA_WIDTH);
-- pdata_out9 <= (others => '0');
--
-- -- row>0 and row<479 (4)left
-- elsif RowsCounter_r > "000000000" and RowsCounter_r < "111011111" and ColsCounter_r = "0000000000" then
-- pdata_out1 <= (others => '0');
-- pdata_out2 <= cache3(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto DATA_WIDTH );
-- pdata_out3 <= cache3(((WINDOW_SIZE)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-1)*DATA_WIDTH) );
-- pdata_out4 <= (others => '0');
-- pdata_out5 <= cache2(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto DATA_WIDTH );
-- pdata_out6 <= cache2(((WINDOW_SIZE)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-1)*DATA_WIDTH) );
-- pdata_out7 <= (others => '0');
-- pdata_out8 <= cache1(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto DATA_WIDTH );
-- pdata_out9 <= cache1(((WINDOW_SIZE)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-1)*DATA_WIDTH) );
--
-- -- row>0 and row<479 and counter2>0 and counter2=639 (6) right
-- elsif RowsCounter_r > "000000000" and RowsCounter_r < "111011111" and ColsCounter_r = "1001111111" then
-- pdata_out1 <= cache3((DATA_WIDTH - 1) downto 0 );
-- pdata_out2 <= cache3(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto DATA_WIDTH );
-- pdata_out3 <= (others => '0');
-- pdata_out4 <= cache2((DATA_WIDTH - 1) downto 0 );
-- pdata_out5 <= cache2(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto DATA_WIDTH );
-- pdata_out6 <= (others => '0');
-- pdata_out7 <= cache1((DATA_WIDTH - 1) downto 0 );
-- pdata_out8 <= cache1(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto DATA_WIDTH );
-- pdata_out9 <= (others => '0');
--
-- -- row=479 and counter2=0 (7) bottom left
-- elsif RowsCounter_r="111011111" and ColsCounter_r="0000000000" then
-- pdata_out1 <= (others => '0');
-- pdata_out2 <= cache3(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto DATA_WIDTH );
-- pdata_out3 <= cache3(((WINDOW_SIZE)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-1)*DATA_WIDTH) );
-- pdata_out4 <= (others => '0');
-- pdata_out5 <= cache2(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto DATA_WIDTH );
-- pdata_out6 <= cache2(((WINDOW_SIZE)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-1)*DATA_WIDTH) );
-- pdata_out7 <= (others => '0');
-- pdata_out8 <= (others => '0');
-- pdata_out9 <= cache2(((WINDOW_SIZE)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-1)*DATA_WIDTH) ); -- 6
--
-- -- row=479 and counter2>0 and counter2<639 (8) bottom
-- elsif RowsCounter_r = "111011111" and ColsCounter_r > "0000000000" and ColsCounter_r < "1001111111" then
-- pdata_out1 <= cache3((DATA_WIDTH - 1) downto 0 );
-- pdata_out2 <= cache3(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto DATA_WIDTH );
-- pdata_out3 <= cache3(((WINDOW_SIZE)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-1)*DATA_WIDTH) );
-- pdata_out4 <= cache2((DATA_WIDTH - 1) downto 0 );
-- pdata_out5 <= cache2(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto DATA_WIDTH );
-- pdata_out6 <= cache2(((WINDOW_SIZE)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-1)*DATA_WIDTH) );
-- pdata_out7 <= (others => '0');
-- pdata_out8 <= (others => '0');
-- pdata_out9 <= (others => '0');
--
-- -- row=479 and counter2=639 (9) bottom right
-- elsif RowsCounter_r = "111011111" and ColsCounter_r = "1001111111" then
-- pdata_out1 <= cache3((DATA_WIDTH - 1) downto 0 );
-- pdata_out2 <= cache3(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto DATA_WIDTH );
-- pdata_out3 <= (others => '0');
-- pdata_out4 <= cache2((DATA_WIDTH - 1) downto 0 );
-- pdata_out5 <= cache2(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto DATA_WIDTH );
-- pdata_out6 <= (others => '0');
-- pdata_out7 <= cache2((DATA_WIDTH - 1) downto 0 ); -- 4
-- pdata_out8 <= (others => '0');
-- pdata_out9 <= (others => '0');
-- 5
-- else
pdata_out1 <= cache3((DATA_WIDTH - 1) downto 0 );
pdata_out2 <= cache3(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto (WINDOW_SIZE-2)*DATA_WIDTH );
pdata_out3 <= cache3(((WINDOW_SIZE)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-1)*DATA_WIDTH) );
pdata_out4 <= cache2((DATA_WIDTH-1) downto 0);
pdata_out5 <= cache2(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto ((WINDOW_SIZE-2)*DATA_WIDTH));
pdata_out6 <= cache2(((WINDOW_SIZE)*DATA_WIDTH-1) downto ((WINDOW_SIZE-1)*DATA_WIDTH));
pdata_out7 <= cache1((DATA_WIDTH-1) downto 0);
pdata_out8 <= cache1(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto ((WINDOW_SIZE-2)*DATA_WIDTH));
pdata_out9 <= cache1(((WINDOW_SIZE)*DATA_WIDTH-1) downto ((WINDOW_SIZE-1)*DATA_WIDTH));
 
-- end if; -- RowsCounter_r and ColsCounter_r
--else
-- dData_out <= (others =>'0');
-- pdata_out1 <= (others =>'0');
-- pdata_out2 <= (others =>'0');
-- pdata_out3 <= (others =>'0');
-- pdata_out4 <= (others =>'0');
-- pdata_out5 <= (others =>'0');
-- pdata_out6 <= (others =>'0');
-- pdata_out7 <= (others =>'0');
-- pdata_out8 <= (others =>'0');
-- pdata_out9 <= (others =>'0');
end if; --rsync_temp
end if; --clk
end process EmittingProcess;
end CacheSystem3;
/trunk/vhdl_src/filterV.vhd
0,0 → 1,306
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.math_real."log2";
 
entity filterV is
generic (
DATA_WIDTH : integer := 8;
GRAD_WIDTH : integer := 16
);
port (
clk : in std_logic;
fsync : in std_logic;
--
pData1x : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
pData2x : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
pData3x : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
pData4x : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
pData5x : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
pData6x : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
pData7x : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
pData8x : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
pData9x : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
--
pData1y : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
pData2y : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
pData3y : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
pData4y : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
pData5y : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
pData6y : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
pData7y : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
pData8y : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
pData9y : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
--
Mdata_o : out STD_LOGIC_VECTOR(GRAD_WIDTH-1-16 downto 0); -- X gradient
Ddata_o : out STD_LOGIC_VECTOR(1 downto 0) -- Y gradient
);
end entity filterV;
architecture Behavioral of filterV is
 
signal p1x,p2x,p3x,p4x,p5x,p6x,p7x,p8x,p9x : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
signal p1xa,p2xa,p3xa,p4xa,p5xa,p6xa,p7xa,p8xa,p9xa : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
signal p1xb,p2xb,p3xb,p4xb,p5xb,p6xb,p7xb,p8xb,p9xb : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
 
signal p1y,p2y,p3y,p4y,p5y,p6y,p7y,p8y,p9y : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
signal p1ya,p2ya,p3ya,p4ya,p5ya,p6ya,p7ya,p8ya,p9ya : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
signal p1yb,p2yb,p3yb,p4yb,p5yb,p6yb,p7yb,p8yb,p9yb : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
 
signal sY1,sY2,sX1,sX2 : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
signal sX1a,sX1b,sX2a,sX2b : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
signal sY1a,sY1b,sY2a,sY2b : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
signal sY1c,sY2c,sXc : STD_LOGIC_VECTOR(GRAD_WIDTH-1 downto 0);
signal Xgrad,Ygrad,XgradM,YgradM : STD_LOGIC_VECTOR(GRAD_WIDTH-1-16 downto 0);
signal XgradS,YgradS : STD_LOGIC;
 
begin
--1----------------------------------------
prod1 : process (clk) -- for the frame sync signal
begin
if rising_edge(clk) then
if fsync ='1' then
-------------------------------------------------------------------GRAD_Y_hardwired multipliers
 
p1ya <=(pData1y(GRAD_WIDTH-1) & pData1y(GRAD_WIDTH-2-7 downto 0) & (7-1 downto 0 => '0')) +
(pData1y(GRAD_WIDTH-1) & pData1y(GRAD_WIDTH-2-4 downto 0) & (4-1 downto 0 => '0'));
p1yb <=(pData1y(GRAD_WIDTH-1) & pData1y(GRAD_WIDTH-2 downto 0));
p2ya <=(pData2y(GRAD_WIDTH-1) & pData2y(GRAD_WIDTH-2-8 downto 0) & (8-1 downto 0 => '0')) +
(pData2y(GRAD_WIDTH-1) & pData2y(GRAD_WIDTH-2-7 downto 0) & (7-1 downto 0 => '0'));
p2yb <=(pData2y(GRAD_WIDTH-1) & pData2y(GRAD_WIDTH-2-5 downto 0) & (5-1 downto 0 => '0')) +
(pData2y(GRAD_WIDTH-1) & pData2y(GRAD_WIDTH-2-4 downto 0) & (4-1 downto 0 => '0')) +
(pData2y(GRAD_WIDTH-1) & pData2y(GRAD_WIDTH-2-2 downto 0) & (2-1 downto 0 => '0'));
p3ya <=(pData3y(GRAD_WIDTH-1) & pData3y(GRAD_WIDTH-2-9 downto 0) & (9-1 downto 0 => '0')) +
(pData3y(GRAD_WIDTH-1) & pData3y(GRAD_WIDTH-2-7 downto 0) & (7-1 downto 0 => '0'));
p3yb <=(pData3y(GRAD_WIDTH-1) & pData3y(GRAD_WIDTH-2-5 downto 0) & (5-1 downto 0 => '0')) +
(pData3y(GRAD_WIDTH-1) & pData3y(GRAD_WIDTH-2-3 downto 0) & (3-1 downto 0 => '0')) +
(pData3y(GRAD_WIDTH-1) & pData3y(GRAD_WIDTH-2-1 downto 0) & (1-1 downto 0 => '0'));
p4ya <=(pData4y(GRAD_WIDTH-1) & pData4y(GRAD_WIDTH-2-8 downto 0) & (8-1 downto 0 => '0')) +
(pData4y(GRAD_WIDTH-1) & pData4y(GRAD_WIDTH-2-6 downto 0) & (6-1 downto 0 => '0'));
p4yb <=(pData4y(GRAD_WIDTH-1) & pData4y(GRAD_WIDTH-2-5 downto 0) & (5-1 downto 0 => '0')) +
(pData4y(GRAD_WIDTH-1) & pData4y(GRAD_WIDTH-2-4 downto 0) & (4-1 downto 0 => '0'));
p5ya <= (others => '0');
p5yb <= (others => '0');
--p5ya <= pData5x;--------DEBUG-------------
p6ya <=(pData6y(GRAD_WIDTH-1) & pData6y(GRAD_WIDTH-2-8 downto 0) & (8-1 downto 0 => '0')) +
(pData6y(GRAD_WIDTH-1) & pData6y(GRAD_WIDTH-2-6 downto 0) & (6-1 downto 0 => '0'));
p6yb <=(pData6y(GRAD_WIDTH-1) & pData6y(GRAD_WIDTH-2-5 downto 0) & (5-1 downto 0 => '0')) +
(pData6y(GRAD_WIDTH-1) & pData6y(GRAD_WIDTH-2-4 downto 0) & (4-1 downto 0 => '0'));
p7ya <=(pData7y(GRAD_WIDTH-1) & pData7y(GRAD_WIDTH-2-9 downto 0) & (9-1 downto 0 => '0')) +
(pData7y(GRAD_WIDTH-1) & pData7y(GRAD_WIDTH-2-7 downto 0) & (7-1 downto 0 => '0'));
p7yb <=(pData7y(GRAD_WIDTH-1) & pData7y(GRAD_WIDTH-2-5 downto 0) & (5-1 downto 0 => '0')) +
(pData7y(GRAD_WIDTH-1) & pData7y(GRAD_WIDTH-2-3 downto 0) & (3-1 downto 0 => '0')) +
(pData7y(GRAD_WIDTH-1) & pData7y(GRAD_WIDTH-2-1 downto 0) & (1-1 downto 0 => '0'));
p8ya <=(pData8y(GRAD_WIDTH-1) & pData8y(GRAD_WIDTH-2-8 downto 0) & (8-1 downto 0 => '0')) +
(pData8y(GRAD_WIDTH-1) & pData8y(GRAD_WIDTH-2-7 downto 0) & (7-1 downto 0 => '0'));
p8yb <=(pData8y(GRAD_WIDTH-1) & pData8y(GRAD_WIDTH-2-5 downto 0) & (5-1 downto 0 => '0')) +
(pData8y(GRAD_WIDTH-1) & pData8y(GRAD_WIDTH-2-4 downto 0) & (4-1 downto 0 => '0')) +
(pData8y(GRAD_WIDTH-1) & pData8y(GRAD_WIDTH-2-2 downto 0) & (2-1 downto 0 => '0'));
p9ya <=(pData9y(GRAD_WIDTH-1) & pData9y(GRAD_WIDTH-2-7 downto 0) & (7-1 downto 0 => '0')) +
(pData9y(GRAD_WIDTH-1) & pData9y(GRAD_WIDTH-2-4 downto 0) & (4-1 downto 0 => '0'));
p9yb <=(pData9y(GRAD_WIDTH-1) & pData9y(GRAD_WIDTH-2 downto 0));
-------------------------------------------------------------------GRAD_X_hardwired multipliers
 
p1xa <=(pData1x(GRAD_WIDTH-1) & pData1x(GRAD_WIDTH-2-4 downto 0) & (4-1 downto 0 => '0'));
p1xb <=(others=>'0');
p2xa <=(pData2x(GRAD_WIDTH-1) & pData2x(GRAD_WIDTH-2-6 downto 0) & (6-1 downto 0 => '0')) +
(pData2x(GRAD_WIDTH-1) & pData2x(GRAD_WIDTH-2-4 downto 0) & (4-1 downto 0 => '0'));
p2xb <=(pData2x(GRAD_WIDTH-1) & pData2x(GRAD_WIDTH-2-2 downto 0) & (2-1 downto 0 => '0'));
p3xa <=(pData3x(GRAD_WIDTH-1) & pData3x(GRAD_WIDTH-2-8 downto 0) & (8-1 downto 0 => '0')) +
(pData3x(GRAD_WIDTH-1) & pData3x(GRAD_WIDTH-2-5 downto 0) & (5-1 downto 0 => '0'));
p3xb <=(pData3x(GRAD_WIDTH-1) & pData3x(GRAD_WIDTH-2-3 downto 0) & (3-1 downto 0 => '0'));
p4xa <=(pData4x(GRAD_WIDTH-1) & pData4x(GRAD_WIDTH-2-9 downto 0) & (9-1 downto 0 => '0')) +
(pData4x(GRAD_WIDTH-1) & pData4x(GRAD_WIDTH-2-6 downto 0) & (6-1 downto 0 => '0'));
p4xb <=(pData4x(GRAD_WIDTH-1) & pData4x(GRAD_WIDTH-2-5 downto 0) & (5-1 downto 0 => '0')) +
(pData4x(GRAD_WIDTH-1) & pData4x(GRAD_WIDTH-2-4 downto 0) & (4-1 downto 0 => '0')) +
(pData4x(GRAD_WIDTH-1) & pData4x(GRAD_WIDTH-2-1 downto 0) & (1-1 downto 0 => '0'));
p5xa <=(pData5x(GRAD_WIDTH-1) & pData5x(GRAD_WIDTH-2-9 downto 0) & (9-1 downto 0 => '0')) +
(pData5x(GRAD_WIDTH-1) & pData5x(GRAD_WIDTH-2-8 downto 0) & (8-1 downto 0 => '0'));
p5xb <=(pData5x(GRAD_WIDTH-1) & pData5x(GRAD_WIDTH-2-5 downto 0) & (5-1 downto 0 => '0')) +
(pData5x(GRAD_WIDTH-1) & pData5x(GRAD_WIDTH-2-2 downto 0) & (2-1 downto 0 => '0'));
 
p6xa <=(pData6x(GRAD_WIDTH-1) & pData6x(GRAD_WIDTH-2-9 downto 0) & (9-1 downto 0 => '0')) +
(pData6x(GRAD_WIDTH-1) & pData6x(GRAD_WIDTH-2-6 downto 0) & (6-1 downto 0 => '0'));
p6xb <=(pData6x(GRAD_WIDTH-1) & pData6x(GRAD_WIDTH-2-5 downto 0) & (5-1 downto 0 => '0')) +
(pData6x(GRAD_WIDTH-1) & pData6x(GRAD_WIDTH-2-4 downto 0) & (4-1 downto 0 => '0')) +
(pData6x(GRAD_WIDTH-1) & pData6x(GRAD_WIDTH-2-1 downto 0) & (1-1 downto 0 => '0'));
 
p7xa <=(pData7x(GRAD_WIDTH-1) & pData7x(GRAD_WIDTH-2-8 downto 0) & (8-1 downto 0 => '0')) +
(pData7x(GRAD_WIDTH-1) & pData7x(GRAD_WIDTH-2-5 downto 0) & (5-1 downto 0 => '0'));
p7xb <=(pData7x(GRAD_WIDTH-1) & pData7x(GRAD_WIDTH-2-3 downto 0) & (3-1 downto 0 => '0'));
 
p8xa <=(pData8x(GRAD_WIDTH-1) & pData8x(GRAD_WIDTH-2-6 downto 0) & (6-1 downto 0 => '0')) +
(pData8x(GRAD_WIDTH-1) & pData8x(GRAD_WIDTH-2-4 downto 0) & (4-1 downto 0 => '0'));
p8xb <=(pData8x(GRAD_WIDTH-1) & pData8x(GRAD_WIDTH-2-2 downto 0) & (2-1 downto 0 => '0'));
 
p9xa <= (pData9x(GRAD_WIDTH-1) & pData9x(GRAD_WIDTH-2-4 downto 0) & (4-1 downto 0 => '0'));
p9xb <=(others=>'0');
end if;
end if;
end process prod1;
--2----------------------------------------
prod2 : process (clk) -- for the frame sync signal
begin
if rising_edge(clk) then
if fsync ='1' then
p1x <= p1xa + p1xb;
p2x <= p2xa + p2xb;
p3x <= p3xa + p3xb;
p4x <= p4xa + p4xb;
p5x <= p5xa + p5xb;
p6x <= p6xa + p6xb;
p7x <= p7xa + p7xb;
p8x <= p8xa + p8xb;
p9x <= p9xa + p9xb;
--
p1y <= p1ya + p1yb;
p2y <= p2ya + p2yb;
p3y <= p3ya + p3yb;
p4y <= p4ya + p4yb;
p5y <= p5ya + p5yb;
p6y <= p6ya + p6yb;
p7y <= p7ya + p7yb;
p8y <= p8ya + p8yb;
p9y <= p9ya + p9yb;
end if;
end if;
end process prod2;
 
--3----------------------------------------
sum1 : process (clk)
begin
if rising_edge(clk) then
if fsync ='1' then
--sY1a <= p5y; ----DEBUG-----------
sY1a <= p1y+p2y;
SY1b <= p3y+p4y;
sY2a <= p6y+p7y;
sY2b <= p8y+p9y;
sX1a <= p1x+p2x;
sX1b <= p3x+p4x;
sX2a <= p5x+p6x;
sX2b <= p7x+p8x+p9x;
end if;
end if;
end process sum1;
--4----------------------------------------
sum2 : process (clk)
begin
if rising_edge(clk) then
if fsync ='1' then
--sY1 <= sY1a; ----DEBUG-----------
sY1 <= sY1a+sY1b;
sY2 <= sY2a+sY2b;
sX1 <= sX1a+sX1b;
sX2 <= sX2a+sX2b;
end if;
end if;
end process sum2;
 
--5----------------------------------------
sum3 : process (clk) -- for the frame sync signal
begin
if rising_edge(clk) then
if fsync ='1' then
sY2c <= (not sY2) + 1;
sY1c <= Sy1;
sXc <= sX1+sX2;
end if;
end if;
end process sum3;
 
--6----------------------------------------
outp : process (clk)
begin
if rising_edge(clk) then
if fsync ='1' then
--Ygrad <= sY1c(15 downto 0); -------DEBUG-------
Ygrad <= sY1c(GRAD_WIDTH-1 downto 16)+sY2c(GRAD_WIDTH-1 downto 16);
Xgrad <= (not sXc(GRAD_WIDTH-1 downto 16)) + 1;
end if;
end if;
end process outp;
--7----------------------------------------
mag : process (clk)
begin
if rising_edge(clk) then
if fsync ='1' then
if Ygrad(GRAD_WIDTH-1-16)='1' then
YgradM <= (not Ygrad) + 1;
else
YgradM <= Ygrad;
end if;
if Xgrad(GRAD_WIDTH-1-16)='1' then
XgradM <= (not Xgrad) + 1;
else
XgradM <= Xgrad;
end if;
XgradS <= Xgrad(GRAD_WIDTH-1-16);
YgradS <= Ygrad(GRAD_WIDTH-1-16);
end if;
end if;
end process ;
--8----------------------------------------
outMag : process (clk)
begin
if rising_edge(clk) then
if fsync ='1' then
Mdata_o <= XgradM + YgradM;
--Mdata_o <= YgradM; ----------------DEBUG-------------
end if;
end if;
end process ;
-------------------------------------------------------------------------------------------------------
-- If we want to get get rid of the atan2() we can just use tan(Gy/Gx):
-- basically the tangent of the angle T defined by Gx and Gy is Gy/Gx: tan(T) = Gy/Gx.
-- So we just have to compare Gy/Gx against the tangent of the reference angle,
-- which are the following constants:
-- tan( p/8) = v2 - 1 ~ 1/2
-- tan(3p/8) = v2 + 1 ~ 2
-- And to avoid the division of Gy/Gx, we can simply compare Gy against Gx multiplied by these constants
-------------------------------------------------------------------------------------------------------
--8
------------------------------------------------------------
edge_sobel_getdir2: process (clk)
begin
if rising_edge(clk) then
if fsync ='1' then
if YgradM(GRAD_WIDTH-1-16 downto 0) < ('0' & XgradM(GRAD_WIDTH-1-16 downto 1)) then Ddata_o <= "01"; --DIRECTION_HORIZONTAL
elsif ('0' & YgradM(GRAD_WIDTH-1-16 downto 1)) > XgradM(GRAD_WIDTH-1-16 downto 0) then Ddata_o <= "00"; -- DIRECTION_VERTICAL
else
if XgradS = YgradS then Ddata_o <= "10"; -- DIRECTION_45R
else Ddata_o <= "11"; -- DIRECTION_45F
end if;
end if;
--Ddata_o <= Ygrada(1 downto 0); ---------DEBUG-------------
end if;
end if;
end process edge_sobel_getdir2;
 
 
 
end Behavioral;
/trunk/vhdl_src/DoubleLineBuffer.vhd
0,0 → 1,62
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity DoubleFiFOLineBuffer is
generic (
DATA_WIDTH : integer := 8;
NO_OF_COLS : integer := 640
);
port(
clk : in std_logic;
fsync : in std_logic;
pdata_in : in std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out1 : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out2 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out3 : buffer std_logic_vector(DATA_WIDTH -1 downto 0) );
end DoubleFiFOLineBuffer;
architecture Behavioral of DoubleFiFOLineBuffer is
 
signal pdata_in_r : std_logic_vector(DATA_WIDTH -1 downto 0);
 
component FIFOLineBuffer is
generic (
DATA_WIDTH : integer := 8;
NO_OF_COLS : integer := 640
);
port(
clk : in std_logic;
fsync : in std_logic;
pdata_in : in std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out : buffer std_logic_vector(DATA_WIDTH -1 downto 0));
end component;
begin
 
pdata_out1 <= pdata_in_r;
update_reg : process (clk)
begin
if rising_edge(clk) then
if fsync = '1' then
pdata_in_r <= pdata_in;
end if;
end if;
end process update_reg;
LineBuffer1 : FIFOLineBuffer
generic map (
DATA_WIDTH => DATA_WIDTH,
NO_OF_COLS => NO_OF_COLS
)
port map(clk, fsync, pdata_in_r, pdata_out2);
LineBuffer2 : FIFOLineBuffer
generic map (
DATA_WIDTH => DATA_WIDTH,
NO_OF_COLS => NO_OF_COLS
)
port map(clk, fsync, pdata_out2, pdata_out3);
 
 
end Behavioral;
/trunk/vhdl_src/ninerowsbuffer.vhd
0,0 → 1,113
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity nineFiFOLineBuffer is
generic (
DATA_WIDTH : integer := 8;
NO_OF_COLS : integer := 640
);
port(
clk : in std_logic;
fsync : in std_logic;
pdata_in : in std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out1 : out std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out2 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out3 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out4 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out5 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out6 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out7 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out8 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out9 : buffer std_logic_vector(DATA_WIDTH -1 downto 0)
);
end nineFiFOLineBuffer;
architecture Behavioral of nineFiFOLineBuffer is
 
signal pdata_in_r : std_logic_vector(DATA_WIDTH -1 downto 0);
 
component FIFOLineBuffer is
generic (
DATA_WIDTH : integer := DATA_WIDTH;
NO_OF_COLS : integer := 640
);
port(
clk : in std_logic;
fsync : in std_logic;
pdata_in : in std_logic_vector(DATA_WIDTH -1 downto 0);
pdata_out : buffer std_logic_vector(DATA_WIDTH -1 downto 0)
);
end component;
begin
pdata_out1 <= pdata_in_r;
 
update_reg : process (clk)
begin
if rising_edge(clk) then
if fsync = '1' then
pdata_in_r <= pdata_in;
end if;
end if;
end process update_reg;
 
LineBuffer1 : FIFOLineBuffer
generic map (
DATA_WIDTH => DATA_WIDTH,
NO_OF_COLS => NO_OF_COLS
)
port map(clk, fsync, pdata_in_r, pdata_out2);
LineBuffer2 : FIFOLineBuffer
generic map (
DATA_WIDTH => DATA_WIDTH,
NO_OF_COLS => NO_OF_COLS
)
port map(clk, fsync, pdata_out2, pdata_out3);
LineBuffer3 : FIFOLineBuffer
generic map (
DATA_WIDTH => DATA_WIDTH,
NO_OF_COLS => NO_OF_COLS
)
port map(clk, fsync, pdata_out3, pdata_out4);
LineBuffer4 : FIFOLineBuffer
generic map (
DATA_WIDTH => DATA_WIDTH,
NO_OF_COLS => NO_OF_COLS
)
port map(clk, fsync, pdata_out4, pdata_out5);
 
LineBuffer5 : FIFOLineBuffer
generic map (
DATA_WIDTH => DATA_WIDTH,
NO_OF_COLS => NO_OF_COLS
)
port map(clk, fsync, pdata_out5, pdata_out6);
LineBuffer6 : FIFOLineBuffer
generic map (
DATA_WIDTH => DATA_WIDTH,
NO_OF_COLS => NO_OF_COLS
)
port map(clk, fsync, pdata_out6, pdata_out7);
LineBuffer7 : FIFOLineBuffer
generic map (
DATA_WIDTH => DATA_WIDTH,
NO_OF_COLS => NO_OF_COLS
)
port map(clk, fsync, pdata_out7, pdata_out8);
LineBuffer8 : FIFOLineBuffer
generic map (
DATA_WIDTH => DATA_WIDTH,
NO_OF_COLS => NO_OF_COLS
)
port map(clk, fsync, pdata_out8, pdata_out9);
 
end Behavioral;
/trunk/readme.txt --- trunk/vhdl_testbench/testbench1.vhd (nonexistent) +++ trunk/vhdl_testbench/testbench1.vhd (revision 2) @@ -0,0 +1,175 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 19:16:58 10/08/2013 +-- Design Name: +-- Module Name: C:/ISE_PROJECTS/sobel_EDA/src/testbench1.vhd +-- Project Name: sobel_EDA +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: topVGA +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +USE ieee.numeric_std.ALL; + +ENTITY testbench1 IS +END testbench1; + +ARCHITECTURE behavior OF testbench1 IS + + + + type FileType is file of integer; + + + COMPONENT top + PORT( + clk : IN std_logic; + rstn : IN std_logic; + data_in : IN std_logic_vector(7 downto 0); + fsync_in : IN std_logic; + fsync_out : OUT std_logic; + data_out : OUT std_logic_vector(7 downto 0) + ); + END COMPONENT; + + + + --Inputs + signal clk : std_logic := '0'; + signal rstn : std_logic := '0'; + signal data_in : std_logic_vector(7 downto 0) := (others => '0'); + signal fsync_in : std_logic := '0'; + + --Outputs + signal fsync_out : std_logic; + signal data_out : std_logic_vector(7 downto 0); + + -- Clock period definitions + constant clk_period : time := 10 ns; + +BEGIN + + --variable i : integer := 1; + + -- Instantiate the Unit Under Test (UUT) + uut: top PORT MAP ( + clk => clk, + rstn => rstn, + data_in => data_in, + fsync_in => fsync_in, + fsync_out => fsync_out, + data_out => data_out + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '1'; + wait for clk_period/2; + clk <= '0'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + file text_in: FileType open read_mode is "inputdata"; + file text_out: FileType open write_mode is "outputdata"; + + variable chr: integer := 0; + + begin + wait for clk_period*1; + rstn <= '1'; + -- hold reset state for 100 ns. + --wait for 100 ns; + + wait for clk_period*18; + + wait for 7 ns; + +-- fsync_in <= '1'; +-- for i in 0 to 400000 loop +-- if i < 307200 then +-- fsync_in <= '1'; +-- read(text_in,chr); +-- data_in <= std_logic_vector(to_unsigned(chr, 8)); +-- --data_in <= '0' & std_logic_vector(to_unsigned(i, 7)); +-- else +-- fsync_in <= '0'; +-- end if; +-- if fsync_out = '1' then +-- write(text_out, to_integer(unsigned(data_out))); +-- end if; +-- wait for clk_period; +-- end loop; + + fsync_in <= '1'; + for i in 0 to 99 loop + fsync_in <= '1'; + read(text_in,chr); + data_in <= std_logic_vector(to_unsigned(chr, 8)); + --data_in <= '0' & std_logic_vector(to_unsigned(i, 7)); + if fsync_out = '1' then + write(text_out, to_integer(unsigned(data_out))); + end if; + wait for clk_period; + end loop; + + fsync_in <= '0'; + for i in 0 to 99999 loop + fsync_in <= '0'; + if fsync_out = '1' then + write(text_out, to_integer(unsigned(data_out))); + end if; + wait for clk_period; + end loop; + + fsync_in <= '1'; + for i in 100 to 307199 loop + fsync_in <= '1'; + read(text_in,chr); + data_in <= std_logic_vector(to_unsigned(chr, 8)); + --data_in <= '0' & std_logic_vector(to_unsigned(i, 7)); + if fsync_out = '1' then + write(text_out, to_integer(unsigned(data_out))); + end if; + wait for clk_period; + end loop; + + fsync_in <= '0'; + for i in 0 to 199999 loop + fsync_in <= '0'; + if fsync_out = '1' then + write(text_out, to_integer(unsigned(data_out))); + end if; + wait for clk_period; + end loop; + + -- insert stimulus here + + wait; + end process; + +END;
/trunk/vhdl_testbench/writefile.m
0,0 → 1,23
%uncomment if using Octave
%pkg load image
 
a=imread('shapes2.bmp');
%a=imread('car.jpg');
%a=imread('radio.jpg');
a=imread('berlu.png');
a = rgb2gray(a);
a=a';
b=a(:);
currentFile = sprintf('inputdata');
FID = fopen(currentFile, 'w');
 
for i=1:1:length(b)
fwrite(FID,b(i),'uint8');
fwrite(FID,0,'uint8');
fwrite(FID,0,'uint8');
fwrite(FID,0,'uint8');
end
 
fclose(FID);
/trunk/vhdl_testbench/readfile.m
0,0 → 1,30
currentFile = sprintf('outputdata');
FID = fopen(currentFile);
 
c=fread(FID);
fclose(FID);
 
c=reshape(c,4,length(c)/4);
c=c(1,:);
c=c';
c=reshape(c,640,480);
c=c';
 
currentFile = sprintf('inputdata');
FID = fopen(currentFile);
 
d=fread(FID);
fclose(FID);
 
d=reshape(d,4,length(d)/4);
d=d(1,:);
d=d';
d=reshape(d,640,480);
d=d';
 
imshow(uint8(c))
figure
imshow(uint8(d))
 
/trunk/vhdl_testbench/readme.txt Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/vhdl_testbench/berlu.png
trunk/vhdl_testbench/berlu.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property

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