Subversion Repositories cheap_ethernet

/cheap_ethernet/trunk/FPGAUDP/FPGAUDP.exe Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

/cheap_ethernet/trunk/FPGAUDP/FPGAUDP.exe

cheap_ethernet/trunk/FPGAUDP/FPGAUDP.exe Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: cheap_ethernet/trunk/FPGAUDP/main.pas =================================================================== --- cheap_ethernet/trunk/FPGAUDP/main.pas (nonexistent) +++ cheap_ethernet/trunk/FPGAUDP/main.pas (revision 3) @@ -0,0 +1,97 @@ +unit main; + +interface + +uses + Windows, Messages, SysUtils, Variants, Classes, Graphics, Controls, Forms, + Dialogs, StdCtrls, IdUDPClient, IdBaseComponent, IdComponent, IdUDPBase, + IdUDPServer, IdSocketHandle, Math, IdTCPServer, IdTCPConnection, + IdTCPClient; + +type + TForm1 = class(TForm) + IdUDPServer1: TIdUDPServer; + Memo1: TMemo; + IdUDPClient1: TIdUDPClient; + Button1: TButton; + Edit1: TEdit; + Label1: TLabel; + Button2: TButton; + Button3: TButton; + Button5: TButton; + Button4: TButton; + Button6: TButton; + procedure IdUDPServer1UDPRead(Sender: TObject; AData: TStream; + ABinding: TIdSocketHandle); + procedure ButtonsClick(Sender: TObject); + procedure FormShow(Sender: TObject); + private + { Private declarations } + public + { Public declarations } + end; + +var + Form1: TForm1; + +implementation + +{$R *.dfm} + +var + cnt: Integer = 0; + +const + CmdDone = 0; + CmdStatus = 1; + CmdLEDCtrl = 2; + CmdSetConfig = 3; + CmdSwChanged = 4; + CmdDataEcho = 5; + + +procedure TForm1.IdUDPServer1UDPRead(Sender: TObject; AData: TStream; + ABinding: TIdSocketHandle); +var + S, T: String; + i, l: Integer; +begin + Memo1.Lines.Add(IntToStr (cnt) + ') Received ' + IntToStr (AData.Size) + ' bytes:'); + cnt := cnt + 1; + l := min (AData.Size, 32); + SetLength (S, l); + AData.Read (S[1], l); + T := ''; + for i := 0 to l - 1 do + T := T + IntToHex (Ord (S[i + 1]), 2) + ' '; + Memo1.Lines.Add (T + #13#10); +end; + +procedure TForm1.FormShow(Sender: TObject); +begin + IdUDPServer1.Active := True; +end; + +procedure TForm1.ButtonsClick(Sender: TObject); +var + S, T: String; + i: Integer; +begin + cnt := cnt + 1; + IdUDPClient1.Host := Edit1.Text; + case (TButton(Sender).Tag) of + 0: S := Chr(CmdLEDCtrl) + #1#0#0#0#0#0#0#0#0#0#0#0#0#0#0#0#0; + 1: S := Chr(CmdLEDCtrl) + #0#0#0#0#0#0#0#0#0#0#0#0#0#0#0#0#0; + 2: S := Chr(CmdSetConfig) + #1#0#0#0#0#0#0#0#0#0#0#0#0#0#0#0#0; + 3: S := Chr(CmdSetConfig) + #0#0#0#0#0#0#0#0#0#0#0#0#0#0#0#0#0; + 4: S := Chr(CmdStatus) + #0#0#0#0#0#0#0#0#0#0#0#0#0#0#0#0#0; + 5: S := Chr(CmdDataEcho) + #1#2#3#4#5#6#7#8#9#10#11#12#13#14#15#16#17; + end; + for i := 0 to Length (S) - 1 do + T := T + IntToHex (Ord (S[i + 1]), 2) + ' '; + Memo1.Lines.Add(IntToStr (cnt) + ') Sending ' + IntToStr (Length (S)) + ' bytes:'); + Memo1.Lines.Add (T); + IdUDPClient1.Send (S); +end; + +end. Index: cheap_ethernet/trunk/FPGAUDP/main.dfm =================================================================== --- cheap_ethernet/trunk/FPGAUDP/main.dfm (nonexistent) +++ cheap_ethernet/trunk/FPGAUDP/main.dfm (revision 3) @@ -0,0 +1,119 @@ +object Form1: TForm1 + Left = 192 + Top = 114 + Width = 763 + Height = 560 + Caption = 'FPGA Cheap Ethernet test' + Color = clBtnFace + Font.Charset = DEFAULT_CHARSET + Font.Color = clWindowText + Font.Height = -11 + Font.Name = 'MS Sans Serif' + Font.Style = [] + OldCreateOrder = False + OnShow = FormShow + DesignSize = ( + 755 + 526) + PixelsPerInch = 96 + TextHeight = 13 + object Label1: TLabel + Left = 24 + Top = 20 + Width = 69 + Height = 13 + Caption = 'Destination IP ' + end + object Memo1: TMemo + Left = 8 + Top = 52 + Width = 739 + Height = 464 + Anchors = [akLeft, akTop, akRight, akBottom] + TabOrder = 0 + end + object Button1: TButton + Left = 244 + Top = 16 + Width = 75 + Height = 25 + Caption = 'Led ON' + TabOrder = 1 + OnClick = ButtonsClick + end + object Edit1: TEdit + Left = 104 + Top = 16 + Width = 121 + Height = 21 + TabOrder = 2 + Text = '192.168.1.44' + end + object Button2: TButton + Tag = 1 + Left = 328 + Top = 16 + Width = 75 + Height = 25 + Caption = 'Led OFF' + TabOrder = 3 + OnClick = ButtonsClick + end + object Button3: TButton + Tag = 5 + Left = 664 + Top = 16 + Width = 75 + Height = 25 + Caption = 'Echo' + TabOrder = 4 + OnClick = ButtonsClick + end + object Button5: TButton + Tag = 4 + Left = 580 + Top = 16 + Width = 75 + Height = 25 + Caption = 'Get Status' + TabOrder = 5 + OnClick = ButtonsClick + end + object Button4: TButton + Tag = 2 + Left = 412 + Top = 16 + Width = 75 + Height = 25 + Caption = 'Autosend ON' + TabOrder = 6 + OnClick = ButtonsClick + end + object Button6: TButton + Tag = 3 + Left = 496 + Top = 16 + Width = 75 + Height = 25 + Caption = 'Autosend OFF' + TabOrder = 7 + OnClick = ButtonsClick + end + object IdUDPServer1: TIdUDPServer + Bindings = < + item + IP = '0.0.0.0' + Port = 1024 + end> + DefaultPort = 0 + OnUDPRead = IdUDPServer1UDPRead + Left = 204 + Top = 64 + end + object IdUDPClient1: TIdUDPClient + Host = '192.168.1.44' + Port = 1024 + Left = 152 + Top = 64 + end +end Index: cheap_ethernet/trunk/FPGAUDP/FPGAUDP.dpr =================================================================== --- cheap_ethernet/trunk/FPGAUDP/FPGAUDP.dpr (nonexistent) +++ cheap_ethernet/trunk/FPGAUDP/FPGAUDP.dpr (revision 3) @@ -0,0 +1,13 @@ +program FPGAUDP; + +uses + Forms, + main in 'main.pas' {Form1}; + +{$R *.res} + +begin + Application.Initialize; + Application.CreateForm(TForm1, Form1); + Application.Run; +end. Index: cheap_ethernet/trunk/FPGAUDP/FPGAUDP.res =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: cheap_ethernet/trunk/FPGAUDP/FPGAUDP.res =================================================================== --- cheap_ethernet/trunk/FPGAUDP/FPGAUDP.res (nonexistent) +++ cheap_ethernet/trunk/FPGAUDP/FPGAUDP.res (revision 3)

cheap_ethernet/trunk/FPGAUDP/FPGAUDP.res Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: cheap_ethernet/trunk/FPGAUDP/main.dcu =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: cheap_ethernet/trunk/FPGAUDP/main.dcu =================================================================== --- cheap_ethernet/trunk/FPGAUDP/main.dcu (nonexistent) +++ cheap_ethernet/trunk/FPGAUDP/main.dcu (revision 3)

cheap_ethernet/trunk/FPGAUDP/main.dcu Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: cheap_ethernet/trunk/docs/transformer1.PNG =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: cheap_ethernet/trunk/docs/transformer1.PNG =================================================================== --- cheap_ethernet/trunk/docs/transformer1.PNG (nonexistent) +++ cheap_ethernet/trunk/docs/transformer1.PNG (revision 3)

cheap_ethernet/trunk/docs/transformer1.PNG Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: cheap_ethernet/trunk/docs/transformer2.PNG =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: cheap_ethernet/trunk/docs/transformer2.PNG =================================================================== --- cheap_ethernet/trunk/docs/transformer2.PNG (nonexistent) +++ cheap_ethernet/trunk/docs/transformer2.PNG (revision 3)

cheap_ethernet/trunk/docs/transformer2.PNG Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: cheap_ethernet/trunk/Ethernet_test/ipcore_dir/_xmsgs/pn_parser.xmsgs =================================================================== --- cheap_ethernet/trunk/Ethernet_test/ipcore_dir/_xmsgs/pn_parser.xmsgs (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/ipcore_dir/_xmsgs/pn_parser.xmsgs (revision 3) @@ -0,0 +1,12 @@ + + + + + + + + + + + + Index: cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX.v =================================================================== --- cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX.v (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX.v (revision 3) @@ -0,0 +1,487 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2012 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// You must compile the wrapper file FIFORX.v when simulating +// the core, FIFORX. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +`timescale 1ns/1ps + +module FIFORX( + rst, + wr_clk, + rd_clk, + din, + wr_en, + rd_en, + dout, + full, + empty +); + +input rst; +input wr_clk; +input rd_clk; +input [7 : 0] din; +input wr_en; +input rd_en; +output [7 : 0] dout; +output full; +output empty; + +// synthesis translate_off + + FIFO_GENERATOR_V9_1 #( + .C_ADD_NGC_CONSTRAINT(0), + .C_APPLICATION_TYPE_AXIS(0), + .C_APPLICATION_TYPE_RACH(0), + .C_APPLICATION_TYPE_RDCH(0), + .C_APPLICATION_TYPE_WACH(0), + .C_APPLICATION_TYPE_WDCH(0), + .C_APPLICATION_TYPE_WRCH(0), + .C_AXI_ADDR_WIDTH(32), + .C_AXI_ARUSER_WIDTH(1), + .C_AXI_AWUSER_WIDTH(1), + .C_AXI_BUSER_WIDTH(1), + .C_AXI_DATA_WIDTH(64), + .C_AXI_ID_WIDTH(4), + .C_AXI_RUSER_WIDTH(1), + .C_AXI_TYPE(0), + .C_AXI_WUSER_WIDTH(1), + .C_AXIS_TDATA_WIDTH(64), + .C_AXIS_TDEST_WIDTH(4), + .C_AXIS_TID_WIDTH(8), + .C_AXIS_TKEEP_WIDTH(4), + .C_AXIS_TSTRB_WIDTH(4), + .C_AXIS_TUSER_WIDTH(4), + .C_AXIS_TYPE(0), + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(10), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(8), + .C_DIN_WIDTH_AXIS(1), + .C_DIN_WIDTH_RACH(32), + .C_DIN_WIDTH_RDCH(64), + .C_DIN_WIDTH_WACH(32), + .C_DIN_WIDTH_WDCH(64), + .C_DIN_WIDTH_WRCH(2), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(8), + .C_ENABLE_RLOCS(0), + .C_ENABLE_RST_SYNC(1), + .C_ERROR_INJECTION_TYPE(0), + .C_ERROR_INJECTION_TYPE_AXIS(0), + .C_ERROR_INJECTION_TYPE_RACH(0), + .C_ERROR_INJECTION_TYPE_RDCH(0), + .C_ERROR_INJECTION_TYPE_WACH(0), + .C_ERROR_INJECTION_TYPE_WDCH(0), + .C_ERROR_INJECTION_TYPE_WRCH(0), + .C_FAMILY("spartan3"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_AXI_ARUSER(0), + .C_HAS_AXI_AWUSER(0), + .C_HAS_AXI_BUSER(0), + .C_HAS_AXI_RD_CHANNEL(0), + .C_HAS_AXI_RUSER(0), + .C_HAS_AXI_WR_CHANNEL(0), + .C_HAS_AXI_WUSER(0), + .C_HAS_AXIS_TDATA(0), + .C_HAS_AXIS_TDEST(0), + .C_HAS_AXIS_TID(0), + .C_HAS_AXIS_TKEEP(0), + .C_HAS_AXIS_TLAST(0), + .C_HAS_AXIS_TREADY(1), + .C_HAS_AXIS_TSTRB(0), + .C_HAS_AXIS_TUSER(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_DATA_COUNTS_AXIS(0), + .C_HAS_DATA_COUNTS_RACH(0), + .C_HAS_DATA_COUNTS_RDCH(0), + .C_HAS_DATA_COUNTS_WACH(0), + .C_HAS_DATA_COUNTS_WDCH(0), + .C_HAS_DATA_COUNTS_WRCH(0), + .C_HAS_INT_CLK(0), + .C_HAS_MASTER_CE(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_PROG_FLAGS_AXIS(0), + .C_HAS_PROG_FLAGS_RACH(0), + .C_HAS_PROG_FLAGS_RDCH(0), + .C_HAS_PROG_FLAGS_WACH(0), + .C_HAS_PROG_FLAGS_WDCH(0), + .C_HAS_PROG_FLAGS_WRCH(0), + .C_HAS_RD_DATA_COUNT(0), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SLAVE_CE(0), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(0), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_IMPLEMENTATION_TYPE_AXIS(1), + .C_IMPLEMENTATION_TYPE_RACH(1), + .C_IMPLEMENTATION_TYPE_RDCH(1), + .C_IMPLEMENTATION_TYPE_WACH(1), + .C_IMPLEMENTATION_TYPE_WDCH(1), + .C_IMPLEMENTATION_TYPE_WRCH(1), + .C_INIT_WR_PNTR_VAL(0), + .C_INTERFACE_TYPE(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(1), + .C_PRELOAD_REGS(0), + .C_PRIM_FIFO_TYPE("1kx18"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(2), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(3), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_EMPTY_TYPE_AXIS(0), + .C_PROG_EMPTY_TYPE_RACH(0), + .C_PROG_EMPTY_TYPE_RDCH(0), + .C_PROG_EMPTY_TYPE_WACH(0), + .C_PROG_EMPTY_TYPE_WDCH(0), + .C_PROG_EMPTY_TYPE_WRCH(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(1021), + .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023), + .C_PROG_FULL_THRESH_NEGATE_VAL(1020), + .C_PROG_FULL_TYPE(0), + .C_PROG_FULL_TYPE_AXIS(0), + .C_PROG_FULL_TYPE_RACH(0), + .C_PROG_FULL_TYPE_RDCH(0), + .C_PROG_FULL_TYPE_WACH(0), + .C_PROG_FULL_TYPE_WDCH(0), + .C_PROG_FULL_TYPE_WRCH(0), + .C_RACH_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(10), + .C_RD_DEPTH(1024), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(10), + .C_RDCH_TYPE(0), + .C_REG_SLICE_MODE_AXIS(0), + .C_REG_SLICE_MODE_RACH(0), + .C_REG_SLICE_MODE_RDCH(0), + .C_REG_SLICE_MODE_WACH(0), + .C_REG_SLICE_MODE_WDCH(0), + .C_REG_SLICE_MODE_WRCH(0), + .C_SYNCHRONIZER_STAGE(2), + .C_UNDERFLOW_LOW(0), + .C_USE_COMMON_OVERFLOW(0), + .C_USE_COMMON_UNDERFLOW(0), + .C_USE_DEFAULT_SETTINGS(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_ECC_AXIS(0), + .C_USE_ECC_RACH(0), + .C_USE_ECC_RDCH(0), + .C_USE_ECC_WACH(0), + .C_USE_ECC_WDCH(0), + .C_USE_ECC_WRCH(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(0), + .C_VALID_LOW(0), + .C_WACH_TYPE(0), + .C_WDCH_TYPE(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(10), + .C_WR_DEPTH(1024), + .C_WR_DEPTH_AXIS(1024), + .C_WR_DEPTH_RACH(16), + .C_WR_DEPTH_RDCH(1024), + .C_WR_DEPTH_WACH(16), + .C_WR_DEPTH_WDCH(1024), + .C_WR_DEPTH_WRCH(16), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(10), + .C_WR_PNTR_WIDTH_AXIS(10), + .C_WR_PNTR_WIDTH_RACH(4), + .C_WR_PNTR_WIDTH_RDCH(10), + .C_WR_PNTR_WIDTH_WACH(4), + .C_WR_PNTR_WIDTH_WDCH(10), + .C_WR_PNTR_WIDTH_WRCH(4), + .C_WR_RESPONSE_LATENCY(1), + .C_WRCH_TYPE(0) + ) + inst ( + .RST(rst), + .WR_CLK(wr_clk), + .RD_CLK(rd_clk), + .DIN(din), + .WR_EN(wr_en), + .RD_EN(rd_en), + .DOUT(dout), + .FULL(full), + .EMPTY(empty), + .BACKUP(), + .BACKUP_MARKER(), + .CLK(), + .SRST(), + .WR_RST(), + .RD_RST(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .INT_CLK(), + .INJECTDBITERR(), + .INJECTSBITERR(), + .ALMOST_FULL(), + .WR_ACK(), + .OVERFLOW(), + .ALMOST_EMPTY(), + .VALID(), + .UNDERFLOW(), + .DATA_COUNT(), + .RD_DATA_COUNT(), + .WR_DATA_COUNT(), + .PROG_FULL(), + .PROG_EMPTY(), + .SBITERR(), + .DBITERR(), + .M_ACLK(), + .S_ACLK(), + .S_ARESETN(), + .M_ACLK_EN(), + .S_ACLK_EN(), + .S_AXI_AWID(), + .S_AXI_AWADDR(), + .S_AXI_AWLEN(), + .S_AXI_AWSIZE(), + .S_AXI_AWBURST(), + .S_AXI_AWLOCK(), + .S_AXI_AWCACHE(), + .S_AXI_AWPROT(), + .S_AXI_AWQOS(), + .S_AXI_AWREGION(), + .S_AXI_AWUSER(), + .S_AXI_AWVALID(), + .S_AXI_AWREADY(), + .S_AXI_WID(), + .S_AXI_WDATA(), + .S_AXI_WSTRB(), + .S_AXI_WLAST(), + .S_AXI_WUSER(), + .S_AXI_WVALID(), + .S_AXI_WREADY(), + .S_AXI_BID(), + .S_AXI_BRESP(), + .S_AXI_BUSER(), + .S_AXI_BVALID(), + .S_AXI_BREADY(), + .M_AXI_AWID(), + .M_AXI_AWADDR(), + .M_AXI_AWLEN(), + .M_AXI_AWSIZE(), + .M_AXI_AWBURST(), + .M_AXI_AWLOCK(), + .M_AXI_AWCACHE(), + .M_AXI_AWPROT(), + .M_AXI_AWQOS(), + .M_AXI_AWREGION(), + .M_AXI_AWUSER(), + .M_AXI_AWVALID(), + .M_AXI_AWREADY(), + .M_AXI_WID(), + .M_AXI_WDATA(), + .M_AXI_WSTRB(), + .M_AXI_WLAST(), + .M_AXI_WUSER(), + .M_AXI_WVALID(), + .M_AXI_WREADY(), + .M_AXI_BID(), + .M_AXI_BRESP(), + .M_AXI_BUSER(), + .M_AXI_BVALID(), + .M_AXI_BREADY(), + .S_AXI_ARID(), + .S_AXI_ARADDR(), + .S_AXI_ARLEN(), + .S_AXI_ARSIZE(), + .S_AXI_ARBURST(), + .S_AXI_ARLOCK(), + .S_AXI_ARCACHE(), + .S_AXI_ARPROT(), + .S_AXI_ARQOS(), + .S_AXI_ARREGION(), + .S_AXI_ARUSER(), + .S_AXI_ARVALID(), + .S_AXI_ARREADY(), + .S_AXI_RID(), + .S_AXI_RDATA(), + .S_AXI_RRESP(), + .S_AXI_RLAST(), + .S_AXI_RUSER(), + .S_AXI_RVALID(), + .S_AXI_RREADY(), + .M_AXI_ARID(), + .M_AXI_ARADDR(), + .M_AXI_ARLEN(), + .M_AXI_ARSIZE(), + .M_AXI_ARBURST(), + .M_AXI_ARLOCK(), + .M_AXI_ARCACHE(), + .M_AXI_ARPROT(), + .M_AXI_ARQOS(), + .M_AXI_ARREGION(), + .M_AXI_ARUSER(), + .M_AXI_ARVALID(), + .M_AXI_ARREADY(), + .M_AXI_RID(), + .M_AXI_RDATA(), + .M_AXI_RRESP(), + .M_AXI_RLAST(), + .M_AXI_RUSER(), + .M_AXI_RVALID(), + .M_AXI_RREADY(), + .S_AXIS_TVALID(), + .S_AXIS_TREADY(), + .S_AXIS_TDATA(), + .S_AXIS_TSTRB(), + .S_AXIS_TKEEP(), + .S_AXIS_TLAST(), + .S_AXIS_TID(), + .S_AXIS_TDEST(), + .S_AXIS_TUSER(), + .M_AXIS_TVALID(), + .M_AXIS_TREADY(), + .M_AXIS_TDATA(), + .M_AXIS_TSTRB(), + .M_AXIS_TKEEP(), + .M_AXIS_TLAST(), + .M_AXIS_TID(), + .M_AXIS_TDEST(), + .M_AXIS_TUSER(), + .AXI_AW_INJECTSBITERR(), + .AXI_AW_INJECTDBITERR(), + .AXI_AW_PROG_FULL_THRESH(), + .AXI_AW_PROG_EMPTY_THRESH(), + .AXI_AW_DATA_COUNT(), + .AXI_AW_WR_DATA_COUNT(), + .AXI_AW_RD_DATA_COUNT(), + .AXI_AW_SBITERR(), + .AXI_AW_DBITERR(), + .AXI_AW_OVERFLOW(), + .AXI_AW_UNDERFLOW(), + .AXI_AW_PROG_FULL(), + .AXI_AW_PROG_EMPTY(), + .AXI_W_INJECTSBITERR(), + .AXI_W_INJECTDBITERR(), + .AXI_W_PROG_FULL_THRESH(), + .AXI_W_PROG_EMPTY_THRESH(), + .AXI_W_DATA_COUNT(), + .AXI_W_WR_DATA_COUNT(), + .AXI_W_RD_DATA_COUNT(), + .AXI_W_SBITERR(), + .AXI_W_DBITERR(), + .AXI_W_OVERFLOW(), + .AXI_W_UNDERFLOW(), + .AXI_B_INJECTSBITERR(), + .AXI_W_PROG_FULL(), + .AXI_W_PROG_EMPTY(), + .AXI_B_INJECTDBITERR(), + .AXI_B_PROG_FULL_THRESH(), + .AXI_B_PROG_EMPTY_THRESH(), + .AXI_B_DATA_COUNT(), + .AXI_B_WR_DATA_COUNT(), + .AXI_B_RD_DATA_COUNT(), + .AXI_B_SBITERR(), + .AXI_B_DBITERR(), + .AXI_B_OVERFLOW(), + .AXI_B_UNDERFLOW(), + .AXI_AR_INJECTSBITERR(), + .AXI_B_PROG_FULL(), + .AXI_B_PROG_EMPTY(), + .AXI_AR_INJECTDBITERR(), + .AXI_AR_PROG_FULL_THRESH(), + .AXI_AR_PROG_EMPTY_THRESH(), + .AXI_AR_DATA_COUNT(), + .AXI_AR_WR_DATA_COUNT(), + .AXI_AR_RD_DATA_COUNT(), + .AXI_AR_SBITERR(), + .AXI_AR_DBITERR(), + .AXI_AR_OVERFLOW(), + .AXI_AR_UNDERFLOW(), + .AXI_AR_PROG_FULL(), + .AXI_AR_PROG_EMPTY(), + .AXI_R_INJECTSBITERR(), + .AXI_R_INJECTDBITERR(), + .AXI_R_PROG_FULL_THRESH(), + .AXI_R_PROG_EMPTY_THRESH(), + .AXI_R_DATA_COUNT(), + .AXI_R_WR_DATA_COUNT(), + .AXI_R_RD_DATA_COUNT(), + .AXI_R_SBITERR(), + .AXI_R_DBITERR(), + .AXI_R_OVERFLOW(), + .AXI_R_UNDERFLOW(), + .AXIS_INJECTSBITERR(), + .AXI_R_PROG_FULL(), + .AXI_R_PROG_EMPTY(), + .AXIS_INJECTDBITERR(), + .AXIS_PROG_FULL_THRESH(), + .AXIS_PROG_EMPTY_THRESH(), + .AXIS_DATA_COUNT(), + .AXIS_WR_DATA_COUNT(), + .AXIS_RD_DATA_COUNT(), + .AXIS_SBITERR(), + .AXIS_DBITERR(), + .AXIS_OVERFLOW(), + .AXIS_UNDERFLOW(), + .AXIS_PROG_FULL(), + .AXIS_PROG_EMPTY() + ); + +// synthesis translate_on + +endmodule Index: cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX.ncf =================================================================== Index: cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX.ngc =================================================================== --- cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX.ngc (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX.ngc (revision 3) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file Index: cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX.gise =================================================================== --- cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX.gise (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX.gise (revision 3) @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + Index: cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX.xise =================================================================== --- cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX.xise (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX.xise (revision 3) @@ -0,0 +1,74 @@ + + + +

+ + + + + + + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX.sym =================================================================== --- cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX.sym (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX.sym (revision 3) @@ -0,0 +1,36 @@ + + + BLOCK + 2012-8-29T7:52:55 + + + + + + + + + + + FIFORX + + + + + + + + + + + + + + + + + + + + + Index: cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX.xco =================================================================== --- cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX.xco (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX.xco (revision 3) @@ -0,0 +1,213 @@ +############################################################## +# +# Xilinx Core Generator version 14.1 +# Date: Wed Aug 29 07:50:26 2012 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:fifo_generator:9.1 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s500e +SET devicefamily = spartan3e +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = pq208 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Fifo_Generator xilinx.com:ip:fifo_generator:9.1 +# END Select +# BEGIN Parameters +CSET add_ngc_constraint_axi=false +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET aruser_width=1 +CSET awuser_width=1 +CSET axi_address_width=32 +CSET axi_data_width=64 +CSET axi_type=AXI4_Stream +CSET axis_type=FIFO +CSET buser_width=1 +CSET clock_enable_type=Slave_Interface_Clock_Enable +CSET clock_type_axi=Common_Clock +CSET component_name=FIFORX +CSET data_count=false +CSET data_count_width=10 +CSET disable_timing_violations=false +CSET disable_timing_violations_axi=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=2 +CSET empty_threshold_assert_value_axis=1022 +CSET empty_threshold_assert_value_rach=1022 +CSET empty_threshold_assert_value_rdch=1022 +CSET empty_threshold_assert_value_wach=1022 +CSET empty_threshold_assert_value_wdch=1022 +CSET empty_threshold_assert_value_wrch=1022 +CSET empty_threshold_negate_value=3 +CSET enable_aruser=false +CSET enable_awuser=false +CSET enable_buser=false +CSET enable_common_overflow=false +CSET enable_common_underflow=false +CSET enable_data_counts_axis=false +CSET enable_data_counts_rach=false +CSET enable_data_counts_rdch=false +CSET enable_data_counts_wach=false +CSET enable_data_counts_wdch=false +CSET enable_data_counts_wrch=false +CSET enable_ecc=false +CSET enable_ecc_axis=false +CSET enable_ecc_rach=false +CSET enable_ecc_rdch=false +CSET enable_ecc_wach=false +CSET enable_ecc_wdch=false +CSET enable_ecc_wrch=false +CSET enable_read_channel=false +CSET enable_read_pointer_increment_by2=false +CSET enable_reset_synchronization=true +CSET enable_ruser=false +CSET enable_tdata=false +CSET enable_tdest=false +CSET enable_tid=false +CSET enable_tkeep=false +CSET enable_tlast=false +CSET enable_tready=true +CSET enable_tstrobe=false +CSET enable_tuser=false +CSET enable_write_channel=false +CSET enable_wuser=false +CSET fifo_application_type_axis=Data_FIFO +CSET fifo_application_type_rach=Data_FIFO +CSET fifo_application_type_rdch=Data_FIFO +CSET fifo_application_type_wach=Data_FIFO +CSET fifo_application_type_wdch=Data_FIFO +CSET fifo_application_type_wrch=Data_FIFO +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET fifo_implementation_axis=Common_Clock_Block_RAM +CSET fifo_implementation_rach=Common_Clock_Block_RAM +CSET fifo_implementation_rdch=Common_Clock_Block_RAM +CSET fifo_implementation_wach=Common_Clock_Block_RAM +CSET fifo_implementation_wdch=Common_Clock_Block_RAM +CSET fifo_implementation_wrch=Common_Clock_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=1021 +CSET full_threshold_assert_value_axis=1023 +CSET full_threshold_assert_value_rach=1023 +CSET full_threshold_assert_value_rdch=1023 +CSET full_threshold_assert_value_wach=1023 +CSET full_threshold_assert_value_wdch=1023 +CSET full_threshold_assert_value_wrch=1023 +CSET full_threshold_negate_value=1020 +CSET id_width=4 +CSET inject_dbit_error=false +CSET inject_dbit_error_axis=false +CSET inject_dbit_error_rach=false +CSET inject_dbit_error_rdch=false +CSET inject_dbit_error_wach=false +CSET inject_dbit_error_wdch=false +CSET inject_dbit_error_wrch=false +CSET inject_sbit_error=false +CSET inject_sbit_error_axis=false +CSET inject_sbit_error_rach=false +CSET inject_sbit_error_rdch=false +CSET inject_sbit_error_wach=false +CSET inject_sbit_error_wdch=false +CSET inject_sbit_error_wrch=false +CSET input_data_width=8 +CSET input_depth=1024 +CSET input_depth_axis=1024 +CSET input_depth_rach=16 +CSET input_depth_rdch=1024 +CSET input_depth_wach=16 +CSET input_depth_wdch=1024 +CSET input_depth_wrch=16 +CSET interface_type=Native +CSET output_data_width=8 +CSET output_depth=1024 +CSET overflow_flag=false +CSET overflow_flag_axi=false +CSET overflow_sense=Active_High +CSET overflow_sense_axi=Active_High +CSET performance_options=Standard_FIFO +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET programmable_full_type_axis=No_Programmable_Full_Threshold +CSET programmable_full_type_rach=No_Programmable_Full_Threshold +CSET programmable_full_type_rdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wach=No_Programmable_Full_Threshold +CSET programmable_full_type_wdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wrch=No_Programmable_Full_Threshold +CSET rach_type=FIFO +CSET rdch_type=FIFO +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=10 +CSET register_slice_mode_axis=Fully_Registered +CSET register_slice_mode_rach=Fully_Registered +CSET register_slice_mode_rdch=Fully_Registered +CSET register_slice_mode_wach=Fully_Registered +CSET register_slice_mode_wdch=Fully_Registered +CSET register_slice_mode_wrch=Fully_Registered +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET ruser_width=1 +CSET synchronization_stages=2 +CSET synchronization_stages_axi=2 +CSET tdata_width=64 +CSET tdest_width=4 +CSET tid_width=8 +CSET tkeep_width=4 +CSET tstrb_width=4 +CSET tuser_width=4 +CSET underflow_flag=false +CSET underflow_flag_axi=false +CSET underflow_sense=Active_High +CSET underflow_sense_axi=Active_High +CSET use_clock_enable=false +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET wach_type=FIFO +CSET wdch_type=FIFO +CSET wrch_type=FIFO +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=10 +CSET wuser_width=1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-04-13T16:13:14Z +# END Extra information +GENERATE +# CRC: 61b5545b Index: cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX.veo =================================================================== --- cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX.veo (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX.veo (revision 3) @@ -0,0 +1,74 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2012 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ + +/******************************************************************************* +* Generated from core with identifier: xilinx.com:ip:fifo_generator:9.1 * +* * +* The FIFO Generator is a parameterizable first-in/first-out memory * +* queue generator. Use it to generate resource and performance * +* optimized FIFOs with common or independent read/write clock domains, * +* and optional fixed or programmable full and empty flags and * +* handshaking signals. Choose from a selection of memory resource * +* types for implementation. Optional Hamming code based error * +* detection and correction as well as error injection capability for * +* system test help to insure data integrity. FIFO width and depth are * +* parameterizable, and for native interface FIFOs, asymmetric read and * +* write port widths are also supported. * +*******************************************************************************/ + +// Interfaces: +// AXI4Stream_MASTER_M_AXIS +// AXI4Stream_SLAVE_S_AXIS +// AXI4_MASTER_M_AXI +// AXI4_SLAVE_S_AXI +// AXI4Lite_MASTER_M_AXI +// AXI4Lite_SLAVE_S_AXI + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +FIFORX your_instance_name ( + .rst(rst), // input rst + .wr_clk(wr_clk), // input wr_clk + .rd_clk(rd_clk), // input rd_clk + .din(din), // input [7 : 0] din + .wr_en(wr_en), // input wr_en + .rd_en(rd_en), // input rd_en + .dout(dout), // output [7 : 0] dout + .full(full), // output full + .empty(empty) // output empty +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file FIFORX.v when simulating +// the core, FIFORX. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + Index: cheap_ethernet/trunk/Ethernet_test/ipcore_dir/DCMMAIN.xaw =================================================================== --- cheap_ethernet/trunk/Ethernet_test/ipcore_dir/DCMMAIN.xaw (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/ipcore_dir/DCMMAIN.xaw (revision 3) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$9fx5>6339$;><5>4:3-5=2<9=$:46?9'iA3<54<9Q;0>?5=07914+67881?=6;=;424?DTD@^CQ=:5NRVX\KKJ^WJKXOLJFNF]@HN7?3HX\VRAALX]@HNOIWLR_I_@NL078EWQ]WFDGURMCKHL\RDJRM8h0M_YU_NLO]ZBDEVY\EYMGIOE\GIM682KY[WQ@NM[\@ATXK9;;7L\XZ^MMH\YCL[UH=7L\XZ^MMH\YAJVOSXH\AAM31?DTPRVEE@TQFNRV\JPKb3HX\VRAALX]SIFB6=2KY[WQ@NM[\V@UB\VFDKDM>8:CQS_YHFESTZLBFD^FEWZKHLLk0M^]@C^UJPM`2K\VRMCKCWEP\VB9VDDIIG[129BS_YDDBUDYY^ZT^VZT@eGPRVZJ^Yj4AVX\W\HS@]ED@95MOUJ7?GSAO:>0O7R_rnhfgqu[P`fbbuRJtigqj`r[ayid~hQkis^-XAEJEHCE"uox4:AOO5>8148GIM5?9?0OAE=X99@HN4_91:>7NBD9178GIMC^01H@FJY_CWEb>EKCM\TNXHH_HLPPf=DDBN]SIGYIEG:?FJLL_UDYY;4CMIEF==DDBLISD@:;BNHB]>4CMIJJZOE]OMTEC][f:AOOLHXAK_MKRAZT99@HNOIW@Dh7NBDIO]SAWOHLl1H@FGA_RP@[Q_WM880OAE@UU]SLDUBWZBBJYm4CMI\B@CCJHI@56M@MLKWP@B03JXNMYKK6:F@IZUWj2NHAR]__HLPPa=CMZAN[ROKJTQW57=CNZUM^H_ZEOAZ[HICMh1O@AQNNE]E\441OS[OCUD:8A]RBZGKGm6HNCUMQ]ZLA=2LJ@^K6;G@\WJSUKLi0JHKKB@AH[GSA12LBBR[AIUQ;?CIR\VY_^l5IOTV\QKOS[h1MCXZPV@NVA4=N=2CIYKI7;HLWAWHFD8;0FDZ[ES]JJUSSW]S[In5EIUVFVZVL:YAh7GG[TDP\RDJRM?1GCLJJD79OKFMBLh1GCNEJD^MVP6=KG^90AET8;L]UEISB?2DNXZA]K59MKKC63F20CKJKRBRFf>VOIZOT_EGIT89SMKNF[K_Xm6^FNHQDJACC02ZBBZGKTI:8TWOJ\PZN==5_RNR\TLHN[HI_E[K:;QQ@HN0VTAGIOIN=4RRV5?WUSW@Di7^GHEYVFVKGK>2YBBJBJc:QWEWRRXV]JEY84SUCWQV753ZSXXHCPSXL@LWIIG\Y87YA_4:VQQ@><]ZOTNXHH9:WPAZDRNNY>7[GJW0`8\DQX^LXXEB@>d:ZJHLH_%QNI,= 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3b=0?10qo=i:181>5<7s-:4?:383>5}#>l09?6g:a;29 3b=0?1/:k48c:9l2=<72-13-5<#>m03:6*9f;5`?>{e;10;6?4?:1y'2`<5;2c>m7>5$7f9<3=#>o0!0c21<0(;h57b98yv5b2909w0:6:2a896`=>11/=o4;0:p71<72;q6844<3:?13?0?3-;i6?64}r56>5<6s4>26::4$6491d=z{;<1<70>m6s|2g83>7}:<009i63<0;7b?xu4?3:1>v3;9;16?85?22?;0(:85699~w17=83;p1>h55`9'33<2i2wx??4?:0y>75<102.<:787;|q0f?6=9r784787;%55>3>;6=4?{%55>3>3>51zm6c<728qvb>>50;3xyk56290:wp`<2;295~{i;:0;66=4>{|l02?6=9rwe?:4?:0y~j6>=83;pqc=6:182x{zuIJHw98596d63<5fuIJIw=sO@Qy~DE \ No newline at end of file Index: cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX.asy =================================================================== --- cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX.asy (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX.asy (revision 3) @@ -0,0 +1,41 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 FIFORX +RECTANGLE Normal 32 32 800 4064 +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName rst +PINATTR Polarity IN +LINE Normal 0 208 32 208 +PIN 0 208 LEFT 36 +PINATTR PinName wr_clk +PINATTR Polarity IN +LINE Wide 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName din[7:0] +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName wr_en +PINATTR Polarity IN +LINE Normal 0 464 32 464 +PIN 0 464 LEFT 36 +PINATTR PinName full +PINATTR Polarity OUT +LINE Normal 832 240 800 240 +PIN 832 240 RIGHT 36 +PINATTR PinName rd_clk +PINATTR Polarity IN +LINE Wide 832 272 800 272 +PIN 832 272 RIGHT 36 +PINATTR PinName dout[7:0] +PINATTR Polarity OUT +LINE Normal 832 304 800 304 +PIN 832 304 RIGHT 36 +PINATTR PinName rd_en +PINATTR Polarity IN +LINE Normal 832 496 800 496 +PIN 832 496 RIGHT 36 +PINATTR PinName empty +PINATTR Polarity OUT + Index: cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX_flist.txt =================================================================== --- cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX_flist.txt (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX_flist.txt (revision 3) @@ -0,0 +1,60 @@ +# Output products list for +FIFORX.asy +FIFORX.gise +FIFORX.ngc +FIFORX.sym +FIFORX.v +FIFORX.veo +FIFORX.xco +FIFORX.xise +FIFORX\doc\fifo_generator_v9_1_vinfo.html +FIFORX\example_design\FIFORX_exdes.ucf +FIFORX\example_design\FIFORX_exdes.vhd +FIFORX\example_design\FIFORX_exdes.xdc +FIFORX\fifo_generator_v9_1_readme.txt +FIFORX\implement\implement.bat +FIFORX\implement\implement.sh +FIFORX\implement\implement_synplify.bat +FIFORX\implement\implement_synplify.sh +FIFORX\implement\planAhead_ise.bat +FIFORX\implement\planAhead_ise.sh +FIFORX\implement\planAhead_ise.tcl +FIFORX\implement\planAhead_rdn.bat +FIFORX\implement\planAhead_rdn.sh +FIFORX\implement\planAhead_rdn.tcl +FIFORX\implement\xst.prj +FIFORX\implement\xst.scr +FIFORX\simulation\FIFORX_dgen.vhd +FIFORX\simulation\FIFORX_dverif.vhd +FIFORX\simulation\FIFORX_pctrl.vhd +FIFORX\simulation\FIFORX_pkg.vhd +FIFORX\simulation\FIFORX_rng.vhd +FIFORX\simulation\FIFORX_synth.vhd +FIFORX\simulation\FIFORX_tb.vhd +FIFORX\simulation\functional\simulate_isim.bat +FIFORX\simulation\functional\simulate_isim.sh +FIFORX\simulation\functional\simulate_mti.bat +FIFORX\simulation\functional\simulate_mti.do +FIFORX\simulation\functional\simulate_mti.sh +FIFORX\simulation\functional\simulate_ncsim.bat +FIFORX\simulation\functional\simulate_vcs.bat +FIFORX\simulation\functional\ucli_commands.key +FIFORX\simulation\functional\vcs_session.tcl +FIFORX\simulation\functional\wave_isim.tcl +FIFORX\simulation\functional\wave_mti.do +FIFORX\simulation\functional\wave_ncsim.sv +FIFORX\simulation\timing\simulate_isim.bat +FIFORX\simulation\timing\simulate_isim.sh +FIFORX\simulation\timing\simulate_mti.bat +FIFORX\simulation\timing\simulate_mti.do +FIFORX\simulation\timing\simulate_mti.sh +FIFORX\simulation\timing\simulate_ncsim.bat +FIFORX\simulation\timing\simulate_vcs.bat +FIFORX\simulation\timing\ucli_commands.key +FIFORX\simulation\timing\vcs_session.tcl +FIFORX\simulation\timing\wave_isim.tcl +FIFORX\simulation\timing\wave_mti.do +FIFORX\simulation\timing\wave_ncsim.sv +FIFORX_flist.txt +FIFORX_xmdf.tcl +_xmsgs\pn_parser.xmsgs Index: cheap_ethernet/trunk/Ethernet_test/ipcore_dir/DCMMAIN.v =================================================================== --- cheap_ethernet/trunk/Ethernet_test/ipcore_dir/DCMMAIN.v (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/ipcore_dir/DCMMAIN.v (revision 3) @@ -0,0 +1,75 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version : 14.1 +// \ \ Application : xaw2verilog +// / / Filename : DCMMAIN.v +// /___/ /\ Timestamp : 08/24/2012 12:52:08 +// \ \ / \ +// \___\/\___\ +// +//Command: xaw2verilog -st C:\Projects\Xilinx\Ethernet\ipcore_dir\.\DCMMAIN.xaw C:\Projects\Xilinx\Ethernet\ipcore_dir\.\DCMMAIN +//Design Name: DCMMAIN +//Device: xc3s500e-4pq208 +// +// Module DCMMAIN +// Generated by Xilinx Architecture Wizard +// Written for synthesis tool: XST +`timescale 1ns / 1ps + +module DCMMAIN(CLKIN_IN, + RST_IN, + CLKDV_OUT, + CLKIN_IBUFG_OUT, + CLK0_OUT); + + input CLKIN_IN; + input RST_IN; + output CLKDV_OUT; + output CLKIN_IBUFG_OUT; + output CLK0_OUT; + + wire CLKDV_BUF; + wire CLKFB_IN; + wire CLKIN_IBUFG; + wire CLK0_BUF; + wire GND_BIT; + + assign GND_BIT = 0; + assign CLKIN_IBUFG_OUT = CLKIN_IBUFG; + assign CLK0_OUT = CLKFB_IN; + BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF), + .O(CLKDV_OUT)); + IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN), + .O(CLKIN_IBUFG)); + BUFG CLK0_BUFG_INST (.I(CLK0_BUF), + .O(CLKFB_IN)); + DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.5), .CLKFX_DIVIDE(1), + .CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"), + .CLKIN_PERIOD(20.000), .CLKOUT_PHASE_SHIFT("NONE"), + .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"), + .DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"), + .FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") ) + DCM_SP_INST (.CLKFB(CLKFB_IN), + .CLKIN(CLKIN_IBUFG), + .DSSEN(GND_BIT), + .PSCLK(GND_BIT), + .PSEN(GND_BIT), + .PSINCDEC(GND_BIT), + .RST(RST_IN), + .CLKDV(CLKDV_BUF), + .CLKFX(), + .CLKFX180(), + .CLK0(CLK0_BUF), + .CLK2X(), + .CLK2X180(), + .CLK90(), + .CLK180(), + .CLK270(), + .LOCKED(), + .PSDONE(), + .STATUS()); +endmodule Index: cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX_xmdf.tcl =================================================================== --- cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX_xmdf.tcl (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/ipcore_dir/FIFORX_xmdf.tcl (revision 3) @@ -0,0 +1,263 @@ +# The package naming convention is _xmdf +package provide FIFORX_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::FIFORX_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::FIFORX_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name FIFORX +} +# ::FIFORX_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::FIFORX_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/doc/fifo_generator_v9_1_vinfo.html +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/example_design/FIFORX_exdes.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/example_design/FIFORX_exdes.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/example_design/FIFORX_exdes.xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/fifo_generator_v9_1_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/implement/implement.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/implement/implement.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/implement/implement_synplify.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/implement/implement_synplify.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/implement/planAhead_ise.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/implement/planAhead_ise.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/implement/planAhead_ise.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/implement/planAhead_rdn.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/implement/planAhead_rdn.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/implement/planAhead_rdn.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/implement/xst.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/implement/xst.scr +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/FIFORX_dgen.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/FIFORX_dverif.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/FIFORX_pctrl.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/FIFORX_pkg.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/FIFORX_rng.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/FIFORX_synth.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/FIFORX_tb.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/functional/simulate_isim.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/functional/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/functional/simulate_mti.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/functional/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/functional/simulate_mti.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/functional/simulate_ncsim.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/functional/simulate_vcs.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/functional/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/functional/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/functional/wave_isim.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/functional/wave_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/functional/wave_ncsim.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/timing/simulate_isim.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/timing/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/timing/simulate_mti.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/timing/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/timing/simulate_mti.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/timing/simulate_ncsim.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/timing/simulate_vcs.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/timing/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/timing/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/timing/wave_isim.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/timing/wave_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX/simulation/timing/wave_ncsim.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX.sym +utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FIFORX_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module FIFORX +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams Index: cheap_ethernet/trunk/Ethernet_test/ethernet_test.v =================================================================== --- cheap_ethernet/trunk/Ethernet_test/ethernet_test.v (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/ethernet_test.v (revision 3) @@ -0,0 +1,291 @@ +`timescale 1ns / 1ps +`include "const.vh" +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: Ivan Krutov (grvfrv@gmail.com) +// +// Create Date: 10:36:10 08/28/2012 +// Design Name: Cheap Ethernet test project +// Module Name: ethernet_test +// Project Name: Cheap Ethernet +// Target Devices: Spartan 3E +// Tool versions: ISE 14.1 +// Description: Base functional of ARP, ICMP, UDP server, UDP client. +// +// Dependencies: EthernetRX.v, EthernetTX.v, TENBASET_RxD.v, TENBASET_TxD.v, +// const.vh +// Revision: +// Revision 0.9 beta +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module ethernet_test(clk_in, + Ethernet_RDp, Ethernet_RDm, Ethernet_TDp, Ethernet_TDm, Ethernet_LED_Link, Ethernet_LED_Act, + PushButton, LED_Test); + +input clk_in; // 50 MHz +input Ethernet_RDp, Ethernet_RDm; // Ethernel input +output Ethernet_TDp, Ethernet_TDm; // Ethernel output +output Ethernet_LED_Link; // Ethernet link - Not realized! (VCC) +output Ethernet_LED_Act; // Etheret activity (low - active) +input PushButton; // Pushbutton for send data test +output LED_Test; + +// Server config +wire [31:0] HostIP = 32'hC0A8012C; // 192.168.1.44 +wire [47:0] HostMAC = 48'h001234567890; +wire [15:0] HostPort = 16'd1024; + +// Client config +wire [31:0] RemoteIP = 32'hC0A80102; // 192.168.1.2 +reg [47:0] RemoteMAC = 48'h0; +wire [15:0] RemotePort = 16'd1024; + +wire clk20, clk50; +wire Ethernet_RD; + +reg SendStart = 0; +wire SendDataReq; +reg [7:0] SendData = 0; +reg [9:0] SendDataLen = 0; +wire [9:0] SendDataPos; +wire SendingPacket; +reg [2:0] SendPacketType = 0; + +reg [31:0] SendToIP = 32'h0; +reg [47:0] SendToMAC = 48'h0; +reg [15:0] SendToPort = 16'h0; + +wire RcvStart, RcvStop; +wire [7:0] RcvData; +wire [9:0] RcvDataLen; +wire [9:0] RcvDataPos; +wire RcvDataAvailable; +wire RcvCRCValid; +wire ReceivingPacket; +wire [2:0] RcvPacketType; +wire [31:0] RcvFromIP; +wire [47:0] RcvFromMAC; +wire [15:0] RcvFromPort; +wire [15:0] RcvICMPId; +wire [15:0] RcvICMPSeq; +wire [15:0] RcvICMPCRC; + +wire Ethernet_LED_Link = 1; +reg Ethernet_LED_Act = 0; +reg LED_Test = 0; +reg last_btn_st = 0; + +reg PacketReceived = 0; +reg PacketProcessed = 0; +reg [7:0] Cmd = 0; +reg [7:0] Arg = 0; +reg SendReq = 0; + +reg [2:0] SavedPacketType = 0; +reg [9:0] SavedDataLen = 0; +reg [15:0] SavedPort = 0; +reg SavedEcho = 0; +reg Echo = 0; + +wire [16:0] SendICMPCRC1 = {RcvICMPCRC[15:8] + 9'h08, RcvICMPCRC[7:0]}; +wire [15:0] SendICMPCRC2 = SendICMPCRC1[15:0] + SendICMPCRC1[16]; + +wire [7:0] FIFOOut; +wire FIFOFull; +wire FIFOEmpty; + + +DCMMAIN DCMMAIN1 ( + .CLKIN_IN(clk_in), // 50 MHz + .RST_IN(1'b0), + .CLKDV_OUT(), + .CLKFX_OUT(clk20), + .CLKIN_IBUFG_OUT(), + .CLK0_OUT(clk50), + .LOCKED_OUT()); + + IBUFDS #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for + // the buffer: "0"-"12" (Spartan-3E) + .IFD_DELAY_VALUE("0"), // Specify the amount of added delay for input + // register: "AUTO", "0"-"6" (Spartan-3E) + .IOSTANDARD("DIFF_HSTL_III_18") // Specify the input I/O standard + ) IBUFDS_EthRD ( + .O(Ethernet_RD), // Buffer output + .I(Ethernet_RDp), // Diff_p buffer input (connect directly to top-level port) + .IB(Ethernet_RDm) // Diff_n buffer input (connect directly to top-level port) + ); + +FIFORX FIFO_RD ( + .rst(RcvStart), // input rst + .wr_clk(clk50), // input wr_clk + .rd_clk(clk20), // input rd_clk + .din(RcvData), // input [7 : 0] din + .wr_en(RcvDataAvailable), // input wr_en + .rd_en(SendDataReq /*&& SendingPacket*/), // input rd_en + .dout(FIFOOut), // output [7 : 0] dout + .full(FIFOFull), // output full + .empty(FIFOEmpty) // output empty +); + +EthernetTX EthTX1 (clk20, + HostIP, SendToIP, HostMAC, SendToMAC, HostPort, SendToPort, + SendStart, SendDataReq, SendData, SendDataLen, SendDataPos, SendingPacket, + SendPacketType, RcvICMPId, RcvICMPSeq, SendICMPCRC2, + Ethernet_TDp, Ethernet_TDm); + +EthernetRX EthRX1 (clk50, + Ethernet_RD, + HostIP, HostMAC, HostPort, + RcvStart, RcvStop, RcvData, RcvDataLen, RcvDataPos, RcvDataAvailable, RcvCRCValid, ReceivingPacket, + RcvPacketType, RcvICMPId, RcvICMPSeq, RcvICMPCRC, + RcvFromIP, RcvFromMAC, RcvFromPort); + + +// Ethernet LEDs +reg [19:0] EthLEDCnt = 0; +always @(posedge clk20) begin + EthLEDCnt <= EthLEDCnt + 1; + Ethernet_LED_Act <= Ethernet_LED_Act && !(ReceivingPacket | SendingPacket); + if (Ethernet_LED_Act) + EthLEDCnt <= 0; + if (&EthLEDCnt) + Ethernet_LED_Act <= 1; +end + +// Transmit packets +always @(posedge clk20) begin + SendStart = 0; + if (!SendingPacket && (PacketReceived || SendReq) && !PacketProcessed) + begin + Echo <= 0; + PacketProcessed <= 1; + SendToIP <= RcvFromIP; + SendToMAC <= RcvFromMAC; + + if (RcvPacketType == `ARPReply) // Remote MAC resolved + begin + RemoteMAC = RcvFromMAC; + SendToPort = SavedPort; + SendStart = 1; + SendPacketType = SavedPacketType; + SendDataLen = SavedDataLen; + Echo <= SavedEcho; + end + else if ((RcvPacketType == `UDP) || SendReq) // Send UDP packet + begin + if (SendReq) + begin + SendToIP <= RemoteIP; + SendToMAC <= RemoteMAC; + end + else if (Cmd == `CmdDataEcho) + Echo <= 1; + SendToPort = RemotePort; + SendStart = 1; + SendPacketType = `UDP; + SendDataLen = SendReq ? 18 : RcvDataLen; + end + else if (RcvPacketType == `ARPReq) // Send ARP reply + begin + SendStart = 1; + SendPacketType = `ARPReply; + SendDataLen = 18; + end + else if (RcvPacketType == `ICMPReq) // Send ICMP reply + begin + Echo <= 1; + SendStart = 1; + SendPacketType = `ICMPReply; + SendDataLen = RcvDataLen; + end + + if (~|RemoteMAC && SendStart && SendReq) // If remote MAC unknown send ARP request + begin // TODO: clear RemoteMAC after 2 minutes inactivity + SavedPacketType <= SendPacketType; + SavedDataLen <= SendDataLen; + SavedPort <= SendToPort; + SavedEcho <= Echo; + SendToIP <= RemoteIP; + SendStart = 1; + SendPacketType = `ARPReq; + SendDataLen = 18; + end + end + + if (!PacketReceived && !SendReq) + PacketProcessed <= 0; + + case (SendDataPos) + 0: SendData <= Cmd; + 1: SendData <= Arg; + default: SendData <= 0; + endcase + + if (Echo /*RcvPacketType == `ICMPReq*/) // Cmd: Data echo + SendData <= FIFOOut; +end + + +reg [25:0] cnt = 0; +reg AutoSend = 1; + +// Receive packets +always @(posedge clk50) begin + if (~&cnt) + cnt <= cnt + 1; + + if (PacketProcessed) + begin + PacketReceived <= 0; + SendReq <= 0; + end + + if (RcvDataAvailable) + if (RcvPacketType == `UDP) + case (RcvDataPos) + 0: Cmd <= RcvData; + 1: Arg <= RcvData; + endcase + + if (RcvStop && RcvCRCValid) + begin + PacketReceived <= 1; + if (RcvPacketType == `UDP) + begin + if (Cmd == `CmdLEDCtrl) // Received Cmd: Leds control + begin + LED_Test <= Arg[0]; + Cmd <= `CmdDone; // Send reply: Cmd: Done + end + else if (Cmd == `CmdStatus) // Received Cmd: Get Status + begin + Cmd <= `CmdStatus; // Send reply: Cmd: Status + Arg <= {5'd0, PushButton, AutoSend, LED_Test}; // Status + end + else if (Cmd == `CmdSetConfig)// Received Cmd: Set Config + begin + Cmd <= `CmdDone; // Send reply: Cmd: Status + AutoSend <= Arg[0]; + end + end + end + + if (!SendingPacket && !ReceivingPacket && !PacketProcessed) + begin + last_btn_st <= PushButton; + if (last_btn_st != PushButton || (&cnt && AutoSend)) + begin + cnt <= 0; + Cmd <= `CmdSwChanged; // Cmd: Pushbuttons state changed + if (&cnt) + Cmd <= `CmdStatus; + Arg <= {8{PushButton}}; + SendReq <= 1; + end + end +end + +endmodule Index: cheap_ethernet/trunk/Ethernet_test/ethernet_test_tb_ping.v =================================================================== --- cheap_ethernet/trunk/Ethernet_test/ethernet_test_tb_ping.v (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/ethernet_test_tb_ping.v (revision 3) @@ -0,0 +1,851 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11:08:22 08/27/2012 +// Design Name: ethernet_test +// Module Name: C:/Projects/Xilinx/Ethernet/ethernet_test_tb.v +// Project Name: Ethernet +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: ethernet_test +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module ethernet_test_tb_ping; + + // Inputs + reg clk_in; + reg Ethernet_RDp; + reg Ethernet_RDm; + reg PushButton; + + // Outputs + wire Ethernet_TDp; + wire Ethernet_TDm; + wire Ethernet_LED_Link; + wire Ethernet_LED_Act; + wire LED_Test; + + + // Instantiate the Unit Under Test (UUT) + ethernet_test uut ( + .clk_in(clk_in), + .Ethernet_RDp(Ethernet_RDp), + .Ethernet_RDm(Ethernet_RDm), + .Ethernet_TDp(Ethernet_TDp), + .Ethernet_TDm(Ethernet_TDm), + .Ethernet_LED_Link(Ethernet_LED_Link), + .Ethernet_LED_Act(Ethernet_LED_Act), + .PushButton(PushButton), + .LED_Test(LED_Test) + ); + + initial begin + // Initialize Inputs + clk_in = 0; + Ethernet_RDp = 0; + Ethernet_RDm = 0; + PushButton = 0; + + // Wait 1000 ns for global reset to finish + #1000; + // 8'h55 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h55 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h55 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h55 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h55 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h55 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h55 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'hD5 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + // 8'h00 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h12 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h34 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h56 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h78 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h90 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + // 8'h00 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h01 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h29 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'hd1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + // 8'h6c + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h98 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + // 8'h08 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h00 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h45 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h00 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h00 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h3c + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h3e + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'hbf + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + // 8'h00 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h00 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h80 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + // 8'h01 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h78 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h83 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + // 8'hc0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + // 8'ha8 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + // 8'h01 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h02 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'hc0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + // 8'ha8 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + // 8'h01 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h2c + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h08 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h00 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h41 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h5b + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h04 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h00 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h08 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h01 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h61 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h62 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h63 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h64 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h65 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h66 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h67 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h68 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h69 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h6a + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h6b + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h6c + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h6d + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h6e + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h6f + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h70 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h71 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h72 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h73 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h74 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h75 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h76 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h77 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h61 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h62 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h63 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h64 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h65 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h66 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h67 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h68 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'h69 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + // 8'hC8 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + // 8'h95 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + // 8'hE6 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + // 8'hE0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 0; Ethernet_RDm = 1; #50; Ethernet_RDp = 1; Ethernet_RDm = 0; // 0 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + #50; Ethernet_RDp = 1; Ethernet_RDm = 0; #50; Ethernet_RDp = 0; Ethernet_RDm = 1; // 1 + + + end + + + parameter PERIOD = 20; + always begin + clk_in = 1'b0; + #(PERIOD/2) clk_in = 1'b1; + #(PERIOD/2); + end + + +endmodule + Index: cheap_ethernet/trunk/Ethernet_test/ethernet_test.xise =================================================================== --- cheap_ethernet/trunk/Ethernet_test/ethernet_test.xise (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/ethernet_test.xise (revision 3) @@ -0,0 +1,411 @@ + + + +

+ + + + + + + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: cheap_ethernet/trunk/Ethernet_test/TENBASET_RxD.v =================================================================== --- cheap_ethernet/trunk/Ethernet_test/TENBASET_RxD.v (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/TENBASET_RxD.v (revision 3) @@ -0,0 +1,91 @@ +`timescale 1ns / 1ps +// 10BASE-T receiving interface (based on fpga4fun.com version) +module TENBASET_RxD(clk48, + manchester_data_in, + RcvData, RcvStart, RcvStop, new_bit_available, new_byte_available, end_of_Ethernet_frame, sync2); + +input clk48; +input manchester_data_in; +output [7:0] RcvData; +output RcvStart; +output RcvStop; +output new_bit_available; +output new_byte_available; +output end_of_Ethernet_frame; +output [9:0] sync2; + +reg [7:0] RcvData = 0; +reg RcvStart = 0; +reg RcvStop = 0; +reg new_bit_available = 0; +reg end_of_Ethernet_frame = 0; + +reg [2:0] in_data = 0; +reg [1:0] cnt = 0; +reg [2:0] transition_timeout = 0; +reg [4:0] sync1 = 0; +reg [9:0] sync2 = 0; + +wire new_byte_available = ((new_bit_available) && (sync2[2:0] == 3'h0) && (sync2[9:3] != 0)); + +always @(posedge clk48) begin + in_data <= {in_data[1:0], manchester_data_in}; + new_bit_available <= (cnt == 3); + if (|cnt || (in_data[2] ^ in_data[1])) + cnt <= cnt + 1; + if (cnt == 3) + RcvData <= {in_data[1], RcvData[7:1]}; +end + +///////////////////////////////////////////////// +always @(posedge clk48) begin + if (end_of_Ethernet_frame) + sync1 <= 0; + else if (new_bit_available) + begin + if (!(RcvData == 8'h55 || RcvData == 8'hAA)) // not preamble? + sync1 <= 0; + else if (~&sync1) // if all bits of this "sync1" counter are one, we decide that enough of the preamble + // has been received, so stop counting and wait for "sync2" to detect the SFD + sync1 <= sync1 + 1; // otherwise keep counting + end +end + +always @(posedge clk48) begin + RcvStart <= 0; + if (end_of_Ethernet_frame) + sync2 <= 0; + else if (new_bit_available) + begin + if (|sync2) // if the SFD has already been detected (Ethernet data is coming in) + begin + sync2 <= sync2 + 1; // then count the bits coming in + if (&sync2) + sync2 <= 8; + end + else if (&sync1 && RcvData == 8'hD5) // otherwise, let's wait for the SFD (0xD5) + begin + RcvStart <= 1; + sync2 <= 1; + end + end +end + +///////////////////////////////////////////////// +// if no clock transistion is detected for some time, that's the end of the Ethernet frame + +always @(posedge clk48) begin + if (in_data[2] ^ in_data[1]) + transition_timeout <= 0; + else if (~&cnt) + transition_timeout <= transition_timeout + 1; +end + +always @(posedge clk48) begin + RcvStop <= 0; + end_of_Ethernet_frame <= &transition_timeout; + if (!end_of_Ethernet_frame && &transition_timeout && |sync2) + RcvStop <= 1; +end + +endmodule Index: cheap_ethernet/trunk/Ethernet_test/DCMMAIN_arwz.ucf =================================================================== --- cheap_ethernet/trunk/Ethernet_test/DCMMAIN_arwz.ucf (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/DCMMAIN_arwz.ucf (revision 3) @@ -0,0 +1,17 @@ +# Generated by Xilinx Architecture Wizard +# --- UCF Template Only --- +# Cut and paste these attributes into the project's UCF file, if desired +INST DCM_SP_INST CLK_FEEDBACK = 1X; +INST DCM_SP_INST CLKDV_DIVIDE = 5.0; +INST DCM_SP_INST CLKFX_DIVIDE = 5; +INST DCM_SP_INST CLKFX_MULTIPLY = 2; +INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; +INST DCM_SP_INST CLKIN_PERIOD = 20.000; +INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; +INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; +INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; +INST DCM_SP_INST FACTORY_JF = C080; +INST DCM_SP_INST PHASE_SHIFT = 0; +INST DCM_SP_INST STARTUP_WAIT = FALSE; Index: cheap_ethernet/trunk/Ethernet_test/TENBASET_TxD.v =================================================================== --- cheap_ethernet/trunk/Ethernet_test/TENBASET_TxD.v (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/TENBASET_TxD.v (revision 3) @@ -0,0 +1,65 @@ +`timescale 1ns / 1ps +// 10BASE-T transmit interface (based on fpga4fun.com version) +module TENBASET_TxD(clk20, + SendingPacket, pkt_data, rdaddress, ShiftData, ShiftCount, CRCflush, CRC, readram, + Ethernet_TDp, Ethernet_TDm); + +input clk20; // a 20MHz clock (this code won't work with a different frequency) +input [7:0] pkt_data; +output [10:0] rdaddress; +input SendingPacket; +output ShiftData; +output [3:0] ShiftCount; +input CRCflush; +input CRC; +output readram; +output Ethernet_TDp, Ethernet_TDm; // the two differential 10BASE-T outputs + + +reg [10:0] rdaddress = 0; +reg [3:0] ShiftCount = 0; +wire readram = (ShiftCount == 15); +reg [7:0] ShiftData = 0; +reg [17:0] LinkPulseCount = 0; +reg LinkPulse = 0; +reg SendingPacketData = 0; +reg [2:0] idlecount = 0; +reg qo = 0; +reg qoe = 0; +reg Ethernet_TDp = 0; +reg Ethernet_TDm = 0; + + +////////////////////////////////////////////////////////////////////// +// 10BASE-T's magic + +always @(posedge clk20) begin + ShiftCount <= SendingPacket ? ShiftCount + 1 : 15; + if (ShiftCount == 15) + rdaddress <= SendingPacket ? rdaddress + 1 : 0; + if (ShiftCount[0]) + ShiftData <= readram ? pkt_data : {1'b0, ShiftData[7:1]}; +end + +// generate the NLP +always @(posedge clk20) begin + LinkPulseCount <= SendingPacket ? 0 : LinkPulseCount + 1; + LinkPulse <= &LinkPulseCount[17:1]; +end + +wire dataout = CRCflush ? CRC : ShiftData[0]; + +// TP_IDL, shift-register and manchester encoder +always @(posedge clk20) begin + SendingPacketData <= SendingPacket; + if (SendingPacketData) + idlecount <= 0; + else if (~&idlecount) + idlecount <= idlecount + 1; + qo <= SendingPacketData ? ~dataout ^ ShiftCount[0] : 1; + qoe <= SendingPacketData | LinkPulse | (idlecount < 6); + Ethernet_TDp <= (qoe ? qo : 1'b0); + Ethernet_TDm <= (qoe ? ~qo : 1'b0); +end + +endmodule Index: cheap_ethernet/trunk/Ethernet_test/ethernet_test.ucf =================================================================== --- cheap_ethernet/trunk/Ethernet_test/ethernet_test.ucf (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/ethernet_test.ucf (revision 3) @@ -0,0 +1,26 @@ +NET "clk_in" LOC = P183; +NET "clk_in" TNM_NET = "clk_in"; +TIMESPEC TS_CLK_IN = PERIOD "clk_in" 20000 ps; + +#NET "Ethernet_TDm" LOC = P55; +#NET "Ethernet_TDp" LOC = P61; +NET "Ethernet_TDp" DRIVE = 6; +NET "Ethernet_TDm" DRIVE = 6; + +NET "Ethernet_TDp" LOC = P82; +NET "Ethernet_TDm" LOC = P83; + +NET "Ethernet_RDp" IOSTANDARD = DIFF_HSTL_III_18; +NET "Ethernet_RDp" LOC = P62; +NET "Ethernet_RDm" IOSTANDARD = DIFF_HSTL_III_18; +NET "Ethernet_RDm" LOC = P63; + +NET "Ethernet_LED_Link" LOC = P84; +NET "Ethernet_LED_Link" DRIVE = 2; +NET "Ethernet_LED_Act" LOC = P86; +NET "Ethernet_LED_Act" DRIVE = 2; + +NET "LED_Test" LOC = P78; + +NET "pushbutton" PULLDOWN; +NET "pushbutton" LOC = P26; Index: cheap_ethernet/trunk/Ethernet_test/ethernet_test.ipf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: cheap_ethernet/trunk/Ethernet_test/ethernet_test.ipf =================================================================== --- cheap_ethernet/trunk/Ethernet_test/ethernet_test.ipf (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/ethernet_test.ipf (revision 3)

cheap_ethernet/trunk/Ethernet_test/ethernet_test.ipf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: cheap_ethernet/trunk/Ethernet_test/EthernetRX.v =================================================================== --- cheap_ethernet/trunk/Ethernet_test/EthernetRX.v (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/EthernetRX.v (revision 3) @@ -0,0 +1,284 @@ +`timescale 1ns / 1ps +`include "const.vh" +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: Ivan Krutov (grvfrv@gmail.com) +// +// Create Date: 10:39:30 08/29/2012 +// Design Name: +// Module Name: EthernetRX +// Project Name: Cheap Ethernet +// Target Devices: Spartan 3E +// Tool versions: ISE 14.1 +// Description: Base functional or ARP, ICMP, UDP +// +// Dependencies: TENBASET_RxD.v, const.vh +// +// Revision: +// Revision 0.9 beta +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module EthernetRX(clk50, + Ethernet_RD, + HostIP, HostMAC, HostPort, + RcvStart, RcvStop, RcvData, RcvDataLen, RcvDataPos, RcvDataAvailable, RcvCRCValid, ReceivingPacket, + RcvPacketType, RcvICMPId, RcvICMPSeq, RcvICMPCRC, + RcvFromIP, RcvFromMAC, RcvFromPort); + +input clk50; +input Ethernet_RD; +input [31:0] HostIP; +input [47:0] HostMAC; +input [15:0] HostPort; + +output RcvStart; +output RcvStop; +output [7:0] RcvData; +output [9:0] RcvDataLen; +output [9:0] RcvDataPos; +output RcvDataAvailable; +output [31:0] RcvFromIP; +output [47:0] RcvFromMAC; +output [15:0] RcvFromPort; +output RcvCRCValid; +output ReceivingPacket; +output [2:0] RcvPacketType; +output [15:0] RcvICMPId; +output [15:0] RcvICMPSeq; +output [15:0] RcvICMPCRC; + + +wire [7:0] RcvData; +wire RcvStop; +wire new_bit_available; +wire new_byte_available; +wire end_of_Ethernet_frame; +wire [9:0] sync2; +reg [31:0] RcvFromIP = 0; +reg [47:0] RcvFromMAC = 0; +reg [15:0] RcvFromPort = 0; +//reg RcvStart = 0; +reg [9:0] RcvDataLen = 0; +reg [9:0] RcvDataPos = 0; +reg RcvDataAvailable = 0; +reg RcvUserData = 0; +reg RcvCRCValid = 0; +reg [2:0] RcvPacketType = 0; +reg [15:0] RcvICMPId = 0; +reg [15:0] RcvICMPSeq = 0; +reg [15:0] RcvICMPCRC = 0; + +reg IgnorePacket = 0; +reg [7:0] tmp = 0; +reg CRCinit = 0; +reg [31:0] CRC = 0; +reg [4:0] CRCcnt = 0; +reg CRCflush = 0; +reg MACValid = 0; +reg BroadcastValid = 0; +reg Broadcast = 0; +reg ARP = 0; +reg ICMP = 0; + +assign ReceivingPacket = |sync2[9:3]; //~end_of_Ethernet_frame; + +TENBASET_RxD TENBASET_RxD1 (clk50, + Ethernet_RD, + RcvData, RcvStart, RcvStop, new_bit_available, new_byte_available, end_of_Ethernet_frame, sync2); + +// generate the CRC32 +wire CRCinput = CRCflush ? 0 : RcvData[7] ^ CRC[31]; +always @(posedge clk50) begin + CRCinit <= (!RcvUserData && sync2 == 0); + if (new_bit_available) + CRC <= CRCinit ? ~0 : ({CRC[30:0], 1'b0} ^ ({32{CRCinput}} & 32'h04C11DB7)); + + if (end_of_Ethernet_frame) + begin + CRCcnt <= 0; + RcvCRCValid <= 0; + end + + if (new_bit_available && CRCflush && (~CRC[31] == RcvData[7])) + begin + CRCcnt <= CRCcnt + 1; + if (&CRCcnt) + RcvCRCValid <= 1; + end +end + +// Packet disasembling +always @(posedge clk50) begin + RcvDataAvailable <= 0; + if (end_of_Ethernet_frame) + begin + BroadcastValid <= 1; + MACValid <= 1; + ARP <= 0; + ICMP <= 0; + Broadcast <= 0; + CRCflush <= 0; + RcvUserData <= 0; + RcvDataPos = 0; + IgnorePacket <= 0; + end + + if (new_byte_available && !IgnorePacket) + begin + if (!RcvUserData) + case (sync2[9:3]) + 01: begin + RcvPacketType <= `Unknown; + if (RcvData != 8'hFF) + BroadcastValid <= 0; + if (RcvData != HostMAC[47:40]) + MACValid <= 0; + end + 02: begin + if (RcvData != 8'hFF) + BroadcastValid <= 0; + if (RcvData != HostMAC[39:32]) + MACValid <= 0; end + 03: begin + if (RcvData != 8'hFF) + BroadcastValid <= 0; + if (RcvData != HostMAC[31:24]) + MACValid <= 0; + end + 04: begin + if (RcvData != 8'hFF) + BroadcastValid <= 0; + if (RcvData != HostMAC[23:16]) + MACValid <= 0; + end + 05: begin + if (RcvData != 8'hFF) + BroadcastValid <= 0; + if (RcvData != HostMAC[15:8]) + MACValid <= 0; + end + 06: begin + if (RcvData != 8'hFF) + BroadcastValid <= 0; + if (RcvData != HostMAC[7:0]) + MACValid <= 0; + end + 07: begin + RcvFromMAC[47:40] <= RcvData; + if (BroadcastValid) + Broadcast <= 1; + else if (!MACValid) + IgnorePacket <= 1; + end + 08: RcvFromMAC[39:32] <= RcvData; + 09: RcvFromMAC[31:24] <= RcvData; + 10: RcvFromMAC[23:16] <= RcvData; + 11: RcvFromMAC[15:8] <= RcvData; + 12: RcvFromMAC[7:0] <= RcvData; + + 13: if (RcvData != 8) IgnorePacket <= 1; // protocol type + 14: if (RcvData == 6) ARP <= 1; + 17: tmp <= RcvData; // ICMP length + 18: RcvDataLen <= {tmp, RcvData} - 28; // ICMP length + 21: tmp <= RcvData; + 22: if (ARP) + if (tmp == 8'h00) + begin + RcvDataLen <= 18; + if (RcvData == 8'h01 && Broadcast) + RcvPacketType <= `ARPReq; + else if (RcvData == 8'h02) + RcvPacketType <= `ARPReply; + end + 23: if (ARP) RcvFromMAC[47:40] <= RcvData; + 24: if (ARP) + RcvFromMAC[39:32] <= RcvData; + else if (RcvData == 1) + ICMP <= 1; + else if (RcvData == 17) + RcvPacketType <= `UDP; + 25: if (ARP) RcvFromMAC[31:24] <= RcvData; + 26: if (ARP) RcvFromMAC[23:16] <= RcvData; + 27: if (ARP) + RcvFromMAC[15:8] <= RcvData; + else + RcvFromIP[31:24] <= RcvData; + 28: if (ARP) + RcvFromMAC[7:0] <= RcvData; + else + RcvFromIP[23:16] <= RcvData; + 29: if (ARP) + RcvFromIP[31:24] <= RcvData; + else + RcvFromIP[15:8] <= RcvData; + 30: if (ARP) + RcvFromIP[23:16] <= RcvData; + else + RcvFromIP[7:0] <= RcvData; + 31: if (ARP) RcvFromIP[15:8] <= RcvData; + 32: if (ARP) RcvFromIP[7:0] <= RcvData; + + 35: if (ICMP) begin + if (RcvData == 8) + RcvPacketType <= `ICMPReq; + end + else + RcvFromPort[15:8] <= RcvData; + 36: RcvFromPort[7:0] <= RcvData; + 37: if (!ARP) + if (ICMP) + RcvICMPCRC[15:8] <= RcvData; + else if (RcvData != HostPort[15:8]) + IgnorePacket <= 1; + 38: if (!ARP) + if (ICMP) + RcvICMPCRC[7:0] <= RcvData; + else if (RcvData != HostPort[7:0]) + IgnorePacket <= 1; + 39: if (ARP) + begin + if (RcvData != HostIP[31:24]) + IgnorePacket <= 1; + end + else if (ICMP) + RcvICMPId[15:8] <= RcvData; + else + tmp <= RcvData; + 40: if (ARP) begin + if (RcvData != HostIP[23:16]) + IgnorePacket <= 1; + end + else if (ICMP) + RcvICMPId[7:0] <= RcvData; + else + RcvDataLen <= {tmp, RcvData} - 8; + 41: if (ARP) + begin + if (RcvData != HostIP[15:8]) + IgnorePacket <= 1; + end + else if (ICMP) + RcvICMPSeq[15:8] <= RcvData; + 42: if (ARP) begin + if (RcvData != HostIP[7:0]) + IgnorePacket <= 1; + end + else if (ICMP) + RcvICMPSeq[7:0] <= RcvData; + 43: begin + RcvDataAvailable <= 1; + RcvUserData <= 1; + end + endcase + else + begin + RcvDataAvailable <= 1; + RcvDataPos = RcvDataPos + 1; + if (RcvDataPos + 1 == RcvDataLen) + CRCflush <= 1; + end + end +end + +endmodule Index: cheap_ethernet/trunk/Ethernet_test/ethernet_test_summary.html =================================================================== --- cheap_ethernet/trunk/Ethernet_test/ethernet_test_summary.html (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/ethernet_test_summary.html (revision 3) @@ -0,0 +1,79 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

ethernet_test Project Status
Project File:	Ethernet_test.xise	Parser Errors:	No Errors
Module Name:	ethernet_test	Implementation State:	New
Target Device:	xc3s500e-4pq208	Errors:
Product Version:	ISE 14.1	Warnings:
Design Goal:	Balanced	Routing Results:	+
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:		Final Timing Score:

+ + + + + + + + + + + + 
+ + + + + + + + + + +

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report
Translation Report
Map Report
Place and Route Report
Power Report
Post-PAR Static Timing Report
Bitgen Report

+ 
+ + +

Secondary Reports			[-]
Report Name	Status	Generated

+ + +
Date Generated: 09/01/2012 - 00:02:44 + \ No newline at end of file Index: cheap_ethernet/trunk/Ethernet_test/EthernetTX.v =================================================================== --- cheap_ethernet/trunk/Ethernet_test/EthernetTX.v (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/EthernetTX.v (revision 3) @@ -0,0 +1,157 @@ +`timescale 1ns / 1ps +`include "const.vh" +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: Ivan Krutov (grvfrv@gmail.com) +// +// Create Date: 22:59:14 08/28/2012 +// Design Name: +// Module Name: EthernetTX +// Project Name: Cheap Ethernet +// Target Devices: Spartan 3E +// Tool versions: ISE 14.1 +// Description: Base functional or ARP, ICMP, UDP +// +// Dependencies: TENBASET_TxD.v, const.vh +// +// Revision: +// Revision 0.9 beta +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module EthernetTX(clk20, + HostIP, RemoteIP, HostMAC, RemoteMAC, HostPort, RemotePort, + SendStart, SendDataReq, SendData, SendDataLen, SendDataPos, SendingPacket, + SendPacketType, SendICMPId, SendICMPSeq, SendICMPCRC, + Ethernet_TDp, Ethernet_TDm); + +input clk20; +input [31:0] HostIP; +input [31:0] RemoteIP; +input [47:0] HostMAC; +input [47:0] RemoteMAC; +input [15:0] HostPort; +input [15:0] RemotePort; +input SendStart; +input [7:0] SendData; +input [9:0] SendDataLen; +output [9:0] SendDataPos; +output SendingPacket; +output SendDataReq; +input [2:0] SendPacketType; +input [15:0] SendICMPId; +input [15:0] SendICMPSeq; +input [15:0] SendICMPCRC; +output Ethernet_TDp, Ethernet_TDm; + +reg [7:0] pkt_data = 0; + +reg SendingPacket = 0; +wire [10:0] rdaddress; +wire [7:0] ShiftData; +wire [3:0] ShiftCount; +wire readram; + +wire [9:0] SendDataPos = (rdaddress > 12'h32) ? (rdaddress - 12'h32) : 0; +wire [15:0] IPHLen = 8'd20 + 8'd8 + SendDataLen; +wire [15:0] UDPHLen = 8'd8 + SendDataLen; + +reg [31:0] CRC = 0; +reg CRCflush = 0; +reg CRCinit = 0; + +assign SendDataReq = (rdaddress > 8'h30) && readram; + +// calculate the IP checksum, big-endian style +wire [18:0] IPchecksum1 = (SendPacketType == `ICMPReply ? 19'hC51D : 19'hC52D) + SendDataLen + + HostIP[31:16] + HostIP[15:0] + RemoteIP[31:16] + RemoteIP[15:0]; +wire [15:0] IPchecksum2 = ~((IPchecksum1[15:0] + IPchecksum1[18:16])); + + +TENBASET_TxD TENBASET_TxD1 (clk20, + SendingPacket, pkt_data, rdaddress, ShiftData, ShiftCount, CRCflush, ~CRC[31], readram, + Ethernet_TDp, Ethernet_TDm); + + +always @(posedge clk20) begin + if (SendStart) + SendingPacket <= 1; + else if (ShiftCount == 14 && rdaddress == (54 + SendDataLen)) + SendingPacket <= 0; +end + +// generate the CRC32 +wire CRCinput = CRCflush ? 0 : (ShiftData[0] ^ CRC[31]); +always @(posedge clk20) begin + if (CRCflush) + CRCflush <= SendingPacket; + else if (readram) + CRCflush <= (rdaddress == (50 + SendDataLen)); + if (readram) + CRCinit <= (rdaddress == 7); + if (ShiftCount[0]) + CRC <= CRCinit ? ~0 : ({CRC[30:0],1'b0} ^ ({32{CRCinput}} & 32'h04C11DB7)); +end + +wire ARP = (SendPacketType == `ARPReply || SendPacketType == `ARPReq); + +always @(posedge clk20) +case (rdaddress) +// Ethernet preamble + 12'h00: pkt_data <= 8'h55; + 12'h01: pkt_data <= 8'h55; + 12'h02: pkt_data <= 8'h55; + 12'h03: pkt_data <= 8'h55; + 12'h04: pkt_data <= 8'h55; + 12'h05: pkt_data <= 8'h55; + 12'h06: pkt_data <= 8'h55; + 12'h07: pkt_data <= 8'hD5; +// Ethernet header + 12'h08: pkt_data <= SendPacketType == `ARPReq ? 8'hFF : RemoteMAC[47:40]; + 12'h09: pkt_data <= SendPacketType == `ARPReq ? 8'hFF : RemoteMAC[39:32]; + 12'h0A: pkt_data <= SendPacketType == `ARPReq ? 8'hFF : RemoteMAC[31:24]; + 12'h0B: pkt_data <= SendPacketType == `ARPReq ? 8'hFF : RemoteMAC[23:16]; + 12'h0C: pkt_data <= SendPacketType == `ARPReq ? 8'hFF : RemoteMAC[15:8]; + 12'h0D: pkt_data <= SendPacketType == `ARPReq ? 8'hFF : RemoteMAC[7:0]; + 12'h0E: pkt_data <= HostMAC[47:40]; + 12'h0F: pkt_data <= HostMAC[39:32]; + 12'h10: pkt_data <= HostMAC[31:24]; + 12'h11: pkt_data <= HostMAC[23:16]; + 12'h12: pkt_data <= HostMAC[15:8]; + 12'h13: pkt_data <= HostMAC[7:0]; +// IP header / ARP / ICMP + 12'h14: pkt_data <= 8'h08; + 12'h15: pkt_data <= ARP ? 8'h06 : 8'h00; + 12'h16: pkt_data <= ARP ? 8'h00 : 8'h45; + 12'h17: pkt_data <= ARP ? 8'h01 : 8'h00; + 12'h18: pkt_data <= ARP ? 8'h08 : IPHLen[15:8]; + 12'h19: pkt_data <= ARP ? 8'h00 : IPHLen[7:0]; + 12'h1A: pkt_data <= ARP ? 8'h06 : 8'h00; + 12'h1B: pkt_data <= ARP ? 8'h04 : 8'h00; + 12'h1C: pkt_data <= 8'h00; + 12'h1D: pkt_data <= SendPacketType == `ARPReply ? 8'h02 : SendPacketType == `ARPReq ? 8'h01 : 8'h00; + 12'h1E: pkt_data <= ARP ? HostMAC[47:40] : 8'h80; + 12'h1F: pkt_data <= ARP ? HostMAC[39:32] : SendPacketType == `ICMPReply ? 8'h01 : 8'h11; + 12'h20: pkt_data <= ARP ? HostMAC[31:24] : IPchecksum2[15:8]; + 12'h21: pkt_data <= ARP ? HostMAC[23:16] : IPchecksum2[ 7:0]; + 12'h22: pkt_data <= ARP ? HostMAC[15:8] : HostIP[31:24]; + 12'h23: pkt_data <= ARP ? HostMAC[7:0] : HostIP[23:16]; + 12'h24: pkt_data <= ARP ? HostIP[31:24] : HostIP[15:8]; + 12'h25: pkt_data <= ARP ? HostIP[23:16] : HostIP[7:0]; + 12'h26: pkt_data <= ARP ? HostIP[15:8] : RemoteIP[31:24]; + 12'h27: pkt_data <= ARP ? HostIP[7:0] : RemoteIP[23:16]; + 12'h28: pkt_data <= SendPacketType == `ARPReply ? RemoteMAC[47:40] : SendPacketType == `ARPReq ? 8'h00 : RemoteIP[15:8]; + 12'h29: pkt_data <= SendPacketType == `ARPReply ? RemoteMAC[39:32] : SendPacketType == `ARPReq ? 8'h00 : RemoteIP[7:0]; +// UDP header / ARP / ICMP + 12'h2A: pkt_data <= SendPacketType == `ARPReply ? RemoteMAC[31:24] : SendPacketType == `ICMPReply ? 8'h00 : SendPacketType == `ARPReq ? 8'h00 : HostPort[15:8]; + 12'h2B: pkt_data <= SendPacketType == `ARPReply ? RemoteMAC[23:16] : HostPort[7:0]; + 12'h2C: pkt_data <= SendPacketType == `ARPReply ? RemoteMAC[15:8] : SendPacketType == `ICMPReply ? SendICMPCRC[15:8] : SendPacketType == `ARPReq ? 8'h00 : RemotePort[15:8]; + 12'h2D: pkt_data <= SendPacketType == `ARPReply ? RemoteMAC[7:0] : SendPacketType == `ICMPReply ? SendICMPCRC[7:0] : RemotePort[7:0]; + 12'h2E: pkt_data <= ARP ? RemoteIP[31:24] : SendPacketType == `ICMPReply ? SendICMPId[15:8] : UDPHLen[15:8]; + 12'h2F: pkt_data <= ARP ? RemoteIP[23:16] : SendPacketType == `ICMPReply ? SendICMPId[7:0] : UDPHLen[7:0]; + 12'h30: pkt_data <= ARP ? RemoteIP[15:8] : SendPacketType == `ICMPReply ? SendICMPSeq[15:8] : 8'h00; + 12'h31: pkt_data <= ARP ? RemoteIP[7:0] : SendPacketType == `ICMPReply ? SendICMPSeq[7:0] : 8'h00; + default: pkt_data <= ARP ? 8'h00 : SendData; +endcase + +endmodule Index: cheap_ethernet/trunk/Ethernet_test/_xmsgs/pn_parser.xmsgs =================================================================== --- cheap_ethernet/trunk/Ethernet_test/_xmsgs/pn_parser.xmsgs (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/_xmsgs/pn_parser.xmsgs (revision 3) @@ -0,0 +1,39 @@ + + + + + + + + + + +Analyzing Verilog file "C:/Projects/Xilinx/Ethernet_test/EthernetRX.v" into library work + + +"C:/Projects/Xilinx/Ethernet_test/EthernetRX.v" Line 2. Include file found: 'C:/Projects/Xilinx/Ethernet/const.vh' in file "C:/Projects/Xilinx/Ethernet_test/EthernetRX.v" line 2 + + + +Analyzing Verilog file "C:/Projects/Xilinx/Ethernet_test/EthernetTX.v" into library work + + +"C:/Projects/Xilinx/Ethernet_test/EthernetTX.v" Line 2. Include file found: 'C:/Projects/Xilinx/Ethernet/const.vh' in file "C:/Projects/Xilinx/Ethernet_test/EthernetTX.v" line 2 + + + +Analyzing Verilog file "C:/Projects/Xilinx/Ethernet_test/TENBASET_RxD.v" into library work + + +Analyzing Verilog file "C:/Projects/Xilinx/Ethernet_test/TENBASET_TxD.v" into library work + + +Analyzing Verilog file "C:/Projects/Xilinx/Ethernet_test/ethernet_test.v" into library work + + +"C:/Projects/Xilinx/Ethernet_test/ethernet_test.v" Line 2. Include file found: 'C:/Projects/Xilinx/Ethernet/const.vh' in file "C:/Projects/Xilinx/Ethernet_test/ethernet_test.v" line 2 + + + + + Index: cheap_ethernet/trunk/Ethernet_test/const.vh =================================================================== --- cheap_ethernet/trunk/Ethernet_test/const.vh (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/const.vh (revision 3) @@ -0,0 +1,20 @@ +`ifndef _const_ +`define _const_ + +// Packet Types +`define Unknown 0 +`define UDP 1 +`define ARPReq 2 +`define ARPReply 3 +`define ICMPReq 4 +`define ICMPReply 5 + +// Commands +`define CmdDone 0 +`define CmdStatus 1 +`define CmdLEDCtrl 2 +`define CmdSetConfig 3 +`define CmdSwChanged 4 +`define CmdDataEcho 5 + +`endif Index: cheap_ethernet/trunk/Ethernet_test/Ethernet_test.gise =================================================================== --- cheap_ethernet/trunk/Ethernet_test/Ethernet_test.gise (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/Ethernet_test.gise (revision 3) @@ -0,0 +1,33 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + Index: cheap_ethernet/trunk/Ethernet_test/iseconfig/ethernet_test.xreport =================================================================== --- cheap_ethernet/trunk/Ethernet_test/iseconfig/ethernet_test.xreport (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/iseconfig/ethernet_test.xreport (revision 3) @@ -0,0 +1,215 @@ + + +

+ 2012-09-01T00:02:45 + ethernet_test + Unknown + C:/Projects/Xilinx/Ethernet_test/iseconfig/ethernet_test.xreport + C:/Projects/Xilinx/Ethernet_test + 2012-09-01T00:02:18 + false +

+ + + + + + + + + + + + + + + + + + + + + + + + Index: cheap_ethernet/trunk/Ethernet_test/iseconfig/Ethernet_test.projectmgr =================================================================== --- cheap_ethernet/trunk/Ethernet_test/iseconfig/Ethernet_test.projectmgr (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/iseconfig/Ethernet_test.projectmgr (revision 3) @@ -0,0 +1,65 @@ + + + + + + + + + 2 + /Automatic `includes + /ethernet_test C:|Projects|Xilinx|Ethernet_test|ethernet_test.v + + + ethernet_test (C:/Projects/Xilinx/Ethernet_test/ethernet_test.v) + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000000ef000000020000000000000000000000000200000064ffffffff000000810000000300000002000000ef0000000100000003000000000000000100000003 + false + ethernet_test (C:/Projects/Xilinx/Ethernet_test/ethernet_test.v) + + + + 1 + Configure Target Device + Design Utilities + Implement Design + Synthesize - XST + User Constraints + + + + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000000db000000010000000100000000000000000000000064ffffffff000000810000000000000001000000db0000000100000000 + false + + + + + 1 + + + 0 + 0 + 000000ff0000000000000001000000000000000001000000000000000000000000000000000000029f000000040101000100000000000000000000000064ffffffff000000810000000000000004000000930000000100000000000000d70000000100000000000000660000000100000000000000cf0000000100000000 + false + const.vh + + + + 1 + work + + + 0 + 0 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000 + false + work + + 000000ff00000000000000020000011b0000011b01000000050100000002 + Implementation + Index: cheap_ethernet/trunk/Ethernet_test/DCMMAIN.v =================================================================== --- cheap_ethernet/trunk/Ethernet_test/DCMMAIN.v (nonexistent) +++ cheap_ethernet/trunk/Ethernet_test/DCMMAIN.v (revision 3) @@ -0,0 +1,84 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version : 14.1 +// \ \ Application : xaw2verilog +// / / Filename : DCMMAIN.v +// /___/ /\ Timestamp : 08/30/2012 14:04:33 +// \ \ / \ +// \___\/\___\ +// +//Command: xaw2verilog -intstyle C:/Projects/Xilinx/Ethernet/ipcore_dir/DCMMAIN.xaw -st DCMMAIN.v +//Design Name: DCMMAIN +//Device: xc3s500e-4pq208 +// +// Module DCMMAIN +// Generated by Xilinx Architecture Wizard +// Written for synthesis tool: XST +// Period Jitter (unit interval) for block DCM_SP_INST = 0.02 UI +// Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 1.18 ns +`timescale 1ns / 1ps + +module DCMMAIN(CLKIN_IN, + RST_IN, + CLKDV_OUT, + CLKFX_OUT, + CLKIN_IBUFG_OUT, + CLK0_OUT, + LOCKED_OUT); + + input CLKIN_IN; + input RST_IN; + output CLKDV_OUT; + output CLKFX_OUT; + output CLKIN_IBUFG_OUT; + output CLK0_OUT; + output LOCKED_OUT; + + wire CLKDV_BUF; + wire CLKFB_IN; + wire CLKFX_BUF; + wire CLKIN_IBUFG; + wire CLK0_BUF; + wire GND_BIT; + + assign GND_BIT = 0; + assign CLKIN_IBUFG_OUT = CLKIN_IBUFG; + assign CLK0_OUT = CLKFB_IN; + BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF), + .O(CLKDV_OUT)); + BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF), + .O(CLKFX_OUT)); + IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN), + .O(CLKIN_IBUFG)); + BUFG CLK0_BUFG_INST (.I(CLK0_BUF), + .O(CLKFB_IN)); + DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(5.0), .CLKFX_DIVIDE(5), + .CLKFX_MULTIPLY(2), .CLKIN_DIVIDE_BY_2("FALSE"), + .CLKIN_PERIOD(20.000), .CLKOUT_PHASE_SHIFT("NONE"), + .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"), + .DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"), + .FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") ) + DCM_SP_INST (.CLKFB(CLKFB_IN), + .CLKIN(CLKIN_IBUFG), + .DSSEN(GND_BIT), + .PSCLK(GND_BIT), + .PSEN(GND_BIT), + .PSINCDEC(GND_BIT), + .RST(RST_IN), + .CLKDV(CLKDV_BUF), + .CLKFX(CLKFX_BUF), + .CLKFX180(), + .CLK0(CLK0_BUF), + .CLK2X(), + .CLK2X180(), + .CLK90(), + .CLK180(), + .CLK270(), + .LOCKED(LOCKED_OUT), + .PSDONE(), + .STATUS()); +endmodule