URL
https://opencores.org/ocsvn/cpu65c02_true_cycle/cpu65c02_true_cycle/trunk
Subversion Repositories cpu65c02_true_cycle
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 11 to Rev 12
- ↔ Reverse comparison
Rev 11 → Rev 12
/trunk/rtl/vhdl/reg_pc.vhd
2,7 → 2,7
-- |
-- Created: |
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) |
-- at - 20:45:03 03.01.2009 |
-- at - 15:22:28 25.02.2009 |
-- |
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) |
-- |
18,7 → 18,6
ld_pc_i : in std_logic; |
offset_i : in std_logic_vector (15 downto 0); |
rst_rst_n_i : in std_logic; |
sel_pc_as_i : in std_logic; |
sel_pc_in_i : in std_logic; |
sel_pc_val_i : in std_logic_vector (1 downto 0); |
adr_nxt_pc_o : out std_logic_vector (15 downto 0); |
31,7 → 30,7
|
-- Jens-D. Gutschmidt Project: R65C02_TC |
-- scantara2003@yahoo.de |
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG |
-- COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG |
-- |
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or any later version. |
43,25 → 42,17
-- |
-- CVS Revisins History |
-- |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.3 2009/01/04 10:20:51 eda |
-- Changes for cosmetic issues only |
-- |
-- Revision 1.2 2009/01/04 09:23:14 eda |
-- - Delete unused nets and blocks (same as R6502_TC) |
-- - Rename blocks |
-- - Re-arrage FSM symbols in block FSM_Execution_Unit |
-- |
-- $Log: not supported by cvs2svn $ |
-- <<-- more -->> |
-- Title: Program Counter Logic |
-- Path: R65C02_TC/Reg_PC/struct |
-- Edited: by eda on 01 Jan 2009 |
-- Edited: by eda on 10 Feb 2009 |
-- |
-- VHDL Architecture R65C02_TC.Reg_PC.struct |
-- |
-- Created: |
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) |
-- at - 20:45:03 03.01.2009 |
-- at - 15:22:29 25.02.2009 |
-- |
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) |
-- |
78,7 → 69,6
signal adr_pc_high_o_i : std_logic_vector(7 downto 0); |
signal adr_pc_low_o_i : std_logic_vector(7 downto 0); |
signal adr_pc_o_i : std_logic_vector(15 downto 0); |
signal as_n_o_i : std_logic; |
signal ci_o_i : std_logic; |
signal cout_pc_o_i : std_logic; |
signal load3_o_i : std_logic; |
94,16 → 84,16
signal adr_nxt_pc_o_internal : std_logic_vector (15 downto 0); |
|
|
-- ModuleWare signal declarations(v1.9) for instance 'U_11' of 'addsub' |
-- ModuleWare signal declarations(v1.9) for instance 'U_2' of 'add' |
signal mw_U_2temp_din0 : std_logic_vector(8 downto 0); |
signal mw_U_2temp_din1 : std_logic_vector(8 downto 0); |
signal mw_U_2sum : unsigned(8 downto 0); |
|
-- ModuleWare signal declarations(v1.9) for instance 'U_11' of 'add' |
signal mw_U_11temp_din0 : std_logic_vector(8 downto 0); |
signal mw_U_11temp_din1 : std_logic_vector(8 downto 0); |
signal mw_U_11sum : unsigned(8 downto 0); |
|
-- ModuleWare signal declarations(v1.9) for instance 'U_12' of 'addsub' |
signal mw_U_12temp_din0 : std_logic_vector(8 downto 0); |
signal mw_U_12temp_din1 : std_logic_vector(8 downto 0); |
signal mw_U_12sum : unsigned(8 downto 0); |
|
-- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff' |
signal mw_U_0reg_cval : std_logic_vector(7 downto 0); |
|
113,36 → 103,28
|
begin |
|
-- ModuleWare code(v1.9) for instance 'U_11' of 'addsub' |
mw_U_11temp_din0 <= '0' & adr_pc_low_o_i; |
mw_U_11temp_din1 <= '0' & val_o_i; |
u_11combo_proc: process (mw_U_11temp_din0, mw_U_11temp_din1, as_n_o_i) |
-- ModuleWare code(v1.9) for instance 'U_2' of 'add' |
mw_U_2temp_din0 <= '0' & adr_pc_low_o_i; |
mw_U_2temp_din1 <= '0' & val_o_i; |
u_2combo_proc: process (mw_U_2temp_din0, mw_U_2temp_din1) |
variable temp_carry : std_logic; |
begin |
temp_carry := '0'; |
if (as_n_o_i = '1') then |
mw_U_11sum <= unsigned(mw_U_11temp_din0) + unsigned(mw_U_11temp_din1) + temp_carry; |
else |
mw_U_11sum <= unsigned(mw_U_11temp_din0) - unsigned(mw_U_11temp_din1) - temp_carry; |
end if; |
end process u_11combo_proc; |
adr_nxt_pc_o_internal(7 DOWNTO 0) <= conv_std_logic_vector(mw_U_11sum(7 downto 0),8); |
cout_pc_o_i <= mw_U_11sum(8); |
mw_U_2sum <= unsigned(mw_U_2temp_din0) + unsigned(mw_U_2temp_din1) + temp_carry; |
end process u_2combo_proc; |
adr_nxt_pc_o_internal(7 DOWNTO 0) <= conv_std_logic_vector(mw_U_2sum(7 downto 0),8); |
cout_pc_o_i <= mw_U_2sum(8) ; |
|
-- ModuleWare code(v1.9) for instance 'U_12' of 'addsub' |
mw_U_12temp_din0 <= '0' & adr_pc_high_o_i; |
mw_U_12temp_din1 <= '0' & offset_high_o_i; |
u_12combo_proc: process (mw_U_12temp_din0, mw_U_12temp_din1, as_n_o_i, ci_o_i) |
-- ModuleWare code(v1.9) for instance 'U_11' of 'add' |
mw_U_11temp_din0 <= '0' & adr_pc_high_o_i; |
mw_U_11temp_din1 <= '0' & offset_high_o_i; |
u_11combo_proc: process (mw_U_11temp_din0, mw_U_11temp_din1, ci_o_i) |
variable temp_carry : std_logic; |
begin |
temp_carry := ci_o_i; |
if (as_n_o_i = '1') then |
mw_U_12sum <= unsigned(mw_U_12temp_din0) + unsigned(mw_U_12temp_din1) + temp_carry; |
else |
mw_U_12sum <= unsigned(mw_U_12temp_din0) - unsigned(mw_U_12temp_din1) - temp_carry; |
end if; |
end process u_12combo_proc; |
adr_nxt_pc_o_internal(15 DOWNTO 8) <= conv_std_logic_vector(mw_U_12sum(7 downto 0),8); |
mw_U_11sum <= unsigned(mw_U_11temp_din0) + unsigned(mw_U_11temp_din1) + temp_carry; |
end process u_11combo_proc; |
adr_nxt_pc_o_internal(15 DOWNTO 8) <= conv_std_logic_vector(mw_U_11sum(7 downto 0),8); |
|
-- ModuleWare code(v1.9) for instance 'U_0' of 'adff' |
adr_pc_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval; |
185,9 → 167,6
-- ModuleWare code(v1.9) for instance 'U_9' of 'constval' |
val_one <= "00000001"; |
|
-- ModuleWare code(v1.9) for instance 'U_2' of 'inv' |
as_n_o_i <= not(sel_pc_as_i); |
|
-- ModuleWare code(v1.9) for instance 'U_8' of 'mux' |
u_8combo_proc: process(adr_pc_o_internal, adr_i, sel_pc_in_i) |
begin |
/trunk/rtl/vhdl/reg_sp.vhd
2,7 → 2,7
-- |
-- Created: |
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) |
-- at - 20:45:03 03.01.2009 |
-- at - 15:22:29 25.02.2009 |
-- |
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) |
-- |
28,7 → 28,7
|
-- Jens-D. Gutschmidt Project: R65C02_TC |
-- scantara2003@yahoo.de |
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG |
-- COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG |
-- |
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or any later version. |
40,25 → 40,17
-- |
-- CVS Revisins History |
-- |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.3 2009/01/04 10:20:51 eda |
-- Changes for cosmetic issues only |
-- |
-- Revision 1.2 2009/01/04 09:23:15 eda |
-- - Delete unused nets and blocks (same as R6502_TC) |
-- - Rename blocks |
-- - Re-arrage FSM symbols in block FSM_Execution_Unit |
-- |
-- $Log: not supported by cvs2svn $ |
-- <<-- more -->> |
-- Title: Stack Pointer Logic |
-- Path: R65C02_TC/Reg_SP/struct |
-- Edited: by eda on 01 Jan 2009 |
-- Edited: by eda on 10 Feb 2009 |
-- |
-- VHDL Architecture R65C02_TC.Reg_SP.struct |
-- |
-- Created: |
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) |
-- at - 20:45:03 03.01.2009 |
-- at - 15:22:29 25.02.2009 |
-- |
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) |
-- |
/trunk/rtl/vhdl/fsm_execution_unit.vhd
2,7 → 2,7
-- |
-- Created: |
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) |
-- at - 20:48:06 04.01.2009 |
-- at - 15:22:30 25.02.2009 |
-- |
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) |
-- |
12,48 → 12,47
|
entity FSM_Execution_Unit is |
port( |
adr_nxt_pc_i : in std_logic_vector (15 downto 0); |
adr_pc_i : in std_logic_vector (15 downto 0); |
adr_sp_i : in std_logic_vector (15 downto 0); |
clk_clk_i : in std_logic; |
d_alu_i : in std_logic_vector ( 7 downto 0 ); |
d_i : in std_logic_vector ( 7 downto 0 ); |
d_regs_out_i : in std_logic_vector ( 7 downto 0 ); |
irq_n_i : in std_logic; |
nmi_i : in std_logic; |
q_a_i : in std_logic_vector ( 7 downto 0 ); |
q_x_i : in std_logic_vector ( 7 downto 0 ); |
q_y_i : in std_logic_vector ( 7 downto 0 ); |
rdy_i : in std_logic; |
reg_0flag_i : in std_logic; |
reg_1flag_i : in std_logic; |
reg_7flag_i : in std_logic; |
rst_rst_n_i : in std_logic; |
so_n_i : in std_logic; |
a_o : out std_logic_vector (15 downto 0); |
adr_o : out std_logic_vector (15 downto 0); |
ch_a_o : out std_logic_vector ( 7 downto 0 ); |
ch_b_o : out std_logic_vector ( 7 downto 0 ); |
d_o : out std_logic_vector ( 7 downto 0 ); |
d_regs_in_o : out std_logic_vector ( 7 downto 0 ); |
fetch_o : out std_logic; |
ld_o : out std_logic_vector ( 1 downto 0 ); |
ld_pc_o : out std_logic; |
ld_sp_o : out std_logic; |
load_regs_o : out std_logic; |
offset_o : out std_logic_vector ( 15 downto 0 ); |
rd_o : out std_logic; |
sel_pc_as_o : out std_logic; |
sel_pc_in_o : out std_logic; |
sel_pc_val_o : out std_logic_vector ( 1 downto 0 ); |
sel_rb_in_o : out std_logic_vector ( 1 downto 0 ); |
sel_rb_out_o : out std_logic_vector ( 1 downto 0 ); |
sel_reg_o : out std_logic_vector ( 1 downto 0 ); |
sel_sp_as_o : out std_logic; |
sel_sp_in_o : out std_logic; |
sync_o : out std_logic; |
wr_n_o : out std_logic; |
wr_o : out std_logic |
adr_nxt_pc_i : in std_logic_vector (15 downto 0); |
adr_pc_i : in std_logic_vector (15 downto 0); |
adr_sp_i : in std_logic_vector (15 downto 0); |
alu_dec_val_i : in std_logic_vector ( 7 downto 0 ); |
clk_clk_i : in std_logic; |
d_alu_i : in std_logic_vector ( 7 downto 0 ); |
d_i : in std_logic_vector ( 7 downto 0 ); |
d_regs_out_i : in std_logic_vector ( 7 downto 0 ); |
irq_n_i : in std_logic; |
nmi_i : in std_logic; |
q_a_i : in std_logic_vector ( 7 downto 0 ); |
q_x_i : in std_logic_vector ( 7 downto 0 ); |
q_y_i : in std_logic_vector ( 7 downto 0 ); |
rdy_i : in std_logic; |
reg_0flag_i : in std_logic; |
reg_1flag_i : in std_logic; |
reg_7flag_i : in std_logic; |
rst_rst_n_i : in std_logic; |
so_n_i : in std_logic; |
a_o : out std_logic_vector (15 downto 0); |
adr_o : out std_logic_vector (15 downto 0); |
ch_a_o : out std_logic_vector ( 7 downto 0 ); |
ch_b_o : out std_logic_vector ( 7 downto 0 ); |
d_o : out std_logic_vector ( 7 downto 0 ); |
d_regs_in_o : out std_logic_vector ( 7 downto 0 ); |
fetch_o : out std_logic; |
ld_o : out std_logic_vector ( 1 downto 0 ); |
ld_pc_o : out std_logic; |
ld_sp_o : out std_logic; |
load_regs_o : out std_logic; |
offset_o : out std_logic_vector ( 15 downto 0 ); |
rd_o : out std_logic; |
sel_pc_in_o : out std_logic; |
sel_pc_val_o : out std_logic_vector ( 1 downto 0 ); |
sel_rb_in_o : out std_logic_vector ( 1 downto 0 ); |
sel_rb_out_o : out std_logic_vector ( 1 downto 0 ); |
sel_reg_o : out std_logic_vector ( 1 downto 0 ); |
sel_sp_as_o : out std_logic; |
sel_sp_in_o : out std_logic; |
sync_o : out std_logic; |
wr_o : out std_logic |
); |
|
-- Declarations |
64,7 → 63,7
|
-- scantara2003@yahoo.de |
|
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG |
-- COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG |
|
-- |
|
96,7 → 95,7
|
-- Path: R65C02_TC/FSM_Execution_Unit/fsm |
|
-- Edited: by eda on 04 Jan 2009 |
-- Edited: by eda on 25 Feb 2009 |
|
-- |
-- VHDL Architecture R65C02_TC.FSM_Execution_Unit.fsm |
103,7 → 102,7
-- |
-- Created: |
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) |
-- at - 20:48:08 04.01.2009 |
-- at - 15:22:32 25.02.2009 |
-- |
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) |
-- |
117,7 → 116,6
signal reg_F : std_logic_vector( 7 DOWNTO 0 ); |
signal reg_PC : std_logic_vector(15 DOWNTO 0); |
signal reg_PC1 : std_logic_vector( 15 DOWNTO 0 ); |
signal reg_sel_pc_as : std_logic; |
signal reg_sel_pc_in : std_logic; |
signal reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 ); |
signal reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 ); |
127,17 → 125,15
signal reg_sel_sp_in : std_logic; |
signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 ); |
signal sig_PC : std_logic_vector(15 DOWNTO 0); |
signal sig_RD : std_logic; |
signal sig_RWn : std_logic; |
signal sig_SYNC : std_logic; |
signal sig_WR : std_logic; |
signal zw_ALU : std_logic_vector( 8 DOWNTO 0 ); |
signal zw_ALU1 : std_logic_vector( 8 DOWNTO 0 ); |
signal zw_ALU2 : std_logic_vector( 8 DOWNTO 0 ); |
signal zw_ALU3 : std_logic_vector( 8 DOWNTO 0 ); |
signal zw_ALU4 : std_logic_vector( 8 DOWNTO 0 ); |
signal zw_ALU5 : std_logic_vector( 8 DOWNTO 0 ); |
signal zw_ALU6 : std_logic_vector( 8 DOWNTO 0 ); |
signal zw_ALU1 : std_logic_vector( 4 DOWNTO 0 ); |
signal zw_ALU2 : std_logic_vector( 4 DOWNTO 0 ); |
signal zw_ALU3 : std_logic_vector( 4 DOWNTO 0 ); |
signal zw_ALU4 : std_logic_vector( 4 DOWNTO 0 ); |
signal zw_ALU5 : std_logic_vector( 3 DOWNTO 0 ); |
signal zw_ALU6 : std_logic_vector( 3 DOWNTO 0 ); |
signal zw_PC : std_logic_vector( 15 DOWNTO 0 ); |
signal zw_REG_ALU : std_logic_vector( 8 DOWNTO 0 ); |
signal zw_REG_NMI : std_logic; |
160,154 → 156,150
attribute state_vector of fsm : architecture is "current_state"; |
|
-- Hard encoding |
constant s544 : state_type := "00000000"; |
constant s545 : state_type := "00000001"; |
constant s546 : state_type := "00000011"; |
constant s547 : state_type := "00000010"; |
constant s549 : state_type := "00000110"; |
constant s550 : state_type := "00000111"; |
constant RES : state_type := "00000101"; |
constant s548 : state_type := "00000100"; |
constant s551 : state_type := "00001100"; |
constant s552 : state_type := "00001101"; |
constant s575 : state_type := "00001111"; |
constant s576 : state_type := "00001110"; |
constant s577 : state_type := "00001010"; |
constant s532 : state_type := "00001011"; |
constant s533 : state_type := "00001001"; |
constant s534 : state_type := "00001000"; |
constant s535 : state_type := "00011000"; |
constant s536 : state_type := "00011001"; |
constant s537 : state_type := "00011011"; |
constant FETCH : state_type := "00011010"; |
constant s6 : state_type := "00011110"; |
constant s7 : state_type := "00011111"; |
constant s8 : state_type := "00011101"; |
constant s9 : state_type := "00011100"; |
constant s10 : state_type := "00010100"; |
constant s13 : state_type := "00010101"; |
constant s18 : state_type := "00010111"; |
constant s19 : state_type := "00010110"; |
constant s26 : state_type := "00010010"; |
constant s27 : state_type := "00010011"; |
constant s203 : state_type := "00010001"; |
constant s204 : state_type := "00010000"; |
constant s212 : state_type := "00110000"; |
constant s216 : state_type := "00110001"; |
constant s219 : state_type := "00110011"; |
constant s220 : state_type := "00110010"; |
constant s227 : state_type := "00110110"; |
constant s228 : state_type := "00110111"; |
constant s230 : state_type := "00110101"; |
constant s231 : state_type := "00110100"; |
constant s229 : state_type := "00111100"; |
constant s512 : state_type := "00111101"; |
constant s554 : state_type := "00111111"; |
constant s578 : state_type := "00111110"; |
constant s581 : state_type := "00111010"; |
constant s582 : state_type := "00111011"; |
constant s583 : state_type := "00111001"; |
constant s584 : state_type := "00111000"; |
constant s585 : state_type := "00101000"; |
constant s586 : state_type := "00101001"; |
constant s587 : state_type := "00101011"; |
constant s580 : state_type := "00101010"; |
constant s178 : state_type := "00101110"; |
constant s194 : state_type := "00101111"; |
constant s195 : state_type := "00101101"; |
constant s196 : state_type := "00101100"; |
constant s197 : state_type := "00100100"; |
constant s198 : state_type := "00100101"; |
constant s199 : state_type := "00100111"; |
constant s200 : state_type := "00100110"; |
constant s205 : state_type := "00100010"; |
constant s206 : state_type := "00100011"; |
constant s207 : state_type := "00100001"; |
constant s208 : state_type := "00100000"; |
constant s209 : state_type := "01100000"; |
constant s213 : state_type := "01100001"; |
constant s214 : state_type := "01100011"; |
constant s513 : state_type := "01100010"; |
constant s588 : state_type := "01100110"; |
constant s589 : state_type := "01100111"; |
constant s590 : state_type := "01100101"; |
constant s591 : state_type := "01100100"; |
constant s592 : state_type := "01101100"; |
constant s593 : state_type := "01101101"; |
constant s594 : state_type := "01101111"; |
constant s595 : state_type := "01101110"; |
constant s596 : state_type := "01101010"; |
constant s597 : state_type := "01101011"; |
constant s405 : state_type := "01101001"; |
constant s408 : state_type := "01101000"; |
constant s410 : state_type := "01111000"; |
constant s411 : state_type := "01111001"; |
constant s414 : state_type := "01111011"; |
constant s415 : state_type := "01111010"; |
constant s417 : state_type := "01111110"; |
constant s419 : state_type := "01111111"; |
constant s420 : state_type := "01111101"; |
constant s598 : state_type := "01111100"; |
constant s599 : state_type := "01110100"; |
constant s600 : state_type := "01110101"; |
constant s268 : state_type := "01110111"; |
constant s305 : state_type := "01110110"; |
constant s306 : state_type := "01110010"; |
constant s267 : state_type := "01110011"; |
constant s269 : state_type := "01110001"; |
constant s303 : state_type := "01110000"; |
constant s272 : state_type := "01010000"; |
constant s275 : state_type := "01010001"; |
constant s308 : state_type := "01010011"; |
constant s309 : state_type := "01010010"; |
constant s274 : state_type := "01010110"; |
constant s310 : state_type := "01010111"; |
constant s402 : state_type := "01010101"; |
constant s421 : state_type := "01010100"; |
constant s422 : state_type := "01011100"; |
constant s423 : state_type := "01011101"; |
constant s424 : state_type := "01011111"; |
constant s362 : state_type := "01011110"; |
constant s221 : state_type := "01011010"; |
constant s232 : state_type := "01011011"; |
constant s233 : state_type := "01011001"; |
constant s234 : state_type := "01011000"; |
constant s235 : state_type := "01001000"; |
constant s538 : state_type := "01001001"; |
constant s539 : state_type := "01001011"; |
constant s540 : state_type := "01001010"; |
constant s541 : state_type := "01001110"; |
constant s542 : state_type := "01001111"; |
constant s543 : state_type := "01001101"; |
constant s425 : state_type := "01001100"; |
constant s426 : state_type := "01000100"; |
constant s427 : state_type := "01000101"; |
constant s428 : state_type := "01000111"; |
constant s429 : state_type := "01000110"; |
constant s430 : state_type := "01000010"; |
constant s431 : state_type := "01000011"; |
constant s432 : state_type := "01000001"; |
constant s433 : state_type := "01000000"; |
constant s434 : state_type := "11000000"; |
constant s236 : state_type := "11000001"; |
constant s245 : state_type := "11000011"; |
constant s246 : state_type := "11000010"; |
constant s248 : state_type := "11000110"; |
constant s345 : state_type := "11000111"; |
constant s346 : state_type := "11000101"; |
constant s252 : state_type := "11000100"; |
constant s253 : state_type := "11001100"; |
constant s435 : state_type := "11001101"; |
constant s436 : state_type := "11001111"; |
constant s437 : state_type := "11001110"; |
constant s438 : state_type := "11001010"; |
constant s439 : state_type := "11001011"; |
constant s440 : state_type := "11001001"; |
constant s441 : state_type := "11001000"; |
constant s442 : state_type := "11011000"; |
constant s443 : state_type := "11011001"; |
constant s444 : state_type := "11011011"; |
constant s0 : state_type := "11011010"; |
constant G30_1 : state_type := "00000000"; |
constant G30_3 : state_type := "00000001"; |
constant G30_4 : state_type := "00000010"; |
constant G30_5 : state_type := "00000011"; |
constant G30_e : state_type := "00000100"; |
constant G30_2 : state_type := "00000101"; |
constant RES : state_type := "00000110"; |
constant G28_1 : state_type := "00000111"; |
constant G28_2 : state_type := "00001000"; |
constant G28_3 : state_type := "00001001"; |
constant G28_5 : state_type := "00001010"; |
constant G28_4 : state_type := "00001011"; |
constant G28_e : state_type := "00001100"; |
constant G29_1 : state_type := "00001101"; |
constant G29_2 : state_type := "00001110"; |
constant G29_3 : state_type := "00001111"; |
constant G29_5 : state_type := "00010000"; |
constant G29_4 : state_type := "00010001"; |
constant G29_e : state_type := "00010010"; |
constant FETCH : state_type := "00010011"; |
constant G1_1 : state_type := "00010100"; |
constant G2_1 : state_type := "00010101"; |
constant G3_1 : state_type := "00010110"; |
constant G4_1 : state_type := "00010111"; |
constant G9_1 : state_type := "00011000"; |
constant G5_1 : state_type := "00011001"; |
constant G6_1 : state_type := "00011010"; |
constant G7_1 : state_type := "00011011"; |
constant G8_1 : state_type := "00011100"; |
constant G19_1 : state_type := "00011101"; |
constant G15_1 : state_type := "00011110"; |
constant G15_3 : state_type := "00011111"; |
constant G15_4 : state_type := "00100000"; |
constant G15_5 : state_type := "00100001"; |
constant G15_2 : state_type := "00100010"; |
constant G15_7 : state_type := "00100011"; |
constant G15_e3 : state_type := "00100100"; |
constant G15_6 : state_type := "00100101"; |
constant G15_e2 : state_type := "00100110"; |
constant G15_e1 : state_type := "00100111"; |
constant G15_8 : state_type := "00101000"; |
constant G10_1 : state_type := "00101001"; |
constant G10_3 : state_type := "00101010"; |
constant G10_4 : state_type := "00101011"; |
constant G10_5 : state_type := "00101100"; |
constant G10_2 : state_type := "00101101"; |
constant G10_7 : state_type := "00101110"; |
constant G10_e3 : state_type := "00101111"; |
constant G10_e1 : state_type := "00110000"; |
constant G10_e2 : state_type := "00110001"; |
constant G10_6 : state_type := "00110010"; |
constant G10_8 : state_type := "00110011"; |
constant G17_1 : state_type := "00110100"; |
constant G17_4 : state_type := "00110101"; |
constant G17_6 : state_type := "00110110"; |
constant G17_3 : state_type := "00110111"; |
constant G17_2 : state_type := "00111000"; |
constant G17_8 : state_type := "00111001"; |
constant G17_9 : state_type := "00111010"; |
constant G17_7 : state_type := "00111011"; |
constant G17_5 : state_type := "00111100"; |
constant G17_10 : state_type := "00111101"; |
constant G17_e : state_type := "00111110"; |
constant G17_11 : state_type := "00111111"; |
constant G16_1 : state_type := "01000000"; |
constant G16_3 : state_type := "01000001"; |
constant G16_4 : state_type := "01000010"; |
constant G16_5 : state_type := "01000011"; |
constant G16_2 : state_type := "01000100"; |
constant G16_7 : state_type := "01000101"; |
constant G16_6 : state_type := "01000110"; |
constant G16_e3 : state_type := "01000111"; |
constant G16_e1 : state_type := "01001000"; |
constant G16_e2 : state_type := "01001001"; |
constant G16_8 : state_type := "01001010"; |
constant G11_1 : state_type := "01001011"; |
constant G11_5 : state_type := "01001100"; |
constant G11_6 : state_type := "01001101"; |
constant G11_2 : state_type := "01001110"; |
constant G11_7 : state_type := "01001111"; |
constant G11_3 : state_type := "01010000"; |
constant G11_4 : state_type := "01010001"; |
constant G11_e : state_type := "01010010"; |
constant G31_1 : state_type := "01010011"; |
constant G34_1 : state_type := "01010100"; |
constant G32_1 : state_type := "01010101"; |
constant G33_1 : state_type := "01010110"; |
constant G12_1 : state_type := "01010111"; |
constant G12_e1 : state_type := "01011000"; |
constant G12_e2 : state_type := "01011001"; |
constant G12_2 : state_type := "01011010"; |
constant G12_3 : state_type := "01011011"; |
constant G12_4 : state_type := "01011100"; |
constant G20_1 : state_type := "01011101"; |
constant G20_2 : state_type := "01011110"; |
constant G20_5 : state_type := "01011111"; |
constant G20_e : state_type := "01100000"; |
constant G20_3 : state_type := "01100001"; |
constant G20_4 : state_type := "01100010"; |
constant G21_1 : state_type := "01100011"; |
constant G21_2 : state_type := "01100100"; |
constant G21_3 : state_type := "01100101"; |
constant G21_4 : state_type := "01100110"; |
constant G21_e : state_type := "01100111"; |
constant G13_3 : state_type := "01101000"; |
constant G13_1 : state_type := "01101001"; |
constant G13_4 : state_type := "01101010"; |
constant G13_2 : state_type := "01101011"; |
constant G13_e1 : state_type := "01101100"; |
constant G13_e2 : state_type := "01101101"; |
constant G18_1 : state_type := "01101110"; |
constant G18_2 : state_type := "01101111"; |
constant G18_3 : state_type := "01110000"; |
constant G18_4 : state_type := "01110001"; |
constant G18_e : state_type := "01110010"; |
constant G18_5 : state_type := "01110011"; |
constant G26_1 : state_type := "01110100"; |
constant G26_2 : state_type := "01110101"; |
constant G26_3 : state_type := "01110110"; |
constant G26_4 : state_type := "01110111"; |
constant G26_e : state_type := "01111000"; |
constant G27_1 : state_type := "01111001"; |
constant G27_2 : state_type := "01111010"; |
constant G27_3 : state_type := "01111011"; |
constant G27_4 : state_type := "01111100"; |
constant G27_e : state_type := "01111101"; |
constant G14_1 : state_type := "01111110"; |
constant G14_5 : state_type := "01111111"; |
constant G14_6 : state_type := "10000000"; |
constant G14_2 : state_type := "10000001"; |
constant G14_7 : state_type := "10000010"; |
constant G14_3 : state_type := "10000011"; |
constant G14_4 : state_type := "10000100"; |
constant G14_e : state_type := "10000101"; |
constant G22_1 : state_type := "10000110"; |
constant G22_e : state_type := "10000111"; |
constant G23_1 : state_type := "10001000"; |
constant G23_e : state_type := "10001001"; |
constant G24_1 : state_type := "10001010"; |
constant G24_2 : state_type := "10001011"; |
constant G24_e : state_type := "10001100"; |
constant G25_1 : state_type := "10001101"; |
constant G25_2 : state_type := "10001110"; |
constant G25_e : state_type := "10001111"; |
|
-- Declare current and next state signals |
signal current_state : state_type; |
317,7 → 309,6
signal d_o_cld : std_logic_vector ( 7 downto 0 ); |
signal rd_o_cld : std_logic ; |
signal sync_o_cld : std_logic ; |
signal wr_n_o_cld : std_logic ; |
signal wr_o_cld : std_logic ; |
|
begin |
335,12 → 326,10
d_o_cld <= X"00"; |
rd_o_cld <= '0'; |
sync_o_cld <= '0'; |
wr_n_o_cld <= '1'; |
wr_o_cld <= '0'; |
reg_F <= "00000100"; |
reg_PC <= X"0000"; |
reg_PC1 <= X"0000"; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_rb_in <= "00"; |
368,7 → 357,6
reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0); |
reg_PC <= reg_PC; |
reg_PC1 <= reg_PC1; |
reg_sel_pc_as <= reg_sel_pc_as; |
reg_sel_pc_in <= reg_sel_pc_in; |
reg_sel_pc_val <= reg_sel_pc_val; |
reg_sel_rb_in <= reg_sel_rb_in; |
391,102 → 379,92
zw_w2 <= zw_w2; |
zw_w3 <= zw_w3; |
d_o_cld <= sig_D_OUT; |
rd_o_cld <= sig_RD; |
rd_o_cld <= NOT(sig_WR); |
sync_o_cld <= sig_SYNC; |
wr_n_o_cld <= sig_RWn; |
wr_o_cld <= sig_WR; |
|
-- Combined Actions |
case current_state is |
when s544 => |
when G30_1 => |
sig_PC <= adr_sp_i; |
when s545 => |
when G30_3 => |
sig_PC <= adr_sp_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
when s546 => |
when G30_4 => |
sig_PC <= adr_pc_i; |
when s547 => |
when G30_5 => |
if (rdy_i = '1') then |
sig_PC <= adr_pc_i; |
zw_w1 (7 downto 0) <= d_i; |
reg_sel_pc_in <= '1'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "11"; |
end if; |
when s549 => |
when G30_e => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_w1 (7 downto 0); |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s550 => |
when G30_2 => |
sig_PC <= adr_sp_i; |
reg_sel_pc_in <= '1'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
when RES => |
reg_sel_pc_in <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_pc_as <= '0'; |
sig_PC <= adr_nxt_pc_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
when s548 => |
when G28_1 => |
if (rdy_i = '1') then |
sig_PC <= adr_sp_i; |
end if; |
when s551 => |
when G28_2 => |
sig_PC <= adr_sp_i; |
when s552 => |
when G28_3 => |
sig_PC <= adr_sp_i; |
when s575 => |
when G28_5 => |
if (rdy_i = '1') then |
sig_PC <= X"FFFF"; |
zw_b1 <= d_i; |
end if; |
when s576 => |
when G28_4 => |
sig_PC <= X"FFFE"; |
when s577 => |
when G28_e => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_b1; |
reg_F(2) <= '1'; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s532 => |
when G29_1 => |
if (rdy_i = '1') then |
sig_PC <= adr_sp_i; |
end if; |
when s533 => |
when G29_2 => |
sig_PC <= adr_sp_i; |
when s534 => |
when G29_3 => |
sig_PC <= adr_sp_i; |
when s535 => |
when G29_5 => |
if (rdy_i = '1') then |
sig_PC <= X"FFFB"; |
reg_sel_pc_in <= '1'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "11"; |
zw_b1 <= d_i; |
end if; |
when s536 => |
when G29_4 => |
sig_PC <= X"FFFA"; |
when s537 => |
when G29_e => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_b1; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
509,8 → 487,6
d_i = X"71" or |
d_i = X"72") and (rdy_i = '1')) then |
sig_PC <= adr_nxt_pc_i; |
|
|
reg_sel_reg <= "00"; |
reg_sel_rb_in <= "11"; |
zw_b1(0) <= reg_F(7); |
695,6 → 671,8
sig_PC <= adr_nxt_pc_i; |
elsif ((d_i = X"40") and (rdy_i = '1')) then |
sig_PC <= adr_nxt_pc_i; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '0'; |
elsif ((d_i = X"60") and (rdy_i = '1')) then |
sig_PC <= adr_nxt_pc_i; |
reg_sel_sp_in <= '0'; |
709,8 → 687,6
d_i = X"F1" or |
d_i = X"F2") and (rdy_i = '1')) then |
sig_PC <= adr_nxt_pc_i; |
|
|
reg_sel_reg <= "00"; |
reg_sel_rb_in <= "11"; |
zw_b1(0) <= reg_F(7); |
821,51 → 797,46
reg_sel_rb_in <= "11"; |
zw_b4 <= X"01"; |
end if; |
when s6 => |
when G1_1 => |
if (rdy_i = '1') then |
sig_PC <= adr_pc_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s7 => |
when G2_1 => |
if (rdy_i = '1') then |
sig_PC <= adr_pc_i; |
reg_F(0) <= '1'; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s8 => |
when G3_1 => |
if (rdy_i = '1') then |
sig_PC <= adr_pc_i; |
reg_F(3) <= '1'; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s9 => |
when G4_1 => |
if (rdy_i = '1') then |
sig_PC <= adr_pc_i; |
reg_F(2) <= '1'; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s10 => |
when G9_1 => |
if (rdy_i = '1' and |
zw_REG_OP = X"9A") then |
sig_PC <= adr_pc_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
875,7 → 846,6
reg_F(7) <= reg_7flag_i; |
reg_F(1) <= reg_1flag_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
884,63 → 854,57
reg_F(7) <= reg_7flag_i; |
reg_F(1) <= reg_1flag_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s13 => |
when G5_1 => |
if (rdy_i = '1') then |
sig_PC <= adr_pc_i; |
reg_F(0) <= '0'; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s18 => |
when G6_1 => |
if (rdy_i = '1') then |
sig_PC <= adr_pc_i; |
reg_F(3) <= '0'; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s19 => |
when G7_1 => |
if (rdy_i = '1') then |
sig_PC <= adr_pc_i; |
reg_F(2) <= '0'; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s26 => |
when G8_1 => |
if (rdy_i = '1') then |
sig_PC <= adr_pc_i; |
reg_F(6) <= '0'; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s27 => |
when G19_1 => |
if (rdy_i = '1') then |
sig_PC <= adr_pc_i; |
reg_F(7) <= reg_7flag_i; |
reg_F(1) <= reg_1flag_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s203 => |
when G15_1 => |
if (rdy_i = '1' and |
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR |
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR |
958,7 → 922,6
reg_F(7) <= reg_7flag_i; |
reg_F(1) <= reg_1flag_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
973,7 → 936,6
reg_F(7) <= reg_7flag_i; |
reg_F(1) <= reg_1flag_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
988,7 → 950,6
reg_F(7) <= reg_7flag_i; |
reg_F(1) <= reg_1flag_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
1008,7 → 969,6
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR |
(zw_ALU(0))); |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
1019,7 → 979,6
reg_F(7) <= reg_7flag_i; |
reg_F(1) <= reg_1flag_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
1092,40 → 1051,40
sig_PC <= X"00" & d_i; |
zw_b1 <= d_alu_i; |
end if; |
when s204 => |
when G15_3 => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_b1; |
end if; |
when s212 => |
when G15_4 => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_b1; |
zw_b3 <= d_alu_i; |
end if; |
when s216 => |
when G15_5 => |
if (rdy_i = '1') then |
sig_PC <= X"00" & zw_b1; |
zw_b1 <= d_alu_i; |
zw_b2(0) <= reg_0flag_i; |
end if; |
when s219 => |
when G15_2 => |
if (rdy_i = '1') then |
sig_PC <= X"00" & zw_b1; |
end if; |
when s220 => |
when G15_7 => |
if (rdy_i = '1') then |
sig_PC <= X"00" & zw_b1; |
end if; |
when s227 => |
when G15_e3 => |
if (rdy_i = '1') then |
sig_PC <= X"00" & d_alu_i; |
zw_b1 <= d_i; |
end if; |
when s228 => |
when G15_6 => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_b1; |
zw_b3 <= d_alu_i; |
end if; |
when s230 => |
when G15_e2 => |
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or |
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or |
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or |
1135,7 → 1094,6
reg_F(7) <= reg_7flag_i; |
reg_F(1) <= reg_1flag_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
1148,7 → 1106,6
reg_F(7) <= reg_7flag_i; |
reg_F(1) <= reg_1flag_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
1161,7 → 1118,6
reg_F(7) <= reg_7flag_i; |
reg_F(1) <= reg_1flag_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
1179,7 → 1135,6
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR |
(zw_ALU(0))); |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
1188,12 → 1143,11
reg_F(7) <= reg_7flag_i; |
reg_F(1) <= reg_1flag_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s231 => |
when G15_e1 => |
if ((rdy_i = '1' AND |
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or |
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or |
1204,7 → 1158,6
reg_F(7) <= reg_7flag_i; |
reg_F(1) <= reg_1flag_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
1218,7 → 1171,6
reg_F(7) <= reg_7flag_i; |
reg_F(1) <= reg_1flag_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
1232,7 → 1184,6
reg_F(7) <= reg_7flag_i; |
reg_F(1) <= reg_1flag_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
1251,7 → 1202,6
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR |
(zw_ALU(0))); |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
1261,7 → 1211,6
reg_F(7) <= reg_7flag_i; |
reg_F(1) <= reg_1flag_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
1268,12 → 1217,12
elsif (rdy_i = '1') then |
sig_PC <= zw_b3 & zw_b1; |
end if; |
when s229 => |
when G15_8 => |
if (rdy_i = '1') then |
sig_PC <= X"00" & zw_b1; |
zw_b1 <= d_i; |
end if; |
when s512 => |
when G10_1 => |
if (rdy_i = '1' and |
zw_REG_OP = X"65") then |
sig_PC <= X"00" & d_i; |
1289,7 → 1238,6
(zw_ALU(0))); |
reg_F(0) <= zw_ALU(8); |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
1331,7 → 1279,6
(zw_ALU(0))); |
reg_F(0) <= zw_ALU4(4); |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
1340,35 → 1287,35
sig_PC <= X"00" & d_i; |
zw_b1 <= d_alu_i; |
end if; |
when s554 => |
when G10_3 => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_b1; |
end if; |
when s578 => |
when G10_4 => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_b1; |
zw_b3 <= d_alu_i; |
end if; |
when s581 => |
when G10_5 => |
if (rdy_i = '1') then |
sig_PC <= X"00" & zw_b1; |
zw_b1 <= d_alu_i; |
zw_b2(0) <= reg_0flag_i; |
end if; |
when s582 => |
when G10_2 => |
if (rdy_i = '1') then |
sig_PC <= X"00" & zw_b1; |
end if; |
when s583 => |
when G10_7 => |
if (rdy_i = '1') then |
sig_PC <= X"00" & zw_b1; |
end if; |
when s584 => |
when G10_e3 => |
if (rdy_i = '1') then |
sig_PC <= X"00" & d_alu_i; |
zw_b1 <= d_i; |
end if; |
when s585 => |
when G10_e1 => |
if (rdy_i = '1' AND |
zw_b2(0) = '0' and |
reg_F(3) = '0') then |
1381,7 → 1328,6
(zw_ALU(0))); |
reg_F(0) <= zw_ALU(8); |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
1397,7 → 1343,6
(zw_ALU(0))); |
reg_F(0) <= zw_ALU4(4); |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
1404,7 → 1349,7
elsif (rdy_i = '1') then |
sig_PC <= zw_b3 & zw_b1; |
end if; |
when s586 => |
when G10_e2 => |
if (rdy_i = '1' and |
reg_F(3) = '0') then |
sig_PC <= adr_pc_i; |
1416,7 → 1361,6
(zw_ALU(0))); |
reg_F(0) <= zw_ALU(8); |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
1431,22 → 1375,21
(zw_ALU(0))); |
reg_F(0) <= zw_ALU4(4); |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s587 => |
when G10_6 => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_b1; |
zw_b3 <= d_alu_i; |
end if; |
when s580 => |
when G10_8 => |
if (rdy_i = '1') then |
sig_PC <= X"00" & zw_b1; |
zw_b1 <= d_i; |
end if; |
when s178 => |
when G17_1 => |
if (rdy_i = '1' and |
(zw_REG_OP = X"85" OR |
zw_REG_OP = X"86" OR |
1494,77 → 1437,55
sig_PC <= X"00" & d_i; |
zw_b1 <= d_alu_i; |
end if; |
when s194 => |
when G17_4 => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_b1; |
zw_b3 <= d_alu_i; |
end if; |
when s195 => |
when G17_6 => |
if (rdy_i = '1') then |
sig_PC <= X"00" & zw_b1; |
zw_b1 <= d_alu_i; |
zw_b2(0) <= reg_0flag_i; |
end if; |
when s196 => |
when G17_3 => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_b1; |
end if; |
when s197 => |
sig_PC <= adr_pc_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
when s198 => |
when G17_2 => |
if (rdy_i = '1') then |
sig_PC <= X"00" & zw_b1; |
end if; |
when s199 => |
when G17_8 => |
if (rdy_i = '1') then |
sig_PC <= X"00" & zw_b1; |
end if; |
when s200 => |
sig_PC <= adr_pc_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
when s205 => |
when G17_9 => |
if (rdy_i = '1') then |
sig_PC <= X"00" & d_alu_i; |
zw_b1 <= d_i; |
end if; |
when s206 => |
when G17_7 => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_b1; |
zw_b3 <= d_alu_i; |
end if; |
when s207 => |
sig_PC <= adr_pc_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
when s208 => |
when G17_5 => |
sig_PC <= zw_b3 & zw_b1; |
when s209 => |
when G17_10 => |
sig_PC <= d_i & zw_b1; |
when s213 => |
when G17_e => |
sig_PC <= adr_pc_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
when s214 => |
when G17_11 => |
if (rdy_i = '1') then |
sig_PC <= X"00" & zw_b1; |
zw_b1 <= d_i; |
end if; |
when s513 => |
when G16_1 => |
if (rdy_i = '1' and |
zw_REG_OP = X"E5") then |
sig_PC <= X"00" & d_i; |
1580,7 → 1501,6
(zw_ALU(0))); |
reg_F(0) <= zw_ALU(8); |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
1622,7 → 1542,6
(zw_ALU(0))); |
reg_F(0) <= zw_ALU2(4); |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
1631,40 → 1550,40
sig_PC <= X"00" & d_i; |
zw_b1 <= d_alu_i; |
end if; |
when s588 => |
when G16_3 => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_b1; |
end if; |
when s589 => |
when G16_4 => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_b1; |
zw_b3 <= d_alu_i; |
end if; |
when s590 => |
when G16_5 => |
if (rdy_i = '1') then |
sig_PC <= X"00" & zw_b1; |
zw_b1 <= d_alu_i; |
zw_b2(0) <= reg_0flag_i; |
end if; |
when s591 => |
when G16_2 => |
if (rdy_i = '1') then |
sig_PC <= X"00" & zw_b1; |
end if; |
when s592 => |
when G16_7 => |
if (rdy_i = '1') then |
sig_PC <= X"00" & zw_b1; |
end if; |
when s593 => |
when G16_6 => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_b1; |
zw_b3 <= d_alu_i; |
end if; |
when s594 => |
when G16_e3 => |
if (rdy_i = '1') then |
sig_PC <= X"00" & d_alu_i; |
zw_b1 <= d_i; |
end if; |
when s595 => |
when G16_e1 => |
if (rdy_i = '1' AND |
zw_b2(0) = '0' and |
reg_F(3) = '0') then |
1677,7 → 1596,6
(zw_ALU(0))); |
reg_F(0) <= zw_ALU(8); |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
1693,7 → 1611,6
(zw_ALU(0))); |
reg_F(0) <= zw_ALU2(4); |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
1700,7 → 1617,7
elsif (rdy_i = '1') then |
sig_PC <= zw_b3 & zw_b1; |
end if; |
when s596 => |
when G16_e2 => |
if (rdy_i = '1' and |
reg_F(3) = '0') then |
sig_PC <= adr_pc_i; |
1712,7 → 1629,6
(zw_ALU(0))); |
reg_F(0) <= zw_ALU(8); |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
1727,17 → 1643,16
(zw_ALU(0))); |
reg_F(0) <= zw_ALU2(4); |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s597 => |
when G16_8 => |
if (rdy_i = '1') then |
sig_PC <= X"00" & zw_b1; |
zw_b1 <= d_i; |
end if; |
when s405 => |
when G11_1 => |
if (rdy_i = '1' and |
(zw_REG_OP = X"1E" or |
zw_REG_OP = X"7E" or |
1771,24 → 1686,24
zw_REG_OP (3 downto 0) = X"7") then |
sig_PC <= X"00" & d_i; |
end if; |
when s408 => |
when G11_5 => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_b1; |
end if; |
when s410 => |
when G11_6 => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_b1; |
zw_b3 <= d_alu_i; |
end if; |
when s411 => |
when G11_2 => |
if (rdy_i = '1') then |
sig_PC <= X"00" & zw_b1; |
end if; |
when s414 => |
when G11_7 => |
if (rdy_i = '1') then |
sig_PC <= zw_b3 & zw_b1; |
end if; |
when s417 => |
when G11_4 => |
if (rdy_i = '1' and |
(zw_REG_OP = X"06" or |
zw_REG_OP = X"16" or |
1832,11 → 1747,10
zw_REG_OP = X"0C")) then |
zw_b1 <= d_i and q_a_i; |
end if; |
when s419 => |
when G11_e => |
if (zw_REG_OP (3 downto 0) = X"7") then |
sig_PC <= adr_pc_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
1847,7 → 1761,6
reg_F(1) <= reg_1flag_i; |
sig_PC <= adr_pc_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
1857,12 → 1770,11
reg_F(1) <= reg_1flag_i; |
sig_PC <= adr_pc_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s420 => |
when G31_1 => |
if (rdy_i = '1') then |
sig_PC <= adr_pc_i; |
reg_F(0) <= q_a_i(7); |
1869,12 → 1781,11
reg_F(7) <= reg_7flag_i; |
reg_F(1) <= reg_1flag_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s598 => |
when G34_1 => |
if (rdy_i = '1') then |
sig_PC <= adr_pc_i; |
reg_F(0) <= q_a_i(0); |
1881,12 → 1792,11
reg_F(7) <= reg_7flag_i; |
reg_F(1) <= reg_1flag_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s599 => |
when G32_1 => |
if (rdy_i = '1') then |
sig_PC <= adr_pc_i; |
reg_F(0) <= q_a_i(0); |
1893,12 → 1803,11
reg_F(7) <= reg_7flag_i; |
reg_F(1) <= reg_1flag_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s600 => |
when G33_1 => |
if (rdy_i = '1') then |
sig_PC <= adr_pc_i; |
reg_F(0) <= q_a_i(7); |
1906,12 → 1815,11
reg_F(7) <= reg_7flag_i; |
reg_F(1) <= reg_1flag_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s268 => |
when G12_1 => |
if (rdy_i = '1' and ( |
(reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or |
(reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or |
1919,7 → 1827,6
(reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) then |
sig_PC <= adr_nxt_pc_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
1945,16 → 1852,14
elsif (rdy_i = '1') then |
sig_PC <= adr_nxt_pc_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "10"; |
zw_b2 <= d_i; |
end if; |
when s305 => |
when G12_e1 => |
if (rdy_i = '1' and |
zw_b3 = adr_nxt_pc_i (15 downto 8)) then |
sig_PC <= adr_nxt_pc_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
1961,21 → 1866,20
elsif (rdy_i = '1') then |
sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0); |
end if; |
when s306 => |
when G12_e2 => |
if (rdy_i = '1') then |
sig_PC <= adr_pc_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s267 => |
when G12_2 => |
if (rdy_i = '1') then |
sig_PC <= X"00" & zw_b1; |
zw_b2 <= d_i; |
end if; |
when s269 => |
when G12_3 => |
if (rdy_i = '1' and ( |
(d_i(0) = '1' and zw_REG_OP = X"8F") or |
(d_i(1) = '1' and zw_REG_OP = X"9F") or |
1997,18 → 1901,16
elsif (rdy_i = '1') then |
sig_PC <= adr_nxt_pc_i; |
end if; |
when s303 => |
when G12_4 => |
if (rdy_i = '1') then |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "10"; |
end if; |
when s272 => |
when G20_1 => |
if (rdy_i = '1' and |
zw_REG_OP = X"4C") then |
sig_PC <= adr_nxt_pc_i; |
reg_sel_pc_in <= '1'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "11"; |
zw_b1 <= d_i; |
elsif (rdy_i = '1' and |
2015,7 → 1917,6
zw_REG_OP = X"6C") then |
sig_PC <= adr_nxt_pc_i; |
reg_sel_pc_in <= '1'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
zw_b1 <= d_i; |
elsif (rdy_i = '1' and |
2022,67 → 1923,60
zw_REG_OP = X"7C") then |
sig_PC <= adr_nxt_pc_i; |
reg_sel_pc_in <= '1'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "10"; |
zw_b1 <= d_i; |
end if; |
when s275 => |
when G20_2 => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_b1; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
end if; |
when s308 => |
when G20_5 => |
if (rdy_i = '1') then |
sig_PC <= adr_pc_i; |
reg_sel_pc_in <= '1'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "11"; |
zw_b1 <= d_i; |
end if; |
when s309 => |
when G20_e => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_b1; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s274 => |
when G20_3 => |
if (rdy_i = '1') then |
sig_PC <= adr_nxt_pc_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
end if; |
when s402 => |
when G21_1 => |
if (rdy_i = '1') then |
sig_PC <= adr_sp_i; |
zw_b1 <= d_i; |
end if; |
when s422 => |
when G21_3 => |
sig_PC <= adr_sp_i; |
when s423 => |
when G21_4 => |
sig_PC <= adr_pc_i; |
reg_sel_pc_in <= '1'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "11"; |
when s424 => |
when G21_e => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_b1 (7 downto 0); |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s362 => |
when G13_3 => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_b1; |
end if; |
when s221 => |
when G13_1 => |
if (rdy_i = '1' and |
zw_REG_OP = X"34") then |
sig_PC <= X"00" & d_i; |
2104,21 → 1998,20
sig_PC <= adr_nxt_pc_i; |
reg_F(1) <= reg_1flag_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s232 => |
when G13_4 => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_b1; |
zw_b3 <= d_alu_i; |
end if; |
when s233 => |
when G13_2 => |
if (rdy_i = '1') then |
sig_PC <= X"00" & zw_b1; |
end if; |
when s234 => |
when G13_e1 => |
if (rdy_i = '1') then |
sig_PC <= adr_pc_i; |
reg_F(7) <= d_i(7); |
2125,12 → 2018,11
reg_F(6) <= d_i(6); |
reg_F(1) <= reg_1flag_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s235 => |
when G13_e2 => |
if (rdy_i = '1' AND |
zw_b2(0) = '0') then |
sig_PC <= adr_pc_i; |
2138,7 → 2030,6
reg_F(6) <= d_i(6); |
reg_F(1) <= reg_1flag_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
2145,94 → 2036,88
elsif (rdy_i = '1') then |
sig_PC <= zw_b3 & zw_b1; |
end if; |
when s538 => |
when G18_1 => |
if (rdy_i = '1') then |
sig_PC <= adr_sp_i; |
end if; |
when s539 => |
when G18_2 => |
sig_PC <= adr_sp_i; |
when s540 => |
when G18_3 => |
sig_PC <= adr_sp_i; |
when s541 => |
when G18_4 => |
sig_PC <= X"FFFE"; |
when s542 => |
when G18_e => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_b1; |
reg_F(2) <= '1'; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s543 => |
when G18_5 => |
if (rdy_i = '1') then |
sig_PC <= X"FFFF"; |
reg_sel_pc_in <= '1'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "11"; |
zw_b1 <= d_i; |
end if; |
when s425 => |
when G26_1 => |
if (rdy_i = '1') then |
sig_PC <= adr_sp_i; |
end if; |
when s426 => |
when G26_2 => |
if (rdy_i = '1') then |
sig_PC <= adr_sp_i; |
end if; |
when s427 => |
when G26_3 => |
if (rdy_i = '1') then |
sig_PC <= adr_sp_i; |
reg_F <= d_i; |
reg_sel_pc_in <= '1'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "11"; |
end if; |
when s428 => |
when G26_4 => |
if (rdy_i = '1') then |
sig_PC <= adr_sp_i; |
zw_b1 <= d_i; |
end if; |
when s429 => |
when G26_e => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_b1; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s430 => |
when G27_1 => |
if (rdy_i = '1') then |
sig_PC <= adr_sp_i; |
end if; |
when s431 => |
when G27_2 => |
if (rdy_i = '1') then |
sig_PC <= adr_sp_i; |
end if; |
when s432 => |
when G27_3 => |
if (rdy_i = '1') then |
sig_PC <= adr_sp_i; |
zw_b1 <= d_i; |
reg_sel_pc_in <= '1'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
end if; |
when s433 => |
when G27_4 => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_b1; |
end if; |
when s434 => |
when G27_e => |
if (rdy_i = '1') then |
sig_PC <= adr_pc_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s236 => |
when G14_1 => |
if (rdy_i = '1' and |
(zw_REG_OP = X"C6" OR |
zw_REG_OP = X"E6")) then |
2254,86 → 2139,78
zw_b1 <= d_alu_i; |
zw_b2(0) <= reg_0flag_i; |
end if; |
when s245 => |
when G14_5 => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_b1; |
end if; |
when s246 => |
when G14_6 => |
if (rdy_i = '1') then |
sig_PC <= d_i & zw_b1; |
zw_b3 <= d_alu_i; |
end if; |
when s248 => |
when G14_2 => |
if (rdy_i = '1') then |
sig_PC <= X"00" & zw_b1; |
end if; |
when s345 => |
if (rdy_i = '1'and |
zw_REG_OP = X"FE") then |
when G14_7 => |
if (rdy_i = '1') then |
sig_PC <= zw_b3 & zw_b1; |
elsif (rdy_i = '1') then |
sig_PC <= zw_b3 & zw_b1; |
end if; |
when s346 => |
when G14_3 => |
if (rdy_i = '1') then |
zw_b1 <= d_alu_i; |
end if; |
when s253 => |
sig_PC <= adr_pc_i; |
when G14_e => |
reg_F(7) <= reg_7flag_i; |
reg_F(1) <= reg_1flag_i; |
sig_PC <= adr_pc_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
when s435 => |
when G22_1 => |
if (rdy_i = '1') then |
sig_PC <= adr_sp_i; |
end if; |
when s436 => |
when G22_e => |
sig_PC <= adr_pc_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
when s437 => |
when G23_1 => |
if (rdy_i = '1') then |
sig_PC <= adr_sp_i; |
end if; |
when s438 => |
when G23_e => |
sig_PC <= adr_pc_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
when s440 => |
when G24_2 => |
if (rdy_i = '1') then |
sig_PC <= adr_sp_i; |
end if; |
when s441 => |
when G24_e => |
if (rdy_i = '1') then |
sig_PC <= adr_pc_i; |
reg_F(7) <= reg_7flag_i; |
reg_F(1) <= reg_1flag_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when s443 => |
when G25_2 => |
if (rdy_i = '1') then |
sig_PC <= adr_sp_i; |
end if; |
when s444 => |
when G25_e => |
if (rdy_i = '1') then |
sig_PC <= adr_pc_i; |
reg_F <= d_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_as <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
2360,82 → 2237,82
----------------------------------------------------------------- |
begin |
case current_state is |
when s544 => |
next_state <= s550; |
when s545 => |
next_state <= s546; |
when s546 => |
next_state <= s547; |
when s547 => |
when G30_1 => |
next_state <= G30_2; |
when G30_3 => |
next_state <= G30_4; |
when G30_4 => |
next_state <= G30_5; |
when G30_5 => |
if (rdy_i = '1') then |
next_state <= s549; |
next_state <= G30_e; |
else |
next_state <= s547; |
next_state <= G30_5; |
end if; |
when s549 => |
when G30_e => |
if (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s549; |
next_state <= G30_e; |
end if; |
when s550 => |
next_state <= s545; |
when G30_2 => |
next_state <= G30_3; |
when RES => |
next_state <= s544; |
when s548 => |
next_state <= G30_1; |
when G28_1 => |
if (rdy_i = '1') then |
next_state <= s551; |
next_state <= G28_2; |
else |
next_state <= s548; |
next_state <= G28_1; |
end if; |
when s551 => |
next_state <= s552; |
when s552 => |
next_state <= s576; |
when s575 => |
when G28_2 => |
next_state <= G28_3; |
when G28_3 => |
next_state <= G28_4; |
when G28_5 => |
if (rdy_i = '1') then |
next_state <= s577; |
next_state <= G28_e; |
else |
next_state <= s575; |
next_state <= G28_5; |
end if; |
when s576 => |
next_state <= s575; |
when s577 => |
when G28_4 => |
next_state <= G28_5; |
when G28_e => |
if (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s577; |
next_state <= G28_e; |
end if; |
when s532 => |
when G29_1 => |
if (rdy_i = '1') then |
next_state <= s533; |
next_state <= G29_2; |
else |
next_state <= s532; |
next_state <= G29_1; |
end if; |
when s533 => |
next_state <= s534; |
when s534 => |
next_state <= s536; |
when s535 => |
when G29_2 => |
next_state <= G29_3; |
when G29_3 => |
next_state <= G29_4; |
when G29_5 => |
if (rdy_i = '1') then |
next_state <= s537; |
next_state <= G29_e; |
else |
next_state <= s535; |
next_state <= G29_5; |
end if; |
when s536 => |
next_state <= s535; |
when s537 => |
when G29_4 => |
next_state <= G29_5; |
when G29_e => |
if (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s537; |
next_state <= G29_e; |
end if; |
when FETCH => |
if ((zw_REG_NMI = '1') and (rdy_i = '1')) then |
next_state <= s532; |
next_state <= G29_1; |
elsif ((irq_n_i = '0' and |
reg_F(2) = '0') and (rdy_i = '1')) then |
next_state <= s548; |
next_state <= G28_1; |
elsif ((d_i = X"69" or |
d_i = X"65" or |
d_i = X"75" or |
2445,7 → 2322,7
d_i = X"61" or |
d_i = X"71" or |
d_i = X"72") and (rdy_i = '1')) then |
next_state <= s512; |
next_state <= G10_1; |
elsif ((d_i = X"06" or |
d_i = X"16" or |
d_i = X"0E" or |
2455,7 → 2332,7
d_i = X"04" or |
d_i = X"0C" or |
d_i = X"1C") and (rdy_i = '1')) then |
next_state <= s405; |
next_state <= G11_1; |
elsif ((d_i = X"90" or |
d_i = X"B0" or |
d_i = X"F0" or |
2466,40 → 2343,40
d_i = X"70" or |
d_i = X"80" or |
d_i (3 downto 0) = X"F") and (rdy_i = '1')) then |
next_state <= s268; |
next_state <= G12_1; |
elsif ((d_i = X"24" or |
d_i = X"2C" or |
d_i = X"3C" or |
d_i = X"34" or |
d_i = X"89") and (rdy_i = '1')) then |
next_state <= s221; |
next_state <= G13_1; |
elsif ((d_i = X"00") and (rdy_i = '1')) then |
next_state <= s538; |
next_state <= G18_1; |
elsif ((d_i = X"18") and (rdy_i = '1')) then |
next_state <= s13; |
next_state <= G5_1; |
elsif ((d_i = X"D8") and (rdy_i = '1')) then |
next_state <= s18; |
next_state <= G6_1; |
elsif ((d_i = X"58") and (rdy_i = '1')) then |
next_state <= s19; |
next_state <= G7_1; |
elsif ((d_i = X"B8") and (rdy_i = '1')) then |
next_state <= s26; |
next_state <= G8_1; |
elsif ((d_i = X"E0" or |
d_i = X"E4" or |
d_i = X"EC") and (rdy_i = '1')) then |
next_state <= s203; |
next_state <= G15_1; |
elsif ((d_i = X"C0" or |
d_i = X"C4" or |
d_i = X"CC") and (rdy_i = '1')) then |
next_state <= s203; |
next_state <= G15_1; |
elsif ((d_i = X"C6" or |
d_i = X"D6" or |
d_i = X"CE" or |
d_i = X"DE") and (rdy_i = '1')) then |
next_state <= s236; |
next_state <= G14_1; |
elsif ((d_i = X"CA") and (rdy_i = '1')) then |
next_state <= s27; |
next_state <= G19_1; |
elsif ((d_i = X"88") and (rdy_i = '1')) then |
next_state <= s27; |
next_state <= G19_1; |
elsif ((d_i = X"49" or |
d_i = X"45" or |
d_i = X"55" or |
2536,22 → 2413,22
d_i = X"D2" or |
d_i = X"52" or |
d_i = X"12") and (rdy_i = '1')) then |
next_state <= s203; |
next_state <= G15_1; |
elsif ((d_i = X"E6" or |
d_i = X"F6" or |
d_i = X"EE" or |
d_i = X"FE") and (rdy_i = '1')) then |
next_state <= s236; |
next_state <= G14_1; |
elsif ((d_i = X"E8") and (rdy_i = '1')) then |
next_state <= s27; |
next_state <= G19_1; |
elsif ((d_i = X"C8") and (rdy_i = '1')) then |
next_state <= s27; |
next_state <= G19_1; |
elsif ((d_i = X"4C" or |
d_i = X"6C" or |
d_i = X"7C") and (rdy_i = '1')) then |
next_state <= s272; |
next_state <= G20_1; |
elsif ((d_i = X"20") and (rdy_i = '1')) then |
next_state <= s402; |
next_state <= G21_1; |
elsif ((d_i = X"A9" or |
d_i = X"A5" or |
d_i = X"B5" or |
2561,48 → 2438,48
d_i = X"A1" or |
d_i = X"B1" or |
d_i = X"B2") and (rdy_i = '1')) then |
next_state <= s203; |
next_state <= G15_1; |
elsif ((d_i = X"A2" or |
d_i = X"A6" or |
d_i = X"B6" or |
d_i = X"AE" or |
d_i = X"BE") and (rdy_i = '1')) then |
next_state <= s203; |
next_state <= G15_1; |
elsif ((d_i = X"A0" or |
d_i = X"A4" or |
d_i = X"B4" or |
d_i = X"AC" or |
d_i = X"BC") and (rdy_i = '1')) then |
next_state <= s203; |
next_state <= G15_1; |
elsif ((d_i = X"46" or |
d_i = X"56" or |
d_i = X"4E" or |
d_i = X"5E") and (rdy_i = '1')) then |
next_state <= s405; |
next_state <= G11_1; |
elsif ((d_i = X"EA") and (rdy_i = '1')) then |
next_state <= s6; |
next_state <= G1_1; |
elsif ((d_i = X"48") and (rdy_i = '1')) then |
next_state <= s435; |
next_state <= G22_1; |
elsif ((d_i = X"08") and (rdy_i = '1')) then |
next_state <= s437; |
next_state <= G23_1; |
elsif ((d_i = X"7A") and (rdy_i = '1')) then |
next_state <= s439; |
next_state <= G24_1; |
elsif ((d_i = X"28") and (rdy_i = '1')) then |
next_state <= s442; |
next_state <= G25_1; |
elsif ((d_i = X"26" or |
d_i = X"36" or |
d_i = X"2E" or |
d_i = X"3E") and (rdy_i = '1')) then |
next_state <= s405; |
next_state <= G11_1; |
elsif ((d_i = X"66" or |
d_i = X"76" or |
d_i = X"6E" or |
d_i = X"7E") and (rdy_i = '1')) then |
next_state <= s405; |
next_state <= G11_1; |
elsif ((d_i = X"40") and (rdy_i = '1')) then |
next_state <= s425; |
next_state <= G26_1; |
elsif ((d_i = X"60") and (rdy_i = '1')) then |
next_state <= s430; |
next_state <= G27_1; |
elsif ((d_i = X"E9" or |
d_i = X"E5" or |
d_i = X"F5" or |
2612,13 → 2489,13
d_i = X"E1" or |
d_i = X"F1" or |
d_i = X"F2") and (rdy_i = '1')) then |
next_state <= s513; |
next_state <= G16_1; |
elsif ((d_i = X"38") and (rdy_i = '1')) then |
next_state <= s7; |
next_state <= G2_1; |
elsif ((d_i = X"F8") and (rdy_i = '1')) then |
next_state <= s8; |
next_state <= G3_1; |
elsif ((d_i = X"78") and (rdy_i = '1')) then |
next_state <= s9; |
next_state <= G4_1; |
elsif ((d_i = X"85" or |
d_i = X"95" or |
d_i = X"8D" or |
2626,82 → 2503,82
d_i = X"99" or |
d_i = X"81" or |
d_i = X"91") and (rdy_i = '1')) then |
next_state <= s178; |
next_state <= G17_1; |
elsif ((d_i = X"86" or |
d_i = X"96" or |
d_i = X"8E") and (rdy_i = '1')) then |
next_state <= s178; |
next_state <= G17_1; |
elsif ((d_i = X"84" or |
d_i = X"94" or |
d_i = X"8C") and (rdy_i = '1')) then |
next_state <= s178; |
next_state <= G17_1; |
elsif ((d_i = X"AA") and (rdy_i = '1')) then |
next_state <= s10; |
next_state <= G9_1; |
elsif ((d_i = X"0A") and (rdy_i = '1')) then |
next_state <= s420; |
next_state <= G31_1; |
elsif ((d_i = X"4A") and (rdy_i = '1')) then |
next_state <= s599; |
next_state <= G32_1; |
elsif ((d_i = X"2A") and (rdy_i = '1')) then |
next_state <= s600; |
next_state <= G33_1; |
elsif ((d_i = X"6A") and (rdy_i = '1')) then |
next_state <= s598; |
next_state <= G34_1; |
elsif ((d_i = X"A8") and (rdy_i = '1')) then |
next_state <= s10; |
next_state <= G9_1; |
elsif ((d_i = X"98") and (rdy_i = '1')) then |
next_state <= s10; |
next_state <= G9_1; |
elsif ((d_i = X"BA") and (rdy_i = '1')) then |
next_state <= s10; |
next_state <= G9_1; |
elsif ((d_i = X"8A") and (rdy_i = '1')) then |
next_state <= s10; |
next_state <= G9_1; |
elsif ((d_i = X"9A") and (rdy_i = '1')) then |
next_state <= s10; |
next_state <= G9_1; |
elsif ((d_i = X"DA") and (rdy_i = '1')) then |
next_state <= s435; |
next_state <= G22_1; |
elsif ((d_i = X"5A") and (rdy_i = '1')) then |
next_state <= s435; |
next_state <= G22_1; |
elsif ((d_i = X"68") and (rdy_i = '1')) then |
next_state <= s439; |
next_state <= G24_1; |
elsif ((d_i = X"FA") and (rdy_i = '1')) then |
next_state <= s439; |
next_state <= G24_1; |
elsif ((d_i = X"9C" or |
d_i = X"9E" or |
d_i = X"64" or |
d_i = X"74") and (rdy_i = '1')) then |
next_state <= s178; |
next_state <= G17_1; |
elsif ((d_i = X"3A") and (rdy_i = '1')) then |
next_state <= s27; |
next_state <= G19_1; |
elsif ((d_i = X"1A") and (rdy_i = '1')) then |
next_state <= s27; |
next_state <= G19_1; |
elsif (rdy_i = '1') then |
next_state <= s6; |
next_state <= G1_1; |
else |
next_state <= FETCH; |
end if; |
when s6 => |
when G1_1 => |
if (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s6; |
next_state <= G1_1; |
end if; |
when s7 => |
when G2_1 => |
if (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s7; |
next_state <= G2_1; |
end if; |
when s8 => |
when G3_1 => |
if (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s8; |
next_state <= G3_1; |
end if; |
when s9 => |
when G4_1 => |
if (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s9; |
next_state <= G4_1; |
end if; |
when s10 => |
when G9_1 => |
if (rdy_i = '1' and |
zw_REG_OP = X"9A") then |
next_state <= FETCH; |
2711,45 → 2588,45
elsif (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s10; |
next_state <= G9_1; |
end if; |
when s13 => |
when G5_1 => |
if (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s13; |
next_state <= G5_1; |
end if; |
when s18 => |
when G6_1 => |
if (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s18; |
next_state <= G6_1; |
end if; |
when s19 => |
when G7_1 => |
if (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s19; |
next_state <= G7_1; |
end if; |
when s26 => |
when G8_1 => |
if (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s26; |
next_state <= G8_1; |
end if; |
when s27 => |
when G19_1 => |
if (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s27; |
next_state <= G19_1; |
end if; |
when s203 => |
when G15_1 => |
if (rdy_i = '1' and |
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR |
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR |
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR |
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then |
next_state <= s230; |
next_state <= G15_e2; |
elsif ((rdy_i = '1' and |
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR |
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or |
2794,7 → 2671,7
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR |
zw_REG_OP = X"35" OR |
zw_REG_OP = X"D5")) then |
next_state <= s219; |
next_state <= G15_2; |
elsif (rdy_i = '1' and |
(zw_REG_OP = X"AD" OR |
zw_REG_OP = X"AE" OR |
2805,7 → 2682,7
zw_REG_OP = X"CD" OR |
zw_REG_OP = X"EC" OR |
zw_REG_OP = X"CC")) then |
next_state <= s204; |
next_state <= G15_3; |
elsif (rdy_i = '1' and |
(zw_REG_OP = X"BD" OR |
zw_REG_OP = X"BC" OR |
2813,7 → 2690,7
zw_REG_OP = X"1D" OR |
zw_REG_OP = X"3D" OR |
zw_REG_OP = X"DD")) then |
next_state <= s212; |
next_state <= G15_4; |
elsif (rdy_i = '1' and |
(zw_REG_OP = X"B9" OR |
zw_REG_OP = X"BE" OR |
2821,7 → 2698,7
zw_REG_OP = X"19" OR |
zw_REG_OP = X"39" OR |
zw_REG_OP = X"D9")) then |
next_state <= s212; |
next_state <= G15_4; |
elsif (rdy_i = '1' and |
(zw_REG_OP = X"B1" OR |
zw_REG_OP = X"51" OR |
2828,7 → 2705,7
zw_REG_OP = X"11" OR |
zw_REG_OP = X"31" OR |
zw_REG_OP = X"D1")) then |
next_state <= s216; |
next_state <= G15_5; |
elsif (rdy_i = '1' and |
(zw_REG_OP = X"A1" OR |
zw_REG_OP = X"41" OR |
2835,10 → 2712,10
zw_REG_OP = X"01" OR |
zw_REG_OP = X"21" OR |
zw_REG_OP = X"C1")) then |
next_state <= s220; |
next_state <= G15_7; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"B6") then |
next_state <= s219; |
next_state <= G15_2; |
elsif (rdy_i = '1' and |
(zw_REG_OP = X"32" OR |
zw_REG_OP = X"D2" OR |
2845,53 → 2722,53
zw_REG_OP = X"52" OR |
zw_REG_OP = X"B2" OR |
zw_REG_OP = X"12")) then |
next_state <= s229; |
next_state <= G15_8; |
else |
next_state <= s203; |
next_state <= G15_1; |
end if; |
when s204 => |
when G15_3 => |
if (rdy_i = '1') then |
next_state <= s230; |
next_state <= G15_e2; |
else |
next_state <= s204; |
next_state <= G15_3; |
end if; |
when s212 => |
when G15_4 => |
if (rdy_i = '1') then |
next_state <= s231; |
next_state <= G15_e1; |
else |
next_state <= s212; |
next_state <= G15_4; |
end if; |
when s216 => |
when G15_5 => |
if (rdy_i = '1') then |
next_state <= s228; |
next_state <= G15_6; |
else |
next_state <= s216; |
next_state <= G15_5; |
end if; |
when s219 => |
when G15_2 => |
if (rdy_i = '1') then |
next_state <= s230; |
next_state <= G15_e2; |
else |
next_state <= s219; |
next_state <= G15_2; |
end if; |
when s220 => |
when G15_7 => |
if (rdy_i = '1') then |
next_state <= s227; |
next_state <= G15_e3; |
else |
next_state <= s220; |
next_state <= G15_7; |
end if; |
when s227 => |
when G15_e3 => |
if (rdy_i = '1') then |
next_state <= s204; |
next_state <= G15_3; |
else |
next_state <= s227; |
next_state <= G15_e3; |
end if; |
when s228 => |
when G15_6 => |
if (rdy_i = '1') then |
next_state <= s231; |
next_state <= G15_e1; |
else |
next_state <= s228; |
next_state <= G15_6; |
end if; |
when s230 => |
when G15_e2 => |
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or |
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or |
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or |
2921,9 → 2798,9
elsif (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s230; |
next_state <= G15_e2; |
end if; |
when s231 => |
when G15_e1 => |
if ((rdy_i = '1' AND |
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or |
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or |
2958,20 → 2835,20
zw_b2(0) = '0') then |
next_state <= FETCH; |
elsif (rdy_i = '1') then |
next_state <= s230; |
next_state <= G15_e2; |
else |
next_state <= s231; |
next_state <= G15_e1; |
end if; |
when s229 => |
when G15_8 => |
if (rdy_i = '1') then |
next_state <= s204; |
next_state <= G15_3; |
else |
next_state <= s229; |
next_state <= G15_8; |
end if; |
when s512 => |
when G10_1 => |
if (rdy_i = '1' and |
zw_REG_OP = X"65") then |
next_state <= s586; |
next_state <= G10_e2; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"69" and |
reg_F(3) = '0') then |
2978,22 → 2855,22
next_state <= FETCH; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"75") then |
next_state <= s582; |
next_state <= G10_2; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"6D") then |
next_state <= s554; |
next_state <= G10_3; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"7D") then |
next_state <= s578; |
next_state <= G10_4; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"79") then |
next_state <= s578; |
next_state <= G10_4; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"71") then |
next_state <= s581; |
next_state <= G10_5; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"61") then |
next_state <= s583; |
next_state <= G10_7; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"69" and |
reg_F(3) = '1') then |
3000,47 → 2877,47
next_state <= FETCH; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"72") then |
next_state <= s580; |
next_state <= G10_8; |
else |
next_state <= s512; |
next_state <= G10_1; |
end if; |
when s554 => |
when G10_3 => |
if (rdy_i = '1') then |
next_state <= s586; |
next_state <= G10_e2; |
else |
next_state <= s554; |
next_state <= G10_3; |
end if; |
when s578 => |
when G10_4 => |
if (rdy_i = '1') then |
next_state <= s585; |
next_state <= G10_e1; |
else |
next_state <= s578; |
next_state <= G10_4; |
end if; |
when s581 => |
when G10_5 => |
if (rdy_i = '1') then |
next_state <= s587; |
next_state <= G10_6; |
else |
next_state <= s581; |
next_state <= G10_5; |
end if; |
when s582 => |
when G10_2 => |
if (rdy_i = '1') then |
next_state <= s586; |
next_state <= G10_e2; |
else |
next_state <= s582; |
next_state <= G10_2; |
end if; |
when s583 => |
when G10_7 => |
if (rdy_i = '1') then |
next_state <= s584; |
next_state <= G10_e3; |
else |
next_state <= s583; |
next_state <= G10_7; |
end if; |
when s584 => |
when G10_e3 => |
if (rdy_i = '1') then |
next_state <= s554; |
next_state <= G10_3; |
else |
next_state <= s584; |
next_state <= G10_e3; |
end if; |
when s585 => |
when G10_e1 => |
if (rdy_i = '1' AND |
zw_b2(0) = '0' and |
reg_F(3) = '0') then |
3050,11 → 2927,11
reg_F(3) = '1') then |
next_state <= FETCH; |
elsif (rdy_i = '1') then |
next_state <= s586; |
next_state <= G10_e2; |
else |
next_state <= s585; |
next_state <= G10_e1; |
end if; |
when s586 => |
when G10_e2 => |
if (rdy_i = '1' and |
reg_F(3) = '0') then |
next_state <= FETCH; |
3062,124 → 2939,118
reg_F(3) = '1') then |
next_state <= FETCH; |
else |
next_state <= s586; |
next_state <= G10_e2; |
end if; |
when s587 => |
when G10_6 => |
if (rdy_i = '1') then |
next_state <= s585; |
next_state <= G10_e1; |
else |
next_state <= s587; |
next_state <= G10_6; |
end if; |
when s580 => |
when G10_8 => |
if (rdy_i = '1') then |
next_state <= s554; |
next_state <= G10_3; |
else |
next_state <= s580; |
next_state <= G10_8; |
end if; |
when s178 => |
when G17_1 => |
if (rdy_i = '1' and |
(zw_REG_OP = X"85" OR |
zw_REG_OP = X"86" OR |
zw_REG_OP = X"64" OR |
zw_REG_OP = X"84")) then |
next_state <= s197; |
next_state <= G17_e; |
elsif (rdy_i = '1' and |
(zw_REG_OP = X"95" OR |
zw_REG_OP = X"74" OR |
zw_REG_OP = X"94")) then |
next_state <= s198; |
next_state <= G17_2; |
elsif (rdy_i = '1' and |
(zw_REG_OP = X"8D" OR |
zw_REG_OP = X"8E" OR |
zw_REG_OP = X"9C" OR |
zw_REG_OP = X"8C")) then |
next_state <= s196; |
next_state <= G17_3; |
elsif (rdy_i = '1' and |
(zw_REG_OP = X"9D" OR |
zw_REG_OP = X"9E")) then |
next_state <= s194; |
next_state <= G17_4; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"99") then |
next_state <= s194; |
next_state <= G17_4; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"91") then |
next_state <= s195; |
next_state <= G17_6; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"81") then |
next_state <= s199; |
next_state <= G17_8; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"96") then |
next_state <= s198; |
next_state <= G17_2; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"92") then |
next_state <= s214; |
next_state <= G17_11; |
else |
next_state <= s178; |
next_state <= G17_1; |
end if; |
when s194 => |
when G17_4 => |
if (rdy_i = '1') then |
next_state <= s208; |
next_state <= G17_5; |
else |
next_state <= s194; |
next_state <= G17_4; |
end if; |
when s195 => |
when G17_6 => |
if (rdy_i = '1') then |
next_state <= s206; |
next_state <= G17_7; |
else |
next_state <= s195; |
next_state <= G17_6; |
end if; |
when s196 => |
when G17_3 => |
if (rdy_i = '1') then |
next_state <= s200; |
next_state <= G17_e; |
else |
next_state <= s196; |
next_state <= G17_3; |
end if; |
when s197 => |
next_state <= FETCH; |
when s198 => |
when G17_2 => |
if (rdy_i = '1') then |
next_state <= s207; |
next_state <= G17_e; |
else |
next_state <= s198; |
next_state <= G17_2; |
end if; |
when s199 => |
when G17_8 => |
if (rdy_i = '1') then |
next_state <= s205; |
next_state <= G17_9; |
else |
next_state <= s199; |
next_state <= G17_8; |
end if; |
when s200 => |
next_state <= FETCH; |
when s205 => |
when G17_9 => |
if (rdy_i = '1') then |
next_state <= s209; |
next_state <= G17_10; |
else |
next_state <= s205; |
next_state <= G17_9; |
end if; |
when s206 => |
when G17_7 => |
if (rdy_i = '1') then |
next_state <= s208; |
next_state <= G17_5; |
else |
next_state <= s206; |
next_state <= G17_7; |
end if; |
when s207 => |
when G17_5 => |
next_state <= G17_e; |
when G17_10 => |
next_state <= G17_e; |
when G17_e => |
next_state <= FETCH; |
when s208 => |
next_state <= s213; |
when s209 => |
next_state <= s213; |
when s213 => |
next_state <= FETCH; |
when s214 => |
when G17_11 => |
if (rdy_i = '1') then |
next_state <= s196; |
next_state <= G17_3; |
else |
next_state <= s214; |
next_state <= G17_11; |
end if; |
when s513 => |
when G16_1 => |
if (rdy_i = '1' and |
zw_REG_OP = X"E5") then |
next_state <= s596; |
next_state <= G16_e2; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"E9" and |
reg_F(3) = '0') then |
3186,22 → 3057,22
next_state <= FETCH; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"F5") then |
next_state <= s591; |
next_state <= G16_2; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"ED") then |
next_state <= s588; |
next_state <= G16_3; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"FD") then |
next_state <= s589; |
next_state <= G16_4; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"F9") then |
next_state <= s589; |
next_state <= G16_4; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"F1") then |
next_state <= s590; |
next_state <= G16_5; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"E1") then |
next_state <= s592; |
next_state <= G16_7; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"E9" and |
reg_F(3) = '1') then |
3208,53 → 3079,53
next_state <= FETCH; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"F2") then |
next_state <= s597; |
next_state <= G16_8; |
else |
next_state <= s513; |
next_state <= G16_1; |
end if; |
when s588 => |
when G16_3 => |
if (rdy_i = '1') then |
next_state <= s596; |
next_state <= G16_e2; |
else |
next_state <= s588; |
next_state <= G16_3; |
end if; |
when s589 => |
when G16_4 => |
if (rdy_i = '1') then |
next_state <= s595; |
next_state <= G16_e1; |
else |
next_state <= s589; |
next_state <= G16_4; |
end if; |
when s590 => |
when G16_5 => |
if (rdy_i = '1') then |
next_state <= s593; |
next_state <= G16_6; |
else |
next_state <= s590; |
next_state <= G16_5; |
end if; |
when s591 => |
when G16_2 => |
if (rdy_i = '1') then |
next_state <= s596; |
next_state <= G16_e2; |
else |
next_state <= s591; |
next_state <= G16_2; |
end if; |
when s592 => |
when G16_7 => |
if (rdy_i = '1') then |
next_state <= s594; |
next_state <= G16_e3; |
else |
next_state <= s592; |
next_state <= G16_7; |
end if; |
when s593 => |
when G16_6 => |
if (rdy_i = '1') then |
next_state <= s595; |
next_state <= G16_e1; |
else |
next_state <= s593; |
next_state <= G16_6; |
end if; |
when s594 => |
when G16_e3 => |
if (rdy_i = '1') then |
next_state <= s588; |
next_state <= G16_3; |
else |
next_state <= s594; |
next_state <= G16_e3; |
end if; |
when s595 => |
when G16_e1 => |
if (rdy_i = '1' AND |
zw_b2(0) = '0' and |
reg_F(3) = '0') then |
3264,11 → 3135,11
reg_F(3) = '1') then |
next_state <= FETCH; |
elsif (rdy_i = '1') then |
next_state <= s596; |
next_state <= G16_e2; |
else |
next_state <= s595; |
next_state <= G16_e1; |
end if; |
when s596 => |
when G16_e2 => |
if (rdy_i = '1' and |
reg_F(3) = '0') then |
next_state <= FETCH; |
3276,32 → 3147,32
reg_F(3) = '1') then |
next_state <= FETCH; |
else |
next_state <= s596; |
next_state <= G16_e2; |
end if; |
when s597 => |
when G16_8 => |
if (rdy_i = '1') then |
next_state <= s588; |
next_state <= G16_3; |
else |
next_state <= s597; |
next_state <= G16_8; |
end if; |
when s405 => |
when G11_1 => |
if (rdy_i = '1' and |
(zw_REG_OP = X"1E" or |
zw_REG_OP = X"7E" or |
zw_REG_OP = X"3E" or |
zw_REG_OP = X"5E")) then |
next_state <= s410; |
next_state <= G11_6; |
elsif (rdy_i = '1' and |
(zw_REG_OP = X"06" or zw_REG_OP = X"66" or |
zw_REG_OP = X"26" or zw_REG_OP = X"46" or |
zw_REG_OP = X"04" or zw_REG_OP = X"14")) then |
next_state <= s415; |
next_state <= G11_3; |
elsif (rdy_i = '1' and |
(zw_REG_OP = X"16" or |
zw_REG_OP = X"76" or |
zw_REG_OP = X"36" or |
zw_REG_OP = X"56")) then |
next_state <= s411; |
next_state <= G11_2; |
elsif (rdy_i = '1' and |
(zw_REG_OP = X"0E" or |
zw_REG_OP = X"6E" or |
3309,88 → 3180,88
zw_REG_OP = X"4E"or |
zw_REG_OP = X"0C" or |
zw_REG_OP = X"1C")) then |
next_state <= s408; |
next_state <= G11_5; |
elsif (rdy_i = '1' and |
zw_REG_OP (3 downto 0) = X"7") then |
next_state <= s415; |
next_state <= G11_3; |
else |
next_state <= s405; |
next_state <= G11_1; |
end if; |
when s408 => |
when G11_5 => |
if (rdy_i = '1') then |
next_state <= s415; |
next_state <= G11_3; |
else |
next_state <= s408; |
next_state <= G11_5; |
end if; |
when s410 => |
when G11_6 => |
if (rdy_i = '1') then |
next_state <= s414; |
next_state <= G11_7; |
else |
next_state <= s410; |
next_state <= G11_6; |
end if; |
when s411 => |
when G11_2 => |
if (rdy_i = '1') then |
next_state <= s415; |
next_state <= G11_3; |
else |
next_state <= s411; |
next_state <= G11_2; |
end if; |
when s414 => |
when G11_7 => |
if (rdy_i = '1') then |
next_state <= s417; |
next_state <= G11_4; |
else |
next_state <= s414; |
next_state <= G11_7; |
end if; |
when s415 => |
when G11_3 => |
if (rdy_i = '1') then |
next_state <= s417; |
next_state <= G11_4; |
else |
next_state <= s415; |
next_state <= G11_3; |
end if; |
when s417 => |
when G11_4 => |
if (rdy_i = '1' and |
(zw_REG_OP = X"06" or |
zw_REG_OP = X"16" or |
zw_REG_OP = X"0E" or |
zw_REG_OP = X"1E")) then |
next_state <= s419; |
next_state <= G11_e; |
elsif (rdy_i = '1' and |
(zw_REG_OP = X"46" or |
zw_REG_OP = X"56" or |
zw_REG_OP = X"4E" or |
zw_REG_OP = X"5E")) then |
next_state <= s419; |
next_state <= G11_e; |
elsif (rdy_i = '1' and |
(zw_REG_OP = X"26" or |
zw_REG_OP = X"36" or |
zw_REG_OP = X"2E" or |
zw_REG_OP = X"3E")) then |
next_state <= s419; |
next_state <= G11_e; |
elsif (rdy_i = '1' and |
(zw_REG_OP = X"66" or |
zw_REG_OP = X"76" or |
zw_REG_OP = X"6E" or |
zw_REG_OP = X"7E")) then |
next_state <= s419; |
next_state <= G11_e; |
elsif (rdy_i = '1' and |
zw_REG_OP (7) = '0' and |
zw_REG_OP (3 downto 0) = X"7") then |
next_state <= s419; |
next_state <= G11_e; |
elsif (rdy_i = '1' and |
zw_REG_OP (7) = '1' and |
zw_REG_OP (3 downto 0) = X"7") then |
next_state <= s419; |
next_state <= G11_e; |
elsif (rdy_i = '1' and |
(zw_REG_OP = X"14" or |
zw_REG_OP = X"1C")) then |
next_state <= s419; |
next_state <= G11_e; |
elsif (rdy_i = '1' and |
(zw_REG_OP = X"04" or |
zw_REG_OP = X"0C")) then |
next_state <= s419; |
next_state <= G11_e; |
else |
next_state <= s417; |
next_state <= G11_4; |
end if; |
when s419 => |
when G11_e => |
if (zw_REG_OP (3 downto 0) = X"7") then |
next_state <= FETCH; |
elsif ((zw_REG_OP = X"14" or |
3401,31 → 3272,31
else |
next_state <= FETCH; |
end if; |
when s420 => |
when G31_1 => |
if (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s420; |
next_state <= G31_1; |
end if; |
when s598 => |
when G34_1 => |
if (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s598; |
next_state <= G34_1; |
end if; |
when s599 => |
when G32_1 => |
if (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s599; |
next_state <= G32_1; |
end if; |
when s600 => |
when G33_1 => |
if (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s600; |
next_state <= G33_1; |
end if; |
when s268 => |
when G12_1 => |
if (rdy_i = '1' and ( |
(reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or |
(reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or |
3449,34 → 3320,34
zw_REG_OP = X"5F" or |
zw_REG_OP = X"6F" or |
zw_REG_OP = X"7F")) then |
next_state <= s267; |
next_state <= G12_2; |
elsif (rdy_i = '1') then |
next_state <= s305; |
next_state <= G12_e1; |
else |
next_state <= s268; |
next_state <= G12_1; |
end if; |
when s305 => |
when G12_e1 => |
if (rdy_i = '1' and |
zw_b3 = adr_nxt_pc_i (15 downto 8)) then |
next_state <= FETCH; |
elsif (rdy_i = '1') then |
next_state <= s306; |
next_state <= G12_e2; |
else |
next_state <= s305; |
next_state <= G12_e1; |
end if; |
when s306 => |
when G12_e2 => |
if (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s306; |
next_state <= G12_e2; |
end if; |
when s267 => |
when G12_2 => |
if (rdy_i = '1') then |
next_state <= s269; |
next_state <= G12_3; |
else |
next_state <= s267; |
next_state <= G12_2; |
end if; |
when s269 => |
when G12_3 => |
if (rdy_i = '1' and ( |
(d_i(0) = '1' and zw_REG_OP = X"8F") or |
(d_i(1) = '1' and zw_REG_OP = X"9F") or |
3494,338 → 3365,329
(d_i(5) = '0' and zw_REG_OP = X"5F") or |
(d_i(6) = '0' and zw_REG_OP = X"6F") or |
(d_i(7) = '0' and zw_REG_OP = X"7F"))) then |
next_state <= s303; |
next_state <= G12_4; |
elsif (rdy_i = '1') then |
next_state <= s306; |
next_state <= G12_e2; |
else |
next_state <= s269; |
next_state <= G12_3; |
end if; |
when s303 => |
when G12_4 => |
if (rdy_i = '1') then |
next_state <= s305; |
next_state <= G12_e1; |
else |
next_state <= s303; |
next_state <= G12_4; |
end if; |
when s272 => |
when G20_1 => |
if (rdy_i = '1' and |
zw_REG_OP = X"4C") then |
next_state <= s309; |
next_state <= G20_e; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"6C") then |
next_state <= s275; |
next_state <= G20_2; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"7C") then |
next_state <= s274; |
next_state <= G20_3; |
else |
next_state <= s272; |
next_state <= G20_1; |
end if; |
when s275 => |
when G20_2 => |
if (rdy_i = '1') then |
next_state <= s310; |
next_state <= G20_4; |
else |
next_state <= s275; |
next_state <= G20_2; |
end if; |
when s308 => |
when G20_5 => |
if (rdy_i = '1') then |
next_state <= s309; |
next_state <= G20_e; |
else |
next_state <= s308; |
next_state <= G20_5; |
end if; |
when s309 => |
when G20_e => |
if (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s309; |
next_state <= G20_e; |
end if; |
when s274 => |
when G20_3 => |
if (rdy_i = '1') then |
next_state <= s310; |
next_state <= G20_4; |
else |
next_state <= s274; |
next_state <= G20_3; |
end if; |
when s310 => |
when G20_4 => |
if (rdy_i = '1') then |
next_state <= s308; |
next_state <= G20_5; |
else |
next_state <= s310; |
next_state <= G20_4; |
end if; |
when s402 => |
when G21_1 => |
if (rdy_i = '1') then |
next_state <= s421; |
next_state <= G21_2; |
else |
next_state <= s402; |
next_state <= G21_1; |
end if; |
when s421 => |
when G21_2 => |
if (rdy_i = '1') then |
next_state <= s422; |
next_state <= G21_3; |
else |
next_state <= s421; |
next_state <= G21_2; |
end if; |
when s422 => |
next_state <= s423; |
when s423 => |
next_state <= s424; |
when s424 => |
when G21_3 => |
next_state <= G21_4; |
when G21_4 => |
next_state <= G21_e; |
when G21_e => |
if (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s424; |
next_state <= G21_e; |
end if; |
when s362 => |
when G13_3 => |
if (rdy_i = '1') then |
next_state <= s234; |
next_state <= G13_e1; |
else |
next_state <= s362; |
next_state <= G13_3; |
end if; |
when s221 => |
when G13_1 => |
if (rdy_i = '1' and |
zw_REG_OP = X"34") then |
next_state <= s233; |
next_state <= G13_2; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"3C") then |
next_state <= s232; |
next_state <= G13_4; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"24") then |
next_state <= s234; |
next_state <= G13_e1; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"2C") then |
next_state <= s362; |
next_state <= G13_3; |
elsif (rdy_i = '1' and |
zw_REG_OP = X"89") then |
next_state <= FETCH; |
else |
next_state <= s221; |
next_state <= G13_1; |
end if; |
when s232 => |
when G13_4 => |
if (rdy_i = '1') then |
next_state <= s235; |
next_state <= G13_e2; |
else |
next_state <= s232; |
next_state <= G13_4; |
end if; |
when s233 => |
when G13_2 => |
if (rdy_i = '1') then |
next_state <= s234; |
next_state <= G13_e1; |
else |
next_state <= s233; |
next_state <= G13_2; |
end if; |
when s234 => |
when G13_e1 => |
if (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s234; |
next_state <= G13_e1; |
end if; |
when s235 => |
when G13_e2 => |
if (rdy_i = '1' AND |
zw_b2(0) = '0') then |
next_state <= FETCH; |
elsif (rdy_i = '1') then |
next_state <= s234; |
next_state <= G13_e1; |
else |
next_state <= s235; |
next_state <= G13_e2; |
end if; |
when s538 => |
when G18_1 => |
if (rdy_i = '1') then |
next_state <= s539; |
next_state <= G18_2; |
else |
next_state <= s538; |
next_state <= G18_1; |
end if; |
when s539 => |
next_state <= s540; |
when s540 => |
next_state <= s541; |
when s541 => |
next_state <= s543; |
when s542 => |
when G18_2 => |
next_state <= G18_3; |
when G18_3 => |
next_state <= G18_4; |
when G18_4 => |
next_state <= G18_5; |
when G18_e => |
if (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s542; |
next_state <= G18_e; |
end if; |
when s543 => |
when G18_5 => |
if (rdy_i = '1') then |
next_state <= s542; |
next_state <= G18_e; |
else |
next_state <= s543; |
next_state <= G18_5; |
end if; |
when s425 => |
when G26_1 => |
if (rdy_i = '1') then |
next_state <= s426; |
next_state <= G26_2; |
else |
next_state <= s425; |
next_state <= G26_1; |
end if; |
when s426 => |
when G26_2 => |
if (rdy_i = '1') then |
next_state <= s427; |
next_state <= G26_3; |
else |
next_state <= s426; |
next_state <= G26_2; |
end if; |
when s427 => |
when G26_3 => |
if (rdy_i = '1') then |
next_state <= s428; |
next_state <= G26_4; |
else |
next_state <= s427; |
next_state <= G26_3; |
end if; |
when s428 => |
when G26_4 => |
if (rdy_i = '1') then |
next_state <= s429; |
next_state <= G26_e; |
else |
next_state <= s428; |
next_state <= G26_4; |
end if; |
when s429 => |
when G26_e => |
if (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s429; |
next_state <= G26_e; |
end if; |
when s430 => |
when G27_1 => |
if (rdy_i = '1') then |
next_state <= s431; |
next_state <= G27_2; |
else |
next_state <= s430; |
next_state <= G27_1; |
end if; |
when s431 => |
when G27_2 => |
if (rdy_i = '1') then |
next_state <= s432; |
next_state <= G27_3; |
else |
next_state <= s431; |
next_state <= G27_2; |
end if; |
when s432 => |
when G27_3 => |
if (rdy_i = '1') then |
next_state <= s433; |
next_state <= G27_4; |
else |
next_state <= s432; |
next_state <= G27_3; |
end if; |
when s433 => |
when G27_4 => |
if (rdy_i = '1') then |
next_state <= s434; |
next_state <= G27_e; |
else |
next_state <= s433; |
next_state <= G27_4; |
end if; |
when s434 => |
when G27_e => |
if (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s434; |
next_state <= G27_e; |
end if; |
when s236 => |
when G14_1 => |
if (rdy_i = '1' and |
(zw_REG_OP = X"C6" OR |
zw_REG_OP = X"E6")) then |
next_state <= s346; |
next_state <= G14_3; |
elsif (rdy_i = '1' and |
(zw_REG_OP = X"D6" OR |
zw_REG_OP = X"F6")) then |
next_state <= s248; |
next_state <= G14_2; |
elsif (rdy_i = '1' and |
(zw_REG_OP = X"CE" OR |
zw_REG_OP = X"EE")) then |
next_state <= s245; |
next_state <= G14_5; |
elsif (rdy_i = '1' and |
(zw_REG_OP = X"DE" OR |
zw_REG_OP = X"FE")) then |
next_state <= s246; |
next_state <= G14_6; |
else |
next_state <= s236; |
next_state <= G14_1; |
end if; |
when s245 => |
when G14_5 => |
if (rdy_i = '1') then |
next_state <= s346; |
next_state <= G14_3; |
else |
next_state <= s245; |
next_state <= G14_5; |
end if; |
when s246 => |
when G14_6 => |
if (rdy_i = '1') then |
next_state <= s345; |
next_state <= G14_7; |
else |
next_state <= s246; |
next_state <= G14_6; |
end if; |
when s248 => |
when G14_2 => |
if (rdy_i = '1') then |
next_state <= s346; |
next_state <= G14_3; |
else |
next_state <= s248; |
next_state <= G14_2; |
end if; |
when s345 => |
if (rdy_i = '1'and |
zw_REG_OP = X"FE") then |
next_state <= s0; |
elsif (rdy_i = '1') then |
next_state <= s346; |
when G14_7 => |
if (rdy_i = '1') then |
next_state <= G14_3; |
else |
next_state <= s345; |
next_state <= G14_7; |
end if; |
when s346 => |
when G14_3 => |
if (rdy_i = '1') then |
next_state <= s252; |
next_state <= G14_4; |
else |
next_state <= s346; |
next_state <= G14_3; |
end if; |
when s252 => |
when G14_4 => |
if (rdy_i = '1') then |
next_state <= s253; |
next_state <= G14_e; |
else |
next_state <= s252; |
next_state <= G14_4; |
end if; |
when s253 => |
when G14_e => |
next_state <= FETCH; |
when s435 => |
when G22_1 => |
if (rdy_i = '1') then |
next_state <= s436; |
next_state <= G22_e; |
else |
next_state <= s435; |
next_state <= G22_1; |
end if; |
when s436 => |
when G22_e => |
next_state <= FETCH; |
when s437 => |
when G23_1 => |
if (rdy_i = '1') then |
next_state <= s438; |
next_state <= G23_e; |
else |
next_state <= s437; |
next_state <= G23_1; |
end if; |
when s438 => |
when G23_e => |
next_state <= FETCH; |
when s439 => |
when G24_1 => |
if (rdy_i = '1') then |
next_state <= s440; |
next_state <= G24_2; |
else |
next_state <= s439; |
next_state <= G24_1; |
end if; |
when s440 => |
when G24_2 => |
if (rdy_i = '1') then |
next_state <= s441; |
next_state <= G24_e; |
else |
next_state <= s440; |
next_state <= G24_2; |
end if; |
when s441 => |
when G24_e => |
if (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s441; |
next_state <= G24_e; |
end if; |
when s442 => |
when G25_1 => |
if (rdy_i = '1') then |
next_state <= s443; |
next_state <= G25_2; |
else |
next_state <= s442; |
next_state <= G25_1; |
end if; |
when s443 => |
when G25_2 => |
if (rdy_i = '1') then |
next_state <= s444; |
next_state <= G25_e; |
else |
next_state <= s443; |
next_state <= G25_2; |
end if; |
when s444 => |
when G25_e => |
if (rdy_i = '1') then |
next_state <= FETCH; |
else |
next_state <= s444; |
next_state <= G25_e; |
end if; |
when s0 => |
if (rdy_i = '1') then |
next_state <= s253; |
else |
next_state <= s0; |
end if; |
when others => |
next_state <= RES; |
end case; |
3836,6 → 3698,7
adr_nxt_pc_i, |
adr_pc_i, |
adr_sp_i, |
alu_dec_val_i, |
current_state, |
d_alu_i, |
d_i, |
3846,7 → 3709,6
q_y_i, |
rdy_i, |
reg_F, |
reg_sel_pc_as, |
reg_sel_pc_in, |
reg_sel_pc_val, |
reg_sel_rb_in, |
3884,7 → 3746,6
ld_sp_o <= '0'; |
load_regs_o <= '0'; |
offset_o <= X"0000"; |
sel_pc_as_o <= reg_sel_pc_as; |
sel_pc_in_o <= reg_sel_pc_in; |
sel_pc_val_o <= reg_sel_pc_val; |
sel_rb_in_o <= reg_sel_rb_in; |
3894,31 → 3755,29
sel_sp_in_o <= reg_sel_sp_in; |
-- Default Assignment To Internals |
sig_D_OUT <= X"00"; |
sig_RD <= '1'; |
sig_RWn <= '1'; |
sig_SYNC <= '0'; |
sig_WR <= '0'; |
zw_ALU <= '0' & X"00"; |
zw_ALU1 <= '0' & X"00"; |
zw_ALU2 <= '0' & X"00"; |
zw_ALU3 <= '0' & X"00"; |
zw_ALU4 <= '0' & X"00"; |
zw_ALU5 <= '0' & X"00"; |
zw_ALU6 <= '0' & X"00"; |
zw_ALU1 <= '0' & X"0"; |
zw_ALU2 <= '0' & X"0"; |
zw_ALU3 <= '0' & X"0"; |
zw_ALU4 <= '0' & X"0"; |
zw_ALU5 <= X"0"; |
zw_ALU6 <= X"0"; |
|
-- Combined Actions |
case current_state is |
when s544 => |
when G30_1 => |
ld_o <= "11"; |
ld_sp_o <= '1'; |
when s545 => |
when G30_3 => |
adr_o <= X"FFFB"; |
ld_o <= "11"; |
ld_pc_o <= '1'; |
when s546 => |
when G30_4 => |
ld_o <= "11"; |
ld_pc_o <= '1'; |
when s549 => |
when G30_e => |
if (rdy_i = '1') then |
adr_o <= d_i & zw_w1 (7 downto 0); |
ld_o <= "11"; |
3926,70 → 3785,55
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s550 => |
when G30_2 => |
ld_o <= "11"; |
ld_sp_o <= '1'; |
when RES => |
ld_o <= "11"; |
ld_pc_o <= '1'; |
|
ld_sp_o <= '1'; |
sig_RWn <= '1'; |
sig_RD <= '1'; |
when s548 => |
when G28_1 => |
if (rdy_i = '1') then |
ld_o <= "11"; |
ld_sp_o <= '1'; |
ld_pc_o <= '1'; |
sig_RWn <= '0'; |
sig_RD <= '0'; |
sig_WR <= '1'; |
sig_D_OUT <= adr_pc_i (15 downto 8); |
end if; |
when s551 => |
when G28_2 => |
ld_o <= "11"; |
ld_sp_o <= '1'; |
sig_RWn <= '0'; |
sig_RD <= '0'; |
sig_WR <= '1'; |
sig_D_OUT <= adr_pc_i (7 downto 0); |
when s552 => |
when G28_3 => |
ld_o <= "11"; |
ld_sp_o <= '1'; |
sig_RWn <= '0'; |
sig_RD <= '0'; |
sig_WR <= '1'; |
sig_D_OUT <= reg_F; |
when s577 => |
when G28_e => |
if (rdy_i = '1') then |
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s532 => |
when G29_1 => |
if (rdy_i = '1') then |
ld_o <= "11"; |
ld_sp_o <= '1'; |
ld_pc_o <= '1'; |
sig_RWn <= '0'; |
sig_RD <= '0'; |
sig_WR <= '1'; |
sig_D_OUT <= adr_pc_i (15 downto 8); |
end if; |
when s533 => |
when G29_2 => |
ld_o <= "11"; |
ld_sp_o <= '1'; |
sig_RWn <= '0'; |
sig_RD <= '0'; |
sig_WR <= '1'; |
sig_D_OUT <= adr_pc_i (7 downto 0); |
when s534 => |
when G29_3 => |
ld_o <= "11"; |
ld_sp_o <= '1'; |
sig_RWn <= '0'; |
sig_RD <= '0'; |
sig_WR <= '1'; |
sig_D_OUT <= reg_F; |
when s537 => |
when G29_e => |
if (rdy_i = '1') then |
adr_o <= d_i & zw_b1; |
ld_o <= "11"; |
3998,8 → 3842,6
fetch_o <= '1'; |
end if; |
when FETCH => |
sig_RWn <= '1'; |
sig_RD <= '1'; |
sig_SYNC <= NOT (rdy_i); |
if ((zw_REG_NMI = '1') and (rdy_i = '1')) then |
ld_o <= "11"; |
4047,8 → 3889,6
d_i = X"3C" or |
d_i = X"34" or |
d_i = X"89") and (rdy_i = '1')) then |
|
|
ld_o <= "11"; |
ld_pc_o <= '1'; |
elsif ((d_i = X"00") and (rdy_i = '1')) then |
4313,27 → 4153,27
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s6 => |
when G1_1 => |
if (rdy_i = '1') then |
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s7 => |
when G2_1 => |
if (rdy_i = '1') then |
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s8 => |
when G3_1 => |
if (rdy_i = '1') then |
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s9 => |
when G4_1 => |
if (rdy_i = '1') then |
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s10 => |
when G9_1 => |
if (rdy_i = '1' and |
zw_REG_OP = X"9A") then |
adr_o <= X"01" & d_regs_out_i; |
4356,27 → 4196,27
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s13 => |
when G5_1 => |
if (rdy_i = '1') then |
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s18 => |
when G6_1 => |
if (rdy_i = '1') then |
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s19 => |
when G7_1 => |
if (rdy_i = '1') then |
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s26 => |
when G8_1 => |
if (rdy_i = '1') then |
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s27 => |
when G19_1 => |
if (rdy_i = '1') then |
d_regs_in_o <= d_alu_i; |
ch_a_o <= d_regs_out_i; |
4385,7 → 4225,7
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s203 => |
when G15_1 => |
if (rdy_i = '1' and |
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR |
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR |
4534,12 → 4374,12
ch_a_o <= d_i; |
ch_b_o <= X"01"; |
end if; |
when s204 => |
when G15_3 => |
if (rdy_i = '1') then |
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s212 => |
when G15_4 => |
if (rdy_i = '1') then |
ch_a_o <= d_i; |
ch_b_o <= "0000000" & zw_b2(0); |
4546,22 → 4386,22
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s216 => |
when G15_5 => |
if (rdy_i = '1') then |
ch_a_o <= d_i; |
ch_b_o <= q_y_i; |
end if; |
when s219 => |
when G15_2 => |
if (rdy_i = '1') then |
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s227 => |
when G15_e3 => |
if (rdy_i = '1') then |
ch_a_o <= zw_b1; |
ch_b_o <= X"01"; |
end if; |
when s228 => |
when G15_6 => |
if (rdy_i = '1') then |
ch_a_o <= d_i; |
ch_b_o <= "0000000" & zw_b2(0); |
4568,7 → 4408,7
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s230 => |
when G15_e2 => |
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or |
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or |
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or |
4620,7 → 4460,7
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s231 => |
when G15_e1 => |
if ((rdy_i = '1' AND |
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or |
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or |
4677,7 → 4517,7
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s512 => |
when G10_1 => |
if (rdy_i = '1' and |
zw_REG_OP = X"65") then |
ld_o <= "11"; |
4727,19 → 4567,17
ld_pc_o <= '1'; |
d_regs_in_o <= zw_ALU(7 downto 0); |
load_regs_o <= '1'; |
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU4(7 downto 5)); |
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU3(7 downto 5)); |
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0)); |
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0)); |
|
zw_ALU4(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0'; |
zw_ALU3(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0'; |
zw_ALU6(2 downto 0) <= (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0'; |
zw_ALU5(2 downto 0) <= (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0'; |
|
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; |
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned |
('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4)); |
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; |
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4)); |
|
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; |
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned |
('0' & d_i(3 downto 0)) + reg_F(0); |
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; |
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0); |
sig_SYNC <= '1'; |
fetch_o <= '1'; |
elsif (rdy_i = '1' and |
4747,12 → 4585,12
ch_a_o <= d_i; |
ch_b_o <= X"01"; |
end if; |
when s554 => |
when G10_3 => |
if (rdy_i = '1') then |
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s578 => |
when G10_4 => |
if (rdy_i = '1') then |
ch_a_o <= d_i; |
ch_b_o <= X"01"; |
4759,22 → 4597,22
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s581 => |
when G10_5 => |
if (rdy_i = '1') then |
ch_a_o <= d_i; |
ch_b_o <= q_y_i; |
end if; |
when s582 => |
when G10_2 => |
if (rdy_i = '1') then |
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s584 => |
when G10_e3 => |
if (rdy_i = '1') then |
ch_a_o <= zw_b1; |
ch_b_o <= X"01"; |
end if; |
when s585 => |
when G10_e1 => |
if (rdy_i = '1' AND |
zw_b2(0) = '0' and |
reg_F(3) = '0') then |
4788,23 → 4626,21
reg_F(3) = '1') then |
d_regs_in_o <= zw_ALU(7 downto 0); |
load_regs_o <= '1'; |
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU4(7 downto 5)); |
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU3(7 downto 5)); |
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0)); |
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0)); |
|
zw_ALU4(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0'; |
zw_ALU3(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0'; |
zw_ALU6(2 downto 0) <= (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0'; |
zw_ALU5(2 downto 0) <= (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0'; |
|
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; |
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned |
('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4)); |
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; |
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4)); |
|
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; |
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned |
('0' & d_i(3 downto 0)) + reg_F(0); |
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; |
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0); |
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s586 => |
when G10_e2 => |
if (rdy_i = '1' and |
reg_F(3) = '0') then |
d_regs_in_o <= zw_ALU(7 downto 0); |
4816,23 → 4652,21
reg_F(3) = '1') then |
d_regs_in_o <= zw_ALU(7 downto 0); |
load_regs_o <= '1'; |
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU4(7 downto 5)); |
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU3(7 downto 5)); |
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0)); |
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0)); |
|
zw_ALU4(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0'; |
zw_ALU3(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0'; |
zw_ALU6(2 downto 0) <= (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0'; |
zw_ALU5(2 downto 0) <= (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0'; |
|
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; |
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned |
('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4)); |
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; |
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4)); |
|
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; |
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned |
('0' & d_i(3 downto 0)) + reg_F(0); |
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; |
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0); |
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s587 => |
when G10_6 => |
if (rdy_i = '1') then |
ch_a_o <= d_i; |
ch_b_o <= X"01"; |
4839,14 → 4673,14
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s178 => |
when G17_1 => |
if (rdy_i = '1' and |
(zw_REG_OP = X"85" OR |
zw_REG_OP = X"86" OR |
zw_REG_OP = X"64" OR |
zw_REG_OP = X"84")) then |
sig_RWn <= '0'; |
sig_RD <= '0'; |
|
|
sig_WR <= '1'; |
sig_D_OUT <= d_regs_out_i; |
ld_o <= "11"; |
4894,7 → 4728,7
ch_a_o <= d_i; |
ch_b_o <= X"01"; |
end if; |
when s194 => |
when G17_4 => |
if (rdy_i = '1') then |
ch_a_o <= d_i; |
ch_b_o <= "0000000" & zw_b2(0); |
4901,41 → 4735,31
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s195 => |
when G17_6 => |
if (rdy_i = '1') then |
ch_a_o <= d_i; |
ch_b_o <= q_y_i; |
end if; |
when s196 => |
when G17_3 => |
if (rdy_i = '1') then |
sig_RWn <= '0'; |
sig_RD <= '0'; |
sig_WR <= '1'; |
sig_D_OUT <= d_regs_out_i; |
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s197 => |
sig_SYNC <= '1'; |
fetch_o <= '1'; |
when s198 => |
when G17_2 => |
if (rdy_i = '1') then |
sig_RWn <= '0'; |
sig_RD <= '0'; |
sig_WR <= '1'; |
sig_D_OUT <= d_regs_out_i; |
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s200 => |
sig_SYNC <= '1'; |
fetch_o <= '1'; |
when s205 => |
when G17_9 => |
if (rdy_i = '1') then |
ch_a_o <= zw_b1; |
ch_b_o <= X"01"; |
end if; |
when s206 => |
when G17_7 => |
if (rdy_i = '1') then |
ch_a_o <= d_i; |
ch_b_o <= "0000000" & zw_b2(0); |
4942,25 → 4766,18
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s207 => |
sig_SYNC <= '1'; |
fetch_o <= '1'; |
when s208 => |
sig_RWn <= '0'; |
sig_RD <= '0'; |
when G17_5 => |
sig_WR <= '1'; |
sig_D_OUT <= d_regs_out_i; |
when s209 => |
sig_RWn <= '0'; |
sig_RD <= '0'; |
when G17_10 => |
sig_WR <= '1'; |
sig_D_OUT <= d_regs_out_i; |
ld_o <= "11"; |
ld_pc_o <= '1'; |
when s213 => |
when G17_e => |
sig_SYNC <= '1'; |
fetch_o <= '1'; |
when s513 => |
when G16_1 => |
if (rdy_i = '1' and |
zw_REG_OP = X"E5") then |
ld_o <= "11"; |
5010,23 → 4827,17
ld_pc_o <= '1'; |
d_regs_in_o <= zw_ALU(7 downto 0); |
load_regs_o <= '1'; |
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + |
unsigned ((zw_ALU6(8 downto 5))); |
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + |
unsigned ((zw_ALU5(8 downto 5))); |
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6); |
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5); |
|
zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & |
(zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0'; |
zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & |
(zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ; |
zw_ALU6 <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0'; |
zw_ALU5 <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ; |
|
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; |
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned |
('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4); |
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; |
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4); |
|
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; |
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned |
('0' & NOT (d_i(3 downto 0))) + reg_F(0); |
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; |
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0); |
sig_SYNC <= '1'; |
fetch_o <= '1'; |
elsif (rdy_i = '1' and |
5034,12 → 4845,12
ch_a_o <= d_i; |
ch_b_o <= X"01"; |
end if; |
when s588 => |
when G16_3 => |
if (rdy_i = '1') then |
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s589 => |
when G16_4 => |
if (rdy_i = '1') then |
ch_a_o <= d_i; |
ch_b_o <= X"01"; |
5046,17 → 4857,17
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s590 => |
when G16_5 => |
if (rdy_i = '1') then |
ch_a_o <= d_i; |
ch_b_o <= q_y_i; |
end if; |
when s591 => |
when G16_2 => |
if (rdy_i = '1') then |
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s593 => |
when G16_6 => |
if (rdy_i = '1') then |
ch_a_o <= d_i; |
ch_b_o <= X"01"; |
5063,12 → 4874,12
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s594 => |
when G16_e3 => |
if (rdy_i = '1') then |
ch_a_o <= zw_b1; |
ch_b_o <= X"01"; |
end if; |
when s595 => |
when G16_e1 => |
if (rdy_i = '1' AND |
zw_b2(0) = '0' and |
reg_F(3) = '0') then |
5082,27 → 4893,21
reg_F(3) = '1') then |
d_regs_in_o <= zw_ALU(7 downto 0); |
load_regs_o <= '1'; |
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + |
unsigned ((zw_ALU6(8 downto 5))); |
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + |
unsigned ((zw_ALU5(8 downto 5))); |
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6); |
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5); |
|
zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & |
(zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0'; |
zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & |
(zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ; |
zw_ALU6 <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0'; |
zw_ALU5 <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ; |
|
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; |
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned |
('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4); |
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; |
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4); |
|
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; |
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned |
('0' & NOT (d_i(3 downto 0))) + reg_F(0); |
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; |
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0); |
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s596 => |
when G16_e2 => |
if (rdy_i = '1' and |
reg_F(3) = '0') then |
d_regs_in_o <= zw_ALU(7 downto 0); |
5114,27 → 4919,21
reg_F(3) = '1') then |
d_regs_in_o <= zw_ALU(7 downto 0); |
load_regs_o <= '1'; |
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + |
unsigned ((zw_ALU6(8 downto 5))); |
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + |
unsigned ((zw_ALU5(8 downto 5))); |
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6); |
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5); |
|
zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & |
(zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0'; |
zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & |
(zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ; |
zw_ALU6 <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0'; |
zw_ALU5 <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ; |
|
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; |
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned |
('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4); |
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; |
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4); |
|
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; |
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned |
('0' & NOT (d_i(3 downto 0))) + reg_F(0); |
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; |
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0); |
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s405 => |
when G11_1 => |
if (rdy_i = '1' and |
(zw_REG_OP = X"1E" or |
zw_REG_OP = X"7E" or |
5171,12 → 4970,12
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s408 => |
when G11_5 => |
if (rdy_i = '1') then |
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s410 => |
when G11_6 => |
if (rdy_i = '1') then |
ch_a_o <= d_i; |
ch_b_o <= "0000000" & zw_b2(0); |
5183,12 → 4982,12
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s411 => |
when G11_2 => |
if (rdy_i = '1') then |
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s417 => |
when G11_4 => |
if (rdy_i = '1' and |
(zw_REG_OP = X"06" or |
zw_REG_OP = X"16" or |
5195,8 → 4994,6
zw_REG_OP = X"0E" or |
zw_REG_OP = X"1E")) then |
sig_D_OUT <= d_i(6 downto 0) & '0'; |
sig_RWn <= '0'; |
sig_RD <= '0'; |
sig_WR <= '1'; |
elsif (rdy_i = '1' and |
(zw_REG_OP = X"46" or |
5204,8 → 5001,6
zw_REG_OP = X"4E" or |
zw_REG_OP = X"5E")) then |
sig_D_OUT <= '0' & d_i(7 downto 1); |
sig_RWn <= '0'; |
sig_RD <= '0'; |
sig_WR <= '1'; |
elsif (rdy_i = '1' and |
(zw_REG_OP = X"26" or |
5213,8 → 5008,6
zw_REG_OP = X"2E" or |
zw_REG_OP = X"3E")) then |
sig_D_OUT <= d_i(6 downto 0) & reg_F(0); |
sig_RWn <= '0'; |
sig_RD <= '0'; |
sig_WR <= '1'; |
elsif (rdy_i = '1' and |
(zw_REG_OP = X"66" or |
5222,41 → 5015,31
zw_REG_OP = X"6E" or |
zw_REG_OP = X"7E")) then |
sig_D_OUT <= reg_F(0) & d_i(7 downto 1); |
sig_RWn <= '0'; |
sig_RD <= '0'; |
sig_WR <= '1'; |
elsif (rdy_i = '1' and |
zw_REG_OP (7) = '0' and |
zw_REG_OP (3 downto 0) = X"7") then |
sig_D_OUT <= d_i and NOT (d_alu_i); |
sig_D_OUT <= d_i and NOT (alu_dec_val_i); |
ch_a_o <= "00000" & zw_REG_OP (6 downto 4) ; |
sig_RWn <= '0'; |
sig_RD <= '0'; |
sig_WR <= '1'; |
elsif (rdy_i = '1' and |
zw_REG_OP (7) = '1' and |
zw_REG_OP (3 downto 0) = X"7") then |
sig_D_OUT <= d_i or d_alu_i; |
sig_D_OUT <= d_i or alu_dec_val_i; |
ch_a_o <= "00000" & zw_REG_OP (6 downto 4) ; |
sig_RWn <= '0'; |
sig_RD <= '0'; |
sig_WR <= '1'; |
elsif (rdy_i = '1' and |
(zw_REG_OP = X"14" or |
zw_REG_OP = X"1C")) then |
sig_D_OUT <= d_i and NOT (q_a_i); |
sig_RWn <= '0'; |
sig_RD <= '0'; |
sig_WR <= '1'; |
elsif (rdy_i = '1' and |
(zw_REG_OP = X"04" or |
zw_REG_OP = X"0C")) then |
sig_D_OUT <= d_i or q_a_i; |
sig_RWn <= '0'; |
sig_RD <= '0'; |
sig_WR <= '1'; |
end if; |
when s419 => |
when G11_e => |
if (zw_REG_OP (3 downto 0) = X"7") then |
sig_SYNC <= '1'; |
fetch_o <= '1'; |
5274,7 → 5057,7
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s420 => |
when G31_1 => |
if (rdy_i = '1') then |
ch_a_o <= q_a_i (6 downto 0) & '0'; |
ch_b_o <= X"00"; |
5283,7 → 5066,7
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s598 => |
when G34_1 => |
if (rdy_i = '1') then |
ch_a_o <= reg_F(0) & q_a_i (7 downto 1); |
ch_b_o <= X"00"; |
5292,7 → 5075,7
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s599 => |
when G32_1 => |
if (rdy_i = '1') then |
ch_a_o <= '0' & q_a_i (7 downto 1); |
ch_b_o <= X"00"; |
5301,7 → 5084,7
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s600 => |
when G33_1 => |
if (rdy_i = '1') then |
ch_a_o <= q_a_i (6 downto 0) & reg_F(0); |
ch_b_o <= X"00"; |
5310,7 → 5093,7
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s268 => |
when G12_1 => |
if (rdy_i = '1' and ( |
(reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or |
(reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or |
5343,7 → 5126,7
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s305 => |
when G12_e1 => |
if (rdy_i = '1' and |
zw_b3 = adr_nxt_pc_i (15 downto 8)) then |
offset_o <= (zw_b2(7) & zw_b2(7) & |
5361,12 → 5144,12
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s306 => |
when G12_e2 => |
if (rdy_i = '1') then |
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s269 => |
when G12_3 => |
if (rdy_i = '1' and ( |
(d_i(0) = '1' and zw_REG_OP = X"8F") or |
(d_i(1) = '1' and zw_REG_OP = X"9F") or |
5388,18 → 5171,18
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s303 => |
when G12_4 => |
if (rdy_i = '1') then |
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s275 => |
when G20_2 => |
if (rdy_i = '1') then |
adr_o <= d_i & zw_b1; |
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s309 => |
when G20_e => |
if (rdy_i = '1') then |
adr_o <= d_i & zw_b1; |
ld_o <= "11"; |
5407,7 → 5190,7
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s274 => |
when G20_3 => |
if (rdy_i = '1') then |
adr_o <= d_i & zw_b1; |
offset_o <= (X"00" & q_x_i); |
5414,27 → 5197,23
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s402 => |
when G21_1 => |
if (rdy_i = '1') then |
ld_o <= "11"; |
ld_sp_o <= '1'; |
ld_pc_o <= '1'; |
end if; |
when s421 => |
when G21_2 => |
if (rdy_i = '1') then |
sig_RWn <= '0'; |
sig_RD <= '0'; |
sig_WR <= '1'; |
sig_D_OUT <= adr_pc_i (15 downto 8); |
end if; |
when s422 => |
when G21_3 => |
ld_o <= "11"; |
ld_sp_o <= '1'; |
sig_RWn <= '0'; |
sig_RD <= '0'; |
sig_WR <= '1'; |
sig_D_OUT <= adr_pc_i (7 downto 0); |
when s424 => |
when G21_e => |
if (rdy_i = '1') then |
adr_o <= d_i & zw_b1; |
ld_o <= "11"; |
5442,12 → 5221,12
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s362 => |
when G13_3 => |
if (rdy_i = '1') then |
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s221 => |
when G13_1 => |
if (rdy_i = '1' and |
zw_REG_OP = X"34") then |
ch_a_o <= d_i; |
5475,7 → 5254,7
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s232 => |
when G13_4 => |
if (rdy_i = '1') then |
ch_a_o <= d_i; |
ch_b_o <= "0000000" & zw_b2(0); |
5482,12 → 5261,12
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s233 => |
when G13_2 => |
if (rdy_i = '1') then |
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s234 => |
when G13_e1 => |
if (rdy_i = '1') then |
ch_a_o <= q_a_i AND d_i; |
ch_b_o <= X"00"; |
5494,7 → 5273,7
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s235 => |
when G13_e2 => |
if (rdy_i = '1' AND |
zw_b2(0) = '0') then |
ch_a_o <= q_a_i AND d_i; |
5502,30 → 5281,24
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s538 => |
when G18_1 => |
if (rdy_i = '1') then |
ld_o <= "11"; |
ld_sp_o <= '1'; |
sig_RWn <= '0'; |
sig_RD <= '0'; |
sig_WR <= '1'; |
sig_D_OUT <= adr_nxt_pc_i (15 downto 8); |
end if; |
when s539 => |
when G18_2 => |
ld_o <= "11"; |
ld_sp_o <= '1'; |
sig_RWn <= '0'; |
sig_RD <= '0'; |
sig_WR <= '1'; |
sig_D_OUT <= adr_nxt_pc_i (7 downto 0); |
when s540 => |
when G18_3 => |
ld_o <= "11"; |
ld_sp_o <= '1'; |
sig_RWn <= '0'; |
sig_RD <= '0'; |
sig_WR <= '1'; |
sig_D_OUT <= reg_F OR X"10"; |
when s542 => |
when G18_e => |
if (rdy_i = '1') then |
adr_o <= d_i & zw_b1; |
ld_o <= "11"; |
5533,22 → 5306,22
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s425 => |
when G26_1 => |
if (rdy_i = '1') then |
ld_o <= "11"; |
ld_sp_o <= '1'; |
end if; |
when s426 => |
when G26_2 => |
if (rdy_i = '1') then |
ld_o <= "11"; |
ld_sp_o <= '1'; |
end if; |
when s427 => |
when G26_3 => |
if (rdy_i = '1') then |
ld_o <= "11"; |
ld_sp_o <= '1'; |
end if; |
when s429 => |
when G26_e => |
if (rdy_i = '1') then |
adr_o <= d_i & zw_b1; |
ld_o <= "11"; |
5556,28 → 5329,28
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s430 => |
when G27_1 => |
if (rdy_i = '1') then |
ld_o <= "11"; |
ld_sp_o <= '1'; |
end if; |
when s431 => |
when G27_2 => |
if (rdy_i = '1') then |
ld_o <= "11"; |
ld_sp_o <= '1'; |
end if; |
when s433 => |
when G27_4 => |
if (rdy_i = '1') then |
adr_o <= d_i & zw_b1; |
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s434 => |
when G27_e => |
if (rdy_i = '1') then |
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s236 => |
when G14_1 => |
if (rdy_i = '1' and |
(zw_REG_OP = X"C6" OR |
zw_REG_OP = X"E6")) then |
5601,12 → 5374,12
ch_a_o <= d_i; |
ch_b_o <= q_x_i; |
end if; |
when s245 => |
when G14_5 => |
if (rdy_i = '1') then |
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s246 => |
when G14_6 => |
if (rdy_i = '1') then |
ch_a_o <= d_i; |
ch_b_o <= "0000000" & zw_b2(0); |
5613,58 → 5386,52
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s248 => |
when G14_2 => |
if (rdy_i = '1') then |
ld_o <= "11"; |
ld_pc_o <= '1'; |
end if; |
when s346 => |
when G14_3 => |
if (rdy_i = '1') then |
ch_a_o <= d_i; |
ch_b_o <= zw_b4; |
end if; |
when s252 => |
when G14_4 => |
if (rdy_i = '1') then |
sig_RWn <= '0'; |
sig_RD <= '0'; |
sig_WR <= '1'; |
sig_D_OUT <= zw_b1; |
end if; |
when s253 => |
when G14_e => |
ch_a_o <= zw_b1; |
ch_b_o <= X"00"; |
sig_SYNC <= '1'; |
fetch_o <= '1'; |
when s435 => |
when G22_1 => |
if (rdy_i = '1') then |
sig_RWn <= '0'; |
sig_RD <= '0'; |
sig_WR <= '1'; |
sig_D_OUT <= d_regs_out_i; |
ld_o <= "11"; |
ld_sp_o <= '1'; |
end if; |
when s436 => |
when G22_e => |
sig_SYNC <= '1'; |
fetch_o <= '1'; |
when s437 => |
when G23_1 => |
if (rdy_i = '1') then |
sig_RWn <= '0'; |
sig_RD <= '0'; |
sig_WR <= '1'; |
sig_D_OUT <= reg_F; |
ld_o <= "11"; |
ld_sp_o <= '1'; |
end if; |
when s438 => |
when G23_e => |
sig_SYNC <= '1'; |
fetch_o <= '1'; |
when s439 => |
when G24_1 => |
if (rdy_i = '1') then |
ld_o <= "11"; |
ld_sp_o <= '1'; |
end if; |
when s441 => |
when G24_e => |
if (rdy_i = '1') then |
d_regs_in_o <= d_i; |
load_regs_o <= '1'; |
5673,25 → 5440,16
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s442 => |
when G25_1 => |
if (rdy_i = '1') then |
ld_o <= "11"; |
ld_sp_o <= '1'; |
end if; |
when s444 => |
when G25_e => |
if (rdy_i = '1') then |
sig_SYNC <= '1'; |
fetch_o <= '1'; |
end if; |
when s0 => |
if (rdy_i = '1') then |
sig_RWn <= '0'; |
sig_RD <= '0'; |
sig_WR <= '1'; |
sig_D_OUT <= d_alu_i; |
ch_a_o <= d_i; |
ch_b_o <= zw_b4; |
end if; |
when others => |
null; |
end case; |
5702,6 → 5460,5
d_o <= d_o_cld; |
rd_o <= rd_o_cld; |
sync_o <= sync_o_cld; |
wr_n_o <= wr_n_o_cld; |
wr_o <= wr_o_cld; |
end fsm; |
/trunk/rtl/vhdl/r65c02_tc.vhd
2,7 → 2,7
-- |
-- Created: |
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) |
-- at - 20:48:26 04.01.2009 |
-- at - 15:22:46 25.02.2009 |
-- |
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) |
-- |
23,7 → 23,6
d_o : out std_logic_vector (7 downto 0); |
rd_o : out std_logic; |
sync_o : out std_logic; |
wr_n_o : out std_logic; |
wr_o : out std_logic |
); |
|
33,7 → 32,7
|
-- Jens-D. Gutschmidt Project: R65C02_TC |
-- scantara2003@yahoo.de |
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG |
-- COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG |
-- |
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or any later version. |
49,13 → 48,13
-- <<-- more -->> |
-- Title: Top Level |
-- Path: R65C02_TC/R65C02_TC/struct |
-- Edited: by eda on 04 Jan 2009 |
-- Edited: by eda on 10 Feb 2009 |
-- |
-- VHDL Architecture R65C02_TC.R65C02_TC.struct |
-- |
-- Created: |
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) |
-- at - 20:48:26 04.01.2009 |
-- at - 15:22:46 25.02.2009 |
-- |
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) |
-- |
86,7 → 85,6
d_o : out std_logic_vector (7 downto 0); |
rd_o : out std_logic ; |
sync_o : out std_logic ; |
wr_n_o : out std_logic ; |
wr_o : out std_logic |
); |
end component; |
113,7 → 111,6
d_o => d_o, |
rd_o => rd_o, |
sync_o => sync_o, |
wr_n_o => wr_n_o, |
wr_o => wr_o |
); |
|
/trunk/rtl/vhdl/core.vhd
2,7 → 2,7
-- |
-- Created: |
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) |
-- at - 20:48:25 04.01.2009 |
-- at - 15:22:45 25.02.2009 |
-- |
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) |
-- |
23,7 → 23,6
d_o : out std_logic_vector (7 downto 0); |
rd_o : out std_logic; |
sync_o : out std_logic; |
wr_n_o : out std_logic; |
wr_o : out std_logic |
); |
|
33,7 → 32,7
|
-- Jens-D. Gutschmidt Project: R65C02_TC |
-- scantara2003@yahoo.de |
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG |
-- COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG |
-- |
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version |
-- 3 of the License, or any later version. |
49,13 → 48,13
-- <<-- more -->> |
-- Title: Core |
-- Path: R65C02_TC/Core/struct |
-- Edited: by eda on 04 Jan 2009 |
-- Edited: by eda on 23 Feb 2009 |
-- |
-- VHDL Architecture R65C02_TC.Core.struct |
-- |
-- Created: |
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) |
-- at - 20:48:25 04.01.2009 |
-- at - 15:22:46 25.02.2009 |
-- |
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) |
-- |
70,38 → 69,38
-- Architecture declarations |
|
-- Internal signal declarations |
signal adr_nxt_pc_o_i : std_logic_vector(15 downto 0); |
signal adr_o_i : std_logic_vector(15 downto 0); |
signal adr_pc_o_i : std_logic_vector(15 downto 0); |
signal adr_sp_o_i : std_logic_vector(15 downto 0); |
signal ch_a_o_i : std_logic_vector(7 downto 0); |
signal ch_b_o_i : std_logic_vector(7 downto 0); |
signal d_alu_n_o_i : std_logic; |
signal d_alu_o_i : std_logic_vector(7 downto 0); |
signal d_alu_or_o_i : std_logic; |
signal d_regs_in_o_i : std_logic_vector(7 downto 0); |
signal d_regs_out_o_i : std_logic_vector(7 downto 0); |
signal fetch_o_i : std_logic; |
signal ld_o_i : std_logic_vector(1 downto 0); |
signal ld_pc_o_i : std_logic; |
signal ld_sp_o_i : std_logic; |
signal load_regs_o_i : std_logic; |
signal nmi_o_i : std_logic; |
signal offset_o_i : std_logic_vector(15 downto 0); |
signal q_a_o_i : std_logic_vector(7 downto 0); |
signal q_x_o_i : std_logic_vector(7 downto 0); |
signal q_y_o_i : std_logic_vector(7 downto 0); |
signal reg_0flag_o_i : std_logic; |
signal reg_1flag_o_i : std_logic; |
signal reg_7flag_o_i : std_logic; |
signal sel_pc_as_o_i : std_logic; |
signal sel_pc_in_o_i : std_logic; |
signal sel_pc_val_o_i : std_logic_vector(1 downto 0); |
signal sel_rb_in_o_i : std_logic_vector(1 downto 0); |
signal sel_rb_out_o_i : std_logic_vector(1 downto 0); |
signal sel_reg_o_i : std_logic_vector(1 downto 0); |
signal sel_sp_as_o_i : std_logic; |
signal sel_sp_in_o_i : std_logic; |
signal adr_nxt_pc_o_i : std_logic_vector(15 downto 0); |
signal adr_o_i : std_logic_vector(15 downto 0); |
signal adr_pc_o_i : std_logic_vector(15 downto 0); |
signal adr_sp_o_i : std_logic_vector(15 downto 0); |
signal alu_dec_val_o_i : std_logic_vector(7 downto 0); |
signal ch_a_o_i : std_logic_vector(7 downto 0); |
signal ch_b_o_i : std_logic_vector(7 downto 0); |
signal d_alu_n_o_i : std_logic; |
signal d_alu_o_i : std_logic_vector(7 downto 0); |
signal d_alu_or_o_i : std_logic; |
signal d_regs_in_o_i : std_logic_vector(7 downto 0); |
signal d_regs_out_o_i : std_logic_vector(7 downto 0); |
signal fetch_o_i : std_logic; |
signal ld_o_i : std_logic_vector(1 downto 0); |
signal ld_pc_o_i : std_logic; |
signal ld_sp_o_i : std_logic; |
signal load_regs_o_i : std_logic; |
signal nmi_o_i : std_logic; |
signal offset_o_i : std_logic_vector(15 downto 0); |
signal q_a_o_i : std_logic_vector(7 downto 0); |
signal q_x_o_i : std_logic_vector(7 downto 0); |
signal q_y_o_i : std_logic_vector(7 downto 0); |
signal reg_0flag_o_i : std_logic; |
signal reg_1flag_o_i : std_logic; |
signal reg_7flag_o_i : std_logic; |
signal sel_pc_in_o_i : std_logic; |
signal sel_pc_val_o_i : std_logic_vector(1 downto 0); |
signal sel_rb_in_o_i : std_logic_vector(1 downto 0); |
signal sel_rb_out_o_i : std_logic_vector(1 downto 0); |
signal sel_reg_o_i : std_logic_vector(1 downto 0); |
signal sel_sp_as_o_i : std_logic; |
signal sel_sp_in_o_i : std_logic; |
|
|
-- ModuleWare signal declarations(v1.9) for instance 'U_11' of 'add' |
112,48 → 111,47
-- Component Declarations |
component FSM_Execution_Unit |
port ( |
adr_nxt_pc_i : in std_logic_vector (15 downto 0); |
adr_pc_i : in std_logic_vector (15 downto 0); |
adr_sp_i : in std_logic_vector (15 downto 0); |
clk_clk_i : in std_logic ; |
d_alu_i : in std_logic_vector ( 7 downto 0 ); |
d_i : in std_logic_vector ( 7 downto 0 ); |
d_regs_out_i : in std_logic_vector ( 7 downto 0 ); |
irq_n_i : in std_logic ; |
nmi_i : in std_logic ; |
q_a_i : in std_logic_vector ( 7 downto 0 ); |
q_x_i : in std_logic_vector ( 7 downto 0 ); |
q_y_i : in std_logic_vector ( 7 downto 0 ); |
rdy_i : in std_logic ; |
reg_0flag_i : in std_logic ; |
reg_1flag_i : in std_logic ; |
reg_7flag_i : in std_logic ; |
rst_rst_n_i : in std_logic ; |
so_n_i : in std_logic ; |
a_o : out std_logic_vector (15 downto 0); |
adr_o : out std_logic_vector (15 downto 0); |
ch_a_o : out std_logic_vector ( 7 downto 0 ); |
ch_b_o : out std_logic_vector ( 7 downto 0 ); |
d_o : out std_logic_vector ( 7 downto 0 ); |
d_regs_in_o : out std_logic_vector ( 7 downto 0 ); |
fetch_o : out std_logic ; |
ld_o : out std_logic_vector ( 1 downto 0 ); |
ld_pc_o : out std_logic ; |
ld_sp_o : out std_logic ; |
load_regs_o : out std_logic ; |
offset_o : out std_logic_vector ( 15 downto 0 ); |
rd_o : out std_logic ; |
sel_pc_as_o : out std_logic ; |
sel_pc_in_o : out std_logic ; |
sel_pc_val_o : out std_logic_vector ( 1 downto 0 ); |
sel_rb_in_o : out std_logic_vector ( 1 downto 0 ); |
sel_rb_out_o : out std_logic_vector ( 1 downto 0 ); |
sel_reg_o : out std_logic_vector ( 1 downto 0 ); |
sel_sp_as_o : out std_logic ; |
sel_sp_in_o : out std_logic ; |
sync_o : out std_logic ; |
wr_n_o : out std_logic ; |
wr_o : out std_logic |
adr_nxt_pc_i : in std_logic_vector (15 downto 0); |
adr_pc_i : in std_logic_vector (15 downto 0); |
adr_sp_i : in std_logic_vector (15 downto 0); |
alu_dec_val_i : in std_logic_vector ( 7 downto 0 ); |
clk_clk_i : in std_logic ; |
d_alu_i : in std_logic_vector ( 7 downto 0 ); |
d_i : in std_logic_vector ( 7 downto 0 ); |
d_regs_out_i : in std_logic_vector ( 7 downto 0 ); |
irq_n_i : in std_logic ; |
nmi_i : in std_logic ; |
q_a_i : in std_logic_vector ( 7 downto 0 ); |
q_x_i : in std_logic_vector ( 7 downto 0 ); |
q_y_i : in std_logic_vector ( 7 downto 0 ); |
rdy_i : in std_logic ; |
reg_0flag_i : in std_logic ; |
reg_1flag_i : in std_logic ; |
reg_7flag_i : in std_logic ; |
rst_rst_n_i : in std_logic ; |
so_n_i : in std_logic ; |
a_o : out std_logic_vector (15 downto 0); |
adr_o : out std_logic_vector (15 downto 0); |
ch_a_o : out std_logic_vector ( 7 downto 0 ); |
ch_b_o : out std_logic_vector ( 7 downto 0 ); |
d_o : out std_logic_vector ( 7 downto 0 ); |
d_regs_in_o : out std_logic_vector ( 7 downto 0 ); |
fetch_o : out std_logic ; |
ld_o : out std_logic_vector ( 1 downto 0 ); |
ld_pc_o : out std_logic ; |
ld_sp_o : out std_logic ; |
load_regs_o : out std_logic ; |
offset_o : out std_logic_vector ( 15 downto 0 ); |
rd_o : out std_logic ; |
sel_pc_in_o : out std_logic ; |
sel_pc_val_o : out std_logic_vector ( 1 downto 0 ); |
sel_rb_in_o : out std_logic_vector ( 1 downto 0 ); |
sel_rb_out_o : out std_logic_vector ( 1 downto 0 ); |
sel_reg_o : out std_logic_vector ( 1 downto 0 ); |
sel_sp_as_o : out std_logic ; |
sel_sp_in_o : out std_logic ; |
sync_o : out std_logic ; |
wr_o : out std_logic |
); |
end component; |
component FSM_NMI |
188,7 → 186,6
ld_pc_i : in std_logic ; |
offset_i : in std_logic_vector (15 downto 0); |
rst_rst_n_i : in std_logic ; |
sel_pc_as_i : in std_logic ; |
sel_pc_in_i : in std_logic ; |
sel_pc_val_i : in std_logic_vector (1 downto 0); |
adr_nxt_pc_o : out std_logic_vector (15 downto 0); |
232,6 → 229,23
d_alu_o_i <= conv_std_logic_vector(mw_U_11sum(7 downto 0),8); |
reg_0flag_o_i <= mw_U_11sum(8) ; |
|
-- ModuleWare code(v1.9) for instance 'U_5' of 'decoder1' |
u_5combo_proc: process (d_alu_o_i(2 DOWNTO 0)) |
begin |
alu_dec_val_o_i <= (others => '0'); |
case d_alu_o_i(2 DOWNTO 0) is |
when "000" => alu_dec_val_o_i(0) <= '1'; |
when "001" => alu_dec_val_o_i(1) <= '1'; |
when "010" => alu_dec_val_o_i(2) <= '1'; |
when "011" => alu_dec_val_o_i(3) <= '1'; |
when "100" => alu_dec_val_o_i(4) <= '1'; |
when "101" => alu_dec_val_o_i(5) <= '1'; |
when "110" => alu_dec_val_o_i(6) <= '1'; |
when "111" => alu_dec_val_o_i(7) <= '1'; |
when others => alu_dec_val_o_i <= (others => '0'); |
end case; |
end process u_5combo_proc; |
|
-- ModuleWare code(v1.9) for instance 'U_8' of 'inv' |
reg_1flag_o_i <= not(d_alu_or_o_i); |
|
247,48 → 261,47
-- Instance port mappings. |
U_4 : FSM_Execution_Unit |
port map ( |
adr_nxt_pc_i => adr_nxt_pc_o_i, |
adr_pc_i => adr_pc_o_i, |
adr_sp_i => adr_sp_o_i, |
clk_clk_i => clk_clk_i, |
d_alu_i => d_alu_o_i, |
d_i => d_i, |
d_regs_out_i => d_regs_out_o_i, |
irq_n_i => irq_n_i, |
nmi_i => nmi_o_i, |
q_a_i => q_a_o_i, |
q_x_i => q_x_o_i, |
q_y_i => q_y_o_i, |
rdy_i => rdy_i, |
reg_0flag_i => reg_0flag_o_i, |
reg_1flag_i => reg_1flag_o_i, |
reg_7flag_i => reg_7flag_o_i, |
rst_rst_n_i => rst_rst_n_i, |
so_n_i => so_n_i, |
a_o => a_o, |
adr_o => adr_o_i, |
ch_a_o => ch_a_o_i, |
ch_b_o => ch_b_o_i, |
d_o => d_o, |
d_regs_in_o => d_regs_in_o_i, |
fetch_o => fetch_o_i, |
ld_o => ld_o_i, |
ld_pc_o => ld_pc_o_i, |
ld_sp_o => ld_sp_o_i, |
load_regs_o => load_regs_o_i, |
offset_o => offset_o_i, |
rd_o => rd_o, |
sel_pc_as_o => sel_pc_as_o_i, |
sel_pc_in_o => sel_pc_in_o_i, |
sel_pc_val_o => sel_pc_val_o_i, |
sel_rb_in_o => sel_rb_in_o_i, |
sel_rb_out_o => sel_rb_out_o_i, |
sel_reg_o => sel_reg_o_i, |
sel_sp_as_o => sel_sp_as_o_i, |
sel_sp_in_o => sel_sp_in_o_i, |
sync_o => sync_o, |
wr_n_o => wr_n_o, |
wr_o => wr_o |
adr_nxt_pc_i => adr_nxt_pc_o_i, |
adr_pc_i => adr_pc_o_i, |
adr_sp_i => adr_sp_o_i, |
alu_dec_val_i => alu_dec_val_o_i, |
clk_clk_i => clk_clk_i, |
d_alu_i => d_alu_o_i, |
d_i => d_i, |
d_regs_out_i => d_regs_out_o_i, |
irq_n_i => irq_n_i, |
nmi_i => nmi_o_i, |
q_a_i => q_a_o_i, |
q_x_i => q_x_o_i, |
q_y_i => q_y_o_i, |
rdy_i => rdy_i, |
reg_0flag_i => reg_0flag_o_i, |
reg_1flag_i => reg_1flag_o_i, |
reg_7flag_i => reg_7flag_o_i, |
rst_rst_n_i => rst_rst_n_i, |
so_n_i => so_n_i, |
a_o => a_o, |
adr_o => adr_o_i, |
ch_a_o => ch_a_o_i, |
ch_b_o => ch_b_o_i, |
d_o => d_o, |
d_regs_in_o => d_regs_in_o_i, |
fetch_o => fetch_o_i, |
ld_o => ld_o_i, |
ld_pc_o => ld_pc_o_i, |
ld_sp_o => ld_sp_o_i, |
load_regs_o => load_regs_o_i, |
offset_o => offset_o_i, |
rd_o => rd_o, |
sel_pc_in_o => sel_pc_in_o_i, |
sel_pc_val_o => sel_pc_val_o_i, |
sel_rb_in_o => sel_rb_in_o_i, |
sel_rb_out_o => sel_rb_out_o_i, |
sel_reg_o => sel_reg_o_i, |
sel_sp_as_o => sel_sp_as_o_i, |
sel_sp_in_o => sel_sp_in_o_i, |
sync_o => sync_o, |
wr_o => wr_o |
); |
U_3 : FSM_NMI |
port map ( |
320,7 → 333,6
ld_pc_i => ld_pc_o_i, |
offset_i => offset_o_i, |
rst_rst_n_i => rst_rst_n_i, |
sel_pc_as_i => sel_pc_as_o_i, |
sel_pc_in_i => sel_pc_in_o_i, |
sel_pc_val_i => sel_pc_val_o_i, |
adr_nxt_pc_o => adr_nxt_pc_o_i, |
/trunk/rtl/vhdl/fsm_nmi.vhd
1,8 → 1,8
-- VHDL Entity R65C02_TC.FSM_NMI.symbol |
-- |
-- Created: |
-- by - eda.UNKNOWN (TEST) |
-- at - 22:45:35 03.01.2009 |
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) |
-- at - 15:22:29 25.02.2009 |
-- |
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) |
-- |
10,24 → 10,24
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
ENTITY FSM_NMI IS |
PORT( |
clk_clk_i : IN std_logic; |
fetch_i : IN std_logic; |
nmi_n_i : IN std_logic; |
rst_rst_n_i : IN std_logic; |
nmi_o : OUT std_logic |
entity FSM_NMI is |
port( |
clk_clk_i : in std_logic; |
fetch_i : in std_logic; |
nmi_n_i : in std_logic; |
rst_rst_n_i : in std_logic; |
nmi_o : out std_logic |
); |
|
-- Declarations |
|
END FSM_NMI ; |
end FSM_NMI ; |
|
-- Jens-D. Gutschmidt Project: R65C02_TC |
|
-- scantara2003@yahoo.de |
|
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG |
-- COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG |
|
-- |
|
51,15 → 51,7
|
-- |
|
-- $Log: not supported by cvs2svn $ |
-- Revision 1.3 2009/01/04 10:20:52 eda |
-- Changes for cosmetic issues only |
-- |
-- Revision 1.2 2009/01/04 09:23:15 eda |
-- - Delete unused nets and blocks (same as R6502_TC) |
-- - Rename blocks |
-- - Re-arrage FSM symbols in block FSM_Execution_Unit |
-- |
-- $Log: not supported by cvs2svn $ |
|
-- <<-- more -->> |
|
67,14 → 59,14
|
-- Path: R65C02_TC/FSM_NMI/fsm |
|
-- Edited: by eda on 03 Jan 2009 |
-- Edited: by eda on 10 Feb 2009 |
|
-- |
-- VHDL Architecture R65C02_TC.FSM_NMI.fsm |
-- |
-- Created: |
-- by - eda.UNKNOWN (TEST) |
-- at - 22:45:35 03.01.2009 |
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) |
-- at - 15:22:30 25.02.2009 |
-- |
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) |
-- |
82,9 → 74,9
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
ARCHITECTURE fsm OF FSM_NMI IS |
architecture fsm of FSM_NMI is |
|
TYPE STATE_TYPE IS ( |
type state_type is ( |
idle, |
idle1, |
idle2, |
92,83 → 84,84
); |
|
-- State vector declaration |
ATTRIBUTE state_vector : string; |
ATTRIBUTE state_vector OF fsm : ARCHITECTURE IS "current_state"; |
attribute state_vector : string; |
attribute state_vector of fsm : architecture is "current_state"; |
|
-- Declare current and next state signals |
SIGNAL current_state : STATE_TYPE; |
SIGNAL next_state : STATE_TYPE; |
signal current_state : state_type; |
signal next_state : state_type; |
|
-- Declare any pre-registered internal signals |
SIGNAL nmi_o_cld : std_logic ; |
signal nmi_o_cld : std_logic ; |
|
BEGIN |
begin |
|
----------------------------------------------------------------- |
clocked_proc : PROCESS ( |
clocked_proc : process ( |
clk_clk_i, |
rst_rst_n_i |
) |
----------------------------------------------------------------- |
BEGIN |
IF (rst_rst_n_i = '0') THEN |
begin |
if (rst_rst_n_i = '0') then |
current_state <= idle; |
-- Default Reset Values |
nmi_o_cld <= '0'; |
ELSIF (clk_clk_i'EVENT AND clk_clk_i = '1') THEN |
elsif (clk_clk_i'event and clk_clk_i = '1') then |
current_state <= next_state; |
-- Default Assignment To Internals |
nmi_o_cld <= '0'; |
|
-- Combined Actions |
CASE current_state IS |
WHEN IMP => |
case current_state is |
when IMP => |
nmi_o_cld <= '1'; |
WHEN OTHERS => |
NULL; |
END CASE; |
END IF; |
END PROCESS clocked_proc; |
when others => |
null; |
end case; |
end if; |
end process clocked_proc; |
|
----------------------------------------------------------------- |
nextstate_proc : PROCESS ( |
nextstate_proc : process ( |
current_state, |
fetch_i, |
nmi_n_i |
) |
----------------------------------------------------------------- |
BEGIN |
CASE current_state IS |
WHEN idle => |
IF (nmi_n_i = '1') THEN |
begin |
case current_state is |
-- <<< REQ1 |
when idle => |
if (nmi_n_i = '1') then |
next_state <= idle1; |
ELSE |
else |
next_state <= idle; |
END IF; |
WHEN idle1 => |
IF (nmi_n_i = '0') THEN |
end if; |
when idle1 => |
if (nmi_n_i = '0') then |
next_state <= idle2; |
ELSE |
else |
next_state <= idle1; |
END IF; |
WHEN idle2 => |
IF (nmi_n_i = '0') THEN |
end if; |
when idle2 => |
if (nmi_n_i = '0') then |
next_state <= IMP; |
ELSE |
else |
next_state <= idle; |
END IF; |
WHEN IMP => |
IF (fetch_i = '1') THEN |
end if; |
when IMP => |
if (fetch_i = '1') then |
next_state <= idle; |
ELSE |
else |
next_state <= IMP; |
END IF; |
WHEN OTHERS => |
end if; |
when others => |
next_state <= idle; |
END CASE; |
END PROCESS nextstate_proc; |
end case; |
end process nextstate_proc; |
|
-- Concurrent Statements |
-- Clocked output assignments |
nmi_o <= nmi_o_cld; |
END fsm; |
end fsm; |
/trunk/rtl/vhdl/regbank_axy.vhd
2,7 → 2,7
-- |
-- Created: |
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) |
-- at - 20:45:03 03.01.2009 |
-- at - 15:22:29 25.02.2009 |
-- |
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) |
-- |
31,7 → 31,7
|
-- Jens-D. Gutschmidt Project: R65C02_TC |
-- scantara2003@yahoo.de |
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG |
-- COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG |
-- |
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or any later version. |
43,25 → 43,17
-- |
-- CVS Revisins History |
-- |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.3 2009/01/04 10:20:51 eda |
-- Changes for cosmetic issues only |
-- |
-- Revision 1.2 2009/01/04 09:23:15 eda |
-- - Delete unused nets and blocks (same as R6502_TC) |
-- - Rename blocks |
-- - Re-arrage FSM symbols in block FSM_Execution_Unit |
-- |
-- $Log: not supported by cvs2svn $ |
-- <<-- more -->> |
-- Title: Register Bank for register A, X and Y |
-- Path: R65C02_TC/RegBank_AXY/struct |
-- Edited: by eda on 02 Jan 2009 |
-- Edited: by eda on 10 Feb 2009 |
-- |
-- VHDL Architecture R65C02_TC.RegBank_AXY.struct |
-- |
-- Created: |
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) |
-- at - 20:45:04 03.01.2009 |
-- at - 15:22:29 25.02.2009 |
-- |
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) |
-- |
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@@ -1,3 +1,11 @@
+(February 25th 2009)
+- (DONE) CORRECTED "RTI" (wrong: use of stack pointer)
+- (DONE) CORRECTED "RMBx" & "SMBx" (wrong: bit translation)
+- (DONE) RENAME all states of "FSM Execution Unit" for better reading
+- (85%) Finish working for Specification of cpu65C02_tc
+- (DONE) CORRECT timing for addressing mode "ABS,X" for "INC" (wrong: 6 cycles instead of 7)
+- (DONE) OPTIMIZE end states of "STA" (s197,s207,s200,s213)
+
(January, 4th 2009)
- (DONE) Remove unused nets, register and modules
- (DONE) Update the HDL Designer files for better viewing and