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/trunk/rtl/Verilog/reg_pc.v
0,0 → 1,251
`define false 1'b 0
`define FALSE 1'b 0
`define true 1'b 1
`define TRUE 1'b 1
 
`timescale 1 ns / 1 ns // timescale for following modules
 
 
// VHDL Entity R65C02_TC.Reg_PC.symbol
//
// Created:
// by - eda.UNKNOWN (ENTWICKL4-XP-PR)
// at - 15:22:28 25.02.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
 
module Reg_PC (
adr_i,
clk_clk_i,
ld_i,
ld_pc_i,
offset_i,
rst_rst_n_i,
sel_pc_in_i,
sel_pc_val_i,
adr_nxt_pc_o,
adr_pc_o);
 
input [15:0] adr_i;
input clk_clk_i;
input [1:0] ld_i;
input ld_pc_i;
input [15:0] offset_i;
input rst_rst_n_i;
input sel_pc_in_i;
input [1:0] sel_pc_val_i;
output [15:0] adr_nxt_pc_o;
output [15:0] adr_pc_o;
 
 
// Jens-D. Gutschmidt Project: R65C02_TC
// scantara2003@yahoo.de
// COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG
//
// This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// CVS Revisins History
//
// $Log: not supported by cvs2svn $
// <<-- more -->>
// Title: Program Counter Logic
// Path: R65C02_TC/Reg_PC/struct
// Edited: by eda on 10 Feb 2009
//
// VHDL Architecture R65C02_TC.Reg_PC.struct
//
// Created:
// by - eda.UNKNOWN (ENTWICKL4-XP-PR)
// at - 15:22:29 25.02.2009
//
// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
//
wire [15:0] adr_nxt_pc_o;
wire [15:0] adr_pc_o;
 
// Declarations
wire [7:0] adr_pc_high_o_i;
wire [7:0] adr_pc_low_o_i;
reg [15:0] adr_pc_o_i;
wire ci_o_i;
wire cout_pc_o_i;
wire load3_o_i;
wire load_o_i;
wire [7:0] offset_high_o_i;
wire [7:0] offset_low_o_i;
reg [7:0] val_o_i;
wire [7:0] val_one;
wire [7:0] val_zero;
 
// Implicit buffer signal declarations
wire [15:0] adr_pc_o_internal;
wire [15:0] adr_nxt_pc_o_internal;
 
// ModuleWare signal declarations(v1.9) for instance 'U_2' of 'add'
wire [8:0] mw_U_2temp_din0;
wire [8:0] mw_U_2temp_din1;
reg [8:0] mw_U_2sum;
 
// ModuleWare signal declarations(v1.9) for instance 'U_11' of 'add'
wire [8:0] mw_U_11temp_din0;
wire [8:0] mw_U_11temp_din1;
reg [8:0] mw_U_11sum;
 
// ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
reg [7:0] mw_U_0reg_cval;
 
// ModuleWare signal declarations(v1.9) for instance 'U_4' of 'adff'
reg [7:0] mw_U_4reg_cval;
 
// ModuleWare code(v1.9) for instance 'U_2' of 'add'
reg u_2combo_proc_temp_carry;
reg u_11combo_proc_temp_carry;
 
assign mw_U_2temp_din0 = {1'b 0, adr_pc_low_o_i};
assign mw_U_2temp_din1 = {1'b 0, val_o_i};
 
always @(mw_U_2temp_din0 or mw_U_2temp_din1)
begin : u_2combo_proc
u_2combo_proc_temp_carry = 1'b 0;
mw_U_2sum <= mw_U_2temp_din0 + mw_U_2temp_din1 + u_2combo_proc_temp_carry;
end
 
assign adr_nxt_pc_o_internal[7:0] = mw_U_2sum[7:0];
assign cout_pc_o_i = mw_U_2sum[8];
 
// ModuleWare code(v1.9) for instance 'U_11' of 'add'
assign mw_U_11temp_din0 = {1'b 0, adr_pc_high_o_i};
assign mw_U_11temp_din1 = {1'b 0, offset_high_o_i};
 
always @(mw_U_11temp_din0 or mw_U_11temp_din1 or ci_o_i)
begin : u_11combo_proc
u_11combo_proc_temp_carry = ci_o_i;
mw_U_11sum <= mw_U_11temp_din0 + mw_U_11temp_din1 + u_11combo_proc_temp_carry;
end
 
assign adr_nxt_pc_o_internal[15:8] = mw_U_11sum[7:0];
// ModuleWare code(v1.9) for instance 'U_0' of 'adff'
assign adr_pc_o_internal[7:0] = mw_U_0reg_cval;
 
always @(posedge clk_clk_i or negedge rst_rst_n_i)
begin : u_0seq_proc
if (rst_rst_n_i == 1'b 0)
begin
mw_U_0reg_cval <= 8'b 00000000;
end
else
begin
if (load_o_i == 1'b 1)
begin
mw_U_0reg_cval <= adr_nxt_pc_o_internal[7:0];
end
end
end
 
// ModuleWare code(v1.9) for instance 'U_4' of 'adff'
assign adr_pc_o_internal[15:8] = mw_U_4reg_cval;
 
always @(posedge clk_clk_i or negedge rst_rst_n_i)
begin : u_4seq_proc
if (rst_rst_n_i == 1'b 0)
begin
mw_U_4reg_cval <= 8'b 00000000;
end
else
begin
if (load3_o_i == 1'b 1)
begin
mw_U_4reg_cval <= adr_nxt_pc_o_internal[15:8];
end
end
end
 
// ModuleWare code(v1.9) for instance 'U_6' of 'and'
assign load_o_i = ld_pc_i & ld_i[0];
 
// ModuleWare code(v1.9) for instance 'U_7' of 'and'
assign load3_o_i = ld_pc_i & ld_i[1];
 
// ModuleWare code(v1.9) for instance 'U_10' of 'and'
assign ci_o_i = cout_pc_o_i & ld_pc_i;
 
// ModuleWare code(v1.9) for instance 'U_1' of 'constval'
assign val_zero = 8'b 00000000;
 
// ModuleWare code(v1.9) for instance 'U_9' of 'constval'
assign val_one = 8'b 00000001;
 
// ModuleWare code(v1.9) for instance 'U_8' of 'mux'
 
always @(adr_pc_o_internal or adr_i or sel_pc_in_i)
begin : u_8combo_proc
case (sel_pc_in_i)
1'b 0:
begin
adr_pc_o_i <= adr_pc_o_internal;
end
1'b 1:
begin
adr_pc_o_i <= adr_i;
end
default:
begin
adr_pc_o_i <= {16{1'b X}};
end
endcase
end
 
// ModuleWare code(v1.9) for instance 'U_13' of 'mux'
 
always @(val_one or val_zero or offset_low_o_i or sel_pc_val_i)
begin : u_13combo_proc
case (sel_pc_val_i)
2'b 00:
begin
val_o_i <= val_one;
end
2'b 01:
begin
val_o_i <= val_zero;
end
2'b 10:
begin
val_o_i <= offset_low_o_i;
end
2'b 11:
begin
val_o_i <= val_zero;
end
default:
begin
val_o_i <= {8{1'b X}};
end
endcase
end
 
// ModuleWare code(v1.9) for instance 'U_3' of 'split'
assign adr_pc_low_o_i = adr_pc_o_i[7:0];
assign adr_pc_high_o_i = adr_pc_o_i[15:8];
 
// ModuleWare code(v1.9) for instance 'U_5' of 'split'
assign offset_low_o_i = offset_i[7:0];
assign offset_high_o_i = offset_i[15:8];
 
// Instance port mappings.
// Implicit buffered output assignments
assign adr_pc_o = adr_pc_o_internal;
assign adr_nxt_pc_o = adr_nxt_pc_o_internal;
 
// Architecture declarations
// Internal signal declarations
 
endmodule // module Reg_PC
 
trunk/rtl/Verilog/reg_pc.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/rtl/Verilog/reg_sp.v =================================================================== --- trunk/rtl/Verilog/reg_sp.v (nonexistent) +++ trunk/rtl/Verilog/reg_sp.v (revision 13) @@ -0,0 +1,169 @@ +`define false 1'b 0 +`define FALSE 1'b 0 +`define true 1'b 1 +`define TRUE 1'b 1 + +`timescale 1 ns / 1 ns // timescale for following modules + + +// VHDL Entity R65C02_TC.Reg_SP.symbol +// +// Created: +// by - eda.UNKNOWN (ENTWICKL4-XP-PR) +// at - 15:22:29 25.02.2009 +// +// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +// + +module Reg_SP ( + adr_low_i, + clk_clk_i, + ld_low_i, + ld_sp_i, + rst_rst_n_i, + sel_sp_as_i, + sel_sp_in_i, + adr_sp_o); + + +input [7:0] adr_low_i; +input clk_clk_i; +input ld_low_i; +input ld_sp_i; +input rst_rst_n_i; +input sel_sp_as_i; +input sel_sp_in_i; +output [15:0] adr_sp_o; + + +// Jens-D. Gutschmidt Project: R65C02_TC +// scantara2003@yahoo.de +// COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG +// +// This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along with this program. If not, see . +// +// CVS Revisins History +// +// $Log: not supported by cvs2svn $ +// <<-- more -->> +// Title: Stack Pointer Logic +// Path: R65C02_TC/Reg_SP/struct +// Edited: by eda on 10 Feb 2009 +// +// VHDL Architecture R65C02_TC.Reg_SP.struct +// +// Created: +// by - eda.UNKNOWN (ENTWICKL4-XP-PR) +// at - 15:22:29 25.02.2009 +// +// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +// +wire [15:0] adr_sp_o; + +// Declarations +wire [7:0] adr_sp_low_o_i; +wire load_o_i; +reg [7:0] result_low1_o_i; +wire [7:0] result_low_o_i; +wire sp_as_n_o_i; +wire [7:0] val_one; + +// Implicit buffer signal declarations +wire [15:0] adr_sp_o_internal; + +// ModuleWare signal declarations(v1.9) for instance 'U_11' of 'addsub' +wire [8:0] mw_U_11temp_din0; +wire [8:0] mw_U_11temp_din1; +reg [8:0] mw_U_11sum; + +// ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff' +reg [7:0] mw_U_0reg_cval; + +// ModuleWare code(v1.9) for instance 'U_11' of 'addsub' +reg u_11combo_proc_temp_carry; + +assign mw_U_11temp_din0 = {1'b 0, adr_sp_low_o_i}; +assign mw_U_11temp_din1 = {1'b 0, val_one}; + +always @(mw_U_11temp_din0 or mw_U_11temp_din1 or sp_as_n_o_i) + begin : u_11combo_proc + u_11combo_proc_temp_carry = 1'b 0; + if (sp_as_n_o_i == 1'b 1) + begin + mw_U_11sum <= mw_U_11temp_din0 + mw_U_11temp_din1 + u_11combo_proc_temp_carry; + end + else + begin + mw_U_11sum <= mw_U_11temp_din0 - mw_U_11temp_din1 - u_11combo_proc_temp_carry; + end + end + +assign result_low_o_i = mw_U_11sum[7:0]; +// ModuleWare code(v1.9) for instance 'U_0' of 'adff' +assign adr_sp_o_internal[7:0] = mw_U_0reg_cval; + +always @(posedge clk_clk_i or negedge rst_rst_n_i) + begin : u_0seq_proc + if (rst_rst_n_i == 1'b 0) + begin + mw_U_0reg_cval <= 8'b 00000000; + end + else + begin + if (load_o_i == 1'b 1) + begin + mw_U_0reg_cval <= result_low1_o_i; + end + end + end + +// ModuleWare code(v1.9) for instance 'U_6' of 'and' +assign load_o_i = ld_sp_i & ld_low_i; + +// ModuleWare code(v1.9) for instance 'U_3' of 'buff' +assign adr_sp_o_internal[15:8] = val_one; + +// ModuleWare code(v1.9) for instance 'U_4' of 'constval' +assign val_one = 8'b 00000001; + +// ModuleWare code(v1.9) for instance 'U_2' of 'inv' +assign sp_as_n_o_i = ~sel_sp_as_i; + +// ModuleWare code(v1.9) for instance 'U_8' of 'mux' + +always @(result_low_o_i or adr_low_i or sel_sp_in_i) + begin : u_8combo_proc + case (sel_sp_in_i) + 1'b 0: + begin + result_low1_o_i <= result_low_o_i; + end + 1'b 1: + begin + result_low1_o_i <= adr_low_i; + end + default: + begin + result_low1_o_i <= {8{1'b X}}; + end + endcase + end + +// ModuleWare code(v1.9) for instance 'U_10' of 'tap' +assign adr_sp_low_o_i = adr_sp_o_internal[7:0]; + +// Instance port mappings. +// Implicit buffered output assignments +assign adr_sp_o = adr_sp_o_internal; + +// Architecture declarations +// Internal signal declarations + +endmodule // module Reg_SP +
trunk/rtl/Verilog/reg_sp.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/rtl/Verilog/fsm_execution_unit.v =================================================================== --- trunk/rtl/Verilog/fsm_execution_unit.v (nonexistent) +++ trunk/rtl/Verilog/fsm_execution_unit.v (revision 13) @@ -0,0 +1,7217 @@ +`define false 1'b 0 +`define FALSE 1'b 0 +`define true 1'b 1 +`define TRUE 1'b 1 + +`timescale 1 ns / 1 ns // timescale for following modules + + +// VHDL Entity R65C02_TC.FSM_Execution_Unit.symbol +// +// Created: +// by - eda.UNKNOWN (ENTWICKL4-XP-PR) +// at - 15:22:30 25.02.2009 +// +// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +// + +module FSM_Execution_Unit ( + adr_nxt_pc_i, + adr_pc_i, + adr_sp_i, + alu_dec_val_i, + clk_clk_i, + d_alu_i, + d_i, + d_regs_out_i, + irq_n_i, + nmi_i, + q_a_i, + q_x_i, + q_y_i, + rdy_i, + reg_0flag_i, + reg_1flag_i, + reg_7flag_i, + rst_rst_n_i, + so_n_i, + a_o, + adr_o, + ch_a_o, + ch_b_o, + d_o, + d_regs_in_o, + fetch_o, + ld_o, + ld_pc_o, + ld_sp_o, + load_regs_o, + offset_o, + rd_o, + sel_pc_in_o, + sel_pc_val_o, + sel_rb_in_o, + sel_rb_out_o, + sel_reg_o, + sel_sp_as_o, + sel_sp_in_o, + sync_o, + wr_o); + + +input [15:0] adr_nxt_pc_i; +input [15:0] adr_pc_i; +input [15:0] adr_sp_i; +input [7:0] alu_dec_val_i; +input clk_clk_i; +input [7:0] d_alu_i; +input [7:0] d_i; +input [7:0] d_regs_out_i; +input irq_n_i; +input nmi_i; +input [7:0] q_a_i; +input [7:0] q_x_i; +input [7:0] q_y_i; +input rdy_i; +input reg_0flag_i; +input reg_1flag_i; +input reg_7flag_i; +input rst_rst_n_i; +input so_n_i; +output [15:0] a_o; +output [15:0] adr_o; +output [7:0] ch_a_o; +output [7:0] ch_b_o; +output [7:0] d_o; +output [7:0] d_regs_in_o; +output fetch_o; +output [1:0] ld_o; +output ld_pc_o; +output ld_sp_o; +output load_regs_o; +output [15:0] offset_o; +output rd_o; +output sel_pc_in_o; +output [1:0] sel_pc_val_o; +output [1:0] sel_rb_in_o; +output [1:0] sel_rb_out_o; +output [1:0] sel_reg_o; +output sel_sp_as_o; +output sel_sp_in_o; +output sync_o; +output wr_o; + + +// Jens-D. Gutschmidt Project: R65C02_TC +// scantara2003@yahoo.de +// COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG +// +// This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along with this program. If not, see . +// +// CVS Revisins History +// +// $Log: not supported by cvs2svn $ +// <<-- more -->> +// Title: FSM Execution Unit for all op codes +// Path: R65C02_TC/FSM_Execution_Unit/fsm +// Edited: by eda on 25 Feb 2009 +// +// VHDL Architecture R65C02_TC.FSM_Execution_Unit.fsm +// +// Created: +// by - eda.UNKNOWN (ENTWICKL4-XP-PR) +// at - 15:22:32 25.02.2009 +// +// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +// +reg [15:0] a_o; +reg [15:0] adr_o; +reg [7:0] ch_a_o; +reg [7:0] ch_b_o; +wire [7:0] d_o; +reg [7:0] d_regs_in_o; +reg fetch_o; +reg [1:0] ld_o; +reg ld_pc_o; +reg ld_sp_o; +reg load_regs_o; +reg [15:0] offset_o; +wire rd_o; +reg sel_pc_in_o; +reg [1:0] sel_pc_val_o; +reg [1:0] sel_rb_in_o; +reg [1:0] sel_rb_out_o; +reg [1:0] sel_reg_o; +reg sel_sp_as_o; +reg sel_sp_in_o; +wire sync_o; +wire wr_o; + +// Declarations +reg [7:0] reg_F; +reg [15:0] reg_PC; +reg [15:0] reg_PC1; +reg reg_sel_pc_in; +reg [1:0] reg_sel_pc_val; +reg [1:0] reg_sel_rb_in; +reg [1:0] reg_sel_rb_out; +reg [1:0] reg_sel_reg; +reg reg_sel_sp_as; +reg reg_sel_sp_in; +reg [7:0] sig_D_OUT; +reg [15:0] sig_PC; +reg sig_SYNC; +reg sig_WR; +reg [8:0] zw_ALU; +reg [4:0] zw_ALU1; +reg [4:0] zw_ALU2; +reg [4:0] zw_ALU3; +reg [4:0] zw_ALU4; +reg [3:0] zw_ALU5; +reg [3:0] zw_ALU6; +reg [15:0] zw_PC; +reg [8:0] zw_REG_ALU; +reg zw_REG_NMI; +reg [7:0] zw_REG_OP; +reg [15:0] zw_REG_sig_PC; +reg [7:0] zw_b1; +reg [7:0] zw_b2; +reg [7:0] zw_b3; +reg [7:0] zw_b4; +reg zw_so; +reg [15:0] zw_w1; +reg [15:0] zw_w2; +reg [15:0] zw_w3; + +// Hard encoding +parameter G30_1 = 8'b 00000000; +parameter G30_3 = 8'b 00000001; +parameter G30_4 = 8'b 00000010; +parameter G30_5 = 8'b 00000011; +parameter G30_e = 8'b 00000100; +parameter G30_2 = 8'b 00000101; +parameter RES = 8'b 00000110; +parameter G28_1 = 8'b 00000111; +parameter G28_2 = 8'b 00001000; +parameter G28_3 = 8'b 00001001; +parameter G28_5 = 8'b 00001010; +parameter G28_4 = 8'b 00001011; +parameter G28_e = 8'b 00001100; +parameter G29_1 = 8'b 00001101; +parameter G29_2 = 8'b 00001110; +parameter G29_3 = 8'b 00001111; +parameter G29_5 = 8'b 00010000; +parameter G29_4 = 8'b 00010001; +parameter G29_e = 8'b 00010010; +parameter FETCH = 8'b 00010011; +parameter G1_1 = 8'b 00010100; +parameter G2_1 = 8'b 00010101; +parameter G3_1 = 8'b 00010110; +parameter G4_1 = 8'b 00010111; +parameter G9_1 = 8'b 00011000; +parameter G5_1 = 8'b 00011001; +parameter G6_1 = 8'b 00011010; +parameter G7_1 = 8'b 00011011; +parameter G8_1 = 8'b 00011100; +parameter G19_1 = 8'b 00011101; +parameter G15_1 = 8'b 00011110; +parameter G15_3 = 8'b 00011111; +parameter G15_4 = 8'b 00100000; +parameter G15_5 = 8'b 00100001; +parameter G15_2 = 8'b 00100010; +parameter G15_7 = 8'b 00100011; +parameter G15_e3 = 8'b 00100100; +parameter G15_6 = 8'b 00100101; +parameter G15_e2 = 8'b 00100110; +parameter G15_e1 = 8'b 00100111; +parameter G15_8 = 8'b 00101000; +parameter G10_1 = 8'b 00101001; +parameter G10_3 = 8'b 00101010; +parameter G10_4 = 8'b 00101011; +parameter G10_5 = 8'b 00101100; +parameter G10_2 = 8'b 00101101; +parameter G10_7 = 8'b 00101110; +parameter G10_e3 = 8'b 00101111; +parameter G10_e1 = 8'b 00110000; +parameter G10_e2 = 8'b 00110001; +parameter G10_6 = 8'b 00110010; +parameter G10_8 = 8'b 00110011; +parameter G17_1 = 8'b 00110100; +parameter G17_4 = 8'b 00110101; +parameter G17_6 = 8'b 00110110; +parameter G17_3 = 8'b 00110111; +parameter G17_2 = 8'b 00111000; +parameter G17_8 = 8'b 00111001; +parameter G17_9 = 8'b 00111010; +parameter G17_7 = 8'b 00111011; +parameter G17_5 = 8'b 00111100; +parameter G17_10 = 8'b 00111101; +parameter G17_e = 8'b 00111110; +parameter G17_11 = 8'b 00111111; +parameter G16_1 = 8'b 01000000; +parameter G16_3 = 8'b 01000001; +parameter G16_4 = 8'b 01000010; +parameter G16_5 = 8'b 01000011; +parameter G16_2 = 8'b 01000100; +parameter G16_7 = 8'b 01000101; +parameter G16_6 = 8'b 01000110; +parameter G16_e3 = 8'b 01000111; +parameter G16_e1 = 8'b 01001000; +parameter G16_e2 = 8'b 01001001; +parameter G16_8 = 8'b 01001010; +parameter G11_1 = 8'b 01001011; +parameter G11_5 = 8'b 01001100; +parameter G11_6 = 8'b 01001101; +parameter G11_2 = 8'b 01001110; +parameter G11_7 = 8'b 01001111; +parameter G11_3 = 8'b 01010000; +parameter G11_4 = 8'b 01010001; +parameter G11_e = 8'b 01010010; +parameter G31_1 = 8'b 01010011; +parameter G34_1 = 8'b 01010100; +parameter G32_1 = 8'b 01010101; +parameter G33_1 = 8'b 01010110; +parameter G12_1 = 8'b 01010111; +parameter G12_e1 = 8'b 01011000; +parameter G12_e2 = 8'b 01011001; +parameter G12_2 = 8'b 01011010; +parameter G12_3 = 8'b 01011011; +parameter G12_4 = 8'b 01011100; +parameter G20_1 = 8'b 01011101; +parameter G20_2 = 8'b 01011110; +parameter G20_5 = 8'b 01011111; +parameter G20_e = 8'b 01100000; +parameter G20_3 = 8'b 01100001; +parameter G20_4 = 8'b 01100010; +parameter G21_1 = 8'b 01100011; +parameter G21_2 = 8'b 01100100; +parameter G21_3 = 8'b 01100101; +parameter G21_4 = 8'b 01100110; +parameter G21_e = 8'b 01100111; +parameter G13_3 = 8'b 01101000; +parameter G13_1 = 8'b 01101001; +parameter G13_4 = 8'b 01101010; +parameter G13_2 = 8'b 01101011; +parameter G13_e1 = 8'b 01101100; +parameter G13_e2 = 8'b 01101101; +parameter G18_1 = 8'b 01101110; +parameter G18_2 = 8'b 01101111; +parameter G18_3 = 8'b 01110000; +parameter G18_4 = 8'b 01110001; +parameter G18_e = 8'b 01110010; +parameter G18_5 = 8'b 01110011; +parameter G26_1 = 8'b 01110100; +parameter G26_2 = 8'b 01110101; +parameter G26_3 = 8'b 01110110; +parameter G26_4 = 8'b 01110111; +parameter G26_e = 8'b 01111000; +parameter G27_1 = 8'b 01111001; +parameter G27_2 = 8'b 01111010; +parameter G27_3 = 8'b 01111011; +parameter G27_4 = 8'b 01111100; +parameter G27_e = 8'b 01111101; +parameter G14_1 = 8'b 01111110; +parameter G14_5 = 8'b 01111111; +parameter G14_6 = 8'b 10000000; +parameter G14_2 = 8'b 10000001; +parameter G14_7 = 8'b 10000010; +parameter G14_3 = 8'b 10000011; +parameter G14_4 = 8'b 10000100; +parameter G14_e = 8'b 10000101; +parameter G22_1 = 8'b 10000110; +parameter G22_e = 8'b 10000111; +parameter G23_1 = 8'b 10001000; +parameter G23_e = 8'b 10001001; +parameter G24_1 = 8'b 10001010; +parameter G24_2 = 8'b 10001011; +parameter G24_e = 8'b 10001100; +parameter G25_1 = 8'b 10001101; +parameter G25_2 = 8'b 10001110; +parameter G25_e = 8'b 10001111; + +// Declare current and next state signals +reg [7:0] current_state; +reg [7:0] next_state; + +// Declare any pre-registered internal signals +reg [7:0] d_o_cld; +reg rd_o_cld; +reg sync_o_cld; +reg wr_o_cld; + +// --------------------------------------------------------------- + + +always @(posedge clk_clk_i or negedge rst_rst_n_i) + begin : clocked_proc + if (rst_rst_n_i == 1'b 0) + begin + current_state <= RES; + +// Default Reset Values + d_o_cld <= 8'h 00; + rd_o_cld <= 1'b 0; + sync_o_cld <= 1'b 0; + wr_o_cld <= 1'b 0; + reg_F <= 8'b 00000100; + reg_PC <= 16'h 0000; + reg_PC1 <= 16'h 0000; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_rb_in <= 2'b 00; + reg_sel_rb_out <= 2'b 00; + reg_sel_reg <= 2'b 00; + reg_sel_sp_as <= 1'b 0; + reg_sel_sp_in <= 1'b 0; + sig_PC <= 16'h 0000; + zw_PC <= 16'h 0000; + zw_REG_ALU <= {1'b 0, 8'h 00}; + zw_REG_NMI <= 1'b 0; + zw_REG_OP <= 8'h 00; + zw_REG_sig_PC <= 16'h 0000; + zw_b1 <= 8'h 00; + zw_b2 <= 8'h 00; + zw_b3 <= 8'h 00; + zw_b4 <= 8'h 00; + zw_so <= 1'b 0; + zw_w1 <= 16'h 0000; + zw_w2 <= 16'h 0000; + zw_w3 <= 16'h 0000; + end + else + begin + current_state <= next_state; + +// Default Assignment To Internals + reg_F <= {reg_F[7], (zw_so | reg_F[6]), reg_F[5:0]}; + reg_PC <= reg_PC; + reg_PC1 <= reg_PC1; + reg_sel_pc_in <= reg_sel_pc_in; + reg_sel_pc_val <= reg_sel_pc_val; + reg_sel_rb_in <= reg_sel_rb_in; + reg_sel_rb_out <= reg_sel_rb_out; + reg_sel_reg <= reg_sel_reg; + reg_sel_sp_as <= reg_sel_sp_as; + reg_sel_sp_in <= reg_sel_sp_in; + sig_PC <= sig_PC; + zw_PC <= zw_PC; + zw_REG_ALU <= zw_REG_ALU; + zw_REG_NMI <= zw_REG_NMI | nmi_i; + zw_REG_OP <= zw_REG_OP; + zw_REG_sig_PC <= zw_REG_sig_PC; + zw_b1 <= zw_b1; + zw_b2 <= zw_b2; + zw_b3 <= zw_b3; + zw_b4 <= zw_b4; + zw_so <= (zw_so | ~so_n_i) & ~reg_F[6]; + zw_w1 <= zw_w1; + zw_w2 <= zw_w2; + zw_w3 <= zw_w3; + d_o_cld <= sig_D_OUT; + rd_o_cld <= ~sig_WR; + sync_o_cld <= sig_SYNC; + wr_o_cld <= sig_WR; + +// Combined Actions + case (current_state) + G30_1: + begin + sig_PC <= adr_sp_i; + end + G30_3: + begin + sig_PC <= adr_sp_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + end + G30_4: + begin + sig_PC <= adr_pc_i; + end + G30_5: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_pc_i; + zw_w1[7:0] <= d_i; + reg_sel_pc_in <= 1'b 1; + reg_sel_pc_val <= 2'b 11; + end + end + G30_e: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_w1[7:0]}; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G30_2: + begin + sig_PC <= adr_sp_i; + reg_sel_pc_in <= 1'b 1; + reg_sel_pc_val <= 2'b 00; + end + RES: + begin + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + sig_PC <= adr_nxt_pc_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + G28_1: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_sp_i; + end + end + G28_2: + begin + sig_PC <= adr_sp_i; + end + G28_3: + begin + sig_PC <= adr_sp_i; + end + G28_5: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= 16'h FFFF; + zw_b1 <= d_i; + end + end + G28_4: + begin + sig_PC <= 16'h FFFE; + end + G28_e: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_b1}; + reg_F[2] <= 1'b 1; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G29_1: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_sp_i; + end + end + G29_2: + begin + sig_PC <= adr_sp_i; + end + G29_3: + begin + sig_PC <= adr_sp_i; + end + G29_5: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= 16'h FFFB; + reg_sel_pc_in <= 1'b 1; + reg_sel_pc_val <= 2'b 11; + zw_b1 <= d_i; + end + end + G29_4: + begin + sig_PC <= 16'h FFFA; + end + G29_e: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_b1}; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + FETCH: + begin + zw_REG_OP <= d_i; + if (zw_REG_NMI == 1'b 1 & rdy_i == 1'b 1) + begin + sig_PC <= adr_nxt_pc_i; + zw_REG_NMI <= 1'b 0; + end + else if (irq_n_i == 1'b 0 & reg_F[2] == 1'b 0 & + rdy_i == 1'b 1 ) + begin + sig_PC <= adr_nxt_pc_i; + end + else if ((d_i == 8'h 69 | d_i == 8'h 65 | + d_i == 8'h 75 | d_i == 8'h 6D | + d_i == 8'h 7D | d_i == 8'h 79 | + d_i == 8'h 61 | d_i == 8'h 71 | + d_i == 8'h 72) & rdy_i == 1'b 1 ) + begin + sig_PC <= adr_nxt_pc_i; + reg_sel_reg <= 2'b 00; + reg_sel_rb_in <= 2'b 11; + zw_b1[0] <= reg_F[7]; + end + else if ((d_i == 8'h 06 | d_i == 8'h 16 | + d_i == 8'h 0E | d_i == 8'h 1E | + d_i[3:0] == 4'h 7 | d_i == 8'h 14 | + d_i == 8'h 04 | d_i == 8'h 0C | + d_i == 8'h 1C) & rdy_i == 1'b 1 ) + begin + sig_PC <= adr_nxt_pc_i; + end + else if ((d_i == 8'h 90 | d_i == 8'h B0 | + d_i == 8'h F0 | d_i == 8'h 30 | + d_i == 8'h D0 | d_i == 8'h 10 | + d_i == 8'h 50 | d_i == 8'h 70 | + d_i == 8'h 80 | d_i[3:0] == 4'h F) & + rdy_i == 1'b 1 ) + begin + sig_PC <= adr_nxt_pc_i; + zw_b3 <= adr_nxt_pc_i[15:8]; + end + else if ((d_i == 8'h 24 | d_i == 8'h 2C | + d_i == 8'h 3C | d_i == 8'h 34 | + d_i == 8'h 89) & rdy_i == 1'b 1 ) + begin + sig_PC <= adr_nxt_pc_i; + end + else if (d_i == 8'h 00 & rdy_i == 1'b 1 ) + begin + sig_PC <= adr_nxt_pc_i; + end + else if (d_i == 8'h 18 & rdy_i == 1'b 1 ) + ; + else if (d_i == 8'h D8 & rdy_i == 1'b 1 ) + ; + else if (d_i == 8'h 58 & rdy_i == 1'b 1 ) + ; + else if (d_i == 8'h B8 & rdy_i == 1'b 1 ) + ; + else if ((d_i == 8'h E0 | d_i == 8'h E4 | + d_i == 8'h EC) & rdy_i == 1'b 1 ) + begin + reg_sel_rb_out <= 2'b 01; + sig_PC <= adr_nxt_pc_i; + end + else if ((d_i == 8'h C0 | d_i == 8'h C4 | + d_i == 8'h CC) & rdy_i == 1'b 1 ) + begin + reg_sel_rb_out <= 2'b 10; + sig_PC <= adr_nxt_pc_i; + end + else if ((d_i == 8'h C6 | d_i == 8'h D6 | + d_i == 8'h CE | d_i == 8'h DE) & + rdy_i == 1'b 1 ) + begin + zw_b4 <= 8'h FF; + sig_PC <= adr_nxt_pc_i; + end + else if (d_i == 8'h CA & rdy_i == 1'b 1 ) + begin + reg_sel_rb_out <= 2'b 01; + reg_sel_reg <= 2'b 01; + reg_sel_rb_in <= 2'b 11; + zw_b4 <= 8'h FF; + end + else if (d_i == 8'h 88 & rdy_i == 1'b 1 ) + begin + reg_sel_rb_out <= 2'b 10; + reg_sel_reg <= 2'b 10; + reg_sel_rb_in <= 2'b 11; + zw_b4 <= 8'h FF; + end + else if ((d_i == 8'h 49 | d_i == 8'h 45 | + d_i == 8'h 55 | d_i == 8'h 4D | + d_i == 8'h 5D | d_i == 8'h 59 | + d_i == 8'h 41 | d_i == 8'h 51 | + d_i == 8'h 09 | d_i == 8'h 05 | + d_i == 8'h 15 | d_i == 8'h 0D | + d_i == 8'h 1D | d_i == 8'h 19 | + d_i == 8'h 01 | d_i == 8'h 11 | + d_i == 8'h 29 | d_i == 8'h 25 | + d_i == 8'h 35 | d_i == 8'h 2D | + d_i == 8'h 3D | d_i == 8'h 39 | + d_i == 8'h 21 | d_i == 8'h 31 | + d_i == 8'h C9 | d_i == 8'h C5 | + d_i == 8'h D5 | d_i == 8'h CD | + d_i == 8'h DD | d_i == 8'h D9 | + d_i == 8'h C1 | d_i == 8'h D1 | + d_i == 8'h 32 | d_i == 8'h D2 | + d_i == 8'h 52 | d_i == 8'h 12) & + rdy_i == 1'b 1 ) + begin + reg_sel_rb_out <= 2'b 00; + reg_sel_reg <= 2'b 00; + reg_sel_rb_in <= 2'b 11; + sig_PC <= adr_nxt_pc_i; + end + else if ((d_i == 8'h E6 | d_i == 8'h F6 | + d_i == 8'h EE | d_i == 8'h FE) & + rdy_i == 1'b 1 ) + begin + zw_b4 <= 8'h 01; + sig_PC <= adr_nxt_pc_i; + end + else if (d_i == 8'h E8 & rdy_i == 1'b 1 ) + begin + reg_sel_rb_out <= 2'b 01; + reg_sel_reg <= 2'b 01; + reg_sel_rb_in <= 2'b 11; + zw_b4 <= 8'h 01; + end + else if (d_i == 8'h C8 & rdy_i == 1'b 1 ) + begin + reg_sel_rb_out <= 2'b 10; + reg_sel_reg <= 2'b 10; + reg_sel_rb_in <= 2'b 11; + zw_b4 <= 8'h 01; + end + else if ((d_i == 8'h 4C | d_i == 8'h 6C | + d_i == 8'h 7C) & rdy_i == 1'b 1 ) + begin + sig_PC <= adr_nxt_pc_i; + end + else if (d_i == 8'h 20 & rdy_i == 1'b 1 ) + begin + sig_PC <= adr_nxt_pc_i; + end + else if ((d_i == 8'h A9 | d_i == 8'h A5 | + d_i == 8'h B5 | d_i == 8'h AD | + d_i == 8'h BD | d_i == 8'h B9 | + d_i == 8'h A1 | d_i == 8'h B1 | + d_i == 8'h B2) & rdy_i == 1'b 1 ) + begin + reg_sel_reg <= 2'b 00; + reg_sel_rb_in <= 2'b 11; + sig_PC <= adr_nxt_pc_i; + end + else if ((d_i == 8'h A2 | d_i == 8'h A6 | + d_i == 8'h B6 | d_i == 8'h AE | + d_i == 8'h BE) & rdy_i == 1'b 1 ) + begin + reg_sel_reg <= 2'b 01; + reg_sel_rb_in <= 2'b 11; + sig_PC <= adr_nxt_pc_i; + end + else if ((d_i == 8'h A0 | d_i == 8'h A4 | + d_i == 8'h B4 | d_i == 8'h AC | + d_i == 8'h BC) & rdy_i == 1'b 1 ) + begin + reg_sel_reg <= 2'b 10; + reg_sel_rb_in <= 2'b 11; + sig_PC <= adr_nxt_pc_i; + end + else if ((d_i == 8'h 46 | d_i == 8'h 56 | + d_i == 8'h 4E | d_i == 8'h 5E) & + rdy_i == 1'b 1 ) + begin + sig_PC <= adr_nxt_pc_i; + end + else if (d_i == 8'h EA & rdy_i == 1'b 1 ) + ; + else if (d_i == 8'h 48 & rdy_i == 1'b 1 ) + begin + reg_sel_rb_out <= 2'b 00; + sig_PC <= adr_nxt_pc_i; + end + else if (d_i == 8'h 08 & rdy_i == 1'b 1 ) + begin + sig_PC <= adr_nxt_pc_i; + end + else if (d_i == 8'h 7A & rdy_i == 1'b 1 ) + begin + reg_sel_reg <= 2'b 10; + reg_sel_rb_in <= 2'b 11; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 0; + end + else if (d_i == 8'h 28 & rdy_i == 1'b 1 ) + begin + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 0; + end + else if ((d_i == 8'h 26 | d_i == 8'h 36 | + d_i == 8'h 2E | d_i == 8'h 3E) & + rdy_i == 1'b 1 ) + begin + sig_PC <= adr_nxt_pc_i; + end + else if ((d_i == 8'h 66 | d_i == 8'h 76 | + d_i == 8'h 6E | d_i == 8'h 7E) & + rdy_i == 1'b 1 ) + begin + sig_PC <= adr_nxt_pc_i; + end + else if (d_i == 8'h 40 & rdy_i == 1'b 1 ) + begin + sig_PC <= adr_nxt_pc_i; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 0; + end + else if (d_i == 8'h 60 & rdy_i == 1'b 1 ) + begin + sig_PC <= adr_nxt_pc_i; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 0; + end + else if ((d_i == 8'h E9 | d_i == 8'h E5 | + d_i == 8'h F5 | d_i == 8'h ED | + d_i == 8'h FD | d_i == 8'h F9 | + d_i == 8'h E1 | d_i == 8'h F1 | + d_i == 8'h F2) & rdy_i == 1'b 1 ) + begin + sig_PC <= adr_nxt_pc_i; + reg_sel_reg <= 2'b 00; + reg_sel_rb_in <= 2'b 11; + zw_b1[0] <= reg_F[7]; + end + else if (d_i == 8'h 38 & rdy_i == 1'b 1 ) + ; + else if (d_i == 8'h F8 & rdy_i == 1'b 1 ) + ; + else if (d_i == 8'h 78 & rdy_i == 1'b 1 ) + ; + else if ((d_i == 8'h 85 | d_i == 8'h 95 | + d_i == 8'h 8D | d_i == 8'h 9D | + d_i == 8'h 99 | d_i == 8'h 81 | + d_i == 8'h 91) & rdy_i == 1'b 1 ) + begin + reg_sel_rb_out <= 2'b 00; + sig_PC <= adr_nxt_pc_i; + end + else if ((d_i == 8'h 86 | d_i == 8'h 96 | + d_i == 8'h 8E) & rdy_i == 1'b 1 ) + begin + reg_sel_rb_out <= 2'b 01; + sig_PC <= adr_nxt_pc_i; + end + else if ((d_i == 8'h 84 | d_i == 8'h 94 | + d_i == 8'h 8C) & rdy_i == 1'b 1 ) + begin + reg_sel_rb_out <= 2'b 10; + sig_PC <= adr_nxt_pc_i; + end + else if (d_i == 8'h AA & rdy_i == 1'b 1 ) + begin + reg_sel_rb_out <= 2'b 00; + reg_sel_reg <= 2'b 01; + reg_sel_rb_in <= 2'b 00; + reg_sel_sp_in <= 1'b 1; + reg_sel_sp_as <= 1'b 0; + end + else if (d_i == 8'h 0A & rdy_i == 1'b 1 ) + begin + reg_sel_rb_out <= 2'b 00; + reg_sel_reg <= 2'b 00; + reg_sel_rb_in <= 2'b 11; + end + else if (d_i == 8'h 4A & rdy_i == 1'b 1 ) + begin + reg_sel_rb_out <= 2'b 00; + reg_sel_reg <= 2'b 00; + reg_sel_rb_in <= 2'b 11; + end + else if (d_i == 8'h 2A & rdy_i == 1'b 1 ) + begin + reg_sel_rb_out <= 2'b 00; + reg_sel_reg <= 2'b 00; + reg_sel_rb_in <= 2'b 11; + end + else if (d_i == 8'h 6A & rdy_i == 1'b 1 ) + begin + reg_sel_rb_out <= 2'b 00; + reg_sel_reg <= 2'b 00; + reg_sel_rb_in <= 2'b 11; + end + else if (d_i == 8'h A8 & rdy_i == 1'b 1 ) + begin + reg_sel_rb_out <= 2'b 00; + reg_sel_reg <= 2'b 10; + reg_sel_rb_in <= 2'b 00; + reg_sel_sp_in <= 1'b 1; + reg_sel_sp_as <= 1'b 0; + end + else if (d_i == 8'h 98 & rdy_i == 1'b 1 ) + begin + reg_sel_rb_out <= 2'b 10; + reg_sel_reg <= 2'b 00; + reg_sel_rb_in <= 2'b 01; + reg_sel_sp_in <= 1'b 1; + reg_sel_sp_as <= 1'b 0; + end + else if (d_i == 8'h BA & rdy_i == 1'b 1 ) + begin + reg_sel_rb_out <= 2'b 01; + reg_sel_reg <= 2'b 01; + reg_sel_rb_in <= 2'b 11; + reg_sel_sp_in <= 1'b 1; + reg_sel_sp_as <= 1'b 0; + end + else if (d_i == 8'h 8A & rdy_i == 1'b 1 ) + begin + reg_sel_rb_out <= 2'b 01; + reg_sel_reg <= 2'b 00; + reg_sel_rb_in <= 2'b 10; + reg_sel_sp_in <= 1'b 1; + reg_sel_sp_as <= 1'b 0; + end + else if (d_i == 8'h 9A & rdy_i == 1'b 1 ) + begin + reg_sel_rb_out <= 2'b 01; + reg_sel_reg <= 2'b 11; + reg_sel_rb_in <= 2'b 11; + reg_sel_sp_in <= 1'b 1; + reg_sel_sp_as <= 1'b 0; + end + else if (d_i == 8'h DA & rdy_i == 1'b 1 ) + begin + reg_sel_rb_out <= 2'b 01; + sig_PC <= adr_nxt_pc_i; + end + else if (d_i == 8'h 5A & rdy_i == 1'b 1 ) + begin + reg_sel_rb_out <= 2'b 10; + sig_PC <= adr_nxt_pc_i; + end + else if (d_i == 8'h 68 & rdy_i == 1'b 1 ) + begin + reg_sel_reg <= 2'b 00; + reg_sel_rb_in <= 2'b 11; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 0; + end + else if (d_i == 8'h FA & rdy_i == 1'b 1 ) + begin + reg_sel_reg <= 2'b 01; + reg_sel_rb_in <= 2'b 11; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 0; + end + else if ((d_i == 8'h 9C | d_i == 8'h 9E | + d_i == 8'h 64 | d_i == 8'h 74) & + rdy_i == 1'b 1 ) + begin + reg_sel_rb_out <= 2'b 11; + sig_PC <= adr_nxt_pc_i; + end + else if (d_i == 8'h 3A & rdy_i == 1'b 1 ) + begin + reg_sel_rb_out <= 2'b 00; + reg_sel_reg <= 2'b 00; + reg_sel_rb_in <= 2'b 11; + zw_b4 <= 8'h FF; + end + else if (d_i == 8'h 1A & rdy_i == 1'b 1 ) + begin + reg_sel_rb_out <= 2'b 00; + reg_sel_reg <= 2'b 00; + reg_sel_rb_in <= 2'b 11; + zw_b4 <= 8'h 01; + end + end + G1_1: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_pc_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G2_1: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_pc_i; + reg_F[0] <= 1'b 1; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G3_1: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_pc_i; + reg_F[3] <= 1'b 1; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G4_1: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_pc_i; + reg_F[2] <= 1'b 1; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G9_1: + begin + if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 9A) + begin + sig_PC <= adr_pc_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h BA ) + begin + sig_PC <= adr_pc_i; + reg_F[7] <= reg_7flag_i; + reg_F[1] <= reg_1flag_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 ) + begin + sig_PC <= adr_pc_i; + reg_F[7] <= reg_7flag_i; + reg_F[1] <= reg_1flag_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G5_1: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_pc_i; + reg_F[0] <= 1'b 0; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G6_1: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_pc_i; + reg_F[3] <= 1'b 0; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G7_1: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_pc_i; + reg_F[2] <= 1'b 0; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G8_1: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_pc_i; + reg_F[6] <= 1'b 0; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G19_1: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_pc_i; + reg_F[7] <= reg_7flag_i; + reg_F[1] <= reg_1flag_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G15_1: + begin + if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A5 | + zw_REG_OP == 8'h A6 | zw_REG_OP == 8'h A4 | + zw_REG_OP == 8'h 45 | zw_REG_OP == 8'h 05 | + zw_REG_OP == 8'h 25 | zw_REG_OP == 8'h C5 | + zw_REG_OP == 8'h E4 | zw_REG_OP == 8'h C4)) + begin + sig_PC <= {8'h 00, d_i}; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 | + zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 | + zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 | + zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 | + zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) & + (zw_REG_OP == 8'h 09 | zw_REG_OP == 8'h 05 | + zw_REG_OP == 8'h 15 | zw_REG_OP == 8'h 0D | + zw_REG_OP == 8'h 1D | zw_REG_OP == 8'h 19 | + zw_REG_OP == 8'h 01 | zw_REG_OP == 8'h 11 | + zw_REG_OP == 8'h 12) ) + begin + sig_PC <= adr_nxt_pc_i; + reg_F[7] <= reg_7flag_i; + reg_F[1] <= reg_1flag_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 | + zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 | + zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 | + zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 | + zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) & + (zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 45 | + zw_REG_OP == 8'h 55 | zw_REG_OP == 8'h 4D | + zw_REG_OP == 8'h 5D | zw_REG_OP == 8'h 59 | + zw_REG_OP == 8'h 41 | zw_REG_OP == 8'h 51 | + zw_REG_OP == 8'h 52) ) + begin + sig_PC <= adr_nxt_pc_i; + reg_F[7] <= reg_7flag_i; + reg_F[1] <= reg_1flag_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 | + zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 | + zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 | + zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 | + zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) & + (zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h 25 | + zw_REG_OP == 8'h 35 | zw_REG_OP == 8'h 2D | + zw_REG_OP == 8'h 3D | zw_REG_OP == 8'h 39 | + zw_REG_OP == 8'h 21 | zw_REG_OP == 8'h 31 | + zw_REG_OP == 8'h 32 | zw_REG_OP == 8'h D2) ) + begin + sig_PC <= adr_nxt_pc_i; + reg_F[7] <= reg_7flag_i; + reg_F[1] <= reg_1flag_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 | + zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 | + zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 | + zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 | + zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) & + (zw_REG_OP == 8'h C9 | zw_REG_OP == 8'h C5 | + zw_REG_OP == 8'h D5 | zw_REG_OP == 8'h CD | + zw_REG_OP == 8'h DD | zw_REG_OP == 8'h D9 | + zw_REG_OP == 8'h C1 | zw_REG_OP == 8'h D1 | + zw_REG_OP == 8'h C0 | zw_REG_OP == 8'h E0 | + zw_REG_OP == 8'h C4 | zw_REG_OP == 8'h E4 | + zw_REG_OP == 8'h CC | zw_REG_OP == 8'h EC) ) + begin + sig_PC <= adr_nxt_pc_i; + reg_F[7] <= zw_ALU[7]; + reg_F[0] <= zw_ALU[8]; + reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] | + zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]); + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 | + zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 | + zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 | + zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 | + zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) ) + begin + sig_PC <= adr_nxt_pc_i; + reg_F[7] <= reg_7flag_i; + reg_F[1] <= reg_1flag_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h B5 | + zw_REG_OP == 8'h B4 | zw_REG_OP == 8'h 55 | + zw_REG_OP == 8'h 15 | zw_REG_OP == 8'h 35 | + zw_REG_OP == 8'h D5) ) + begin + sig_PC <= {8'h 00, d_i}; + zw_b1 <= d_alu_i; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h AD | + zw_REG_OP == 8'h AE | zw_REG_OP == 8'h AC | + zw_REG_OP == 8'h 4D | zw_REG_OP == 8'h 0D | + zw_REG_OP == 8'h 2D | zw_REG_OP == 8'h CD | + zw_REG_OP == 8'h EC | zw_REG_OP == 8'h CC) ) + begin + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h BD | + zw_REG_OP == 8'h BC | zw_REG_OP == 8'h 5D | + zw_REG_OP == 8'h 1D | zw_REG_OP == 8'h 3D | + zw_REG_OP == 8'h DD) ) + begin + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2[0] <= reg_0flag_i; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h B9 | + zw_REG_OP == 8'h BE | zw_REG_OP == 8'h 59 | + zw_REG_OP == 8'h 19 | zw_REG_OP == 8'h 39 | + zw_REG_OP == 8'h D9) ) + begin + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2[0] <= reg_0flag_i; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h B1 | + zw_REG_OP == 8'h 51 | zw_REG_OP == 8'h 11 | + zw_REG_OP == 8'h 31 | zw_REG_OP == 8'h D1) ) + begin + sig_PC <= {8'h 00, d_i}; + zw_b1 <= d_alu_i; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A1 | + zw_REG_OP == 8'h 41 | zw_REG_OP == 8'h 01 | + zw_REG_OP == 8'h 21 | zw_REG_OP == 8'h C1) ) + begin + sig_PC <= {8'h 00, d_i}; + zw_b1 <= d_alu_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h B6 ) + begin + sig_PC <= {8'h 00, d_i}; + zw_b1 <= d_alu_i; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 32 | + zw_REG_OP == 8'h D2 | zw_REG_OP == 8'h 52 | + zw_REG_OP == 8'h B2 | zw_REG_OP == 8'h 12) ) + begin + sig_PC <= {8'h 00, d_i}; + zw_b1 <= d_alu_i; + end + end + G15_3: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_b1}; + end + end + G15_4: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_b1}; + zw_b3 <= d_alu_i; + end + end + G15_5: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {8'h 00, zw_b1}; + zw_b1 <= d_alu_i; + zw_b2[0] <= reg_0flag_i; + end + end + G15_2: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {8'h 00, zw_b1}; + end + end + G15_7: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {8'h 00, zw_b1}; + end + end + G15_e3: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {8'h 00, d_alu_i}; + zw_b1 <= d_i; + end + end + G15_6: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_b1}; + zw_b3 <= d_alu_i; + end + end + G15_e2: + begin + if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 09 | + zw_REG_OP == 8'h 05 | zw_REG_OP == 8'h 15 | + zw_REG_OP == 8'h 0D | zw_REG_OP == 8'h 1D | + zw_REG_OP == 8'h 19 | zw_REG_OP == 8'h 01 | + zw_REG_OP == 8'h 11 | zw_REG_OP == 8'h 12)) + begin + sig_PC <= adr_pc_i; + reg_F[7] <= reg_7flag_i; + reg_F[1] <= reg_1flag_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 49 | + zw_REG_OP == 8'h 45 | zw_REG_OP == 8'h 55 | + zw_REG_OP == 8'h 4D | zw_REG_OP == 8'h 5D | + zw_REG_OP == 8'h 59 | zw_REG_OP == 8'h 41 | + zw_REG_OP == 8'h 51 | zw_REG_OP == 8'h 52) ) + begin + sig_PC <= adr_pc_i; + reg_F[7] <= reg_7flag_i; + reg_F[1] <= reg_1flag_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 29 | + zw_REG_OP == 8'h 25 | zw_REG_OP == 8'h 35 | + zw_REG_OP == 8'h 2D | zw_REG_OP == 8'h 3D | + zw_REG_OP == 8'h 39 | zw_REG_OP == 8'h 21 | + zw_REG_OP == 8'h 31 | zw_REG_OP == 8'h 32 | + zw_REG_OP == 8'h D2) ) + begin + sig_PC <= adr_pc_i; + reg_F[7] <= reg_7flag_i; + reg_F[1] <= reg_1flag_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h C9 | + zw_REG_OP == 8'h C5 | zw_REG_OP == 8'h D5 | + zw_REG_OP == 8'h CD | zw_REG_OP == 8'h DD | + zw_REG_OP == 8'h D9 | zw_REG_OP == 8'h C1 | + zw_REG_OP == 8'h D1 | zw_REG_OP == 8'h C0 | + zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C4 | + zw_REG_OP == 8'h E4 | zw_REG_OP == 8'h CC | + zw_REG_OP == 8'h EC) ) + begin + sig_PC <= adr_pc_i; + reg_F[7] <= zw_ALU[7]; + reg_F[0] <= zw_ALU[8]; + reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] | + zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]); + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 ) + begin + sig_PC <= adr_pc_i; + reg_F[7] <= reg_7flag_i; + reg_F[1] <= reg_1flag_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G15_e1: + begin + if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 & + (zw_REG_OP == 8'h 09 | zw_REG_OP == 8'h 05 | + zw_REG_OP == 8'h 15 | zw_REG_OP == 8'h 0D | + zw_REG_OP == 8'h 1D | zw_REG_OP == 8'h 19 | + zw_REG_OP == 8'h 01 | zw_REG_OP == 8'h 11 | + zw_REG_OP == 8'h 12)) + begin + sig_PC <= adr_pc_i; + reg_F[7] <= reg_7flag_i; + reg_F[1] <= reg_1flag_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 & + (zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 45 | + zw_REG_OP == 8'h 55 | zw_REG_OP == 8'h 4D | + zw_REG_OP == 8'h 5D | zw_REG_OP == 8'h 59 | + zw_REG_OP == 8'h 41 | zw_REG_OP == 8'h 51 | + zw_REG_OP == 8'h 52) ) + begin + sig_PC <= adr_pc_i; + reg_F[7] <= reg_7flag_i; + reg_F[1] <= reg_1flag_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 & + (zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h 25 | + zw_REG_OP == 8'h 35 | zw_REG_OP == 8'h 2D | + zw_REG_OP == 8'h 3D | zw_REG_OP == 8'h 39 | + zw_REG_OP == 8'h 21 | zw_REG_OP == 8'h 31 | + zw_REG_OP == 8'h 32 | zw_REG_OP == 8'h D2) ) + begin + sig_PC <= adr_pc_i; + reg_F[7] <= reg_7flag_i; + reg_F[1] <= reg_1flag_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 & + (zw_REG_OP == 8'h C9 | zw_REG_OP == 8'h C5 | + zw_REG_OP == 8'h D5 | zw_REG_OP == 8'h CD | + zw_REG_OP == 8'h DD | zw_REG_OP == 8'h D9 | + zw_REG_OP == 8'h C1 | zw_REG_OP == 8'h D1 | + zw_REG_OP == 8'h C0 | zw_REG_OP == 8'h E0 | + zw_REG_OP == 8'h C4 | zw_REG_OP == 8'h E4 | + zw_REG_OP == 8'h CC | zw_REG_OP == 8'h EC) ) + begin + sig_PC <= adr_pc_i; + reg_F[7] <= zw_ALU[7]; + reg_F[0] <= zw_ALU[8]; + reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] | + zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]); + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 ) + begin + sig_PC <= adr_pc_i; + reg_F[7] <= reg_7flag_i; + reg_F[1] <= reg_1flag_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 ) + begin + sig_PC <= {zw_b3, zw_b1}; + end + end + G15_8: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {8'h 00, zw_b1}; + zw_b1 <= d_i; + end + end + G10_1: + begin + if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 65) + begin + sig_PC <= {8'h 00, d_i}; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 69 & + reg_F[3] == 1'b 0 ) + begin + sig_PC <= adr_nxt_pc_i; + reg_F[7] <= zw_ALU[7]; + reg_F[6] <= zw_b1[0] ^ zw_ALU[7]; + reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] | + zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]); + reg_F[0] <= zw_ALU[8]; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 75 ) + begin + sig_PC <= {8'h 00, d_i}; + zw_b1 <= d_alu_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 6D ) + begin + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 7D ) + begin + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2[0] <= reg_0flag_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 79 ) + begin + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2[0] <= reg_0flag_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 71 ) + begin + sig_PC <= {8'h 00, d_i}; + zw_b1 <= d_alu_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 61 ) + begin + sig_PC <= {8'h 00, d_i}; + zw_b1 <= d_alu_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 69 & + reg_F[3] == 1'b 1 ) + begin + sig_PC <= adr_nxt_pc_i; + reg_F[7] <= zw_ALU[7]; + reg_F[6] <= zw_b1[0] ^ zw_ALU[7]; + reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] | + zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]); + reg_F[0] <= zw_ALU4[4]; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 72 ) + begin + sig_PC <= {8'h 00, d_i}; + zw_b1 <= d_alu_i; + end + end + G10_3: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_b1}; + end + end + G10_4: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_b1}; + zw_b3 <= d_alu_i; + end + end + G10_5: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {8'h 00, zw_b1}; + zw_b1 <= d_alu_i; + zw_b2[0] <= reg_0flag_i; + end + end + G10_2: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {8'h 00, zw_b1}; + end + end + G10_7: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {8'h 00, zw_b1}; + end + end + G10_e3: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {8'h 00, d_alu_i}; + zw_b1 <= d_i; + end + end + G10_e1: + begin + if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 & + reg_F[3] == 1'b 0) + begin + sig_PC <= adr_pc_i; + reg_F[7] <= zw_ALU[7]; + reg_F[6] <= zw_b1[0] ^ zw_ALU[7]; + reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] | + zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]); + reg_F[0] <= zw_ALU[8]; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 & + reg_F[3] == 1'b 1 ) + begin + sig_PC <= adr_pc_i; + reg_F[7] <= zw_ALU[7]; + reg_F[6] <= zw_b1[0] ^ zw_ALU[7]; + reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] | + zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]); + reg_F[0] <= zw_ALU4[4]; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 ) + begin + sig_PC <= {zw_b3, zw_b1}; + end + end + G10_e2: + begin + if (rdy_i == 1'b 1 & reg_F[3] == 1'b 0) + begin + sig_PC <= adr_pc_i; + reg_F[7] <= zw_ALU[7]; + reg_F[6] <= zw_b1[0] ^ zw_ALU[7]; + reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] | + zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]); + reg_F[0] <= zw_ALU[8]; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 & reg_F[3] == 1'b 1 ) + begin + sig_PC <= adr_pc_i; + reg_F[7] <= zw_ALU[7]; + reg_F[6] <= zw_b1[0] ^ zw_ALU[7]; + reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] | + zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]); + reg_F[0] <= zw_ALU4[4]; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G10_6: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_b1}; + zw_b3 <= d_alu_i; + end + end + G10_8: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {8'h 00, zw_b1}; + zw_b1 <= d_i; + end + end + G17_1: + begin + if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 85 | + zw_REG_OP == 8'h 86 | zw_REG_OP == 8'h 64 | + zw_REG_OP == 8'h 84)) + begin + sig_PC <= {8'h 00, d_i}; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 95 | + zw_REG_OP == 8'h 74 | zw_REG_OP == 8'h 94) ) + begin + sig_PC <= {8'h 00, d_i}; + zw_b1 <= d_alu_i; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 8D | + zw_REG_OP == 8'h 8E | zw_REG_OP == 8'h 9C | + zw_REG_OP == 8'h 8C) ) + begin + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 9D | + zw_REG_OP == 8'h 9E) ) + begin + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2[0] <= reg_0flag_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 99 ) + begin + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2[0] <= reg_0flag_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 91 ) + begin + sig_PC <= {8'h 00, d_i}; + zw_b1 <= d_alu_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 81 ) + begin + sig_PC <= {8'h 00, d_i}; + zw_b1 <= d_alu_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 96 ) + begin + sig_PC <= {8'h 00, d_i}; + zw_b1 <= d_alu_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 92 ) + begin + sig_PC <= {8'h 00, d_i}; + zw_b1 <= d_alu_i; + end + end + G17_4: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_b1}; + zw_b3 <= d_alu_i; + end + end + G17_6: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {8'h 00, zw_b1}; + zw_b1 <= d_alu_i; + zw_b2[0] <= reg_0flag_i; + end + end + G17_3: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_b1}; + end + end + G17_2: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {8'h 00, zw_b1}; + end + end + G17_8: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {8'h 00, zw_b1}; + end + end + G17_9: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {8'h 00, d_alu_i}; + zw_b1 <= d_i; + end + end + G17_7: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_b1}; + zw_b3 <= d_alu_i; + end + end + G17_5: + begin + sig_PC <= {zw_b3, zw_b1}; + end + G17_10: + begin + sig_PC <= {d_i, zw_b1}; + end + G17_e: + begin + sig_PC <= adr_pc_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + G17_11: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {8'h 00, zw_b1}; + zw_b1 <= d_i; + end + end + G16_1: + begin + if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E5) + begin + sig_PC <= {8'h 00, d_i}; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E9 & + reg_F[3] == 1'b 0 ) + begin + sig_PC <= adr_nxt_pc_i; + reg_F[7] <= zw_ALU[7]; + reg_F[6] <= zw_b1[0] ^ zw_ALU[7]; + reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] | + zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]); + reg_F[0] <= zw_ALU[8]; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F5 ) + begin + sig_PC <= {8'h 00, d_i}; + zw_b1 <= d_alu_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h ED ) + begin + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h FD ) + begin + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2[0] <= reg_0flag_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F9 ) + begin + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2[0] <= reg_0flag_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F1 ) + begin + sig_PC <= {8'h 00, d_i}; + zw_b1 <= d_alu_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E1 ) + begin + sig_PC <= {8'h 00, d_i}; + zw_b1 <= d_alu_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E9 & + reg_F[3] == 1'b 1 ) + begin + sig_PC <= adr_nxt_pc_i; + reg_F[7] <= zw_ALU[7]; + reg_F[6] <= zw_b1[0] ^ zw_ALU[7]; + reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] | + zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]); + reg_F[0] <= zw_ALU2[4]; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F2 ) + begin + sig_PC <= {8'h 00, d_i}; + zw_b1 <= d_alu_i; + end + end + G16_3: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_b1}; + end + end + G16_4: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_b1}; + zw_b3 <= d_alu_i; + end + end + G16_5: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {8'h 00, zw_b1}; + zw_b1 <= d_alu_i; + zw_b2[0] <= reg_0flag_i; + end + end + G16_2: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {8'h 00, zw_b1}; + end + end + G16_7: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {8'h 00, zw_b1}; + end + end + G16_6: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_b1}; + zw_b3 <= d_alu_i; + end + end + G16_e3: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {8'h 00, d_alu_i}; + zw_b1 <= d_i; + end + end + G16_e1: + begin + if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 & + reg_F[3] == 1'b 0) + begin + sig_PC <= adr_pc_i; + reg_F[7] <= zw_ALU[7]; + reg_F[6] <= zw_b1[0] ^ zw_ALU[7]; + reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] | + zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]); + reg_F[0] <= zw_ALU[8]; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 & + reg_F[3] == 1'b 1 ) + begin + sig_PC <= adr_pc_i; + reg_F[7] <= zw_ALU[7]; + reg_F[6] <= zw_b1[0] ^ zw_ALU[7]; + reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] | + zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]); + reg_F[0] <= zw_ALU2[4]; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 ) + begin + sig_PC <= {zw_b3, zw_b1}; + end + end + G16_e2: + begin + if (rdy_i == 1'b 1 & reg_F[3] == 1'b 0) + begin + sig_PC <= adr_pc_i; + reg_F[7] <= zw_ALU[7]; + reg_F[6] <= zw_b1[0] ^ zw_ALU[7]; + reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] | + zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]); + reg_F[0] <= zw_ALU[8]; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 & reg_F[3] == 1'b 1 ) + begin + sig_PC <= adr_pc_i; + reg_F[7] <= zw_ALU[7]; + reg_F[6] <= zw_b1[0] ^ zw_ALU[7]; + reg_F[1] <= ~(zw_ALU[7] | zw_ALU[6] | zw_ALU[5] | zw_ALU[4] | + zw_ALU[3] | zw_ALU[2] | zw_ALU[1] | zw_ALU[0]); + reg_F[0] <= zw_ALU2[4]; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G16_8: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {8'h 00, zw_b1}; + zw_b1 <= d_i; + end + end + G11_1: + begin + if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 1E | + zw_REG_OP == 8'h 7E | zw_REG_OP == 8'h 3E | + zw_REG_OP == 8'h 5E)) + begin + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2[0] <= reg_0flag_i; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 06 | + zw_REG_OP == 8'h 66 | zw_REG_OP == 8'h 26 | + zw_REG_OP == 8'h 46 | zw_REG_OP == 8'h 04 | + zw_REG_OP == 8'h 14) ) + begin + sig_PC <= {8'h 00, d_i}; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 16 | + zw_REG_OP == 8'h 76 | zw_REG_OP == 8'h 36 | + zw_REG_OP == 8'h 56) ) + begin + sig_PC <= {8'h 00, d_i}; + zw_b1 <= d_alu_i; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 0E | + zw_REG_OP == 8'h 6E | zw_REG_OP == 8'h 2E | + zw_REG_OP == 8'h 4E | zw_REG_OP == 8'h 0C | + zw_REG_OP == 8'h 1C) ) + begin + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP[3:0] == 4'h 7 ) + begin + sig_PC <= {8'h 00, d_i}; + end + end + G11_5: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_b1}; + end + end + G11_6: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_b1}; + zw_b3 <= d_alu_i; + end + end + G11_2: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {8'h 00, zw_b1}; + end + end + G11_7: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {zw_b3, zw_b1}; + end + end + G11_4: + begin + if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 06 | + zw_REG_OP == 8'h 16 | zw_REG_OP == 8'h 0E | + zw_REG_OP == 8'h 1E)) + begin + zw_b1 <= {d_i[6:0], 1'b 0}; + zw_b2[0] <= d_i[7]; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 46 | + zw_REG_OP == 8'h 56 | zw_REG_OP == 8'h 4E | + zw_REG_OP == 8'h 5E) ) + begin + zw_b1 <= {1'b 0, d_i[7:1]}; + zw_b2[0] <= d_i[0]; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 26 | + zw_REG_OP == 8'h 36 | zw_REG_OP == 8'h 2E | + zw_REG_OP == 8'h 3E) ) + begin + zw_b1 <= {d_i[6:0], reg_F[0]}; + zw_b2[0] <= d_i[7]; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 66 | + zw_REG_OP == 8'h 76 | zw_REG_OP == 8'h 6E | + zw_REG_OP == 8'h 7E) ) + begin + zw_b1 <= {reg_F[0], d_i[7:1]}; + zw_b2[0] <= d_i[0]; + end + else if (rdy_i == 1'b 1 & zw_REG_OP[7] == 1'b 0 & + zw_REG_OP[3:0] == 4'h 7 ) + ; + else if (rdy_i == 1'b 1 & zw_REG_OP[7] == 1'b 1 & + zw_REG_OP[3:0] == 4'h 7 ) + ; + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 14 | + zw_REG_OP == 8'h 1C) ) + begin + zw_b1 <= d_i & q_a_i; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 04 | + zw_REG_OP == 8'h 0C) ) + begin + zw_b1 <= d_i & q_a_i; + end + end + G11_e: + begin + if (zw_REG_OP[3:0] == 4'h 7) + begin + sig_PC <= adr_pc_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (zw_REG_OP == 8'h 14 | zw_REG_OP == 8'h 04 | + zw_REG_OP == 8'h 0C | zw_REG_OP == 8'h 1C ) + begin + reg_F[1] <= reg_1flag_i; + sig_PC <= adr_pc_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else + begin + reg_F[0] <= zw_b2[0]; + reg_F[7] <= reg_7flag_i; + reg_F[1] <= reg_1flag_i; + sig_PC <= adr_pc_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G31_1: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_pc_i; + reg_F[0] <= q_a_i[7]; + reg_F[7] <= reg_7flag_i; + reg_F[1] <= reg_1flag_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G34_1: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_pc_i; + reg_F[0] <= q_a_i[0]; + reg_F[7] <= reg_7flag_i; + reg_F[1] <= reg_1flag_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G32_1: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_pc_i; + reg_F[0] <= q_a_i[0]; + reg_F[7] <= reg_7flag_i; + reg_F[1] <= reg_1flag_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G33_1: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_pc_i; + reg_F[0] <= q_a_i[7]; + reg_F[0] <= q_a_i[7]; + reg_F[7] <= reg_7flag_i; + reg_F[1] <= reg_1flag_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G12_1: + begin + if (rdy_i == 1'b 1 & (reg_F[0] == 1'b 1 & + zw_REG_OP == 8'h 90 | reg_F[0] == 1'b 0 & + zw_REG_OP == 8'h B0 | reg_F[1] == 1'b 0 & + zw_REG_OP == 8'h F0 | reg_F[7] == 1'b 0 & + zw_REG_OP == 8'h 30 | reg_F[1] == 1'b 1 & + zw_REG_OP == 8'h D0 | reg_F[7] == 1'b 1 & + zw_REG_OP == 8'h 10 | reg_F[6] == 1'b 1 & + zw_REG_OP == 8'h 50 | reg_F[6] == 1'b 0 & + zw_REG_OP == 8'h 70)) + begin + sig_PC <= adr_nxt_pc_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 8F | + zw_REG_OP == 8'h 9F | zw_REG_OP == 8'h AF | + zw_REG_OP == 8'h BF | zw_REG_OP == 8'h CF | + zw_REG_OP == 8'h DF | zw_REG_OP == 8'h EF | + zw_REG_OP == 8'h FF | zw_REG_OP == 8'h 0F | + zw_REG_OP == 8'h 1F | zw_REG_OP == 8'h 2F | + zw_REG_OP == 8'h 3F | zw_REG_OP == 8'h 4F | + zw_REG_OP == 8'h 5F | zw_REG_OP == 8'h 6F | + zw_REG_OP == 8'h 7F) ) + begin + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + end + else if (rdy_i == 1'b 1 ) + begin + sig_PC <= adr_nxt_pc_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 10; + zw_b2 <= d_i; + end + end + G12_e1: + begin + if (rdy_i == 1'b 1 & zw_b3 == adr_nxt_pc_i[15:8]) + begin + sig_PC <= adr_nxt_pc_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 ) + begin + sig_PC <= {zw_b3, adr_nxt_pc_i[7:0]}; + end + end + G12_e2: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_pc_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G12_2: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {8'h 00, zw_b1}; + zw_b2 <= d_i; + end + end + G12_3: + begin + if (rdy_i == 1'b 1 & (d_i[0] == 1'b 1 & + zw_REG_OP == 8'h 8F | d_i[1] == 1'b 1 & + zw_REG_OP == 8'h 9F | d_i[2] == 1'b 1 & + zw_REG_OP == 8'h AF | d_i[3] == 1'b 1 & + zw_REG_OP == 8'h BF | d_i[4] == 1'b 1 & + zw_REG_OP == 8'h CF | d_i[5] == 1'b 1 & + zw_REG_OP == 8'h DF | d_i[6] == 1'b 1 & + zw_REG_OP == 8'h EF | d_i[7] == 1'b 1 & + zw_REG_OP == 8'h FF | d_i[0] == 1'b 0 & + zw_REG_OP == 8'h 0F | d_i[1] == 1'b 0 & + zw_REG_OP == 8'h 1F | d_i[2] == 1'b 0 & + zw_REG_OP == 8'h 2F | d_i[3] == 1'b 0 & + zw_REG_OP == 8'h 3F | d_i[4] == 1'b 0 & + zw_REG_OP == 8'h 4F | d_i[5] == 1'b 0 & + zw_REG_OP == 8'h 5F | d_i[6] == 1'b 0 & + zw_REG_OP == 8'h 6F | d_i[7] == 1'b 0 & + zw_REG_OP == 8'h 7F)) + begin + sig_PC <= adr_nxt_pc_i; + end + else if (rdy_i == 1'b 1 ) + begin + sig_PC <= adr_nxt_pc_i; + end + end + G12_4: + begin + if (rdy_i == 1'b 1) + begin + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 10; + end + end + G20_1: + begin + if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 4C) + begin + sig_PC <= adr_nxt_pc_i; + reg_sel_pc_in <= 1'b 1; + reg_sel_pc_val <= 2'b 11; + zw_b1 <= d_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 6C ) + begin + sig_PC <= adr_nxt_pc_i; + reg_sel_pc_in <= 1'b 1; + reg_sel_pc_val <= 2'b 00; + zw_b1 <= d_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 7C ) + begin + sig_PC <= adr_nxt_pc_i; + reg_sel_pc_in <= 1'b 1; + reg_sel_pc_val <= 2'b 10; + zw_b1 <= d_i; + end + end + G20_2: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_b1}; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + end + end + G20_5: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_pc_i; + reg_sel_pc_in <= 1'b 1; + reg_sel_pc_val <= 2'b 11; + zw_b1 <= d_i; + end + end + G20_e: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_b1}; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G20_3: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_nxt_pc_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + end + end + G21_1: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_sp_i; + zw_b1 <= d_i; + end + end + G21_3: + begin + sig_PC <= adr_sp_i; + end + G21_4: + begin + sig_PC <= adr_pc_i; + reg_sel_pc_in <= 1'b 1; + reg_sel_pc_val <= 2'b 11; + end + G21_e: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_b1[7:0]}; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G13_3: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_b1}; + end + end + G13_1: + begin + if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 34) + begin + sig_PC <= {8'h 00, d_i}; + zw_b1 <= d_alu_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 3C ) + begin + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2[0] <= reg_0flag_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 24 ) + begin + sig_PC <= {8'h 00, d_i}; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 2C ) + begin + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 89 ) + begin + sig_PC <= adr_nxt_pc_i; + reg_F[1] <= reg_1flag_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G13_4: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_b1}; + zw_b3 <= d_alu_i; + end + end + G13_2: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {8'h 00, zw_b1}; + end + end + G13_e1: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_pc_i; + reg_F[7] <= d_i[7]; + reg_F[6] <= d_i[6]; + reg_F[1] <= reg_1flag_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G13_e2: + begin + if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0) + begin + sig_PC <= adr_pc_i; + reg_F[7] <= d_i[7]; + reg_F[6] <= d_i[6]; + reg_F[1] <= reg_1flag_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + else if (rdy_i == 1'b 1 ) + begin + sig_PC <= {zw_b3, zw_b1}; + end + end + G18_1: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_sp_i; + end + end + G18_2: + begin + sig_PC <= adr_sp_i; + end + G18_3: + begin + sig_PC <= adr_sp_i; + end + G18_4: + begin + sig_PC <= 16'h FFFE; + end + G18_e: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_b1}; + reg_F[2] <= 1'b 1; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G18_5: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= 16'h FFFF; + reg_sel_pc_in <= 1'b 1; + reg_sel_pc_val <= 2'b 11; + zw_b1 <= d_i; + end + end + G26_1: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_sp_i; + end + end + G26_2: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_sp_i; + end + end + G26_3: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_sp_i; + reg_F <= d_i; + reg_sel_pc_in <= 1'b 1; + reg_sel_pc_val <= 2'b 11; + end + end + G26_4: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_sp_i; + zw_b1 <= d_i; + end + end + G26_e: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_b1}; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G27_1: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_sp_i; + end + end + G27_2: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_sp_i; + end + end + G27_3: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_sp_i; + zw_b1 <= d_i; + reg_sel_pc_in <= 1'b 1; + reg_sel_pc_val <= 2'b 00; + end + end + G27_4: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_b1}; + end + end + G27_e: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_pc_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G14_1: + begin + if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h C6 | + zw_REG_OP == 8'h E6)) + begin + sig_PC <= {8'h 00, d_i}; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h D6 | + zw_REG_OP == 8'h F6) ) + begin + sig_PC <= {8'h 00, d_i}; + zw_b1 <= d_alu_i; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h CE | + zw_REG_OP == 8'h EE) ) + begin + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h DE | + zw_REG_OP == 8'h FE) ) + begin + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2[0] <= reg_0flag_i; + end + end + G14_5: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_b1}; + end + end + G14_6: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {d_i, zw_b1}; + zw_b3 <= d_alu_i; + end + end + G14_2: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {8'h 00, zw_b1}; + end + end + G14_7: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= {zw_b3, zw_b1}; + end + end + G14_3: + begin + if (rdy_i == 1'b 1) + begin + zw_b1 <= d_alu_i; + end + end + G14_e: + begin + reg_F[7] <= reg_7flag_i; + reg_F[1] <= reg_1flag_i; + sig_PC <= adr_pc_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + G22_1: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_sp_i; + end + end + G22_e: + begin + sig_PC <= adr_pc_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + G23_1: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_sp_i; + end + end + G23_e: + begin + sig_PC <= adr_pc_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + G24_2: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_sp_i; + end + end + G24_e: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_pc_i; + reg_F[7] <= reg_7flag_i; + reg_F[1] <= reg_1flag_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + G25_2: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_sp_i; + end + end + G25_e: + begin + if (rdy_i == 1'b 1) + begin + sig_PC <= adr_pc_i; + reg_F <= d_i; + reg_sel_pc_in <= 1'b 0; + reg_sel_pc_val <= 2'b 00; + reg_sel_sp_in <= 1'b 0; + reg_sel_sp_as <= 1'b 1; + end + end + default: + ; + endcase + end + end + +// --------------------------------------------------------------- + +// --------------------------------------------------------------- + +always @(adr_nxt_pc_i or current_state or d_i or irq_n_i or rdy_i + or reg_F or zw_REG_NMI or zw_REG_OP or zw_b2 or zw_b3) + begin : nextstate_proc + case (current_state) + G30_1: + begin + next_state <= G30_2; + end + G30_3: + begin + next_state <= G30_4; + end + G30_4: + begin + next_state <= G30_5; + end + G30_5: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G30_e; + end + else + begin + next_state <= G30_5; + end + end + G30_e: + begin + if (rdy_i == 1'b 1) + begin + next_state <= FETCH; + end + else + begin + next_state <= G30_e; + end + end + G30_2: + begin + next_state <= G30_3; + end + RES: + begin + next_state <= G30_1; + end + G28_1: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G28_2; + end + else + begin + next_state <= G28_1; + end + end + G28_2: + begin + next_state <= G28_3; + end + G28_3: + begin + next_state <= G28_4; + end + G28_5: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G28_e; + end + else + begin + next_state <= G28_5; + end + end + G28_4: + begin + next_state <= G28_5; + end + G28_e: + begin + if (rdy_i == 1'b 1) + begin + next_state <= FETCH; + end + else + begin + next_state <= G28_e; + end + end + G29_1: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G29_2; + end + else + begin + next_state <= G29_1; + end + end + G29_2: + begin + next_state <= G29_3; + end + G29_3: + begin + next_state <= G29_4; + end + G29_5: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G29_e; + end + else + begin + next_state <= G29_5; + end + end + G29_4: + begin + next_state <= G29_5; + end + G29_e: + begin + if (rdy_i == 1'b 1) + begin + next_state <= FETCH; + end + else + begin + next_state <= G29_e; + end + end + FETCH: + begin + if (zw_REG_NMI == 1'b 1 & rdy_i == 1'b 1) + begin + next_state <= G29_1; + end + else if (irq_n_i == 1'b 0 & reg_F[2] == 1'b 0 & + rdy_i == 1'b 1 ) + begin + next_state <= G28_1; + end + else if ((d_i == 8'h 69 | d_i == 8'h 65 | + d_i == 8'h 75 | d_i == 8'h 6D | + d_i == 8'h 7D | d_i == 8'h 79 | + d_i == 8'h 61 | d_i == 8'h 71 | + d_i == 8'h 72) & rdy_i == 1'b 1 ) + begin + next_state <= G10_1; + end + else if ((d_i == 8'h 06 | d_i == 8'h 16 | + d_i == 8'h 0E | d_i == 8'h 1E | + d_i[3:0] == 4'h 7 | d_i == 8'h 14 | + d_i == 8'h 04 | d_i == 8'h 0C | + d_i == 8'h 1C) & rdy_i == 1'b 1 ) + begin + next_state <= G11_1; + end + else if ((d_i == 8'h 90 | d_i == 8'h B0 | + d_i == 8'h F0 | d_i == 8'h 30 | + d_i == 8'h D0 | d_i == 8'h 10 | + d_i == 8'h 50 | d_i == 8'h 70 | + d_i == 8'h 80 | d_i[3:0] == 4'h F) & + rdy_i == 1'b 1 ) + begin + next_state <= G12_1; + end + else if ((d_i == 8'h 24 | d_i == 8'h 2C | + d_i == 8'h 3C | d_i == 8'h 34 | + d_i == 8'h 89) & rdy_i == 1'b 1 ) + begin + next_state <= G13_1; + end + else if (d_i == 8'h 00 & rdy_i == 1'b 1 ) + begin + next_state <= G18_1; + end + else if (d_i == 8'h 18 & rdy_i == 1'b 1 ) + begin + next_state <= G5_1; + end + else if (d_i == 8'h D8 & rdy_i == 1'b 1 ) + begin + next_state <= G6_1; + end + else if (d_i == 8'h 58 & rdy_i == 1'b 1 ) + begin + next_state <= G7_1; + end + else if (d_i == 8'h B8 & rdy_i == 1'b 1 ) + begin + next_state <= G8_1; + end + else if ((d_i == 8'h E0 | d_i == 8'h E4 | + d_i == 8'h EC) & rdy_i == 1'b 1 ) + begin + next_state <= G15_1; + end + else if ((d_i == 8'h C0 | d_i == 8'h C4 | + d_i == 8'h CC) & rdy_i == 1'b 1 ) + begin + next_state <= G15_1; + end + else if ((d_i == 8'h C6 | d_i == 8'h D6 | + d_i == 8'h CE | d_i == 8'h DE) & + rdy_i == 1'b 1 ) + begin + next_state <= G14_1; + end + else if (d_i == 8'h CA & rdy_i == 1'b 1 ) + begin + next_state <= G19_1; + end + else if (d_i == 8'h 88 & rdy_i == 1'b 1 ) + begin + next_state <= G19_1; + end + else if ((d_i == 8'h 49 | d_i == 8'h 45 | + d_i == 8'h 55 | d_i == 8'h 4D | + d_i == 8'h 5D | d_i == 8'h 59 | + d_i == 8'h 41 | d_i == 8'h 51 | + d_i == 8'h 09 | d_i == 8'h 05 | + d_i == 8'h 15 | d_i == 8'h 0D | + d_i == 8'h 1D | d_i == 8'h 19 | + d_i == 8'h 01 | d_i == 8'h 11 | + d_i == 8'h 29 | d_i == 8'h 25 | + d_i == 8'h 35 | d_i == 8'h 2D | + d_i == 8'h 3D | d_i == 8'h 39 | + d_i == 8'h 21 | d_i == 8'h 31 | + d_i == 8'h C9 | d_i == 8'h C5 | + d_i == 8'h D5 | d_i == 8'h CD | + d_i == 8'h DD | d_i == 8'h D9 | + d_i == 8'h C1 | d_i == 8'h D1 | + d_i == 8'h 32 | d_i == 8'h D2 | + d_i == 8'h 52 | d_i == 8'h 12) & + rdy_i == 1'b 1 ) + begin + next_state <= G15_1; + end + else if ((d_i == 8'h E6 | d_i == 8'h F6 | + d_i == 8'h EE | d_i == 8'h FE) & + rdy_i == 1'b 1 ) + begin + next_state <= G14_1; + end + else if (d_i == 8'h E8 & rdy_i == 1'b 1 ) + begin + next_state <= G19_1; + end + else if (d_i == 8'h C8 & rdy_i == 1'b 1 ) + begin + next_state <= G19_1; + end + else if ((d_i == 8'h 4C | d_i == 8'h 6C | + d_i == 8'h 7C) & rdy_i == 1'b 1 ) + begin + next_state <= G20_1; + end + else if (d_i == 8'h 20 & rdy_i == 1'b 1 ) + begin + next_state <= G21_1; + end + else if ((d_i == 8'h A9 | d_i == 8'h A5 | + d_i == 8'h B5 | d_i == 8'h AD | + d_i == 8'h BD | d_i == 8'h B9 | + d_i == 8'h A1 | d_i == 8'h B1 | + d_i == 8'h B2) & rdy_i == 1'b 1 ) + begin + next_state <= G15_1; + end + else if ((d_i == 8'h A2 | d_i == 8'h A6 | + d_i == 8'h B6 | d_i == 8'h AE | + d_i == 8'h BE) & rdy_i == 1'b 1 ) + begin + next_state <= G15_1; + end + else if ((d_i == 8'h A0 | d_i == 8'h A4 | + d_i == 8'h B4 | d_i == 8'h AC | + d_i == 8'h BC) & rdy_i == 1'b 1 ) + begin + next_state <= G15_1; + end + else if ((d_i == 8'h 46 | d_i == 8'h 56 | + d_i == 8'h 4E | d_i == 8'h 5E) & + rdy_i == 1'b 1 ) + begin + next_state <= G11_1; + end + else if (d_i == 8'h EA & rdy_i == 1'b 1 ) + begin + next_state <= G1_1; + end + else if (d_i == 8'h 48 & rdy_i == 1'b 1 ) + begin + next_state <= G22_1; + end + else if (d_i == 8'h 08 & rdy_i == 1'b 1 ) + begin + next_state <= G23_1; + end + else if (d_i == 8'h 7A & rdy_i == 1'b 1 ) + begin + next_state <= G24_1; + end + else if (d_i == 8'h 28 & rdy_i == 1'b 1 ) + begin + next_state <= G25_1; + end + else if ((d_i == 8'h 26 | d_i == 8'h 36 | + d_i == 8'h 2E | d_i == 8'h 3E) & + rdy_i == 1'b 1 ) + begin + next_state <= G11_1; + end + else if ((d_i == 8'h 66 | d_i == 8'h 76 | + d_i == 8'h 6E | d_i == 8'h 7E) & + rdy_i == 1'b 1 ) + begin + next_state <= G11_1; + end + else if (d_i == 8'h 40 & rdy_i == 1'b 1 ) + begin + next_state <= G26_1; + end + else if (d_i == 8'h 60 & rdy_i == 1'b 1 ) + begin + next_state <= G27_1; + end + else if ((d_i == 8'h E9 | d_i == 8'h E5 | + d_i == 8'h F5 | d_i == 8'h ED | + d_i == 8'h FD | d_i == 8'h F9 | + d_i == 8'h E1 | d_i == 8'h F1 | + d_i == 8'h F2) & rdy_i == 1'b 1 ) + begin + next_state <= G16_1; + end + else if (d_i == 8'h 38 & rdy_i == 1'b 1 ) + begin + next_state <= G2_1; + end + else if (d_i == 8'h F8 & rdy_i == 1'b 1 ) + begin + next_state <= G3_1; + end + else if (d_i == 8'h 78 & rdy_i == 1'b 1 ) + begin + next_state <= G4_1; + end + else if ((d_i == 8'h 85 | d_i == 8'h 95 | + d_i == 8'h 8D | d_i == 8'h 9D | + d_i == 8'h 99 | d_i == 8'h 81 | + d_i == 8'h 91) & rdy_i == 1'b 1 ) + begin + next_state <= G17_1; + end + else if ((d_i == 8'h 86 | d_i == 8'h 96 | + d_i == 8'h 8E) & rdy_i == 1'b 1 ) + begin + next_state <= G17_1; + end + else if ((d_i == 8'h 84 | d_i == 8'h 94 | + d_i == 8'h 8C) & rdy_i == 1'b 1 ) + begin + next_state <= G17_1; + end + else if (d_i == 8'h AA & rdy_i == 1'b 1 ) + begin + next_state <= G9_1; + end + else if (d_i == 8'h 0A & rdy_i == 1'b 1 ) + begin + next_state <= G31_1; + end + else if (d_i == 8'h 4A & rdy_i == 1'b 1 ) + begin + next_state <= G32_1; + end + else if (d_i == 8'h 2A & rdy_i == 1'b 1 ) + begin + next_state <= G33_1; + end + else if (d_i == 8'h 6A & rdy_i == 1'b 1 ) + begin + next_state <= G34_1; + end + else if (d_i == 8'h A8 & rdy_i == 1'b 1 ) + begin + next_state <= G9_1; + end + else if (d_i == 8'h 98 & rdy_i == 1'b 1 ) + begin + next_state <= G9_1; + end + else if (d_i == 8'h BA & rdy_i == 1'b 1 ) + begin + next_state <= G9_1; + end + else if (d_i == 8'h 8A & rdy_i == 1'b 1 ) + begin + next_state <= G9_1; + end + else if (d_i == 8'h 9A & rdy_i == 1'b 1 ) + begin + next_state <= G9_1; + end + else if (d_i == 8'h DA & rdy_i == 1'b 1 ) + begin + next_state <= G22_1; + end + else if (d_i == 8'h 5A & rdy_i == 1'b 1 ) + begin + next_state <= G22_1; + end + else if (d_i == 8'h 68 & rdy_i == 1'b 1 ) + begin + next_state <= G24_1; + end + else if (d_i == 8'h FA & rdy_i == 1'b 1 ) + begin + next_state <= G24_1; + end + else if ((d_i == 8'h 9C | d_i == 8'h 9E | + d_i == 8'h 64 | d_i == 8'h 74) & + rdy_i == 1'b 1 ) + begin + next_state <= G17_1; + end + else if (d_i == 8'h 3A & rdy_i == 1'b 1 ) + begin + next_state <= G19_1; + end + else if (d_i == 8'h 1A & rdy_i == 1'b 1 ) + begin + next_state <= G19_1; + end + else if (rdy_i == 1'b 1 ) + begin + next_state <= G1_1; + end + else + begin + next_state <= FETCH; + end + end + G1_1: + begin + if (rdy_i == 1'b 1) + begin + next_state <= FETCH; + end + else + begin + next_state <= G1_1; + end + end + G2_1: + begin + if (rdy_i == 1'b 1) + begin + next_state <= FETCH; + end + else + begin + next_state <= G2_1; + end + end + G3_1: + begin + if (rdy_i == 1'b 1) + begin + next_state <= FETCH; + end + else + begin + next_state <= G3_1; + end + end + G4_1: + begin + if (rdy_i == 1'b 1) + begin + next_state <= FETCH; + end + else + begin + next_state <= G4_1; + end + end + G9_1: + begin + if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 9A) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h BA ) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 ) + begin + next_state <= FETCH; + end + else + begin + next_state <= G9_1; + end + end + G5_1: + begin + if (rdy_i == 1'b 1) + begin + next_state <= FETCH; + end + else + begin + next_state <= G5_1; + end + end + G6_1: + begin + if (rdy_i == 1'b 1) + begin + next_state <= FETCH; + end + else + begin + next_state <= G6_1; + end + end + G7_1: + begin + if (rdy_i == 1'b 1) + begin + next_state <= FETCH; + end + else + begin + next_state <= G7_1; + end + end + G8_1: + begin + if (rdy_i == 1'b 1) + begin + next_state <= FETCH; + end + else + begin + next_state <= G8_1; + end + end + G19_1: + begin + if (rdy_i == 1'b 1) + begin + next_state <= FETCH; + end + else + begin + next_state <= G19_1; + end + end + G15_1: + begin + if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A5 | + zw_REG_OP == 8'h A6 | zw_REG_OP == 8'h A4 | + zw_REG_OP == 8'h 45 | zw_REG_OP == 8'h 05 | + zw_REG_OP == 8'h 25 | zw_REG_OP == 8'h C5 | + zw_REG_OP == 8'h E4 | zw_REG_OP == 8'h C4)) + begin + next_state <= G15_e2; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 | + zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 | + zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 | + zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 | + zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) & + (zw_REG_OP == 8'h 09 | zw_REG_OP == 8'h 05 | + zw_REG_OP == 8'h 15 | zw_REG_OP == 8'h 0D | + zw_REG_OP == 8'h 1D | zw_REG_OP == 8'h 19 | + zw_REG_OP == 8'h 01 | zw_REG_OP == 8'h 11 | + zw_REG_OP == 8'h 12) ) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 | + zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 | + zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 | + zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 | + zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) & + (zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 45 | + zw_REG_OP == 8'h 55 | zw_REG_OP == 8'h 4D | + zw_REG_OP == 8'h 5D | zw_REG_OP == 8'h 59 | + zw_REG_OP == 8'h 41 | zw_REG_OP == 8'h 51 | + zw_REG_OP == 8'h 52) ) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 | + zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 | + zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 | + zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 | + zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) & + (zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h 25 | + zw_REG_OP == 8'h 35 | zw_REG_OP == 8'h 2D | + zw_REG_OP == 8'h 3D | zw_REG_OP == 8'h 39 | + zw_REG_OP == 8'h 21 | zw_REG_OP == 8'h 31 | + zw_REG_OP == 8'h 32 | zw_REG_OP == 8'h D2) ) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 | + zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 | + zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 | + zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 | + zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) & + (zw_REG_OP == 8'h C9 | zw_REG_OP == 8'h C5 | + zw_REG_OP == 8'h D5 | zw_REG_OP == 8'h CD | + zw_REG_OP == 8'h DD | zw_REG_OP == 8'h D9 | + zw_REG_OP == 8'h C1 | zw_REG_OP == 8'h D1 | + zw_REG_OP == 8'h C0 | zw_REG_OP == 8'h E0 | + zw_REG_OP == 8'h C4 | zw_REG_OP == 8'h E4 | + zw_REG_OP == 8'h CC | zw_REG_OP == 8'h EC) ) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 | + zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 | + zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 | + zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 | + zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) ) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h B5 | + zw_REG_OP == 8'h B4 | zw_REG_OP == 8'h 55 | + zw_REG_OP == 8'h 15 | zw_REG_OP == 8'h 35 | + zw_REG_OP == 8'h D5) ) + begin + next_state <= G15_2; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h AD | + zw_REG_OP == 8'h AE | zw_REG_OP == 8'h AC | + zw_REG_OP == 8'h 4D | zw_REG_OP == 8'h 0D | + zw_REG_OP == 8'h 2D | zw_REG_OP == 8'h CD | + zw_REG_OP == 8'h EC | zw_REG_OP == 8'h CC) ) + begin + next_state <= G15_3; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h BD | + zw_REG_OP == 8'h BC | zw_REG_OP == 8'h 5D | + zw_REG_OP == 8'h 1D | zw_REG_OP == 8'h 3D | + zw_REG_OP == 8'h DD) ) + begin + next_state <= G15_4; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h B9 | + zw_REG_OP == 8'h BE | zw_REG_OP == 8'h 59 | + zw_REG_OP == 8'h 19 | zw_REG_OP == 8'h 39 | + zw_REG_OP == 8'h D9) ) + begin + next_state <= G15_4; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h B1 | + zw_REG_OP == 8'h 51 | zw_REG_OP == 8'h 11 | + zw_REG_OP == 8'h 31 | zw_REG_OP == 8'h D1) ) + begin + next_state <= G15_5; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A1 | + zw_REG_OP == 8'h 41 | zw_REG_OP == 8'h 01 | + zw_REG_OP == 8'h 21 | zw_REG_OP == 8'h C1) ) + begin + next_state <= G15_7; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h B6 ) + begin + next_state <= G15_2; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 32 | + zw_REG_OP == 8'h D2 | zw_REG_OP == 8'h 52 | + zw_REG_OP == 8'h B2 | zw_REG_OP == 8'h 12) ) + begin + next_state <= G15_8; + end + else + begin + next_state <= G15_1; + end + end + G15_3: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G15_e2; + end + else + begin + next_state <= G15_3; + end + end + G15_4: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G15_e1; + end + else + begin + next_state <= G15_4; + end + end + G15_5: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G15_6; + end + else + begin + next_state <= G15_5; + end + end + G15_2: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G15_e2; + end + else + begin + next_state <= G15_2; + end + end + G15_7: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G15_e3; + end + else + begin + next_state <= G15_7; + end + end + G15_e3: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G15_3; + end + else + begin + next_state <= G15_e3; + end + end + G15_6: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G15_e1; + end + else + begin + next_state <= G15_6; + end + end + G15_e2: + begin + if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 09 | + zw_REG_OP == 8'h 05 | zw_REG_OP == 8'h 15 | + zw_REG_OP == 8'h 0D | zw_REG_OP == 8'h 1D | + zw_REG_OP == 8'h 19 | zw_REG_OP == 8'h 01 | + zw_REG_OP == 8'h 11 | zw_REG_OP == 8'h 12)) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 49 | + zw_REG_OP == 8'h 45 | zw_REG_OP == 8'h 55 | + zw_REG_OP == 8'h 4D | zw_REG_OP == 8'h 5D | + zw_REG_OP == 8'h 59 | zw_REG_OP == 8'h 41 | + zw_REG_OP == 8'h 51 | zw_REG_OP == 8'h 52) ) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 29 | + zw_REG_OP == 8'h 25 | zw_REG_OP == 8'h 35 | + zw_REG_OP == 8'h 2D | zw_REG_OP == 8'h 3D | + zw_REG_OP == 8'h 39 | zw_REG_OP == 8'h 21 | + zw_REG_OP == 8'h 31 | zw_REG_OP == 8'h 32 | + zw_REG_OP == 8'h D2) ) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h C9 | + zw_REG_OP == 8'h C5 | zw_REG_OP == 8'h D5 | + zw_REG_OP == 8'h CD | zw_REG_OP == 8'h DD | + zw_REG_OP == 8'h D9 | zw_REG_OP == 8'h C1 | + zw_REG_OP == 8'h D1 | zw_REG_OP == 8'h C0 | + zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C4 | + zw_REG_OP == 8'h E4 | zw_REG_OP == 8'h CC | + zw_REG_OP == 8'h EC) ) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 ) + begin + next_state <= FETCH; + end + else + begin + next_state <= G15_e2; + end + end + G15_e1: + begin + if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 & + (zw_REG_OP == 8'h 09 | zw_REG_OP == 8'h 05 | + zw_REG_OP == 8'h 15 | zw_REG_OP == 8'h 0D | + zw_REG_OP == 8'h 1D | zw_REG_OP == 8'h 19 | + zw_REG_OP == 8'h 01 | zw_REG_OP == 8'h 11 | + zw_REG_OP == 8'h 12)) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 & + (zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 45 | + zw_REG_OP == 8'h 55 | zw_REG_OP == 8'h 4D | + zw_REG_OP == 8'h 5D | zw_REG_OP == 8'h 59 | + zw_REG_OP == 8'h 41 | zw_REG_OP == 8'h 51 | + zw_REG_OP == 8'h 52) ) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 & + (zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h 25 | + zw_REG_OP == 8'h 35 | zw_REG_OP == 8'h 2D | + zw_REG_OP == 8'h 3D | zw_REG_OP == 8'h 39 | + zw_REG_OP == 8'h 21 | zw_REG_OP == 8'h 31 | + zw_REG_OP == 8'h 32 | zw_REG_OP == 8'h D2) ) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 & + (zw_REG_OP == 8'h C9 | zw_REG_OP == 8'h C5 | + zw_REG_OP == 8'h D5 | zw_REG_OP == 8'h CD | + zw_REG_OP == 8'h DD | zw_REG_OP == 8'h D9 | + zw_REG_OP == 8'h C1 | zw_REG_OP == 8'h D1 | + zw_REG_OP == 8'h C0 | zw_REG_OP == 8'h E0 | + zw_REG_OP == 8'h C4 | zw_REG_OP == 8'h E4 | + zw_REG_OP == 8'h CC | zw_REG_OP == 8'h EC) ) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 ) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 ) + begin + next_state <= G15_e2; + end + else + begin + next_state <= G15_e1; + end + end + G15_8: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G15_3; + end + else + begin + next_state <= G15_8; + end + end + G10_1: + begin + if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 65) + begin + next_state <= G10_e2; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 69 & + reg_F[3] == 1'b 0 ) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 75 ) + begin + next_state <= G10_2; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 6D ) + begin + next_state <= G10_3; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 7D ) + begin + next_state <= G10_4; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 79 ) + begin + next_state <= G10_4; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 71 ) + begin + next_state <= G10_5; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 61 ) + begin + next_state <= G10_7; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 69 & + reg_F[3] == 1'b 1 ) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 72 ) + begin + next_state <= G10_8; + end + else + begin + next_state <= G10_1; + end + end + G10_3: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G10_e2; + end + else + begin + next_state <= G10_3; + end + end + G10_4: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G10_e1; + end + else + begin + next_state <= G10_4; + end + end + G10_5: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G10_6; + end + else + begin + next_state <= G10_5; + end + end + G10_2: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G10_e2; + end + else + begin + next_state <= G10_2; + end + end + G10_7: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G10_e3; + end + else + begin + next_state <= G10_7; + end + end + G10_e3: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G10_3; + end + else + begin + next_state <= G10_e3; + end + end + G10_e1: + begin + if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 & + reg_F[3] == 1'b 0) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 & + reg_F[3] == 1'b 1 ) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 ) + begin + next_state <= G10_e2; + end + else + begin + next_state <= G10_e1; + end + end + G10_e2: + begin + if (rdy_i == 1'b 1 & reg_F[3] == 1'b 0) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 & reg_F[3] == 1'b 1 ) + begin + next_state <= FETCH; + end + else + begin + next_state <= G10_e2; + end + end + G10_6: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G10_e1; + end + else + begin + next_state <= G10_6; + end + end + G10_8: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G10_3; + end + else + begin + next_state <= G10_8; + end + end + G17_1: + begin + if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 85 | + zw_REG_OP == 8'h 86 | zw_REG_OP == 8'h 64 | + zw_REG_OP == 8'h 84)) + begin + next_state <= G17_e; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 95 | + zw_REG_OP == 8'h 74 | zw_REG_OP == 8'h 94) ) + begin + next_state <= G17_2; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 8D | + zw_REG_OP == 8'h 8E | zw_REG_OP == 8'h 9C | + zw_REG_OP == 8'h 8C) ) + begin + next_state <= G17_3; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 9D | + zw_REG_OP == 8'h 9E) ) + begin + next_state <= G17_4; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 99 ) + begin + next_state <= G17_4; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 91 ) + begin + next_state <= G17_6; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 81 ) + begin + next_state <= G17_8; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 96 ) + begin + next_state <= G17_2; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 92 ) + begin + next_state <= G17_11; + end + else + begin + next_state <= G17_1; + end + end + G17_4: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G17_5; + end + else + begin + next_state <= G17_4; + end + end + G17_6: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G17_7; + end + else + begin + next_state <= G17_6; + end + end + G17_3: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G17_e; + end + else + begin + next_state <= G17_3; + end + end + G17_2: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G17_e; + end + else + begin + next_state <= G17_2; + end + end + G17_8: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G17_9; + end + else + begin + next_state <= G17_8; + end + end + G17_9: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G17_10; + end + else + begin + next_state <= G17_9; + end + end + G17_7: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G17_5; + end + else + begin + next_state <= G17_7; + end + end + G17_5: + begin + next_state <= G17_e; + end + G17_10: + begin + next_state <= G17_e; + end + G17_e: + begin + next_state <= FETCH; + end + G17_11: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G17_3; + end + else + begin + next_state <= G17_11; + end + end + G16_1: + begin + if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E5) + begin + next_state <= G16_e2; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E9 & + reg_F[3] == 1'b 0 ) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F5 ) + begin + next_state <= G16_2; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h ED ) + begin + next_state <= G16_3; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h FD ) + begin + next_state <= G16_4; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F9 ) + begin + next_state <= G16_4; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F1 ) + begin + next_state <= G16_5; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E1 ) + begin + next_state <= G16_7; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E9 & + reg_F[3] == 1'b 1 ) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F2 ) + begin + next_state <= G16_8; + end + else + begin + next_state <= G16_1; + end + end + G16_3: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G16_e2; + end + else + begin + next_state <= G16_3; + end + end + G16_4: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G16_e1; + end + else + begin + next_state <= G16_4; + end + end + G16_5: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G16_6; + end + else + begin + next_state <= G16_5; + end + end + G16_2: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G16_e2; + end + else + begin + next_state <= G16_2; + end + end + G16_7: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G16_e3; + end + else + begin + next_state <= G16_7; + end + end + G16_6: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G16_e1; + end + else + begin + next_state <= G16_6; + end + end + G16_e3: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G16_3; + end + else + begin + next_state <= G16_e3; + end + end + G16_e1: + begin + if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 & + reg_F[3] == 1'b 0) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 & + reg_F[3] == 1'b 1 ) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 ) + begin + next_state <= G16_e2; + end + else + begin + next_state <= G16_e1; + end + end + G16_e2: + begin + if (rdy_i == 1'b 1 & reg_F[3] == 1'b 0) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 & reg_F[3] == 1'b 1 ) + begin + next_state <= FETCH; + end + else + begin + next_state <= G16_e2; + end + end + G16_8: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G16_3; + end + else + begin + next_state <= G16_8; + end + end + G11_1: + begin + if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 1E | + zw_REG_OP == 8'h 7E | zw_REG_OP == 8'h 3E | + zw_REG_OP == 8'h 5E)) + begin + next_state <= G11_6; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 06 | + zw_REG_OP == 8'h 66 | zw_REG_OP == 8'h 26 | + zw_REG_OP == 8'h 46 | zw_REG_OP == 8'h 04 | + zw_REG_OP == 8'h 14) ) + begin + next_state <= G11_3; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 16 | + zw_REG_OP == 8'h 76 | zw_REG_OP == 8'h 36 | + zw_REG_OP == 8'h 56) ) + begin + next_state <= G11_2; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 0E | + zw_REG_OP == 8'h 6E | zw_REG_OP == 8'h 2E | + zw_REG_OP == 8'h 4E | zw_REG_OP == 8'h 0C | + zw_REG_OP == 8'h 1C) ) + begin + next_state <= G11_5; + end + else if (rdy_i == 1'b 1 & zw_REG_OP[3:0] == 4'h 7 ) + begin + next_state <= G11_3; + end + else + begin + next_state <= G11_1; + end + end + G11_5: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G11_3; + end + else + begin + next_state <= G11_5; + end + end + G11_6: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G11_7; + end + else + begin + next_state <= G11_6; + end + end + G11_2: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G11_3; + end + else + begin + next_state <= G11_2; + end + end + G11_7: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G11_4; + end + else + begin + next_state <= G11_7; + end + end + G11_3: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G11_4; + end + else + begin + next_state <= G11_3; + end + end + G11_4: + begin + if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 06 | + zw_REG_OP == 8'h 16 | zw_REG_OP == 8'h 0E | + zw_REG_OP == 8'h 1E)) + begin + next_state <= G11_e; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 46 | + zw_REG_OP == 8'h 56 | zw_REG_OP == 8'h 4E | + zw_REG_OP == 8'h 5E) ) + begin + next_state <= G11_e; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 26 | + zw_REG_OP == 8'h 36 | zw_REG_OP == 8'h 2E | + zw_REG_OP == 8'h 3E) ) + begin + next_state <= G11_e; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 66 | + zw_REG_OP == 8'h 76 | zw_REG_OP == 8'h 6E | + zw_REG_OP == 8'h 7E) ) + begin + next_state <= G11_e; + end + else if (rdy_i == 1'b 1 & zw_REG_OP[7] == 1'b 0 & + zw_REG_OP[3:0] == 4'h 7 ) + begin + next_state <= G11_e; + end + else if (rdy_i == 1'b 1 & zw_REG_OP[7] == 1'b 1 & + zw_REG_OP[3:0] == 4'h 7 ) + begin + next_state <= G11_e; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 14 | + zw_REG_OP == 8'h 1C) ) + begin + next_state <= G11_e; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 04 | + zw_REG_OP == 8'h 0C) ) + begin + next_state <= G11_e; + end + else + begin + next_state <= G11_4; + end + end + G11_e: + begin + if (zw_REG_OP[3:0] == 4'h 7) + begin + next_state <= FETCH; + end + else if (zw_REG_OP == 8'h 14 | zw_REG_OP == 8'h 04 | + zw_REG_OP == 8'h 0C | zw_REG_OP == 8'h 1C ) + begin + next_state <= FETCH; + end + else + begin + next_state <= FETCH; + end + end + G31_1: + begin + if (rdy_i == 1'b 1) + begin + next_state <= FETCH; + end + else + begin + next_state <= G31_1; + end + end + G34_1: + begin + if (rdy_i == 1'b 1) + begin + next_state <= FETCH; + end + else + begin + next_state <= G34_1; + end + end + G32_1: + begin + if (rdy_i == 1'b 1) + begin + next_state <= FETCH; + end + else + begin + next_state <= G32_1; + end + end + G33_1: + begin + if (rdy_i == 1'b 1) + begin + next_state <= FETCH; + end + else + begin + next_state <= G33_1; + end + end + G12_1: + begin + if (rdy_i == 1'b 1 & (reg_F[0] == 1'b 1 & + zw_REG_OP == 8'h 90 | reg_F[0] == 1'b 0 & + zw_REG_OP == 8'h B0 | reg_F[1] == 1'b 0 & + zw_REG_OP == 8'h F0 | reg_F[7] == 1'b 0 & + zw_REG_OP == 8'h 30 | reg_F[1] == 1'b 1 & + zw_REG_OP == 8'h D0 | reg_F[7] == 1'b 1 & + zw_REG_OP == 8'h 10 | reg_F[6] == 1'b 1 & + zw_REG_OP == 8'h 50 | reg_F[6] == 1'b 0 & + zw_REG_OP == 8'h 70)) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 8F | + zw_REG_OP == 8'h 9F | zw_REG_OP == 8'h AF | + zw_REG_OP == 8'h BF | zw_REG_OP == 8'h CF | + zw_REG_OP == 8'h DF | zw_REG_OP == 8'h EF | + zw_REG_OP == 8'h FF | zw_REG_OP == 8'h 0F | + zw_REG_OP == 8'h 1F | zw_REG_OP == 8'h 2F | + zw_REG_OP == 8'h 3F | zw_REG_OP == 8'h 4F | + zw_REG_OP == 8'h 5F | zw_REG_OP == 8'h 6F | + zw_REG_OP == 8'h 7F) ) + begin + next_state <= G12_2; + end + else if (rdy_i == 1'b 1 ) + begin + next_state <= G12_e1; + end + else + begin + next_state <= G12_1; + end + end + G12_e1: + begin + if (rdy_i == 1'b 1 & zw_b3 == adr_nxt_pc_i[15:8]) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 ) + begin + next_state <= G12_e2; + end + else + begin + next_state <= G12_e1; + end + end + G12_e2: + begin + if (rdy_i == 1'b 1) + begin + next_state <= FETCH; + end + else + begin + next_state <= G12_e2; + end + end + G12_2: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G12_3; + end + else + begin + next_state <= G12_2; + end + end + G12_3: + begin + if (rdy_i == 1'b 1 & (d_i[0] == 1'b 1 & + zw_REG_OP == 8'h 8F | d_i[1] == 1'b 1 & + zw_REG_OP == 8'h 9F | d_i[2] == 1'b 1 & + zw_REG_OP == 8'h AF | d_i[3] == 1'b 1 & + zw_REG_OP == 8'h BF | d_i[4] == 1'b 1 & + zw_REG_OP == 8'h CF | d_i[5] == 1'b 1 & + zw_REG_OP == 8'h DF | d_i[6] == 1'b 1 & + zw_REG_OP == 8'h EF | d_i[7] == 1'b 1 & + zw_REG_OP == 8'h FF | d_i[0] == 1'b 0 & + zw_REG_OP == 8'h 0F | d_i[1] == 1'b 0 & + zw_REG_OP == 8'h 1F | d_i[2] == 1'b 0 & + zw_REG_OP == 8'h 2F | d_i[3] == 1'b 0 & + zw_REG_OP == 8'h 3F | d_i[4] == 1'b 0 & + zw_REG_OP == 8'h 4F | d_i[5] == 1'b 0 & + zw_REG_OP == 8'h 5F | d_i[6] == 1'b 0 & + zw_REG_OP == 8'h 6F | d_i[7] == 1'b 0 & + zw_REG_OP == 8'h 7F)) + begin + next_state <= G12_4; + end + else if (rdy_i == 1'b 1 ) + begin + next_state <= G12_e2; + end + else + begin + next_state <= G12_3; + end + end + G12_4: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G12_e1; + end + else + begin + next_state <= G12_4; + end + end + G20_1: + begin + if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 4C) + begin + next_state <= G20_e; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 6C ) + begin + next_state <= G20_2; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 7C ) + begin + next_state <= G20_3; + end + else + begin + next_state <= G20_1; + end + end + G20_2: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G20_4; + end + else + begin + next_state <= G20_2; + end + end + G20_5: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G20_e; + end + else + begin + next_state <= G20_5; + end + end + G20_e: + begin + if (rdy_i == 1'b 1) + begin + next_state <= FETCH; + end + else + begin + next_state <= G20_e; + end + end + G20_3: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G20_4; + end + else + begin + next_state <= G20_3; + end + end + G20_4: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G20_5; + end + else + begin + next_state <= G20_4; + end + end + G21_1: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G21_2; + end + else + begin + next_state <= G21_1; + end + end + G21_2: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G21_3; + end + else + begin + next_state <= G21_2; + end + end + G21_3: + begin + next_state <= G21_4; + end + G21_4: + begin + next_state <= G21_e; + end + G21_e: + begin + if (rdy_i == 1'b 1) + begin + next_state <= FETCH; + end + else + begin + next_state <= G21_e; + end + end + G13_3: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G13_e1; + end + else + begin + next_state <= G13_3; + end + end + G13_1: + begin + if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 34) + begin + next_state <= G13_2; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 3C ) + begin + next_state <= G13_4; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 24 ) + begin + next_state <= G13_e1; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 2C ) + begin + next_state <= G13_3; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 89 ) + begin + next_state <= FETCH; + end + else + begin + next_state <= G13_1; + end + end + G13_4: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G13_e2; + end + else + begin + next_state <= G13_4; + end + end + G13_2: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G13_e1; + end + else + begin + next_state <= G13_2; + end + end + G13_e1: + begin + if (rdy_i == 1'b 1) + begin + next_state <= FETCH; + end + else + begin + next_state <= G13_e1; + end + end + G13_e2: + begin + if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0) + begin + next_state <= FETCH; + end + else if (rdy_i == 1'b 1 ) + begin + next_state <= G13_e1; + end + else + begin + next_state <= G13_e2; + end + end + G18_1: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G18_2; + end + else + begin + next_state <= G18_1; + end + end + G18_2: + begin + next_state <= G18_3; + end + G18_3: + begin + next_state <= G18_4; + end + G18_4: + begin + next_state <= G18_5; + end + G18_e: + begin + if (rdy_i == 1'b 1) + begin + next_state <= FETCH; + end + else + begin + next_state <= G18_e; + end + end + G18_5: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G18_e; + end + else + begin + next_state <= G18_5; + end + end + G26_1: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G26_2; + end + else + begin + next_state <= G26_1; + end + end + G26_2: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G26_3; + end + else + begin + next_state <= G26_2; + end + end + G26_3: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G26_4; + end + else + begin + next_state <= G26_3; + end + end + G26_4: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G26_e; + end + else + begin + next_state <= G26_4; + end + end + G26_e: + begin + if (rdy_i == 1'b 1) + begin + next_state <= FETCH; + end + else + begin + next_state <= G26_e; + end + end + G27_1: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G27_2; + end + else + begin + next_state <= G27_1; + end + end + G27_2: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G27_3; + end + else + begin + next_state <= G27_2; + end + end + G27_3: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G27_4; + end + else + begin + next_state <= G27_3; + end + end + G27_4: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G27_e; + end + else + begin + next_state <= G27_4; + end + end + G27_e: + begin + if (rdy_i == 1'b 1) + begin + next_state <= FETCH; + end + else + begin + next_state <= G27_e; + end + end + G14_1: + begin + if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h C6 | + zw_REG_OP == 8'h E6)) + begin + next_state <= G14_3; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h D6 | + zw_REG_OP == 8'h F6) ) + begin + next_state <= G14_2; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h CE | + zw_REG_OP == 8'h EE) ) + begin + next_state <= G14_5; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h DE | + zw_REG_OP == 8'h FE) ) + begin + next_state <= G14_6; + end + else + begin + next_state <= G14_1; + end + end + G14_5: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G14_3; + end + else + begin + next_state <= G14_5; + end + end + G14_6: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G14_7; + end + else + begin + next_state <= G14_6; + end + end + G14_2: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G14_3; + end + else + begin + next_state <= G14_2; + end + end + G14_7: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G14_3; + end + else + begin + next_state <= G14_7; + end + end + G14_3: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G14_4; + end + else + begin + next_state <= G14_3; + end + end + G14_4: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G14_e; + end + else + begin + next_state <= G14_4; + end + end + G14_e: + begin + next_state <= FETCH; + end + G22_1: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G22_e; + end + else + begin + next_state <= G22_1; + end + end + G22_e: + begin + next_state <= FETCH; + end + G23_1: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G23_e; + end + else + begin + next_state <= G23_1; + end + end + G23_e: + begin + next_state <= FETCH; + end + G24_1: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G24_2; + end + else + begin + next_state <= G24_1; + end + end + G24_2: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G24_e; + end + else + begin + next_state <= G24_2; + end + end + G24_e: + begin + if (rdy_i == 1'b 1) + begin + next_state <= FETCH; + end + else + begin + next_state <= G24_e; + end + end + G25_1: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G25_2; + end + else + begin + next_state <= G25_1; + end + end + G25_2: + begin + if (rdy_i == 1'b 1) + begin + next_state <= G25_e; + end + else + begin + next_state <= G25_2; + end + end + G25_e: + begin + if (rdy_i == 1'b 1) + begin + next_state <= FETCH; + end + else + begin + next_state <= G25_e; + end + end + default: + begin + next_state <= RES; + end + endcase + end + +// --------------------------------------------------------------- + +// --------------------------------------------------------------- + +always @(adr_nxt_pc_i or adr_pc_i or adr_sp_i or alu_dec_val_i or current_state + or d_alu_i or d_i or d_regs_out_i or irq_n_i or q_a_i + or q_x_i or q_y_i or rdy_i or reg_F or reg_sel_pc_in + or reg_sel_pc_val or reg_sel_rb_in or reg_sel_rb_out or reg_sel_reg or reg_sel_sp_as + or reg_sel_sp_in or sig_PC or zw_ALU or zw_ALU1 or zw_ALU2 + or zw_ALU3 or zw_ALU4 or zw_ALU5 or zw_ALU6 or zw_REG_NMI + or zw_REG_OP or zw_b1 or zw_b2 or zw_b3 or zw_b4 + or zw_w1) + begin : output_proc + a_o <= sig_PC; + adr_o <= 16'h 0000; + ch_a_o <= 8'h 00; + ch_b_o <= 8'h 00; + d_regs_in_o <= 8'h 00; + fetch_o <= 1'b 0; + ld_o <= 2'b 00; + ld_pc_o <= 1'b 0; + ld_sp_o <= 1'b 0; + load_regs_o <= 1'b 0; + offset_o <= 16'h 0000; + sel_pc_in_o <= reg_sel_pc_in; + sel_pc_val_o <= reg_sel_pc_val; + sel_rb_in_o <= reg_sel_rb_in; + sel_rb_out_o <= reg_sel_rb_out; + sel_reg_o <= reg_sel_reg; + sel_sp_as_o <= reg_sel_sp_as; + sel_sp_in_o <= reg_sel_sp_in; + +// Default Assignment To Internals + sig_D_OUT <= 8'h 00; + sig_SYNC <= 1'b 0; + sig_WR <= 1'b 0; + zw_ALU <= {1'b 0, 8'h 00}; + zw_ALU1 <= {1'b 0, 4'h 0}; + zw_ALU2 <= {1'b 0, 4'h 0}; + zw_ALU3 <= {1'b 0, 4'h 0}; + zw_ALU4 <= {1'b 0, 4'h 0}; + zw_ALU5 <= 4'h 0; + zw_ALU6 <= 4'h 0; + +// Combined Actions + case (current_state) + G30_1: + begin + ld_o <= 2'b 11; + ld_sp_o <= 1'b 1; + end + G30_3: + begin + adr_o <= 16'h FFFB; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + G30_4: + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + G30_e: + begin + if (rdy_i == 1'b 1) + begin + adr_o <= {d_i, zw_w1[7:0]}; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G30_2: + begin + ld_o <= 2'b 11; + ld_sp_o <= 1'b 1; + end + RES: + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + ld_sp_o <= 1'b 1; + end + G28_1: + begin + if (rdy_i == 1'b 1) + begin + ld_o <= 2'b 11; + ld_sp_o <= 1'b 1; + ld_pc_o <= 1'b 1; + sig_WR <= 1'b 1; + sig_D_OUT <= adr_pc_i[15:8]; + end + end + G28_2: + begin + ld_o <= 2'b 11; + ld_sp_o <= 1'b 1; + sig_WR <= 1'b 1; + sig_D_OUT <= adr_pc_i[7:0]; + end + G28_3: + begin + ld_o <= 2'b 11; + ld_sp_o <= 1'b 1; + sig_WR <= 1'b 1; + sig_D_OUT <= reg_F; + end + G28_e: + begin + if (rdy_i == 1'b 1) + begin + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G29_1: + begin + if (rdy_i == 1'b 1) + begin + ld_o <= 2'b 11; + ld_sp_o <= 1'b 1; + ld_pc_o <= 1'b 1; + sig_WR <= 1'b 1; + sig_D_OUT <= adr_pc_i[15:8]; + end + end + G29_2: + begin + ld_o <= 2'b 11; + ld_sp_o <= 1'b 1; + sig_WR <= 1'b 1; + sig_D_OUT <= adr_pc_i[7:0]; + end + G29_3: + begin + ld_o <= 2'b 11; + ld_sp_o <= 1'b 1; + sig_WR <= 1'b 1; + sig_D_OUT <= reg_F; + end + G29_e: + begin + if (rdy_i == 1'b 1) + begin + adr_o <= {d_i, zw_b1}; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + FETCH: + begin + sig_SYNC <= ~rdy_i; + if (zw_REG_NMI == 1'b 1 & rdy_i == 1'b 1) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (irq_n_i == 1'b 0 & reg_F[2] == 1'b 0 & + rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if ((d_i == 8'h 69 | d_i == 8'h 65 | + d_i == 8'h 75 | d_i == 8'h 6D | + d_i == 8'h 7D | d_i == 8'h 79 | + d_i == 8'h 61 | d_i == 8'h 71 | + d_i == 8'h 72) & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if ((d_i == 8'h 06 | d_i == 8'h 16 | + d_i == 8'h 0E | d_i == 8'h 1E | + d_i[3:0] == 4'h 7 | d_i == 8'h 14 | + d_i == 8'h 04 | d_i == 8'h 0C | + d_i == 8'h 1C) & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if ((d_i == 8'h 90 | d_i == 8'h B0 | + d_i == 8'h F0 | d_i == 8'h 30 | + d_i == 8'h D0 | d_i == 8'h 10 | + d_i == 8'h 50 | d_i == 8'h 70 | + d_i == 8'h 80 | d_i[3:0] == 4'h F) & + rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if ((d_i == 8'h 24 | d_i == 8'h 2C | + d_i == 8'h 3C | d_i == 8'h 34 | + d_i == 8'h 89) & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h 00 & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h 18 & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h D8 & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h 58 & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h B8 & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if ((d_i == 8'h E0 | d_i == 8'h E4 | + d_i == 8'h EC) & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if ((d_i == 8'h C0 | d_i == 8'h C4 | + d_i == 8'h CC) & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if ((d_i == 8'h C6 | d_i == 8'h D6 | + d_i == 8'h CE | d_i == 8'h DE) & + rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h CA & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h 88 & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if ((d_i == 8'h 49 | d_i == 8'h 45 | + d_i == 8'h 55 | d_i == 8'h 4D | + d_i == 8'h 5D | d_i == 8'h 59 | + d_i == 8'h 41 | d_i == 8'h 51 | + d_i == 8'h 09 | d_i == 8'h 05 | + d_i == 8'h 15 | d_i == 8'h 0D | + d_i == 8'h 1D | d_i == 8'h 19 | + d_i == 8'h 01 | d_i == 8'h 11 | + d_i == 8'h 29 | d_i == 8'h 25 | + d_i == 8'h 35 | d_i == 8'h 2D | + d_i == 8'h 3D | d_i == 8'h 39 | + d_i == 8'h 21 | d_i == 8'h 31 | + d_i == 8'h C9 | d_i == 8'h C5 | + d_i == 8'h D5 | d_i == 8'h CD | + d_i == 8'h DD | d_i == 8'h D9 | + d_i == 8'h C1 | d_i == 8'h D1 | + d_i == 8'h 32 | d_i == 8'h D2 | + d_i == 8'h 52 | d_i == 8'h 12) & + rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if ((d_i == 8'h E6 | d_i == 8'h F6 | + d_i == 8'h EE | d_i == 8'h FE) & + rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h E8 & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h C8 & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if ((d_i == 8'h 4C | d_i == 8'h 6C | + d_i == 8'h 7C) & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h 20 & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if ((d_i == 8'h A9 | d_i == 8'h A5 | + d_i == 8'h B5 | d_i == 8'h AD | + d_i == 8'h BD | d_i == 8'h B9 | + d_i == 8'h A1 | d_i == 8'h B1 | + d_i == 8'h B2) & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if ((d_i == 8'h A2 | d_i == 8'h A6 | + d_i == 8'h B6 | d_i == 8'h AE | + d_i == 8'h BE) & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if ((d_i == 8'h A0 | d_i == 8'h A4 | + d_i == 8'h B4 | d_i == 8'h AC | + d_i == 8'h BC) & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if ((d_i == 8'h 46 | d_i == 8'h 56 | + d_i == 8'h 4E | d_i == 8'h 5E) & + rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h EA & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h 48 & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h 08 & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h 7A & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h 28 & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if ((d_i == 8'h 26 | d_i == 8'h 36 | + d_i == 8'h 2E | d_i == 8'h 3E) & + rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if ((d_i == 8'h 66 | d_i == 8'h 76 | + d_i == 8'h 6E | d_i == 8'h 7E) & + rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h 40 & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h 60 & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if ((d_i == 8'h E9 | d_i == 8'h E5 | + d_i == 8'h F5 | d_i == 8'h ED | + d_i == 8'h FD | d_i == 8'h F9 | + d_i == 8'h E1 | d_i == 8'h F1 | + d_i == 8'h F2) & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h 38 & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h F8 & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h 78 & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if ((d_i == 8'h 85 | d_i == 8'h 95 | + d_i == 8'h 8D | d_i == 8'h 9D | + d_i == 8'h 99 | d_i == 8'h 81 | + d_i == 8'h 91) & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if ((d_i == 8'h 86 | d_i == 8'h 96 | + d_i == 8'h 8E) & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if ((d_i == 8'h 84 | d_i == 8'h 94 | + d_i == 8'h 8C) & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h AA & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h 0A & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h 4A & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h 2A & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h 6A & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h A8 & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h 98 & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h BA & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h 8A & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h 9A & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h DA & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h 5A & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h 68 & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h FA & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if ((d_i == 8'h 9C | d_i == 8'h 9E | + d_i == 8'h 64 | d_i == 8'h 74) & + rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h 3A & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (d_i == 8'h 1A & rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G1_1: + begin + if (rdy_i == 1'b 1) + begin + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G2_1: + begin + if (rdy_i == 1'b 1) + begin + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G3_1: + begin + if (rdy_i == 1'b 1) + begin + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G4_1: + begin + if (rdy_i == 1'b 1) + begin + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G9_1: + begin + if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 9A) + begin + adr_o <= {8'h 01, d_regs_out_i}; + ld_o <= 2'b 11; + ld_sp_o <= 1'b 1; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h BA ) + begin + d_regs_in_o <= adr_sp_i[7:0]; + ch_a_o <= adr_sp_i[7:0]; + ch_b_o <= 8'h 00; + load_regs_o <= 1'b 1; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 ) + begin + ch_a_o <= d_regs_out_i; + ch_b_o <= 8'h 00; + load_regs_o <= 1'b 1; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G5_1: + begin + if (rdy_i == 1'b 1) + begin + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G6_1: + begin + if (rdy_i == 1'b 1) + begin + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G7_1: + begin + if (rdy_i == 1'b 1) + begin + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G8_1: + begin + if (rdy_i == 1'b 1) + begin + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G19_1: + begin + if (rdy_i == 1'b 1) + begin + d_regs_in_o <= d_alu_i; + ch_a_o <= d_regs_out_i; + ch_b_o <= zw_b4; + load_regs_o <= 1'b 1; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G15_1: + begin + if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A5 | + zw_REG_OP == 8'h A6 | zw_REG_OP == 8'h A4 | + zw_REG_OP == 8'h 45 | zw_REG_OP == 8'h 05 | + zw_REG_OP == 8'h 25 | zw_REG_OP == 8'h C5 | + zw_REG_OP == 8'h E4 | zw_REG_OP == 8'h C4)) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 | + zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 | + zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 | + zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 | + zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) & + (zw_REG_OP == 8'h 09 | zw_REG_OP == 8'h 05 | + zw_REG_OP == 8'h 15 | zw_REG_OP == 8'h 0D | + zw_REG_OP == 8'h 1D | zw_REG_OP == 8'h 19 | + zw_REG_OP == 8'h 01 | zw_REG_OP == 8'h 11 | + zw_REG_OP == 8'h 12) ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + d_regs_in_o <= d_i | q_a_i; + load_regs_o <= 1'b 1; + ch_a_o <= d_i | q_a_i; + ch_b_o <= 8'h 00; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 | + zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 | + zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 | + zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 | + zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) & + (zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 45 | + zw_REG_OP == 8'h 55 | zw_REG_OP == 8'h 4D | + zw_REG_OP == 8'h 5D | zw_REG_OP == 8'h 59 | + zw_REG_OP == 8'h 41 | zw_REG_OP == 8'h 51 | + zw_REG_OP == 8'h 52) ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + d_regs_in_o <= d_i ^ q_a_i; + load_regs_o <= 1'b 1; + ch_a_o <= d_i ^ q_a_i; + ch_b_o <= 8'h 00; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 | + zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 | + zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 | + zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 | + zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) & + (zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h 25 | + zw_REG_OP == 8'h 35 | zw_REG_OP == 8'h 2D | + zw_REG_OP == 8'h 3D | zw_REG_OP == 8'h 39 | + zw_REG_OP == 8'h 21 | zw_REG_OP == 8'h 31 | + zw_REG_OP == 8'h 32 | zw_REG_OP == 8'h D2) ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + d_regs_in_o <= d_i & q_a_i; + load_regs_o <= 1'b 1; + ch_a_o <= d_i & q_a_i; + ch_b_o <= 8'h 00; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 | + zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 | + zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 | + zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 | + zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) & + (zw_REG_OP == 8'h C9 | zw_REG_OP == 8'h C5 | + zw_REG_OP == 8'h D5 | zw_REG_OP == 8'h CD | + zw_REG_OP == 8'h DD | zw_REG_OP == 8'h D9 | + zw_REG_OP == 8'h C1 | zw_REG_OP == 8'h D1 | + zw_REG_OP == 8'h C0 | zw_REG_OP == 8'h E0 | + zw_REG_OP == 8'h C4 | zw_REG_OP == 8'h E4 | + zw_REG_OP == 8'h CC | zw_REG_OP == 8'h EC) ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + zw_ALU <= {1'b 0, d_regs_out_i} + {1'b 0, (~d_i)} + + 1; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A9 | + zw_REG_OP == 8'h A2 | zw_REG_OP == 8'h A0 | + zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C0 | + zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 09 | + zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h C9) ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + d_regs_in_o <= d_i; + load_regs_o <= 1'b 1; + ch_a_o <= d_i; + ch_b_o <= 8'h 00; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h B5 | + zw_REG_OP == 8'h B4 | zw_REG_OP == 8'h 55 | + zw_REG_OP == 8'h 15 | zw_REG_OP == 8'h 35 | + zw_REG_OP == 8'h D5) ) + begin + ch_a_o <= d_i; + ch_b_o <= q_x_i; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h AD | + zw_REG_OP == 8'h AE | zw_REG_OP == 8'h AC | + zw_REG_OP == 8'h 4D | zw_REG_OP == 8'h 0D | + zw_REG_OP == 8'h 2D | zw_REG_OP == 8'h CD | + zw_REG_OP == 8'h EC | zw_REG_OP == 8'h CC) ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h BD | + zw_REG_OP == 8'h BC | zw_REG_OP == 8'h 5D | + zw_REG_OP == 8'h 1D | zw_REG_OP == 8'h 3D | + zw_REG_OP == 8'h DD) ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + ch_a_o <= d_i; + ch_b_o <= q_x_i; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h B9 | + zw_REG_OP == 8'h BE | zw_REG_OP == 8'h 59 | + zw_REG_OP == 8'h 19 | zw_REG_OP == 8'h 39 | + zw_REG_OP == 8'h D9) ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + ch_a_o <= d_i; + ch_b_o <= q_y_i; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h B1 | + zw_REG_OP == 8'h 51 | zw_REG_OP == 8'h 11 | + zw_REG_OP == 8'h 31 | zw_REG_OP == 8'h D1) ) + begin + ch_a_o <= d_i; + ch_b_o <= 8'h 01; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h A1 | + zw_REG_OP == 8'h 41 | zw_REG_OP == 8'h 01 | + zw_REG_OP == 8'h 21 | zw_REG_OP == 8'h C1) ) + begin + ch_a_o <= d_i; + ch_b_o <= q_x_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h B6 ) + begin + ch_a_o <= d_i; + ch_b_o <= q_y_i; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 32 | + zw_REG_OP == 8'h D2 | zw_REG_OP == 8'h 52 | + zw_REG_OP == 8'h B2 | zw_REG_OP == 8'h 12) ) + begin + ch_a_o <= d_i; + ch_b_o <= 8'h 01; + end + end + G15_3: + begin + if (rdy_i == 1'b 1) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G15_4: + begin + if (rdy_i == 1'b 1) + begin + ch_a_o <= d_i; + ch_b_o <= {7'b 0000000, zw_b2[0]}; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G15_5: + begin + if (rdy_i == 1'b 1) + begin + ch_a_o <= d_i; + ch_b_o <= q_y_i; + end + end + G15_2: + begin + if (rdy_i == 1'b 1) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G15_e3: + begin + if (rdy_i == 1'b 1) + begin + ch_a_o <= zw_b1; + ch_b_o <= 8'h 01; + end + end + G15_6: + begin + if (rdy_i == 1'b 1) + begin + ch_a_o <= d_i; + ch_b_o <= {7'b 0000000, zw_b2[0]}; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G15_e2: + begin + if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 09 | + zw_REG_OP == 8'h 05 | zw_REG_OP == 8'h 15 | + zw_REG_OP == 8'h 0D | zw_REG_OP == 8'h 1D | + zw_REG_OP == 8'h 19 | zw_REG_OP == 8'h 01 | + zw_REG_OP == 8'h 11 | zw_REG_OP == 8'h 12)) + begin + d_regs_in_o <= d_i | q_a_i; + load_regs_o <= 1'b 1; + ch_a_o <= d_i | q_a_i; + ch_b_o <= 8'h 00; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 49 | + zw_REG_OP == 8'h 45 | zw_REG_OP == 8'h 55 | + zw_REG_OP == 8'h 4D | zw_REG_OP == 8'h 5D | + zw_REG_OP == 8'h 59 | zw_REG_OP == 8'h 41 | + zw_REG_OP == 8'h 51 | zw_REG_OP == 8'h 52) ) + begin + d_regs_in_o <= d_i ^ q_a_i; + load_regs_o <= 1'b 1; + ch_a_o <= d_i ^ q_a_i; + ch_b_o <= 8'h 00; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 29 | + zw_REG_OP == 8'h 25 | zw_REG_OP == 8'h 35 | + zw_REG_OP == 8'h 2D | zw_REG_OP == 8'h 3D | + zw_REG_OP == 8'h 39 | zw_REG_OP == 8'h 21 | + zw_REG_OP == 8'h 31 | zw_REG_OP == 8'h 32 | + zw_REG_OP == 8'h D2) ) + begin + d_regs_in_o <= d_i & q_a_i; + load_regs_o <= 1'b 1; + ch_a_o <= d_i & q_a_i; + ch_b_o <= 8'h 00; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h C9 | + zw_REG_OP == 8'h C5 | zw_REG_OP == 8'h D5 | + zw_REG_OP == 8'h CD | zw_REG_OP == 8'h DD | + zw_REG_OP == 8'h D9 | zw_REG_OP == 8'h C1 | + zw_REG_OP == 8'h D1 | zw_REG_OP == 8'h C0 | + zw_REG_OP == 8'h E0 | zw_REG_OP == 8'h C4 | + zw_REG_OP == 8'h E4 | zw_REG_OP == 8'h CC | + zw_REG_OP == 8'h EC) ) + begin + zw_ALU <= {1'b 0, d_regs_out_i} + {1'b 0, (~d_i)} + + 1; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 ) + begin + d_regs_in_o <= d_i; + load_regs_o <= 1'b 1; + ch_a_o <= d_i; + ch_b_o <= 8'h 00; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G15_e1: + begin + if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 & + (zw_REG_OP == 8'h 09 | zw_REG_OP == 8'h 05 | + zw_REG_OP == 8'h 15 | zw_REG_OP == 8'h 0D | + zw_REG_OP == 8'h 1D | zw_REG_OP == 8'h 19 | + zw_REG_OP == 8'h 01 | zw_REG_OP == 8'h 11 | + zw_REG_OP == 8'h 12)) + begin + d_regs_in_o <= d_i | q_a_i; + load_regs_o <= 1'b 1; + ch_a_o <= d_i | q_a_i; + ch_b_o <= 8'h 00; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 & + (zw_REG_OP == 8'h 49 | zw_REG_OP == 8'h 45 | + zw_REG_OP == 8'h 55 | zw_REG_OP == 8'h 4D | + zw_REG_OP == 8'h 5D | zw_REG_OP == 8'h 59 | + zw_REG_OP == 8'h 41 | zw_REG_OP == 8'h 51 | + zw_REG_OP == 8'h 52) ) + begin + d_regs_in_o <= d_i ^ q_a_i; + load_regs_o <= 1'b 1; + ch_a_o <= d_i ^ q_a_i; + ch_b_o <= 8'h 00; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 & + (zw_REG_OP == 8'h 29 | zw_REG_OP == 8'h 25 | + zw_REG_OP == 8'h 35 | zw_REG_OP == 8'h 2D | + zw_REG_OP == 8'h 3D | zw_REG_OP == 8'h 39 | + zw_REG_OP == 8'h 21 | zw_REG_OP == 8'h 31 | + zw_REG_OP == 8'h 32 | zw_REG_OP == 8'h D2) ) + begin + d_regs_in_o <= d_i & q_a_i; + load_regs_o <= 1'b 1; + ch_a_o <= d_i & q_a_i; + ch_b_o <= 8'h 00; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 & + (zw_REG_OP == 8'h C9 | zw_REG_OP == 8'h C5 | + zw_REG_OP == 8'h D5 | zw_REG_OP == 8'h CD | + zw_REG_OP == 8'h DD | zw_REG_OP == 8'h D9 | + zw_REG_OP == 8'h C1 | zw_REG_OP == 8'h D1 | + zw_REG_OP == 8'h C0 | zw_REG_OP == 8'h E0 | + zw_REG_OP == 8'h C4 | zw_REG_OP == 8'h E4 | + zw_REG_OP == 8'h CC | zw_REG_OP == 8'h EC) ) + begin + zw_ALU <= {1'b 0, d_regs_out_i} + {1'b 0, (~d_i)} + + 1; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 ) + begin + d_regs_in_o <= d_i; + load_regs_o <= 1'b 1; + ch_a_o <= d_i; + ch_b_o <= 8'h 00; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G10_1: + begin + if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 65) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 69 & + reg_F[3] == 1'b 0 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + d_regs_in_o <= zw_ALU[7:0]; + load_regs_o <= 1'b 1; + zw_ALU <= {1'b 0, q_a_i} + {1'b 0, d_i} + + reg_F[0]; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 75 ) + begin + ch_a_o <= d_i; + ch_b_o <= q_x_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 6D ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 7D ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + ch_a_o <= d_i; + ch_b_o <= q_x_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 79 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + ch_a_o <= d_i; + ch_b_o <= q_y_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 71 ) + begin + ch_a_o <= d_i; + ch_b_o <= 8'h 01; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 61 ) + begin + ch_a_o <= d_i; + ch_b_o <= q_x_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 69 & + reg_F[3] == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + d_regs_in_o <= zw_ALU[7:0]; + load_regs_o <= 1'b 1; + zw_ALU[7:4] <= zw_ALU2[3:0] + zw_ALU6[2:0]; + zw_ALU[3:0] <= zw_ALU1[3:0] + zw_ALU5[2:0]; + zw_ALU6[2:0] <= {(zw_ALU2[4] | zw_ALU4[4]), (zw_ALU2[4] | zw_ALU4[4]), + 1'b 0}; + zw_ALU5[2:0] <= {(zw_ALU1[4] | zw_ALU3[4]), (zw_ALU1[4] | zw_ALU3[4]), + 1'b 0}; + zw_ALU4 <= {1'b 0, zw_ALU2[3:0]} + 6; + zw_ALU2 <= {1'b 0, q_a_i[7:4]} + {1'b 0, d_i[7:4]} + + (zw_ALU1[4] | zw_ALU3[4]); + zw_ALU3 <= {1'b 0, zw_ALU1[3:0]} + 6; + zw_ALU1 <= {1'b 0, q_a_i[3:0]} + {1'b 0, d_i[3:0]} + + reg_F[0]; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 72 ) + begin + ch_a_o <= d_i; + ch_b_o <= 8'h 01; + end + end + G10_3: + begin + if (rdy_i == 1'b 1) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G10_4: + begin + if (rdy_i == 1'b 1) + begin + ch_a_o <= d_i; + ch_b_o <= 8'h 01; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G10_5: + begin + if (rdy_i == 1'b 1) + begin + ch_a_o <= d_i; + ch_b_o <= q_y_i; + end + end + G10_2: + begin + if (rdy_i == 1'b 1) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G10_e3: + begin + if (rdy_i == 1'b 1) + begin + ch_a_o <= zw_b1; + ch_b_o <= 8'h 01; + end + end + G10_e1: + begin + if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 & + reg_F[3] == 1'b 0) + begin + d_regs_in_o <= zw_ALU[7:0]; + load_regs_o <= 1'b 1; + zw_ALU <= {1'b 0, q_a_i} + {1'b 0, d_i} + + reg_F[0]; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 & + reg_F[3] == 1'b 1 ) + begin + d_regs_in_o <= zw_ALU[7:0]; + load_regs_o <= 1'b 1; + zw_ALU[7:4] <= zw_ALU2[3:0] + zw_ALU6[2:0]; + zw_ALU[3:0] <= zw_ALU1[3:0] + zw_ALU5[2:0]; + zw_ALU6[2:0] <= {(zw_ALU2[4] | zw_ALU4[4]), (zw_ALU2[4] | zw_ALU4[4]), + 1'b 0}; + zw_ALU5[2:0] <= {(zw_ALU1[4] | zw_ALU3[4]), (zw_ALU1[4] | zw_ALU3[4]), + 1'b 0}; + zw_ALU4 <= {1'b 0, zw_ALU2[3:0]} + 6; + zw_ALU2 <= {1'b 0, q_a_i[7:4]} + {1'b 0, d_i[7:4]} + + (zw_ALU1[4] | zw_ALU3[4]); + zw_ALU3 <= {1'b 0, zw_ALU1[3:0]} + 6; + zw_ALU1 <= {1'b 0, q_a_i[3:0]} + {1'b 0, d_i[3:0]} + + reg_F[0]; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G10_e2: + begin + if (rdy_i == 1'b 1 & reg_F[3] == 1'b 0) + begin + d_regs_in_o <= zw_ALU[7:0]; + load_regs_o <= 1'b 1; + zw_ALU <= {1'b 0, q_a_i} + {1'b 0, d_i} + + reg_F[0]; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & reg_F[3] == 1'b 1 ) + begin + d_regs_in_o <= zw_ALU[7:0]; + load_regs_o <= 1'b 1; + zw_ALU[7:4] <= zw_ALU2[3:0] + zw_ALU6[2:0]; + zw_ALU[3:0] <= zw_ALU1[3:0] + zw_ALU5[2:0]; + zw_ALU6[2:0] <= {(zw_ALU2[4] | zw_ALU4[4]), (zw_ALU2[4] | zw_ALU4[4]), + 1'b 0}; + zw_ALU5[2:0] <= {(zw_ALU1[4] | zw_ALU3[4]), (zw_ALU1[4] | zw_ALU3[4]), + 1'b 0}; + zw_ALU4 <= {1'b 0, zw_ALU2[3:0]} + 6; + zw_ALU2 <= {1'b 0, q_a_i[7:4]} + {1'b 0, d_i[7:4]} + + (zw_ALU1[4] | zw_ALU3[4]); + zw_ALU3 <= {1'b 0, zw_ALU1[3:0]} + 6; + zw_ALU1 <= {1'b 0, q_a_i[3:0]} + {1'b 0, d_i[3:0]} + + reg_F[0]; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G10_6: + begin + if (rdy_i == 1'b 1) + begin + ch_a_o <= d_i; + ch_b_o <= 8'h 01; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G17_1: + begin + if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 85 | + zw_REG_OP == 8'h 86 | zw_REG_OP == 8'h 64 | + zw_REG_OP == 8'h 84)) + begin + sig_WR <= 1'b 1; + sig_D_OUT <= d_regs_out_i; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 95 | + zw_REG_OP == 8'h 74 | zw_REG_OP == 8'h 94) ) + begin + ch_a_o <= d_i; + ch_b_o <= q_x_i; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 8D | + zw_REG_OP == 8'h 8E | zw_REG_OP == 8'h 9C | + zw_REG_OP == 8'h 8C) ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 9D | + zw_REG_OP == 8'h 9E) ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + ch_a_o <= d_i; + ch_b_o <= q_x_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 99 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + ch_a_o <= d_i; + ch_b_o <= q_y_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 91 ) + begin + ch_a_o <= d_i; + ch_b_o <= 8'h 01; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 81 ) + begin + ch_a_o <= d_i; + ch_b_o <= q_x_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 96 ) + begin + ch_a_o <= d_i; + ch_b_o <= q_y_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 92 ) + begin + ch_a_o <= d_i; + ch_b_o <= 8'h 01; + end + end + G17_4: + begin + if (rdy_i == 1'b 1) + begin + ch_a_o <= d_i; + ch_b_o <= {7'b 0000000, zw_b2[0]}; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G17_6: + begin + if (rdy_i == 1'b 1) + begin + ch_a_o <= d_i; + ch_b_o <= q_y_i; + end + end + G17_3: + begin + if (rdy_i == 1'b 1) + begin + sig_WR <= 1'b 1; + sig_D_OUT <= d_regs_out_i; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G17_2: + begin + if (rdy_i == 1'b 1) + begin + sig_WR <= 1'b 1; + sig_D_OUT <= d_regs_out_i; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G17_9: + begin + if (rdy_i == 1'b 1) + begin + ch_a_o <= zw_b1; + ch_b_o <= 8'h 01; + end + end + G17_7: + begin + if (rdy_i == 1'b 1) + begin + ch_a_o <= d_i; + ch_b_o <= {7'b 0000000, zw_b2[0]}; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G17_5: + begin + sig_WR <= 1'b 1; + sig_D_OUT <= d_regs_out_i; + end + G17_10: + begin + sig_WR <= 1'b 1; + sig_D_OUT <= d_regs_out_i; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + G17_e: + begin + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + G16_1: + begin + if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E5) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E9 & + reg_F[3] == 1'b 0 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + d_regs_in_o <= zw_ALU[7:0]; + load_regs_o <= 1'b 1; + zw_ALU <= {1'b 0, q_a_i} + {1'b 0, (~d_i)} + + reg_F[0]; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F5 ) + begin + ch_a_o <= d_i; + ch_b_o <= q_x_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h ED ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h FD ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + ch_a_o <= d_i; + ch_b_o <= q_x_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F9 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + ch_a_o <= d_i; + ch_b_o <= q_y_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F1 ) + begin + ch_a_o <= d_i; + ch_b_o <= 8'h 01; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E1 ) + begin + ch_a_o <= d_i; + ch_b_o <= q_x_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h E9 & + reg_F[3] == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + d_regs_in_o <= zw_ALU[7:0]; + load_regs_o <= 1'b 1; + zw_ALU[7:4] <= zw_ALU2[3:0] + zw_ALU6; + zw_ALU[3:0] <= zw_ALU1[3:0] + zw_ALU5; + zw_ALU6 <= {(zw_ALU4[4] | ~zw_ALU2[4]), 1'b 0, (zw_ALU4[4] | + ~zw_ALU2[4]), 1'b 0}; + zw_ALU5 <= {(zw_ALU3[4] | ~zw_ALU1[4]), 1'b 0, (zw_ALU3[4] | + ~zw_ALU1[4]), 1'b 0}; + zw_ALU4 <= {1'b 0, zw_ALU2[3:0]} + 6; + zw_ALU2 <= {1'b 0, q_a_i[7:4]} + {1'b 0, (~d_i[7:4])} + + zw_ALU1[4]; + zw_ALU3 <= {1'b 0, zw_ALU1[3:0]} + 6; + zw_ALU1 <= {1'b 0, q_a_i[3:0]} + {1'b 0, (~d_i[3:0])} + + reg_F[0]; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h F2 ) + begin + ch_a_o <= d_i; + ch_b_o <= 8'h 01; + end + end + G16_3: + begin + if (rdy_i == 1'b 1) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G16_4: + begin + if (rdy_i == 1'b 1) + begin + ch_a_o <= d_i; + ch_b_o <= 8'h 01; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G16_5: + begin + if (rdy_i == 1'b 1) + begin + ch_a_o <= d_i; + ch_b_o <= q_y_i; + end + end + G16_2: + begin + if (rdy_i == 1'b 1) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G16_6: + begin + if (rdy_i == 1'b 1) + begin + ch_a_o <= d_i; + ch_b_o <= 8'h 01; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G16_e3: + begin + if (rdy_i == 1'b 1) + begin + ch_a_o <= zw_b1; + ch_b_o <= 8'h 01; + end + end + G16_e1: + begin + if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 & + reg_F[3] == 1'b 0) + begin + d_regs_in_o <= zw_ALU[7:0]; + load_regs_o <= 1'b 1; + zw_ALU <= {1'b 0, q_a_i} + {1'b 0, (~d_i)} + + reg_F[0]; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0 & + reg_F[3] == 1'b 1 ) + begin + d_regs_in_o <= zw_ALU[7:0]; + load_regs_o <= 1'b 1; + zw_ALU[7:4] <= zw_ALU2[3:0] + zw_ALU6; + zw_ALU[3:0] <= zw_ALU1[3:0] + zw_ALU5; + zw_ALU6 <= {(zw_ALU4[4] | ~zw_ALU2[4]), 1'b 0, (zw_ALU4[4] | + ~zw_ALU2[4]), 1'b 0}; + zw_ALU5 <= {(zw_ALU3[4] | ~zw_ALU1[4]), 1'b 0, (zw_ALU3[4] | + ~zw_ALU1[4]), 1'b 0}; + zw_ALU4 <= {1'b 0, zw_ALU2[3:0]} + 6; + zw_ALU2 <= {1'b 0, q_a_i[7:4]} + {1'b 0, (~d_i[7:4])} + + zw_ALU1[4]; + zw_ALU3 <= {1'b 0, zw_ALU1[3:0]} + 6; + zw_ALU1 <= {1'b 0, q_a_i[3:0]} + {1'b 0, (~d_i[3:0])} + + reg_F[0]; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G16_e2: + begin + if (rdy_i == 1'b 1 & reg_F[3] == 1'b 0) + begin + d_regs_in_o <= zw_ALU[7:0]; + load_regs_o <= 1'b 1; + zw_ALU <= {1'b 0, q_a_i} + {1'b 0, (~d_i)} + + reg_F[0]; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & reg_F[3] == 1'b 1 ) + begin + d_regs_in_o <= zw_ALU[7:0]; + load_regs_o <= 1'b 1; + zw_ALU[7:4] <= zw_ALU2[3:0] + zw_ALU6; + zw_ALU[3:0] <= zw_ALU1[3:0] + zw_ALU5; + zw_ALU6 <= {(zw_ALU4[4] | ~zw_ALU2[4]), 1'b 0, (zw_ALU4[4] | + ~zw_ALU2[4]), 1'b 0}; + zw_ALU5 <= {(zw_ALU3[4] | ~zw_ALU1[4]), 1'b 0, (zw_ALU3[4] | + ~zw_ALU1[4]), 1'b 0}; + zw_ALU4 <= {1'b 0, zw_ALU2[3:0]} + 6; + zw_ALU2 <= {1'b 0, q_a_i[7:4]} + {1'b 0, (~d_i[7:4])} + + zw_ALU1[4]; + zw_ALU3 <= {1'b 0, zw_ALU1[3:0]} + 6; + zw_ALU1 <= {1'b 0, q_a_i[3:0]} + {1'b 0, (~d_i[3:0])} + + reg_F[0]; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G11_1: + begin + if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 1E | + zw_REG_OP == 8'h 7E | zw_REG_OP == 8'h 3E | + zw_REG_OP == 8'h 5E)) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + ch_a_o <= d_i; + ch_b_o <= q_x_i; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 06 | + zw_REG_OP == 8'h 66 | zw_REG_OP == 8'h 26 | + zw_REG_OP == 8'h 46 | zw_REG_OP == 8'h 04 | + zw_REG_OP == 8'h 14) ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 16 | + zw_REG_OP == 8'h 76 | zw_REG_OP == 8'h 36 | + zw_REG_OP == 8'h 56) ) + begin + ch_a_o <= d_i; + ch_b_o <= q_x_i; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 0E | + zw_REG_OP == 8'h 6E | zw_REG_OP == 8'h 2E | + zw_REG_OP == 8'h 4E | zw_REG_OP == 8'h 0C | + zw_REG_OP == 8'h 1C) ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_REG_OP[3:0] == 4'h 7 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G11_5: + begin + if (rdy_i == 1'b 1) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G11_6: + begin + if (rdy_i == 1'b 1) + begin + ch_a_o <= d_i; + ch_b_o <= {7'b 0000000, zw_b2[0]}; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G11_2: + begin + if (rdy_i == 1'b 1) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G11_4: + begin + if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 06 | + zw_REG_OP == 8'h 16 | zw_REG_OP == 8'h 0E | + zw_REG_OP == 8'h 1E)) + begin + sig_D_OUT <= {d_i[6:0], 1'b 0}; + sig_WR <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 46 | + zw_REG_OP == 8'h 56 | zw_REG_OP == 8'h 4E | + zw_REG_OP == 8'h 5E) ) + begin + sig_D_OUT <= {1'b 0, d_i[7:1]}; + sig_WR <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 26 | + zw_REG_OP == 8'h 36 | zw_REG_OP == 8'h 2E | + zw_REG_OP == 8'h 3E) ) + begin + sig_D_OUT <= {d_i[6:0], reg_F[0]}; + sig_WR <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 66 | + zw_REG_OP == 8'h 76 | zw_REG_OP == 8'h 6E | + zw_REG_OP == 8'h 7E) ) + begin + sig_D_OUT <= {reg_F[0], d_i[7:1]}; + sig_WR <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_REG_OP[7] == 1'b 0 & + zw_REG_OP[3:0] == 4'h 7 ) + begin + sig_D_OUT <= d_i & ~alu_dec_val_i; + ch_a_o <= {5'b 00000, zw_REG_OP[6:4]}; + sig_WR <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_REG_OP[7] == 1'b 1 & + zw_REG_OP[3:0] == 4'h 7 ) + begin + sig_D_OUT <= d_i | alu_dec_val_i; + ch_a_o <= {5'b 00000, zw_REG_OP[6:4]}; + sig_WR <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 14 | + zw_REG_OP == 8'h 1C) ) + begin + sig_D_OUT <= d_i & ~q_a_i; + sig_WR <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 04 | + zw_REG_OP == 8'h 0C) ) + begin + sig_D_OUT <= d_i | q_a_i; + sig_WR <= 1'b 1; + end + end + G11_e: + begin + if (zw_REG_OP[3:0] == 4'h 7) + begin + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else if (zw_REG_OP == 8'h 14 | zw_REG_OP == 8'h 04 | + zw_REG_OP == 8'h 0C | zw_REG_OP == 8'h 1C ) + begin + ch_a_o <= zw_b1; + ch_b_o <= 8'h 00; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else + begin + ch_a_o <= zw_b1; + ch_b_o <= 8'h 00; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G31_1: + begin + if (rdy_i == 1'b 1) + begin + ch_a_o <= {q_a_i[6:0], 1'b 0}; + ch_b_o <= 8'h 00; + d_regs_in_o <= {q_a_i[6:0], 1'b 0}; + load_regs_o <= 1'b 1; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G34_1: + begin + if (rdy_i == 1'b 1) + begin + ch_a_o <= {reg_F[0], q_a_i[7:1]}; + ch_b_o <= 8'h 00; + d_regs_in_o <= {reg_F[0], q_a_i[7:1]}; + load_regs_o <= 1'b 1; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G32_1: + begin + if (rdy_i == 1'b 1) + begin + ch_a_o <= {1'b 0, q_a_i[7:1]}; + ch_b_o <= 8'h 00; + d_regs_in_o <= {1'b 0, q_a_i[7:1]}; + load_regs_o <= 1'b 1; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G33_1: + begin + if (rdy_i == 1'b 1) + begin + ch_a_o <= {q_a_i[6:0], reg_F[0]}; + ch_b_o <= 8'h 00; + d_regs_in_o <= {q_a_i[6:0], reg_F[0]}; + load_regs_o <= 1'b 1; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G12_1: + begin + if (rdy_i == 1'b 1 & (reg_F[0] == 1'b 1 & + zw_REG_OP == 8'h 90 | reg_F[0] == 1'b 0 & + zw_REG_OP == 8'h B0 | reg_F[1] == 1'b 0 & + zw_REG_OP == 8'h F0 | reg_F[7] == 1'b 0 & + zw_REG_OP == 8'h 30 | reg_F[1] == 1'b 1 & + zw_REG_OP == 8'h D0 | reg_F[7] == 1'b 1 & + zw_REG_OP == 8'h 10 | reg_F[6] == 1'b 1 & + zw_REG_OP == 8'h 50 | reg_F[6] == 1'b 0 & + zw_REG_OP == 8'h 70)) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h 8F | + zw_REG_OP == 8'h 9F | zw_REG_OP == 8'h AF | + zw_REG_OP == 8'h BF | zw_REG_OP == 8'h CF | + zw_REG_OP == 8'h DF | zw_REG_OP == 8'h EF | + zw_REG_OP == 8'h FF | zw_REG_OP == 8'h 0F | + zw_REG_OP == 8'h 1F | zw_REG_OP == 8'h 2F | + zw_REG_OP == 8'h 3F | zw_REG_OP == 8'h 4F | + zw_REG_OP == 8'h 5F | zw_REG_OP == 8'h 6F | + zw_REG_OP == 8'h 7F) ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G12_e1: + begin + if (rdy_i == 1'b 1 & zw_b3 == adr_nxt_pc_i[15:8]) + begin + offset_o <= {zw_b2[7], zw_b2[7], zw_b2[7], zw_b2[7], + zw_b2[7], zw_b2[7], zw_b2[7], zw_b2[7], + zw_b2[7], zw_b2[6:0]}; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 ) + begin + offset_o <= {zw_b2[7], zw_b2[7], zw_b2[7], zw_b2[7], + zw_b2[7], zw_b2[7], zw_b2[7], zw_b2[7], + zw_b2[7], zw_b2[6:0]}; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G12_e2: + begin + if (rdy_i == 1'b 1) + begin + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G12_3: + begin + if (rdy_i == 1'b 1 & (d_i[0] == 1'b 1 & + zw_REG_OP == 8'h 8F | d_i[1] == 1'b 1 & + zw_REG_OP == 8'h 9F | d_i[2] == 1'b 1 & + zw_REG_OP == 8'h AF | d_i[3] == 1'b 1 & + zw_REG_OP == 8'h BF | d_i[4] == 1'b 1 & + zw_REG_OP == 8'h CF | d_i[5] == 1'b 1 & + zw_REG_OP == 8'h DF | d_i[6] == 1'b 1 & + zw_REG_OP == 8'h EF | d_i[7] == 1'b 1 & + zw_REG_OP == 8'h FF | d_i[0] == 1'b 0 & + zw_REG_OP == 8'h 0F | d_i[1] == 1'b 0 & + zw_REG_OP == 8'h 1F | d_i[2] == 1'b 0 & + zw_REG_OP == 8'h 2F | d_i[3] == 1'b 0 & + zw_REG_OP == 8'h 3F | d_i[4] == 1'b 0 & + zw_REG_OP == 8'h 4F | d_i[5] == 1'b 0 & + zw_REG_OP == 8'h 5F | d_i[6] == 1'b 0 & + zw_REG_OP == 8'h 6F | d_i[7] == 1'b 0 & + zw_REG_OP == 8'h 7F)) + ; + else if (rdy_i == 1'b 1 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G12_4: + begin + if (rdy_i == 1'b 1) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G20_2: + begin + if (rdy_i == 1'b 1) + begin + adr_o <= {d_i, zw_b1}; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G20_e: + begin + if (rdy_i == 1'b 1) + begin + adr_o <= {d_i, zw_b1}; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G20_3: + begin + if (rdy_i == 1'b 1) + begin + adr_o <= {d_i, zw_b1}; + offset_o <= {8'h 00, q_x_i}; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G21_1: + begin + if (rdy_i == 1'b 1) + begin + ld_o <= 2'b 11; + ld_sp_o <= 1'b 1; + ld_pc_o <= 1'b 1; + end + end + G21_2: + begin + if (rdy_i == 1'b 1) + begin + sig_WR <= 1'b 1; + sig_D_OUT <= adr_pc_i[15:8]; + end + end + G21_3: + begin + ld_o <= 2'b 11; + ld_sp_o <= 1'b 1; + sig_WR <= 1'b 1; + sig_D_OUT <= adr_pc_i[7:0]; + end + G21_e: + begin + if (rdy_i == 1'b 1) + begin + adr_o <= {d_i, zw_b1}; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G13_3: + begin + if (rdy_i == 1'b 1) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G13_1: + begin + if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 34) + begin + ch_a_o <= d_i; + ch_b_o <= q_x_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 3C ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + ch_a_o <= d_i; + ch_b_o <= q_x_i; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 24 ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 2C ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & zw_REG_OP == 8'h 89 ) + begin + ch_a_o <= q_a_i & d_i; + ch_b_o <= 8'h 00; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G13_4: + begin + if (rdy_i == 1'b 1) + begin + ch_a_o <= d_i; + ch_b_o <= {7'b 0000000, zw_b2[0]}; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G13_2: + begin + if (rdy_i == 1'b 1) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G13_e1: + begin + if (rdy_i == 1'b 1) + begin + ch_a_o <= q_a_i & d_i; + ch_b_o <= 8'h 00; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G13_e2: + begin + if (rdy_i == 1'b 1 & zw_b2[0] == 1'b 0) + begin + ch_a_o <= q_a_i & d_i; + ch_b_o <= 8'h 00; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G18_1: + begin + if (rdy_i == 1'b 1) + begin + ld_o <= 2'b 11; + ld_sp_o <= 1'b 1; + sig_WR <= 1'b 1; + sig_D_OUT <= adr_nxt_pc_i[15:8]; + end + end + G18_2: + begin + ld_o <= 2'b 11; + ld_sp_o <= 1'b 1; + sig_WR <= 1'b 1; + sig_D_OUT <= adr_nxt_pc_i[7:0]; + end + G18_3: + begin + ld_o <= 2'b 11; + ld_sp_o <= 1'b 1; + sig_WR <= 1'b 1; + sig_D_OUT <= reg_F | 8'h 10; + end + G18_e: + begin + if (rdy_i == 1'b 1) + begin + adr_o <= {d_i, zw_b1}; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G26_1: + begin + if (rdy_i == 1'b 1) + begin + ld_o <= 2'b 11; + ld_sp_o <= 1'b 1; + end + end + G26_2: + begin + if (rdy_i == 1'b 1) + begin + ld_o <= 2'b 11; + ld_sp_o <= 1'b 1; + end + end + G26_3: + begin + if (rdy_i == 1'b 1) + begin + ld_o <= 2'b 11; + ld_sp_o <= 1'b 1; + end + end + G26_e: + begin + if (rdy_i == 1'b 1) + begin + adr_o <= {d_i, zw_b1}; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G27_1: + begin + if (rdy_i == 1'b 1) + begin + ld_o <= 2'b 11; + ld_sp_o <= 1'b 1; + end + end + G27_2: + begin + if (rdy_i == 1'b 1) + begin + ld_o <= 2'b 11; + ld_sp_o <= 1'b 1; + end + end + G27_4: + begin + if (rdy_i == 1'b 1) + begin + adr_o <= {d_i, zw_b1}; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G27_e: + begin + if (rdy_i == 1'b 1) + begin + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G14_1: + begin + if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h C6 | + zw_REG_OP == 8'h E6)) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h D6 | + zw_REG_OP == 8'h F6) ) + begin + ch_a_o <= d_i; + ch_b_o <= q_x_i; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h CE | + zw_REG_OP == 8'h EE) ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + else if (rdy_i == 1'b 1 & (zw_REG_OP == 8'h DE | + zw_REG_OP == 8'h FE) ) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + ch_a_o <= d_i; + ch_b_o <= q_x_i; + end + end + G14_5: + begin + if (rdy_i == 1'b 1) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G14_6: + begin + if (rdy_i == 1'b 1) + begin + ch_a_o <= d_i; + ch_b_o <= {7'b 0000000, zw_b2[0]}; + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G14_2: + begin + if (rdy_i == 1'b 1) + begin + ld_o <= 2'b 11; + ld_pc_o <= 1'b 1; + end + end + G14_3: + begin + if (rdy_i == 1'b 1) + begin + ch_a_o <= d_i; + ch_b_o <= zw_b4; + end + end + G14_4: + begin + if (rdy_i == 1'b 1) + begin + sig_WR <= 1'b 1; + sig_D_OUT <= zw_b1; + end + end + G14_e: + begin + ch_a_o <= zw_b1; + ch_b_o <= 8'h 00; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + G22_1: + begin + if (rdy_i == 1'b 1) + begin + sig_WR <= 1'b 1; + sig_D_OUT <= d_regs_out_i; + ld_o <= 2'b 11; + ld_sp_o <= 1'b 1; + end + end + G22_e: + begin + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + G23_1: + begin + if (rdy_i == 1'b 1) + begin + sig_WR <= 1'b 1; + sig_D_OUT <= reg_F; + ld_o <= 2'b 11; + ld_sp_o <= 1'b 1; + end + end + G23_e: + begin + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + G24_1: + begin + if (rdy_i == 1'b 1) + begin + ld_o <= 2'b 11; + ld_sp_o <= 1'b 1; + end + end + G24_e: + begin + if (rdy_i == 1'b 1) + begin + d_regs_in_o <= d_i; + load_regs_o <= 1'b 1; + ch_a_o <= d_i; + ch_b_o <= 8'h 00; + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + G25_1: + begin + if (rdy_i == 1'b 1) + begin + ld_o <= 2'b 11; + ld_sp_o <= 1'b 1; + end + end + G25_e: + begin + if (rdy_i == 1'b 1) + begin + sig_SYNC <= 1'b 1; + fetch_o <= 1'b 1; + end + end + default: + ; + endcase + end + +// Concurrent Statements +// Clocked output assignments + +// --------------------------------------------------------------- +// Default Assignment +assign d_o = d_o_cld; +assign rd_o = rd_o_cld; +assign sync_o = sync_o_cld; +assign wr_o = wr_o_cld; + +// Architecture Declarations + +endmodule // module FSM_Execution_Unit +
trunk/rtl/Verilog/fsm_execution_unit.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/rtl/Verilog/r65c02_tc.v =================================================================== --- trunk/rtl/Verilog/r65c02_tc.v (nonexistent) +++ trunk/rtl/Verilog/r65c02_tc.v (revision 13) @@ -0,0 +1,107 @@ +`define false 1'b 0 +`define FALSE 1'b 0 +`define true 1'b 1 +`define TRUE 1'b 1 + +`timescale 1 ns / 1 ns // timescale for following modules + + +// VHDL Entity R65C02_TC.R65C02_TC.symbol +// +// Created: +// by - eda.UNKNOWN (ENTWICKL4-XP-PR) +// at - 15:22:46 25.02.2009 +// +// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +// + +module R65C02_TC ( + clk_clk_i, + d_i, + irq_n_i, + nmi_n_i, + rdy_i, + rst_rst_n_i, + so_n_i, + a_o, + d_o, + rd_o, + sync_o, + wr_o); + + +input clk_clk_i; +input [7:0] d_i; +input irq_n_i; +input nmi_n_i; +input rdy_i; +input rst_rst_n_i; +input so_n_i; +output [15:0] a_o; +output [7:0] d_o; +output rd_o; +output sync_o; +output wr_o; + + +// Jens-D. Gutschmidt Project: R65C02_TC +// scantara2003@yahoo.de +// COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG +// +// This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along with this program. If not, see . +// +// CVS Revisins History +// +// $Log: not supported by cvs2svn $ +// <<-- more -->> +// Title: Top Level +// Path: R65C02_TC/R65C02_TC/struct +// Edited: by eda on 10 Feb 2009 +// +// VHDL Architecture R65C02_TC.R65C02_TC.struct +// +// Created: +// by - eda.UNKNOWN (ENTWICKL4-XP-PR) +// at - 15:22:46 25.02.2009 +// +// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +// +wire [15:0] a_o; +wire [7:0] d_o; +wire rd_o; +wire sync_o; +wire wr_o; + +// Declarations + +// Optional embedded configurations +// pragma synthesis_off + +// pragma synthesis_on +// Instance port mappings. + +Core U_0 (.clk_clk_i(clk_clk_i), + .d_i(d_i), + .irq_n_i(irq_n_i), + .nmi_n_i(nmi_n_i), + .rdy_i(rdy_i), + .rst_rst_n_i(rst_rst_n_i), + .so_n_i(so_n_i), + .a_o(a_o), + .d_o(d_o), + .rd_o(rd_o), + .sync_o(sync_o), + .wr_o(wr_o)); + +// Architecture declarations +// Internal signal declarations +// Component Declarations + +endmodule // module R65C02_TC +
trunk/rtl/Verilog/r65c02_tc.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/rtl/Verilog/core.v =================================================================== --- trunk/rtl/Verilog/core.v (nonexistent) +++ trunk/rtl/Verilog/core.v (revision 13) @@ -0,0 +1,280 @@ +`define false 1'b 0 +`define FALSE 1'b 0 +`define true 1'b 1 +`define TRUE 1'b 1 + +`timescale 1 ns / 1 ns // timescale for following modules + + +// VHDL Entity R65C02_TC.Core.symbol +// +// Created: +// by - eda.UNKNOWN (ENTWICKL4-XP-PR) +// at - 15:22:45 25.02.2009 +// +// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +// + +module Core ( + clk_clk_i, + d_i, + irq_n_i, + nmi_n_i, + rdy_i, + rst_rst_n_i, + so_n_i, + a_o, + d_o, + rd_o, + sync_o, + wr_o); + + +input clk_clk_i; +input [7:0] d_i; +input irq_n_i; +input nmi_n_i; +input rdy_i; +input rst_rst_n_i; +input so_n_i; +output [15:0] a_o; +output [7:0] d_o; +output rd_o; +output sync_o; +output wr_o; + + +// Jens-D. Gutschmidt Project: R65C02_TC +// scantara2003@yahoo.de +// COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG +// +// This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version +// 3 of the License, or any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A +// PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along with this program. If not, see . +// +// CVS Revisins History +// +// $Log: not supported by cvs2svn $ +// <<-- more -->> +// Title: Core +// Path: R65C02_TC/Core/struct +// Edited: by eda on 23 Feb 2009 +// +// VHDL Architecture R65C02_TC.Core.struct +// +// Created: +// by - eda.UNKNOWN (ENTWICKL4-XP-PR) +// at - 15:22:46 25.02.2009 +// +// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +// +wire [15:0] a_o; +wire [7:0] d_o; +wire rd_o; +wire sync_o; +wire wr_o; + +// Declarations +wire [15:0] adr_nxt_pc_o_i; +wire [15:0] adr_o_i; +wire [15:0] adr_pc_o_i; +wire [15:0] adr_sp_o_i; +reg [7:0] alu_dec_val_o_i; +wire [7:0] ch_a_o_i; +wire [7:0] ch_b_o_i; +wire d_alu_n_o_i; +wire [7:0] d_alu_o_i; +wire d_alu_or_o_i; +wire [7:0] d_regs_in_o_i; +wire [7:0] d_regs_out_o_i; +wire fetch_o_i; +wire [1:0] ld_o_i; +wire ld_pc_o_i; +wire ld_sp_o_i; +wire load_regs_o_i; +wire nmi_o_i; +wire [15:0] offset_o_i; +wire [7:0] q_a_o_i; +wire [7:0] q_x_o_i; +wire [7:0] q_y_o_i; +wire reg_0flag_o_i; +wire reg_1flag_o_i; +wire reg_7flag_o_i; +wire sel_pc_in_o_i; +wire [1:0] sel_pc_val_o_i; +wire [1:0] sel_rb_in_o_i; +wire [1:0] sel_rb_out_o_i; +wire [1:0] sel_reg_o_i; +wire sel_sp_as_o_i; +wire sel_sp_in_o_i; + +// ModuleWare signal declarations(v1.9) for instance 'U_11' of 'add' +wire [8:0] mw_U_11temp_din0; +wire [8:0] mw_U_11temp_din1; +reg [8:0] mw_U_11sum; + +// Component Declarations + +// Optional embedded configurations +// pragma synthesis_off + +// pragma synthesis_on +// ModuleWare code(v1.9) for instance 'U_11' of 'add' +reg u_11combo_proc_temp_carry; + +assign mw_U_11temp_din0 = {1'b 0, ch_a_o_i}; +assign mw_U_11temp_din1 = {1'b 0, ch_b_o_i}; + +always @(mw_U_11temp_din0 or mw_U_11temp_din1) + begin : u_11combo_proc + u_11combo_proc_temp_carry = 1'b 0; + mw_U_11sum <= mw_U_11temp_din0 + mw_U_11temp_din1 + u_11combo_proc_temp_carry; + end + +assign d_alu_o_i = mw_U_11sum[7:0]; +assign reg_0flag_o_i = mw_U_11sum[8]; + +// ModuleWare code(v1.9) for instance 'U_5' of 'decoder1' + +always @(d_alu_o_i[2:0]) + begin : u_5combo_proc + alu_dec_val_o_i <= {8{1'b 0}}; + case (d_alu_o_i[2:0]) + 3'b 000: + begin + alu_dec_val_o_i[0] <= 1'b 1; + end + 3'b 001: + begin + alu_dec_val_o_i[1] <= 1'b 1; + end + 3'b 010: + begin + alu_dec_val_o_i[2] <= 1'b 1; + end + 3'b 011: + begin + alu_dec_val_o_i[3] <= 1'b 1; + end + 3'b 100: + begin + alu_dec_val_o_i[4] <= 1'b 1; + end + 3'b 101: + begin + alu_dec_val_o_i[5] <= 1'b 1; + end + 3'b 110: + begin + alu_dec_val_o_i[6] <= 1'b 1; + end + 3'b 111: + begin + alu_dec_val_o_i[7] <= 1'b 1; + end + default: + begin + alu_dec_val_o_i <= {8{1'b 0}}; + end + endcase + end + +// ModuleWare code(v1.9) for instance 'U_8' of 'inv' +assign reg_1flag_o_i = ~d_alu_or_o_i; + +// ModuleWare code(v1.9) for instance 'U_9' of 'inv' +assign reg_7flag_o_i = ~d_alu_n_o_i; + +// ModuleWare code(v1.9) for instance 'U_10' of 'inv' +assign d_alu_n_o_i = ~d_alu_o_i[7]; + +// ModuleWare code(v1.9) for instance 'U_7' of 'por' +assign d_alu_or_o_i = d_alu_o_i[0] | d_alu_o_i[1] | d_alu_o_i[2] | d_alu_o_i[3] | + d_alu_o_i[4] | d_alu_o_i[5] | d_alu_o_i[6] | d_alu_o_i[7]; + +// Instance port mappings. +FSM_Execution_Unit U_4 (.adr_nxt_pc_i(adr_nxt_pc_o_i), + .adr_pc_i(adr_pc_o_i), + .adr_sp_i(adr_sp_o_i), + .alu_dec_val_i(alu_dec_val_o_i), + .clk_clk_i(clk_clk_i), + .d_alu_i(d_alu_o_i), + .d_i(d_i), + .d_regs_out_i(d_regs_out_o_i), + .irq_n_i(irq_n_i), + .nmi_i(nmi_o_i), + .q_a_i(q_a_o_i), + .q_x_i(q_x_o_i), + .q_y_i(q_y_o_i), + .rdy_i(rdy_i), + .reg_0flag_i(reg_0flag_o_i), + .reg_1flag_i(reg_1flag_o_i), + .reg_7flag_i(reg_7flag_o_i), + .rst_rst_n_i(rst_rst_n_i), + .so_n_i(so_n_i), + .a_o(a_o), + .adr_o(adr_o_i), + .ch_a_o(ch_a_o_i), + .ch_b_o(ch_b_o_i), + .d_o(d_o), + .d_regs_in_o(d_regs_in_o_i), + .fetch_o(fetch_o_i), + .ld_o(ld_o_i), + .ld_pc_o(ld_pc_o_i), + .ld_sp_o(ld_sp_o_i), + .load_regs_o(load_regs_o_i), + .offset_o(offset_o_i), + .rd_o(rd_o), + .sel_pc_in_o(sel_pc_in_o_i), + .sel_pc_val_o(sel_pc_val_o_i), + .sel_rb_in_o(sel_rb_in_o_i), + .sel_rb_out_o(sel_rb_out_o_i), + .sel_reg_o(sel_reg_o_i), + .sel_sp_as_o(sel_sp_as_o_i), + .sel_sp_in_o(sel_sp_in_o_i), + .sync_o(sync_o), + .wr_o(wr_o)); +FSM_NMI U_3 (.clk_clk_i(clk_clk_i), + .fetch_i(fetch_o_i), + .nmi_n_i(nmi_n_i), + .rst_rst_n_i(rst_rst_n_i), + .nmi_o(nmi_o_i)); +RegBank_AXY U_2 (.clk_clk_i(clk_clk_i), + .d_regs_in_i(d_regs_in_o_i), + .load_regs_i(load_regs_o_i), + .rst_rst_n_i(rst_rst_n_i), + .sel_rb_in_i(sel_rb_in_o_i), + .sel_rb_out_i(sel_rb_out_o_i), + .sel_reg_i(sel_reg_o_i), + .d_regs_out_o(d_regs_out_o_i), + .q_a_o(q_a_o_i), + .q_x_o(q_x_o_i), + .q_y_o(q_y_o_i)); +Reg_PC U_0 (.adr_i(adr_o_i), + .clk_clk_i(clk_clk_i), + .ld_i(ld_o_i), + .ld_pc_i(ld_pc_o_i), + .offset_i(offset_o_i), + .rst_rst_n_i(rst_rst_n_i), + .sel_pc_in_i(sel_pc_in_o_i), + .sel_pc_val_i(sel_pc_val_o_i), + .adr_nxt_pc_o(adr_nxt_pc_o_i), + .adr_pc_o(adr_pc_o_i)); +Reg_SP U_1 (.adr_low_i(adr_o_i[7:0]), + .clk_clk_i(clk_clk_i), + .ld_low_i(ld_o_i[0]), + .ld_sp_i(ld_sp_o_i), + .rst_rst_n_i(rst_rst_n_i), + .sel_sp_as_i(sel_sp_as_o_i), + .sel_sp_in_i(sel_sp_in_o_i), + .adr_sp_o(adr_sp_o_i)); + +// Architecture declarations +// Internal signal declarations + +endmodule // module Core +
trunk/rtl/Verilog/core.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/rtl/Verilog/fsm_nmi.v =================================================================== --- trunk/rtl/Verilog/fsm_nmi.v (nonexistent) +++ trunk/rtl/Verilog/fsm_nmi.v (revision 13) @@ -0,0 +1,176 @@ +`define false 1'b 0 +`define FALSE 1'b 0 +`define true 1'b 1 +`define TRUE 1'b 1 + +`timescale 1 ns / 1 ns // timescale for following modules + + +// VHDL Entity R65C02_TC.FSM_NMI.symbol +// +// Created: +// by - eda.UNKNOWN (ENTWICKL4-XP-PR) +// at - 15:22:29 25.02.2009 +// +// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +// + +module FSM_NMI ( + clk_clk_i, + fetch_i, + nmi_n_i, + rst_rst_n_i, + nmi_o); + + +input clk_clk_i; +input fetch_i; +input nmi_n_i; +input rst_rst_n_i; +output nmi_o; + + +// Jens-D. Gutschmidt Project: R65C02_TC +// scantara2003@yahoo.de +// COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG +// +// This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along with this program. If not, see . +// +// CVS Revisins History +// +// $Log: not supported by cvs2svn $ +// <<-- more -->> +// Title: FSM for NMI +// Path: R65C02_TC/FSM_NMI/fsm +// Edited: by eda on 10 Feb 2009 +// +// VHDL Architecture R65C02_TC.FSM_NMI.fsm +// +// Created: +// by - eda.UNKNOWN (ENTWICKL4-XP-PR) +// at - 15:22:30 25.02.2009 +// +// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +// +wire nmi_o; + +// Declarations + +// TYPE state_type: +parameter state_type_idle = 0; +parameter state_type_idle1 = 1; +parameter state_type_idle2 = 2; +parameter state_type_IMP = 3; + + +// Declare current and next state signals +reg [1:0] current_state; +reg [1:0] next_state; + +// Declare any pre-registered internal signals +reg nmi_o_cld; + +// --------------------------------------------------------------- + + +always @(posedge clk_clk_i or negedge rst_rst_n_i) + begin : clocked_proc + if (rst_rst_n_i == 1'b 0) + begin + current_state <= state_type_idle; + +// Default Reset Values + nmi_o_cld <= 1'b 0; + end + else + begin + current_state <= next_state; + +// Default Assignment To Internals + nmi_o_cld <= 1'b 0; + +// Combined Actions + case (current_state) + state_type_IMP: + begin + nmi_o_cld <= 1'b 1; + end + default: + ; + endcase + end + end + +// --------------------------------------------------------------- + +// --------------------------------------------------------------- + +always @(current_state or fetch_i or nmi_n_i) + begin : nextstate_proc + case (current_state) + state_type_idle: + begin + if (nmi_n_i == 1'b 1) + begin + next_state <= state_type_idle1; +// <<< REQ1 + end + else + begin + next_state <= state_type_idle; + end + end + state_type_idle1: + begin + if (nmi_n_i == 1'b 0) + begin + next_state <= state_type_idle2; + end + else + begin + next_state <= state_type_idle1; + end + end + state_type_idle2: + begin + if (nmi_n_i == 1'b 0) + begin + next_state <= state_type_IMP; + end + else + begin + next_state <= state_type_idle; + end + end + state_type_IMP: + begin + if (fetch_i == 1'b 1) + begin + next_state <= state_type_idle; + end + else + begin + next_state <= state_type_IMP; + end + end + default: + begin + next_state <= state_type_idle; + end + endcase + end + +// Concurrent Statements +// Clocked output assignments + +// --------------------------------------------------------------- +assign nmi_o = nmi_o_cld; + +endmodule // module FSM_NMI +
trunk/rtl/Verilog/fsm_nmi.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/rtl/Verilog/regbank_axy.v =================================================================== --- trunk/rtl/Verilog/regbank_axy.v (nonexistent) +++ trunk/rtl/Verilog/regbank_axy.v (revision 13) @@ -0,0 +1,258 @@ +`define false 1'b 0 +`define FALSE 1'b 0 +`define true 1'b 1 +`define TRUE 1'b 1 + +`timescale 1 ns / 1 ns // timescale for following modules + + +// VHDL Entity R65C02_TC.RegBank_AXY.symbol +// +// Created: +// by - eda.UNKNOWN (ENTWICKL4-XP-PR) +// at - 15:22:29 25.02.2009 +// +// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +// + +module RegBank_AXY ( + clk_clk_i, + d_regs_in_i, + load_regs_i, + rst_rst_n_i, + sel_rb_in_i, + sel_rb_out_i, + sel_reg_i, + d_regs_out_o, + q_a_o, + q_x_o, + q_y_o); + + +input clk_clk_i; +input [7:0] d_regs_in_i; +input load_regs_i; +input rst_rst_n_i; +input [1:0] sel_rb_in_i; +input [1:0] sel_rb_out_i; +input [1:0] sel_reg_i; +output [7:0] d_regs_out_o; +output [7:0] q_a_o; +output [7:0] q_x_o; +output [7:0] q_y_o; + + +// Jens-D. Gutschmidt Project: R65C02_TC +// scantara2003@yahoo.de +// COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG +// +// This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along with this program. If not, see . +// +// CVS Revisins History +// +// $Log: not supported by cvs2svn $ +// <<-- more -->> +// Title: Register Bank for register A, X and Y +// Path: R65C02_TC/RegBank_AXY/struct +// Edited: by eda on 10 Feb 2009 +// +// VHDL Architecture R65C02_TC.RegBank_AXY.struct +// +// Created: +// by - eda.UNKNOWN (ENTWICKL4-XP-PR) +// at - 15:22:29 25.02.2009 +// +// Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +// +reg [7:0] d_regs_out_o; +wire [7:0] q_a_o; +wire [7:0] q_x_o; +wire [7:0] q_y_o; + +// Declarations +reg [2:0] ld; +wire load1_o_i; +wire load2_o_i; +wire load_o_i; +reg [7:0] q_mux_o_i; +wire [7:0] val_zero; + +// Implicit buffer signal declarations +wire [7:0] q_a_o_internal; +wire [7:0] q_x_o_internal; +wire [7:0] q_y_o_internal; + +// ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff' +reg [7:0] mw_U_0reg_cval; + +// ModuleWare signal declarations(v1.9) for instance 'U_4' of 'adff' +reg [7:0] mw_U_4reg_cval; + +// ModuleWare signal declarations(v1.9) for instance 'U_5' of 'adff' +reg [7:0] mw_U_5reg_cval; + +// ModuleWare code(v1.9) for instance 'U_0' of 'adff' + +assign q_a_o_internal = mw_U_0reg_cval; + +always @(posedge clk_clk_i or negedge rst_rst_n_i) + begin : u_0seq_proc + if (rst_rst_n_i == 1'b 0) + begin + mw_U_0reg_cval <= 8'b 00000000; + end + else + begin + if (load_o_i == 1'b 1) + begin + mw_U_0reg_cval <= q_mux_o_i; + end + end + end + +// ModuleWare code(v1.9) for instance 'U_4' of 'adff' +assign q_x_o_internal = mw_U_4reg_cval; + +always @(posedge clk_clk_i or negedge rst_rst_n_i) + begin : u_4seq_proc + if (rst_rst_n_i == 1'b 0) + begin + mw_U_4reg_cval <= 8'b 00000000; + end + else + begin + if (load1_o_i == 1'b 1) + begin + mw_U_4reg_cval <= q_mux_o_i; + end + end + end + +// ModuleWare code(v1.9) for instance 'U_5' of 'adff' +assign q_y_o_internal = mw_U_5reg_cval; + +always @(posedge clk_clk_i or negedge rst_rst_n_i) + begin : u_5seq_proc + if (rst_rst_n_i == 1'b 0) + begin + mw_U_5reg_cval <= 8'b 00000000; + end + else + begin + if (load2_o_i == 1'b 1) + begin + mw_U_5reg_cval <= q_mux_o_i; + end + end + end + +// ModuleWare code(v1.9) for instance 'U_6' of 'and' +assign load_o_i = load_regs_i & ld[0]; + +// ModuleWare code(v1.9) for instance 'U_7' of 'and' +assign load1_o_i = load_regs_i & ld[1]; + +// ModuleWare code(v1.9) for instance 'U_8' of 'and' +assign load2_o_i = load_regs_i & ld[2]; + +// ModuleWare code(v1.9) for instance 'U_11' of 'constval' +assign val_zero = 8'b 00000000; + +// ModuleWare code(v1.9) for instance 'U_1' of 'decoder1' + +always @(sel_reg_i) + begin : u_1combo_proc + ld <= {3{1'b 0}}; + case (sel_reg_i) + 2'b 00: + begin + ld[0] <= 1'b 1; + end + 2'b 01: + begin + ld[1] <= 1'b 1; + end + 2'b 10: + begin + ld[2] <= 1'b 1; + end + default: + begin + ld <= {3{1'b 0}}; + end + endcase + end + +// ModuleWare code(v1.9) for instance 'U_2' of 'mux' + +always @(q_a_o_internal or q_x_o_internal or q_y_o_internal or val_zero or sel_rb_out_i) + begin : u_2combo_proc + case (sel_rb_out_i) + 2'b 00: + begin + d_regs_out_o <= q_a_o_internal; + end + 2'b 01: + begin + d_regs_out_o <= q_x_o_internal; + end + 2'b 10: + begin + d_regs_out_o <= q_y_o_internal; + end + 2'b 11: + begin + d_regs_out_o <= val_zero; + end + default: + begin + d_regs_out_o <= {8{1'b X}}; + end + endcase + end + +// ModuleWare code(v1.9) for instance 'U_3' of 'mux' + +always @(q_a_o_internal or q_y_o_internal or q_x_o_internal or d_regs_in_i or sel_rb_in_i) + begin : u_3combo_proc + case (sel_rb_in_i) + 2'b 00: + begin + q_mux_o_i <= q_a_o_internal; + end + 2'b 01: + begin + q_mux_o_i <= q_y_o_internal; + end + 2'b 10: + begin + q_mux_o_i <= q_x_o_internal; + end + 2'b 11: + begin + q_mux_o_i <= d_regs_in_i; + end + default: + begin + q_mux_o_i <= {8{1'b X}}; + end + endcase + end + +// Instance port mappings. +// Implicit buffered output assignments +assign q_a_o = q_a_o_internal; +assign q_x_o = q_x_o_internal; +assign q_y_o = q_y_o_internal; + +// Architecture declarations +// Internal signal declarations + +endmodule // module RegBank_AXY +
trunk/rtl/Verilog/regbank_axy.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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