URL
https://opencores.org/ocsvn/cpu65c02_true_cycle/cpu65c02_true_cycle/trunk
Subversion Repositories cpu65c02_true_cycle
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Rev 21 → Rev 22
/cpu65c02_true_cycle/trunk/doc/HTML_r65c02_tc.7z
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/cpu65c02_true_cycle/trunk/rtl/vhdl/fsm_execution_unit.vhd
64,6 → 64,8
-- (email: opencores@vivare-services.com) |
-- |
-- Versions: |
-- Revision 1.1202 2018/09/10 12:14:00 jens |
-- - RESET generates SYNC now, 1 dead cycle delayed |
-- Revision 1.1202 RC 2018/09/09 03:00:00 jens |
-- - ADC / SBC flags and A like R65C02 now |
-- Revision 1.1202 BETA 2018/09/05 19:35:00 jens |
161,7 → 163,7
-- |
-- Created: |
-- by - eda.UNKNOWN (ENTW-7HPZ200) |
-- at - 12:26:19 09.09.2018 |
-- at - 12:21:39 10.09.2018 |
-- |
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) |
-- |
395,6 → 397,7
constant s271 : state_type := "11110001"; |
constant s272 : state_type := "11110011"; |
constant s309 : state_type := "11110010"; |
constant RES7 : state_type := "11110110"; |
|
-- Declare current and next state signals |
signal current_state : state_type; |
420,7 → 423,7
current_state <= RES; |
-- Default Reset Values |
d_o_cld <= X"00"; |
rd_o_cld <= '0'; |
rd_o_cld <= '1'; |
sync_o_cld <= '0'; |
wr_n_o_cld <= '1'; |
wr_o_cld <= '0'; |
522,11 → 525,6
when RES => |
reg_sel_pc_in <= '0'; |
reg_sel_pc_val <= "00"; |
sig_PC <= adr_nxt_pc_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
when FETCH => |
zw_REG_OP <= d_i; |
if ((d_i = X"00") and (rdy_i = '1')) then |
2468,6 → 2466,12
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
end if; |
when RES7 => |
sig_PC <= adr_nxt_pc_i; |
reg_sel_pc_in <= '0'; |
reg_sel_pc_val <= "00"; |
reg_sel_sp_in <= '0'; |
reg_sel_sp_as <= '1'; |
when others => |
null; |
end case; |
2528,7 → 2532,7
next_state <= s550; |
end if; |
when RES => |
next_state <= s544; |
next_state <= RES7; |
when FETCH => |
if ((d_i = X"00") and (rdy_i = '1')) then |
next_state <= brk1; |
4174,6 → 4178,8
else |
next_state <= s309; |
end if; |
when RES7 => |
next_state <= s544; |
when others => |
next_state <= RES; |
end case; |
4291,12 → 4297,7
ld_o <= "11"; |
end if; |
when RES => |
ld_o <= "11"; |
ld_pc_o <= '1'; |
|
ld_sp_o <= '1'; |
sig_RWn <= '1'; |
sig_RD <= '1'; |
sig_SYNC <= '1'; |
when FETCH => |
sig_RWn <= '1'; |
sig_RD <= '1'; |
6057,6 → 6058,13
if (rdy_i = '1') then |
sig_SYNC <= '1'; |
end if; |
when RES7 => |
ld_o <= "11"; |
ld_pc_o <= '1'; |
|
ld_sp_o <= '1'; |
sig_RWn <= '1'; |
sig_RD <= '1'; |
when others => |
null; |
end case; |
/cpu65c02_true_cycle/trunk/rtl/vhdl/fsm_intnmi.vhd
2,7 → 2,7
-- |
-- Created: |
-- by - eda.UNKNOWN (ENTW-7HPZ200) |
-- at - 11:59:05 06.09.2018 |
-- at - 12:35:56 10.09.2018 |
-- |
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) |
-- |
58,7 → 58,7
-- |
-- Created: |
-- by - eda.UNKNOWN (ENTW-7HPZ200) |
-- at - 11:59:05 06.09.2018 |
-- at - 12:35:56 10.09.2018 |
-- |
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) |
-- |
/cpu65c02_true_cycle/trunk/rtl/vhdl/r65c02_tc.vhd
35,6 → 35,8
-- (email: opencores@vivare-services.com) |
-- |
-- Versions: |
-- Revision 1.52 2018/09/10 12:14:00 jens |
-- - RESET generates SYNC now, 1 dead cycle delayed |
-- Revision 1.52 RC 2018/09/09 03:00:00 jens |
-- - ADC / SBC flags and A like R65C02 now |
-- Revision 1.52 BETA 2018/09/05 19:35:00 jens |
99,7 → 101,7
-- |
-- Created: |
-- by - eda.UNKNOWN (ENTW-7HPZ200) |
-- at - 12:27:04 09.09.2018 |
-- at - 12:21:16 10.09.2018 |
-- |
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) |
-- |