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/cpu65c02_true_cycle/trunk/asm/6502_interrupt_test.a65 File deleted \ No newline at end of file
/cpu65c02_true_cycle/trunk/asm/6502_decimal_test.a65 File deleted
/cpu65c02_true_cycle/trunk/asm/6502_functional_test.a65 File deleted \ No newline at end of file
/cpu65c02_true_cycle/trunk/asm/65C02_extended_opcodes_test.a65c File deleted
/cpu65c02_true_cycle/trunk/asm/readme.txt File deleted
/cpu65c02_true_cycle/trunk/rtl/vhdl/fsm_intnmi.vhd File deleted
/cpu65c02_true_cycle/trunk/rtl/vhdl/fsm_execution_unit.vhd File deleted
/cpu65c02_true_cycle/trunk/rtl/vhdl/r65c02_tc.vhd File deleted
cpu65c02_true_cycle/trunk/rtl/vhdl/r65c02_tc.vhd Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: cpu65c02_true_cycle/trunk/rtl/vhdl/core.vhd =================================================================== --- cpu65c02_true_cycle/trunk/rtl/vhdl/core.vhd (revision 22) +++ cpu65c02_true_cycle/trunk/rtl/vhdl/core.vhd (nonexistent) @@ -1,396 +0,0 @@ --- VHDL Entity r65c02_tc.core.symbol --- --- Created: --- by - jens.Domain Users (ENTW-7HPZ200) --- at - 11:09:21 08/01/13 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - -entity core is - port( - clk_clk_i : in std_logic; - d_i : in std_logic_vector (7 downto 0); - irq_n_i : in std_logic; - nmi_n_i : in std_logic; - rdy_i : in std_logic; - rst_rst_n_i : in std_logic; - so_n_i : in std_logic; - a_o : out std_logic_vector (15 downto 0); - d_o : out std_logic_vector (7 downto 0); - rd_o : out std_logic; - sync_o : out std_logic; - wr_n_o : out std_logic; - wr_o : out std_logic - ); - --- Declarations - -end core ; - --- (C) 2008 - 2018 Jens Gutschmidt --- (email: opencores@vivare-services.com) --- --- Versions: --- Revision 1.8 2013/08/01 11:00:00 jens --- - Change Block names to lower case --- - Bug Fix RMB, SMB Bug - Bit position decoded wrong. Adding a priority encoder. --- --- Revision 1.7 2013/07/21 11:11:00 jens --- - Changing the title block and internal revision history --- --- Revision 1.6 2009/01/04 10:20:47 eda --- Changes for cosmetic issues only --- --- Revision 1.5 2009/01/04 09:23:10 eda --- - Delete unused nets and blocks (same as R6502_TC) --- - Rename blocks --- --- Revision 1.4 2009/01/03 16:53:02 eda --- - Unused nets and blocks deleted --- - Renamed blocks --- --- Revision 1.3 2009/01/03 16:42:02 eda --- - Unused nets and blocks deleted --- - Renamed blocks --- --- Revision 1.2 2008/12/31 19:31:24 eda --- Production Release --- --- --- --- VHDL Architecture r65c02_tc.core.struct --- --- Created: --- by - eda.UNKNOWN (ENTW-7HPZ200) --- at - 12:00:34 06.09.2018 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) --- --- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt --- --- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. --- --- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License along with this program. If not, see . --- --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - -library r65c02_tc; - -architecture struct of core is - - -- Architecture declarations - - -- Internal signal declarations - signal adr_nxt_pc_o_i : std_logic_vector(15 downto 0); - signal adr_o_i : std_logic_vector(15 downto 0); - signal adr_pc_o_i : std_logic_vector(15 downto 0); - signal adr_sp_o_i : std_logic_vector(15 downto 0); - signal ch_a_o_i : std_logic_vector(7 downto 0); - signal ch_b_o_i : std_logic_vector(7 downto 0); - signal d_alu_n_o_i : std_logic; - signal d_alu_o_i : std_logic_vector(7 downto 0); - signal d_alu_or_o_i : std_logic; - signal d_alu_prio_o_i : std_logic_vector(7 downto 0); - signal d_regs_in_o_i : std_logic_vector(7 downto 0); - signal d_regs_out_o_i : std_logic_vector(7 downto 0); - signal ld_o_i : std_logic_vector(1 downto 0); - signal ld_pc_o_i : std_logic; - signal ld_sp_o_i : std_logic; - signal load_regs_o_i : std_logic; - signal nmi_o_i : std_logic; - signal offset_o_i : std_logic_vector(15 downto 0); - signal q_a_o_i : std_logic_vector(7 downto 0); - signal q_x_o_i : std_logic_vector(7 downto 0); - signal q_y_o_i : std_logic_vector(7 downto 0); - signal reg_0flag_o_i : std_logic; - signal reg_1flag_o_i : std_logic; - signal reg_7flag_o_i : std_logic; - signal rst_nmi_o_i : std_logic; - signal sel_pc_in_o_i : std_logic; - signal sel_pc_val_o_i : std_logic_vector(1 downto 0); - signal sel_rb_in_o_i : std_logic_vector(1 downto 0); - signal sel_rb_out_o_i : std_logic_vector(1 downto 0); - signal sel_reg_o_i : std_logic_vector(1 downto 0); - signal sel_sp_as_o_i : std_logic; - signal sel_sp_in_o_i : std_logic; - signal var_shift_data_o_i : std_logic_vector(7 downto 0); - - - -- Component Declarations - component fsm_execution_unit - port ( - adr_nxt_pc_i : in std_logic_vector (15 downto 0); - adr_pc_i : in std_logic_vector (15 downto 0); - adr_sp_i : in std_logic_vector (15 downto 0); - clk_clk_i : in std_logic ; - d_alu_i : in std_logic_vector ( 7 downto 0 ); - d_alu_prio_i : in std_logic_vector (7 downto 0); - d_i : in std_logic_vector ( 7 downto 0 ); - d_regs_out_i : in std_logic_vector ( 7 downto 0 ); - irq_n_i : in std_logic ; - nmi_i : in std_logic ; - q_a_i : in std_logic_vector ( 7 downto 0 ); - q_x_i : in std_logic_vector ( 7 downto 0 ); - q_y_i : in std_logic_vector ( 7 downto 0 ); - rdy_i : in std_logic ; - reg_0flag_i : in std_logic ; - reg_1flag_i : in std_logic ; - reg_7flag_i : in std_logic ; - rst_rst_n_i : in std_logic ; - so_n_i : in std_logic ; - a_o : out std_logic_vector (15 downto 0); - adr_o : out std_logic_vector (15 downto 0); - ch_a_o : out std_logic_vector ( 7 downto 0 ); - ch_b_o : out std_logic_vector ( 7 downto 0 ); - d_o : out std_logic_vector ( 7 downto 0 ); - d_regs_in_o : out std_logic_vector ( 7 downto 0 ); - ld_o : out std_logic_vector ( 1 downto 0 ); - ld_pc_o : out std_logic ; - ld_sp_o : out std_logic ; - load_regs_o : out std_logic ; - offset_o : out std_logic_vector ( 15 downto 0 ); - rd_o : out std_logic ; - rst_nmi_o : out std_logic ; - sel_pc_in_o : out std_logic ; - sel_pc_val_o : out std_logic_vector ( 1 downto 0 ); - sel_rb_in_o : out std_logic_vector ( 1 downto 0 ); - sel_rb_out_o : out std_logic_vector ( 1 downto 0 ); - sel_reg_o : out std_logic_vector ( 1 downto 0 ); - sel_sp_as_o : out std_logic ; - sel_sp_in_o : out std_logic ; - sync_o : out std_logic ; - wr_n_o : out std_logic ; - wr_o : out std_logic - ); - end component; - component fsm_intnmi - port ( - clk_clk_i : in std_logic ; - nmi_n_i : in std_logic ; - rst_nmi_i : in std_logic ; - rst_rst_n_i : in std_logic ; - nmi_o : out std_logic - ); - end component; - component reg_pc - port ( - adr_i : in std_logic_vector (15 downto 0); - clk_clk_i : in std_logic ; - ld_i : in std_logic_vector (1 downto 0); - ld_pc_i : in std_logic ; - offset_i : in std_logic_vector (15 downto 0); - rst_rst_n_i : in std_logic ; - sel_pc_in_i : in std_logic ; - sel_pc_val_i : in std_logic_vector (1 downto 0); - adr_nxt_pc_o : out std_logic_vector (15 downto 0); - adr_pc_o : out std_logic_vector (15 downto 0) - ); - end component; - component reg_sp - port ( - adr_low_i : in std_logic_vector (7 downto 0); - clk_clk_i : in std_logic ; - ld_low_i : in std_logic ; - ld_sp_i : in std_logic ; - rst_rst_n_i : in std_logic ; - sel_sp_as_i : in std_logic ; - sel_sp_in_i : in std_logic ; - adr_sp_o : out std_logic_vector (15 downto 0) - ); - end component; - component regbank_axy - port ( - clk_clk_i : in std_logic ; - d_regs_in_i : in std_logic_vector (7 downto 0); - load_regs_i : in std_logic ; - rst_rst_n_i : in std_logic ; - sel_rb_in_i : in std_logic_vector (1 downto 0); - sel_rb_out_i : in std_logic_vector (1 downto 0); - sel_reg_i : in std_logic_vector (1 downto 0); - d_regs_out_o : out std_logic_vector (7 downto 0); - q_a_o : out std_logic_vector (7 downto 0); - q_x_o : out std_logic_vector (7 downto 0); - q_y_o : out std_logic_vector (7 downto 0) - ); - end component; - - -- Optional embedded configurations - -- pragma synthesis_off - for all : fsm_execution_unit use entity r65c02_tc.fsm_execution_unit; - for all : fsm_intnmi use entity r65c02_tc.fsm_intnmi; - for all : reg_pc use entity r65c02_tc.reg_pc; - for all : reg_sp use entity r65c02_tc.reg_sp; - for all : regbank_axy use entity r65c02_tc.regbank_axy; - -- pragma synthesis_on - - -begin - -- Architecture concurrent statements - -- HDL Embedded Text Block 1 eb1 - -- eb1 1 - var_shift_data_o_i <= x"01"; - - - -- ModuleWare code(v1.12) for instance 'U_11' of 'add' - u_11combo_proc: process (ch_a_o_i, ch_b_o_i) - variable temp_din0 : std_logic_vector(8 downto 0); - variable temp_din1 : std_logic_vector(8 downto 0); - variable temp_sum : unsigned(8 downto 0); - variable temp_carry : std_logic; - begin - temp_din0 := '0' & ch_a_o_i; - temp_din1 := '0' & ch_b_o_i; - temp_carry := '0'; - temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry; - d_alu_o_i <= conv_std_logic_vector(temp_sum(7 downto 0),8); - reg_0flag_o_i <= temp_sum(8) ; - end process u_11combo_proc; - - -- ModuleWare code(v1.12) for instance 'U_8' of 'inv' - reg_1flag_o_i <= not(d_alu_or_o_i); - - -- ModuleWare code(v1.12) for instance 'U_9' of 'inv' - reg_7flag_o_i <= not(d_alu_n_o_i); - - -- ModuleWare code(v1.12) for instance 'U_10' of 'inv' - d_alu_n_o_i <= not(d_alu_o_i(7)); - - -- ModuleWare code(v1.12) for instance 'U_5' of 'lshift' - u_5combo_proc : process (var_shift_data_o_i, ch_a_o_i) - variable temp_shift : std_logic_vector (3 downto 0); - variable temp_dout : std_logic_vector (7 downto 0); - variable temp_din : std_logic_vector (7 downto 0); - begin - temp_din := (others=> 'X'); - temp_shift := ch_a_o_i(3 downto 0); - temp_din := var_shift_data_o_i; - for i in 0 to 3 loop - if (i < 3) then - if (temp_shift(i) = '1') then - temp_dout := (others => '0'); - temp_dout(7 downto 2**i) := temp_din(7 - 2**i downto 0); - elsif (temp_shift(i) = '0') then - temp_dout := temp_din; - else - temp_dout := (others => 'X'); - end if; - else - if (temp_shift(i) = '1') then - temp_dout := (others => '0'); - elsif (temp_shift(i) = '0') then - temp_dout := temp_din; - else - temp_dout := (others => 'X'); - end if; - end if; - temp_din := temp_dout; - end loop; - d_alu_prio_o_i <= temp_dout; - end process u_5combo_proc; - - -- ModuleWare code(v1.12) for instance 'U_7' of 'por' - d_alu_or_o_i <= d_alu_o_i(0) or d_alu_o_i(1) or d_alu_o_i(2) or d_alu_o_i(3) or d_alu_o_i(4) or d_alu_o_i(5) or d_alu_o_i(6) or d_alu_o_i(7); - - -- Instance port mappings. - U_4 : fsm_execution_unit - port map ( - adr_nxt_pc_i => adr_nxt_pc_o_i, - adr_pc_i => adr_pc_o_i, - adr_sp_i => adr_sp_o_i, - clk_clk_i => clk_clk_i, - d_alu_i => d_alu_o_i, - d_alu_prio_i => d_alu_prio_o_i, - d_i => d_i, - d_regs_out_i => d_regs_out_o_i, - irq_n_i => irq_n_i, - nmi_i => nmi_o_i, - q_a_i => q_a_o_i, - q_x_i => q_x_o_i, - q_y_i => q_y_o_i, - rdy_i => rdy_i, - reg_0flag_i => reg_0flag_o_i, - reg_1flag_i => reg_1flag_o_i, - reg_7flag_i => reg_7flag_o_i, - rst_rst_n_i => rst_rst_n_i, - so_n_i => so_n_i, - a_o => a_o, - adr_o => adr_o_i, - ch_a_o => ch_a_o_i, - ch_b_o => ch_b_o_i, - d_o => d_o, - d_regs_in_o => d_regs_in_o_i, - ld_o => ld_o_i, - ld_pc_o => ld_pc_o_i, - ld_sp_o => ld_sp_o_i, - load_regs_o => load_regs_o_i, - offset_o => offset_o_i, - rd_o => rd_o, - rst_nmi_o => rst_nmi_o_i, - sel_pc_in_o => sel_pc_in_o_i, - sel_pc_val_o => sel_pc_val_o_i, - sel_rb_in_o => sel_rb_in_o_i, - sel_rb_out_o => sel_rb_out_o_i, - sel_reg_o => sel_reg_o_i, - sel_sp_as_o => sel_sp_as_o_i, - sel_sp_in_o => sel_sp_in_o_i, - sync_o => sync_o, - wr_n_o => wr_n_o, - wr_o => wr_o - ); - U_3 : fsm_intnmi - port map ( - clk_clk_i => clk_clk_i, - nmi_n_i => nmi_n_i, - rst_nmi_i => rst_nmi_o_i, - rst_rst_n_i => rst_rst_n_i, - nmi_o => nmi_o_i - ); - U_0 : reg_pc - port map ( - adr_i => adr_o_i, - clk_clk_i => clk_clk_i, - ld_i => ld_o_i, - ld_pc_i => ld_pc_o_i, - offset_i => offset_o_i, - rst_rst_n_i => rst_rst_n_i, - sel_pc_in_i => sel_pc_in_o_i, - sel_pc_val_i => sel_pc_val_o_i, - adr_nxt_pc_o => adr_nxt_pc_o_i, - adr_pc_o => adr_pc_o_i - ); - U_1 : reg_sp - port map ( - adr_low_i => adr_o_i(7 DOWNTO 0), - clk_clk_i => clk_clk_i, - ld_low_i => ld_o_i(0), - ld_sp_i => ld_sp_o_i, - rst_rst_n_i => rst_rst_n_i, - sel_sp_as_i => sel_sp_as_o_i, - sel_sp_in_i => sel_sp_in_o_i, - adr_sp_o => adr_sp_o_i - ); - U_2 : regbank_axy - port map ( - clk_clk_i => clk_clk_i, - d_regs_in_i => d_regs_in_o_i, - load_regs_i => load_regs_o_i, - rst_rst_n_i => rst_rst_n_i, - sel_rb_in_i => sel_rb_in_o_i, - sel_rb_out_i => sel_rb_out_o_i, - sel_reg_i => sel_reg_o_i, - d_regs_out_o => d_regs_out_o_i, - q_a_o => q_a_o_i, - q_x_o => q_x_o_i, - q_y_o => q_y_o_i - ); - -end struct;
cpu65c02_true_cycle/trunk/rtl/vhdl/core.vhd Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: cpu65c02_true_cycle/trunk/rtl/vhdl/regbank_axy.vhd =================================================================== --- cpu65c02_true_cycle/trunk/rtl/vhdl/regbank_axy.vhd (revision 22) +++ cpu65c02_true_cycle/trunk/rtl/vhdl/regbank_axy.vhd (nonexistent) @@ -1,207 +0,0 @@ --- VHDL Entity r65c02_tc.regbank_axy.symbol --- --- Created: --- by - eda.UNKNOWN (ENTW-7HPZ200) --- at - 20:45:48 27.08.2018 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - -entity regbank_axy is - port( - clk_clk_i : in std_logic; - d_regs_in_i : in std_logic_vector (7 downto 0); - load_regs_i : in std_logic; - rst_rst_n_i : in std_logic; - sel_rb_in_i : in std_logic_vector (1 downto 0); - sel_rb_out_i : in std_logic_vector (1 downto 0); - sel_reg_i : in std_logic_vector (1 downto 0); - d_regs_out_o : out std_logic_vector (7 downto 0); - q_a_o : out std_logic_vector (7 downto 0); - q_x_o : out std_logic_vector (7 downto 0); - q_y_o : out std_logic_vector (7 downto 0) - ); - --- Declarations - -end regbank_axy ; - --- (C) 2008 - 2018 Jens Gutschmidt --- (email: opencores@vivare-services.com) --- --- Versions: --- Revision 1.7 2013/07/21 11:11:00 jens --- - Changing the title block and internal revision history --- --- Revision 1.6 2009/01/04 10:20:47 eda --- Changes for cosmetic issues only --- --- Revision 1.5 2009/01/04 09:23:10 eda --- - Delete unused nets and blocks (same as R6502_TC) --- - Rename blocks --- --- Revision 1.4 2009/01/03 16:53:02 eda --- - Unused nets and blocks deleted --- - Renamed blocks --- --- Revision 1.3 2009/01/03 16:42:02 eda --- - Unused nets and blocks deleted --- - Renamed blocks --- --- Revision 1.2 2008/12/31 19:31:24 eda --- Production Release --- --- --- --- VHDL Architecture r65c02_tc.regbank_axy.struct --- --- Created: --- by - eda.UNKNOWN (ENTW-7HPZ200) --- at - 12:04:48 06.09.2018 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) --- --- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt --- --- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. --- --- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License along with this program. If not, see . --- --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - - -architecture struct of regbank_axy is - - -- Architecture declarations - - -- Internal signal declarations - signal ld : std_logic_vector(2 downto 0); - signal load1_o_i : std_logic; - signal load2_o_i : std_logic; - signal load_o_i : std_logic; - signal q_mux_o_i : std_logic_vector(7 downto 0); - signal val_zero : std_logic_vector(7 downto 0); - - -- Implicit buffer signal declarations - signal q_a_o_internal : std_logic_vector (7 downto 0); - signal q_x_o_internal : std_logic_vector (7 downto 0); - signal q_y_o_internal : std_logic_vector (7 downto 0); - - - -- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff' - signal mw_U_0reg_cval : std_logic_vector(7 downto 0); - - -- ModuleWare signal declarations(v1.12) for instance 'U_4' of 'adff' - signal mw_U_4reg_cval : std_logic_vector(7 downto 0); - - -- ModuleWare signal declarations(v1.12) for instance 'U_5' of 'adff' - signal mw_U_5reg_cval : std_logic_vector(7 downto 0); - - -begin - - -- ModuleWare code(v1.12) for instance 'U_0' of 'adff' - q_a_o_internal <= mw_U_0reg_cval; - u_0seq_proc: process (clk_clk_i, rst_rst_n_i) - begin - if (rst_rst_n_i = '0') then - mw_U_0reg_cval <= "00000000"; - elsif (clk_clk_i'event and clk_clk_i='1') then - if (load_o_i = '1') then - mw_U_0reg_cval <= q_mux_o_i; - end if; - end if; - end process u_0seq_proc; - - -- ModuleWare code(v1.12) for instance 'U_4' of 'adff' - q_x_o_internal <= mw_U_4reg_cval; - u_4seq_proc: process (clk_clk_i, rst_rst_n_i) - begin - if (rst_rst_n_i = '0') then - mw_U_4reg_cval <= "00000000"; - elsif (clk_clk_i'event and clk_clk_i='1') then - if (load1_o_i = '1') then - mw_U_4reg_cval <= q_mux_o_i; - end if; - end if; - end process u_4seq_proc; - - -- ModuleWare code(v1.12) for instance 'U_5' of 'adff' - q_y_o_internal <= mw_U_5reg_cval; - u_5seq_proc: process (clk_clk_i, rst_rst_n_i) - begin - if (rst_rst_n_i = '0') then - mw_U_5reg_cval <= "00000000"; - elsif (clk_clk_i'event and clk_clk_i='1') then - if (load2_o_i = '1') then - mw_U_5reg_cval <= q_mux_o_i; - end if; - end if; - end process u_5seq_proc; - - -- ModuleWare code(v1.12) for instance 'U_6' of 'and' - load_o_i <= load_regs_i and ld(0); - - -- ModuleWare code(v1.12) for instance 'U_7' of 'and' - load1_o_i <= load_regs_i and ld(1); - - -- ModuleWare code(v1.12) for instance 'U_8' of 'and' - load2_o_i <= load_regs_i and ld(2); - - -- ModuleWare code(v1.12) for instance 'U_11' of 'constval' - val_zero <= "00000000"; - - -- ModuleWare code(v1.12) for instance 'U_1' of 'decoder1' - u_1combo_proc: process (sel_reg_i) - begin - ld <= (others => '0'); - case sel_reg_i is - when "00" => ld(0) <= '1'; - when "01" => ld(1) <= '1'; - when "10" => ld(2) <= '1'; - when others => ld <= (others => '0'); - end case; - end process u_1combo_proc; - - -- ModuleWare code(v1.12) for instance 'U_2' of 'mux' - u_2combo_proc: process(q_a_o_internal, q_x_o_internal, q_y_o_internal, - val_zero, sel_rb_out_i) - begin - case sel_rb_out_i is - when "00" => d_regs_out_o <= q_a_o_internal; - when "01" => d_regs_out_o <= q_x_o_internal; - when "10" => d_regs_out_o <= q_y_o_internal; - when "11" => d_regs_out_o <= val_zero; - when others => d_regs_out_o <= (others => 'X'); - end case; - end process u_2combo_proc; - - -- ModuleWare code(v1.12) for instance 'U_3' of 'mux' - u_3combo_proc: process(q_a_o_internal, q_y_o_internal, q_x_o_internal, - d_regs_in_i, sel_rb_in_i) - begin - case sel_rb_in_i is - when "00" => q_mux_o_i <= q_a_o_internal; - when "01" => q_mux_o_i <= q_y_o_internal; - when "10" => q_mux_o_i <= q_x_o_internal; - when "11" => q_mux_o_i <= d_regs_in_i; - when others => q_mux_o_i <= (others => 'X'); - end case; - end process u_3combo_proc; - - -- Instance port mappings. - - -- Implicit buffered output assignments - q_a_o <= q_a_o_internal; - q_x_o <= q_x_o_internal; - q_y_o <= q_y_o_internal; - -end struct;
cpu65c02_true_cycle/trunk/rtl/vhdl/regbank_axy.vhd Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: cpu65c02_true_cycle/trunk/rtl/vhdl/reg_pc.vhd =================================================================== --- cpu65c02_true_cycle/trunk/rtl/vhdl/reg_pc.vhd (revision 22) +++ cpu65c02_true_cycle/trunk/rtl/vhdl/reg_pc.vhd (nonexistent) @@ -1,237 +0,0 @@ --- VHDL Entity r65c02_tc.reg_pc.symbol --- --- Created: --- by - eda.UNKNOWN (ENTW-7HPZ200) --- at - 11:59:59 06.09.2018 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - -entity reg_pc is - port( - adr_i : in std_logic_vector (15 downto 0); - clk_clk_i : in std_logic; - ld_i : in std_logic_vector (1 downto 0); - ld_pc_i : in std_logic; - offset_i : in std_logic_vector (15 downto 0); - rst_rst_n_i : in std_logic; - sel_pc_in_i : in std_logic; - sel_pc_val_i : in std_logic_vector (1 downto 0); - adr_nxt_pc_o : out std_logic_vector (15 downto 0); - adr_pc_o : out std_logic_vector (15 downto 0) - ); - --- Declarations - -end reg_pc ; - --- (C) 2008 - 2018 Jens Gutschmidt --- (email: opencores@vivare-services.com) --- --- Versions: --- Revision 1.7 2013/07/21 11:11:00 jens --- - Changing the title block and internal revision history --- --- Revision 1.6 2009/01/04 10:20:47 eda --- Changes for cosmetic issues only --- --- Revision 1.5 2009/01/04 09:23:10 eda --- - Delete unused nets and blocks (same as R6502_TC) --- - Rename blocks --- --- Revision 1.4 2009/01/03 16:53:02 eda --- - Unused nets and blocks deleted --- - Renamed blocks --- --- Revision 1.3 2009/01/03 16:42:02 eda --- - Unused nets and blocks deleted --- - Renamed blocks --- --- Revision 1.2 2008/12/31 19:31:24 eda --- Production Release --- --- --- --- VHDL Architecture r65c02_tc.reg_pc.struct --- --- Created: --- by - eda.UNKNOWN (ENTW-7HPZ200) --- at - 11:59:59 06.09.2018 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) --- --- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt --- --- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. --- --- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License along with this program. If not, see . --- --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - - -architecture struct of reg_pc is - - -- Architecture declarations - - -- Internal signal declarations - signal adr_pc_high_o_i : std_logic_vector(7 downto 0); - signal adr_pc_low_o_i : std_logic_vector(7 downto 0); - signal adr_pc_o_i : std_logic_vector(15 downto 0); - signal ci_o_i : std_logic; - signal cout_pc_o_i : std_logic; - signal load3_o_i : std_logic; - signal load_o_i : std_logic; - signal offset_high_o_i : std_logic_vector(7 downto 0); - signal offset_low_o_i : std_logic_vector(7 downto 0); - signal val_o_i : std_logic_vector(7 downto 0); - signal val_one : std_logic_vector(7 downto 0); - signal val_zero : std_logic_vector(7 downto 0); - - -- Implicit buffer signal declarations - signal adr_nxt_pc_o_internal : std_logic_vector (15 downto 0); - signal adr_pc_o_internal : std_logic_vector (15 downto 0); - - - -- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff' - signal mw_U_0reg_cval : std_logic_vector(7 downto 0); - - -- ModuleWare signal declarations(v1.12) for instance 'U_4' of 'adff' - signal mw_U_4reg_cval : std_logic_vector(7 downto 0); - - -- ModuleWare signal declarations(v1.12) for instance 'U_3' of 'split' - signal mw_U_3temp_din : std_logic_vector(15 downto 0); - - -- ModuleWare signal declarations(v1.12) for instance 'U_5' of 'split' - signal mw_U_5temp_din : std_logic_vector(15 downto 0); - - -begin - - -- ModuleWare code(v1.12) for instance 'U_2' of 'add' - u_2combo_proc: process (adr_pc_low_o_i, val_o_i) - variable temp_din0 : std_logic_vector(8 downto 0); - variable temp_din1 : std_logic_vector(8 downto 0); - variable temp_sum : unsigned(8 downto 0); - variable temp_carry : std_logic; - begin - temp_din0 := '0' & adr_pc_low_o_i; - temp_din1 := '0' & val_o_i; - temp_carry := '0'; - temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry; - adr_nxt_pc_o_internal(7 DOWNTO 0) <= conv_std_logic_vector(temp_sum(7 downto 0),8); - cout_pc_o_i <= temp_sum(8) ; - end process u_2combo_proc; - - -- ModuleWare code(v1.12) for instance 'U_11' of 'add' - u_11combo_proc: process (adr_pc_high_o_i, offset_high_o_i, ci_o_i) - variable temp_din0 : std_logic_vector(8 downto 0); - variable temp_din1 : std_logic_vector(8 downto 0); - variable temp_sum : unsigned(8 downto 0); - variable temp_carry : std_logic; - begin - temp_din0 := '0' & adr_pc_high_o_i; - temp_din1 := '0' & offset_high_o_i; - temp_carry := ci_o_i; - temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry; - adr_nxt_pc_o_internal(15 DOWNTO 8) <= conv_std_logic_vector(temp_sum(7 downto 0),8); - end process u_11combo_proc; - - -- ModuleWare code(v1.12) for instance 'U_0' of 'adff' - adr_pc_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval; - u_0seq_proc: process (clk_clk_i, rst_rst_n_i) - begin - if (rst_rst_n_i = '0') then - mw_U_0reg_cval <= "00000000"; - elsif (clk_clk_i'event and clk_clk_i='1') then - if (load_o_i = '1') then - mw_U_0reg_cval <= adr_nxt_pc_o_internal(7 DOWNTO 0); - end if; - end if; - end process u_0seq_proc; - - -- ModuleWare code(v1.12) for instance 'U_4' of 'adff' - adr_pc_o_internal(15 DOWNTO 8) <= mw_U_4reg_cval; - u_4seq_proc: process (clk_clk_i, rst_rst_n_i) - begin - if (rst_rst_n_i = '0') then - mw_U_4reg_cval <= "00000000"; - elsif (clk_clk_i'event and clk_clk_i='1') then - if (load3_o_i = '1') then - mw_U_4reg_cval <= adr_nxt_pc_o_internal(15 DOWNTO 8); - end if; - end if; - end process u_4seq_proc; - - -- ModuleWare code(v1.12) for instance 'U_6' of 'and' - load_o_i <= ld_pc_i and ld_i(0); - - -- ModuleWare code(v1.12) for instance 'U_7' of 'and' - load3_o_i <= ld_pc_i and ld_i(1); - - -- ModuleWare code(v1.12) for instance 'U_10' of 'and' - ci_o_i <= cout_pc_o_i and ld_pc_i; - - -- ModuleWare code(v1.12) for instance 'U_1' of 'constval' - val_zero <= "00000000"; - - -- ModuleWare code(v1.12) for instance 'U_9' of 'constval' - val_one <= "00000001"; - - -- ModuleWare code(v1.12) for instance 'U_8' of 'mux' - u_8combo_proc: process(adr_pc_o_internal, adr_i, sel_pc_in_i) - begin - case sel_pc_in_i is - when '0' => adr_pc_o_i <= adr_pc_o_internal; - when '1' => adr_pc_o_i <= adr_i; - when others => adr_pc_o_i <= (others => 'X'); - end case; - end process u_8combo_proc; - - -- ModuleWare code(v1.12) for instance 'U_13' of 'mux' - u_13combo_proc: process(val_one, val_zero, offset_low_o_i, - sel_pc_val_i) - begin - case sel_pc_val_i is - when "00" => val_o_i <= val_one; - when "01" => val_o_i <= val_zero; - when "10" => val_o_i <= offset_low_o_i; - when "11" => val_o_i <= val_zero; - when others => val_o_i <= (others => 'X'); - end case; - end process u_13combo_proc; - - -- ModuleWare code(v1.12) for instance 'U_3' of 'split' - mw_U_3temp_din <= adr_pc_o_i; - u_3combo_proc: process (mw_U_3temp_din) - variable temp_din: std_logic_vector(15 downto 0); - begin - temp_din := mw_U_3temp_din(15 downto 0); - adr_pc_low_o_i <= temp_din(7 downto 0); - adr_pc_high_o_i <= temp_din(15 downto 8); - end process u_3combo_proc; - - -- ModuleWare code(v1.12) for instance 'U_5' of 'split' - mw_U_5temp_din <= offset_i; - u_5combo_proc: process (mw_U_5temp_din) - variable temp_din: std_logic_vector(15 downto 0); - begin - temp_din := mw_U_5temp_din(15 downto 0); - offset_low_o_i <= temp_din(7 downto 0); - offset_high_o_i <= temp_din(15 downto 8); - end process u_5combo_proc; - - -- Instance port mappings. - - -- Implicit buffered output assignments - adr_nxt_pc_o <= adr_nxt_pc_o_internal; - adr_pc_o <= adr_pc_o_internal; - -end struct;
cpu65c02_true_cycle/trunk/rtl/vhdl/reg_pc.vhd Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: cpu65c02_true_cycle/trunk/rtl/vhdl/reg_sp.vhd =================================================================== --- cpu65c02_true_cycle/trunk/rtl/vhdl/reg_sp.vhd (revision 22) +++ cpu65c02_true_cycle/trunk/rtl/vhdl/reg_sp.vhd (nonexistent) @@ -1,161 +0,0 @@ --- VHDL Entity r65c02_tc.reg_sp.symbol --- --- Created: --- by - eda.UNKNOWN (ENTW-7HPZ200) --- at - 12:04:08 06.09.2018 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - -entity reg_sp is - port( - adr_low_i : in std_logic_vector (7 downto 0); - clk_clk_i : in std_logic; - ld_low_i : in std_logic; - ld_sp_i : in std_logic; - rst_rst_n_i : in std_logic; - sel_sp_as_i : in std_logic; - sel_sp_in_i : in std_logic; - adr_sp_o : out std_logic_vector (15 downto 0) - ); - --- Declarations - -end reg_sp ; - --- (C) 2008 - 2018 Jens Gutschmidt --- (email: opencores@vivare-services.com) --- --- Versions: --- Revision 1.7 2013/07/21 11:11:00 jens --- - Changing the title block and internal revision history --- --- Revision 1.6 2009/01/04 10:20:47 eda --- Changes for cosmetic issues only --- --- Revision 1.5 2009/01/04 09:23:10 eda --- - Delete unused nets and blocks (same as R6502_TC) --- - Rename blocks --- --- Revision 1.4 2009/01/03 16:53:02 eda --- - Unused nets and blocks deleted --- - Renamed blocks --- --- Revision 1.3 2009/01/03 16:42:02 eda --- - Unused nets and blocks deleted --- - Renamed blocks --- --- Revision 1.2 2008/12/31 19:31:24 eda --- Production Release --- --- --- --- VHDL Architecture r65c02_tc.reg_sp.struct --- --- Created: --- by - eda.UNKNOWN (ENTW-7HPZ200) --- at - 12:04:08 06.09.2018 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) --- --- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt --- --- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. --- --- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License along with this program. If not, see . --- --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - - -architecture struct of reg_sp is - - -- Architecture declarations - - -- Internal signal declarations - signal adr_sp_low_o_i : std_logic_vector(7 downto 0); - signal load_o_i : std_logic; - signal result_low1_o_i : std_logic_vector(7 downto 0); - signal result_low_o_i : std_logic_vector(7 downto 0); - signal sp_as_n_o_i : std_logic; - signal val_one : std_logic_vector(7 downto 0); - - -- Implicit buffer signal declarations - signal adr_sp_o_internal : std_logic_vector (15 downto 0); - - - -- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff' - signal mw_U_0reg_cval : std_logic_vector(7 downto 0); - - -begin - - -- ModuleWare code(v1.12) for instance 'U_11' of 'addsub' - u_11combo_proc: process (adr_sp_low_o_i, val_one, sp_as_n_o_i) - variable temp_din0 : std_logic_vector(8 downto 0); - variable temp_din1 : std_logic_vector(8 downto 0); - variable temp_sum : unsigned(8 downto 0); - variable temp_carry : std_logic; - begin - temp_din0 := '0' & adr_sp_low_o_i; - temp_din1 := '0' & val_one; - temp_carry := '0'; - if (sp_as_n_o_i = '1') then - temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry; - else - temp_sum := unsigned(temp_din0) - unsigned(temp_din1) - temp_carry; - end if; - result_low_o_i <= conv_std_logic_vector(temp_sum(7 downto 0),8); - end process u_11combo_proc; - - -- ModuleWare code(v1.12) for instance 'U_0' of 'adff' - adr_sp_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval; - u_0seq_proc: process (clk_clk_i, rst_rst_n_i) - begin - if (rst_rst_n_i = '0') then - mw_U_0reg_cval <= "00000000"; - elsif (clk_clk_i'event and clk_clk_i='1') then - if (load_o_i = '1') then - mw_U_0reg_cval <= result_low1_o_i; - end if; - end if; - end process u_0seq_proc; - - -- ModuleWare code(v1.12) for instance 'U_6' of 'and' - load_o_i <= ld_sp_i and ld_low_i; - - -- ModuleWare code(v1.12) for instance 'U_3' of 'buff' - adr_sp_o_internal(15 DOWNTO 8) <= val_one; - - -- ModuleWare code(v1.12) for instance 'U_4' of 'constval' - val_one <= "00000001"; - - -- ModuleWare code(v1.12) for instance 'U_2' of 'inv' - sp_as_n_o_i <= not(sel_sp_as_i); - - -- ModuleWare code(v1.12) for instance 'U_8' of 'mux' - u_8combo_proc: process(result_low_o_i, adr_low_i, sel_sp_in_i) - begin - case sel_sp_in_i is - when '0' => result_low1_o_i <= result_low_o_i; - when '1' => result_low1_o_i <= adr_low_i; - when others => result_low1_o_i <= (others => 'X'); - end case; - end process u_8combo_proc; - - -- ModuleWare code(v1.12) for instance 'U_10' of 'tap' - adr_sp_low_o_i <= adr_sp_o_internal(7 downto 0); - - -- Instance port mappings. - - -- Implicit buffered output assignments - adr_sp_o <= adr_sp_o_internal; - -end struct;
cpu65c02_true_cycle/trunk/rtl/vhdl/reg_sp.vhd Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: cpu65c02_true_cycle/trunk/doc/65C02_opcodes_cycles_testet_V0_94.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: cpu65c02_true_cycle/trunk/doc/65C02_opcodes_cycles_testet_V0_94.pdf =================================================================== --- cpu65c02_true_cycle/trunk/doc/65C02_opcodes_cycles_testet_V0_94.pdf (revision 22) +++ cpu65c02_true_cycle/trunk/doc/65C02_opcodes_cycles_testet_V0_94.pdf (nonexistent)
cpu65c02_true_cycle/trunk/doc/65C02_opcodes_cycles_testet_V0_94.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: cpu65c02_true_cycle/trunk/doc/65C02_OP code_table_A01.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: cpu65c02_true_cycle/trunk/doc/65C02_OP code_table_A01.pdf =================================================================== --- cpu65c02_true_cycle/trunk/doc/65C02_OP code_table_A01.pdf (revision 22) +++ cpu65c02_true_cycle/trunk/doc/65C02_OP code_table_A01.pdf (nonexistent)
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cpu65c02_true_cycle/trunk/doc/HTML_r65c02_tc.7z Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: cpu65c02_true_cycle/trunk/TO_DO_list.txt =================================================================== --- cpu65c02_true_cycle/trunk/TO_DO_list.txt (revision 22) +++ cpu65c02_true_cycle/trunk/TO_DO_list.txt (revision 23) @@ -1,3 +1,9 @@ +(October 15th 2018) +- (DONE) Add seperated area for BETA and RELEASE CANDIDATES +- (DONE) Performance improvements +- (WORKING) Creating test strategy for RDY signal +- (DONE) Finish working for Specification of cpu65C02_tc + (September 09th 2018) - (WORKING) Performance improvements - (WORKING) Creating test strategy for RDY signal Index: cpu65c02_true_cycle/trunk/beta/asm/__empty__ =================================================================== Index: cpu65c02_true_cycle/trunk/beta/doc/65C02_OP code_table_A02.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: cpu65c02_true_cycle/trunk/beta/doc/65C02_OP code_table_A02.pdf =================================================================== --- cpu65c02_true_cycle/trunk/beta/doc/65C02_OP code_table_A02.pdf (nonexistent) +++ cpu65c02_true_cycle/trunk/beta/doc/65C02_OP code_table_A02.pdf (revision 23)
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cpu65c02_true_cycle/trunk/beta/doc/R65C02 IP Core Specification.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: cpu65c02_true_cycle/trunk/beta/doc/errata.txt =================================================================== --- cpu65c02_true_cycle/trunk/beta/doc/errata.txt (nonexistent) +++ cpu65c02_true_cycle/trunk/beta/doc/errata.txt (revision 23) @@ -0,0 +1,21 @@ +v2.00RC 2018/10/14 +FUNCTIONALITY: + no errata reported/opened + +TIMING: + no errata reported/opened + +SIGNALING: + no errata reported/opened + + +v1.52 2018/09/10 +FUNCTIONALITY: + no errata reported/opened + +TIMING: + no errata reported/opened + +SIGNALING: + no errata reported/opened + Index: cpu65c02_true_cycle/trunk/beta/doc/src/__empty__ =================================================================== Index: cpu65c02_true_cycle/trunk/beta/rtl/verilog/__empty__ =================================================================== Index: cpu65c02_true_cycle/trunk/beta/rtl/vhdl/core.vhd =================================================================== --- cpu65c02_true_cycle/trunk/beta/rtl/vhdl/core.vhd (nonexistent) +++ cpu65c02_true_cycle/trunk/beta/rtl/vhdl/core.vhd (revision 23) @@ -0,0 +1,396 @@ +-- VHDL Entity r65c02_tc.core.symbol +-- +-- Created: +-- by - jens.Domain Users (ENTW-7HPZ200) +-- at - 11:09:21 08/01/13 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +entity core is + port( + clk_clk_i : in std_logic; + d_i : in std_logic_vector (7 downto 0); + irq_n_i : in std_logic; + nmi_n_i : in std_logic; + rdy_i : in std_logic; + rst_rst_n_i : in std_logic; + so_n_i : in std_logic; + a_o : out std_logic_vector (15 downto 0); + d_o : out std_logic_vector (7 downto 0); + rd_o : out std_logic; + sync_o : out std_logic; + wr_n_o : out std_logic; + wr_o : out std_logic + ); + +-- Declarations + +end core ; + +-- (C) 2008 - 2018 Jens Gutschmidt +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 1.8 2013/08/01 11:00:00 jens +-- - Change Block names to lower case +-- - Bug Fix RMB, SMB Bug - Bit position decoded wrong. Adding a priority encoder. +-- +-- Revision 1.7 2013/07/21 11:11:00 jens +-- - Changing the title block and internal revision history +-- +-- Revision 1.6 2009/01/04 10:20:47 eda +-- Changes for cosmetic issues only +-- +-- Revision 1.5 2009/01/04 09:23:10 eda +-- - Delete unused nets and blocks (same as R6502_TC) +-- - Rename blocks +-- +-- Revision 1.4 2009/01/03 16:53:02 eda +-- - Unused nets and blocks deleted +-- - Renamed blocks +-- +-- Revision 1.3 2009/01/03 16:42:02 eda +-- - Unused nets and blocks deleted +-- - Renamed blocks +-- +-- Revision 1.2 2008/12/31 19:31:24 eda +-- Production Release +-- +-- +-- +-- VHDL Architecture r65c02_tc.core.struct +-- +-- Created: +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 17:51:04 27.09.2018 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt +-- +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. +-- +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +library r65c02_tc; + +architecture struct of core is + + -- Architecture declarations + + -- Internal signal declarations + signal adr_nxt_pc_o_i : std_logic_vector(15 downto 0); + signal adr_o_i : std_logic_vector(15 downto 0); + signal adr_pc_o_i : std_logic_vector(15 downto 0); + signal adr_sp_o_i : std_logic_vector(15 downto 0); + signal ch_a_o_i : std_logic_vector(7 downto 0); + signal ch_b_o_i : std_logic_vector(7 downto 0); + signal d_alu_n_o_i : std_logic; + signal d_alu_o_i : std_logic_vector(7 downto 0); + signal d_alu_or_o_i : std_logic; + signal d_alu_prio_o_i : std_logic_vector(7 downto 0); + signal d_regs_in_o_i : std_logic_vector(7 downto 0); + signal d_regs_out_o_i : std_logic_vector(7 downto 0); + signal ld_o_i : std_logic_vector(1 downto 0); + signal ld_pc_o_i : std_logic; + signal ld_sp_o_i : std_logic; + signal load_regs_o_i : std_logic; + signal nmi_o_i : std_logic; + signal offset_o_i : std_logic_vector(15 downto 0); + signal q_a_o_i : std_logic_vector(7 downto 0); + signal q_x_o_i : std_logic_vector(7 downto 0); + signal q_y_o_i : std_logic_vector(7 downto 0); + signal reg_0flag_o_i : std_logic; + signal reg_1flag_o_i : std_logic; + signal reg_7flag_o_i : std_logic; + signal rst_nmi_o_i : std_logic; + signal sel_pc_in_o_i : std_logic; + signal sel_pc_val_o_i : std_logic_vector(1 downto 0); + signal sel_rb_in_o_i : std_logic_vector(1 downto 0); + signal sel_rb_out_o_i : std_logic_vector(1 downto 0); + signal sel_reg_o_i : std_logic_vector(1 downto 0); + signal sel_sp_as_o_i : std_logic; + signal sel_sp_in_o_i : std_logic; + signal var_shift_data_o_i : std_logic_vector(7 downto 0); + + + -- Component Declarations + component fsm_execution_unit + port ( + adr_nxt_pc_i : in std_logic_vector (15 downto 0); + adr_pc_i : in std_logic_vector (15 downto 0); + adr_sp_i : in std_logic_vector (15 downto 0); + clk_clk_i : in std_logic ; + d_alu_i : in std_logic_vector ( 7 downto 0 ); + d_alu_prio_i : in std_logic_vector (7 downto 0); + d_i : in std_logic_vector ( 7 downto 0 ); + d_regs_out_i : in std_logic_vector ( 7 downto 0 ); + irq_n_i : in std_logic ; + nmi_i : in std_logic ; + q_a_i : in std_logic_vector ( 7 downto 0 ); + q_x_i : in std_logic_vector ( 7 downto 0 ); + q_y_i : in std_logic_vector ( 7 downto 0 ); + rdy_i : in std_logic ; + reg_0flag_i : in std_logic ; + reg_1flag_i : in std_logic ; + reg_7flag_i : in std_logic ; + rst_rst_n_i : in std_logic ; + so_n_i : in std_logic ; + a_o : out std_logic_vector (15 downto 0); + adr_o : out std_logic_vector (15 downto 0); + ch_a_o : out std_logic_vector ( 7 downto 0 ); + ch_b_o : out std_logic_vector ( 7 downto 0 ); + d_o : out std_logic_vector ( 7 downto 0 ); + d_regs_in_o : out std_logic_vector ( 7 downto 0 ); + ld_o : out std_logic_vector ( 1 downto 0 ); + ld_pc_o : out std_logic ; + ld_sp_o : out std_logic ; + load_regs_o : out std_logic ; + offset_o : out std_logic_vector ( 15 downto 0 ); + rd_o : out std_logic ; + rst_nmi_o : out std_logic ; + sel_pc_in_o : out std_logic ; + sel_pc_val_o : out std_logic_vector ( 1 downto 0 ); + sel_rb_in_o : out std_logic_vector ( 1 downto 0 ); + sel_rb_out_o : out std_logic_vector ( 1 downto 0 ); + sel_reg_o : out std_logic_vector ( 1 downto 0 ); + sel_sp_as_o : out std_logic ; + sel_sp_in_o : out std_logic ; + sync_o : out std_logic ; + wr_n_o : out std_logic ; + wr_o : out std_logic + ); + end component; + component fsm_intnmi + port ( + clk_clk_i : in std_logic ; + nmi_n_i : in std_logic ; + rst_nmi_i : in std_logic ; + rst_rst_n_i : in std_logic ; + nmi_o : out std_logic + ); + end component; + component reg_pc + port ( + adr_i : in std_logic_vector (15 downto 0); + clk_clk_i : in std_logic ; + ld_i : in std_logic_vector (1 downto 0); + ld_pc_i : in std_logic ; + offset_i : in std_logic_vector (15 downto 0); + rst_rst_n_i : in std_logic ; + sel_pc_in_i : in std_logic ; + sel_pc_val_i : in std_logic_vector (1 downto 0); + adr_nxt_pc_o : out std_logic_vector (15 downto 0); + adr_pc_o : out std_logic_vector (15 downto 0) + ); + end component; + component reg_sp + port ( + adr_low_i : in std_logic_vector (7 downto 0); + clk_clk_i : in std_logic ; + ld_low_i : in std_logic ; + ld_sp_i : in std_logic ; + rst_rst_n_i : in std_logic ; + sel_sp_as_i : in std_logic ; + sel_sp_in_i : in std_logic ; + adr_sp_o : out std_logic_vector (15 downto 0) + ); + end component; + component regbank_axy + port ( + clk_clk_i : in std_logic ; + d_regs_in_i : in std_logic_vector (7 downto 0); + load_regs_i : in std_logic ; + rst_rst_n_i : in std_logic ; + sel_rb_in_i : in std_logic_vector (1 downto 0); + sel_rb_out_i : in std_logic_vector (1 downto 0); + sel_reg_i : in std_logic_vector (1 downto 0); + d_regs_out_o : out std_logic_vector (7 downto 0); + q_a_o : out std_logic_vector (7 downto 0); + q_x_o : out std_logic_vector (7 downto 0); + q_y_o : out std_logic_vector (7 downto 0) + ); + end component; + + -- Optional embedded configurations + -- pragma synthesis_off + for all : fsm_execution_unit use entity r65c02_tc.fsm_execution_unit; + for all : fsm_intnmi use entity r65c02_tc.fsm_intnmi; + for all : reg_pc use entity r65c02_tc.reg_pc; + for all : reg_sp use entity r65c02_tc.reg_sp; + for all : regbank_axy use entity r65c02_tc.regbank_axy; + -- pragma synthesis_on + + +begin + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + -- eb1 1 + var_shift_data_o_i <= x"01"; + + + -- ModuleWare code(v1.12) for instance 'U_11' of 'add' + u_11combo_proc: process (ch_a_o_i, ch_b_o_i) + variable temp_din0 : std_logic_vector(8 downto 0); + variable temp_din1 : std_logic_vector(8 downto 0); + variable temp_sum : unsigned(8 downto 0); + variable temp_carry : std_logic; + begin + temp_din0 := '0' & ch_a_o_i; + temp_din1 := '0' & ch_b_o_i; + temp_carry := '0'; + temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry; + d_alu_o_i <= conv_std_logic_vector(temp_sum(7 downto 0),8); + reg_0flag_o_i <= temp_sum(8) ; + end process u_11combo_proc; + + -- ModuleWare code(v1.12) for instance 'U_8' of 'inv' + reg_1flag_o_i <= not(d_alu_or_o_i); + + -- ModuleWare code(v1.12) for instance 'U_9' of 'inv' + reg_7flag_o_i <= not(d_alu_n_o_i); + + -- ModuleWare code(v1.12) for instance 'U_10' of 'inv' + d_alu_n_o_i <= not(d_alu_o_i(7)); + + -- ModuleWare code(v1.12) for instance 'U_5' of 'lshift' + u_5combo_proc : process (var_shift_data_o_i, ch_a_o_i) + variable temp_shift : std_logic_vector (3 downto 0); + variable temp_dout : std_logic_vector (7 downto 0); + variable temp_din : std_logic_vector (7 downto 0); + begin + temp_din := (others=> 'X'); + temp_shift := ch_a_o_i(3 downto 0); + temp_din := var_shift_data_o_i; + for i in 0 to 3 loop + if (i < 3) then + if (temp_shift(i) = '1') then + temp_dout := (others => '0'); + temp_dout(7 downto 2**i) := temp_din(7 - 2**i downto 0); + elsif (temp_shift(i) = '0') then + temp_dout := temp_din; + else + temp_dout := (others => 'X'); + end if; + else + if (temp_shift(i) = '1') then + temp_dout := (others => '0'); + elsif (temp_shift(i) = '0') then + temp_dout := temp_din; + else + temp_dout := (others => 'X'); + end if; + end if; + temp_din := temp_dout; + end loop; + d_alu_prio_o_i <= temp_dout; + end process u_5combo_proc; + + -- ModuleWare code(v1.12) for instance 'U_7' of 'por' + d_alu_or_o_i <= d_alu_o_i(0) or d_alu_o_i(1) or d_alu_o_i(2) or d_alu_o_i(3) or d_alu_o_i(4) or d_alu_o_i(5) or d_alu_o_i(6) or d_alu_o_i(7); + + -- Instance port mappings. + U_4 : fsm_execution_unit + port map ( + adr_nxt_pc_i => adr_nxt_pc_o_i, + adr_pc_i => adr_pc_o_i, + adr_sp_i => adr_sp_o_i, + clk_clk_i => clk_clk_i, + d_alu_i => d_alu_o_i, + d_alu_prio_i => d_alu_prio_o_i, + d_i => d_i, + d_regs_out_i => d_regs_out_o_i, + irq_n_i => irq_n_i, + nmi_i => nmi_o_i, + q_a_i => q_a_o_i, + q_x_i => q_x_o_i, + q_y_i => q_y_o_i, + rdy_i => rdy_i, + reg_0flag_i => reg_0flag_o_i, + reg_1flag_i => reg_1flag_o_i, + reg_7flag_i => reg_7flag_o_i, + rst_rst_n_i => rst_rst_n_i, + so_n_i => so_n_i, + a_o => a_o, + adr_o => adr_o_i, + ch_a_o => ch_a_o_i, + ch_b_o => ch_b_o_i, + d_o => d_o, + d_regs_in_o => d_regs_in_o_i, + ld_o => ld_o_i, + ld_pc_o => ld_pc_o_i, + ld_sp_o => ld_sp_o_i, + load_regs_o => load_regs_o_i, + offset_o => offset_o_i, + rd_o => rd_o, + rst_nmi_o => rst_nmi_o_i, + sel_pc_in_o => sel_pc_in_o_i, + sel_pc_val_o => sel_pc_val_o_i, + sel_rb_in_o => sel_rb_in_o_i, + sel_rb_out_o => sel_rb_out_o_i, + sel_reg_o => sel_reg_o_i, + sel_sp_as_o => sel_sp_as_o_i, + sel_sp_in_o => sel_sp_in_o_i, + sync_o => sync_o, + wr_n_o => wr_n_o, + wr_o => wr_o + ); + U_3 : fsm_intnmi + port map ( + clk_clk_i => clk_clk_i, + nmi_n_i => nmi_n_i, + rst_nmi_i => rst_nmi_o_i, + rst_rst_n_i => rst_rst_n_i, + nmi_o => nmi_o_i + ); + U_0 : reg_pc + port map ( + adr_i => adr_o_i, + clk_clk_i => clk_clk_i, + ld_i => ld_o_i, + ld_pc_i => ld_pc_o_i, + offset_i => offset_o_i, + rst_rst_n_i => rst_rst_n_i, + sel_pc_in_i => sel_pc_in_o_i, + sel_pc_val_i => sel_pc_val_o_i, + adr_nxt_pc_o => adr_nxt_pc_o_i, + adr_pc_o => adr_pc_o_i + ); + U_1 : reg_sp + port map ( + adr_low_i => adr_o_i(7 DOWNTO 0), + clk_clk_i => clk_clk_i, + ld_low_i => ld_o_i(0), + ld_sp_i => ld_sp_o_i, + rst_rst_n_i => rst_rst_n_i, + sel_sp_as_i => sel_sp_as_o_i, + sel_sp_in_i => sel_sp_in_o_i, + adr_sp_o => adr_sp_o_i + ); + U_2 : regbank_axy + port map ( + clk_clk_i => clk_clk_i, + d_regs_in_i => d_regs_in_o_i, + load_regs_i => load_regs_o_i, + rst_rst_n_i => rst_rst_n_i, + sel_rb_in_i => sel_rb_in_o_i, + sel_rb_out_i => sel_rb_out_o_i, + sel_reg_i => sel_reg_o_i, + d_regs_out_o => d_regs_out_o_i, + q_a_o => q_a_o_i, + q_x_o => q_x_o_i, + q_y_o => q_y_o_i + ); + +end struct; Index: cpu65c02_true_cycle/trunk/beta/rtl/vhdl/fsm_execution_unit.vhd =================================================================== --- cpu65c02_true_cycle/trunk/beta/rtl/vhdl/fsm_execution_unit.vhd (nonexistent) +++ cpu65c02_true_cycle/trunk/beta/rtl/vhdl/fsm_execution_unit.vhd (revision 23) @@ -0,0 +1,4974 @@ +-- VHDL Entity r65c02_tc.fsm_execution_unit.symbol +-- +-- Created: +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 15:56:20 27.08.2018 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +entity fsm_execution_unit is + port( + adr_nxt_pc_i : in std_logic_vector (15 downto 0); + adr_pc_i : in std_logic_vector (15 downto 0); + adr_sp_i : in std_logic_vector (15 downto 0); + clk_clk_i : in std_logic; + d_alu_i : in std_logic_vector ( 7 downto 0 ); + d_alu_prio_i : in std_logic_vector (7 downto 0); + d_i : in std_logic_vector ( 7 downto 0 ); + d_regs_out_i : in std_logic_vector ( 7 downto 0 ); + irq_n_i : in std_logic; + nmi_i : in std_logic; + q_a_i : in std_logic_vector ( 7 downto 0 ); + q_x_i : in std_logic_vector ( 7 downto 0 ); + q_y_i : in std_logic_vector ( 7 downto 0 ); + rdy_i : in std_logic; + reg_0flag_i : in std_logic; + reg_1flag_i : in std_logic; + reg_7flag_i : in std_logic; + rst_rst_n_i : in std_logic; + so_n_i : in std_logic; + a_o : out std_logic_vector (15 downto 0); + adr_o : out std_logic_vector (15 downto 0); + ch_a_o : out std_logic_vector ( 7 downto 0 ); + ch_b_o : out std_logic_vector ( 7 downto 0 ); + d_o : out std_logic_vector ( 7 downto 0 ); + d_regs_in_o : out std_logic_vector ( 7 downto 0 ); + ld_o : out std_logic_vector ( 1 downto 0 ); + ld_pc_o : out std_logic; + ld_sp_o : out std_logic; + load_regs_o : out std_logic; + offset_o : out std_logic_vector ( 15 downto 0 ); + rd_o : out std_logic; + rst_nmi_o : out std_logic; + sel_pc_in_o : out std_logic; + sel_pc_val_o : out std_logic_vector ( 1 downto 0 ); + sel_rb_in_o : out std_logic_vector ( 1 downto 0 ); + sel_rb_out_o : out std_logic_vector ( 1 downto 0 ); + sel_reg_o : out std_logic_vector ( 1 downto 0 ); + sel_sp_as_o : out std_logic; + sel_sp_in_o : out std_logic; + sync_o : out std_logic; + wr_n_o : out std_logic; + wr_o : out std_logic + ); + +-- Declarations + +end fsm_execution_unit ; + +-- (C) 2008 - 2018 Jens Gutschmidt +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 1.13 2018/10/14 11:50:00 jens +-- - Performance improvements +-- Revision 1.1202 2018/09/10 12:14:00 jens +-- - RESET generates SYNC now, 1 dead cycle delayed +-- Revision 1.1202 RC 2018/09/09 03:00:00 jens +-- - ADC / SBC flags and A like R65C02 now +-- Revision 1.1202 BETA 2018/09/05 19:35:00 jens +-- - BBRx/BBSx internal cycles like real 65C02 now +-- - Bug Fix ADC and SBC in decimal mode (all op codes - +-- 1 cycle is missing +-- - Bug Fix ADC and SBC in decimal mode (all op codes - +-- "Overflow" flag was computed wrong) +-- Revision 1.1202 BETA 2018/09/02 18:49:00 jens +-- - Interrupt NMI and IRQ processing via FETCH stage now +-- Revision 1.1202 BETA 2018/08/30 15:39:00 jens +-- - Interrupt priority order is now: BRQ - NMI - IRQ +-- - Performance improvements on-going (Mealy -> Moore) +-- Revision 1.1202 BETA 2018/08/23 20:27:00 jens +-- - Bug Fixes All Branch Instructions +-- (BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS, BRA) +-- 3 cycles now if branch forward occur and the branch +-- instruction lies on a xxFEh location. +-- (BBR, BBS) 6 cycles now if branch forward occur and the +-- branch instruction lies on a xxFDh location. +-- - Bug Fix Hardware Interrupts NMI & IRQ - 7 cycles & "SYNC" now +-- - Bug Fix Now all cycles are delayable (WR and internal) +-- +-- Revision 1.1201 BETA 2014/04/19 14:44:00 jens +-- (never submitted to opencores) +-- - Bug Fix JMP ABS - produced a 6502 like JMP (IND) PCH. +-- When the ABS address data bytes cross the page +-- boundary (e.g. $02FE JMP hhll reads hh from +-- $02FF and ll from $0200, instead $02FF and $0300) +-- +-- Revision 1.12 RC 2013/07/31 11:53:00 jens +-- - Bug Fix CMP (IND) - wrongly decoded as function AND +-- - Bug Fix BRK should clear decimal flag P Reg +-- - Bug Fix JMP (ABS,X) - Low Address outputted twice - no High Address +-- - Bug Fix Unknown Ops - Used allways 1b2c NOP ($EA) - new NOPs created +-- - Bug Fix DECIMAL ADC and SBC (all op codes - "C" flag was computed wrong) +-- - Bug Fix INC/DEC ABS,X - N/Z flag wrongly computed +-- - Bug Fix RTI - should increment stack pointer (decremented) +-- - Bug Fix "E" & "B" flags (Bits 5 & 4) - should be always "1" in P Reg. Change "RES", "RTI", "IRQ" & "NMI" substates. +-- - Bug Fix ADC and SBC (all op codes - "Overflow" flag was computed wrong) +-- - Bug Fix RMB, SMB Bug - Bit position decoded wrong. +-- +-- Revision 1.11 2013/07/21 11:11:00 jens +-- - Changing the title block and internal revision history +-- - Bug Fix STA [(IND)] op$92 ($92 was missed in the connection list at state FETCH) +-- +-- Revision 1.10 2010/02/08 17:34:20 eda +-- BUGFIX for IRQn, NMIn and RTI +-- After detection of NMI or IRQ the address of the next instruction stacked wrong. +-- NMI now overwrites the vector address of IRQ if NMI asserted after IRQ and the +-- vector address is not loaded yet. +-- +-- +-- Revision 1.9 2010/02/08 17:32:19 eda +-- BUGFIX for IRQn, NMIn and RTI +-- After detection of NMI or IRQ the address of the next instruction stacked wrong. +-- NMI now overwrites the vector address of IRQ if NMI asserted after IRQ and the +-- vector address is not loaded yet. +-- +-- +-- Revision 1.8 2009/01/04 20:23:42 eda +-- *** EMERGENCY BUGFIX *** +-- - Signal rd_o was corrupted in last version. wr_o and wr_n are not effected. +-- - OP JMP (indirect) produced a 65C02 like jump. On 6502 a special case exist +-- when the (indirect) address cross the page boundary (e.g. JMP (02FF) reads from +-- $02FF and $0200, instead of $02FF and $0300) +-- +-- Revision 1.7 2009/01/04 16:54:59 eda +-- - Removed unused bits in ALU (zw_ALUx) +-- +-- Revision 1.6 2009/01/04 10:27:49 eda +-- Changes for cosmetic issues only +-- +-- Revision 1.5 2009/01/04 10:25:04 eda +-- Changes for cosmetic issues only +-- +-- Revision 1.4 2009/01/03 16:53:01 eda +-- - Unused nets and blocks deleted +-- - Re-arragend symbols in block FSM_Execution_Unit +-- - Renamed blocks +-- - Input SO implemented +-- +-- Revision 1.3 2009/01/03 16:42:02 eda +-- - Unused nets and blocks deleted +-- - Re-arragend symbols in block FSM_Execution_Unit +-- - Renamed blocks +-- - Input SO implemented +-- +-- Revision 1.2 2008/12/31 19:31:24 eda +-- Production Release +-- +-- +-- (C) 2008 - 2018 Jens Gutschmidt +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 1.01 2018/10/14 11:57:00 jens +-- Production Release +-- +-- +-- (C) 2008 - 2018 Jens Gutschmidt +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 1.01 2018/09/26 11:11:00 jens +-- Production Release +-- +-- +-- (C) 2008 - 2018 Jens Gutschmidt +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 1.01 2018/09/26 11:11:00 jens +-- Production Release +-- +-- +-- (C) 2008 - 2018 Jens Gutschmidt +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 1.01 2018/09/26 11:11:00 jens +-- Production Release +-- +-- +-- (C) 2008 - 2018 Jens Gutschmidt +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 1.01 2018/10/02 10:36:00 jens +-- Production Release +-- +-- +-- +-- VHDL Architecture r65c02_tc.fsm_execution_unit.fsm +-- +-- Created: +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 12:03:14 14.10.2018 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt +-- +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. +-- +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along with this program. If not, see . +-- +-- +-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt +-- +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. +-- +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +architecture fsm of fsm_execution_unit is + + -- Architecture Declarations + signal adc_sbc_finished : std_logic; + signal addr_correction : std_logic_vector(7 DOWNTO 0); + signal c_detect_out : std_logic; + signal cnz_detect_in : std_logic_vector(8 DOWNTO 0); + signal irq_finished : std_logic; + signal n_detect_out : std_logic; + signal op_fetch : std_logic; + signal op_finished : std_logic; + signal reg_F : std_logic_vector( 7 DOWNTO 0 ); + signal reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 ); + signal reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 ); + signal reg_sel_reg : std_logic_vector( 1 DOWNTO 0 ); + signal rmb_started : std_logic; + signal rst_finished : std_logic; + signal sel_pc_in : std_logic; + signal sel_pc_val : std_logic_vector( 1 DOWNTO 0 ); + signal sel_sp_as : std_logic; + signal sel_sp_in : std_logic; + signal shift_rot_asl_out : std_logic_vector( 7 DOWNTO 0 ); + signal shift_rot_in : std_logic_vector( 7 DOWNTO 0 ); + signal shift_rot_l_c_out : std_logic; + signal shift_rot_lsr_out : std_logic_vector( 7 DOWNTO 0 ); + signal shift_rot_r_c_out : std_logic; + signal shift_rot_rol_out : std_logic_vector( 7 DOWNTO 0 ); + signal shift_rot_ror_out : std_logic_vector( 7 DOWNTO 0 ); + signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 ); + signal sig_PC : std_logic_vector(15 DOWNTO 0); + signal sig_RD : std_logic; + signal sig_RWn : std_logic; + signal sig_SYNC : std_logic; + signal sig_WR : std_logic; + signal z_detect_out : std_logic; + signal zw_ALU : std_logic_vector(9 DOWNTO 0); + signal zw_ALU1 : std_logic_vector(9 DOWNTO 0); + signal zw_ALU2 : std_logic_vector(9 DOWNTO 0); + signal zw_ALU3 : std_logic_vector(9 DOWNTO 0); + signal zw_ALU4 : std_logic_vector(9 DOWNTO 0); + signal zw_ALU5 : std_logic_vector(9 DOWNTO 0); + signal zw_ALU6 : std_logic_vector(9 DOWNTO 0); + signal zw_PC : std_logic_vector( 15 DOWNTO 0 ); + signal zw_REG_ALU : std_logic_vector( 8 DOWNTO 0 ); + signal zw_REG_OP : std_logic_vector( 7 DOWNTO 0 ); + signal zw_REG_sig_PC : std_logic_vector(15 DOWNTO 0); + signal zw_b1 : std_logic_vector( 7 DOWNTO 0 ); + signal zw_b10 : std_logic_vector(9 DOWNTO 0); + signal zw_b11 : std_logic_vector( 7 DOWNTO 0 ); + signal zw_b12 : std_logic_vector( 7 DOWNTO 0 ); + signal zw_b13 : std_logic_vector( 7 DOWNTO 0 ); + signal zw_b14 : std_logic_vector( 7 DOWNTO 0 ); + signal zw_b2 : std_logic_vector( 7 DOWNTO 0 ); + signal zw_b3 : std_logic_vector( 7 DOWNTO 0 ); + signal zw_b4 : std_logic_vector( 7 DOWNTO 0 ); + signal zw_b5 : std_logic_vector( 7 DOWNTO 0 ); + signal zw_b6 : std_logic_vector( 7 DOWNTO 0 ); + signal zw_b7 : std_logic_vector(9 DOWNTO 0); + signal zw_b8 : std_logic_vector(9 DOWNTO 0); + signal zw_b9 : std_logic_vector(9 DOWNTO 0); + signal zw_din : std_logic_vector(7 DOWNTO 0); + signal zw_reg_0flag : std_logic; + signal zw_so : std_logic; + signal zw_w1 : std_logic_vector( 15 DOWNTO 0 ); + signal zw_w2 : std_logic_vector( 15 DOWNTO 0 ); + signal zw_w3 : std_logic_vector( 15 DOWNTO 0 ); + + type csm_state_type is ( + res2, + res4, + res5, + res6, + res7, + res3, + RES, + FETCH, + s6, + s10, + s268, + s305, + s306, + jmp1, + jmp2_1, + jmp4_12, + jmp_ex, + jmp2_2, + jmp3_1, + jsr1, + jsr2, + jsr3, + jsr4, + jsr5, + brk1, + brk2, + brk3, + brk4, + brk6, + brk5, + rti1, + rti2, + rti3, + rti4, + rti5, + rts1, + rts2, + rts3, + rts4, + rts5, + pha1, + pha2, + php1, + php2, + pla1, + pla2, + pla3, + plp1, + plp2, + plp3, + irq1, + irq2, + irq3, + irq5b, + irq5a, + irq4, + irq6a, + s11, + s12, + s20, + s14, + s21, + s23, + s15, + s25, + s28, + s16, + s30, + s31, + s32, + s33, + s34, + s36, + jmp3_2, + s270, + s307, + s308, + s271, + s272, + s309, + RES0, + zp1, + zp2, + zpx1, + zpx2, + zpx3, + ab1, + ab2, + ab3, + absx1, + absx2, + absx4, + absx3, + ind1, + ind3, + ind4, + ind2, + indy1, + indy2, + indy3, + indy5, + indy4, + indx1, + indx4, + indx2, + indx3, + indx5, + zpy1, + zpy2, + zpy3, + absy2, + absy1, + absy4, + absy3, + imm1, + imp1, + irq6b, + absx5, + absy5, + indy6, + s237, + s348, + s254, + s255, + s238, + s257, + s350, + s258, + s259, + s239, + s260, + s352, + s263, + s264, + s240, + s266, + s353, + s354, + s269, + s273, + zp2w, + zpx3w, + zpy3w, + ab3w, + absx4w, + absx3w, + absy4w, + absy3w, + ind4w, + indx5w, + indy5w, + indy4w, + s256, + s261, + s265, + s274, + s355, + zp3, + zpx4, + ab4, + ind5, + indx6, + imm2 + ); + type csm_functions_state_type is ( + f_idle, + f_and, + f_lda, + f_rst, + f_eor, + f_cmp, + f_ora, + f_clc, + f_sec, + f_cld, + f_sed, + f_clv, + f_cli, + f_sei, + f_rti, + f_irq, + f_res, + f_bit1, + f_bit2, + f_de_in_a, + f_adc_bin, + f_sbc_bin, + f_adc_dec, + f_adc_dec1, + f_sbc_dec, + f_sbc_dec1, + f_asla, + f_lsra, + f_rola, + f_rora, + f_tax, + f_tsx, + f_decr, + f_asl, + f_lsr, + f_rol, + f_ror, + f_rmb, + f_smb, + f_trb, + f_tsb + ); + type csm_rb_out_state_type is ( + rb_out_idle, + rb_out_01, + rb_out_10, + rb_out_11 + ); + type csm_reg_state_type is ( + reg_idle, + reg_10, + reg_11, + reg_01 + ); + type csm_rb_in_state_type is ( + rb_in_idle, + rb_in_01, + rb_in_10, + rb_in_00 + ); + type csm_add_value_state_type is ( + add_val_idle, + add_val + ); + + -- Declare current and next state signals + signal csm_current_state : csm_state_type; + signal csm_next_state : csm_state_type; + signal csm_functions_current_state : csm_functions_state_type; + signal csm_functions_next_state : csm_functions_state_type; + signal csm_rb_out_current_state : csm_rb_out_state_type; + signal csm_rb_out_next_state : csm_rb_out_state_type; + signal csm_reg_current_state : csm_reg_state_type; + signal csm_reg_next_state : csm_reg_state_type; + signal csm_rb_in_current_state : csm_rb_in_state_type; + signal csm_rb_in_next_state : csm_rb_in_state_type; + signal csm_add_value_current_state : csm_add_value_state_type; + signal csm_add_value_next_state : csm_add_value_state_type; + + -- Declare any pre-registered internal signals + signal sync_o_cld : std_logic ; + +begin + + ----------------------------------------------------------------- + csm_clocked_proc : process ( + clk_clk_i, + rst_rst_n_i + ) + ----------------------------------------------------------------- + begin + if (rst_rst_n_i = '0') then + csm_current_state <= RES; + -- Default Reset Values + sync_o_cld <= '0'; + reg_sel_rb_in <= "00"; + reg_sel_rb_out <= "00"; + reg_sel_reg <= "00"; + zw_PC <= X"0000"; + zw_REG_ALU <= '0' & X"00"; + zw_REG_OP <= X"00"; + zw_REG_sig_PC <= X"0000"; + zw_b1 <= X"00"; + zw_b11 <= X"00"; + zw_b12 <= X"00"; + zw_b2 <= X"00"; + zw_b3 <= X"00"; + zw_b5 <= X"00"; + zw_b6 <= X"00"; + zw_reg_0flag <= '0'; + zw_so <= '0'; + zw_w1 <= X"0000"; + zw_w2 <= X"0000"; + zw_w3 <= X"0000"; + elsif (clk_clk_i'event and clk_clk_i = '1') then + csm_current_state <= csm_next_state; + -- Default Assignment To Internals + reg_sel_rb_in <= reg_sel_rb_in; + reg_sel_rb_out <= reg_sel_rb_out; + reg_sel_reg <= reg_sel_reg; + zw_PC <= zw_PC; + zw_REG_ALU <= zw_REG_ALU; + zw_REG_OP <= zw_REG_OP; + zw_REG_sig_PC <= zw_REG_sig_PC; + zw_b1 <= zw_b1; + zw_b11 <= zw_b11; + zw_b12 <= zw_b12; + zw_b2 <= zw_b2; + zw_b3 <= zw_b3; + zw_b5 <= zw_b5; + zw_b6 <= zw_b6; + zw_reg_0flag <= zw_reg_0flag; + zw_so <= (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6))); + zw_w1 <= zw_w1; + zw_w2 <= zw_w2; + zw_w3 <= zw_w3; + sync_o_cld <= sig_SYNC; + + -- Combined Actions + case csm_current_state is + when res6 => + zw_b5 <= d_i; + when FETCH => + zw_REG_OP <= d_i; + if ((d_i = X"00") and (rdy_i = '1')) then + elsif ((nmi_i = '1') and (rdy_i = '1')) then + zw_w3 <= adr_pc_i; + elsif ((irq_n_i = '0' and + reg_F(2) = '0') and (rdy_i = '1')) then + zw_w3 <= adr_pc_i; + end if; + when s268 => + zw_b3 <= adr_nxt_pc_i (15 downto 8); + zw_b2 <= d_i; + when jmp1 => + zw_b5 <= d_i; + when jmp2_1 => + zw_b6 <= d_i; + when jmp4_12 => + zw_b5 <= d_i; + when jmp2_2 => + zw_b6 <= d_i; + when jsr1 => + zw_b1 <= d_i; + when jsr2 => + zw_b11 <= adr_pc_i (15 downto 8); + zw_b12 <= adr_pc_i (7 downto 0); + when brk1 => + zw_b11 <= adr_nxt_pc_i (15 downto 8); + zw_b12 <= adr_nxt_pc_i (7 downto 0); + when brk3 => + zw_b11 <= reg_F OR X"30"; + when brk5 => + zw_b5 <= d_i; + when rti4 => + zw_b5 <= d_i; + when rts3 => + zw_b5 <= d_i; + when rts4 => + zw_b6 <= d_i; + when irq1 => + zw_b11 <= zw_w3 (15 downto 8); + zw_b12 <= zw_w3 (7 downto 0); + when irq3 => + zw_b11 <= reg_F AND X"EF"; + when irq5b => + zw_b5 <= d_i; + when irq5a => + zw_b5 <= d_i; + when s270 => + zw_b2 <= d_i; + when s308 => + zw_w3 <= adr_pc_i; + zw_b2 <= d_i; + zw_b3 <= adr_nxt_pc_i (15 downto 8); + when s272 => + zw_b1 <= d_i; + when zp1 => + zw_b5 <= d_i; + zw_b11 <= d_regs_out_i; + when zpx1 => + zw_b5 <= d_i; + zw_b11 <= d_regs_out_i; + when zpx2 => + zw_b1 <= d_alu_i; + when ab1 => + zw_b5 <= d_i; + zw_b11 <= d_regs_out_i; + when ab2 => + zw_b6 <= d_i; + when absx1 => + zw_b5 <= d_i; + zw_b11 <= d_regs_out_i; + when absx2 => + zw_b6 <= d_i; + zw_b1 <= d_alu_i; + zw_reg_0flag <= reg_0flag_i; + when absx3 => + zw_b3 <= d_alu_i; + when ind1 => + zw_b5 <= d_i; + zw_b11 <= d_regs_out_i; + when ind3 => + zw_b5 <= d_i; + when ind2 => + zw_b1 <= d_alu_i; + zw_b6 <= d_i; + when indy1 => + zw_b5 <= d_i; + zw_b11 <= d_regs_out_i; + when indy2 => + zw_b2 <= d_i; + zw_b1 <= d_alu_i; + when indy3 => + zw_b5 <= d_i; + zw_b6 <= d_alu_i; + zw_reg_0flag <= reg_0flag_i; + when indy4 => + zw_b3 <= d_alu_i; + when indx1 => + zw_b5 <= d_i; + zw_b11 <= d_regs_out_i; + when indx4 => + zw_b2 <= d_i; + when indx2 => + zw_b1 <= d_alu_i; + when indx3 => + zw_b5 <= d_i; + zw_b6 <= d_alu_i; + when zpy1 => + zw_b5 <= d_i; + zw_b11 <= d_regs_out_i; + when zpy2 => + zw_b1 <= d_alu_i; + when absy2 => + zw_b6 <= d_i; + zw_b1 <= d_alu_i; + zw_reg_0flag <= reg_0flag_i; + when absy1 => + zw_b5 <= d_i; + zw_b11 <= d_regs_out_i; + when absy3 => + zw_b3 <= d_alu_i; + when s237 => + zw_b5 <= d_i; + when s348 => + zw_b2 <= d_i; + when s254 => + zw_b11 <= d_alu_i; + when s238 => + zw_b5 <= d_i; + when s257 => + zw_b1 <= d_alu_i; + when s350 => + zw_b2 <= d_i; + when s258 => + zw_b11 <= d_alu_i; + when s239 => + zw_b5 <= d_i; + when s260 => + zw_b6 <= d_i; + when s352 => + zw_b2 <= d_i; + when s263 => + zw_b11 <= d_alu_i; + when s240 => + zw_b5 <= d_i; + when s266 => + zw_b6 <= d_i; + zw_b1 <= d_alu_i; + zw_reg_0flag <= reg_0flag_i; + when s353 => + zw_b2 <= d_i; + zw_b3 <= d_alu_i; + when s354 => + zw_b2 <= d_i; + when s269 => + zw_b11 <= d_alu_i; + when absx3w => + zw_b3 <= d_alu_i; + when absy3w => + zw_b3 <= d_alu_i; + when indy4w => + zw_b3 <= d_alu_i; + when s256 => + zw_b11 <= zw_b13; + when s261 => + zw_b11 <= zw_b13; + when s265 => + zw_b11 <= zw_b13; + when s274 => + zw_b11 <= zw_b13; + when others => + null; + end case; + end if; + end process csm_clocked_proc; + + ----------------------------------------------------------------- + csm_nextstate_proc : process ( + addr_correction, + csm_current_state, + d_i, + irq_n_i, + nmi_i, + rdy_i, + reg_F, + zw_REG_OP, + zw_b1, + zw_reg_0flag + ) + ----------------------------------------------------------------- + begin + case csm_current_state is + when res2 => + if (rdy_i = '1') then + csm_next_state <= res3; + else + csm_next_state <= res2; + end if; + when res4 => + if (rdy_i = '1') then + csm_next_state <= res5; + else + csm_next_state <= res4; + end if; + when res5 => + if (rdy_i = '1') then + csm_next_state <= res6; + else + csm_next_state <= res5; + end if; + when res6 => + if (rdy_i = '1') then + csm_next_state <= res7; + else + csm_next_state <= res6; + end if; + when res7 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= res7; + end if; + when res3 => + if (rdy_i = '1') then + csm_next_state <= res4; + else + csm_next_state <= res3; + end if; + when RES => + csm_next_state <= RES0; + when FETCH => + if ((d_i = X"00") and (rdy_i = '1')) then + csm_next_state <= brk1; + elsif ((nmi_i = '1') and (rdy_i = '1')) then + csm_next_state <= irq1; + elsif ((irq_n_i = '0' and + reg_F(2) = '0') and (rdy_i = '1')) then + csm_next_state <= irq1; + elsif ((d_i = X"8F" or + d_i = X"9F" or + d_i = X"AF" or + d_i = X"BF" or + d_i = X"CF" or + d_i = X"DF" or + d_i = X"EF" or + d_i = X"FF" or + d_i = X"0F" or + d_i = X"1F" or + d_i = X"2F" or + d_i = X"3F" or + d_i = X"4F" or + d_i = X"5F" or + d_i = X"6F" or + d_i = X"7F") and (rdy_i = '1')) then + csm_next_state <= s270; + elsif ((d_i = X"90" or + d_i = X"B0" or + d_i = X"F0" or + d_i = X"30" or + d_i = X"D0" or + d_i = X"10" or + d_i = X"50" or + d_i = X"70" or + d_i = X"80") and (rdy_i = '1')) then + csm_next_state <= s268; + elsif ((d_i = X"4C" or + d_i = X"6C" or + d_i = X"7C") and (rdy_i = '1')) then + csm_next_state <= jmp1; + elsif ((d_i = X"20") and (rdy_i = '1')) then + csm_next_state <= jsr1; + elsif ((d_i = X"68") and (rdy_i = '1')) then + csm_next_state <= pla1; + elsif ((d_i = X"FA") and (rdy_i = '1')) then + csm_next_state <= pla1; + elsif ((d_i = X"C6" or + d_i = X"E6" or + d_i = X"66" or + d_i = X"06" or + d_i = X"46" or + d_i = X"26" or + d_i (3 downto 0) = X"7" or + d_i = X"14" or + d_i = X"04") and (rdy_i = '1')) then + csm_next_state <= s237; + elsif ((d_i = X"D6" or + d_i = X"F6" or + d_i = X"76" or + d_i = X"16" or + d_i = X"56" or + d_i = X"36") and (rdy_i = '1')) then + csm_next_state <= s238; + elsif ((d_i = X"CE" or + d_i = X"EE" or + d_i = X"6E" or + d_i = X"0E" or + d_i = X"4E" or + d_i = X"2E" or + d_i = X"1C" or + d_i = X"0C") and (rdy_i = '1')) then + csm_next_state <= s239; + elsif ((d_i = X"DE" or + d_i = X"FE" or + d_i = X"7E" or + d_i = X"1E" or + d_i = X"5E" or + d_i = X"3E") and (rdy_i = '1')) then + csm_next_state <= s240; + elsif ((d_i = X"09" or + d_i = X"29" or + d_i = X"49" or + d_i = X"69" or + d_i = X"89" or + d_i = X"A0" or + d_i = X"A2" or + d_i = X"A9" or + d_i = X"C9" or + d_i = X"E0" or + d_i = X"C0" or + d_i = X"E9") and (rdy_i = '1')) then + csm_next_state <= imm1; + elsif ((d_i = X"05" or + d_i = X"25" or + d_i = X"45" or + d_i = X"65" or + d_i = X"A5" or + d_i = X"24" or + d_i = X"C5" or + d_i = X"E4" or + d_i = X"C4" or + d_i = X"A6" or + d_i = X"A4" or + d_i = X"E5" or + d_i = X"85" or + d_i = X"86" or + d_i = X"84" or + d_i = X"64") and (rdy_i = '1')) then + csm_next_state <= zp1; + elsif ((d_i = X"15" or + d_i = X"35" or + d_i = X"55" or + d_i = X"75" or + d_i = X"B5" or + d_i = X"34" or + d_i = X"D5" or + d_i = X"B4" or + d_i = X"F5" or + d_i = X"95" or + d_i = X"94" or + d_i = X"74") and (rdy_i = '1')) then + csm_next_state <= zpx1; + elsif ((d_i = X"B6" or + d_i = X"96") and (rdy_i = '1')) then + csm_next_state <= zpy1; + elsif ((d_i = X"6D" or + d_i = X"2D" or + d_i = X"2C" or + d_i = X"CD" or + d_i = X"CC" or + d_i = X"EC" or + d_i = X"4D" or + d_i = X"AD" or + d_i = X"AE" or + d_i = X"AC" or + d_i = X"0D" or + d_i = X"ED" or + d_i = X"8D" or + d_i = X"8E" or + d_i = X"8C" or + d_i = X"9C") and (rdy_i = '1')) then + csm_next_state <= ab1; + elsif ((d_i = X"7D" or + d_i = X"3D" or + d_i = X"3C" or + d_i = X"DD" or + d_i = X"5D" or + d_i = X"BD" or + d_i = X"BC" or + d_i = X"1D" or + d_i = X"FD" or + d_i = X"9D" or + d_i = X"9E") and (rdy_i = '1')) then + csm_next_state <= absx1; + elsif ((d_i = X"79" or + d_i = X"39" or + d_i = X"D9" or + d_i = X"5D" or + d_i = X"59" or + d_i = X"B9" or + d_i = X"BE" or + d_i = X"19" or + d_i = X"F9" or + d_i = X"99") and (rdy_i = '1')) then + csm_next_state <= absy1; + elsif ((d_i = X"72" or + d_i = X"32" or + d_i = X"D2" or + d_i = X"59" or + d_i = X"52" or + d_i = X"B2" or + d_i = X"12" or + d_i = X"F2" or + d_i = X"92") and (rdy_i = '1')) then + csm_next_state <= ind1; + elsif ((d_i = X"71" or + d_i = X"31" or + d_i = X"D1" or + d_i = X"51" or + d_i = X"B1" or + d_i = X"11" or + d_i = X"F1" or + d_i = X"91") and (rdy_i = '1')) then + csm_next_state <= indy1; + elsif ((d_i = X"61" or + d_i = X"21" or + d_i = X"C1" or + d_i = X"41" or + d_i = X"A1" or + d_i = X"01" or + d_i = X"E1" or + d_i = X"81") and (rdy_i = '1')) then + csm_next_state <= indx1; + elsif ((d_i = X"B8" or + d_i = X"38" or + d_i = X"18" or + d_i = X"F8" or + d_i = X"D8" or + d_i = X"78" or + d_i = X"58" or + d_i = X"0A" or + d_i = X"4A" or + d_i = X"2A" or + d_i = X"6A" or + d_i = X"A8" or + d_i = X"98" or + d_i = X"BA" or + d_i = X"8A" or + d_i = X"AA" or + d_i = X"C8" or + d_i = X"E8" or + d_i = X"1A" or + d_i = X"88" or + d_i = X"CA" or + d_i = X"3A") and (rdy_i = '1')) then + csm_next_state <= imp1; + elsif ((d_i = X"7A") and (rdy_i = '1')) then + csm_next_state <= pla1; + elsif ((d_i = X"28") and (rdy_i = '1')) then + csm_next_state <= plp1; + elsif ((d_i = X"9A") and (rdy_i = '1')) then + csm_next_state <= s10; + elsif ((d_i = X"60") and (rdy_i = '1')) then + csm_next_state <= rts1; + elsif ((d_i = X"40") and (rdy_i = '1')) then + csm_next_state <= rti1; + elsif ((d_i = X"08") and (rdy_i = '1')) then + csm_next_state <= php1; + elsif ((d_i = X"5A") and (rdy_i = '1')) then + csm_next_state <= pha1; + elsif ((d_i = X"DA") and (rdy_i = '1')) then + csm_next_state <= pha1; + elsif ((d_i = X"48") and (rdy_i = '1')) then + csm_next_state <= pha1; + elsif ((d_i = X"EA") and (rdy_i = '1')) then + csm_next_state <= s6; + elsif ((d_i(3 downto 0) = X"3" or + d_i(3 downto 0) = X"B") and (rdy_i = '1')) then + csm_next_state <= FETCH; + elsif ((d_i = X"02" or + d_i = X"22" or + d_i = X"42" or + d_i = X"62" or + d_i = X"82" or + d_i = X"C2" or + d_i = X"E2") and (rdy_i = '1')) then + csm_next_state <= s11; + elsif ((d_i = X"44") and (rdy_i = '1')) then + csm_next_state <= s12; + elsif ((d_i = X"54" or + d_i = X"D4" or + d_i = X"F4") and (rdy_i = '1')) then + csm_next_state <= s14; + elsif ((d_i = X"DC" or + d_i = X"FC") and (rdy_i = '1')) then + csm_next_state <= s15; + elsif ((d_i = X"5C") and (rdy_i = '1')) then + csm_next_state <= s16; + else + csm_next_state <= FETCH; + end if; + when s6 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= s6; + end if; + when s10 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= s10; + end if; + when s268 => + if (rdy_i = '1' and ( + (reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or + (reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or + (reg_F(1) = '1' and zw_REG_OP = X"D0") or (reg_F(7) = '1' and zw_REG_OP = X"10") or + (reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) then + csm_next_state <= FETCH; + elsif (rdy_i = '1') then + csm_next_state <= s305; + else + csm_next_state <= s268; + end if; + when s305 => + if (rdy_i = '1' and + addr_correction = X"00") then + csm_next_state <= FETCH; + elsif (rdy_i = '1') then + csm_next_state <= s306; + else + csm_next_state <= s305; + end if; + when s306 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= s306; + end if; + when jmp1 => + if (rdy_i = '1' and + zw_REG_OP = X"4C") then + csm_next_state <= jmp_ex; + elsif (rdy_i = '1' and + zw_REG_OP = X"6C") then + csm_next_state <= jmp2_1; + elsif (rdy_i = '1' and + zw_REG_OP = X"7C") then + csm_next_state <= jmp2_2; + else + csm_next_state <= jmp1; + end if; + when jmp2_1 => + if (rdy_i = '1') then + csm_next_state <= jmp3_1; + else + csm_next_state <= jmp2_1; + end if; + when jmp4_12 => + if (rdy_i = '1') then + csm_next_state <= jmp_ex; + else + csm_next_state <= jmp4_12; + end if; + when jmp_ex => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= jmp_ex; + end if; + when jmp2_2 => + if (rdy_i = '1') then + csm_next_state <= jmp3_2; + else + csm_next_state <= jmp2_2; + end if; + when jmp3_1 => + if (rdy_i = '1') then + csm_next_state <= jmp4_12; + else + csm_next_state <= jmp3_1; + end if; + when jsr1 => + if (rdy_i = '1') then + csm_next_state <= jsr2; + else + csm_next_state <= jsr1; + end if; + when jsr2 => + if (rdy_i = '1') then + csm_next_state <= jsr3; + else + csm_next_state <= jsr2; + end if; + when jsr3 => + if (rdy_i = '1') then + csm_next_state <= jsr4; + else + csm_next_state <= jsr3; + end if; + when jsr4 => + if (rdy_i = '1') then + csm_next_state <= jsr5; + else + csm_next_state <= jsr4; + end if; + when jsr5 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= jsr5; + end if; + when brk1 => + if (rdy_i = '1') then + csm_next_state <= brk2; + else + csm_next_state <= brk1; + end if; + when brk2 => + if (rdy_i = '1') then + csm_next_state <= brk3; + else + csm_next_state <= brk2; + end if; + when brk3 => + if (rdy_i = '1') then + csm_next_state <= brk4; + else + csm_next_state <= brk3; + end if; + when brk4 => + if (rdy_i = '1') then + csm_next_state <= brk5; + else + csm_next_state <= brk4; + end if; + when brk6 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= brk6; + end if; + when brk5 => + if (rdy_i = '1') then + csm_next_state <= brk6; + else + csm_next_state <= brk5; + end if; + when rti1 => + if (rdy_i = '1') then + csm_next_state <= rti2; + else + csm_next_state <= rti1; + end if; + when rti2 => + if (rdy_i = '1') then + csm_next_state <= rti3; + else + csm_next_state <= rti2; + end if; + when rti3 => + if (rdy_i = '1') then + csm_next_state <= rti4; + else + csm_next_state <= rti3; + end if; + when rti4 => + if (rdy_i = '1') then + csm_next_state <= rti5; + else + csm_next_state <= rti4; + end if; + when rti5 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= rti5; + end if; + when rts1 => + if (rdy_i = '1') then + csm_next_state <= rts2; + else + csm_next_state <= rts1; + end if; + when rts2 => + if (rdy_i = '1') then + csm_next_state <= rts3; + else + csm_next_state <= rts2; + end if; + when rts3 => + if (rdy_i = '1') then + csm_next_state <= rts4; + else + csm_next_state <= rts3; + end if; + when rts4 => + if (rdy_i = '1') then + csm_next_state <= rts5; + else + csm_next_state <= rts4; + end if; + when rts5 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= rts5; + end if; + when pha1 => + if (rdy_i = '1') then + csm_next_state <= pha2; + else + csm_next_state <= pha1; + end if; + when pha2 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= pha2; + end if; + when php1 => + if (rdy_i = '1') then + csm_next_state <= php2; + else + csm_next_state <= php1; + end if; + when php2 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= php2; + end if; + when pla1 => + if (rdy_i = '1') then + csm_next_state <= pla2; + else + csm_next_state <= pla1; + end if; + when pla2 => + if (rdy_i = '1') then + csm_next_state <= pla3; + else + csm_next_state <= pla2; + end if; + when pla3 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= pla3; + end if; + when plp1 => + if (rdy_i = '1') then + csm_next_state <= plp2; + else + csm_next_state <= plp1; + end if; + when plp2 => + if (rdy_i = '1') then + csm_next_state <= plp3; + else + csm_next_state <= plp2; + end if; + when plp3 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= plp3; + end if; + when irq1 => + if (rdy_i = '1') then + csm_next_state <= irq2; + else + csm_next_state <= irq1; + end if; + when irq2 => + if (rdy_i = '1') then + csm_next_state <= irq3; + else + csm_next_state <= irq2; + end if; + when irq3 => + if (rdy_i = '1') then + csm_next_state <= irq4; + else + csm_next_state <= irq3; + end if; + when irq5b => + if (rdy_i = '1') then + csm_next_state <= irq6b; + else + csm_next_state <= irq5b; + end if; + when irq5a => + if (rdy_i = '1') then + csm_next_state <= irq6a; + else + csm_next_state <= irq5a; + end if; + when irq4 => + if (rdy_i = '1' and + nmi_i = '1') then + csm_next_state <= irq5a; + elsif (rdy_i = '1') then + csm_next_state <= irq5b; + else + csm_next_state <= irq4; + end if; + when irq6a => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= irq6a; + end if; + when s11 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= s11; + end if; + when s12 => + if (rdy_i = '1') then + csm_next_state <= s20; + else + csm_next_state <= s12; + end if; + when s20 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= s20; + end if; + when s14 => + if (rdy_i = '1') then + csm_next_state <= s21; + else + csm_next_state <= s14; + end if; + when s21 => + if (rdy_i = '1') then + csm_next_state <= s23; + else + csm_next_state <= s21; + end if; + when s23 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= s23; + end if; + when s15 => + if (rdy_i = '1') then + csm_next_state <= s25; + else + csm_next_state <= s15; + end if; + when s25 => + if (rdy_i = '1') then + csm_next_state <= s28; + else + csm_next_state <= s25; + end if; + when s28 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= s28; + end if; + when s16 => + if (rdy_i = '1') then + csm_next_state <= s30; + else + csm_next_state <= s16; + end if; + when s30 => + if (rdy_i = '1') then + csm_next_state <= s31; + else + csm_next_state <= s30; + end if; + when s31 => + if (rdy_i = '1') then + csm_next_state <= s32; + else + csm_next_state <= s31; + end if; + when s32 => + if (rdy_i = '1') then + csm_next_state <= s34; + else + csm_next_state <= s32; + end if; + when s33 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= s33; + end if; + when s34 => + if (rdy_i = '1') then + csm_next_state <= s36; + else + csm_next_state <= s34; + end if; + when s36 => + if (rdy_i = '1') then + csm_next_state <= s33; + else + csm_next_state <= s36; + end if; + when jmp3_2 => + if (rdy_i = '1') then + csm_next_state <= jmp4_12; + else + csm_next_state <= jmp3_2; + end if; + when s270 => + if (rdy_i = '1') then + csm_next_state <= s271; + else + csm_next_state <= s270; + end if; + when s307 => + if (rdy_i = '1' and + addr_correction = X"00") then + csm_next_state <= FETCH; + elsif (rdy_i = '1') then + csm_next_state <= s309; + else + csm_next_state <= s307; + end if; + when s308 => + if (rdy_i = '1' and ( + (zw_b1(0) = '0' and zw_REG_OP = X"8F") or + (zw_b1(1) = '0' and zw_REG_OP = X"9F") or + (zw_b1(2) = '0' and zw_REG_OP = X"AF") or + (zw_b1(3) = '0' and zw_REG_OP = X"BF") or + (zw_b1(4) = '0' and zw_REG_OP = X"CF") or + (zw_b1(5) = '0' and zw_REG_OP = X"DF") or + (zw_b1(6) = '0' and zw_REG_OP = X"EF") or + (zw_b1(7) = '0' and zw_REG_OP = X"FF") or + (zw_b1(0) = '1' and zw_REG_OP = X"0F") or + (zw_b1(1) = '1' and zw_REG_OP = X"1F") or + (zw_b1(2) = '1' and zw_REG_OP = X"2F") or + (zw_b1(3) = '1' and zw_REG_OP = X"3F") or + (zw_b1(4) = '1' and zw_REG_OP = X"4F") or + (zw_b1(5) = '1' and zw_REG_OP = X"5F") or + (zw_b1(6) = '1' and zw_REG_OP = X"6F") or + (zw_b1(7) = '1' and zw_REG_OP = X"7F"))) then + csm_next_state <= FETCH; + elsif (rdy_i = '1') then + csm_next_state <= s307; + else + csm_next_state <= s308; + end if; + when s271 => + if (rdy_i = '1') then + csm_next_state <= s272; + else + csm_next_state <= s271; + end if; + when s272 => + if (rdy_i = '1') then + csm_next_state <= s308; + else + csm_next_state <= s272; + end if; + when s309 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= s309; + end if; + when RES0 => + csm_next_state <= res2; + when zp1 => + if (rdy_i = '1' and + (zw_REG_OP = X"85" OR + zw_REG_OP = X"86" OR + zw_REG_OP = X"64" OR + zw_REG_OP = X"84")) then + csm_next_state <= zp2w; + elsif (rdy_i = '1') then + csm_next_state <= zp2; + else + csm_next_state <= zp1; + end if; + when zp2 => + if (rdy_i = '1' and + reg_F(3) = '1' and + (zw_REG_OP = X"65" OR + zw_REG_OP = X"E5")) then + csm_next_state <= zp3; + elsif (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= zp2; + end if; + when zpx1 => + if (rdy_i = '1') then + csm_next_state <= zpx2; + else + csm_next_state <= zpx1; + end if; + when zpx2 => + if (rdy_i = '1' and + (zw_REG_OP = X"95" OR + zw_REG_OP = X"74" OR + zw_REG_OP = X"94")) then + csm_next_state <= zpx3w; + elsif (rdy_i = '1') then + csm_next_state <= zpx3; + else + csm_next_state <= zpx2; + end if; + when zpx3 => + if (rdy_i = '1' and + reg_F(3) = '1' and + (zw_REG_OP = X"75" OR + zw_REG_OP = X"F5")) then + csm_next_state <= zpx4; + elsif (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= zpx3; + end if; + when ab1 => + if (rdy_i = '1') then + csm_next_state <= ab2; + else + csm_next_state <= ab1; + end if; + when ab2 => + if (rdy_i = '1' and + (zw_REG_OP = X"8D" OR + zw_REG_OP = X"8E" OR + zw_REG_OP = X"9C" OR + zw_REG_OP = X"8C")) then + csm_next_state <= ab3w; + elsif (rdy_i = '1') then + csm_next_state <= ab3; + else + csm_next_state <= ab2; + end if; + when ab3 => + if (rdy_i = '1' and + reg_F(3) = '1' and + (zw_REG_OP = X"6D" OR + zw_REG_OP = X"ED")) then + csm_next_state <= ab4; + elsif (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= ab3; + end if; + when absx1 => + if (rdy_i = '1') then + csm_next_state <= absx2; + else + csm_next_state <= absx1; + end if; + when absx2 => + if (rdy_i = '1' and + (zw_REG_OP = X"9D" OR + zw_REG_OP = X"9E")) then + csm_next_state <= absx3w; + elsif (rdy_i = '1') then + csm_next_state <= absx3; + else + csm_next_state <= absx2; + end if; + when absx4 => + if ((rdy_i = '1') and ((zw_REG_OP = X"7D" or + zw_REG_OP = X"FD") and + reg_F(3) = '1')) then + csm_next_state <= absx5; + elsif (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= absx4; + end if; + when absx3 => + if ((rdy_i = '1' AND + zw_reg_0flag = '0') and ((zw_REG_OP = X"7D" or + zw_REG_OP = X"FD") and + reg_F(3) = '1')) then + csm_next_state <= absx5; + elsif (rdy_i = '1' AND + zw_reg_0flag = '0') then + csm_next_state <= FETCH; + elsif (rdy_i = '1') then + csm_next_state <= absx4; + else + csm_next_state <= absx3; + end if; + when ind1 => + if (rdy_i = '1') then + csm_next_state <= ind2; + else + csm_next_state <= ind1; + end if; + when ind3 => + if (rdy_i = '1' and + zw_REG_OP = X"92") then + csm_next_state <= ind4w; + elsif (rdy_i = '1') then + csm_next_state <= ind4; + else + csm_next_state <= ind3; + end if; + when ind4 => + if (rdy_i = '1' and + reg_F(3) = '1' and + (zw_REG_OP = X"72" OR + zw_REG_OP = X"F2")) then + csm_next_state <= ind5; + elsif (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= ind4; + end if; + when ind2 => + if (rdy_i = '1') then + csm_next_state <= ind3; + else + csm_next_state <= ind2; + end if; + when indy1 => + if (rdy_i = '1') then + csm_next_state <= indy2; + else + csm_next_state <= indy1; + end if; + when indy2 => + if (rdy_i = '1') then + csm_next_state <= indy3; + else + csm_next_state <= indy2; + end if; + when indy3 => + if (rdy_i = '1' and + zw_REG_OP = X"91") then + csm_next_state <= indy4w; + elsif (rdy_i = '1') then + csm_next_state <= indy4; + else + csm_next_state <= indy3; + end if; + when indy5 => + if ((rdy_i = '1') and ((zw_REG_OP = X"71" or + zw_REG_OP = X"F1") and + reg_F(3) = '1')) then + csm_next_state <= indy6; + elsif (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= indy5; + end if; + when indy4 => + if ((rdy_i = '1' AND + zw_reg_0flag = '0') and ((zw_REG_OP = X"71" or + zw_REG_OP = X"F1") and + reg_F(3) = '1')) then + csm_next_state <= indy6; + elsif (rdy_i = '1' AND + zw_reg_0flag = '0') then + csm_next_state <= FETCH; + elsif (rdy_i = '1') then + csm_next_state <= indy5; + else + csm_next_state <= indy4; + end if; + when indx1 => + if (rdy_i = '1') then + csm_next_state <= indx2; + else + csm_next_state <= indx1; + end if; + when indx4 => + if (rdy_i = '1' and + zw_REG_OP = X"81") then + csm_next_state <= indx5w; + elsif (rdy_i = '1') then + csm_next_state <= indx5; + else + csm_next_state <= indx4; + end if; + when indx2 => + if (rdy_i = '1') then + csm_next_state <= indx3; + else + csm_next_state <= indx2; + end if; + when indx3 => + if (rdy_i = '1') then + csm_next_state <= indx4; + else + csm_next_state <= indx3; + end if; + when indx5 => + if (rdy_i = '1' and + reg_F(3) = '1' and + (zw_REG_OP = X"61" OR + zw_REG_OP = X"E1")) then + csm_next_state <= indx6; + elsif (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= indx5; + end if; + when zpy1 => + if (rdy_i = '1') then + csm_next_state <= zpy2; + else + csm_next_state <= zpy1; + end if; + when zpy2 => + if (rdy_i = '1' and + zw_REG_OP = X"96") then + csm_next_state <= zpy3w; + elsif (rdy_i = '1') then + csm_next_state <= zpy3; + else + csm_next_state <= zpy2; + end if; + when zpy3 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= zpy3; + end if; + when absy2 => + if (rdy_i = '1' and + zw_REG_OP = X"99") then + csm_next_state <= absy3w; + elsif (rdy_i = '1') then + csm_next_state <= absy3; + else + csm_next_state <= absy2; + end if; + when absy1 => + if (rdy_i = '1') then + csm_next_state <= absy2; + else + csm_next_state <= absy1; + end if; + when absy4 => + if ((rdy_i = '1') and ((zw_REG_OP = X"79" or + zw_REG_OP = X"F9") and + reg_F(3) = '1')) then + csm_next_state <= absy5; + elsif (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= absy4; + end if; + when absy3 => + if ((rdy_i = '1' AND + zw_reg_0flag = '0') and ((zw_REG_OP = X"79" or + zw_REG_OP = X"F9") and + reg_F(3) = '1')) then + csm_next_state <= absy5; + elsif (rdy_i = '1' AND + zw_reg_0flag = '0') then + csm_next_state <= FETCH; + elsif (rdy_i = '1') then + csm_next_state <= absy4; + else + csm_next_state <= absy3; + end if; + when imm1 => + if (rdy_i = '1' and + reg_F(3) = '1' and + (zw_REG_OP = X"69" OR + zw_REG_OP = X"E9")) then + csm_next_state <= imm2; + elsif (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= imm1; + end if; + when imp1 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= imp1; + end if; + when irq6b => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= irq6b; + end if; + when absx5 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= absx5; + end if; + when absy5 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= absy5; + end if; + when indy6 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= indy6; + end if; + when s237 => + if (rdy_i = '1') then + csm_next_state <= s348; + else + csm_next_state <= s237; + end if; + when s348 => + if (rdy_i = '1' and + (zw_REG_OP = X"C6" or + zw_REG_OP = X"E6")) then + csm_next_state <= s254; + elsif (rdy_i = '1') then + csm_next_state <= s256; + else + csm_next_state <= s348; + end if; + when s254 => + if (rdy_i = '1') then + csm_next_state <= s255; + else + csm_next_state <= s254; + end if; + when s255 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= s255; + end if; + when s238 => + if (rdy_i = '1') then + csm_next_state <= s257; + else + csm_next_state <= s238; + end if; + when s257 => + if (rdy_i = '1') then + csm_next_state <= s350; + else + csm_next_state <= s257; + end if; + when s350 => + if (rdy_i = '1' and + (zw_REG_OP = X"D6" or + zw_REG_OP = X"F6")) then + csm_next_state <= s258; + elsif (rdy_i = '1') then + csm_next_state <= s261; + else + csm_next_state <= s350; + end if; + when s258 => + if (rdy_i = '1') then + csm_next_state <= s259; + else + csm_next_state <= s258; + end if; + when s259 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= s259; + end if; + when s239 => + if (rdy_i = '1') then + csm_next_state <= s260; + else + csm_next_state <= s239; + end if; + when s260 => + if (rdy_i = '1') then + csm_next_state <= s352; + else + csm_next_state <= s260; + end if; + when s352 => + if (rdy_i = '1' and + (zw_REG_OP = X"CE" or + zw_REG_OP = X"EE")) then + csm_next_state <= s263; + elsif (rdy_i = '1') then + csm_next_state <= s265; + else + csm_next_state <= s352; + end if; + when s263 => + if (rdy_i = '1') then + csm_next_state <= s264; + else + csm_next_state <= s263; + end if; + when s264 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= s264; + end if; + when s240 => + if (rdy_i = '1') then + csm_next_state <= s266; + else + csm_next_state <= s240; + end if; + when s266 => + if (rdy_i = '1') then + csm_next_state <= s353; + else + csm_next_state <= s266; + end if; + when s353 => + if (rdy_i = '1' AND + zw_reg_0flag = '0' and + (zw_REG_OP = X"DE" or + zw_REG_OP = X"FE")) then + csm_next_state <= s269; + elsif (rdy_i = '1' and + (zw_REG_OP = X"DE" or + zw_REG_OP = X"FE")) then + csm_next_state <= s354; + elsif (rdy_i = '1' AND + zw_reg_0flag = '0') then + csm_next_state <= s274; + elsif (rdy_i = '1') then + csm_next_state <= s355; + else + csm_next_state <= s353; + end if; + when s354 => + if (rdy_i = '1') then + csm_next_state <= s269; + else + csm_next_state <= s354; + end if; + when s269 => + if (rdy_i = '1') then + csm_next_state <= s273; + else + csm_next_state <= s269; + end if; + when s273 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= s273; + end if; + when zp2w => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= zp2w; + end if; + when zpx3w => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= zpx3w; + end if; + when zpy3w => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= zpy3w; + end if; + when ab3w => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= ab3w; + end if; + when absx4w => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= absx4w; + end if; + when absx3w => + if (rdy_i = '1' AND + zw_reg_0flag = '0') then + csm_next_state <= FETCH; + elsif (rdy_i = '1') then + csm_next_state <= absx4w; + else + csm_next_state <= absx3w; + end if; + when absy4w => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= absy4w; + end if; + when absy3w => + if (rdy_i = '1' AND + zw_reg_0flag = '0') then + csm_next_state <= FETCH; + elsif (rdy_i = '1') then + csm_next_state <= absy4w; + else + csm_next_state <= absy3w; + end if; + when ind4w => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= ind4w; + end if; + when indx5w => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= indx5w; + end if; + when indy5w => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= indy5w; + end if; + when indy4w => + if (rdy_i = '1' AND + zw_reg_0flag = '0') then + csm_next_state <= FETCH; + elsif (rdy_i = '1') then + csm_next_state <= indy5w; + else + csm_next_state <= indy4w; + end if; + when s256 => + if (rdy_i = '1') then + csm_next_state <= s255; + else + csm_next_state <= s256; + end if; + when s261 => + if (rdy_i = '1') then + csm_next_state <= s259; + else + csm_next_state <= s261; + end if; + when s265 => + if (rdy_i = '1') then + csm_next_state <= s264; + else + csm_next_state <= s265; + end if; + when s274 => + if (rdy_i = '1') then + csm_next_state <= s273; + else + csm_next_state <= s274; + end if; + when s355 => + if (rdy_i = '1') then + csm_next_state <= s274; + else + csm_next_state <= s355; + end if; + when zp3 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= zp3; + end if; + when zpx4 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= zpx4; + end if; + when ab4 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= ab4; + end if; + when ind5 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= ind5; + end if; + when indx6 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= indx6; + end if; + when imm2 => + if (rdy_i = '1') then + csm_next_state <= FETCH; + else + csm_next_state <= imm2; + end if; + when others => + csm_next_state <= RES; + end case; + end process csm_nextstate_proc; + + ----------------------------------------------------------------- + csm_output_proc : process ( + addr_correction, + adr_nxt_pc_i, + adr_pc_i, + adr_sp_i, + csm_current_state, + d_i, + d_regs_out_i, + irq_n_i, + nmi_i, + q_x_i, + q_y_i, + rdy_i, + reg_F, + sel_pc_in, + sel_pc_val, + sel_sp_as, + sel_sp_in, + sig_D_OUT, + sig_PC, + sig_RD, + sig_RWn, + sig_WR, + zw_REG_OP, + zw_b1, + zw_b11, + zw_b12, + zw_b2, + zw_b3, + zw_b4, + zw_b5, + zw_b6, + zw_reg_0flag, + zw_w3 + ) + ----------------------------------------------------------------- + begin + -- Default Assignment + a_o <= sig_PC; + adr_o <= X"0000"; + ch_a_o <= X"00"; + ch_b_o <= X"00"; + d_o <= sig_D_OUT; + ld_o <= "00"; + ld_pc_o <= '0'; + ld_sp_o <= '0'; + offset_o <= X"0000"; + rd_o <= sig_RD; + rst_nmi_o <= '0'; + sel_pc_in_o <= sel_pc_in; + sel_pc_val_o <= sel_pc_val; + sel_sp_as_o <= sel_sp_as; + sel_sp_in_o <= sel_sp_in; + wr_n_o <= sig_RWn; + wr_o <= sig_WR; + -- Default Assignment To Internals + adc_sbc_finished <= '0'; + addr_correction <= X"00"; + irq_finished <= '0'; + op_fetch <= '0'; + op_finished <= '0'; + rmb_started <= '0'; + rst_finished <= '0'; + sel_pc_in <= '0'; + sel_pc_val <= "00"; + sel_sp_as <= '1'; + sel_sp_in <= '0'; + sig_D_OUT <= X"00"; + sig_PC <= X"0000"; + sig_RD <= '1'; + sig_RWn <= '1'; + sig_SYNC <= '0'; + sig_WR <= '0'; + + -- Combined Actions + case csm_current_state is + when res2 => + sig_PC <= adr_pc_i; + sel_sp_in <= '0'; + sel_sp_as <= '0'; + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when res4 => + sig_PC <= adr_sp_i; + adr_o <= X"FFFB"; + sel_pc_in <= '1'; + sel_pc_val <= "00"; + ld_pc_o <= '1'; + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when res5 => + sig_PC <= adr_sp_i; + when res6 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when res7 => + sig_PC <= adr_pc_i; + adr_o <= d_i & zw_b5; + sel_pc_in <= '1'; + sel_pc_val <= "11"; + ld_pc_o <= '1'; + rst_finished <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + sig_SYNC <= '1'; + end if; + when res3 => + sig_PC <= adr_sp_i; + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when RES => + sig_PC <= adr_pc_i; + sig_SYNC <= '1'; + when FETCH => + sig_PC <= adr_pc_i; + op_fetch <= '1'; + sig_RWn <= '1'; + sig_RD <= '1'; + sig_SYNC <= NOT (rdy_i); + ld_pc_o <= '1'; + if ((d_i = X"00") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((nmi_i = '1') and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((irq_n_i = '0' and + reg_F(2) = '0') and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"8F" or + d_i = X"9F" or + d_i = X"AF" or + d_i = X"BF" or + d_i = X"CF" or + d_i = X"DF" or + d_i = X"EF" or + d_i = X"FF" or + d_i = X"0F" or + d_i = X"1F" or + d_i = X"2F" or + d_i = X"3F" or + d_i = X"4F" or + d_i = X"5F" or + d_i = X"6F" or + d_i = X"7F") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"90" or + d_i = X"B0" or + d_i = X"F0" or + d_i = X"30" or + d_i = X"D0" or + d_i = X"10" or + d_i = X"50" or + d_i = X"70" or + d_i = X"80") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"4C" or + d_i = X"6C" or + d_i = X"7C") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"20") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"68") and (rdy_i = '1')) then + elsif ((d_i = X"FA") and (rdy_i = '1')) then + elsif ((d_i = X"C6" or + d_i = X"E6" or + d_i = X"66" or + d_i = X"06" or + d_i = X"46" or + d_i = X"26" or + d_i (3 downto 0) = X"7" or + d_i = X"14" or + d_i = X"04") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"D6" or + d_i = X"F6" or + d_i = X"76" or + d_i = X"16" or + d_i = X"56" or + d_i = X"36") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"CE" or + d_i = X"EE" or + d_i = X"6E" or + d_i = X"0E" or + d_i = X"4E" or + d_i = X"2E" or + d_i = X"1C" or + d_i = X"0C") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"DE" or + d_i = X"FE" or + d_i = X"7E" or + d_i = X"1E" or + d_i = X"5E" or + d_i = X"3E") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"09" or + d_i = X"29" or + d_i = X"49" or + d_i = X"69" or + d_i = X"89" or + d_i = X"A0" or + d_i = X"A2" or + d_i = X"A9" or + d_i = X"C9" or + d_i = X"E0" or + d_i = X"C0" or + d_i = X"E9") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"05" or + d_i = X"25" or + d_i = X"45" or + d_i = X"65" or + d_i = X"A5" or + d_i = X"24" or + d_i = X"C5" or + d_i = X"E4" or + d_i = X"C4" or + d_i = X"A6" or + d_i = X"A4" or + d_i = X"E5" or + d_i = X"85" or + d_i = X"86" or + d_i = X"84" or + d_i = X"64") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"15" or + d_i = X"35" or + d_i = X"55" or + d_i = X"75" or + d_i = X"B5" or + d_i = X"34" or + d_i = X"D5" or + d_i = X"B4" or + d_i = X"F5" or + d_i = X"95" or + d_i = X"94" or + d_i = X"74") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"B6" or + d_i = X"96") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"6D" or + d_i = X"2D" or + d_i = X"2C" or + d_i = X"CD" or + d_i = X"CC" or + d_i = X"EC" or + d_i = X"4D" or + d_i = X"AD" or + d_i = X"AE" or + d_i = X"AC" or + d_i = X"0D" or + d_i = X"ED" or + d_i = X"8D" or + d_i = X"8E" or + d_i = X"8C" or + d_i = X"9C") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"7D" or + d_i = X"3D" or + d_i = X"3C" or + d_i = X"DD" or + d_i = X"5D" or + d_i = X"BD" or + d_i = X"BC" or + d_i = X"1D" or + d_i = X"FD" or + d_i = X"9D" or + d_i = X"9E") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"79" or + d_i = X"39" or + d_i = X"D9" or + d_i = X"5D" or + d_i = X"59" or + d_i = X"B9" or + d_i = X"BE" or + d_i = X"19" or + d_i = X"F9" or + d_i = X"99") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"72" or + d_i = X"32" or + d_i = X"D2" or + d_i = X"59" or + d_i = X"52" or + d_i = X"B2" or + d_i = X"12" or + d_i = X"F2" or + d_i = X"92") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"71" or + d_i = X"31" or + d_i = X"D1" or + d_i = X"51" or + d_i = X"B1" or + d_i = X"11" or + d_i = X"F1" or + d_i = X"91") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"61" or + d_i = X"21" or + d_i = X"C1" or + d_i = X"41" or + d_i = X"A1" or + d_i = X"01" or + d_i = X"E1" or + d_i = X"81") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"B8" or + d_i = X"38" or + d_i = X"18" or + d_i = X"F8" or + d_i = X"D8" or + d_i = X"78" or + d_i = X"58" or + d_i = X"0A" or + d_i = X"4A" or + d_i = X"2A" or + d_i = X"6A" or + d_i = X"A8" or + d_i = X"98" or + d_i = X"BA" or + d_i = X"8A" or + d_i = X"AA" or + d_i = X"C8" or + d_i = X"E8" or + d_i = X"1A" or + d_i = X"88" or + d_i = X"CA" or + d_i = X"3A") and (rdy_i = '1')) then + elsif ((d_i = X"7A") and (rdy_i = '1')) then + elsif ((d_i = X"28") and (rdy_i = '1')) then + elsif ((d_i = X"9A") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"60") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"40") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"08") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"5A") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"DA") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"48") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"EA") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i(3 downto 0) = X"3" or + d_i(3 downto 0) = X"B") and (rdy_i = '1')) then + ld_o <= "11"; + sig_SYNC <= '1'; + elsif ((d_i = X"02" or + d_i = X"22" or + d_i = X"42" or + d_i = X"62" or + d_i = X"82" or + d_i = X"C2" or + d_i = X"E2") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"44") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"54" or + d_i = X"D4" or + d_i = X"F4") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"DC" or + d_i = X"FC") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"5C") and (rdy_i = '1')) then + ld_o <= "11"; + end if; + when s6 => + sig_PC <= adr_pc_i; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s10 => + sig_PC <= adr_pc_i; + sel_sp_in <= '1'; + sel_sp_as <= '0'; + ld_sp_o <= '1'; + if (rdy_i = '1') then + adr_o <= X"01" & q_x_i; + ld_o <= "11"; + sig_SYNC <= '1'; + end if; + when s268 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + if (rdy_i = '1' and ( + (reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or + (reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or + (reg_F(1) = '1' and zw_REG_OP = X"D0") or (reg_F(7) = '1' and zw_REG_OP = X"10") or + (reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) then + ld_o <= "11"; + sig_SYNC <= '1'; + elsif (rdy_i = '1') then + ld_o <= "11"; + end if; + when s305 => + sig_PC <= adr_pc_i; + addr_correction <= zw_b3 XOR adr_nxt_pc_i (15 downto 8); + sel_pc_in <= '0'; + sel_pc_val <= "10"; + offset_o <= (zw_b2(7) & zw_b2(7) & + zw_b2(7) & zw_b2(7) & zw_b2(7) & + zw_b2(7) & zw_b2(7) & zw_b2(7) & + zw_b2(7) & zw_b2(6 downto 0)); + ld_pc_o <= '1'; + if (rdy_i = '1' and + addr_correction = X"00") then + ld_o <= "11"; + sig_SYNC <= '1'; + elsif (rdy_i = '1') then + ld_o <= "11"; + end if; + when s306 => + sig_PC <= zw_b3 & adr_pc_i (7 downto 0); + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when jmp1 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + if (rdy_i = '1' and + zw_REG_OP = X"4C") then + ld_o <= "11"; + elsif (rdy_i = '1' and + zw_REG_OP = X"6C") then + ld_o <= "11"; + elsif (rdy_i = '1' and + zw_REG_OP = X"7C") then + ld_o <= "11"; + end if; + when jmp2_1 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when jmp4_12 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when jmp_ex => + sig_PC <= adr_pc_i; + adr_o <= d_i & zw_b5; + sel_pc_in <= '1'; + sel_pc_val <= "11"; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + sig_SYNC <= '1'; + end if; + when jmp2_2 => + sig_PC <= adr_pc_i; + when jmp3_1 => + sig_PC <= zw_b6 & zw_b5; + adr_o <= zw_b6 & zw_b5; + sel_pc_in <= '1'; + sel_pc_val <= "11"; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when jsr1 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when jsr2 => + sig_PC <= adr_sp_i; + when jsr3 => + sig_PC <= adr_sp_i; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= zw_b11; + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when jsr4 => + sig_PC <= adr_sp_i; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= zw_b12; + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when jsr5 => + sig_PC <= adr_pc_i; + adr_o <= d_i & zw_b1; + sel_pc_in <= '1'; + sel_pc_val <= "11"; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + sig_SYNC <= '1'; + end if; + when brk1 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when brk2 => + sig_PC <= adr_sp_i; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= zw_b11; + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when brk3 => + sig_PC <= adr_sp_i; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= zw_b12; + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when brk4 => + sig_PC <= adr_sp_i; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= zw_b11; + ld_sp_o <= '1'; + irq_finished <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when brk6 => + sig_PC <= X"FFFF"; + adr_o <= d_i & zw_b5; + sel_pc_in <= '1'; + sel_pc_val <= "11"; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + sig_SYNC <= '1'; + end if; + when brk5 => + sig_PC <= X"FFFE"; + when rti1 => + sig_PC <= adr_pc_i; + when rti2 => + sig_PC <= adr_sp_i; + sel_sp_in <= '0'; + sel_sp_as <= '0'; + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when rti3 => + sig_PC <= adr_sp_i; + sel_sp_in <= '0'; + sel_sp_as <= '0'; + ld_sp_o <= '1'; + op_finished <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when rti4 => + sig_PC <= adr_sp_i; + sel_sp_in <= '0'; + sel_sp_as <= '0'; + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when rti5 => + sig_PC <= adr_sp_i; + adr_o <= d_i & zw_b5; + sel_pc_in <= '1'; + sel_pc_val <= "11"; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + sig_SYNC <= '1'; + end if; + when rts1 => + sig_PC <= adr_pc_i; + when rts2 => + sig_PC <= adr_sp_i; + sel_sp_in <= '0'; + sel_sp_as <= '0'; + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when rts3 => + sig_PC <= adr_sp_i; + sel_sp_in <= '0'; + sel_sp_as <= '0'; + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when rts4 => + sig_PC <= adr_sp_i; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when rts5 => + sig_PC <= zw_b6 & zw_b5; + adr_o <= zw_b6 & zw_b5; + sel_pc_in <= '1'; + sel_pc_val <= "00"; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + sig_SYNC <= '1'; + end if; + when pha1 => + sig_PC <= adr_pc_i; + when pha2 => + sig_PC <= adr_sp_i; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= d_regs_out_i; + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + sig_SYNC <= '1'; + end if; + when php1 => + sig_PC <= adr_pc_i; + when php2 => + sig_PC <= adr_sp_i; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= reg_F OR X"30"; + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + sig_SYNC <= '1'; + end if; + when pla1 => + sig_PC <= adr_pc_i; + when pla2 => + sig_PC <= adr_pc_i; + sel_sp_in <= '0'; + sel_sp_as <= '0'; + ld_pc_o <= '1'; + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when pla3 => + sig_PC <= adr_sp_i; + op_finished <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when plp1 => + sig_PC <= adr_pc_i; + when plp2 => + sig_PC <= adr_pc_i; + sel_sp_in <= '0'; + sel_sp_as <= '0'; + ld_pc_o <= '1'; + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when plp3 => + sig_PC <= adr_sp_i; + op_finished <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when irq1 => + sig_PC <= adr_pc_i; + when irq2 => + sig_PC <= adr_sp_i; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= zw_b11; + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when irq3 => + sig_PC <= adr_sp_i; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= zw_b12; + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when irq5b => + sig_PC <= X"FFFE"; + when irq5a => + sig_PC <= X"FFFA"; + when irq4 => + sig_PC <= adr_sp_i; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= zw_b11; + ld_sp_o <= '1'; + irq_finished <= '1'; + if (rdy_i = '1' and + nmi_i = '1') then + ld_o <= "11"; + elsif (rdy_i = '1') then + ld_o <= "11"; + end if; + when irq6a => + sig_PC <= X"FFFB"; + adr_o <= d_i & zw_b5; + rst_nmi_o <= '1'; + sel_pc_in <= '1'; + sel_pc_val <= "11"; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + sig_SYNC <= '1'; + end if; + when s11 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + sig_SYNC <= '1'; + end if; + when s12 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s20 => + sig_PC <= adr_pc_i; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s14 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s21 => + sig_PC <= adr_pc_i; + when s23 => + sig_PC <= adr_pc_i; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s15 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s25 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s28 => + sig_PC <= adr_pc_i; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s16 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s30 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s31 => + sig_PC <= adr_pc_i; + when s32 => + sig_PC <= adr_pc_i; + when s33 => + sig_PC <= adr_pc_i; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s34 => + sig_PC <= adr_pc_i; + when s36 => + sig_PC <= adr_pc_i; + when jmp3_2 => + sig_PC <= zw_b6 & zw_b5; + adr_o <= zw_b6 & zw_b5; + offset_o <= (X"00" & q_x_i); + sel_pc_in <= '1'; + sel_pc_val <= "10"; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s270 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s307 => + sig_PC <= zw_w3; + addr_correction <= zw_b3 XOR adr_nxt_pc_i (15 downto 8); + sel_pc_in <= '0'; + sel_pc_val <= "10"; + offset_o <= (zw_b2(7) & zw_b2(7) & + zw_b2(7) & zw_b2(7) & zw_b2(7) & + zw_b2(7) & zw_b2(7) & zw_b2(7) & + zw_b2(7) & zw_b2(6 downto 0)); + ld_pc_o <= '1'; + if (rdy_i = '1' and + addr_correction = X"00") then + ld_o <= "11"; + sig_SYNC <= '1'; + elsif (rdy_i = '1') then + ld_o <= "11"; + end if; + when s308 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + if (rdy_i = '1' and ( + (zw_b1(0) = '0' and zw_REG_OP = X"8F") or + (zw_b1(1) = '0' and zw_REG_OP = X"9F") or + (zw_b1(2) = '0' and zw_REG_OP = X"AF") or + (zw_b1(3) = '0' and zw_REG_OP = X"BF") or + (zw_b1(4) = '0' and zw_REG_OP = X"CF") or + (zw_b1(5) = '0' and zw_REG_OP = X"DF") or + (zw_b1(6) = '0' and zw_REG_OP = X"EF") or + (zw_b1(7) = '0' and zw_REG_OP = X"FF") or + (zw_b1(0) = '1' and zw_REG_OP = X"0F") or + (zw_b1(1) = '1' and zw_REG_OP = X"1F") or + (zw_b1(2) = '1' and zw_REG_OP = X"2F") or + (zw_b1(3) = '1' and zw_REG_OP = X"3F") or + (zw_b1(4) = '1' and zw_REG_OP = X"4F") or + (zw_b1(5) = '1' and zw_REG_OP = X"5F") or + (zw_b1(6) = '1' and zw_REG_OP = X"6F") or + (zw_b1(7) = '1' and zw_REG_OP = X"7F"))) then + ld_o <= "11"; + sig_SYNC <= '1'; + elsif (rdy_i = '1') then + ld_o <= "11"; + end if; + when s271 => + sig_PC <= X"00" & zw_b2; + when s272 => + sig_PC <= X"00" & zw_b2; + when s309 => + sig_PC <= zw_b3 & adr_pc_i(7 downto 0); + offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & + zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & + zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0)); + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when RES0 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + ld_o <= "11"; + when zp1 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + if (rdy_i = '1' and + (zw_REG_OP = X"85" OR + zw_REG_OP = X"86" OR + zw_REG_OP = X"64" OR + zw_REG_OP = X"84")) then + ld_o <= "11"; + elsif (rdy_i = '1') then + ld_o <= "11"; + end if; + when zp2 => + sig_PC <= X"00" & zw_b5; + op_finished <= '1'; + if (rdy_i = '1' and + reg_F(3) = '1' and + (zw_REG_OP = X"65" OR + zw_REG_OP = X"E5")) then + elsif (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when zpx1 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + when zpx2 => + sig_PC <= X"00" & zw_b5; + ch_a_o <= zw_b5; + ch_b_o <= q_x_i; + ld_pc_o <= '1'; + if (rdy_i = '1' and + (zw_REG_OP = X"95" OR + zw_REG_OP = X"74" OR + zw_REG_OP = X"94")) then + ld_o <= "11"; + elsif (rdy_i = '1') then + ld_o <= "11"; + end if; + when zpx3 => + sig_PC <= X"00" & zw_b1; + op_finished <= '1'; + if (rdy_i = '1' and + reg_F(3) = '1' and + (zw_REG_OP = X"75" OR + zw_REG_OP = X"F5")) then + elsif (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when ab1 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when ab2 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + if (rdy_i = '1' and + (zw_REG_OP = X"8D" OR + zw_REG_OP = X"8E" OR + zw_REG_OP = X"9C" OR + zw_REG_OP = X"8C")) then + ld_o <= "11"; + elsif (rdy_i = '1') then + ld_o <= "11"; + end if; + when ab3 => + sig_PC <= zw_b6 & zw_b5; + op_finished <= '1'; + if (rdy_i = '1' and + reg_F(3) = '1' and + (zw_REG_OP = X"6D" OR + zw_REG_OP = X"ED")) then + elsif (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when absx1 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when absx2 => + sig_PC <= adr_pc_i; + ch_a_o <= zw_b5; + ch_b_o <= q_x_i; + ld_pc_o <= '1'; + if (rdy_i = '1' and + (zw_REG_OP = X"9D" OR + zw_REG_OP = X"9E")) then + ld_o <= "11"; + elsif (rdy_i = '1') then + ld_o <= "11"; + end if; + when absx4 => + sig_PC <= zw_b3 & zw_b1; + op_finished <= '1'; + adc_sbc_finished <= reg_F(3); + if ((rdy_i = '1') and ((zw_REG_OP = X"7D" or + zw_REG_OP = X"FD") and + reg_F(3) = '1')) then + elsif (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when absx3 => + sig_PC <= zw_b6 & zw_b1; + ch_a_o <= zw_b6; + ch_b_o <= "0000000" & zw_reg_0flag; + op_finished <= NOT(zw_reg_0flag); + if ((rdy_i = '1' AND + zw_reg_0flag = '0') and ((zw_REG_OP = X"7D" or + zw_REG_OP = X"FD") and + reg_F(3) = '1')) then + elsif (rdy_i = '1' AND + zw_reg_0flag = '0') then + sig_SYNC <= '1'; + end if; + when ind1 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + when ind3 => + sig_PC <= X"00" & zw_b1; + ld_pc_o <= '1'; + if (rdy_i = '1' and + zw_REG_OP = X"92") then + ld_o <= "11"; + elsif (rdy_i = '1') then + ld_o <= "11"; + end if; + when ind4 => + sig_PC <= zw_b5 & zw_b6; + op_finished <= '1'; + if (rdy_i = '1' and + reg_F(3) = '1' and + (zw_REG_OP = X"72" OR + zw_REG_OP = X"F2")) then + elsif (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when ind2 => + sig_PC <= X"00" & zw_b5; + ch_a_o <= zw_b5; + ch_b_o <= X"01"; + when indy1 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + when indy2 => + sig_PC <= X"00" & zw_b5; + ch_a_o <= zw_b5; + ch_b_o <= X"01"; + when indy3 => + sig_PC <= X"00" & zw_b1; + ch_a_o <= zw_b2; + ch_b_o <= q_y_i; + ld_pc_o <= '1'; + if (rdy_i = '1' and + zw_REG_OP = X"91") then + ld_o <= "11"; + elsif (rdy_i = '1') then + ld_o <= "11"; + end if; + when indy5 => + sig_PC <= zw_b3 & zw_b6; + op_finished <= '1'; + adc_sbc_finished <= reg_F(3); + if ((rdy_i = '1') and ((zw_REG_OP = X"71" or + zw_REG_OP = X"F1") and + reg_F(3) = '1')) then + elsif (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when indy4 => + sig_PC <= zw_b5 & zw_b6; + ch_a_o <= zw_b5; + ch_b_o <= "0000000" & zw_reg_0flag; + op_finished <= NOT(zw_reg_0flag); + if ((rdy_i = '1' AND + zw_reg_0flag = '0') and ((zw_REG_OP = X"71" or + zw_REG_OP = X"F1") and + reg_F(3) = '1')) then + elsif (rdy_i = '1' AND + zw_reg_0flag = '0') then + sig_SYNC <= '1'; + end if; + when indx1 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + when indx4 => + sig_PC <= X"00" & zw_b6; + ld_pc_o <= '1'; + if (rdy_i = '1' and + zw_REG_OP = X"81") then + ld_o <= "11"; + elsif (rdy_i = '1') then + ld_o <= "11"; + end if; + when indx2 => + sig_PC <= X"00" & zw_b5; + ch_a_o <= zw_b5; + ch_b_o <= q_x_i; + when indx3 => + sig_PC <= X"00" & zw_b1; + ch_a_o <= zw_b1; + ch_b_o <= X"01"; + when indx5 => + sig_PC <= zw_b2 & zw_b5; + op_finished <= '1'; + if (rdy_i = '1' and + reg_F(3) = '1' and + (zw_REG_OP = X"61" OR + zw_REG_OP = X"E1")) then + elsif (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when zpy1 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + when zpy2 => + sig_PC <= X"00" & zw_b5; + ch_a_o <= zw_b5; + ch_b_o <= q_y_i; + ld_pc_o <= '1'; + if (rdy_i = '1' and + zw_REG_OP = X"96") then + ld_o <= "11"; + elsif (rdy_i = '1') then + ld_o <= "11"; + end if; + when zpy3 => + sig_PC <= X"00" & zw_b1; + op_finished <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when absy2 => + sig_PC <= adr_pc_i; + ch_a_o <= zw_b5; + ch_b_o <= q_y_i; + ld_pc_o <= '1'; + if (rdy_i = '1' and + zw_REG_OP = X"99") then + ld_o <= "11"; + elsif (rdy_i = '1') then + ld_o <= "11"; + end if; + when absy1 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when absy4 => + sig_PC <= zw_b3 & zw_b1; + op_finished <= '1'; + adc_sbc_finished <= reg_F(3); + if ((rdy_i = '1') and ((zw_REG_OP = X"79" or + zw_REG_OP = X"F9") and + reg_F(3) = '1')) then + elsif (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when absy3 => + sig_PC <= zw_b6 & zw_b1; + ch_a_o <= zw_b6; + ch_b_o <= "0000000" & zw_reg_0flag; + op_finished <= NOT(zw_reg_0flag); + if ((rdy_i = '1' AND + zw_reg_0flag = '0') and ((zw_REG_OP = X"79" or + zw_REG_OP = X"F9") and + reg_F(3) = '1')) then + elsif (rdy_i = '1' AND + zw_reg_0flag = '0') then + sig_SYNC <= '1'; + end if; + when imm1 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + op_finished <= '1'; + if (rdy_i = '1' and + reg_F(3) = '1' and + (zw_REG_OP = X"69" OR + zw_REG_OP = X"E9")) then + elsif (rdy_i = '1') then + ld_o <= "11"; + sig_SYNC <= '1'; + end if; + when imp1 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + op_finished <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + sig_SYNC <= '1'; + end if; + when irq6b => + sig_PC <= X"FFFF"; + adr_o <= d_i & zw_b5; + sel_pc_in <= '1'; + sel_pc_val <= "11"; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + sig_SYNC <= '1'; + end if; + when absx5 => + sig_PC <= zw_b3 & zw_b1; + adc_sbc_finished <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when absy5 => + sig_PC <= zw_b3 & zw_b1; + adc_sbc_finished <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when indy6 => + sig_PC <= zw_b3 & zw_b6; + adc_sbc_finished <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s237 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s348 => + sig_PC <= X"00" & zw_b5; + rmb_started <= '1'; + when s254 => + sig_PC <= X"00" & zw_b5; + ch_a_o <= zw_b2; + ch_b_o <= zw_b4; + when s255 => + sig_PC <= X"00" & zw_b5; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= zw_b11; + op_finished <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s238 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + when s257 => + sig_PC <= X"00" & zw_b5; + ch_a_o <= zw_b5; + ch_b_o <= q_x_i; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s350 => + sig_PC <= X"00" & zw_b1; + rmb_started <= '1'; + when s258 => + sig_PC <= X"00" & zw_b1; + ch_a_o <= zw_b2; + ch_b_o <= zw_b4; + when s259 => + sig_PC <= X"00" & zw_b1; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= zw_b11; + op_finished <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s239 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s260 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s352 => + sig_PC <= zw_b6 & zw_b5; + rmb_started <= '1'; + when s263 => + sig_PC <= zw_b6 & zw_b5; + ch_a_o <= zw_b2; + ch_b_o <= zw_b4; + when s264 => + sig_PC <= zw_b6 & zw_b5; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= zw_b11; + op_finished <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s240 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s266 => + sig_PC <= adr_pc_i; + ch_a_o <= zw_b5; + ch_b_o <= q_x_i; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s353 => + sig_PC <= zw_b6 & zw_b1; + rmb_started <= NOT(zw_reg_0flag); + ch_a_o <= zw_b6; + ch_b_o <= "0000000" & zw_reg_0flag; + when s354 => + sig_PC <= zw_b3 & zw_b1; + when s269 => + sig_PC <= zw_b3 & zw_b1; + ch_a_o <= zw_b2; + ch_b_o <= zw_b4; + when s273 => + sig_PC <= zw_b3 & zw_b1; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= zw_b11; + op_finished <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when zp2w => + sig_PC <= X"00" & zw_b5; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= zw_b11; + op_finished <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when zpx3w => + sig_PC <= X"00" & zw_b1; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= zw_b11; + op_finished <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when zpy3w => + sig_PC <= X"00" & zw_b1; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= zw_b11; + op_finished <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when ab3w => + sig_PC <= zw_b6 & zw_b5; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= zw_b11; + op_finished <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when absx4w => + sig_PC <= zw_b3 & zw_b1; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= zw_b11; + op_finished <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when absx3w => + sig_PC <= zw_b6 & zw_b1; + ch_a_o <= zw_b6; + ch_b_o <= "0000000" & zw_reg_0flag; + sig_RWn <= zw_reg_0flag; + sig_RD <= zw_reg_0flag; + sig_WR <= NOT(zw_reg_0flag); + sig_D_OUT <= zw_b11; + op_finished <= NOT(zw_reg_0flag); + if (rdy_i = '1' AND + zw_reg_0flag = '0') then + sig_SYNC <= '1'; + end if; + when absy4w => + sig_PC <= zw_b3 & zw_b1; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= zw_b11; + op_finished <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when absy3w => + sig_PC <= zw_b6 & zw_b1; + ch_a_o <= zw_b6; + ch_b_o <= "0000000" & zw_reg_0flag; + sig_RWn <= zw_reg_0flag; + sig_RD <= zw_reg_0flag; + sig_WR <= NOT(zw_reg_0flag); + sig_D_OUT <= zw_b11; + op_finished <= NOT(zw_reg_0flag); + if (rdy_i = '1' AND + zw_reg_0flag = '0') then + sig_SYNC <= '1'; + end if; + when ind4w => + sig_PC <= zw_b5 & zw_b6; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= zw_b11; + op_finished <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when indx5w => + sig_PC <= zw_b2 & zw_b5; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= zw_b11; + op_finished <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when indy5w => + sig_PC <= zw_b3 & zw_b6; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= zw_b11; + op_finished <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when indy4w => + sig_PC <= zw_b5 & zw_b6; + ch_a_o <= zw_b5; + ch_b_o <= "0000000" & zw_reg_0flag; + sig_RWn <= zw_reg_0flag; + sig_RD <= zw_reg_0flag; + sig_WR <= NOT(zw_reg_0flag); + sig_D_OUT <= zw_b11; + op_finished <= NOT(zw_reg_0flag); + if (rdy_i = '1' AND + zw_reg_0flag = '0') then + sig_SYNC <= '1'; + end if; + when s256 => + sig_PC <= X"00" & zw_b5; + ch_a_o <= "00000" & zw_REG_OP (6 downto 4) ; + when s261 => + sig_PC <= X"00" & zw_b1; + when s265 => + sig_PC <= zw_b6 & zw_b5; + when s274 => + sig_PC <= zw_b3 & zw_b1; + when s355 => + sig_PC <= zw_b3 & zw_b1; + rmb_started <= '1'; + when zp3 => + sig_PC <= X"00" & zw_b5; + adc_sbc_finished <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when zpx4 => + sig_PC <= X"00" & zw_b1; + adc_sbc_finished <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when ab4 => + sig_PC <= zw_b6 & zw_b5; + adc_sbc_finished <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when ind5 => + sig_PC <= zw_b5 & zw_b6; + adc_sbc_finished <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when indx6 => + sig_PC <= zw_b2 & zw_b5; + adc_sbc_finished <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when imm2 => + sig_PC <= adr_pc_i; + ld_pc_o <= '1'; + adc_sbc_finished <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + sig_SYNC <= '1'; + end if; + when others => + null; + end case; + end process csm_output_proc; + + ----------------------------------------------------------------- + csm_functions_clocked_proc : process ( + clk_clk_i, + rst_rst_n_i + ) + ----------------------------------------------------------------- + begin + if (rst_rst_n_i = '0') then + csm_functions_current_state <= f_rst; + -- Default Reset Values + reg_F <= "00110100"; + zw_b10 <= "00" & X"00"; + zw_b14 <= X"00"; + zw_b7 <= "00" & X"00"; + zw_b8 <= "00" & X"00"; + zw_b9 <= "00" & X"00"; + zw_din <= X"00"; + elsif (clk_clk_i'event and clk_clk_i = '1') then + csm_functions_current_state <= csm_functions_next_state; + -- Default Assignment To Internals + reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0); + zw_b10 <= zw_b10; + zw_b14 <= zw_b14; + zw_b7 <= zw_b7; + zw_b8 <= zw_b8; + zw_b9 <= zw_b9; + zw_din <= zw_din; + + -- Combined Actions + case csm_functions_current_state is + when f_idle => + zw_din <= d_i; + when f_and => + zw_din <= d_i; + reg_F(7) <= n_detect_out; + reg_F(1) <= z_detect_out; + when f_lda => + zw_din <= d_i; + reg_F(7) <= n_detect_out; + reg_F(1) <= z_detect_out; + when f_eor => + zw_din <= d_i; + reg_F(7) <= n_detect_out; + reg_F(1) <= z_detect_out; + when f_cmp => + zw_din <= d_i; + reg_F(7) <= n_detect_out; + reg_F(1) <= z_detect_out; + reg_F(0) <= c_detect_out; + when f_ora => + zw_din <= d_i; + reg_F(7) <= n_detect_out; + reg_F(1) <= z_detect_out; + when f_clc => + reg_F(0) <= '0'; + when f_sec => + reg_F(0) <= '1'; + when f_cld => + reg_F(3) <= '0'; + when f_sed => + reg_F(3) <= '1'; + when f_clv => + reg_F(6) <= '0'; + when f_cli => + reg_F(2) <= '0'; + when f_sei => + reg_F(2) <= '1'; + when f_rti => + zw_din <= d_i; + reg_F(7 downto 6) <= zw_din(7 downto 6); + reg_F(3 downto 0) <= zw_din(3 downto 0); + when f_irq => + reg_F(2) <= '1'; + reg_F(3) <= '0'; + when f_res => + reg_F(2) <= '1'; + reg_F(3) <= '0'; + reg_F(5) <= '1'; + when f_bit1 => + zw_din <= d_i; + reg_F(1) <= z_detect_out; + when f_bit2 => + zw_din <= d_i; + reg_F(7) <= zw_din(7); + reg_F(6) <= zw_din(6); + reg_F(1) <= z_detect_out; + when f_de_in_a => + reg_F(7) <= n_detect_out; + reg_F(1) <= z_detect_out; + when f_adc_bin => + zw_din <= d_i; + reg_F(7) <= zw_ALU(7); + reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (NOT zw_din(7))) OR + (NOT zw_ALU(7) AND (q_a_i(7)) AND (zw_din(7))); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU(8); + when f_sbc_bin => + zw_din <= d_i; + reg_F(7) <= zw_ALU(7); + reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (zw_din(7))) OR + (NOT zw_ALU(7) AND (q_a_i(7)) AND (NOT zw_din(7))); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= (zw_ALU(8) AND (NOT q_a_i(7)) AND (NOT zw_din(7))) OR + (zw_ALU(8) AND (q_a_i(7)) AND (zw_din(7))) OR + (NOT zw_ALU(8) AND (q_a_i(7)) AND (NOT zw_din(7))) OR + (zw_ALU(8) AND (q_a_i(7)) AND (NOT zw_din(7))); + when f_adc_dec => + zw_din <= d_i; + reg_F(6) <= (zw_ALU5(3) XOR q_a_i(7)) AND (NOT (q_a_i(7) XOR zw_din(7))); + reg_F(0) <= zw_ALU4(4); + zw_b8(8 downto 5) <= '0' & ((zw_ALU4(4))) & ((zw_ALU4(4))) & '0'; + zw_b10(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + + unsigned ('0' & zw_din(7 downto 4)) + (zw_ALU3(4)); + zw_b7(8 downto 5) <= '0' & ((zw_ALU3(4))) & ((zw_ALU3(4))) & '0'; + zw_b9(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + + unsigned ('0' & zw_din(3 downto 0)) + reg_F(0); + when f_adc_dec1 => + reg_F(7) <= zw_ALU(7); + reg_F(1) <= NOT (zw_ALU(7) OR zw_ALU(6) OR zw_ALU(5) OR + zw_ALU(4) OR zw_ALU(3) OR zw_ALU(2) OR zw_ALU(1) OR + zw_ALU(0)); + when f_sbc_dec => + zw_din <= d_i; + reg_F(6) <= (zw_ALU2(3) XOR q_a_i(7)) AND (q_a_i(7) XOR zw_din(7)); + reg_F(0) <= (zw_ALU2(4)); + zw_b9(7 downto 0) <= '0' & + (NOT zw_ALU2(4)) & + (NOT zw_ALU2(4)) & + '0' & + '0' & + (NOT zw_ALU1(4)) & + (NOT zw_ALU1(4)) & + '0'; + zw_b8(5 downto 0) <= unsigned ("00" & q_a_i(7 downto 4)) + + unsigned ("00" & NOT (zw_din(7 downto 4))) + (zw_ALU1(4)); + zw_b7(5 downto 0) <= unsigned ("00" & q_a_i(3 downto 0)) + + unsigned ("00" & NOT (zw_din(3 downto 0))) + reg_F(0); + when f_sbc_dec1 => + reg_F(7) <= zw_ALU(7); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + when f_asla => + reg_F(7) <= n_detect_out; + reg_F(1) <= z_detect_out; + reg_F(0) <= shift_rot_l_c_out; + when f_lsra => + reg_F(7) <= n_detect_out; + reg_F(1) <= z_detect_out; + reg_F(0) <= shift_rot_r_c_out; + when f_rola => + reg_F(7) <= n_detect_out; + reg_F(1) <= z_detect_out; + reg_F(0) <= shift_rot_l_c_out; + when f_rora => + reg_F(7) <= n_detect_out; + reg_F(1) <= z_detect_out; + reg_F(0) <= shift_rot_r_c_out; + when f_tax => + reg_F(7) <= n_detect_out; + reg_F(1) <= z_detect_out; + when f_tsx => + reg_F(7) <= n_detect_out; + reg_F(1) <= z_detect_out; + when f_decr => + reg_F(7) <= n_detect_out; + reg_F(1) <= z_detect_out; + when f_asl => + reg_F(7) <= n_detect_out; + reg_F(1) <= z_detect_out; + reg_F(0) <= shift_rot_l_c_out; + when f_lsr => + reg_F(7) <= n_detect_out; + reg_F(1) <= z_detect_out; + reg_F(0) <= shift_rot_r_c_out; + when f_rol => + reg_F(7) <= n_detect_out; + reg_F(1) <= z_detect_out; + reg_F(0) <= shift_rot_l_c_out; + when f_ror => + reg_F(7) <= n_detect_out; + reg_F(1) <= z_detect_out; + reg_F(0) <= shift_rot_r_c_out; + when f_trb => + reg_F(1) <= z_detect_out; + when f_tsb => + reg_F(1) <= z_detect_out; + when others => + null; + end case; + end if; + end process csm_functions_clocked_proc; + + ----------------------------------------------------------------- + csm_functions_nextstate_proc : process ( + adc_sbc_finished, + csm_functions_current_state, + irq_finished, + op_finished, + rdy_i, + reg_F, + rmb_started, + rst_finished, + zw_REG_OP + ) + ----------------------------------------------------------------- + begin + case csm_functions_current_state is + when f_idle => + if (op_finished = '1' and + (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31" or + zw_REG_OP = X"32")) then + csm_functions_next_state <= f_and; + elsif (op_finished = '1' and + (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or zw_REG_OP = X"D2")) then + csm_functions_next_state <= f_cmp; + elsif (op_finished = '1' and + (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51" or + zw_REG_OP = X"52")) then + csm_functions_next_state <= f_eor; + elsif (op_finished = '1' and + (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11" or + zw_REG_OP = X"12")) then + csm_functions_next_state <= f_ora; + elsif (op_finished = '1' and + (zw_REG_OP = X"A9" or zw_REG_OP = X"A5" or zw_REG_OP = X"B5" or zw_REG_OP = X"AD" or + zw_REG_OP = X"BD" or zw_REG_OP = X"B9" or zw_REG_OP = X"A1" or zw_REG_OP = X"B1" or + zw_REG_OP = X"B2" or + zw_REG_OP = X"A2" or zw_REG_OP = X"A6" or zw_REG_OP = X"B6" or zw_REG_OP = X"AE" or + zw_REG_OP = X"BE" or + zw_REG_OP = X"A0" or zw_REG_OP = X"A4" or zw_REG_OP = X"B4" or zw_REG_OP = X"AC" or + zw_REG_OP = X"BC" or + zw_REG_OP = X"68" or zw_REG_OP = X"FA" or zw_REG_OP = X"7A")) then + csm_functions_next_state <= f_lda; + elsif (op_finished = '1' and + zw_REG_OP = X"18") then + csm_functions_next_state <= f_clc; + elsif (op_finished = '1' and + zw_REG_OP = X"38") then + csm_functions_next_state <= f_sec; + elsif (op_finished = '1' and + zw_REG_OP = X"D8") then + csm_functions_next_state <= f_cld; + elsif (op_finished = '1' and + zw_REG_OP = X"F8") then + csm_functions_next_state <= f_sed; + elsif (op_finished = '1' and + zw_REG_OP = X"B8") then + csm_functions_next_state <= f_clv; + elsif (op_finished = '1' and + zw_REG_OP = X"58") then + csm_functions_next_state <= f_cli; + elsif (op_finished = '1' and + (zw_REG_OP = X"78")) then + csm_functions_next_state <= f_sei; + elsif (op_finished = '1' and + (zw_REG_OP = X"40" or + zw_REG_OP = X"28")) then + csm_functions_next_state <= f_rti; + elsif (irq_finished = '1') then + csm_functions_next_state <= f_irq; + elsif (rst_finished = '1') then + csm_functions_next_state <= f_res; + elsif (op_finished = '1' and + zw_REG_OP = X"89") then + csm_functions_next_state <= f_bit1; + elsif (op_finished = '1' and + (zw_REG_OP = X"24" or + zw_REG_OP = X"34" or + zw_REG_OP = X"2C" or + zw_REG_OP = X"3C")) then + csm_functions_next_state <= f_bit2; + elsif (op_finished = '1' and + (zw_REG_OP = X"3A" or + zw_REG_OP = X"CA" or + zw_REG_OP = X"88" or + zw_REG_OP = X"1A" or + zw_REG_OP = X"E8" or + zw_REG_OP = X"C8")) then + csm_functions_next_state <= f_de_in_a; + elsif (op_finished = '1' and + reg_F(3) = '0' and + (zw_REG_OP = X"69" or + zw_REG_OP = X"65" or + zw_REG_OP = X"75" or + zw_REG_OP = X"6D" or + zw_REG_OP = X"72" or + zw_REG_OP = X"7D" or + zw_REG_OP = X"79" or + zw_REG_OP = X"71" or + zw_REG_OP = X"61")) then + csm_functions_next_state <= f_adc_bin; + elsif (op_finished = '1' and + reg_F(3) = '0' and + (zw_REG_OP = X"E9" or + zw_REG_OP = X"E5" or + zw_REG_OP = X"F5" or + zw_REG_OP = X"ED" or + zw_REG_OP = X"F2" or + zw_REG_OP = X"FD" or + zw_REG_OP = X"F9" or + zw_REG_OP = X"F1" or + zw_REG_OP = X"E1")) then + csm_functions_next_state <= f_sbc_bin; + elsif (op_finished = '1' and + reg_F(3) = '1' and + (zw_REG_OP = X"69" or zw_REG_OP = X"65" or zw_REG_OP = X"75" or + zw_REG_OP = X"6D" or zw_REG_OP = X"72" or zw_REG_OP = X"7D" or + zw_REG_OP = X"79" or zw_REG_OP = X"71" or zw_REG_OP = X"61")) then + csm_functions_next_state <= f_adc_dec; + elsif (op_finished = '1' and + reg_F(3) = '1' and + (zw_REG_OP = X"E9" or zw_REG_OP = X"E5" or zw_REG_OP = X"F5" or + zw_REG_OP = X"ED" or zw_REG_OP = X"F2" or zw_REG_OP = X"FD" or + zw_REG_OP = X"F9" or zw_REG_OP = X"F1" or zw_REG_OP = X"E1")) then + csm_functions_next_state <= f_sbc_dec; + elsif (op_finished = '1' and + zw_REG_OP = X"0A") then + csm_functions_next_state <= f_asla; + elsif (op_finished = '1' and + zw_REG_OP = X"4A") then + csm_functions_next_state <= f_lsra; + elsif (op_finished = '1' and + zw_REG_OP = X"2A") then + csm_functions_next_state <= f_rola; + elsif (op_finished = '1' and + zw_REG_OP = X"6A") then + csm_functions_next_state <= f_rora; + elsif (op_finished = '1' and + (zw_REG_OP = X"AA" or zw_REG_OP = X"8A" or + zw_REG_OP = X"A8" or zw_REG_OP = X"98")) then + csm_functions_next_state <= f_tax; + elsif (op_finished = '1' and + zw_REG_OP = X"BA") then + csm_functions_next_state <= f_tsx; + elsif (op_finished = '1' and + (zw_REG_OP = X"C6" or zw_REG_OP = X"E6" or + zw_REG_OP = X"D6" or zw_REG_OP = X"F6" or + zw_REG_OP = X"CE" or zw_REG_OP = X"EE" or + zw_REG_OP = X"DE" or zw_REG_OP = X"FE")) then + csm_functions_next_state <= f_decr; + elsif (rmb_started = '1' and + (zw_REG_OP = X"66" or + zw_REG_OP = X"76" or + zw_REG_OP = X"6E" or + zw_REG_OP = X"7E")) then + csm_functions_next_state <= f_ror; + elsif (rmb_started = '1' and + (zw_REG_OP = X"06" or + zw_REG_OP = X"16" or + zw_REG_OP = X"0E" or + zw_REG_OP = X"1E")) then + csm_functions_next_state <= f_asl; + elsif (rmb_started = '1' and + (zw_REG_OP = X"46" or + zw_REG_OP = X"56" or + zw_REG_OP = X"4E" or + zw_REG_OP = X"5E")) then + csm_functions_next_state <= f_lsr; + elsif (rmb_started = '1' and + (zw_REG_OP = X"26" or + zw_REG_OP = X"36" or + zw_REG_OP = X"2E" or + zw_REG_OP = X"3E")) then + csm_functions_next_state <= f_rol; + elsif (rmb_started = '1' and + zw_REG_OP (7) = '0' and + zw_REG_OP (3 downto 0) = X"7") then + csm_functions_next_state <= f_rmb; + elsif (rmb_started = '1' and + zw_REG_OP (7) = '1' and + zw_REG_OP (3 downto 0) = X"7") then + csm_functions_next_state <= f_smb; + elsif (rmb_started = '1' and + (zw_REG_OP = X"14" or + zw_REG_OP = X"1C")) then + csm_functions_next_state <= f_trb; + elsif (rmb_started = '1' and + (zw_REG_OP = X"04" or + zw_REG_OP = X"0C")) then + csm_functions_next_state <= f_tsb; + else + csm_functions_next_state <= f_idle; + end if; + when f_and => + if (rdy_i = '1') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_and; + end if; + when f_lda => + if (rdy_i = '1') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_lda; + end if; + when f_rst => + csm_functions_next_state <= f_idle; + when f_eor => + if (rdy_i = '1') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_eor; + end if; + when f_cmp => + if (rdy_i = '1') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_cmp; + end if; + when f_ora => + if (rdy_i = '1') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_ora; + end if; + when f_clc => + if (op_finished = '0') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_clc; + end if; + when f_sec => + if (op_finished = '0') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_sec; + end if; + when f_cld => + if (op_finished = '0') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_cld; + end if; + when f_sed => + if (op_finished = '0') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_sed; + end if; + when f_clv => + if (op_finished = '0') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_clv; + end if; + when f_cli => + if (op_finished = '0') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_cli; + end if; + when f_sei => + if (op_finished = '0') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_sei; + end if; + when f_rti => + if (rdy_i = '1') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_rti; + end if; + when f_irq => + if (irq_finished = '0') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_irq; + end if; + when f_res => + if (rst_finished = '0') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_res; + end if; + when f_bit1 => + if (rdy_i = '1') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_bit1; + end if; + when f_bit2 => + if (rdy_i = '1') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_bit2; + end if; + when f_de_in_a => + if (rdy_i = '1') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_de_in_a; + end if; + when f_adc_bin => + if (rdy_i = '1') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_adc_bin; + end if; + when f_sbc_bin => + if (rdy_i = '1') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_sbc_bin; + end if; + when f_adc_dec => + if (rdy_i = '1') then + csm_functions_next_state <= f_adc_dec1; + else + csm_functions_next_state <= f_adc_dec; + end if; + when f_adc_dec1 => + if (adc_sbc_finished = '0') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_adc_dec1; + end if; + when f_sbc_dec => + if (rdy_i = '1') then + csm_functions_next_state <= f_sbc_dec1; + else + csm_functions_next_state <= f_sbc_dec; + end if; + when f_sbc_dec1 => + if (adc_sbc_finished = '0') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_sbc_dec1; + end if; + when f_asla => + if (op_finished = '0') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_asla; + end if; + when f_lsra => + if (op_finished = '0') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_lsra; + end if; + when f_rola => + if (op_finished = '0') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_rola; + end if; + when f_rora => + if (op_finished = '0') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_rora; + end if; + when f_tax => + if (rdy_i = '1') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_tax; + end if; + when f_tsx => + if (op_finished = '0') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_tsx; + end if; + when f_decr => + if (op_finished = '0') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_decr; + end if; + when f_asl => + if (rmb_started = '0') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_asl; + end if; + when f_lsr => + if (rmb_started = '0') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_lsr; + end if; + when f_rol => + if (rmb_started = '0') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_rol; + end if; + when f_ror => + if (rmb_started = '0') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_ror; + end if; + when f_rmb => + if (rmb_started = '0') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_rmb; + end if; + when f_smb => + if (rmb_started = '0') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_smb; + end if; + when f_trb => + if (rmb_started = '0') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_trb; + end if; + when f_tsb => + if (rmb_started = '0') then + csm_functions_next_state <= f_idle; + else + csm_functions_next_state <= f_tsb; + end if; + when others => + csm_functions_next_state <= f_rst; + end case; + end process csm_functions_nextstate_proc; + + ----------------------------------------------------------------- + csm_functions_output_proc : process ( + adr_sp_i, + cnz_detect_in, + csm_functions_current_state, + d_alu_prio_i, + d_regs_out_i, + q_a_i, + reg_F, + shift_rot_asl_out, + shift_rot_in, + shift_rot_lsr_out, + shift_rot_rol_out, + shift_rot_ror_out, + zw_ALU, + zw_ALU1, + zw_ALU3, + zw_ALU5, + zw_b10, + zw_b11, + zw_b2, + zw_b4, + zw_b7, + zw_b8, + zw_b9, + zw_din + ) + ----------------------------------------------------------------- + begin + -- Default Assignment + d_regs_in_o <= X"00"; + load_regs_o <= '0'; + -- Default Assignment To Internals + c_detect_out <= cnz_detect_in(8); + cnz_detect_in <= '0' & X"00"; + n_detect_out <= cnz_detect_in(7); + shift_rot_asl_out <= shift_rot_in (6 downto 0) & '0'; + shift_rot_in <= X"00"; + shift_rot_l_c_out <= shift_rot_in (7); + shift_rot_lsr_out <= '0' & shift_rot_in (7 downto 1); + shift_rot_r_c_out <= shift_rot_in (0); + shift_rot_rol_out <= shift_rot_in (6 downto 0) & reg_F(0); + shift_rot_ror_out <= reg_F(0) & shift_rot_in (7 downto 1); + z_detect_out <= NOT(cnz_detect_in(7) OR cnz_detect_in(6) OR cnz_detect_in(5) OR cnz_detect_in(4) OR cnz_detect_in(3) OR cnz_detect_in(2) OR cnz_detect_in(1) OR cnz_detect_in(0)); + zw_ALU <= "00" & X"00"; + zw_ALU1 <= "00" & X"00"; + zw_ALU2 <= "00" & X"00"; + zw_ALU3 <= "00" & X"00"; + zw_ALU4 <= "00" & X"00"; + zw_ALU5 <= "00" & X"00"; + zw_ALU6 <= "00" & X"00"; + zw_b13 <= X"00"; + + -- Combined Actions + case csm_functions_current_state is + when f_and => + d_regs_in_o <= zw_din AND q_a_i; + load_regs_o <= '1'; + cnz_detect_in <= '0' & (zw_din AND q_a_i); + when f_lda => + d_regs_in_o <= zw_din; + load_regs_o <= '1'; + cnz_detect_in <= '0' & (zw_din); + when f_rst => + d_regs_in_o <= X"00"; + load_regs_o <= '0'; + when f_eor => + d_regs_in_o <= zw_din XOR q_a_i; + load_regs_o <= '1'; + cnz_detect_in <= '0' & (zw_din XOR q_a_i); + when f_cmp => + cnz_detect_in <= unsigned ('0' & d_regs_out_i) + + unsigned ('0' & NOT (zw_din)) + 1; + when f_ora => + d_regs_in_o <= zw_din OR q_a_i; + load_regs_o <= '1'; + cnz_detect_in <= '0' & (zw_din OR q_a_i); + when f_bit1 => + cnz_detect_in <= '0' & (zw_din AND q_a_i); + when f_bit2 => + cnz_detect_in <= '0' & (zw_din AND q_a_i); + when f_de_in_a => + d_regs_in_o <= unsigned(d_regs_out_i) + unsigned(zw_b4); + load_regs_o <= '1'; + cnz_detect_in <= '0' & (unsigned(d_regs_out_i) + unsigned(zw_b4)); + when f_adc_bin => + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & zw_din) + reg_F(0); + when f_sbc_bin => + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (zw_din)) + reg_F(0); + when f_adc_dec => + zw_ALU4(4) <= zw_ALU5(4) OR + (zw_ALU5(3) AND zw_ALU5(2)) OR + (zw_ALU5(3) AND zw_ALU5(1)); + zw_ALU5(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + + unsigned ('0' & zw_din(7 downto 4)) + (zw_ALU3(4)); + zw_ALU3(4) <= zw_ALU1(4) OR + (zw_ALU1(3) AND zw_ALU1(2)) OR + (zw_ALU1(3) AND zw_ALU1(1)); + zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + + unsigned ('0' & zw_din(3 downto 0)) + reg_F(0); + when f_adc_dec1 => + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU(7 downto 4) <= unsigned (zw_b10(3 downto 0)) + unsigned (zw_b8(8 downto 5)); + zw_ALU(3 downto 0) <= unsigned (zw_b9(3 downto 0)) + unsigned (zw_b7(8 downto 5)); + when f_sbc_dec => + zw_ALU2(5 downto 0) <= unsigned ("00" & q_a_i(7 downto 4)) + + unsigned ("00" & NOT (zw_din(7 downto 4))) + (zw_ALU1(4)); + zw_ALU1(5 downto 0) <= unsigned ("00" & q_a_i(3 downto 0)) + + unsigned ("00" & NOT (zw_din(3 downto 0))) + reg_F(0); + when f_sbc_dec1 => + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU(7 downto 0) <= unsigned (( zw_b8(3 downto 0)) & ( zw_b7(3 downto 0))) - + unsigned (zw_b9(7 downto 0)); + when f_asla => + shift_rot_in <= q_a_i; + d_regs_in_o <= shift_rot_asl_out; + load_regs_o <= '1'; + cnz_detect_in <= '0' & (shift_rot_asl_out); + when f_lsra => + shift_rot_in <= q_a_i; + d_regs_in_o <= shift_rot_lsr_out; + load_regs_o <= '1'; + cnz_detect_in <= '0' & (shift_rot_lsr_out); + when f_rola => + shift_rot_in <= q_a_i; + d_regs_in_o <= shift_rot_rol_out; + load_regs_o <= '1'; + cnz_detect_in <= '0' & (shift_rot_rol_out); + when f_rora => + shift_rot_in <= q_a_i; + d_regs_in_o <= shift_rot_ror_out; + load_regs_o <= '1'; + cnz_detect_in <= '0' & (shift_rot_ror_out); + when f_tax => + load_regs_o <= '1'; + cnz_detect_in <= '0' & (d_regs_out_i); + when f_tsx => + d_regs_in_o <= adr_sp_i (7 downto 0); + load_regs_o <= '1'; + cnz_detect_in <= '0' & (adr_sp_i (7 downto 0)); + when f_decr => + cnz_detect_in <= '0' & (zw_b11); + when f_asl => + shift_rot_in <= zw_b2; + zw_b13 <= shift_rot_asl_out; + cnz_detect_in <= '0' & (shift_rot_asl_out); + when f_lsr => + shift_rot_in <= zw_b2; + zw_b13 <= shift_rot_lsr_out; + cnz_detect_in <= '0' & (shift_rot_lsr_out); + when f_rol => + shift_rot_in <= zw_b2; + zw_b13 <= shift_rot_rol_out; + cnz_detect_in <= '0' & (shift_rot_rol_out); + when f_ror => + shift_rot_in <= zw_b2; + zw_b13 <= shift_rot_ror_out; + cnz_detect_in <= '0' & (shift_rot_ror_out); + when f_rmb => + zw_b13 <= zw_b2 and NOT (d_alu_prio_i); + when f_smb => + zw_b13 <= zw_b2 or d_alu_prio_i; + when f_trb => + zw_b13 <= zw_b2 and NOT (q_a_i); + cnz_detect_in <= '0' & (zw_b2 and q_a_i); + when f_tsb => + zw_b13 <= zw_b2 or q_a_i; + cnz_detect_in <= '0' & (zw_b2 and q_a_i); + when others => + null; + end case; + end process csm_functions_output_proc; + + ----------------------------------------------------------------- + csm_rb_out_clocked_proc : process ( + clk_clk_i, + rst_rst_n_i + ) + ----------------------------------------------------------------- + begin + if (rst_rst_n_i = '0') then + csm_rb_out_current_state <= rb_out_idle; + elsif (clk_clk_i'event and clk_clk_i = '1') then + csm_rb_out_current_state <= csm_rb_out_next_state; + end if; + end process csm_rb_out_clocked_proc; + + ----------------------------------------------------------------- + csm_rb_out_nextstate_proc : process ( + csm_rb_out_current_state, + op_fetch, + zw_REG_OP + ) + ----------------------------------------------------------------- + begin + case csm_rb_out_current_state is + when rb_out_idle => + if (op_fetch = '0' and + (zw_REG_OP = X"8A" or + zw_REG_OP = X"9A" or + zw_REG_OP = X"BA" or + zw_REG_OP = X"86" or + zw_REG_OP = X"96" or + zw_REG_OP = X"8E" or + zw_REG_OP = X"E8" or + zw_REG_OP = X"CA" or + zw_REG_OP = X"DA" or + zw_REG_OP = X"E0" or + zw_REG_OP = X"E4" or + zw_REG_OP = X"EC")) then + csm_rb_out_next_state <= rb_out_01; + elsif (op_fetch = '0' and + (zw_REG_OP = X"5A" or + zw_REG_OP = X"98" or + zw_REG_OP = X"84" or + zw_REG_OP = X"88" or + zw_REG_OP = X"94" or + zw_REG_OP = X"8C" or + zw_REG_OP = X"C8" or + zw_REG_OP = X"C0" or + zw_REG_OP = X"C4" or + zw_REG_OP = X"CC")) then + csm_rb_out_next_state <= rb_out_10; + elsif (op_fetch = '0' and + (zw_REG_OP = X"9C" or + zw_REG_OP = X"9E" or + zw_REG_OP = X"64" or + zw_REG_OP = X"74")) then + csm_rb_out_next_state <= rb_out_11; + else + csm_rb_out_next_state <= rb_out_idle; + end if; + when rb_out_01 => + if (op_fetch = '1') then + csm_rb_out_next_state <= rb_out_idle; + else + csm_rb_out_next_state <= rb_out_01; + end if; + when rb_out_10 => + if (op_fetch = '1') then + csm_rb_out_next_state <= rb_out_idle; + else + csm_rb_out_next_state <= rb_out_10; + end if; + when rb_out_11 => + if (op_fetch = '1') then + csm_rb_out_next_state <= rb_out_idle; + else + csm_rb_out_next_state <= rb_out_11; + end if; + when others => + csm_rb_out_next_state <= rb_out_idle; + end case; + end process csm_rb_out_nextstate_proc; + + ----------------------------------------------------------------- + csm_rb_out_output_proc : process ( + csm_rb_out_current_state, + op_fetch, + zw_REG_OP + ) + ----------------------------------------------------------------- + begin + -- Default Assignment + sel_rb_out_o <= "00"; + + -- Combined Actions + case csm_rb_out_current_state is + when rb_out_idle => + sel_rb_out_o <= "00"; + if (op_fetch = '0' and + (zw_REG_OP = X"8A" or + zw_REG_OP = X"9A" or + zw_REG_OP = X"BA" or + zw_REG_OP = X"86" or + zw_REG_OP = X"96" or + zw_REG_OP = X"8E" or + zw_REG_OP = X"E8" or + zw_REG_OP = X"CA" or + zw_REG_OP = X"DA" or + zw_REG_OP = X"E0" or + zw_REG_OP = X"E4" or + zw_REG_OP = X"EC")) then + sel_rb_out_o <= "01"; + elsif (op_fetch = '0' and + (zw_REG_OP = X"5A" or + zw_REG_OP = X"98" or + zw_REG_OP = X"84" or + zw_REG_OP = X"88" or + zw_REG_OP = X"94" or + zw_REG_OP = X"8C" or + zw_REG_OP = X"C8" or + zw_REG_OP = X"C0" or + zw_REG_OP = X"C4" or + zw_REG_OP = X"CC")) then + sel_rb_out_o <= "10"; + elsif (op_fetch = '0' and + (zw_REG_OP = X"9C" or + zw_REG_OP = X"9E" or + zw_REG_OP = X"64" or + zw_REG_OP = X"74")) then + sel_rb_out_o <= "11"; + end if; + when rb_out_01 => + sel_rb_out_o <= "01"; + when rb_out_10 => + sel_rb_out_o <= "10"; + when rb_out_11 => + sel_rb_out_o <= "11"; + when others => + null; + end case; + end process csm_rb_out_output_proc; + + ----------------------------------------------------------------- + csm_reg_clocked_proc : process ( + clk_clk_i, + rst_rst_n_i + ) + ----------------------------------------------------------------- + begin + if (rst_rst_n_i = '0') then + csm_reg_current_state <= reg_idle; + elsif (clk_clk_i'event and clk_clk_i = '1') then + csm_reg_current_state <= csm_reg_next_state; + end if; + end process csm_reg_clocked_proc; + + ----------------------------------------------------------------- + csm_reg_nextstate_proc : process ( + csm_reg_current_state, + op_fetch, + zw_REG_OP + ) + ----------------------------------------------------------------- + begin + case csm_reg_current_state is + when reg_idle => + if (op_fetch = '0' and + (zw_REG_OP = X"FA" or + zw_REG_OP = X"BA" or + zw_REG_OP = X"AA" or + zw_REG_OP = X"A2" or + zw_REG_OP = X"A6" or + zw_REG_OP = X"B6" or + zw_REG_OP = X"AE" or + zw_REG_OP = X"BE" or + zw_REG_OP = X"E8" or + zw_REG_OP = X"CA")) then + csm_reg_next_state <= reg_01; + elsif (op_fetch = '0' and + (zw_REG_OP = X"A8" or + zw_REG_OP = X"7A" or + zw_REG_OP = X"A0" or + zw_REG_OP = X"A4" or + zw_REG_OP = X"B4" or + zw_REG_OP = X"AC" or + zw_REG_OP = X"BC" or + zw_REG_OP = X"C8" or + zw_REG_OP = X"88")) then + csm_reg_next_state <= reg_10; + elsif (op_fetch = '0' and + (zw_REG_OP = X"9A")) then + csm_reg_next_state <= reg_11; + else + csm_reg_next_state <= reg_idle; + end if; + when reg_10 => + if (op_fetch = '1') then + csm_reg_next_state <= reg_idle; + else + csm_reg_next_state <= reg_10; + end if; + when reg_11 => + if (op_fetch = '1') then + csm_reg_next_state <= reg_idle; + else + csm_reg_next_state <= reg_11; + end if; + when reg_01 => + if (op_fetch = '1') then + csm_reg_next_state <= reg_idle; + else + csm_reg_next_state <= reg_01; + end if; + when others => + csm_reg_next_state <= reg_idle; + end case; + end process csm_reg_nextstate_proc; + + ----------------------------------------------------------------- + csm_reg_output_proc : process ( + csm_reg_current_state, + op_fetch, + zw_REG_OP + ) + ----------------------------------------------------------------- + begin + -- Default Assignment + sel_reg_o <= "00"; + + -- Combined Actions + case csm_reg_current_state is + when reg_idle => + sel_reg_o<= "00"; + if (op_fetch = '0' and + (zw_REG_OP = X"FA" or + zw_REG_OP = X"BA" or + zw_REG_OP = X"AA" or + zw_REG_OP = X"A2" or + zw_REG_OP = X"A6" or + zw_REG_OP = X"B6" or + zw_REG_OP = X"AE" or + zw_REG_OP = X"BE" or + zw_REG_OP = X"E8" or + zw_REG_OP = X"CA")) then + sel_reg_o <= "01"; + elsif (op_fetch = '0' and + (zw_REG_OP = X"A8" or + zw_REG_OP = X"7A" or + zw_REG_OP = X"A0" or + zw_REG_OP = X"A4" or + zw_REG_OP = X"B4" or + zw_REG_OP = X"AC" or + zw_REG_OP = X"BC" or + zw_REG_OP = X"C8" or + zw_REG_OP = X"88")) then + sel_reg_o <= "10"; + elsif (op_fetch = '0' and + (zw_REG_OP = X"9A")) then + sel_reg_o <= "11"; + end if; + when reg_10 => + sel_reg_o <= "10"; + when reg_11 => + sel_reg_o <= "11"; + when reg_01 => + sel_reg_o <= "01"; + when others => + null; + end case; + end process csm_reg_output_proc; + + ----------------------------------------------------------------- + csm_rb_in_clocked_proc : process ( + clk_clk_i, + rst_rst_n_i + ) + ----------------------------------------------------------------- + begin + if (rst_rst_n_i = '0') then + csm_rb_in_current_state <= rb_in_idle; + elsif (clk_clk_i'event and clk_clk_i = '1') then + csm_rb_in_current_state <= csm_rb_in_next_state; + end if; + end process csm_rb_in_clocked_proc; + + ----------------------------------------------------------------- + csm_rb_in_nextstate_proc : process ( + csm_rb_in_current_state, + op_fetch, + zw_REG_OP + ) + ----------------------------------------------------------------- + begin + case csm_rb_in_current_state is + when rb_in_idle => + if (op_fetch = '0' and + (zw_REG_OP = X"A8" or + zw_REG_OP = X"AA")) then + csm_rb_in_next_state <= rb_in_00; + elsif (op_fetch = '0' and + (zw_REG_OP = X"98")) then + csm_rb_in_next_state <= rb_in_01; + elsif (op_fetch = '0' and + (zw_REG_OP = X"8A")) then + csm_rb_in_next_state <= rb_in_10; + else + csm_rb_in_next_state <= rb_in_idle; + end if; + when rb_in_01 => + if (op_fetch = '1') then + csm_rb_in_next_state <= rb_in_idle; + else + csm_rb_in_next_state <= rb_in_01; + end if; + when rb_in_10 => + if (op_fetch = '1') then + csm_rb_in_next_state <= rb_in_idle; + else + csm_rb_in_next_state <= rb_in_10; + end if; + when rb_in_00 => + if (op_fetch = '1') then + csm_rb_in_next_state <= rb_in_idle; + else + csm_rb_in_next_state <= rb_in_00; + end if; + when others => + csm_rb_in_next_state <= rb_in_idle; + end case; + end process csm_rb_in_nextstate_proc; + + ----------------------------------------------------------------- + csm_rb_in_output_proc : process ( + csm_rb_in_current_state, + op_fetch, + zw_REG_OP + ) + ----------------------------------------------------------------- + begin + -- Default Assignment + sel_rb_in_o <= "00"; + + -- Combined Actions + case csm_rb_in_current_state is + when rb_in_idle => + sel_rb_in_o <= "11"; + if (op_fetch = '0' and + (zw_REG_OP = X"A8" or + zw_REG_OP = X"AA")) then + sel_rb_in_o <= "00"; + elsif (op_fetch = '0' and + (zw_REG_OP = X"98")) then + sel_rb_in_o <= "01"; + elsif (op_fetch = '0' and + (zw_REG_OP = X"8A")) then + sel_rb_in_o <= "10"; + end if; + when rb_in_01 => + sel_rb_in_o <= "01"; + when rb_in_10 => + sel_rb_in_o <= "10"; + when rb_in_00 => + sel_rb_in_o <= "00"; + when others => + null; + end case; + end process csm_rb_in_output_proc; + + ----------------------------------------------------------------- + csm_add_value_clocked_proc : process ( + clk_clk_i, + rst_rst_n_i + ) + ----------------------------------------------------------------- + begin + if (rst_rst_n_i = '0') then + csm_add_value_current_state <= add_val_idle; + elsif (clk_clk_i'event and clk_clk_i = '1') then + csm_add_value_current_state <= csm_add_value_next_state; + end if; + end process csm_add_value_clocked_proc; + + ----------------------------------------------------------------- + csm_add_value_nextstate_proc : process ( + csm_add_value_current_state, + op_fetch, + zw_REG_OP + ) + ----------------------------------------------------------------- + begin + case csm_add_value_current_state is + when add_val_idle => + if (op_fetch = '0' and + (zw_REG_OP = X"C6" or + zw_REG_OP = X"D6" or + zw_REG_OP = X"CE" or + zw_REG_OP = X"DE" or + zw_REG_OP = X"CA" or + zw_REG_OP = X"88" or + zw_REG_OP = X"3A")) then + csm_add_value_next_state <= add_val; + else + csm_add_value_next_state <= add_val_idle; + end if; + when add_val => + if (op_fetch = '1') then + csm_add_value_next_state <= add_val_idle; + else + csm_add_value_next_state <= add_val; + end if; + when others => + csm_add_value_next_state <= add_val_idle; + end case; + end process csm_add_value_nextstate_proc; + + ----------------------------------------------------------------- + csm_add_value_output_proc : process ( + csm_add_value_current_state + ) + ----------------------------------------------------------------- + begin + -- Default Assignment To Internals + zw_b4 <= X"00"; + + -- Combined Actions + case csm_add_value_current_state is + when add_val_idle => + zw_b4 <= X"01"; + when add_val => + zw_b4 <= X"FF"; + when others => + null; + end case; + end process csm_add_value_output_proc; + + -- Concurrent Statements + -- Clocked output assignments + sync_o <= sync_o_cld; +end fsm; Index: cpu65c02_true_cycle/trunk/beta/rtl/vhdl/fsm_intnmi.vhd =================================================================== --- cpu65c02_true_cycle/trunk/beta/rtl/vhdl/fsm_intnmi.vhd (nonexistent) +++ cpu65c02_true_cycle/trunk/beta/rtl/vhdl/fsm_intnmi.vhd (revision 23) @@ -0,0 +1,167 @@ +-- VHDL Entity r65c02_tc.fsm_intnmi.symbol +-- +-- Created: +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 12:35:56 10.09.2018 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +entity fsm_intnmi is + port( + clk_clk_i : in std_logic; + nmi_n_i : in std_logic; + rst_nmi_i : in std_logic; + rst_rst_n_i : in std_logic; + nmi_o : out std_logic + ); + +-- Declarations + +end fsm_intnmi ; + +-- (C) 2008 - 2013 Jens Gutschmidt +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 1.8 2018/09/01 18:07:00 jens +-- - NMI = '0' need at least 1 cycles for correct +-- operation now (2 cycles in the past) +-- +-- Revision 1.7 2013/07/21 11:11:00 jens +-- - Changing the title block and internal revision history +-- +-- Revision 1.6 2009/01/04 10:20:47 eda +-- Changes for cosmetic issues only +-- +-- Revision 1.5 2009/01/04 09:23:10 eda +-- - Delete unused nets and blocks (same as R6502_TC) +-- - Rename blocks +-- +-- Revision 1.4 2009/01/03 16:53:02 eda +-- - Unused nets and blocks deleted +-- - Renamed blocks +-- +-- Revision 1.3 2009/01/03 16:42:02 eda +-- - Unused nets and blocks deleted +-- - Renamed blocks +-- +-- Revision 1.2 2008/12/31 19:31:24 eda +-- Production Release +-- +-- +-- +-- VHDL Architecture r65c02_tc.fsm_intnmi.fsm +-- +-- Created: +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 12:35:56 10.09.2018 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +-- COPYRIGHT (C) 2008 - 2013 by Jens Gutschmidt +-- +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. +-- +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +architecture fsm of fsm_intnmi is + + type state_type is ( + idle, + idle1, + IMP + ); + + -- State vector declaration + attribute state_vector : string; + attribute state_vector of fsm : architecture is "current_state"; + + -- Declare current and next state signals + signal current_state : state_type; + signal next_state : state_type; + + -- Declare any pre-registered internal signals + signal nmi_o_cld : std_logic ; + +begin + + ----------------------------------------------------------------- + clocked_proc : process ( + clk_clk_i, + rst_rst_n_i + ) + ----------------------------------------------------------------- + begin + if (rst_rst_n_i = '0') then + current_state <= idle; + -- Default Reset Values + nmi_o_cld <= '0'; + elsif (clk_clk_i'event and clk_clk_i = '1') then + current_state <= next_state; + -- Default Assignment To Internals + nmi_o_cld <= '0'; + + -- Combined Actions + case current_state is + when idle1 => + if (nmi_n_i = '0') then + nmi_o_cld <= '1'; + end if; + when IMP => + nmi_o_cld <= '1'; + if (rst_nmi_i = '1') then + nmi_o_cld <= '0'; + end if; + when others => + null; + end case; + end if; + end process clocked_proc; + + ----------------------------------------------------------------- + nextstate_proc : process ( + current_state, + nmi_n_i, + rst_nmi_i + ) + ----------------------------------------------------------------- + begin + case current_state is + when idle => + if (nmi_n_i = '1') then + next_state <= idle1; + else + next_state <= idle; + end if; + when idle1 => + if (nmi_n_i = '0') then + next_state <= IMP; + else + next_state <= idle1; + end if; + when IMP => + if (rst_nmi_i = '1') then + next_state <= idle; + else + next_state <= IMP; + end if; + when others => + next_state <= idle; + end case; + end process nextstate_proc; + + -- Concurrent Statements + -- Clocked output assignments + nmi_o <= nmi_o_cld; +end fsm; Index: cpu65c02_true_cycle/trunk/beta/rtl/vhdl/r65c02_tc.vhd =================================================================== --- cpu65c02_true_cycle/trunk/beta/rtl/vhdl/r65c02_tc.vhd (nonexistent) +++ cpu65c02_true_cycle/trunk/beta/rtl/vhdl/r65c02_tc.vhd (revision 23) @@ -0,0 +1,177 @@ +-- VHDL Entity r65c02_tc.r65c02_tc.symbol +-- +-- Created: +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 15:49:08 04.10.2018 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +entity r65c02_tc is + port( + clk_clk_i : in std_logic; + d_i : in std_logic_vector (7 downto 0); + irq_n_i : in std_logic; + nmi_n_i : in std_logic; + rdy_i : in std_logic; + rst_rst_n_i : in std_logic; + so_n_i : in std_logic; + a_o : out std_logic_vector (15 downto 0); + d_o : out std_logic_vector (7 downto 0); + rd_o : out std_logic; + sync_o : out std_logic; + wr_n_o : out std_logic; + wr_o : out std_logic + ); + +-- Declarations + +end r65c02_tc ; + +-- (C) 2008 - 2018 Jens Gutschmidt +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 2.00RC 2018/10/14 11:50:00 jens +-- - Performance improvements +-- Revision 1.52 2018/09/10 12:14:00 jens +-- - RESET generates SYNC now, 1 dead cycle delayed +-- Revision 1.52 RC 2018/09/09 03:00:00 jens +-- - ADC / SBC flags and A like R65C02 now +-- Revision 1.52 BETA 2018/09/05 19:35:00 jens +-- - BBRx/BBSx internal cycles like real 65C02 now +-- - Bug Fix ADC and SBC in decimal mode (all op codes - +-- 1 cycle is missing +-- - Bug Fix ADC and SBC in decimal mode (all op codes - +-- "Overflow" flag was computed wrong) +-- Revision 1.52 BETA 2018/09/02 18:49:00 jens +-- - Interrupt NMI and IRQ processing via FETCH stage now +-- Revision 1.52 BETA 2018/08/30 15:39:00 jens +-- - Interrupt priority order is now: BRQ - NMI - IRQ +-- - Performance improvements on-going (Mealy -> Moore) +-- Revision 1.52 BETA 2018/08/23 20:27:00 jens +-- - Bug Fixes All Branch Instructions +-- (BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS, BRA) +-- 3 cycles now if branch forward occur and the branch +-- instruction lies on a xxFEh location. +-- (BBR, BBS) 6 cycles now if branch forward occur and the +-- branch instruction lies on a xxFDh location. +-- - Bug Fix Hardware Interrupts NMI & IRQ - 7 cycles & "SYNC" now +-- - Bug Fix Now all cycles are delayable (WR and internal) +-- +-- Revision 1.51 RC 2014/04/19 14:44:00 jens +-- (never submitted to opencores) +-- - Bug Fix JMP ABS - produced a 6502 like JMP (IND) PCH. +-- When the ABS address data bytes cross the page +-- boundary (e.g. $02FE JMP hhll reads hh from +-- $02FF and ll from $0200, instead $02FF and $0300) +-- +-- Revision 1.5 RC 2013/08/01 11:00:00 jens +-- - Change Block name to lower case +-- - Bug Fix CMP (IND) - wrongly decoded as function AND +-- - Bug Fix BRK should clear decimal flag in P Reg +-- - Bug Fix JMP (ABS,X) - Low Address outputted twice - no High Address +-- - Bug Fix Unknown Ops - Used always 1b2c NOP ($EA) - new NOPs created +-- - Bug Fix DECIMAL ADC and SBC (all op codes - "C" flag was computed wrong) +-- - Bug Fix INC/DEC ABS,X - N/Z flag wrongly computed +-- - Bug Fix RTI - should increment stack pointer +-- - Bug Fix "E" & "B" flags (Bits 5 & 4) - should be always "1" in P Reg. Change "RES", "RTI", "IRQ" & "NMI" substates. +-- - Bug Fix ADC and SBC (all sub codes - "Overflow" flag was computed wrong) +-- - Bug Fix RMB, SMB Bug - Bit position decoded wrong +-- +-- Revision 1.4 2013/07/21 11:11:00 jens +-- - Changing the title block and internal revision history +-- - Bug Fix STA [(IND)] op$92 ($92 was missed in the connection list at state FETCH) +-- +-- Revision 1.3 2009/01/04 10:20:50 eda +-- Changes for cosmetic issues only +-- +-- Revision 1.2 2009/01/04 09:23:12 eda +-- - Delete unused nets and blocks (same as R6502_TC) +-- - Rename blocks +-- - Re-arrage FSM symbols in block FSM_Execution_Unit +-- +-- Revision 1.1 2009/01/03 16:36:48 eda +-- -- no description -- +-- +-- +-- +-- VHDL Architecture r65c02_tc.r65c02_tc.struct +-- +-- Created: +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 11:59:49 14.10.2018 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt +-- +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. +-- +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +library r65c02_tc; + +architecture struct of r65c02_tc is + + -- Architecture declarations + + -- Internal signal declarations + + + -- Component Declarations + component core + port ( + clk_clk_i : in std_logic ; + d_i : in std_logic_vector (7 downto 0); + irq_n_i : in std_logic ; + nmi_n_i : in std_logic ; + rdy_i : in std_logic ; + rst_rst_n_i : in std_logic ; + so_n_i : in std_logic ; + a_o : out std_logic_vector (15 downto 0); + d_o : out std_logic_vector (7 downto 0); + rd_o : out std_logic ; + sync_o : out std_logic ; + wr_n_o : out std_logic ; + wr_o : out std_logic + ); + end component; + + -- Optional embedded configurations + -- pragma synthesis_off + for all : core use entity r65c02_tc.core; + -- pragma synthesis_on + + +begin + + -- Instance port mappings. + U_0 : core + port map ( + clk_clk_i => clk_clk_i, + d_i => d_i, + irq_n_i => irq_n_i, + nmi_n_i => nmi_n_i, + rdy_i => rdy_i, + rst_rst_n_i => rst_rst_n_i, + so_n_i => so_n_i, + a_o => a_o, + d_o => d_o, + rd_o => rd_o, + sync_o => sync_o, + wr_n_o => wr_n_o, + wr_o => wr_o + ); + +end struct; Index: cpu65c02_true_cycle/trunk/beta/rtl/vhdl/reg_pc.vhd =================================================================== --- cpu65c02_true_cycle/trunk/beta/rtl/vhdl/reg_pc.vhd (nonexistent) +++ cpu65c02_true_cycle/trunk/beta/rtl/vhdl/reg_pc.vhd (revision 23) @@ -0,0 +1,237 @@ +-- VHDL Entity r65c02_tc.reg_pc.symbol +-- +-- Created: +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 11:59:59 06.09.2018 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +entity reg_pc is + port( + adr_i : in std_logic_vector (15 downto 0); + clk_clk_i : in std_logic; + ld_i : in std_logic_vector (1 downto 0); + ld_pc_i : in std_logic; + offset_i : in std_logic_vector (15 downto 0); + rst_rst_n_i : in std_logic; + sel_pc_in_i : in std_logic; + sel_pc_val_i : in std_logic_vector (1 downto 0); + adr_nxt_pc_o : out std_logic_vector (15 downto 0); + adr_pc_o : out std_logic_vector (15 downto 0) + ); + +-- Declarations + +end reg_pc ; + +-- (C) 2008 - 2018 Jens Gutschmidt +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 1.7 2013/07/21 11:11:00 jens +-- - Changing the title block and internal revision history +-- +-- Revision 1.6 2009/01/04 10:20:47 eda +-- Changes for cosmetic issues only +-- +-- Revision 1.5 2009/01/04 09:23:10 eda +-- - Delete unused nets and blocks (same as R6502_TC) +-- - Rename blocks +-- +-- Revision 1.4 2009/01/03 16:53:02 eda +-- - Unused nets and blocks deleted +-- - Renamed blocks +-- +-- Revision 1.3 2009/01/03 16:42:02 eda +-- - Unused nets and blocks deleted +-- - Renamed blocks +-- +-- Revision 1.2 2008/12/31 19:31:24 eda +-- Production Release +-- +-- +-- +-- VHDL Architecture r65c02_tc.reg_pc.struct +-- +-- Created: +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 11:59:59 06.09.2018 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt +-- +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. +-- +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + + +architecture struct of reg_pc is + + -- Architecture declarations + + -- Internal signal declarations + signal adr_pc_high_o_i : std_logic_vector(7 downto 0); + signal adr_pc_low_o_i : std_logic_vector(7 downto 0); + signal adr_pc_o_i : std_logic_vector(15 downto 0); + signal ci_o_i : std_logic; + signal cout_pc_o_i : std_logic; + signal load3_o_i : std_logic; + signal load_o_i : std_logic; + signal offset_high_o_i : std_logic_vector(7 downto 0); + signal offset_low_o_i : std_logic_vector(7 downto 0); + signal val_o_i : std_logic_vector(7 downto 0); + signal val_one : std_logic_vector(7 downto 0); + signal val_zero : std_logic_vector(7 downto 0); + + -- Implicit buffer signal declarations + signal adr_nxt_pc_o_internal : std_logic_vector (15 downto 0); + signal adr_pc_o_internal : std_logic_vector (15 downto 0); + + + -- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff' + signal mw_U_0reg_cval : std_logic_vector(7 downto 0); + + -- ModuleWare signal declarations(v1.12) for instance 'U_4' of 'adff' + signal mw_U_4reg_cval : std_logic_vector(7 downto 0); + + -- ModuleWare signal declarations(v1.12) for instance 'U_3' of 'split' + signal mw_U_3temp_din : std_logic_vector(15 downto 0); + + -- ModuleWare signal declarations(v1.12) for instance 'U_5' of 'split' + signal mw_U_5temp_din : std_logic_vector(15 downto 0); + + +begin + + -- ModuleWare code(v1.12) for instance 'U_2' of 'add' + u_2combo_proc: process (adr_pc_low_o_i, val_o_i) + variable temp_din0 : std_logic_vector(8 downto 0); + variable temp_din1 : std_logic_vector(8 downto 0); + variable temp_sum : unsigned(8 downto 0); + variable temp_carry : std_logic; + begin + temp_din0 := '0' & adr_pc_low_o_i; + temp_din1 := '0' & val_o_i; + temp_carry := '0'; + temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry; + adr_nxt_pc_o_internal(7 DOWNTO 0) <= conv_std_logic_vector(temp_sum(7 downto 0),8); + cout_pc_o_i <= temp_sum(8) ; + end process u_2combo_proc; + + -- ModuleWare code(v1.12) for instance 'U_11' of 'add' + u_11combo_proc: process (adr_pc_high_o_i, offset_high_o_i, ci_o_i) + variable temp_din0 : std_logic_vector(8 downto 0); + variable temp_din1 : std_logic_vector(8 downto 0); + variable temp_sum : unsigned(8 downto 0); + variable temp_carry : std_logic; + begin + temp_din0 := '0' & adr_pc_high_o_i; + temp_din1 := '0' & offset_high_o_i; + temp_carry := ci_o_i; + temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry; + adr_nxt_pc_o_internal(15 DOWNTO 8) <= conv_std_logic_vector(temp_sum(7 downto 0),8); + end process u_11combo_proc; + + -- ModuleWare code(v1.12) for instance 'U_0' of 'adff' + adr_pc_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval; + u_0seq_proc: process (clk_clk_i, rst_rst_n_i) + begin + if (rst_rst_n_i = '0') then + mw_U_0reg_cval <= "00000000"; + elsif (clk_clk_i'event and clk_clk_i='1') then + if (load_o_i = '1') then + mw_U_0reg_cval <= adr_nxt_pc_o_internal(7 DOWNTO 0); + end if; + end if; + end process u_0seq_proc; + + -- ModuleWare code(v1.12) for instance 'U_4' of 'adff' + adr_pc_o_internal(15 DOWNTO 8) <= mw_U_4reg_cval; + u_4seq_proc: process (clk_clk_i, rst_rst_n_i) + begin + if (rst_rst_n_i = '0') then + mw_U_4reg_cval <= "00000000"; + elsif (clk_clk_i'event and clk_clk_i='1') then + if (load3_o_i = '1') then + mw_U_4reg_cval <= adr_nxt_pc_o_internal(15 DOWNTO 8); + end if; + end if; + end process u_4seq_proc; + + -- ModuleWare code(v1.12) for instance 'U_6' of 'and' + load_o_i <= ld_pc_i and ld_i(0); + + -- ModuleWare code(v1.12) for instance 'U_7' of 'and' + load3_o_i <= ld_pc_i and ld_i(1); + + -- ModuleWare code(v1.12) for instance 'U_10' of 'and' + ci_o_i <= cout_pc_o_i and ld_pc_i; + + -- ModuleWare code(v1.12) for instance 'U_1' of 'constval' + val_zero <= "00000000"; + + -- ModuleWare code(v1.12) for instance 'U_9' of 'constval' + val_one <= "00000001"; + + -- ModuleWare code(v1.12) for instance 'U_8' of 'mux' + u_8combo_proc: process(adr_pc_o_internal, adr_i, sel_pc_in_i) + begin + case sel_pc_in_i is + when '0' => adr_pc_o_i <= adr_pc_o_internal; + when '1' => adr_pc_o_i <= adr_i; + when others => adr_pc_o_i <= (others => 'X'); + end case; + end process u_8combo_proc; + + -- ModuleWare code(v1.12) for instance 'U_13' of 'mux' + u_13combo_proc: process(val_one, val_zero, offset_low_o_i, + sel_pc_val_i) + begin + case sel_pc_val_i is + when "00" => val_o_i <= val_one; + when "01" => val_o_i <= val_zero; + when "10" => val_o_i <= offset_low_o_i; + when "11" => val_o_i <= val_zero; + when others => val_o_i <= (others => 'X'); + end case; + end process u_13combo_proc; + + -- ModuleWare code(v1.12) for instance 'U_3' of 'split' + mw_U_3temp_din <= adr_pc_o_i; + u_3combo_proc: process (mw_U_3temp_din) + variable temp_din: std_logic_vector(15 downto 0); + begin + temp_din := mw_U_3temp_din(15 downto 0); + adr_pc_low_o_i <= temp_din(7 downto 0); + adr_pc_high_o_i <= temp_din(15 downto 8); + end process u_3combo_proc; + + -- ModuleWare code(v1.12) for instance 'U_5' of 'split' + mw_U_5temp_din <= offset_i; + u_5combo_proc: process (mw_U_5temp_din) + variable temp_din: std_logic_vector(15 downto 0); + begin + temp_din := mw_U_5temp_din(15 downto 0); + offset_low_o_i <= temp_din(7 downto 0); + offset_high_o_i <= temp_din(15 downto 8); + end process u_5combo_proc; + + -- Instance port mappings. + + -- Implicit buffered output assignments + adr_nxt_pc_o <= adr_nxt_pc_o_internal; + adr_pc_o <= adr_pc_o_internal; + +end struct; Index: cpu65c02_true_cycle/trunk/beta/rtl/vhdl/reg_sp.vhd =================================================================== --- cpu65c02_true_cycle/trunk/beta/rtl/vhdl/reg_sp.vhd (nonexistent) +++ cpu65c02_true_cycle/trunk/beta/rtl/vhdl/reg_sp.vhd (revision 23) @@ -0,0 +1,161 @@ +-- VHDL Entity r65c02_tc.reg_sp.symbol +-- +-- Created: +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 12:04:08 06.09.2018 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +entity reg_sp is + port( + adr_low_i : in std_logic_vector (7 downto 0); + clk_clk_i : in std_logic; + ld_low_i : in std_logic; + ld_sp_i : in std_logic; + rst_rst_n_i : in std_logic; + sel_sp_as_i : in std_logic; + sel_sp_in_i : in std_logic; + adr_sp_o : out std_logic_vector (15 downto 0) + ); + +-- Declarations + +end reg_sp ; + +-- (C) 2008 - 2018 Jens Gutschmidt +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 1.7 2013/07/21 11:11:00 jens +-- - Changing the title block and internal revision history +-- +-- Revision 1.6 2009/01/04 10:20:47 eda +-- Changes for cosmetic issues only +-- +-- Revision 1.5 2009/01/04 09:23:10 eda +-- - Delete unused nets and blocks (same as R6502_TC) +-- - Rename blocks +-- +-- Revision 1.4 2009/01/03 16:53:02 eda +-- - Unused nets and blocks deleted +-- - Renamed blocks +-- +-- Revision 1.3 2009/01/03 16:42:02 eda +-- - Unused nets and blocks deleted +-- - Renamed blocks +-- +-- Revision 1.2 2008/12/31 19:31:24 eda +-- Production Release +-- +-- +-- +-- VHDL Architecture r65c02_tc.reg_sp.struct +-- +-- Created: +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 12:04:08 06.09.2018 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt +-- +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. +-- +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + + +architecture struct of reg_sp is + + -- Architecture declarations + + -- Internal signal declarations + signal adr_sp_low_o_i : std_logic_vector(7 downto 0); + signal load_o_i : std_logic; + signal result_low1_o_i : std_logic_vector(7 downto 0); + signal result_low_o_i : std_logic_vector(7 downto 0); + signal sp_as_n_o_i : std_logic; + signal val_one : std_logic_vector(7 downto 0); + + -- Implicit buffer signal declarations + signal adr_sp_o_internal : std_logic_vector (15 downto 0); + + + -- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff' + signal mw_U_0reg_cval : std_logic_vector(7 downto 0); + + +begin + + -- ModuleWare code(v1.12) for instance 'U_11' of 'addsub' + u_11combo_proc: process (adr_sp_low_o_i, val_one, sp_as_n_o_i) + variable temp_din0 : std_logic_vector(8 downto 0); + variable temp_din1 : std_logic_vector(8 downto 0); + variable temp_sum : unsigned(8 downto 0); + variable temp_carry : std_logic; + begin + temp_din0 := '0' & adr_sp_low_o_i; + temp_din1 := '0' & val_one; + temp_carry := '0'; + if (sp_as_n_o_i = '1') then + temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry; + else + temp_sum := unsigned(temp_din0) - unsigned(temp_din1) - temp_carry; + end if; + result_low_o_i <= conv_std_logic_vector(temp_sum(7 downto 0),8); + end process u_11combo_proc; + + -- ModuleWare code(v1.12) for instance 'U_0' of 'adff' + adr_sp_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval; + u_0seq_proc: process (clk_clk_i, rst_rst_n_i) + begin + if (rst_rst_n_i = '0') then + mw_U_0reg_cval <= "00000000"; + elsif (clk_clk_i'event and clk_clk_i='1') then + if (load_o_i = '1') then + mw_U_0reg_cval <= result_low1_o_i; + end if; + end if; + end process u_0seq_proc; + + -- ModuleWare code(v1.12) for instance 'U_6' of 'and' + load_o_i <= ld_sp_i and ld_low_i; + + -- ModuleWare code(v1.12) for instance 'U_3' of 'buff' + adr_sp_o_internal(15 DOWNTO 8) <= val_one; + + -- ModuleWare code(v1.12) for instance 'U_4' of 'constval' + val_one <= "00000001"; + + -- ModuleWare code(v1.12) for instance 'U_2' of 'inv' + sp_as_n_o_i <= not(sel_sp_as_i); + + -- ModuleWare code(v1.12) for instance 'U_8' of 'mux' + u_8combo_proc: process(result_low_o_i, adr_low_i, sel_sp_in_i) + begin + case sel_sp_in_i is + when '0' => result_low1_o_i <= result_low_o_i; + when '1' => result_low1_o_i <= adr_low_i; + when others => result_low1_o_i <= (others => 'X'); + end case; + end process u_8combo_proc; + + -- ModuleWare code(v1.12) for instance 'U_10' of 'tap' + adr_sp_low_o_i <= adr_sp_o_internal(7 downto 0); + + -- Instance port mappings. + + -- Implicit buffered output assignments + adr_sp_o <= adr_sp_o_internal; + +end struct; Index: cpu65c02_true_cycle/trunk/beta/rtl/vhdl/regbank_axy.vhd =================================================================== --- cpu65c02_true_cycle/trunk/beta/rtl/vhdl/regbank_axy.vhd (nonexistent) +++ cpu65c02_true_cycle/trunk/beta/rtl/vhdl/regbank_axy.vhd (revision 23) @@ -0,0 +1,207 @@ +-- VHDL Entity r65c02_tc.regbank_axy.symbol +-- +-- Created: +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 20:45:48 27.08.2018 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +entity regbank_axy is + port( + clk_clk_i : in std_logic; + d_regs_in_i : in std_logic_vector (7 downto 0); + load_regs_i : in std_logic; + rst_rst_n_i : in std_logic; + sel_rb_in_i : in std_logic_vector (1 downto 0); + sel_rb_out_i : in std_logic_vector (1 downto 0); + sel_reg_i : in std_logic_vector (1 downto 0); + d_regs_out_o : out std_logic_vector (7 downto 0); + q_a_o : out std_logic_vector (7 downto 0); + q_x_o : out std_logic_vector (7 downto 0); + q_y_o : out std_logic_vector (7 downto 0) + ); + +-- Declarations + +end regbank_axy ; + +-- (C) 2008 - 2018 Jens Gutschmidt +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 1.7 2013/07/21 11:11:00 jens +-- - Changing the title block and internal revision history +-- +-- Revision 1.6 2009/01/04 10:20:47 eda +-- Changes for cosmetic issues only +-- +-- Revision 1.5 2009/01/04 09:23:10 eda +-- - Delete unused nets and blocks (same as R6502_TC) +-- - Rename blocks +-- +-- Revision 1.4 2009/01/03 16:53:02 eda +-- - Unused nets and blocks deleted +-- - Renamed blocks +-- +-- Revision 1.3 2009/01/03 16:42:02 eda +-- - Unused nets and blocks deleted +-- - Renamed blocks +-- +-- Revision 1.2 2008/12/31 19:31:24 eda +-- Production Release +-- +-- +-- +-- VHDL Architecture r65c02_tc.regbank_axy.struct +-- +-- Created: +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 12:04:48 06.09.2018 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt +-- +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. +-- +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + + +architecture struct of regbank_axy is + + -- Architecture declarations + + -- Internal signal declarations + signal ld : std_logic_vector(2 downto 0); + signal load1_o_i : std_logic; + signal load2_o_i : std_logic; + signal load_o_i : std_logic; + signal q_mux_o_i : std_logic_vector(7 downto 0); + signal val_zero : std_logic_vector(7 downto 0); + + -- Implicit buffer signal declarations + signal q_a_o_internal : std_logic_vector (7 downto 0); + signal q_x_o_internal : std_logic_vector (7 downto 0); + signal q_y_o_internal : std_logic_vector (7 downto 0); + + + -- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff' + signal mw_U_0reg_cval : std_logic_vector(7 downto 0); + + -- ModuleWare signal declarations(v1.12) for instance 'U_4' of 'adff' + signal mw_U_4reg_cval : std_logic_vector(7 downto 0); + + -- ModuleWare signal declarations(v1.12) for instance 'U_5' of 'adff' + signal mw_U_5reg_cval : std_logic_vector(7 downto 0); + + +begin + + -- ModuleWare code(v1.12) for instance 'U_0' of 'adff' + q_a_o_internal <= mw_U_0reg_cval; + u_0seq_proc: process (clk_clk_i, rst_rst_n_i) + begin + if (rst_rst_n_i = '0') then + mw_U_0reg_cval <= "00000000"; + elsif (clk_clk_i'event and clk_clk_i='1') then + if (load_o_i = '1') then + mw_U_0reg_cval <= q_mux_o_i; + end if; + end if; + end process u_0seq_proc; + + -- ModuleWare code(v1.12) for instance 'U_4' of 'adff' + q_x_o_internal <= mw_U_4reg_cval; + u_4seq_proc: process (clk_clk_i, rst_rst_n_i) + begin + if (rst_rst_n_i = '0') then + mw_U_4reg_cval <= "00000000"; + elsif (clk_clk_i'event and clk_clk_i='1') then + if (load1_o_i = '1') then + mw_U_4reg_cval <= q_mux_o_i; + end if; + end if; + end process u_4seq_proc; + + -- ModuleWare code(v1.12) for instance 'U_5' of 'adff' + q_y_o_internal <= mw_U_5reg_cval; + u_5seq_proc: process (clk_clk_i, rst_rst_n_i) + begin + if (rst_rst_n_i = '0') then + mw_U_5reg_cval <= "00000000"; + elsif (clk_clk_i'event and clk_clk_i='1') then + if (load2_o_i = '1') then + mw_U_5reg_cval <= q_mux_o_i; + end if; + end if; + end process u_5seq_proc; + + -- ModuleWare code(v1.12) for instance 'U_6' of 'and' + load_o_i <= load_regs_i and ld(0); + + -- ModuleWare code(v1.12) for instance 'U_7' of 'and' + load1_o_i <= load_regs_i and ld(1); + + -- ModuleWare code(v1.12) for instance 'U_8' of 'and' + load2_o_i <= load_regs_i and ld(2); + + -- ModuleWare code(v1.12) for instance 'U_11' of 'constval' + val_zero <= "00000000"; + + -- ModuleWare code(v1.12) for instance 'U_1' of 'decoder1' + u_1combo_proc: process (sel_reg_i) + begin + ld <= (others => '0'); + case sel_reg_i is + when "00" => ld(0) <= '1'; + when "01" => ld(1) <= '1'; + when "10" => ld(2) <= '1'; + when others => ld <= (others => '0'); + end case; + end process u_1combo_proc; + + -- ModuleWare code(v1.12) for instance 'U_2' of 'mux' + u_2combo_proc: process(q_a_o_internal, q_x_o_internal, q_y_o_internal, + val_zero, sel_rb_out_i) + begin + case sel_rb_out_i is + when "00" => d_regs_out_o <= q_a_o_internal; + when "01" => d_regs_out_o <= q_x_o_internal; + when "10" => d_regs_out_o <= q_y_o_internal; + when "11" => d_regs_out_o <= val_zero; + when others => d_regs_out_o <= (others => 'X'); + end case; + end process u_2combo_proc; + + -- ModuleWare code(v1.12) for instance 'U_3' of 'mux' + u_3combo_proc: process(q_a_o_internal, q_y_o_internal, q_x_o_internal, + d_regs_in_i, sel_rb_in_i) + begin + case sel_rb_in_i is + when "00" => q_mux_o_i <= q_a_o_internal; + when "01" => q_mux_o_i <= q_y_o_internal; + when "10" => q_mux_o_i <= q_x_o_internal; + when "11" => q_mux_o_i <= d_regs_in_i; + when others => q_mux_o_i <= (others => 'X'); + end case; + end process u_3combo_proc; + + -- Instance port mappings. + + -- Implicit buffered output assignments + q_a_o <= q_a_o_internal; + q_x_o <= q_x_o_internal; + q_y_o <= q_y_o_internal; + +end struct; Index: cpu65c02_true_cycle/trunk/released/asm/6502_decimal_test.a65 =================================================================== --- cpu65c02_true_cycle/trunk/released/asm/6502_decimal_test.a65 (nonexistent) +++ cpu65c02_true_cycle/trunk/released/asm/6502_decimal_test.a65 (revision 23) @@ -0,0 +1,362 @@ +; Verify decimal mode behavior +; Written by Bruce Clark. This code is public domain. +; see http://www.6502.org/tutorials/decimal_mode.html +; +; Returns: +; ERROR = 0 if the test passed +; ERROR = 1 if the test failed +; modify the code at the DONE label for desired program end +; +; This routine requires 17 bytes of RAM -- 1 byte each for: +; AR, CF, DA, DNVZC, ERROR, HA, HNVZC, N1, N1H, N1L, N2, N2L, NF, VF, and ZF +; and 2 bytes for N2H +; +; Variables: +; N1 and N2 are the two numbers to be added or subtracted +; N1H, N1L, N2H, and N2L are the upper 4 bits and lower 4 bits of N1 and N2 +; DA and DNVZC are the actual accumulator and flag results in decimal mode +; HA and HNVZC are the accumulator and flag results when N1 and N2 are +; added or subtracted using binary arithmetic +; AR, NF, VF, ZF, and CF are the predicted decimal mode accumulator and +; flag results, calculated using binary arithmetic +; +; This program takes approximately 1 minute at 1 MHz (a few seconds more on +; a 65C02 than a 6502 or 65816) +; + +; Configuration: +cputype = 1 ; 0 = 6502, 1 = 65C02, 2 = 65C816 +vld_bcd = 0 ; 0 = allow invalid bcd, 1 = valid bcd only +chk_a = 1 ; check accumulator +chk_n = 1 ; check sign (negative) flag +chk_v = 1 ; check overflow flag +chk_z = 1 ; check zero flag +chk_c = 1 ; check carry flag + +end_of_test macro + db $db ;execute 65C02 stop instruction + endm + + data + org 0 +; operands - register Y = carry in +N1 ds 1 +N2 ds 1 +; binary result +HA ds 1 +HNVZC ds 1 + ;04 +; decimal result +DA ds 1 +DNVZC ds 1 +; predicted results +AR ds 1 +NF ds 1 + ;08 +VF ds 1 +ZF ds 1 +CF ds 1 +ERROR ds 1 + ;0C +; workspace +N1L ds 1 +N1H ds 1 +N2L ds 1 +N2H ds 2 + + code + org $200 +TEST ldy #1 ; initialize Y (used to loop through carry flag values) + sty ERROR ; store 1 in ERROR until the test passes + lda #0 ; initialize N1 and N2 + sta N1 + sta N2 +LOOP1 lda N2 ; N2L = N2 & $0F + and #$0F ; [1] see text + if vld_bcd = 1 + cmp #$0a + bcs NEXT2 + endif + sta N2L + lda N2 ; N2H = N2 & $F0 + and #$F0 ; [2] see text + if vld_bcd = 1 + cmp #$a0 + bcs NEXT2 + endif + sta N2H + ora #$0F ; N2H+1 = (N2 & $F0) + $0F + sta N2H+1 +LOOP2 lda N1 ; N1L = N1 & $0F + and #$0F ; [3] see text + if vld_bcd = 1 + cmp #$0a + bcs NEXT1 + endif + sta N1L + lda N1 ; N1H = N1 & $F0 + and #$F0 ; [4] see text + if vld_bcd = 1 + cmp #$a0 + bcs NEXT1 + endif + sta N1H + jsr ADD + jsr A6502 + jsr COMPARE + bne DONE + jsr SUB + jsr S6502 + jsr COMPARE + bne DONE +NEXT1 inc N1 ; [5] see text + bne LOOP2 ; loop through all 256 values of N1 +NEXT2 inc N2 ; [6] see text + bne LOOP1 ; loop through all 256 values of N2 + dey + bpl LOOP1 ; loop through both values of the carry flag + lda #0 ; test passed, so store 0 in ERROR + sta ERROR +DONE + lda ERROR + jmp DONE + end_of_test + +; Calculate the actual decimal mode accumulator and flags, the accumulator +; and flag results when N1 is added to N2 using binary arithmetic, the +; predicted accumulator result, the predicted carry flag, and the predicted +; V flag +; +ADD sed ; decimal mode + cpy #1 ; set carry if Y = 1, clear carry if Y = 0 + lda N1 + adc N2 + sta DA ; actual accumulator result in decimal mode + php + pla + sta DNVZC ; actual flags result in decimal mode + cld ; binary mode + cpy #1 ; set carry if Y = 1, clear carry if Y = 0 + lda N1 + adc N2 + sta HA ; accumulator result of N1+N2 using binary arithmetic + + php + pla + sta HNVZC ; flags result of N1+N2 using binary arithmetic + cpy #1 + lda N1L + adc N2L + cmp #$0A + ldx #0 + bcc A1 + inx + adc #5 ; add 6 (carry is set) + and #$0F + sec +A1 ora N1H +; +; if N1L + N2L < $0A, then add N2 & $F0 +; if N1L + N2L >= $0A, then add (N2 & $F0) + $0F + 1 (carry is set) +; + adc N2H,x + php + bcs A2 + cmp #$A0 + bcc A3 +A2 adc #$5F ; add $60 (carry is set) + sec +A3 sta AR ; predicted accumulator result + php + pla + sta CF ; predicted carry result + pla +; +; note that all 8 bits of the P register are stored in VF +; + sta VF ; predicted V flags + rts + +; Calculate the actual decimal mode accumulator and flags, and the +; accumulator and flag results when N2 is subtracted from N1 using binary +; arithmetic +; +SUB sed ; decimal mode + cpy #1 ; set carry if Y = 1, clear carry if Y = 0 + lda N1 + sbc N2 + sta DA ; actual accumulator result in decimal mode + php + pla + sta DNVZC ; actual flags result in decimal mode + cld ; binary mode + cpy #1 ; set carry if Y = 1, clear carry if Y = 0 + lda N1 + sbc N2 + sta HA ; accumulator result of N1-N2 using binary arithmetic + + php + pla + sta HNVZC ; flags result of N1-N2 using binary arithmetic + rts + + if cputype != 1 +; Calculate the predicted SBC accumulator result for the 6502 and 65816 +; +SUB1 cpy #1 ; set carry if Y = 1, clear carry if Y = 0 + lda N1L + sbc N2L + ldx #0 + bcs S11 + inx + sbc #5 ; subtract 6 (carry is clear) + and #$0F + clc +S11 ora N1H +; +; if N1L - N2L >= 0, then subtract N2 & $F0 +; if N1L - N2L < 0, then subtract (N2 & $F0) + $0F + 1 (carry is clear) +; + sbc N2H,x + bcs S12 + sbc #$5F ; subtract $60 (carry is clear) +S12 sta AR + rts + endif + + if cputype = 1 +; Calculate the predicted SBC accumulator result for the 6502 and 65C02 +; +SUB2 cpy #1 ; set carry if Y = 1, clear carry if Y = 0 + lda N1L + sbc N2L + ldx #0 + bcs S21 + inx + and #$0F + clc +S21 ora N1H +; +; if N1L - N2L >= 0, then subtract N2 & $F0 +; if N1L - N2L < 0, then subtract (N2 & $F0) + $0F + 1 (carry is clear) +; + sbc N2H,x + bcs S22 + sbc #$5F ; subtract $60 (carry is clear) +S22 cpx #0 + beq S23 + sbc #6 +S23 sta AR ; predicted accumulator result + rts + endif + +; Compare accumulator actual results to predicted results +; +; Return: +; Z flag = 1 (BEQ branch) if same +; Z flag = 0 (BNE branch) if different +; +COMPARE + if chk_a = 1 + lda DA + cmp AR + bne C1 + endif + if chk_n = 1 + lda DNVZC ; [7] see text + eor NF + and #$80 ; mask off N flag + bne C1 + endif + if chk_v = 1 + lda DNVZC ; [8] see text + eor VF + and #$40 ; mask off V flag + bne C1 ; [9] see text + endif + if chk_z = 1 + lda DNVZC + eor ZF ; mask off Z flag + and #2 + bne C1 ; [10] see text + endif + if chk_c = 1 + lda DNVZC + eor CF + and #1 ; mask off C flag + endif +C1 rts + +; These routines store the predicted values for ADC and SBC for the 6502, +; 65C02, and 65816 in AR, CF, NF, VF, and ZF + + if cputype = 0 + +A6502 lda VF ; 6502 +; +; since all 8 bits of the P register were stored in VF, bit 7 of VF contains +; the N flag for NF +; + sta NF + lda HNVZC + sta ZF + rts + +S6502 jsr SUB1 + lda HNVZC + sta NF + sta VF + sta ZF + sta CF + rts + + endif + if cputype = 1 + +A6502 lda AR ; 65C02 + php + pla + sta NF + sta ZF + rts + +S6502 jsr SUB2 + lda AR + php + pla + sta NF + sta ZF + lda HNVZC + sta VF + sta CF + rts + + endif + if cputype = 2 + +A6502 lda AR ; 65C816 + php + pla + sta NF + sta ZF + rts + +S6502 jsr SUB1 + lda AR + php + pla + sta NF + sta ZF + lda HNVZC + sta VF + sta CF + rts + + endif + + org $fffa ;vectors + dw TEST + dw TEST + dw TEST + + end TEST Index: cpu65c02_true_cycle/trunk/released/asm/6502_functional_test.a65 =================================================================== --- cpu65c02_true_cycle/trunk/released/asm/6502_functional_test.a65 (nonexistent) +++ cpu65c02_true_cycle/trunk/released/asm/6502_functional_test.a65 (revision 23) @@ -0,0 +1,6105 @@ +; +; 6 5 0 2 F U N C T I O N A L T E S T +; +; Copyright (C) 2012-2015 Klaus Dormann +; +; This program is free software: you can redistribute it and/or modify +; it under the terms of the GNU General Public License as published by +; the Free Software Foundation, either version 3 of the License, or +; (at your option) any later version. +; +; This program is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program. If not, see . + + +; This program is designed to test all opcodes of a 6502 emulator using all +; addressing modes with focus on propper setting of the processor status +; register bits. +; +; version 04-dec-2017 +; contact info at http://2m5.de or email K@2m5.de +; +; assembled with AS65 from http://www.kingswood-consulting.co.uk/assemblers/ +; command line switches: -l -m -s2 -w -h0 +; | | | | no page headers in listing +; | | | wide listing (133 char/col) +; | | write intel hex file instead of binary +; | expand macros in listing +; generate pass2 listing +; +; No IO - should be run from a monitor with access to registers. +; To run load intel hex image with a load command, than alter PC to 400 hex +; (code_segment) and enter a go command. +; Loop on program counter determines error or successful completion of test. +; Check listing for relevant traps (jump/branch *). +; Please note that in early tests some instructions will have to be used before +; they are actually tested! +; +; RESET, NMI or IRQ should not occur and will be trapped if vectors are enabled. +; Tests documented behavior of the original NMOS 6502 only! No unofficial +; opcodes. Additional opcodes of newer versions of the CPU (65C02, 65816) will +; not be tested. Decimal ops will only be tested with valid BCD operands and +; N V Z flags will be ignored. +; +; Debugging hints: +; Most of the code is written sequentially. if you hit a trap, check the +; immediately preceeding code for the instruction to be tested. Results are +; tested first, flags are checked second by pushing them onto the stack and +; pulling them to the accumulator after the result was checked. The "real" +; flags are no longer valid for the tested instruction at this time! +; If the tested instruction was indexed, the relevant index (X or Y) must +; also be checked. Opposed to the flags, X and Y registers are still valid. +; +; versions: +; 28-jul-2012 1st version distributed for testing +; 29-jul-2012 fixed references to location 0, now #0 +; added license - GPLv3 +; 30-jul-2012 added configuration options +; 01-aug-2012 added trap macro to allow user to change error handling +; 01-dec-2012 fixed trap in branch field must be a branch +; 02-mar-2013 fixed PLA flags not tested +; 19-jul-2013 allowed ROM vectors to be loaded when load_data_direct = 0 +; added test sequence check to detect if tests jump their fence +; 23-jul-2013 added RAM integrity check option +; 16-aug-2013 added error report to standard output option +; 13-dec-2014 added binary/decimal opcode table switch test +; 14-dec-2014 improved relative address test +; 23-aug-2015 added option to disable self modifying tests +; 24-aug-2015 all self modifying immediate opcodes now execute in data RAM +; added small branch offset pretest +; 21-oct-2015 added option to disable decimal mode ADC & SBC tests +; 04-dec-2017 fixed BRK only tested with interrupts enabled +; added option to skip the remainder of a failing test +; in report.i65 + + +; C O N F I G U R A T I O N + +;ROM_vectors writable (0=no, 1=yes) +;if ROM vectors can not be used interrupts will not be trapped +;as a consequence BRK can not be tested but will be emulated to test RTI +ROM_vectors = 1 + +;load_data_direct (0=move from code segment, 1=load directly) +;loading directly is preferred but may not be supported by your platform +;0 produces only consecutive object code, 1 is not suitable for a binary image +load_data_direct = 1 + +;I_flag behavior (0=force enabled, 1=force disabled, 2=prohibit change, 3=allow +;change) 2 requires extra code and is not recommended. SEI & CLI can only be +;tested if you allow changing the interrupt status (I_flag = 3) +I_flag = 3 + +;configure memory - try to stay away from memory used by the system +;zero_page memory start address, $50 (80) consecutive Bytes required +; add 2 if I_flag = 2 +zero_page = $a + +;data_segment memory start address, $6A (106) consecutive Bytes required +data_segment = $200 + if (data_segment & $ff) != 0 + ERROR ERROR ERROR low byte of data_segment MUST be $00 !! + endif + +;code_segment memory start address, 13kB of consecutive space required +; add 2.5 kB if I_flag = 2 +code_segment = $400 + +;self modifying code may be disabled to allow running in ROM +;0=part of the code is self modifying and must reside in RAM +;1=tests disabled: branch range +disable_selfmod = 0 + +;report errors through I/O channel (0=use standard self trap loops, 1=include +;report.i65 as I/O channel, add 3.5 kB) +report = 0 + +;RAM integrity test option. Checks for undesired RAM writes. +;set lowest non RAM or RAM mirror address page (-1=disable, 0=64k, $40=16k) +;leave disabled if a monitor, OS or background interrupt is allowed to alter RAM +ram_top = -1 + +;disable test decimal mode ADC & SBC, 0=enable, 1=disable, +;2=disable including decimal flag in processor status +disable_decimal = 0 + + noopt ;do not take shortcuts + +;macros for error & success traps to allow user modification +;example: +;trap macro +; jsr my_error_handler +; endm +;trap_eq macro +; bne skip\? +; trap ;failed equal (zero) +;skip\? +; endm +; +; my_error_handler should pop the calling address from the stack and report it. +; putting larger portions of code (more than 3 bytes) inside the trap macro +; may lead to branch range problems for some tests. + if report = 0 +trap macro + jmp * ;failed anyway + endm +trap_eq macro + beq * ;failed equal (zero) + endm +trap_ne macro + bne * ;failed not equal (non zero) + endm +trap_cs macro + bcs * ;failed carry set + endm +trap_cc macro + bcc * ;failed carry clear + endm +trap_mi macro + bmi * ;failed minus (bit 7 set) + endm +trap_pl macro + bpl * ;failed plus (bit 7 clear) + endm +trap_vs macro + bvs * ;failed overflow set + endm +trap_vc macro + bvc * ;failed overflow clear + endm +; please observe that during the test the stack gets invalidated +; therefore a RTS inside the success macro is not possible +success macro + jmp * ;test passed, no errors + endm + endif + if report = 1 +trap macro + jsr report_error + endm +trap_eq macro + bne skip\? + trap ;failed equal (zero) +skip\? + endm +trap_ne macro + beq skip\? + trap ;failed not equal (non zero) +skip\? + endm +trap_cs macro + bcc skip\? + trap ;failed carry set +skip\? + endm +trap_cc macro + bcs skip\? + trap ;failed carry clear +skip\? + endm +trap_mi macro + bpl skip\? + trap ;failed minus (bit 7 set) +skip\? + endm +trap_pl macro + bmi skip\? + trap ;failed plus (bit 7 clear) +skip\? + endm +trap_vs macro + bvc skip\? + trap ;failed overflow set +skip\? + endm +trap_vc macro + bvs skip\? + trap ;failed overflow clear +skip\? + endm +; please observe that during the test the stack gets invalidated +; therefore a RTS inside the success macro is not possible +success macro + jsr report_success + endm + endif + + +carry equ %00000001 ;flag bits in status +zero equ %00000010 +intdis equ %00000100 +decmode equ %00001000 +break equ %00010000 +reserv equ %00100000 +overfl equ %01000000 +minus equ %10000000 + +fc equ carry +fz equ zero +fzc equ carry+zero +fv equ overfl +fvz equ overfl+zero +fn equ minus +fnc equ minus+carry +fnz equ minus+zero +fnzc equ minus+zero+carry +fnv equ minus+overfl + +fao equ break+reserv ;bits always on after PHP, BRK +fai equ fao+intdis ;+ forced interrupt disable +faod equ fao+decmode ;+ ignore decimal +faid equ fai+decmode ;+ ignore decimal +m8 equ $ff ;8 bit mask +m8i equ $ff&~intdis ;8 bit mask - interrupt disable + +;macros to allow masking of status bits. +;masking test of decimal bit +;masking of interrupt enable/disable on load and compare +;masking of always on bits after PHP or BRK (unused & break) on compare + if disable_decimal < 2 + if I_flag = 0 +load_flag macro + lda #\1&m8i ;force enable interrupts (mask I) + endm +cmp_flag macro + cmp #(\1|fao)&m8i ;I_flag is always enabled + always on bits + endm +eor_flag macro + eor #(\1&m8i|fao) ;mask I, invert expected flags + always on bits + endm + endif + if I_flag = 1 +load_flag macro + lda #\1|intdis ;force disable interrupts + endm +cmp_flag macro + cmp #(\1|fai)&m8 ;I_flag is always disabled + always on bits + endm +eor_flag macro + eor #(\1|fai) ;invert expected flags + always on bits + I + endm + endif + if I_flag = 2 +load_flag macro + lda #\1 + ora flag_I_on ;restore I-flag + and flag_I_off + endm +cmp_flag macro + eor flag_I_on ;I_flag is never changed + cmp #(\1|fao)&m8i ;expected flags + always on bits, mask I + endm +eor_flag macro + eor flag_I_on ;I_flag is never changed + eor #(\1&m8i|fao) ;mask I, invert expected flags + always on bits + endm + endif + if I_flag = 3 +load_flag macro + lda #\1 ;allow test to change I-flag (no mask) + endm +cmp_flag macro + cmp #(\1|fao)&m8 ;expected flags + always on bits + endm +eor_flag macro + eor #\1|fao ;invert expected flags + always on bits + endm + endif + else + if I_flag = 0 +load_flag macro + lda #\1&m8i ;force enable interrupts (mask I) + endm +cmp_flag macro + ora #decmode ;ignore decimal mode bit + cmp #(\1|faod)&m8i ;I_flag is always enabled + always on bits + endm +eor_flag macro + ora #decmode ;ignore decimal mode bit + eor #(\1&m8i|faod) ;mask I, invert expected flags + always on bits + endm + endif + if I_flag = 1 +load_flag macro + lda #\1|intdis ;force disable interrupts + endm +cmp_flag macro + ora #decmode ;ignore decimal mode bit + cmp #(\1|faid)&m8 ;I_flag is always disabled + always on bits + endm +eor_flag macro + ora #decmode ;ignore decimal mode bit + eor #(\1|faid) ;invert expected flags + always on bits + I + endm + endif + if I_flag = 2 +load_flag macro + lda #\1 + ora flag_I_on ;restore I-flag + and flag_I_off + endm +cmp_flag macro + eor flag_I_on ;I_flag is never changed + ora #decmode ;ignore decimal mode bit + cmp #(\1|faod)&m8i ;expected flags + always on bits, mask I + endm +eor_flag macro + eor flag_I_on ;I_flag is never changed + ora #decmode ;ignore decimal mode bit + eor #(\1&m8i|faod) ;mask I, invert expected flags + always on bits + endm + endif + if I_flag = 3 +load_flag macro + lda #\1 ;allow test to change I-flag (no mask) + endm +cmp_flag macro + ora #decmode ;ignore decimal mode bit + cmp #(\1|faod)&m8 ;expected flags + always on bits + endm +eor_flag macro + ora #decmode ;ignore decimal mode bit + eor #\1|faod ;invert expected flags + always on bits + endm + endif + endif + +;macros to set (register|memory|zeropage) & status +set_stat macro ;setting flags in the processor status register + load_flag \1 + pha ;use stack to load status + plp + endm + +set_a macro ;precharging accu & status + load_flag \2 + pha ;use stack to load status + lda #\1 ;precharge accu + plp + endm + +set_x macro ;precharging index & status + load_flag \2 + pha ;use stack to load status + ldx #\1 ;precharge index x + plp + endm + +set_y macro ;precharging index & status + load_flag \2 + pha ;use stack to load status + ldy #\1 ;precharge index y + plp + endm + +set_ax macro ;precharging indexed accu & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;precharge accu + plp + endm + +set_ay macro ;precharging indexed accu & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,y ;precharge accu + plp + endm + +set_z macro ;precharging indexed zp & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;load to zeropage + sta zpt + plp + endm + +set_zx macro ;precharging zp,x & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;load to indexed zeropage + sta zpt,x + plp + endm + +set_abs macro ;precharging indexed memory & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;load to memory + sta abst + plp + endm + +set_absx macro ;precharging abs,x & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;load to indexed memory + sta abst,x + plp + endm + +;macros to test (register|memory|zeropage) & status & (mask) +tst_stat macro ;testing flags in the processor status register + php ;save status + pla ;use stack to retrieve status + pha + cmp_flag \1 + trap_ne + plp ;restore status + endm + +tst_a macro ;testing result in accu & flags + php ;save flags + cmp #\1 ;test result + trap_ne + pla ;load status + pha + cmp_flag \2 + trap_ne + plp ;restore status + endm + +tst_x macro ;testing result in x index & flags + php ;save flags + cpx #\1 ;test result + trap_ne + pla ;load status + pha + cmp_flag \2 + trap_ne + plp ;restore status + endm + +tst_y macro ;testing result in y index & flags + php ;save flags + cpy #\1 ;test result + trap_ne + pla ;load status + pha + cmp_flag \2 + trap_ne + plp ;restore status + endm + +tst_ax macro ;indexed testing result in accu & flags + php ;save flags + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne ; + endm + +tst_ay macro ;indexed testing result in accu & flags + php ;save flags + cmp \1,y ;test result + trap_ne ; + pla ;load status + eor_flag \3 + cmp \2,y ;test flags + trap_ne + endm + +tst_z macro ;indexed testing result in zp & flags + php ;save flags + lda zpt + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne + endm + +tst_zx macro ;testing result in zp,x & flags + php ;save flags + lda zpt,x + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne + endm + +tst_abs macro ;indexed testing result in memory & flags + php ;save flags + lda abst + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne + endm + +tst_absx macro ;testing result in abs,x & flags + php ;save flags + lda abst,x + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne + endm + +; RAM integrity test +; verifies that none of the previous tests has altered RAM outside of the +; designated write areas. +; uses zpt word as indirect pointer, zpt+2 word as checksum + if ram_top > -1 +check_ram macro + cld + lda #0 + sta zpt ;set low byte of indirect pointer + sta zpt+3 ;checksum high byte + if disable_selfmod = 0 + sta range_adr ;reset self modifying code + endif + clc + ldx #zp_bss-zero_page ;zeropage - write test area +ccs3\? adc zero_page,x + bcc ccs2\? + inc zpt+3 ;carry to high byte + clc +ccs2\? inx + bne ccs3\? + ldx #hi(abs1) ;set high byte of indirect pointer + stx zpt+1 + ldy #lo(abs1) ;data after write & execute test area +ccs5\? adc (zpt),y + bcc ccs4\? + inc zpt+3 ;carry to high byte + clc +ccs4\? iny + bne ccs5\? + inx ;advance RAM high address + stx zpt+1 + cpx #ram_top + bne ccs5\? + sta zpt+2 ;checksum low is + cmp ram_chksm ;checksum low expected + trap_ne ;checksum mismatch + lda zpt+3 ;checksum high is + cmp ram_chksm+1 ;checksum high expected + trap_ne ;checksum mismatch + endm + else +check_ram macro + ;RAM check disabled - RAM size not set + endm + endif + +next_test macro ;make sure, tests don't jump the fence + lda test_case ;previous test + cmp #test_num + trap_ne ;test is out of sequence +test_num = test_num + 1 + lda #test_num ;*** next tests' number + sta test_case + ;check_ram ;uncomment to find altered RAM after each test + endm + + if load_data_direct = 1 + data + else + bss ;uninitialized segment, copy of data at end of code! + endif + org zero_page +;break test interrupt save +irq_a ds 1 ;a register +irq_x ds 1 ;x register + if I_flag = 2 +;masking for I bit in status +flag_I_on ds 1 ;or mask to load flags +flag_I_off ds 1 ;and mask to load flags + endif +zpt ;5 bytes store/modify test area +;add/subtract operand generation and result/flag prediction +adfc ds 1 ;carry flag before op +ad1 ds 1 ;operand 1 - accumulator +ad2 ds 1 ;operand 2 - memory / immediate +adrl ds 1 ;expected result bits 0-7 +adrh ds 1 ;expected result bit 8 (carry) +adrf ds 1 ;expected flags NV0000ZC (only binary mode) +sb2 ds 1 ;operand 2 complemented for subtract +zp_bss +zp1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR +zp7f db $7f ;test pattern for compare +;logical zeropage operands +zpOR db 0,$1f,$71,$80 ;test pattern for OR +zpAN db $0f,$ff,$7f,$80 ;test pattern for AND +zpEO db $ff,$0f,$8f,$8f ;test pattern for EOR +;indirect addressing pointers +ind1 dw abs1 ;indirect pointer to pattern in absolute memory + dw abs1+1 + dw abs1+2 + dw abs1+3 + dw abs7f +inw1 dw abs1-$f8 ;indirect pointer for wrap-test pattern +indt dw abst ;indirect pointer to store area in absolute memory + dw abst+1 + dw abst+2 + dw abst+3 +inwt dw abst-$f8 ;indirect pointer for wrap-test store +indAN dw absAN ;indirect pointer to AND pattern in absolute memory + dw absAN+1 + dw absAN+2 + dw absAN+3 +indEO dw absEO ;indirect pointer to EOR pattern in absolute memory + dw absEO+1 + dw absEO+2 + dw absEO+3 +indOR dw absOR ;indirect pointer to OR pattern in absolute memory + dw absOR+1 + dw absOR+2 + dw absOR+3 +;add/subtract indirect pointers +adi2 dw ada2 ;indirect pointer to operand 2 in absolute memory +sbi2 dw sba2 ;indirect pointer to complemented operand 2 (SBC) +adiy2 dw ada2-$ff ;with offset for indirect indexed +sbiy2 dw sba2-$ff +zp_bss_end + + org data_segment +test_case ds 1 ;current test number +ram_chksm ds 2 ;checksum for RAM integrity test +;add/subtract operand copy - abs tests write area +abst ;5 bytes store/modify test area +ada2 ds 1 ;operand 2 +sba2 ds 1 ;operand 2 complemented for subtract + ds 3 ;fill remaining bytes +data_bss + if load_data_direct = 1 +ex_andi and #0 ;execute immediate opcodes + rts +ex_eori eor #0 ;execute immediate opcodes + rts +ex_orai ora #0 ;execute immediate opcodes + rts +ex_adci adc #0 ;execute immediate opcodes + rts +ex_sbci sbc #0 ;execute immediate opcodes + rts + else +ex_andi ds 3 +ex_eori ds 3 +ex_orai ds 3 +ex_adci ds 3 +ex_sbci ds 3 + endif +abs1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR +abs7f db $7f ;test pattern for compare +;loads +fLDx db fn,fn,0,fz ;expected flags for load +;shifts +rASL ;expected result ASL & ROL -carry +rROL db $86,$04,$82,0 ; " +rROLc db $87,$05,$83,1 ;expected result ROL +carry +rLSR ;expected result LSR & ROR -carry +rROR db $61,$41,$20,0 ; " +rRORc db $e1,$c1,$a0,$80 ;expected result ROR +carry +fASL ;expected flags for shifts +fROL db fnc,fc,fn,fz ;no carry in +fROLc db fnc,fc,fn,0 ;carry in +fLSR +fROR db fc,0,fc,fz ;no carry in +fRORc db fnc,fn,fnc,fn ;carry in +;increments (decrements) +rINC db $7f,$80,$ff,0,1 ;expected result for INC/DEC +fINC db 0,fn,fn,fz,0 ;expected flags for INC/DEC +;logical memory operand +absOR db 0,$1f,$71,$80 ;test pattern for OR +absAN db $0f,$ff,$7f,$80 ;test pattern for AND +absEO db $ff,$0f,$8f,$8f ;test pattern for EOR +;logical accu operand +absORa db 0,$f1,$1f,0 ;test pattern for OR +absANa db $f0,$ff,$ff,$ff ;test pattern for AND +absEOa db $ff,$f0,$f0,$0f ;test pattern for EOR +;logical results +absrlo db 0,$ff,$7f,$80 +absflo db fz,fn,0,fn +data_bss_end + + + code + org code_segment +start cld + ldx #$ff + txs + lda #0 ;*** test 0 = initialize + sta test_case +test_num = 0 + +;stop interrupts before initializing BSS + if I_flag = 1 + sei + endif + +;initialize I/O for report channel + if report = 1 + jsr report_init + endif + +;pretest small branch offset + ldx #5 + jmp psb_test +psb_bwok + ldy #5 + bne psb_forw + trap ;branch should be taken + dey ;forward landing zone + dey + dey + dey + dey +psb_forw + dey + dey + dey + dey + dey + beq psb_fwok + trap ;forward offset + + dex ;backward landing zone + dex + dex + dex + dex +psb_back + dex + dex + dex + dex + dex + beq psb_bwok + trap ;backward offset +psb_test + bne psb_back + trap ;branch should be taken +psb_fwok + +;initialize BSS segment + if load_data_direct != 1 + ldx #zp_end-zp_init-1 +ld_zp lda zp_init,x + sta zp_bss,x + dex + bpl ld_zp + ldx #data_end-data_init-1 +ld_data lda data_init,x + sta data_bss,x + dex + bpl ld_data + if ROM_vectors = 1 + ldx #5 +ld_vect lda vec_init,x + sta vec_bss,x + dex + bpl ld_vect + endif + endif + +;retain status of interrupt flag + if I_flag = 2 + php + pla + and #4 ;isolate flag + sta flag_I_on ;or mask + eor #lo(~4) ;reverse + sta flag_I_off ;and mask + endif + +;generate checksum for RAM integrity test + if ram_top > -1 + lda #0 + sta zpt ;set low byte of indirect pointer + sta ram_chksm+1 ;checksum high byte + if disable_selfmod = 0 + sta range_adr ;reset self modifying code + endif + clc + ldx #zp_bss-zero_page ;zeropage - write test area +gcs3 adc zero_page,x + bcc gcs2 + inc ram_chksm+1 ;carry to high byte + clc +gcs2 inx + bne gcs3 + ldx #hi(abs1) ;set high byte of indirect pointer + stx zpt+1 + ldy #lo(abs1) ;data after write & execute test area +gcs5 adc (zpt),y + bcc gcs4 + inc ram_chksm+1 ;carry to high byte + clc +gcs4 iny + bne gcs5 + inx ;advance RAM high address + stx zpt+1 + cpx #ram_top + bne gcs5 + sta ram_chksm ;checksum complete + endif + next_test + + if disable_selfmod = 0 +;testing relative addressing with BEQ + ldy #$fe ;testing maximum range, not -1/-2 (invalid/self adr) +range_loop + dey ;next relative address + tya + tax ;precharge count to end of loop + bpl range_fw ;calculate relative address + clc ;avoid branch self or to relative address of branch + adc #2 + nop ;offset landing zone - tolerate +/-5 offset to branch + nop + nop + nop + nop +range_fw + nop + nop + nop + nop + nop + eor #$7f ;complement except sign + sta range_adr ;load into test target + lda #0 ;should set zero flag in status register + jmp range_op + + dex ; offset landing zone - backward branch too far + dex + dex + dex + dex + ;relative address target field with branch under test in the middle + dex ;-128 - max backward + dex + dex + dex + dex + dex + dex + dex + dex ;-120 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-110 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-100 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-90 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-80 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-70 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-60 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-50 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-40 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-30 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-20 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-10 + dex + dex + dex + dex + dex + dex + dex ;-3 +range_op ;test target with zero flag=0, z=1 if previous dex +range_adr = *+1 ;modifiable relative address + beq *+64 ;+64 if called without modification + dex ;+0 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+10 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+20 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+30 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+40 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+50 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+60 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+70 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+80 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+90 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+100 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+110 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+120 + dex + dex + dex + dex + dex + dex + nop ;offset landing zone - forward branch too far + nop + nop + nop + nop + beq range_ok ;+127 - max forward + trap ; bad range + nop ;offset landing zone - tolerate +/-5 offset to branch + nop + nop + nop + nop +range_ok + nop + nop + nop + nop + nop + cpy #0 + beq range_end + jmp range_loop +range_end ;range test successful + endif + next_test + +;partial test BNE & CMP, CPX, CPY immediate + cpy #1 ;testing BNE true + bne test_bne + trap +test_bne + lda #0 + cmp #0 ;test compare immediate + trap_ne + trap_cc + trap_mi + cmp #1 + trap_eq + trap_cs + trap_pl + tax + cpx #0 ;test compare x immediate + trap_ne + trap_cc + trap_mi + cpx #1 + trap_eq + trap_cs + trap_pl + tay + cpy #0 ;test compare y immediate + trap_ne + trap_cc + trap_mi + cpy #1 + trap_eq + trap_cs + trap_pl + next_test +;testing stack operations PHA PHP PLA PLP + + ldx #$ff ;initialize stack + txs + lda #$55 + pha + lda #$aa + pha + cmp $1fe ;on stack ? + trap_ne + tsx + txa ;overwrite accu + cmp #$fd ;sp decremented? + trap_ne + pla + cmp #$aa ;successful retreived from stack? + trap_ne + pla + cmp #$55 + trap_ne + cmp $1ff ;remains on stack? + trap_ne + tsx + cpx #$ff ;sp incremented? + trap_ne + next_test + +;testing branch decisions BPL BMI BVC BVS BCC BCS BNE BEQ + set_stat $ff ;all on + bpl nbr1 ;branches should not be taken + bvc nbr2 + bcc nbr3 + bne nbr4 + bmi br1 ;branches should be taken + trap +br1 bvs br2 + trap +br2 bcs br3 + trap +br3 beq br4 + trap +nbr1 + trap ;previous bpl taken +nbr2 + trap ;previous bvc taken +nbr3 + trap ;previous bcc taken +nbr4 + trap ;previous bne taken +br4 php + tsx + cpx #$fe ;sp after php? + trap_ne + pla + cmp_flag $ff ;returned all flags on? + trap_ne + tsx + cpx #$ff ;sp after php? + trap_ne + set_stat 0 ;all off + bmi nbr11 ;branches should not be taken + bvs nbr12 + bcs nbr13 + beq nbr14 + bpl br11 ;branches should be taken + trap +br11 bvc br12 + trap +br12 bcc br13 + trap +br13 bne br14 + trap +nbr11 + trap ;previous bmi taken +nbr12 + trap ;previous bvs taken +nbr13 + trap ;previous bcs taken +nbr14 + trap ;previous beq taken +br14 php + pla + cmp_flag 0 ;flags off except break (pushed by sw) + reserved? + trap_ne + ;crosscheck flags + set_stat zero + bne brzs1 + beq brzs2 +brzs1 + trap ;branch zero/non zero +brzs2 bcs brzs3 + bcc brzs4 +brzs3 + trap ;branch carry/no carry +brzs4 bmi brzs5 + bpl brzs6 +brzs5 + trap ;branch minus/plus +brzs6 bvs brzs7 + bvc brzs8 +brzs7 + trap ;branch overflow/no overflow +brzs8 + set_stat carry + beq brcs1 + bne brcs2 +brcs1 + trap ;branch zero/non zero +brcs2 bcc brcs3 + bcs brcs4 +brcs3 + trap ;branch carry/no carry +brcs4 bmi brcs5 + bpl brcs6 +brcs5 + trap ;branch minus/plus +brcs6 bvs brcs7 + bvc brcs8 +brcs7 + trap ;branch overflow/no overflow + +brcs8 + set_stat minus + beq brmi1 + bne brmi2 +brmi1 + trap ;branch zero/non zero +brmi2 bcs brmi3 + bcc brmi4 +brmi3 + trap ;branch carry/no carry +brmi4 bpl brmi5 + bmi brmi6 +brmi5 + trap ;branch minus/plus +brmi6 bvs brmi7 + bvc brmi8 +brmi7 + trap ;branch overflow/no overflow +brmi8 + set_stat overfl + beq brvs1 + bne brvs2 +brvs1 + trap ;branch zero/non zero +brvs2 bcs brvs3 + bcc brvs4 +brvs3 + trap ;branch carry/no carry +brvs4 bmi brvs5 + bpl brvs6 +brvs5 + trap ;branch minus/plus +brvs6 bvc brvs7 + bvs brvs8 +brvs7 + trap ;branch overflow/no overflow +brvs8 + set_stat $ff-zero + beq brzc1 + bne brzc2 +brzc1 + trap ;branch zero/non zero +brzc2 bcc brzc3 + bcs brzc4 +brzc3 + trap ;branch carry/no carry +brzc4 bpl brzc5 + bmi brzc6 +brzc5 + trap ;branch minus/plus +brzc6 bvc brzc7 + bvs brzc8 +brzc7 + trap ;branch overflow/no overflow +brzc8 + set_stat $ff-carry + bne brcc1 + beq brcc2 +brcc1 + trap ;branch zero/non zero +brcc2 bcs brcc3 + bcc brcc4 +brcc3 + trap ;branch carry/no carry +brcc4 bpl brcc5 + bmi brcc6 +brcc5 + trap ;branch minus/plus +brcc6 bvc brcc7 + bvs brcc8 +brcc7 + trap ;branch overflow/no overflow +brcc8 + set_stat $ff-minus + bne brpl1 + beq brpl2 +brpl1 + trap ;branch zero/non zero +brpl2 bcc brpl3 + bcs brpl4 +brpl3 + trap ;branch carry/no carry +brpl4 bmi brpl5 + bpl brpl6 +brpl5 + trap ;branch minus/plus +brpl6 bvc brpl7 + bvs brpl8 +brpl7 + trap ;branch overflow/no overflow +brpl8 + set_stat $ff-overfl + bne brvc1 + beq brvc2 +brvc1 + trap ;branch zero/non zero +brvc2 bcc brvc3 + bcs brvc4 +brvc3 + trap ;branch carry/no carry +brvc4 bpl brvc5 + bmi brvc6 +brvc5 + trap ;branch minus/plus +brvc6 bvs brvc7 + bvc brvc8 +brvc7 + trap ;branch overflow/no overflow +brvc8 + next_test + +; test PHA does not alter flags or accumulator but PLA does + ldx #$55 ;x & y protected + ldy #$aa + set_a 1,$ff ;push + pha + tst_a 1,$ff + set_a 0,0 + pha + tst_a 0,0 + set_a $ff,$ff + pha + tst_a $ff,$ff + set_a 1,0 + pha + tst_a 1,0 + set_a 0,$ff + pha + tst_a 0,$ff + set_a $ff,0 + pha + tst_a $ff,0 + set_a 0,$ff ;pull + pla + tst_a $ff,$ff-zero + set_a $ff,0 + pla + tst_a 0,zero + set_a $fe,$ff + pla + tst_a 1,$ff-zero-minus + set_a 0,0 + pla + tst_a $ff,minus + set_a $ff,$ff + pla + tst_a 0,$ff-minus + set_a $fe,0 + pla + tst_a 1,0 + cpx #$55 ;x & y unchanged? + trap_ne + cpy #$aa + trap_ne + next_test + +; partial pretest EOR # + set_a $3c,0 + eor #$c3 + tst_a $ff,fn + set_a $c3,0 + eor #$c3 + tst_a 0,fz + next_test + +; PC modifying instructions except branches (NOP, JMP, JSR, RTS, BRK, RTI) +; testing NOP + ldx #$24 + ldy #$42 + set_a $18,0 + nop + tst_a $18,0 + cpx #$24 + trap_ne + cpy #$42 + trap_ne + ldx #$db + ldy #$bd + set_a $e7,$ff + nop + tst_a $e7,$ff + cpx #$db + trap_ne + cpy #$bd + trap_ne + next_test + +; jump absolute + set_stat $0 + lda #'F' + ldx #'A' + ldy #'R' ;N=0, V=0, Z=0, C=0 + jmp test_far + nop + nop + trap_ne ;runover protection + inx + inx +far_ret + trap_eq ;returned flags OK? + trap_pl + trap_cc + trap_vc + cmp #('F'^$aa) ;returned registers OK? + trap_ne + cpx #('A'+1) + trap_ne + cpy #('R'-3) + trap_ne + dex + iny + iny + iny + eor #$aa ;N=0, V=1, Z=0, C=1 + jmp test_near + nop + nop + trap_ne ;runover protection + inx + inx +test_near + trap_eq ;passed flags OK? + trap_mi + trap_cc + trap_vc + cmp #'F' ;passed registers OK? + trap_ne + cpx #'A' + trap_ne + cpy #'R' + trap_ne + next_test + +; jump indirect + set_stat 0 + lda #'I' + ldx #'N' + ldy #'D' ;N=0, V=0, Z=0, C=0 + jmp (ptr_tst_ind) + nop + trap_ne ;runover protection + dey + dey +ind_ret + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + plp + trap_eq ;returned flags OK? + trap_pl + trap_cc + trap_vc + cmp #('I'^$aa) ;returned registers OK? + trap_ne + cpx #('N'+1) + trap_ne + cpy #('D'-6) + trap_ne + tsx ;SP check + cpx #$ff + trap_ne + next_test + +; jump subroutine & return from subroutine + set_stat 0 + lda #'J' + ldx #'S' + ldy #'R' ;N=0, V=0, Z=0, C=0 + jsr test_jsr +jsr_ret = *-1 ;last address of jsr = return address + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + plp + trap_eq ;returned flags OK? + trap_pl + trap_cc + trap_vc + cmp #('J'^$aa) ;returned registers OK? + trap_ne + cpx #('S'+1) + trap_ne + cpy #('R'-6) + trap_ne + tsx ;sp? + cpx #$ff + trap_ne + next_test + +; break & return from interrupt + if ROM_vectors = 1 + load_flag 0 ;with interrupts enabled if allowed! + pha + lda #'B' + ldx #'R' + ldy #'K' + plp ;N=0, V=0, Z=0, C=0 + brk + else + lda #hi brk_ret0 ;emulated break + pha + lda #lo brk_ret0 + pha + load_flag fao ;set break & unused on stack + pha + load_flag intdis ;during interrupt + pha + lda #'B' + ldx #'R' + ldy #'K' + plp ;N=0, V=0, Z=0, C=0 + jmp irq_trap + endif + dey ;should not be executed +brk_ret0 ;address of break return + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + cmp #'B'^$aa ;returned registers OK? + ;the IRQ vector was never executed if A & X stay unmodified + trap_ne + cpx #'R'+1 + trap_ne + cpy #'K'-6 + trap_ne + pla ;returned flags OK (unchanged)? + cmp_flag 0 + trap_ne + tsx ;sp? + cpx #$ff + trap_ne + if ROM_vectors = 1 + load_flag $ff ;with interrupts disabled if allowed! + pha + lda #$ff-'B' + ldx #$ff-'R' + ldy #$ff-'K' + plp ;N=1, V=1, Z=1, C=1 + brk + else + lda #hi brk_ret1 ;emulated break + pha + lda #lo brk_ret1 + pha + load_flag $ff + pha ;set break & unused on stack + pha ;actual flags + lda #$ff-'B' + ldx #$ff-'R' + ldy #$ff-'K' + plp ;N=1, V=1, Z=1, C=1 + jmp irq_trap + endif + dey ;should not be executed +brk_ret1 ;address of break return + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + cmp #($ff-'B')^$aa ;returned registers OK? + ;the IRQ vector was never executed if A & X stay unmodified + trap_ne + cpx #$ff-'R'+1 + trap_ne + cpy #$ff-'K'-6 + trap_ne + pla ;returned flags OK (unchanged)? + cmp_flag $ff + trap_ne + tsx ;sp? + cpx #$ff + trap_ne + next_test + +; test set and clear flags CLC CLI CLD CLV SEC SEI SED + set_stat $ff + clc + tst_stat $ff-carry + sec + tst_stat $ff + if I_flag = 3 + cli + tst_stat $ff-intdis + sei + tst_stat $ff + endif + cld + tst_stat $ff-decmode + sed + tst_stat $ff + clv + tst_stat $ff-overfl + set_stat 0 + tst_stat 0 + sec + tst_stat carry + clc + tst_stat 0 + if I_flag = 3 + sei + tst_stat intdis + cli + tst_stat 0 + endif + sed + tst_stat decmode + cld + tst_stat 0 + set_stat overfl + tst_stat overfl + clv + tst_stat 0 + next_test +; testing index register increment/decrement and transfer +; INX INY DEX DEY TAX TXA TAY TYA + ldx #$fe + set_stat $ff + inx ;ff + tst_x $ff,$ff-zero + inx ;00 + tst_x 0,$ff-minus + inx ;01 + tst_x 1,$ff-minus-zero + dex ;00 + tst_x 0,$ff-minus + dex ;ff + tst_x $ff,$ff-zero + dex ;fe + set_stat 0 + inx ;ff + tst_x $ff,minus + inx ;00 + tst_x 0,zero + inx ;01 + tst_x 1,0 + dex ;00 + tst_x 0,zero + dex ;ff + tst_x $ff,minus + + ldy #$fe + set_stat $ff + iny ;ff + tst_y $ff,$ff-zero + iny ;00 + tst_y 0,$ff-minus + iny ;01 + tst_y 1,$ff-minus-zero + dey ;00 + tst_y 0,$ff-minus + dey ;ff + tst_y $ff,$ff-zero + dey ;fe + set_stat 0 + iny ;ff + tst_y $ff,0+minus + iny ;00 + tst_y 0,zero + iny ;01 + tst_y 1,0 + dey ;00 + tst_y 0,zero + dey ;ff + tst_y $ff,minus + + ldx #$ff + set_stat $ff + txa + tst_a $ff,$ff-zero + php + inx ;00 + plp + txa + tst_a 0,$ff-minus + php + inx ;01 + plp + txa + tst_a 1,$ff-minus-zero + set_stat 0 + txa + tst_a 1,0 + php + dex ;00 + plp + txa + tst_a 0,zero + php + dex ;ff + plp + txa + tst_a $ff,minus + + ldy #$ff + set_stat $ff + tya + tst_a $ff,$ff-zero + php + iny ;00 + plp + tya + tst_a 0,$ff-minus + php + iny ;01 + plp + tya + tst_a 1,$ff-minus-zero + set_stat 0 + tya + tst_a 1,0 + php + dey ;00 + plp + tya + tst_a 0,zero + php + dey ;ff + plp + tya + tst_a $ff,minus + + load_flag $ff + pha + ldx #$ff ;ff + txa + plp + tay + tst_y $ff,$ff-zero + php + inx ;00 + txa + plp + tay + tst_y 0,$ff-minus + php + inx ;01 + txa + plp + tay + tst_y 1,$ff-minus-zero + load_flag 0 + pha + lda #0 + txa + plp + tay + tst_y 1,0 + php + dex ;00 + txa + plp + tay + tst_y 0,zero + php + dex ;ff + txa + plp + tay + tst_y $ff,minus + + + load_flag $ff + pha + ldy #$ff ;ff + tya + plp + tax + tst_x $ff,$ff-zero + php + iny ;00 + tya + plp + tax + tst_x 0,$ff-minus + php + iny ;01 + tya + plp + tax + tst_x 1,$ff-minus-zero + load_flag 0 + pha + lda #0 ;preset status + tya + plp + tax + tst_x 1,0 + php + dey ;00 + tya + plp + tax + tst_x 0,zero + php + dey ;ff + tya + plp + tax + tst_x $ff,minus + next_test + +;TSX sets NZ - TXS does not +; This section also tests for proper stack wrap around. + ldx #1 ;01 + set_stat $ff + txs + php + lda $101 + cmp_flag $ff + trap_ne + set_stat 0 + txs + php + lda $101 + cmp_flag 0 + trap_ne + dex ;00 + set_stat $ff + txs + php + lda $100 + cmp_flag $ff + trap_ne + set_stat 0 + txs + php + lda $100 + cmp_flag 0 + trap_ne + dex ;ff + set_stat $ff + txs + php + lda $1ff + cmp_flag $ff + trap_ne + set_stat 0 + txs + php + lda $1ff + cmp_flag 0 + + ldx #1 + txs ;sp=01 + set_stat $ff + tsx ;clears Z, N + php ;sp=00 + cpx #1 + trap_ne + lda $101 + cmp_flag $ff-minus-zero + trap_ne + set_stat $ff + tsx ;clears N, sets Z + php ;sp=ff + cpx #0 + trap_ne + lda $100 + cmp_flag $ff-minus + trap_ne + set_stat $ff + tsx ;clears N, sets Z + php ;sp=fe + cpx #$ff + trap_ne + lda $1ff + cmp_flag $ff-zero + trap_ne + + ldx #1 + txs ;sp=01 + set_stat 0 + tsx ;clears Z, N + php ;sp=00 + cpx #1 + trap_ne + lda $101 + cmp_flag 0 + trap_ne + set_stat 0 + tsx ;clears N, sets Z + php ;sp=ff + cpx #0 + trap_ne + lda $100 + cmp_flag zero + trap_ne + set_stat 0 + tsx ;clears N, sets Z + php ;sp=fe + cpx #$ff + trap_ne + lda $1ff + cmp_flag minus + trap_ne + pla ;sp=ff + next_test + +; testing index register load & store LDY LDX STY STX all addressing modes +; LDX / STX - zp,y / abs,y + ldy #3 +tldx + set_stat 0 + ldx zp1,y + php ;test stores do not alter flags + txa + eor #$c3 + plp + sta abst,y + php ;flags after load/store sequence + eor #$c3 + cmp abs1,y ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,y ;test flags + trap_ne + dey + bpl tldx + + ldy #3 +tldx1 + set_stat $ff + ldx zp1,y + php ;test stores do not alter flags + txa + eor #$c3 + plp + sta abst,y + php ;flags after load/store sequence + eor #$c3 + cmp abs1,y ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,y ;test flags + trap_ne + dey + bpl tldx1 + + ldy #3 +tldx2 + set_stat 0 + ldx abs1,y + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt,y + php ;flags after load/store sequence + eor #$c3 + cmp zp1,y ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,y ;test flags + trap_ne + dey + bpl tldx2 + + ldy #3 +tldx3 + set_stat $ff + ldx abs1,y + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt,y + php ;flags after load/store sequence + eor #$c3 + cmp zp1,y ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,y ;test flags + trap_ne + dey + bpl tldx3 + + ldy #3 ;testing store result + ldx #0 +tstx lda zpt,y + eor #$c3 + cmp zp1,y + trap_ne ;store to zp data + stx zpt,y ;clear + lda abst,y + eor #$c3 + cmp abs1,y + trap_ne ;store to abs data + txa + sta abst,y ;clear + dey + bpl tstx + next_test + +; indexed wraparound test (only zp should wrap) + ldy #3+$fa +tldx4 ldx zp1-$fa&$ff,y ;wrap on indexed zp + txa + sta abst-$fa,y ;no STX abs,y! + dey + cpy #$fa + bcs tldx4 + ldy #3+$fa +tldx5 ldx abs1-$fa,y ;no wrap on indexed abs + stx zpt-$fa&$ff,y + dey + cpy #$fa + bcs tldx5 + ldy #3 ;testing wraparound result + ldx #0 +tstx1 lda zpt,y + cmp zp1,y + trap_ne ;store to zp data + stx zpt,y ;clear + lda abst,y + cmp abs1,y + trap_ne ;store to abs data + txa + sta abst,y ;clear + dey + bpl tstx1 + next_test + +; LDY / STY - zp,x / abs,x + ldx #3 +tldy + set_stat 0 + ldy zp1,x + php ;test stores do not alter flags + tya + eor #$c3 + plp + sta abst,x + php ;flags after load/store sequence + eor #$c3 + cmp abs1,x ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,x ;test flags + trap_ne + dex + bpl tldy + + ldx #3 +tldy1 + set_stat $ff + ldy zp1,x + php ;test stores do not alter flags + tya + eor #$c3 + plp + sta abst,x + php ;flags after load/store sequence + eor #$c3 + cmp abs1,x ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,x ;test flags + trap_ne + dex + bpl tldy1 + + ldx #3 +tldy2 + set_stat 0 + ldy abs1,x + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt,x + php ;flags after load/store sequence + eor #$c3 + cmp zp1,x ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,x ;test flags + trap_ne + dex + bpl tldy2 + + ldx #3 +tldy3 + set_stat $ff + ldy abs1,x + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt,x + php ;flags after load/store sequence + eor #$c3 + cmp zp1,x ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,x ;test flags + trap_ne + dex + bpl tldy3 + + ldx #3 ;testing store result + ldy #0 +tsty lda zpt,x + eor #$c3 + cmp zp1,x + trap_ne ;store to zp,x data + sty zpt,x ;clear + lda abst,x + eor #$c3 + cmp abs1,x + trap_ne ;store to abs,x data + txa + sta abst,x ;clear + dex + bpl tsty + next_test + +; indexed wraparound test (only zp should wrap) + ldx #3+$fa +tldy4 ldy zp1-$fa&$ff,x ;wrap on indexed zp + tya + sta abst-$fa,x ;no STX abs,x! + dex + cpx #$fa + bcs tldy4 + ldx #3+$fa +tldy5 ldy abs1-$fa,x ;no wrap on indexed abs + sty zpt-$fa&$ff,x + dex + cpx #$fa + bcs tldy5 + ldx #3 ;testing wraparound result + ldy #0 +tsty1 lda zpt,x + cmp zp1,x + trap_ne ;store to zp,x data + sty zpt,x ;clear + lda abst,x + cmp abs1,x + trap_ne ;store to abs,x data + txa + sta abst,x ;clear + dex + bpl tsty1 + next_test + +; LDX / STX - zp / abs / # + set_stat 0 + ldx zp1 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx abst + php ;flags after load/store sequence + eor #$c3 + tax + cpx #$c3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + ldx zp1+1 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx abst+1 + php ;flags after load/store sequence + eor #$c3 + tax + cpx #$82 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + ldx zp1+2 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx abst+2 + php ;flags after load/store sequence + eor #$c3 + tax + cpx #$41 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + ldx zp1+3 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx abst+3 + php ;flags after load/store sequence + eor #$c3 + tax + cpx #0 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + + set_stat $ff + ldx zp1 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx abst + php ;flags after load/store sequence + eor #$c3 + tax + cpx #$c3 ;test result + trap_ne ; + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + ldx zp1+1 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx abst+1 + php ;flags after load/store sequence + eor #$c3 + tax + cpx #$82 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + ldx zp1+2 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx abst+2 + php ;flags after load/store sequence + eor #$c3 + tax + cpx #$41 ;test result + trap_ne ; + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + ldx zp1+3 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx abst+3 + php ;flags after load/store sequence + eor #$c3 + tax + cpx #0 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + + set_stat 0 + ldx abs1 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt + php ;flags after load/store sequence + eor #$c3 + cmp zp1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + ldx abs1+1 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt+1 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + ldx abs1+2 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt+2 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+2 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + ldx abs1+3 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt+3 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + + set_stat $ff + ldx abs1 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt + php ;flags after load/store sequence + eor #$c3 + tax + cpx zp1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + ldx abs1+1 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt+1 + php ;flags after load/store sequence + eor #$c3 + tax + cpx zp1+1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + ldx abs1+2 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt+2 + php ;flags after load/store sequence + eor #$c3 + tax + cpx zp1+2 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + ldx abs1+3 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt+3 + php ;flags after load/store sequence + eor #$c3 + tax + cpx zp1+3 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + + set_stat 0 + ldx #$c3 + php + cpx abs1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + ldx #$82 + php + cpx abs1+1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + ldx #$41 + php + cpx abs1+2 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + ldx #0 + php + cpx abs1+3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + + set_stat $ff + ldx #$c3 + php + cpx abs1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + ldx #$82 + php + cpx abs1+1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + ldx #$41 + php + cpx abs1+2 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + ldx #0 + php + cpx abs1+3 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + + ldx #0 + lda zpt + eor #$c3 + cmp zp1 + trap_ne ;store to zp data + stx zpt ;clear + lda abst + eor #$c3 + cmp abs1 + trap_ne ;store to abs data + stx abst ;clear + lda zpt+1 + eor #$c3 + cmp zp1+1 + trap_ne ;store to zp data + stx zpt+1 ;clear + lda abst+1 + eor #$c3 + cmp abs1+1 + trap_ne ;store to abs data + stx abst+1 ;clear + lda zpt+2 + eor #$c3 + cmp zp1+2 + trap_ne ;store to zp data + stx zpt+2 ;clear + lda abst+2 + eor #$c3 + cmp abs1+2 + trap_ne ;store to abs data + stx abst+2 ;clear + lda zpt+3 + eor #$c3 + cmp zp1+3 + trap_ne ;store to zp data + stx zpt+3 ;clear + lda abst+3 + eor #$c3 + cmp abs1+3 + trap_ne ;store to abs data + stx abst+3 ;clear + next_test + +; LDY / STY - zp / abs / # + set_stat 0 + ldy zp1 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty abst + php ;flags after load/store sequence + eor #$c3 + tay + cpy #$c3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + ldy zp1+1 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty abst+1 + php ;flags after load/store sequence + eor #$c3 + tay + cpy #$82 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + ldy zp1+2 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty abst+2 + php ;flags after load/store sequence + eor #$c3 + tay + cpy #$41 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + ldy zp1+3 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty abst+3 + php ;flags after load/store sequence + eor #$c3 + tay + cpy #0 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + + set_stat $ff + ldy zp1 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty abst + php ;flags after load/store sequence + eor #$c3 + tay + cpy #$c3 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + ldy zp1+1 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty abst+1 + php ;flags after load/store sequence + eor #$c3 + tay + cpy #$82 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + ldy zp1+2 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty abst+2 + php ;flags after load/store sequence + eor #$c3 + tay + cpy #$41 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + ldy zp1+3 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty abst+3 + php ;flags after load/store sequence + eor #$c3 + tay + cpy #0 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + + set_stat 0 + ldy abs1 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt + php ;flags after load/store sequence + eor #$c3 + tay + cpy zp1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + ldy abs1+1 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt+1 + php ;flags after load/store sequence + eor #$c3 + tay + cpy zp1+1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + ldy abs1+2 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt+2 + php ;flags after load/store sequence + eor #$c3 + tay + cpy zp1+2 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + ldy abs1+3 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt+3 + php ;flags after load/store sequence + eor #$c3 + tay + cpy zp1+3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + + set_stat $ff + ldy abs1 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt + php ;flags after load/store sequence + eor #$c3 + tay + cmp zp1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + ldy abs1+1 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt+1 + php ;flags after load/store sequence + eor #$c3 + tay + cmp zp1+1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + ldy abs1+2 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt+2 + php ;flags after load/store sequence + eor #$c3 + tay + cmp zp1+2 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + ldy abs1+3 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt+3 + php ;flags after load/store sequence + eor #$c3 + tay + cmp zp1+3 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + + + set_stat 0 + ldy #$c3 + php + cpy abs1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + ldy #$82 + php + cpy abs1+1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + ldy #$41 + php + cpy abs1+2 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + ldy #0 + php + cpy abs1+3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + + set_stat $ff + ldy #$c3 + php + cpy abs1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + ldy #$82 + php + cpy abs1+1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + ldy #$41 + php + cpy abs1+2 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + ldy #0 + php + cpy abs1+3 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + + ldy #0 + lda zpt + eor #$c3 + cmp zp1 + trap_ne ;store to zp data + sty zpt ;clear + lda abst + eor #$c3 + cmp abs1 + trap_ne ;store to abs data + sty abst ;clear + lda zpt+1 + eor #$c3 + cmp zp1+1 + trap_ne ;store to zp+1 data + sty zpt+1 ;clear + lda abst+1 + eor #$c3 + cmp abs1+1 + trap_ne ;store to abs+1 data + sty abst+1 ;clear + lda zpt+2 + eor #$c3 + cmp zp1+2 + trap_ne ;store to zp+2 data + sty zpt+2 ;clear + lda abst+2 + eor #$c3 + cmp abs1+2 + trap_ne ;store to abs+2 data + sty abst+2 ;clear + lda zpt+3 + eor #$c3 + cmp zp1+3 + trap_ne ;store to zp+3 data + sty zpt+3 ;clear + lda abst+3 + eor #$c3 + cmp abs1+3 + trap_ne ;store to abs+3 data + sty abst+3 ;clear + next_test + +; testing load / store accumulator LDA / STA all addressing modes +; LDA / STA - zp,x / abs,x + ldx #3 +tldax + set_stat 0 + lda zp1,x + php ;test stores do not alter flags + eor #$c3 + plp + sta abst,x + php ;flags after load/store sequence + eor #$c3 + cmp abs1,x ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,x ;test flags + trap_ne + dex + bpl tldax + + ldx #3 +tldax1 + set_stat $ff + lda zp1,x + php ;test stores do not alter flags + eor #$c3 + plp + sta abst,x + php ;flags after load/store sequence + eor #$c3 + cmp abs1,x ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,x ;test flags + trap_ne + dex + bpl tldax1 + + ldx #3 +tldax2 + set_stat 0 + lda abs1,x + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt,x + php ;flags after load/store sequence + eor #$c3 + cmp zp1,x ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,x ;test flags + trap_ne + dex + bpl tldax2 + + ldx #3 +tldax3 + set_stat $ff + lda abs1,x + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt,x + php ;flags after load/store sequence + eor #$c3 + cmp zp1,x ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,x ;test flags + trap_ne + dex + bpl tldax3 + + ldx #3 ;testing store result + ldy #0 +tstax lda zpt,x + eor #$c3 + cmp zp1,x + trap_ne ;store to zp,x data + sty zpt,x ;clear + lda abst,x + eor #$c3 + cmp abs1,x + trap_ne ;store to abs,x data + txa + sta abst,x ;clear + dex + bpl tstax + next_test + +; LDA / STA - (zp),y / abs,y / (zp,x) + ldy #3 +tlday + set_stat 0 + lda (ind1),y + php ;test stores do not alter flags + eor #$c3 + plp + sta abst,y + php ;flags after load/store sequence + eor #$c3 + cmp abs1,y ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,y ;test flags + trap_ne + dey + bpl tlday + + ldy #3 +tlday1 + set_stat $ff + lda (ind1),y + php ;test stores do not alter flags + eor #$c3 + plp + sta abst,y + php ;flags after load/store sequence + eor #$c3 + cmp abs1,y ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,y ;test flags + trap_ne + dey + bpl tlday1 + + ldy #3 ;testing store result + ldx #0 +tstay lda abst,y + eor #$c3 + cmp abs1,y + trap_ne ;store to abs data + txa + sta abst,y ;clear + dey + bpl tstay + + ldy #3 +tlday2 + set_stat 0 + lda abs1,y + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt),y + php ;flags after load/store sequence + eor #$c3 + cmp (ind1),y ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,y ;test flags + trap_ne + dey + bpl tlday2 + + ldy #3 +tlday3 + set_stat $ff + lda abs1,y + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt),y + php ;flags after load/store sequence + eor #$c3 + cmp (ind1),y ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,y ;test flags + trap_ne + dey + bpl tlday3 + + ldy #3 ;testing store result + ldx #0 +tstay1 lda abst,y + eor #$c3 + cmp abs1,y + trap_ne ;store to abs data + txa + sta abst,y ;clear + dey + bpl tstay1 + + ldx #6 + ldy #3 +tldax4 + set_stat 0 + lda (ind1,x) + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt,x) + php ;flags after load/store sequence + eor #$c3 + cmp abs1,y ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,y ;test flags + trap_ne + dex + dex + dey + bpl tldax4 + + ldx #6 + ldy #3 +tldax5 + set_stat $ff + lda (ind1,x) + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt,x) + php ;flags after load/store sequence + eor #$c3 + cmp abs1,y ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,y ;test flags + trap_ne + dex + dex + dey + bpl tldax5 + + ldy #3 ;testing store result + ldx #0 +tstay2 lda abst,y + eor #$c3 + cmp abs1,y + trap_ne ;store to abs data + txa + sta abst,y ;clear + dey + bpl tstay2 + next_test + +; indexed wraparound test (only zp should wrap) + ldx #3+$fa +tldax6 lda zp1-$fa&$ff,x ;wrap on indexed zp + sta abst-$fa,x ;no STX abs,x! + dex + cpx #$fa + bcs tldax6 + ldx #3+$fa +tldax7 lda abs1-$fa,x ;no wrap on indexed abs + sta zpt-$fa&$ff,x + dex + cpx #$fa + bcs tldax7 + + ldx #3 ;testing wraparound result + ldy #0 +tstax1 lda zpt,x + cmp zp1,x + trap_ne ;store to zp,x data + sty zpt,x ;clear + lda abst,x + cmp abs1,x + trap_ne ;store to abs,x data + txa + sta abst,x ;clear + dex + bpl tstax1 + + ldy #3+$f8 + ldx #6+$f8 +tlday4 lda (ind1-$f8&$ff,x) ;wrap on indexed zp indirect + sta abst-$f8,y + dex + dex + dey + cpy #$f8 + bcs tlday4 + ldy #3 ;testing wraparound result + ldx #0 +tstay4 lda abst,y + cmp abs1,y + trap_ne ;store to abs data + txa + sta abst,y ;clear + dey + bpl tstay4 + + ldy #3+$f8 +tlday5 lda abs1-$f8,y ;no wrap on indexed abs + sta (inwt),y + dey + cpy #$f8 + bcs tlday5 + ldy #3 ;testing wraparound result + ldx #0 +tstay5 lda abst,y + cmp abs1,y + trap_ne ;store to abs data + txa + sta abst,y ;clear + dey + bpl tstay5 + + ldy #3+$f8 + ldx #6+$f8 +tlday6 lda (inw1),y ;no wrap on zp indirect indexed + sta (indt-$f8&$ff,x) + dex + dex + dey + cpy #$f8 + bcs tlday6 + ldy #3 ;testing wraparound result + ldx #0 +tstay6 lda abst,y + cmp abs1,y + trap_ne ;store to abs data + txa + sta abst,y ;clear + dey + bpl tstay6 + next_test + +; LDA / STA - zp / abs / # + set_stat 0 + lda zp1 + php ;test stores do not alter flags + eor #$c3 + plp + sta abst + php ;flags after load/store sequence + eor #$c3 + cmp #$c3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + lda zp1+1 + php ;test stores do not alter flags + eor #$c3 + plp + sta abst+1 + php ;flags after load/store sequence + eor #$c3 + cmp #$82 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + lda zp1+2 + php ;test stores do not alter flags + eor #$c3 + plp + sta abst+2 + php ;flags after load/store sequence + eor #$c3 + cmp #$41 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + lda zp1+3 + php ;test stores do not alter flags + eor #$c3 + plp + sta abst+3 + php ;flags after load/store sequence + eor #$c3 + cmp #0 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + set_stat $ff + lda zp1 + php ;test stores do not alter flags + eor #$c3 + plp + sta abst + php ;flags after load/store sequence + eor #$c3 + cmp #$c3 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + lda zp1+1 + php ;test stores do not alter flags + eor #$c3 + plp + sta abst+1 + php ;flags after load/store sequence + eor #$c3 + cmp #$82 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + lda zp1+2 + php ;test stores do not alter flags + eor #$c3 + plp + sta abst+2 + php ;flags after load/store sequence + eor #$c3 + cmp #$41 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + lda zp1+3 + php ;test stores do not alter flags + eor #$c3 + plp + sta abst+3 + php ;flags after load/store sequence + eor #$c3 + cmp #0 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + set_stat 0 + lda abs1 + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt + php ;flags after load/store sequence + eor #$c3 + cmp zp1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + lda abs1+1 + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt+1 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + lda abs1+2 + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt+2 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+2 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + lda abs1+3 + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt+3 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + set_stat $ff + lda abs1 + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt + php ;flags after load/store sequence + eor #$c3 + cmp zp1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + lda abs1+1 + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt+1 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + lda abs1+2 + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt+2 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+2 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + lda abs1+3 + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt+3 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+3 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + set_stat 0 + lda #$c3 + php + cmp abs1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + lda #$82 + php + cmp abs1+1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + lda #$41 + php + cmp abs1+2 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + lda #0 + php + cmp abs1+3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + + set_stat $ff + lda #$c3 + php + cmp abs1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + lda #$82 + php + cmp abs1+1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + lda #$41 + php + cmp abs1+2 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + lda #0 + php + cmp abs1+3 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + + ldx #0 + lda zpt + eor #$c3 + cmp zp1 + trap_ne ;store to zp data + stx zpt ;clear + lda abst + eor #$c3 + cmp abs1 + trap_ne ;store to abs data + stx abst ;clear + lda zpt+1 + eor #$c3 + cmp zp1+1 + trap_ne ;store to zp data + stx zpt+1 ;clear + lda abst+1 + eor #$c3 + cmp abs1+1 + trap_ne ;store to abs data + stx abst+1 ;clear + lda zpt+2 + eor #$c3 + cmp zp1+2 + trap_ne ;store to zp data + stx zpt+2 ;clear + lda abst+2 + eor #$c3 + cmp abs1+2 + trap_ne ;store to abs data + stx abst+2 ;clear + lda zpt+3 + eor #$c3 + cmp zp1+3 + trap_ne ;store to zp data + stx zpt+3 ;clear + lda abst+3 + eor #$c3 + cmp abs1+3 + trap_ne ;store to abs data + stx abst+3 ;clear + next_test + +; testing bit test & compares BIT CPX CPY CMP all addressing modes +; BIT - zp / abs + set_a $ff,0 + bit zp1+3 ;00 - should set Z / clear NV + tst_a $ff,fz + set_a 1,0 + bit zp1+2 ;41 - should set V (M6) / clear NZ + tst_a 1,fv + set_a 1,0 + bit zp1+1 ;82 - should set N (M7) & Z / clear V + tst_a 1,fnz + set_a 1,0 + bit zp1 ;c3 - should set N (M7) & V (M6) / clear Z + tst_a 1,fnv + + set_a $ff,$ff + bit zp1+3 ;00 - should set Z / clear NV + tst_a $ff,~fnv + set_a 1,$ff + bit zp1+2 ;41 - should set V (M6) / clear NZ + tst_a 1,~fnz + set_a 1,$ff + bit zp1+1 ;82 - should set N (M7) & Z / clear V + tst_a 1,~fv + set_a 1,$ff + bit zp1 ;c3 - should set N (M7) & V (M6) / clear Z + tst_a 1,~fz + + set_a $ff,0 + bit abs1+3 ;00 - should set Z / clear NV + tst_a $ff,fz + set_a 1,0 + bit abs1+2 ;41 - should set V (M6) / clear NZ + tst_a 1,fv + set_a 1,0 + bit abs1+1 ;82 - should set N (M7) & Z / clear V + tst_a 1,fnz + set_a 1,0 + bit abs1 ;c3 - should set N (M7) & V (M6) / clear Z + tst_a 1,fnv + + set_a $ff,$ff + bit abs1+3 ;00 - should set Z / clear NV + tst_a $ff,~fnv + set_a 1,$ff + bit abs1+2 ;41 - should set V (M6) / clear NZ + tst_a 1,~fnz + set_a 1,$ff + bit abs1+1 ;82 - should set N (M7) & Z / clear V + tst_a 1,~fv + set_a 1,$ff + bit abs1 ;c3 - should set N (M7) & V (M6) / clear Z + tst_a 1,~fz + next_test + +; CPX - zp / abs / # + set_x $80,0 + cpx zp7f + tst_stat fc + dex + cpx zp7f + tst_stat fzc + dex + cpx zp7f + tst_x $7e,fn + set_x $80,$ff + cpx zp7f + tst_stat ~fnz + dex + cpx zp7f + tst_stat ~fn + dex + cpx zp7f + tst_x $7e,~fzc + + set_x $80,0 + cpx abs7f + tst_stat fc + dex + cpx abs7f + tst_stat fzc + dex + cpx abs7f + tst_x $7e,fn + set_x $80,$ff + cpx abs7f + tst_stat ~fnz + dex + cpx abs7f + tst_stat ~fn + dex + cpx abs7f + tst_x $7e,~fzc + + set_x $80,0 + cpx #$7f + tst_stat fc + dex + cpx #$7f + tst_stat fzc + dex + cpx #$7f + tst_x $7e,fn + set_x $80,$ff + cpx #$7f + tst_stat ~fnz + dex + cpx #$7f + tst_stat ~fn + dex + cpx #$7f + tst_x $7e,~fzc + next_test + +; CPY - zp / abs / # + set_y $80,0 + cpy zp7f + tst_stat fc + dey + cpy zp7f + tst_stat fzc + dey + cpy zp7f + tst_y $7e,fn + set_y $80,$ff + cpy zp7f + tst_stat ~fnz + dey + cpy zp7f + tst_stat ~fn + dey + cpy zp7f + tst_y $7e,~fzc + + set_y $80,0 + cpy abs7f + tst_stat fc + dey + cpy abs7f + tst_stat fzc + dey + cpy abs7f + tst_y $7e,fn + set_y $80,$ff + cpy abs7f + tst_stat ~fnz + dey + cpy abs7f + tst_stat ~fn + dey + cpy abs7f + tst_y $7e,~fzc + + set_y $80,0 + cpy #$7f + tst_stat fc + dey + cpy #$7f + tst_stat fzc + dey + cpy #$7f + tst_y $7e,fn + set_y $80,$ff + cpy #$7f + tst_stat ~fnz + dey + cpy #$7f + tst_stat ~fn + dey + cpy #$7f + tst_y $7e,~fzc + next_test + +; CMP - zp / abs / # + set_a $80,0 + cmp zp7f + tst_a $80,fc + set_a $7f,0 + cmp zp7f + tst_a $7f,fzc + set_a $7e,0 + cmp zp7f + tst_a $7e,fn + set_a $80,$ff + cmp zp7f + tst_a $80,~fnz + set_a $7f,$ff + cmp zp7f + tst_a $7f,~fn + set_a $7e,$ff + cmp zp7f + tst_a $7e,~fzc + + set_a $80,0 + cmp abs7f + tst_a $80,fc + set_a $7f,0 + cmp abs7f + tst_a $7f,fzc + set_a $7e,0 + cmp abs7f + tst_a $7e,fn + set_a $80,$ff + cmp abs7f + tst_a $80,~fnz + set_a $7f,$ff + cmp abs7f + tst_a $7f,~fn + set_a $7e,$ff + cmp abs7f + tst_a $7e,~fzc + + set_a $80,0 + cmp #$7f + tst_a $80,fc + set_a $7f,0 + cmp #$7f + tst_a $7f,fzc + set_a $7e,0 + cmp #$7f + tst_a $7e,fn + set_a $80,$ff + cmp #$7f + tst_a $80,~fnz + set_a $7f,$ff + cmp #$7f + tst_a $7f,~fn + set_a $7e,$ff + cmp #$7f + tst_a $7e,~fzc + + ldx #4 ;with indexing by X + set_a $80,0 + cmp zp1,x + tst_a $80,fc + set_a $7f,0 + cmp zp1,x + tst_a $7f,fzc + set_a $7e,0 + cmp zp1,x + tst_a $7e,fn + set_a $80,$ff + cmp zp1,x + tst_a $80,~fnz + set_a $7f,$ff + cmp zp1,x + tst_a $7f,~fn + set_a $7e,$ff + cmp zp1,x + tst_a $7e,~fzc + + set_a $80,0 + cmp abs1,x + tst_a $80,fc + set_a $7f,0 + cmp abs1,x + tst_a $7f,fzc + set_a $7e,0 + cmp abs1,x + tst_a $7e,fn + set_a $80,$ff + cmp abs1,x + tst_a $80,~fnz + set_a $7f,$ff + cmp abs1,x + tst_a $7f,~fn + set_a $7e,$ff + cmp abs1,x + tst_a $7e,~fzc + + ldy #4 ;with indexing by Y + ldx #8 ;with indexed indirect + set_a $80,0 + cmp abs1,y + tst_a $80,fc + set_a $7f,0 + cmp abs1,y + tst_a $7f,fzc + set_a $7e,0 + cmp abs1,y + tst_a $7e,fn + set_a $80,$ff + cmp abs1,y + tst_a $80,~fnz + set_a $7f,$ff + cmp abs1,y + tst_a $7f,~fn + set_a $7e,$ff + cmp abs1,y + tst_a $7e,~fzc + + set_a $80,0 + cmp (ind1,x) + tst_a $80,fc + set_a $7f,0 + cmp (ind1,x) + tst_a $7f,fzc + set_a $7e,0 + cmp (ind1,x) + tst_a $7e,fn + set_a $80,$ff + cmp (ind1,x) + tst_a $80,~fnz + set_a $7f,$ff + cmp (ind1,x) + tst_a $7f,~fn + set_a $7e,$ff + cmp (ind1,x) + tst_a $7e,~fzc + + set_a $80,0 + cmp (ind1),y + tst_a $80,fc + set_a $7f,0 + cmp (ind1),y + tst_a $7f,fzc + set_a $7e,0 + cmp (ind1),y + tst_a $7e,fn + set_a $80,$ff + cmp (ind1),y + tst_a $80,~fnz + set_a $7f,$ff + cmp (ind1),y + tst_a $7f,~fn + set_a $7e,$ff + cmp (ind1),y + tst_a $7e,~fzc + next_test + +; testing shifts - ASL LSR ROL ROR all addressing modes +; shifts - accumulator + ldx #3 +tasl + set_ax zp1,0 + asl a + tst_ax rASL,fASL,0 + dex + bpl tasl + ldx #3 +tasl1 + set_ax zp1,$ff + asl a + tst_ax rASL,fASL,$ff-fnzc + dex + bpl tasl1 + + ldx #3 +tlsr + set_ax zp1,0 + lsr a + tst_ax rLSR,fLSR,0 + dex + bpl tlsr + ldx #3 +tlsr1 + set_ax zp1,$ff + lsr a + tst_ax rLSR,fLSR,$ff-fnzc + dex + bpl tlsr1 + + ldx #3 +trol + set_ax zp1,0 + rol a + tst_ax rROL,fROL,0 + dex + bpl trol + ldx #3 +trol1 + set_ax zp1,$ff-fc + rol a + tst_ax rROL,fROL,$ff-fnzc + dex + bpl trol1 + + ldx #3 +trolc + set_ax zp1,fc + rol a + tst_ax rROLc,fROLc,0 + dex + bpl trolc + ldx #3 +trolc1 + set_ax zp1,$ff + rol a + tst_ax rROLc,fROLc,$ff-fnzc + dex + bpl trolc1 + + ldx #3 +tror + set_ax zp1,0 + ror a + tst_ax rROR,fROR,0 + dex + bpl tror + ldx #3 +tror1 + set_ax zp1,$ff-fc + ror a + tst_ax rROR,fROR,$ff-fnzc + dex + bpl tror1 + + ldx #3 +trorc + set_ax zp1,fc + ror a + tst_ax rRORc,fRORc,0 + dex + bpl trorc + ldx #3 +trorc1 + set_ax zp1,$ff + ror a + tst_ax rRORc,fRORc,$ff-fnzc + dex + bpl trorc1 + next_test + +; shifts - zeropage + ldx #3 +tasl2 + set_z zp1,0 + asl zpt + tst_z rASL,fASL,0 + dex + bpl tasl2 + ldx #3 +tasl3 + set_z zp1,$ff + asl zpt + tst_z rASL,fASL,$ff-fnzc + dex + bpl tasl3 + + ldx #3 +tlsr2 + set_z zp1,0 + lsr zpt + tst_z rLSR,fLSR,0 + dex + bpl tlsr2 + ldx #3 +tlsr3 + set_z zp1,$ff + lsr zpt + tst_z rLSR,fLSR,$ff-fnzc + dex + bpl tlsr3 + + ldx #3 +trol2 + set_z zp1,0 + rol zpt + tst_z rROL,fROL,0 + dex + bpl trol2 + ldx #3 +trol3 + set_z zp1,$ff-fc + rol zpt + tst_z rROL,fROL,$ff-fnzc + dex + bpl trol3 + + ldx #3 +trolc2 + set_z zp1,fc + rol zpt + tst_z rROLc,fROLc,0 + dex + bpl trolc2 + ldx #3 +trolc3 + set_z zp1,$ff + rol zpt + tst_z rROLc,fROLc,$ff-fnzc + dex + bpl trolc3 + + ldx #3 +tror2 + set_z zp1,0 + ror zpt + tst_z rROR,fROR,0 + dex + bpl tror2 + ldx #3 +tror3 + set_z zp1,$ff-fc + ror zpt + tst_z rROR,fROR,$ff-fnzc + dex + bpl tror3 + + ldx #3 +trorc2 + set_z zp1,fc + ror zpt + tst_z rRORc,fRORc,0 + dex + bpl trorc2 + ldx #3 +trorc3 + set_z zp1,$ff + ror zpt + tst_z rRORc,fRORc,$ff-fnzc + dex + bpl trorc3 + next_test + +; shifts - absolute + ldx #3 +tasl4 + set_abs zp1,0 + asl abst + tst_abs rASL,fASL,0 + dex + bpl tasl4 + ldx #3 +tasl5 + set_abs zp1,$ff + asl abst + tst_abs rASL,fASL,$ff-fnzc + dex + bpl tasl5 + + ldx #3 +tlsr4 + set_abs zp1,0 + lsr abst + tst_abs rLSR,fLSR,0 + dex + bpl tlsr4 + ldx #3 +tlsr5 + set_abs zp1,$ff + lsr abst + tst_abs rLSR,fLSR,$ff-fnzc + dex + bpl tlsr5 + + ldx #3 +trol4 + set_abs zp1,0 + rol abst + tst_abs rROL,fROL,0 + dex + bpl trol4 + ldx #3 +trol5 + set_abs zp1,$ff-fc + rol abst + tst_abs rROL,fROL,$ff-fnzc + dex + bpl trol5 + + ldx #3 +trolc4 + set_abs zp1,fc + rol abst + tst_abs rROLc,fROLc,0 + dex + bpl trolc4 + ldx #3 +trolc5 + set_abs zp1,$ff + rol abst + tst_abs rROLc,fROLc,$ff-fnzc + dex + bpl trolc5 + + ldx #3 +tror4 + set_abs zp1,0 + ror abst + tst_abs rROR,fROR,0 + dex + bpl tror4 + ldx #3 +tror5 + set_abs zp1,$ff-fc + ror abst + tst_abs rROR,fROR,$ff-fnzc + dex + bpl tror5 + + ldx #3 +trorc4 + set_abs zp1,fc + ror abst + tst_abs rRORc,fRORc,0 + dex + bpl trorc4 + ldx #3 +trorc5 + set_abs zp1,$ff + ror abst + tst_abs rRORc,fRORc,$ff-fnzc + dex + bpl trorc5 + next_test + +; shifts - zp indexed + ldx #3 +tasl6 + set_zx zp1,0 + asl zpt,x + tst_zx rASL,fASL,0 + dex + bpl tasl6 + ldx #3 +tasl7 + set_zx zp1,$ff + asl zpt,x + tst_zx rASL,fASL,$ff-fnzc + dex + bpl tasl7 + + ldx #3 +tlsr6 + set_zx zp1,0 + lsr zpt,x + tst_zx rLSR,fLSR,0 + dex + bpl tlsr6 + ldx #3 +tlsr7 + set_zx zp1,$ff + lsr zpt,x + tst_zx rLSR,fLSR,$ff-fnzc + dex + bpl tlsr7 + + ldx #3 +trol6 + set_zx zp1,0 + rol zpt,x + tst_zx rROL,fROL,0 + dex + bpl trol6 + ldx #3 +trol7 + set_zx zp1,$ff-fc + rol zpt,x + tst_zx rROL,fROL,$ff-fnzc + dex + bpl trol7 + + ldx #3 +trolc6 + set_zx zp1,fc + rol zpt,x + tst_zx rROLc,fROLc,0 + dex + bpl trolc6 + ldx #3 +trolc7 + set_zx zp1,$ff + rol zpt,x + tst_zx rROLc,fROLc,$ff-fnzc + dex + bpl trolc7 + + ldx #3 +tror6 + set_zx zp1,0 + ror zpt,x + tst_zx rROR,fROR,0 + dex + bpl tror6 + ldx #3 +tror7 + set_zx zp1,$ff-fc + ror zpt,x + tst_zx rROR,fROR,$ff-fnzc + dex + bpl tror7 + + ldx #3 +trorc6 + set_zx zp1,fc + ror zpt,x + tst_zx rRORc,fRORc,0 + dex + bpl trorc6 + ldx #3 +trorc7 + set_zx zp1,$ff + ror zpt,x + tst_zx rRORc,fRORc,$ff-fnzc + dex + bpl trorc7 + next_test + +; shifts - abs indexed + ldx #3 +tasl8 + set_absx zp1,0 + asl abst,x + tst_absx rASL,fASL,0 + dex + bpl tasl8 + ldx #3 +tasl9 + set_absx zp1,$ff + asl abst,x + tst_absx rASL,fASL,$ff-fnzc + dex + bpl tasl9 + + ldx #3 +tlsr8 + set_absx zp1,0 + lsr abst,x + tst_absx rLSR,fLSR,0 + dex + bpl tlsr8 + ldx #3 +tlsr9 + set_absx zp1,$ff + lsr abst,x + tst_absx rLSR,fLSR,$ff-fnzc + dex + bpl tlsr9 + + ldx #3 +trol8 + set_absx zp1,0 + rol abst,x + tst_absx rROL,fROL,0 + dex + bpl trol8 + ldx #3 +trol9 + set_absx zp1,$ff-fc + rol abst,x + tst_absx rROL,fROL,$ff-fnzc + dex + bpl trol9 + + ldx #3 +trolc8 + set_absx zp1,fc + rol abst,x + tst_absx rROLc,fROLc,0 + dex + bpl trolc8 + ldx #3 +trolc9 + set_absx zp1,$ff + rol abst,x + tst_absx rROLc,fROLc,$ff-fnzc + dex + bpl trolc9 + + ldx #3 +tror8 + set_absx zp1,0 + ror abst,x + tst_absx rROR,fROR,0 + dex + bpl tror8 + ldx #3 +tror9 + set_absx zp1,$ff-fc + ror abst,x + tst_absx rROR,fROR,$ff-fnzc + dex + bpl tror9 + + ldx #3 +trorc8 + set_absx zp1,fc + ror abst,x + tst_absx rRORc,fRORc,0 + dex + bpl trorc8 + ldx #3 +trorc9 + set_absx zp1,$ff + ror abst,x + tst_absx rRORc,fRORc,$ff-fnzc + dex + bpl trorc9 + next_test + +; testing memory increment/decrement - INC DEC all addressing modes +; zeropage + ldx #0 + lda #$7e + sta zpt +tinc + set_stat 0 + inc zpt + tst_z rINC,fINC,0 + inx + cpx #2 + bne tinc1 + lda #$fe + sta zpt +tinc1 cpx #5 + bne tinc + dex + inc zpt +tdec + set_stat 0 + dec zpt + tst_z rINC,fINC,0 + dex + bmi tdec1 + cpx #1 + bne tdec + lda #$81 + sta zpt + bne tdec +tdec1 + ldx #0 + lda #$7e + sta zpt +tinc10 + set_stat $ff + inc zpt + tst_z rINC,fINC,$ff-fnz + inx + cpx #2 + bne tinc11 + lda #$fe + sta zpt +tinc11 cpx #5 + bne tinc10 + dex + inc zpt +tdec10 + set_stat $ff + dec zpt + tst_z rINC,fINC,$ff-fnz + dex + bmi tdec11 + cpx #1 + bne tdec10 + lda #$81 + sta zpt + bne tdec10 +tdec11 + next_test + +; absolute memory + ldx #0 + lda #$7e + sta abst +tinc2 + set_stat 0 + inc abst + tst_abs rINC,fINC,0 + inx + cpx #2 + bne tinc3 + lda #$fe + sta abst +tinc3 cpx #5 + bne tinc2 + dex + inc abst +tdec2 + set_stat 0 + dec abst + tst_abs rINC,fINC,0 + dex + bmi tdec3 + cpx #1 + bne tdec2 + lda #$81 + sta abst + bne tdec2 +tdec3 + ldx #0 + lda #$7e + sta abst +tinc12 + set_stat $ff + inc abst + tst_abs rINC,fINC,$ff-fnz + inx + cpx #2 + bne tinc13 + lda #$fe + sta abst +tinc13 cpx #5 + bne tinc12 + dex + inc abst +tdec12 + set_stat $ff + dec abst + tst_abs rINC,fINC,$ff-fnz + dex + bmi tdec13 + cpx #1 + bne tdec12 + lda #$81 + sta abst + bne tdec12 +tdec13 + next_test + +; zeropage indexed + ldx #0 + lda #$7e +tinc4 sta zpt,x + set_stat 0 + inc zpt,x + tst_zx rINC,fINC,0 + lda zpt,x + inx + cpx #2 + bne tinc5 + lda #$fe +tinc5 cpx #5 + bne tinc4 + dex + lda #2 +tdec4 sta zpt,x + set_stat 0 + dec zpt,x + tst_zx rINC,fINC,0 + lda zpt,x + dex + bmi tdec5 + cpx #1 + bne tdec4 + lda #$81 + bne tdec4 +tdec5 + ldx #0 + lda #$7e +tinc14 sta zpt,x + set_stat $ff + inc zpt,x + tst_zx rINC,fINC,$ff-fnz + lda zpt,x + inx + cpx #2 + bne tinc15 + lda #$fe +tinc15 cpx #5 + bne tinc14 + dex + lda #2 +tdec14 sta zpt,x + set_stat $ff + dec zpt,x + tst_zx rINC,fINC,$ff-fnz + lda zpt,x + dex + bmi tdec15 + cpx #1 + bne tdec14 + lda #$81 + bne tdec14 +tdec15 + next_test + +; memory indexed + ldx #0 + lda #$7e +tinc6 sta abst,x + set_stat 0 + inc abst,x + tst_absx rINC,fINC,0 + lda abst,x + inx + cpx #2 + bne tinc7 + lda #$fe +tinc7 cpx #5 + bne tinc6 + dex + lda #2 +tdec6 sta abst,x + set_stat 0 + dec abst,x + tst_absx rINC,fINC,0 + lda abst,x + dex + bmi tdec7 + cpx #1 + bne tdec6 + lda #$81 + bne tdec6 +tdec7 + ldx #0 + lda #$7e +tinc16 sta abst,x + set_stat $ff + inc abst,x + tst_absx rINC,fINC,$ff-fnz + lda abst,x + inx + cpx #2 + bne tinc17 + lda #$fe +tinc17 cpx #5 + bne tinc16 + dex + lda #2 +tdec16 sta abst,x + set_stat $ff + dec abst,x + tst_absx rINC,fINC,$ff-fnz + lda abst,x + dex + bmi tdec17 + cpx #1 + bne tdec16 + lda #$81 + bne tdec16 +tdec17 + next_test + +; testing logical instructions - AND EOR ORA all addressing modes +; AND + ldx #3 ;immediate +tand lda zpAN,x + sta ex_andi+1 ;set AND # operand + set_ax absANa,0 + jsr ex_andi ;execute AND # in RAM + tst_ax absrlo,absflo,0 + dex + bpl tand + ldx #3 +tand1 lda zpAN,x + sta ex_andi+1 ;set AND # operand + set_ax absANa,$ff + jsr ex_andi ;execute AND # in RAM + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tand1 + + ldx #3 ;zp +tand2 lda zpAN,x + sta zpt + set_ax absANa,0 + and zpt + tst_ax absrlo,absflo,0 + dex + bpl tand2 + ldx #3 +tand3 lda zpAN,x + sta zpt + set_ax absANa,$ff + and zpt + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tand3 + + ldx #3 ;abs +tand4 lda zpAN,x + sta abst + set_ax absANa,0 + and abst + tst_ax absrlo,absflo,0 + dex + bpl tand4 + ldx #3 +tand5 lda zpAN,x + sta abst + set_ax absANa,$ff + and abst + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tand6 + + ldx #3 ;zp,x +tand6 + set_ax absANa,0 + and zpAN,x + tst_ax absrlo,absflo,0 + dex + bpl tand6 + ldx #3 +tand7 + set_ax absANa,$ff + and zpAN,x + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tand7 + + ldx #3 ;abs,x +tand8 + set_ax absANa,0 + and absAN,x + tst_ax absrlo,absflo,0 + dex + bpl tand8 + ldx #3 +tand9 + set_ax absANa,$ff + and absAN,x + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tand9 + + ldy #3 ;abs,y +tand10 + set_ay absANa,0 + and absAN,y + tst_ay absrlo,absflo,0 + dey + bpl tand10 + ldy #3 +tand11 + set_ay absANa,$ff + and absAN,y + tst_ay absrlo,absflo,$ff-fnz + dey + bpl tand11 + + ldx #6 ;(zp,x) + ldy #3 +tand12 + set_ay absANa,0 + and (indAN,x) + tst_ay absrlo,absflo,0 + dex + dex + dey + bpl tand12 + ldx #6 + ldy #3 +tand13 + set_ay absANa,$ff + and (indAN,x) + tst_ay absrlo,absflo,$ff-fnz + dex + dex + dey + bpl tand13 + + ldy #3 ;(zp),y +tand14 + set_ay absANa,0 + and (indAN),y + tst_ay absrlo,absflo,0 + dey + bpl tand14 + ldy #3 +tand15 + set_ay absANa,$ff + and (indAN),y + tst_ay absrlo,absflo,$ff-fnz + dey + bpl tand15 + next_test + +; EOR + ldx #3 ;immediate - self modifying code +teor lda zpEO,x + sta ex_eori+1 ;set EOR # operand + set_ax absEOa,0 + jsr ex_eori ;execute EOR # in RAM + tst_ax absrlo,absflo,0 + dex + bpl teor + ldx #3 +teor1 lda zpEO,x + sta ex_eori+1 ;set EOR # operand + set_ax absEOa,$ff + jsr ex_eori ;execute EOR # in RAM + tst_ax absrlo,absflo,$ff-fnz + dex + bpl teor1 + + ldx #3 ;zp +teor2 lda zpEO,x + sta zpt + set_ax absEOa,0 + eor zpt + tst_ax absrlo,absflo,0 + dex + bpl teor2 + ldx #3 +teor3 lda zpEO,x + sta zpt + set_ax absEOa,$ff + eor zpt + tst_ax absrlo,absflo,$ff-fnz + dex + bpl teor3 + + ldx #3 ;abs +teor4 lda zpEO,x + sta abst + set_ax absEOa,0 + eor abst + tst_ax absrlo,absflo,0 + dex + bpl teor4 + ldx #3 +teor5 lda zpEO,x + sta abst + set_ax absEOa,$ff + eor abst + tst_ax absrlo,absflo,$ff-fnz + dex + bpl teor6 + + ldx #3 ;zp,x +teor6 + set_ax absEOa,0 + eor zpEO,x + tst_ax absrlo,absflo,0 + dex + bpl teor6 + ldx #3 +teor7 + set_ax absEOa,$ff + eor zpEO,x + tst_ax absrlo,absflo,$ff-fnz + dex + bpl teor7 + + ldx #3 ;abs,x +teor8 + set_ax absEOa,0 + eor absEO,x + tst_ax absrlo,absflo,0 + dex + bpl teor8 + ldx #3 +teor9 + set_ax absEOa,$ff + eor absEO,x + tst_ax absrlo,absflo,$ff-fnz + dex + bpl teor9 + + ldy #3 ;abs,y +teor10 + set_ay absEOa,0 + eor absEO,y + tst_ay absrlo,absflo,0 + dey + bpl teor10 + ldy #3 +teor11 + set_ay absEOa,$ff + eor absEO,y + tst_ay absrlo,absflo,$ff-fnz + dey + bpl teor11 + + ldx #6 ;(zp,x) + ldy #3 +teor12 + set_ay absEOa,0 + eor (indEO,x) + tst_ay absrlo,absflo,0 + dex + dex + dey + bpl teor12 + ldx #6 + ldy #3 +teor13 + set_ay absEOa,$ff + eor (indEO,x) + tst_ay absrlo,absflo,$ff-fnz + dex + dex + dey + bpl teor13 + + ldy #3 ;(zp),y +teor14 + set_ay absEOa,0 + eor (indEO),y + tst_ay absrlo,absflo,0 + dey + bpl teor14 + ldy #3 +teor15 + set_ay absEOa,$ff + eor (indEO),y + tst_ay absrlo,absflo,$ff-fnz + dey + bpl teor15 + next_test + +; OR + ldx #3 ;immediate - self modifying code +tora lda zpOR,x + sta ex_orai+1 ;set ORA # operand + set_ax absORa,0 + jsr ex_orai ;execute ORA # in RAM + tst_ax absrlo,absflo,0 + dex + bpl tora + ldx #3 +tora1 lda zpOR,x + sta ex_orai+1 ;set ORA # operand + set_ax absORa,$ff + jsr ex_orai ;execute ORA # in RAM + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tora1 + + ldx #3 ;zp +tora2 lda zpOR,x + sta zpt + set_ax absORa,0 + ora zpt + tst_ax absrlo,absflo,0 + dex + bpl tora2 + ldx #3 +tora3 lda zpOR,x + sta zpt + set_ax absORa,$ff + ora zpt + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tora3 + + ldx #3 ;abs +tora4 lda zpOR,x + sta abst + set_ax absORa,0 + ora abst + tst_ax absrlo,absflo,0 + dex + bpl tora4 + ldx #3 +tora5 lda zpOR,x + sta abst + set_ax absORa,$ff + ora abst + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tora6 + + ldx #3 ;zp,x +tora6 + set_ax absORa,0 + ora zpOR,x + tst_ax absrlo,absflo,0 + dex + bpl tora6 + ldx #3 +tora7 + set_ax absORa,$ff + ora zpOR,x + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tora7 + + ldx #3 ;abs,x +tora8 + set_ax absORa,0 + ora absOR,x + tst_ax absrlo,absflo,0 + dex + bpl tora8 + ldx #3 +tora9 + set_ax absORa,$ff + ora absOR,x + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tora9 + + ldy #3 ;abs,y +tora10 + set_ay absORa,0 + ora absOR,y + tst_ay absrlo,absflo,0 + dey + bpl tora10 + ldy #3 +tora11 + set_ay absORa,$ff + ora absOR,y + tst_ay absrlo,absflo,$ff-fnz + dey + bpl tora11 + + ldx #6 ;(zp,x) + ldy #3 +tora12 + set_ay absORa,0 + ora (indOR,x) + tst_ay absrlo,absflo,0 + dex + dex + dey + bpl tora12 + ldx #6 + ldy #3 +tora13 + set_ay absORa,$ff + ora (indOR,x) + tst_ay absrlo,absflo,$ff-fnz + dex + dex + dey + bpl tora13 + + ldy #3 ;(zp),y +tora14 + set_ay absORa,0 + ora (indOR),y + tst_ay absrlo,absflo,0 + dey + bpl tora14 + ldy #3 +tora15 + set_ay absORa,$ff + ora (indOR),y + tst_ay absrlo,absflo,$ff-fnz + dey + bpl tora15 + if I_flag = 3 + cli + endif + next_test + +; full binary add/subtract test +; iterates through all combinations of operands and carry input +; uses increments/decrements to predict result & result flags + cld + ldx #ad2 ;for indexed test + ldy #$ff ;max range + lda #0 ;start with adding zeroes & no carry + sta adfc ;carry in - for diag + sta ad1 ;operand 1 - accumulator + sta ad2 ;operand 2 - memory or immediate + sta ada2 ;non zp + sta adrl ;expected result bits 0-7 + sta adrh ;expected result bit 8 (carry out) + lda #$ff ;complemented operand 2 for subtract + sta sb2 + sta sba2 ;non zp + lda #2 ;expected Z-flag + sta adrf +tadd clc ;test with carry clear + jsr chkadd + inc adfc ;now with carry + inc adrl ;result +1 + php ;save N & Z from low result + php + pla ;accu holds expected flags + and #$82 ;mask N & Z + plp + bne tadd1 + inc adrh ;result bit 8 - carry +tadd1 ora adrh ;merge C to expected flags + sta adrf ;save expected flags except overflow + sec ;test with carry set + jsr chkadd + dec adfc ;same for operand +1 but no carry + inc ad1 + bne tadd ;iterate op1 + lda #0 ;preset result to op2 when op1 = 0 + sta adrh + inc ada2 + inc ad2 + php ;save NZ as operand 2 becomes the new result + pla + and #$82 ;mask N00000Z0 + sta adrf ;no need to check carry as we are adding to 0 + dec sb2 ;complement subtract operand 2 + dec sba2 + lda ad2 + sta adrl + bne tadd ;iterate op2 + if disable_decimal < 1 + next_test + +; decimal add/subtract test +; *** WARNING - tests documented behavior only! *** +; only valid BCD operands are tested, N V Z flags are ignored +; iterates through all valid combinations of operands and carry input +; uses increments/decrements to predict result & carry flag + sed + ldx #ad2 ;for indexed test + ldy #$ff ;max range + lda #$99 ;start with adding 99 to 99 with carry + sta ad1 ;operand 1 - accumulator + sta ad2 ;operand 2 - memory or immediate + sta ada2 ;non zp + sta adrl ;expected result bits 0-7 + lda #1 ;set carry in & out + sta adfc ;carry in - for diag + sta adrh ;expected result bit 8 (carry out) + lda #0 ;complemented operand 2 for subtract + sta sb2 + sta sba2 ;non zp +tdad sec ;test with carry set + jsr chkdad + dec adfc ;now with carry clear + lda adrl ;decimal adjust result + bne tdad1 ;skip clear carry & preset result 99 (9A-1) + dec adrh + lda #$99 + sta adrl + bne tdad3 +tdad1 and #$f ;lower nibble mask + bne tdad2 ;no decimal adjust needed + dec adrl ;decimal adjust (?0-6) + dec adrl + dec adrl + dec adrl + dec adrl + dec adrl +tdad2 dec adrl ;result -1 +tdad3 clc ;test with carry clear + jsr chkdad + inc adfc ;same for operand -1 but with carry + lda ad1 ;decimal adjust operand 1 + beq tdad5 ;iterate operand 2 + and #$f ;lower nibble mask + bne tdad4 ;skip decimal adjust + dec ad1 ;decimal adjust (?0-6) + dec ad1 + dec ad1 + dec ad1 + dec ad1 + dec ad1 +tdad4 dec ad1 ;operand 1 -1 + jmp tdad ;iterate op1 + +tdad5 lda #$99 ;precharge op1 max + sta ad1 + lda ad2 ;decimal adjust operand 2 + beq tdad7 ;end of iteration + and #$f ;lower nibble mask + bne tdad6 ;skip decimal adjust + dec ad2 ;decimal adjust (?0-6) + dec ad2 + dec ad2 + dec ad2 + dec ad2 + dec ad2 + inc sb2 ;complemented decimal adjust for subtract (?9+6) + inc sb2 + inc sb2 + inc sb2 + inc sb2 + inc sb2 +tdad6 dec ad2 ;operand 2 -1 + inc sb2 ;complemented operand for subtract + lda sb2 + sta sba2 ;copy as non zp operand + lda ad2 + sta ada2 ;copy as non zp operand + sta adrl ;new result since op1+carry=00+carry +op2=op2 + inc adrh ;result carry + bne tdad ;iterate op2 +tdad7 + next_test + +; decimal/binary switch test +; tests CLD, SED, PLP, RTI to properly switch between decimal & binary opcode +; tables + clc + cld + php + lda #$55 + adc #$55 + cmp #$aa + trap_ne ;expected binary result after cld + clc + sed + php + lda #$55 + adc #$55 + cmp #$10 + trap_ne ;expected decimal result after sed + cld + plp + lda #$55 + adc #$55 + cmp #$10 + trap_ne ;expected decimal result after plp D=1 + plp + lda #$55 + adc #$55 + cmp #$aa + trap_ne ;expected binary result after plp D=0 + clc + lda #hi bin_rti_ret ;emulated interrupt for rti + pha + lda #lo bin_rti_ret + pha + php + sed + lda #hi dec_rti_ret ;emulated interrupt for rti + pha + lda #lo dec_rti_ret + pha + php + cld + rti +dec_rti_ret + lda #$55 + adc #$55 + cmp #$10 + trap_ne ;expected decimal result after rti D=1 + rti +bin_rti_ret + lda #$55 + adc #$55 + cmp #$aa + trap_ne ;expected binary result after rti D=0 + endif + + lda test_case + cmp #test_num + trap_ne ;previous test is out of sequence + lda #$f0 ;mark opcode testing complete + sta test_case + +; final RAM integrity test +; verifies that none of the previous tests has altered RAM outside of the +; designated write areas. + check_ram +; *** DEBUG INFO *** +; to debug checksum errors uncomment check_ram in the next_test macro to +; narrow down the responsible opcode. +; may give false errors when monitor, OS or other background activity is +; allowed during previous tests. + + +; S U C C E S S ************************************************ +; ------------- + success ;if you get here everything went well +; ------------- +; S U C C E S S ************************************************ + jmp start ;run again + + if disable_decimal < 1 +; core subroutine of the decimal add/subtract test +; *** WARNING - tests documented behavior only! *** +; only valid BCD operands are tested, N V Z flags are ignored +; iterates through all valid combinations of operands and carry input +; uses increments/decrements to predict result & carry flag +chkdad +; decimal ADC / SBC zp + php ;save carry for subtract + lda ad1 + adc ad2 ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + php ;save carry for next add + lda ad1 + sbc sb2 ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad flags + plp +; decimal ADC / SBC abs + php ;save carry for subtract + lda ad1 + adc ada2 ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + php ;save carry for next add + lda ad1 + sbc sba2 ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp +; decimal ADC / SBC # + php ;save carry for subtract + lda ad2 + sta ex_adci+1 ;set ADC # operand + lda ad1 + jsr ex_adci ;execute ADC # in RAM + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + php ;save carry for next add + lda sb2 + sta ex_sbci+1 ;set SBC # operand + lda ad1 + jsr ex_sbci ;execute SBC # in RAM + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp +; decimal ADC / SBC zp,x + php ;save carry for subtract + lda ad1 + adc 0,x ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + php ;save carry for next add + lda ad1 + sbc sb2-ad2,x ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp +; decimal ADC / SBC abs,x + php ;save carry for subtract + lda ad1 + adc ada2-ad2,x ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + php ;save carry for next add + lda ad1 + sbc sba2-ad2,x ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp +; decimal ADC / SBC abs,y + php ;save carry for subtract + lda ad1 + adc ada2-$ff,y ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + php ;save carry for next add + lda ad1 + sbc sba2-$ff,y ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp +; decimal ADC / SBC (zp,x) + php ;save carry for subtract + lda ad1 + adc (lo adi2-ad2,x) ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + php ;save carry for next add + lda ad1 + sbc (lo sbi2-ad2,x) ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp +; decimal ADC / SBC (abs),y + php ;save carry for subtract + lda ad1 + adc (adiy2),y ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + php ;save carry for next add + lda ad1 + sbc (sbiy2),y ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + rts + endif + +; core subroutine of the full binary add/subtract test +; iterates through all combinations of operands and carry input +; uses increments/decrements to predict result & result flags +chkadd lda adrf ;add V-flag if overflow + and #$83 ;keep N-----ZC / clear V + pha + lda ad1 ;test sign unequal between operands + eor ad2 + bmi ckad1 ;no overflow possible - operands have different sign + lda ad1 ;test sign equal between operands and result + eor adrl + bpl ckad1 ;no overflow occured - operand and result have same sign + pla + ora #$40 ;set V + pha +ckad1 pla + sta adrf ;save expected flags +; binary ADC / SBC zp + php ;save carry for subtract + lda ad1 + adc ad2 ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc sb2 ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp +; binary ADC / SBC abs + php ;save carry for subtract + lda ad1 + adc ada2 ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc sba2 ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp +; binary ADC / SBC # + php ;save carry for subtract + lda ad2 + sta ex_adci+1 ;set ADC # operand + lda ad1 + jsr ex_adci ;execute ADC # in RAM + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda sb2 + sta ex_sbci+1 ;set SBC # operand + lda ad1 + jsr ex_sbci ;execute SBC # in RAM + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp +; binary ADC / SBC zp,x + php ;save carry for subtract + lda ad1 + adc 0,x ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc sb2-ad2,x ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp +; binary ADC / SBC abs,x + php ;save carry for subtract + lda ad1 + adc ada2-ad2,x ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc sba2-ad2,x ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp +; binary ADC / SBC abs,y + php ;save carry for subtract + lda ad1 + adc ada2-$ff,y ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc sba2-$ff,y ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp +; binary ADC / SBC (zp,x) + php ;save carry for subtract + lda ad1 + adc (lo adi2-ad2,x) ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc (lo sbi2-ad2,x) ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp +; binary ADC / SBC (abs),y + php ;save carry for subtract + lda ad1 + adc (adiy2),y ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc (sbiy2),y ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + rts + +; target for the jump absolute test + dey + dey +test_far + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + plp + trap_cs ;flags loaded? + trap_vs + trap_mi + trap_eq + cmp #'F' ;registers loaded? + trap_ne + cpx #'A' + trap_ne + cpy #('R'-3) + trap_ne + pha ;save a,x + txa + pha + tsx + cpx #$fd ;check SP + trap_ne + pla ;restore x + tax + set_stat $ff + pla ;restore a + inx ;return registers with modifications + eor #$aa ;N=1, V=1, Z=0, C=1 + jmp far_ret + +; target for the jump indirect test + align +ptr_tst_ind dw test_ind +ptr_ind_ret dw ind_ret + trap ;runover protection + dey + dey +test_ind + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + plp + trap_cs ;flags loaded? + trap_vs + trap_mi + trap_eq + cmp #'I' ;registers loaded? + trap_ne + cpx #'N' + trap_ne + cpy #('D'-3) + trap_ne + pha ;save a,x + txa + pha + tsx + cpx #$fd ;check SP + trap_ne + pla ;restore x + tax + set_stat $ff + pla ;restore a + inx ;return registers with modifications + eor #$aa ;N=1, V=1, Z=0, C=1 + jmp (ptr_ind_ret) + trap ;runover protection + jmp start ;catastrophic error - cannot continue + +; target for the jump subroutine test + dey + dey +test_jsr + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + plp + trap_cs ;flags loaded? + trap_vs + trap_mi + trap_eq + cmp #'J' ;registers loaded? + trap_ne + cpx #'S' + trap_ne + cpy #('R'-3) + trap_ne + pha ;save a,x + txa + pha + tsx ;sp -4? (return addr,a,x) + cpx #$fb + trap_ne + lda $1ff ;propper return on stack + cmp #hi(jsr_ret) + trap_ne + lda $1fe + cmp #lo(jsr_ret) + trap_ne + set_stat $ff + pla ;pull x,a + tax + pla + inx ;return registers with modifications + eor #$aa ;N=1, V=1, Z=0, C=1 + rts + trap ;runover protection + jmp start ;catastrophic error - cannot continue + +;trap in case of unexpected IRQ, NMI, BRK, RESET - BRK test target +nmi_trap + trap ;check stack for conditions at NMI + jmp start ;catastrophic error - cannot continue +res_trap + trap ;unexpected RESET + jmp start ;catastrophic error - cannot continue + + dey + dey +irq_trap ;BRK test or unextpected BRK or IRQ + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + ;next traps could be caused by unexpected BRK or IRQ + ;check stack for BREAK and originating location + ;possible jump/branch into weeds (uninitialized space) + cmp #$ff-'B' ;BRK pass 2 registers loaded? + beq break2 + cmp #'B' ;BRK pass 1 registers loaded? + trap_ne + cpx #'R' + trap_ne + cpy #'K'-3 + trap_ne + sta irq_a ;save registers during break test + stx irq_x + tsx ;test break on stack + lda $102,x + cmp_flag 0 ;break test should have B=1 & unused=1 on stack + trap_ne ; - no break flag on stack + pla + cmp_flag intdis ;should have added interrupt disable + trap_ne + tsx + cpx #$fc ;sp -3? (return addr, flags) + trap_ne + lda $1ff ;propper return on stack + cmp #hi(brk_ret0) + trap_ne + lda $1fe + cmp #lo(brk_ret0) + trap_ne + load_flag $ff + pha + ldx irq_x + inx ;return registers with modifications + lda irq_a + eor #$aa + plp ;N=1, V=1, Z=1, C=1 but original flags should be restored + rti + trap ;runover protection + jmp start ;catastrophic error - cannot continue + +break2 ;BRK pass 2 + cpx #$ff-'R' + trap_ne + cpy #$ff-'K'-3 + trap_ne + sta irq_a ;save registers during break test + stx irq_x + tsx ;test break on stack + lda $102,x + cmp_flag $ff ;break test should have B=1 + trap_ne ; - no break flag on stack + pla + ora #decmode ;ignore decmode cleared if 65c02 + cmp_flag $ff ;actual passed flags + trap_ne + tsx + cpx #$fc ;sp -3? (return addr, flags) + trap_ne + lda $1ff ;propper return on stack + cmp #hi(brk_ret1) + trap_ne + lda $1fe + cmp #lo(brk_ret1) + trap_ne + load_flag intdis + pha + ldx irq_x + inx ;return registers with modifications + lda irq_a + eor #$aa + plp ;N=0, V=0, Z=0, C=0 but original flags should be restored + rti + trap ;runover protection + jmp start ;catastrophic error - cannot continue + + if report = 1 + include "report.i65" + endif + +;copy of data to initialize BSS segment + if load_data_direct != 1 +zp_init +zp1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR +zp7f_ db $7f ;test pattern for compare +;logical zeropage operands +zpOR_ db 0,$1f,$71,$80 ;test pattern for OR +zpAN_ db $0f,$ff,$7f,$80 ;test pattern for AND +zpEO_ db $ff,$0f,$8f,$8f ;test pattern for EOR +;indirect addressing pointers +ind1_ dw abs1 ;indirect pointer to pattern in absolute memory + dw abs1+1 + dw abs1+2 + dw abs1+3 + dw abs7f +inw1_ dw abs1-$f8 ;indirect pointer for wrap-test pattern +indt_ dw abst ;indirect pointer to store area in absolute memory + dw abst+1 + dw abst+2 + dw abst+3 +inwt_ dw abst-$f8 ;indirect pointer for wrap-test store +indAN_ dw absAN ;indirect pointer to AND pattern in absolute memory + dw absAN+1 + dw absAN+2 + dw absAN+3 +indEO_ dw absEO ;indirect pointer to EOR pattern in absolute memory + dw absEO+1 + dw absEO+2 + dw absEO+3 +indOR_ dw absOR ;indirect pointer to OR pattern in absolute memory + dw absOR+1 + dw absOR+2 + dw absOR+3 +;add/subtract indirect pointers +adi2_ dw ada2 ;indirect pointer to operand 2 in absolute memory +sbi2_ dw sba2 ;indirect pointer to complemented operand 2 (SBC) +adiy2_ dw ada2-$ff ;with offset for indirect indexed +sbiy2_ dw sba2-$ff +zp_end + if (zp_end - zp_init) != (zp_bss_end - zp_bss) + ;force assembler error if size is different + ERROR ERROR ERROR ;mismatch between bss and zeropage data + endif +data_init +ex_and_ and #0 ;execute immediate opcodes + rts +ex_eor_ eor #0 ;execute immediate opcodes + rts +ex_ora_ ora #0 ;execute immediate opcodes + rts +ex_adc_ adc #0 ;execute immediate opcodes + rts +ex_sbc_ sbc #0 ;execute immediate opcodes + rts +abs1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR +abs7f_ db $7f ;test pattern for compare +;loads +fLDx_ db fn,fn,0,fz ;expected flags for load +;shifts +rASL_ ;expected result ASL & ROL -carry +rROL_ db $86,$04,$82,0 ; " +rROLc_ db $87,$05,$83,1 ;expected result ROL +carry +rLSR_ ;expected result LSR & ROR -carry +rROR_ db $61,$41,$20,0 ; " +rRORc_ db $e1,$c1,$a0,$80 ;expected result ROR +carry +fASL_ ;expected flags for shifts +fROL_ db fnc,fc,fn,fz ;no carry in +fROLc_ db fnc,fc,fn,0 ;carry in +fLSR_ +fROR_ db fc,0,fc,fz ;no carry in +fRORc_ db fnc,fn,fnc,fn ;carry in +;increments (decrements) +rINC_ db $7f,$80,$ff,0,1 ;expected result for INC/DEC +fINC_ db 0,fn,fn,fz,0 ;expected flags for INC/DEC +;logical memory operand +absOR_ db 0,$1f,$71,$80 ;test pattern for OR +absAN_ db $0f,$ff,$7f,$80 ;test pattern for AND +absEO_ db $ff,$0f,$8f,$8f ;test pattern for EOR +;logical accu operand +absORa_ db 0,$f1,$1f,0 ;test pattern for OR +absANa_ db $f0,$ff,$ff,$ff ;test pattern for AND +absEOa_ db $ff,$f0,$f0,$0f ;test pattern for EOR +;logical results +absrlo_ db 0,$ff,$7f,$80 +absflo_ db fz,fn,0,fn +data_end + if (data_end - data_init) != (data_bss_end - data_bss) + ;force assembler error if size is different + ERROR ERROR ERROR ;mismatch between bss and data + endif + +vec_init + dw nmi_trap +; dw res_trap + dw start + dw irq_trap +vec_bss equ $fffa + endif ;end of RAM init data + + if (load_data_direct = 1) & (ROM_vectors = 1) + org $fffa ;vectors + dw nmi_trap +; dw res_trap + dw start + dw irq_trap + endif + + end start + \ No newline at end of file Index: cpu65c02_true_cycle/trunk/released/asm/6502_interrupt_test.a65 =================================================================== --- cpu65c02_true_cycle/trunk/released/asm/6502_interrupt_test.a65 (nonexistent) +++ cpu65c02_true_cycle/trunk/released/asm/6502_interrupt_test.a65 (revision 23) @@ -0,0 +1,1029 @@ +; +; 6 5 0 2 I N T E R R U P T T E S T +; +; Copyright (C) 2013 Klaus Dormann +; +; This program is free software: you can redistribute it and/or modify +; it under the terms of the GNU General Public License as published by +; the Free Software Foundation, either version 3 of the License, or +; (at your option) any later version. +; +; This program is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program. If not, see . + + +; This program is designed to test IRQ and NMI of a 6502 emulator. It requires +; an internal or external feedback register to the IRQ & NMI inputs +; +; version 15-aug-2014 +; contact info at http://2m5.de or email K@2m5.de +; +; assembled with AS65 from http://www.kingswood-consulting.co.uk/assemblers/ +; command line switches: -l -m -s2 -w -h0 +; | | | | no page headers in listing +; | | | wide listing (133 char/col) +; | | write intel hex file instead of binary +; | expand macros in listing +; generate pass2 listing +; +; No IO - should be run from a monitor with access to registers. +; To run load intel hex image with a load command, than alter PC to 400 hex and +; enter a go command. +; Loop on program counter determines error or successful completion of test. +; Check listing for relevant traps (jump/branch *). +; +; Debugging hints: +; Most of the code is written sequentially. if you hit a trap, check the +; immediately preceeding code for the instruction to be tested. Results are +; tested first, flags are checked second by pushing them onto the stack and +; pulling them to the accumulator after the result was checked. The "real" +; flags are no longer valid for the tested instruction at this time! +; If the tested instruction was indexed, the relevant index (X or Y) must +; also be checked. Opposed to the flags, X and Y registers are still valid. +; +; versions: +; 19-jul-2013 1st version distributed for testing +; 16-aug-2013 added error report to standard output option +; 15-aug-2014 added filter to feedback (bit 7 will cause diag stop in emu) + + +; C O N F I G U R A T I O N +; +;ROM_vectors MUST be writable & the I_flag MUST be alterable + +;load_data_direct (0=move from code segment, 1=load directly) +;loading directly is preferred but may not be supported by your platform +;0 produces only consecutive object code, 1 is not suitable for a binary image +load_data_direct = 1 + +;NMI & IRQ are tested with a feedback register +;emulators diag register - set i_drive = 0 for a latch (74HC573) +I_port = $bffc ;feedback port address +I_ddr = 0 ;feedback DDR address, 0 = no DDR +I_drive = 1 ;0 = totem pole, 1 = open collector +IRQ_bit = 0 ;bit number of feedback to IRQ +NMI_bit = 1 ;bit number of feedback to NMI, -1 if not available +I_filter = $7f ;filtering bit 7 = diag stop + +;typical IO chip port B - set i_drive = 0 to avoid pullup resistors +;I_port = $bfb2 ;feedback port address +;I_ddr = $bfb3 ;feedback DDR address, 0 = no DDR +;I_drive = 1 ;0 = totem pole, 1 = open collector +;IRQ_bit = 0 ;bit number of feedback to IRQ +;NMI_bit = 1 ;bit number of feedback to NMI, -1 if not available +;I_filter = $ff ;no bits filtered + +;decimal mode flag during IRQ, NMI & BRK +;D_clear = 0 ;0 = not cleared (NMOS), 1 = cleared (CMOS) +D_clear = 1 ;0 = not cleared (NMOS), 1 = cleared (CMOS) + +;configure memory - try to stay away from memory used by the system +;zero_page memory start address, 6 consecutive Bytes required +zero_page = $a + +;data_segment memory start address, 4 consecutive Bytes required +data_segment = $200 + +;code_segment memory start address +code_segment = $400 + +;report errors through I/O channel (0=use standard self trap loops, 1=include +;report.i65 as I/O channel) +report = 0 + + noopt ;do not take shortcuts + +;macros for error & success traps to allow user modification +;example: +;trap macro +; jsr my_error_handler +; endm +;trap_eq macro +; bne skip\? +; trap ;failed equal (zero) +;skip\? +; endm +; +; my_error_handler should pop the calling address from the stack and report it. +; putting larger portions of code (more than 3 bytes) inside the trap macro +; may lead to branch range problems for some tests. + if report = 0 +trap macro + jmp * ;failed anyway + endm +trap_eq macro + beq * ;failed equal (zero) + endm +trap_ne macro + bne * ;failed not equal (non zero) + endm +; please observe that during the test the stack gets invalidated +; therefore a RTS inside the success macro is not possible +success macro + jmp * ;test passed, no errors + endm + endif + if report = 1 +trap macro + jsr report_error + endm +trap_eq macro + bne skip\? + trap ;failed equal (zero) +skip\? + endm +trap_ne macro + beq skip\? + trap ;failed not equal (non zero) +skip\? + endm +; please observe that during the test the stack gets invalidated +; therefore a RTS inside the success macro is not possible +success macro + jsr report_success + endm + endif + + +carry equ %00000001 ;flag bits in status +zero equ %00000010 +intdis equ %00000100 +decmode equ %00001000 +break equ %00010000 +reserv equ %00100000 +overfl equ %01000000 +minus equ %10000000 + +fc equ carry +fz equ zero +fzc equ carry+zero +fv equ overfl +fvz equ overfl+zero +fn equ minus +fnc equ minus+carry +fnz equ minus+zero +fnzc equ minus+zero+carry +fnv equ minus+overfl + +fao equ break+reserv ;bits always on after PHP, BRK +fai equ fao+intdis ;+ forced interrupt disable +m8 equ $ff ;8 bit mask +m8i equ $ff&~intdis ;8 bit mask - interrupt disable + +;macros to set status +push_stat macro ;setting flags in the processor status register + lda #\1 + pha ;use stack to load status + endm + +set_stat macro ;setting flags in the processor status register + lda #\1 + pha ;use stack to load status + plp + endm + + if load_data_direct = 1 + data + else + bss ;uninitialized segment, copy of data at end of code! + endif + org zero_page +;BRK, IRQ, NMI test interrupt save +zpt +irq_a ds 1 ;a register +irq_x ds 1 ;x register +irq_f ds 1 ;flags +nmi_a ds 1 ;a register +nmi_x ds 1 ;x register +nmi_f ds 1 ;flags +zp_bss + +;fixed stack locations +lst_f equ $1fe ;last flags before interrupt +lst_a equ $1ff ;last accumulator before interrupt + + org data_segment +;concurrent NMI, IRQ & BRK test result +nmi_count ds 1 ;lowest number handled first, $ff = never +irq_count ds 1 ;separation-1 = instructions between interrupts +brk_count ds 1 +;expected interrupt mask +I_src ds 1 ;bit: 0=BRK, 1=IRQ, 2=NMI +data_bss + + code + org code_segment +start cld + lda #0 ;clear expected interrupts for 2nd run + sta I_src + ldx #$ff + txs + +;initialize I/O for report channel + if report = 1 + jsr report_init + endif + +; load system vectors + if load_data_direct != 1 + ldx #5 +ld_vect lda vec_init,x + sta vec_bss,x + dex + bpl ld_vect + endif + +; IRQ & NMI test - requires a feedback register + if I_drive > 1 + ERROR ;invalid interrupt drive! + endif + if NMI_bit < 0 + if I_drive = 0 ;totem pole (push/pull, 0 -> I_port to force interrupt) +I_set macro ibit ;ibit = interrupt bit + lda I_port ;turn on interrupt by bit + and #I_filter-(1<<\1) + plp ;set flags + pha ;save to verify + php + sta I_port ;interrupt next instruction plus outbound delay + endm +I_clr macro ibit ;ibit = interrupt bit + lda I_port ;turn off interrupt by bit + and #I_filter + ora #(1< I_DDR or I_port to force interrupt + if I_ddr != 0 ;with DDR +I_set macro ibit ;ibit = interrupt bit + lda I_ddr ;turn on interrupt by bit + and #I_filter + ora #(1<<\1) + plp ;set flags + pha ;save to verify + php + sta I_ddr ;interrupt next instruction plus outbound delay + endm +I_clr macro ibit ;ibit = interrupt bit + lda I_ddr ;turn off interrupt by bit + and #I_filter-(1< I_port to force interrupt) +I_set macro ibit ;ibit = interrupt bit + lda I_port ;turn on interrupt by bit + if ibit > 7 ;set both NMI & IRQ + and #I_filter-(1< I_DDR or I_port to force interrupt + if I_ddr != 0 ;with DDR +I_set macro ibit ;ibit = interrupt bit + lda I_ddr ;turn on interrupt by bit + and #I_filter + if ibit > 7 ;set both NMI & IRQ + ora #(1< 7 ;set both NMI & IRQ + ora #(1<. + + +; This program is designed to test all additional 65C02 opcodes, addressing +; modes and functionality not available in the NMOS version of the 6502. +; The 6502_functional_test is a prerequisite to this test. +; NMI, IRQ, STP & WAI are covered in the 6502_interrupt_test. +; +; version 04-dec-2017 +; contact info at http://2m5.de or email K@2m5.de +; +; assembled with AS65 from http://www.kingswood-consulting.co.uk/assemblers/ +; command line switches: -l -m -s2 -w -x -h0 +; | | | | | no page headers in listing +; | | | | 65C02 extensions +; | | | wide listing (133 char/col) +; | | write intel hex file instead of binary +; | expand macros in listing +; generate pass2 listing +; +; No IO - should be run from a monitor with access to registers. +; To run load intel hex image with a load command, than alter PC to 400 hex +; (code_segment) and enter a go command. +; Loop on program counter determines error or successful completion of test. +; Check listing for relevant traps (jump/branch *). +; Please note that in early tests some instructions will have to be used before +; they are actually tested! +; +; RESET, NMI or IRQ should not occur and will be trapped if vectors are enabled. +; Tests documented behavior of the original 65C02 only! +; Decimal ops will only be tested with valid BCD operands and the V flag will +; be ignored as it is absolutely useless in decimal mode. +; +; Debugging hints: +; Most of the code is written sequentially. if you hit a trap, check the +; immediately preceeding code for the instruction to be tested. Results are +; tested first, flags are checked second by pushing them onto the stack and +; pulling them to the accumulator after the result was checked. The "real" +; flags are no longer valid for the tested instruction at this time! +; If the tested instruction was indexed, the relevant index (X or Y) must +; also be checked. Opposed to the flags, X and Y registers are still valid. +; +; versions: +; 19-jul-2013 1st version distributed for testing +; 23-jul-2013 fixed BRA out of range due to larger trap macros +; added RAM integrity check +; 16-aug-2013 added error report to standard output option +; 23-aug-2015 change revoked +; 24-aug-2015 all self modifying immediate opcodes now execute in data RAM +; 28-aug-2015 fixed decimal adc/sbc immediate only testing carry +; 09-feb-2017 fixed RMB/SMB tested when they shouldn't be tested +; 04-dec-2017 fixed BRK not tested for actually going through the IRQ vector +; added option to skip the remainder of a failing test +; in report.i65 +; added skip override to undefined opcode as NOP test + + +; C O N F I G U R A T I O N + +;ROM_vectors writable (0=no, 1=yes) +;if ROM vectors can not be used interrupts will not be trapped +;as a consequence BRK can not be tested but will be emulated to test RTI +ROM_vectors = 1 + +;load_data_direct (0=move from code segment, 1=load directly) +;loading directly is preferred but may not be supported by your platform +;0 produces only consecutive object code, 1 is not suitable for a binary image +load_data_direct = 1 + +;I_flag behavior (0=force enabled, 1=force disabled, 2=prohibit change, 3=allow +;change) 2 requires extra code and is not recommended. +I_flag = 3 + +;configure memory - try to stay away from memory used by the system +;zero_page memory start address, $4e (78) consecutive Bytes required +; add 2 if I_flag = 2 +zero_page = $a + +;data_segment memory start address, $63 (99) consecutive Bytes required +; + 12 Bytes at data_segment + $f9 (JMP indirect page cross test) +data_segment = $200 + if (data_segment & $ff) != 0 + ERROR ERROR ERROR low byte of data_segment MUST be $00 !! + endif + +;code_segment memory start address, 10kB of consecutive space required +; add 1 kB if I_flag = 2 +code_segment = $400 + +;added WDC only opcodes WAI & STP (0=test as NOPs, >0=no test) +wdc_op = 1 + +;added Rockwell & WDC opcodes BBR, BBS, RMB & SMB +;(0=test as NOPs, 1=full test, >1=no test) +rkwl_wdc_op = 1 + +;skip testing all undefined opcodes override +;0=test as NOP, >0=skip +skip_nop = 0 + +;report errors through I/O channel (0=use standard self trap loops, 1=include +;report.i65 as I/O channel, add 3 kB) +report = 0 + +;RAM integrity test option. Checks for undesired RAM writes. +;set lowest non RAM or RAM mirror address page (-1=disable, 0=64k, $40=16k) +;leave disabled if a monitor, OS or background interrupt is allowed to alter RAM +ram_top = -1 + + noopt ;do not take shortcuts + +;macros for error & success traps to allow user modification +;example: +;trap macro +; jsr my_error_handler +; endm +;trap_eq macro +; bne skip\? +; trap ;failed equal (zero) +;skip\? +; endm +; +; my_error_handler should pop the calling address from the stack and report it. +; putting larger portions of code (more than 3 bytes) inside the trap macro +; may lead to branch range problems for some tests. + if report = 0 +trap macro + jmp * ;failed anyway + endm +trap_eq macro + beq * ;failed equal (zero) + endm +trap_ne macro + bne * ;failed not equal (non zero) + endm +trap_cs macro + bcs * ;failed carry set + endm +trap_cc macro + bcc * ;failed carry clear + endm +trap_mi macro + bmi * ;failed minus (bit 7 set) + endm +trap_pl macro + bpl * ;failed plus (bit 7 clear) + endm +trap_vs macro + bvs * ;failed overflow set + endm +trap_vc macro + bvc * ;failed overflow clear + endm +; please observe that during the test the stack gets invalidated +; therefore a RTS inside the success macro is not possible +success macro + jmp * ;test passed, no errors + endm + endif + if report = 1 +trap macro + jsr report_error + endm +trap_eq macro + bne skip\? + trap ;failed equal (zero) +skip\? + endm +trap_ne macro + beq skip\? + trap ;failed not equal (non zero) +skip\? + endm +trap_cs macro + bcc skip\? + trap ;failed carry set +skip\? + endm +trap_cc macro + bcs skip\? + trap ;failed carry clear +skip\? + endm +trap_mi macro + bpl skip\? + trap ;failed minus (bit 7 set) +skip\? + endm +trap_pl macro + bmi skip\? + trap ;failed plus (bit 7 clear) +skip\? + endm +trap_vs macro + bvc skip\? + trap ;failed overflow set +skip\? + endm +trap_vc macro + bvs skip\? + trap ;failed overflow clear +skip\? + endm +; please observe that during the test the stack gets invalidated +; therefore a RTS inside the success macro is not possible +success macro + jsr report_success + endm + endif + + +carry equ %00000001 ;flag bits in status +zero equ %00000010 +intdis equ %00000100 +decmode equ %00001000 +break equ %00010000 +reserv equ %00100000 +overfl equ %01000000 +minus equ %10000000 + +fc equ carry +fz equ zero +fzc equ carry+zero +fv equ overfl +fvz equ overfl+zero +fn equ minus +fnc equ minus+carry +fnz equ minus+zero +fnzc equ minus+zero+carry +fnv equ minus+overfl + +fao equ break+reserv ;bits always on after PHP, BRK +fai equ fao+intdis ;+ forced interrupt disable +m8 equ $ff ;8 bit mask +m8i equ $ff&~intdis ;8 bit mask - interrupt disable + +;macros to allow masking of status bits. +;masking of interrupt enable/disable on load and compare +;masking of always on bits after PHP or BRK (unused & break) on compare + if I_flag = 0 +load_flag macro + lda #\1&m8i ;force enable interrupts (mask I) + endm +cmp_flag macro + cmp #(\1|fao)&m8i ;I_flag is always enabled + always on bits + endm +eor_flag macro + eor #(\1&m8i|fao) ;mask I, invert expected flags + always on bits + endm + endif + if I_flag = 1 +load_flag macro + lda #\1|intdis ;force disable interrupts + endm +cmp_flag macro + cmp #(\1|fai)&m8 ;I_flag is always disabled + always on bits + endm +eor_flag macro + eor #(\1|fai) ;invert expected flags + always on bits + I + endm + endif + if I_flag = 2 +load_flag macro + lda #\1 + ora flag_I_on ;restore I-flag + and flag_I_off + endm +cmp_flag macro + eor flag_I_on ;I_flag is never changed + cmp #(\1|fao)&m8i ;expected flags + always on bits, mask I + endm +eor_flag macro + eor flag_I_on ;I_flag is never changed + eor #(\1&m8i|fao) ;mask I, invert expected flags + always on bits + endm + endif + if I_flag = 3 +load_flag macro + lda #\1 ;allow test to change I-flag (no mask) + endm +cmp_flag macro + cmp #(\1|fao)&m8 ;expected flags + always on bits + endm +eor_flag macro + eor #\1|fao ;invert expected flags + always on bits + endm + endif + +;macros to set (register|memory|zeropage) & status +set_stat macro ;setting flags in the processor status register + load_flag \1 + pha ;use stack to load status + plp + endm + +set_a macro ;precharging accu & status + load_flag \2 + pha ;use stack to load status + lda #\1 ;precharge accu + plp + endm + +set_x macro ;precharging index & status + load_flag \2 + pha ;use stack to load status + ldx #\1 ;precharge index x + plp + endm + +set_y macro ;precharging index & status + load_flag \2 + pha ;use stack to load status + ldy #\1 ;precharge index y + plp + endm + +set_ax macro ;precharging indexed accu & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;precharge accu + plp + endm + +set_ay macro ;precharging indexed accu & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,y ;precharge accu + plp + endm + +set_z macro ;precharging indexed zp & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;load to zeropage + sta zpt + plp + endm + +set_zx macro ;precharging zp,x & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;load to indexed zeropage + sta zpt,x + plp + endm + +set_abs macro ;precharging indexed memory & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;load to memory + sta abst + plp + endm + +set_absx macro ;precharging abs,x & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;load to indexed memory + sta abst,x + plp + endm + +;macros to test (register|memory|zeropage) & status & (mask) +tst_stat macro ;testing flags in the processor status register + php ;save status + pla ;use stack to retrieve status + pha + cmp_flag \1 + trap_ne + plp ;restore status + endm + +tst_a macro ;testing result in accu & flags + php ;save flags + cmp #\1 ;test result + trap_ne + pla ;load status + pha + cmp_flag \2 + trap_ne + plp ;restore status + endm + +tst_as macro ;testing result in accu & flags, save accu + pha + php ;save flags + cmp #\1 ;test result + trap_ne + pla ;load status + pha + cmp_flag \2 + trap_ne + plp ;restore status + pla + endm + +tst_x macro ;testing result in x index & flags + php ;save flags + cpx #\1 ;test result + trap_ne + pla ;load status + pha + cmp_flag \2 + trap_ne + plp ;restore status + endm + +tst_y macro ;testing result in y index & flags + php ;save flags + cpy #\1 ;test result + trap_ne + pla ;load status + pha + cmp_flag \2 + trap_ne + plp ;restore status + endm + +tst_ax macro ;indexed testing result in accu & flags + php ;save flags + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne ; + endm + +tst_ay macro ;indexed testing result in accu & flags + php ;save flags + cmp \1,y ;test result + trap_ne ; + pla ;load status + eor_flag \3 + cmp \2,y ;test flags + trap_ne + endm + +tst_z macro ;indexed testing result in zp & flags + php ;save flags + lda zpt + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne + endm + +tst_zx macro ;testing result in zp,x & flags + php ;save flags + lda zpt,x + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne + endm + +tst_abs macro ;indexed testing result in memory & flags + php ;save flags + lda abst + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne + endm + +tst_absx macro ;testing result in abs,x & flags + php ;save flags + lda abst,x + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne + endm + +; RAM integrity test +; verifies that none of the previous tests has altered RAM outside of the +; designated write areas. +; uses zpt word as indirect pointer, zpt+2 word as checksum + if ram_top > -1 +check_ram macro + cld + lda #0 + sta zpt ;set low byte of indirect pointer + sta zpt+3 ;checksum high byte + ldx #11 ;reset modifiable RAM +ccs1\? sta jxi_tab,x ;JMP indirect page cross area + dex + bpl ccs1\? + clc + ldx #zp_bss-zero_page ;zeropage - write test area +ccs3\? adc zero_page,x + bcc ccs2\? + inc zpt+3 ;carry to high byte + clc +ccs2\? inx + bne ccs3\? + ldx #hi(abs1) ;set high byte of indirect pointer + stx zpt+1 + ldy #lo(abs1) ;data after write & execute test area +ccs5\? adc (zpt),y + bcc ccs4\? + inc zpt+3 ;carry to high byte + clc +ccs4\? iny + bne ccs5\? + inx ;advance RAM high address + stx zpt+1 + cpx #ram_top + bne ccs5\? + sta zpt+2 ;checksum low is + cmp ram_chksm ;checksum low expected + trap_ne ;checksum mismatch + lda zpt+3 ;checksum high is + cmp ram_chksm+1 ;checksum high expected + trap_ne ;checksum mismatch + endm + else +check_ram macro + ;RAM check disabled - RAM size not set + endm + endif + +next_test macro ;make sure, tests don't jump the fence + lda test_case ;previous test + cmp #test_num + trap_ne ;test is out of sequence +test_num = test_num + 1 + lda #test_num ;*** next tests' number + sta test_case + ;check_ram ;uncomment to find altered RAM after each test + endm + + if load_data_direct = 1 + data + else + bss ;uninitialized segment, copy of data at end of code! + endif + org zero_page +;break test interrupt save +irq_a ds 1 ;a register +irq_x ds 1 ;x register + if I_flag = 2 +;masking for I bit in status +flag_I_on ds 1 ;or mask to load flags +flag_I_off ds 1 ;and mask to load flags + endif +zpt ;5 bytes store/modify test area +;add/subtract operand generation and result/flag prediction +adfc ds 1 ;carry flag before op +ad1 ds 1 ;operand 1 - accumulator +ad2 ds 1 ;operand 2 - memory / immediate +adrl ds 1 ;expected result bits 0-7 +adrh ds 1 ;expected result bit 8 (carry) +adrf ds 1 ;expected flags NV0000ZC (-V in decimal mode) +sb2 ds 1 ;operand 2 complemented for subtract +zp_bss +zp1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR +zp7f db $7f ;test pattern for compare +;logical zeropage operands +zpOR db 0,$1f,$71,$80 ;test pattern for OR +zpAN db $0f,$ff,$7f,$80 ;test pattern for AND +zpEO db $ff,$0f,$8f,$8f ;test pattern for EOR +;indirect addressing pointers +ind1 dw abs1 ;indirect pointer to pattern in absolute memory + dw abs1+1 + dw abs1+2 + dw abs1+3 + dw abs7f +inw1 dw abs1-$f8 ;indirect pointer for wrap-test pattern +indt dw abst ;indirect pointer to store area in absolute memory + dw abst+1 + dw abst+2 + dw abst+3 +inwt dw abst-$f8 ;indirect pointer for wrap-test store +indAN dw absAN ;indirect pointer to AND pattern in absolute memory + dw absAN+1 + dw absAN+2 + dw absAN+3 +indEO dw absEO ;indirect pointer to EOR pattern in absolute memory + dw absEO+1 + dw absEO+2 + dw absEO+3 +indOR dw absOR ;indirect pointer to OR pattern in absolute memory + dw absOR+1 + dw absOR+2 + dw absOR+3 +;add/subtract indirect pointers +adi2 dw ada2 ;indirect pointer to operand 2 in absolute memory +sbi2 dw sba2 ;indirect pointer to complemented operand 2 (SBC) +adiy2 dw ada2-$ff ;with offset for indirect indexed +sbiy2 dw sba2-$ff +zp_bss_end + + org data_segment +pg_x ds 2 ;high JMP indirect address for page cross bug +test_case ds 1 ;current test number +ram_chksm ds 2 ;checksum for RAM integrity test +;add/subtract operand copy - abs tests write area +abst ;5 bytes store/modify test area +ada2 ds 1 ;operand 2 +sba2 ds 1 ;operand 2 complemented for subtract + ds 3 ;fill remaining bytes +data_bss + if load_data_direct = 1 +ex_adci adc #0 ;execute immediate opcodes + rts +ex_sbci sbc #0 ;execute immediate opcodes + rts + else +ex_adci ds 3 +ex_sbci ds 3 + endif +abs1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR +abs7f db $7f ;test pattern for compare +;loads +fLDx db fn,fn,0,fz ;expected flags for load +;shifts +rASL ;expected result ASL & ROL -carry +rROL db $86,$04,$82,0 ; " +rROLc db $87,$05,$83,1 ;expected result ROL +carry +rLSR ;expected result LSR & ROR -carry +rROR db $61,$41,$20,0 ; " +rRORc db $e1,$c1,$a0,$80 ;expected result ROR +carry +fASL ;expected flags for shifts +fROL db fnc,fc,fn,fz ;no carry in +fROLc db fnc,fc,fn,0 ;carry in +fLSR +fROR db fc,0,fc,fz ;no carry in +fRORc db fnc,fn,fnc,fn ;carry in +;increments (decrements) +rINC db $7f,$80,$ff,0,1 ;expected result for INC/DEC +fINC db 0,fn,fn,fz,0 ;expected flags for INC/DEC +;logical memory operand +absOR db 0,$1f,$71,$80 ;test pattern for OR +absAN db $0f,$ff,$7f,$80 ;test pattern for AND +absEO db $ff,$0f,$8f,$8f ;test pattern for EOR +;logical accu operand +absORa db 0,$f1,$1f,0 ;test pattern for OR +absANa db $f0,$ff,$ff,$ff ;test pattern for AND +absEOa db $ff,$f0,$f0,$0f ;test pattern for EOR +;logical results +absrlo db 0,$ff,$7f,$80 +absflo db fz,fn,0,fn +data_bss_end +;define area for page crossing JMP (abs) & JMP (abs,x) test +jxi_tab equ data_segment + $100 - 7 ;JMP (jxi_tab,x) x=6 +ji_tab equ data_segment + $100 - 3 ;JMP (ji_tab+2) +jxp_tab equ data_segment + $100 ;JMP (jxp_tab-255) x=255 + + + code + org code_segment +start cld + ldx #$ff + txs + lda #0 ;*** test 0 = initialize + sta test_case +test_num = 0 + +;stop interrupts before initializing BSS + if I_flag = 1 + sei + endif + +;initialize I/O for report channel + if report = 1 + jsr report_init + endif + +;initialize BSS segment + if load_data_direct != 1 + ldx #zp_end-zp_init-1 +ld_zp lda zp_init,x + sta zp_bss,x + dex + bpl ld_zp + ldx #data_end-data_init-1 +ld_data lda data_init,x + sta data_bss,x + dex + bpl ld_data + if ROM_vectors = 1 + ldx #5 +ld_vect lda vec_init,x + sta vec_bss,x + dex + bpl ld_vect + endif + endif + +;retain status of interrupt flag + if I_flag = 2 + php + pla + and #4 ;isolate flag + sta flag_I_on ;or mask + eor #lo(~4) ;reverse + sta flag_I_off ;and mask + endif + +;generate checksum for RAM integrity test + if ram_top > -1 + lda #0 + sta zpt ;set low byte of indirect pointer + sta ram_chksm+1 ;checksum high byte + ldx #11 ;reset modifiable RAM +gcs1 sta jxi_tab,x ;JMP indirect page cross area + dex + bpl gcs1 + clc + ldx #zp_bss-zero_page ;zeropage - write test area +gcs3 adc zero_page,x + bcc gcs2 + inc ram_chksm+1 ;carry to high byte + clc +gcs2 inx + bne gcs3 + ldx #hi(abs1) ;set high byte of indirect pointer + stx zpt+1 + ldy #lo(abs1) ;data after write & execute test area +gcs5 adc (zpt),y + bcc gcs4 + inc ram_chksm+1 ;carry to high byte + clc +gcs4 iny + bne gcs5 + inx ;advance RAM high address + stx zpt+1 + cpx #ram_top + bne gcs5 + sta ram_chksm ;checksum complete + endif + next_test + +;testing stack operations PHX PHY PLX PLY + lda #$99 ;protect a + ldx #$ff ;initialize stack + txs + ldx #$55 + phx + ldx #$aa + phx + cpx $1fe ;on stack ? + trap_ne + tsx + cpx #$fd ;sp decremented? + trap_ne + ply + cpy #$aa ;successful retreived from stack? + trap_ne + ply + cpy #$55 + trap_ne + cpy $1ff ;remains on stack? + trap_ne + tsx + cpx #$ff ;sp incremented? + trap_ne + + ldy #$a5 + phy + ldy #$5a + phy + cpy $1fe ;on stack ? + trap_ne + tsx + cpx #$fd ;sp decremented? + trap_ne + plx + cpx #$5a ;successful retreived from stack? + trap_ne + plx + cpx #$a5 + trap_ne + cpx $1ff ;remains on stack? + trap_ne + tsx + cpx #$ff ;sp incremented? + trap_ne + cmp #$99 ;unchanged? + trap_ne + next_test + +; test PHX does not alter flags or X but PLX does + ldy #$aa ;protect y + set_x 1,$ff ;push + phx + tst_x 1,$ff + set_x 0,0 + phx + tst_x 0,0 + set_x $ff,$ff + phx + tst_x $ff,$ff + set_x 1,0 + phx + tst_x 1,0 + set_x 0,$ff + phx + tst_x 0,$ff + set_x $ff,0 + phx + tst_x $ff,0 + set_x 0,$ff ;pull + plx + tst_x $ff,$ff-zero + set_x $ff,0 + plx + tst_x 0,zero + set_x $fe,$ff + plx + tst_x 1,$ff-zero-minus + set_x 0,0 + plx + tst_x $ff,minus + set_x $ff,$ff + plx + tst_x 0,$ff-minus + set_x $fe,0 + plx + tst_x 1,0 + cpy #$aa ;Y unchanged + trap_ne + next_test + +; test PHY does not alter flags or Y but PLY does + ldx #$55 ;x & a protected + set_y 1,$ff ;push + phy + tst_y 1,$ff + set_y 0,0 + phy + tst_y 0,0 + set_y $ff,$ff + phy + tst_y $ff,$ff + set_y 1,0 + phy + tst_y 1,0 + set_y 0,$ff + phy + tst_y 0,$ff + set_y $ff,0 + phy + tst_y $ff,0 + set_y 0,$ff ;pull + ply + tst_y $ff,$ff-zero + set_y $ff,0 + ply + tst_y 0,zero + set_y $fe,$ff + ply + tst_y 1,$ff-zero-minus + set_y 0,0 + ply + tst_y $ff,minus + set_y $ff,$ff + ply + tst_y 0,$ff-minus + set_y $fe,0 + ply + tst_y 1,0 + cpx #$55 ;x unchanged? + trap_ne + next_test + +; PC modifying instructions (BRA, BBR, BBS, 1, 2, 3 byte NOPs, JMP(abs,x)) +; testing unconditional branch BRA + + ldx #$81 ;protect unused registers + ldy #$7e + set_a 0,$ff + bra br1 ;branch should always be taken + trap +br1 + tst_a 0,$ff + set_a $ff,0 + bra br2 ;branch should always be taken + trap +br2 + tst_a $ff,0 + cpx #$81 + trap_ne + cpy #$7e + trap_ne + next_test + + ldy #0 ;branch range test + bra bra0 + +bra1 cpy #1 + trap_ne ;long range backward + iny + bra bra2 + +bra3 cpy #3 + trap_ne ;long range backward + iny + bra bra4 + +bra5 cpy #5 + trap_ne ;long range backward + iny + ldy #0 + bra brf0 + + iny + iny + iny + iny +brf0 bra brf1 + + iny + iny + iny +brf1 iny + bra brf2 + + iny + iny +brf2 iny + iny + bra brf3 + + iny +brf3 iny + iny + iny + bra brf4 + +brf4 iny + iny + iny + iny + cpy #10 + trap_ne ;short range forward + bra brb0 + +brb4 dey + dey + dey + dey + bra brb5 + +brb3 dey + dey + dey + bra brb4 + +brb2 dey + dey + bra brb3 + +brb1 dey + bra brb2 + +brb0 bra brb1 + +brb5 cpy #0 + trap_ne ;short range backward + bra bra6 + +bra4 cpy #4 + trap_ne ;long range forward + iny + bra bra5 + +bra2 cpy #2 + trap_ne ;long range forward + iny + bra bra3 + +bra0 cpy #0 + trap_ne ;long range forward + iny + bra bra1 + +bra6 + next_test + + if rkwl_wdc_op = 1 +; testing BBR & BBS + +bbt macro ;\1 = bitnum + lda #(1<<\1) ;testing 1 bit on + sta zpt + set_a $33,0 ;with flags off + bbr \1,zpt,fail1\? + bbs \1,zpt,ok1\? + trap ;bbs branch not taken +fail1\? + trap ;bbr branch taken +ok1\? + tst_a $33,0 + set_a $cc,$ff ;with flags on + bbr \1,zpt,fail2\? + bbs \1,zpt,ok2\? + trap ;bbs branch not taken +fail2\? + trap ;bbr branch taken +ok2\? + tst_a $cc,$ff + lda zpt + cmp #(1<<\1) + trap_ne ;zp altered + lda #$ff-(1<<\1) ;testing 1 bit off + sta zpt + set_a $33,0 ;with flags off + bbs \1,zpt,fail3\? + bbr \1,zpt,ok3\? + trap ;bbr branch not taken +fail3\? + trap ;bbs branch taken +ok3\? + tst_a $33,0 + set_a $cc,$ff ;with flags on + bbs \1,zpt,fail4\? + bbr \1,zpt,ok4\? + trap ;bbr branch not taken +fail4\? + trap ;bbs branch taken +ok4\? + tst_a $cc,$ff + lda zpt + cmp #$ff-(1<<\1) + trap_ne ;zp altered + endm + + ldx #$11 ;test bbr/bbs integrity + ldy #$22 + bbt 0 + bbt 1 + bbt 2 + bbt 3 + bbt 4 + bbt 5 + bbt 6 + bbt 7 + cpx #$11 + trap_ne ;x overwritten + cpy #$22 + trap_ne ;y overwritten + next_test + +bbrc macro ;\1 = bitnum + bbr \1,zpt,skip\? + eor #(1<<\1) +skip\? + endm +bbsc macro ;\1 = bitnum + bbs \1,zpt,skip\? + eor #(1<<\1) +skip\? + endm + + lda #0 ;combined bit test + sta zpt +bbcl lda #0 + bbrc 0 + bbrc 1 + bbrc 2 + bbrc 3 + bbrc 4 + bbrc 5 + bbrc 6 + bbrc 7 + eor zpt + trap_ne ;failed bbr bitnum in accu + lda #$ff + bbsc 0 + bbsc 1 + bbsc 2 + bbsc 3 + bbsc 4 + bbsc 5 + bbsc 6 + bbsc 7 + eor zpt + trap_ne ;failed bbs bitnum in accu + inc zpt + bne bbcl + next_test + endif + +; testing NOP + +nop_test macro ;\1 = opcode, \2 = # of bytes + ldy #$42 + ldx #4-\2 + db \1 ;test nop length + if \2 = 1 + dex + dex + endif + if \2 = 2 + iny + dex + endif + if \2 = 3 + iny + iny + endif + dex + trap_ne ;wrong number of bytes + set_a $ff-\1,0 + db \1 ;test nop integrity - flags off + nop + nop + tst_a $ff-\1,0 + set_a $aa-\1,$ff + db \1 ;test nop integrity - flags on + nop + nop + tst_a $aa-\1,$ff + cpy #$42 + trap_ne ;y changed + cpx #0 + trap_ne ;x changed + endm + + if skip_nop = 0 + nop_test $02,2 + nop_test $22,2 + nop_test $42,2 + nop_test $62,2 + nop_test $82,2 + nop_test $c2,2 + nop_test $e2,2 + nop_test $44,2 + nop_test $54,2 + nop_test $d4,2 + nop_test $f4,2 + nop_test $5c,3 + nop_test $dc,3 + nop_test $fc,3 + nop_test $03,1 + nop_test $13,1 + nop_test $23,1 + nop_test $33,1 + nop_test $43,1 + nop_test $53,1 + nop_test $63,1 + nop_test $73,1 + nop_test $83,1 + nop_test $93,1 + nop_test $a3,1 + nop_test $b3,1 + nop_test $c3,1 + nop_test $d3,1 + nop_test $e3,1 + nop_test $f3,1 + nop_test $0b,1 + nop_test $1b,1 + nop_test $2b,1 + nop_test $3b,1 + nop_test $4b,1 + nop_test $5b,1 + nop_test $6b,1 + nop_test $7b,1 + nop_test $8b,1 + nop_test $9b,1 + nop_test $ab,1 + nop_test $bb,1 + nop_test $eb,1 + nop_test $fb,1 + if rkwl_wdc_op = 0 ;NOPs not available on Rockwell & WDC 65C02 + nop_test $07,1 + nop_test $17,1 + nop_test $27,1 + nop_test $37,1 + nop_test $47,1 + nop_test $57,1 + nop_test $67,1 + nop_test $77,1 + nop_test $87,1 + nop_test $97,1 + nop_test $a7,1 + nop_test $b7,1 + nop_test $c7,1 + nop_test $d7,1 + nop_test $e7,1 + nop_test $f7,1 + nop_test $0f,1 + nop_test $1f,1 + nop_test $2f,1 + nop_test $3f,1 + nop_test $4f,1 + nop_test $5f,1 + nop_test $6f,1 + nop_test $7f,1 + nop_test $8f,1 + nop_test $9f,1 + nop_test $af,1 + nop_test $bf,1 + nop_test $cf,1 + nop_test $df,1 + nop_test $ef,1 + nop_test $ff,1 + endif + if wdc_op = 0 ;NOPs not available on WDC 65C02 (WAI, STP) + nop_test $cb,1 + nop_test $db,1 + endif + next_test + endif + +; jump indirect (test page cross bug is fixed) + ldx #3 ;prepare table +ji1 lda ji_adr,x + sta ji_tab,x + dex + bpl ji1 + lda #hi(ji_px) ;high address if page cross bug + sta pg_x + set_stat 0 + lda #'I' + ldx #'N' + ldy #'D' ;N=0, V=0, Z=0, C=0 + jmp (ji_tab) + nop + trap_ne ;runover protection + + dey + dey +ji_ret php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + plp + trap_eq ;returned flags OK? + trap_pl + trap_cc + trap_vc + cmp #('I'^$aa) ;returned registers OK? + trap_ne + cpx #('N'+1) + trap_ne + cpy #('D'-6) + trap_ne + tsx ;SP check + cpx #$ff + trap_ne + next_test + +; jump indexed indirect + ldx #11 ;prepare table +jxi1 lda jxi_adr,x + sta jxi_tab,x + dex + bpl jxi1 + lda #hi(jxi_px) ;high address if page cross bug + sta pg_x + set_stat 0 + lda #'X' + ldx #4 + ldy #'I' ;N=0, V=0, Z=0, C=0 + jmp (jxi_tab,x) + nop + trap_ne ;runover protection + + dey + dey +jxi_ret php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + plp + trap_eq ;returned flags OK? + trap_pl + trap_cc + trap_vc + cmp #('X'^$aa) ;returned registers OK? + trap_ne + cpx #6 + trap_ne + cpy #('I'-6) + trap_ne + tsx ;SP check + cpx #$ff + trap_ne + + lda #lo(jxp_ok) ;test with index causing a page cross + sta jxp_tab + lda #hi(jxp_ok) + sta jxp_tab+1 + lda #lo(jxp_px) + sta pg_x + lda #hi(jxp_px) + sta pg_x+1 + ldx #$ff + jmp (jxp_tab-$ff,x) + +jxp_px + trap ;page cross by index to wrong page + +jxp_ok + next_test + + if ROM_vectors = 1 +; test BRK clears decimal mode + load_flag 0 ;with interrupts enabled if allowed! + pha + lda #'B' + ldx #'R' + ldy #'K' + plp ;N=0, V=0, Z=0, C=0 + brk + dey ;should not be executed +brk_ret0 ;address of break return + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + cmp #'B'^$aa ;returned registers OK? + ;the IRQ vector was never executed if A & X stay unmodified + trap_ne + cpx #'R'+1 + trap_ne + cpy #'K'-6 + trap_ne + pla ;returned flags OK (unchanged)? + cmp_flag 0 + trap_ne + tsx ;sp? + cpx #$ff + trap_ne +;pass 2 + load_flag $ff ;with interrupts disabled if allowed! + pha + lda #$ff-'B' + ldx #$ff-'R' + ldy #$ff-'K' + plp ;N=1, V=1, Z=1, C=1 + brk + dey ;should not be executed +brk_ret1 ;address of break return + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + cmp #($ff-'B')^$aa ;returned registers OK? + ;the IRQ vector was never executed if A & X stay unmodified + trap_ne + cpx #$ff-'R'+1 + trap_ne + cpy #$ff-'K'-6 + trap_ne + pla ;returned flags OK (unchanged)? + cmp_flag $ff + trap_ne + tsx ;sp? + cpx #$ff + trap_ne + next_test + endif + +; testing accumulator increment/decrement INC A & DEC A + ldx #$ac ;protect x & y + ldy #$dc + set_a $fe,$ff + inc a ;ff + tst_as $ff,$ff-zero + inc a ;00 + tst_as 0,$ff-minus + inc a ;01 + tst_as 1,$ff-minus-zero + dec a ;00 + tst_as 0,$ff-minus + dec a ;ff + tst_as $ff,$ff-zero + dec a ;fe + set_a $fe,0 + inc a ;ff + tst_as $ff,minus + inc a ;00 + tst_as 0,zero + inc a ;01 + tst_as 1,0 + dec a ;00 + tst_as 0,zero + dec a ;ff + tst_as $ff,minus + cpx #$ac + trap_ne ;x altered during test + cpy #$dc + trap_ne ;y altered during test + tsx + cpx #$ff + trap_ne ;sp push/pop mismatch + next_test + +; testing load / store accumulator LDA / STA (zp) + ldx #$99 ;protect x & y + ldy #$66 + set_stat 0 + lda (ind1) + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt) + php ;flags after load/store sequence + eor #$c3 + cmp #$c3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + lda (ind1+2) + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt+2) + php ;flags after load/store sequence + eor #$c3 + cmp #$82 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + lda (ind1+4) + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt+4) + php ;flags after load/store sequence + eor #$c3 + cmp #$41 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + lda (ind1+6) + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt+6) + php ;flags after load/store sequence + eor #$c3 + cmp #0 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + cpx #$99 + trap_ne ;x altered during test + cpy #$66 + trap_ne ;y altered during test + + ldy #3 ;testing store result + ldx #0 +tstai1 lda abst,y + eor #$c3 + cmp abs1,y + trap_ne ;store to indirect data + txa + sta abst,y ;clear + dey + bpl tstai1 + + ldx #$99 ;protect x & y + ldy #$66 + set_stat $ff + lda (ind1) + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt) + php ;flags after load/store sequence + eor #$c3 + cmp #$c3 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + lda (ind1+2) + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt+2) + php ;flags after load/store sequence + eor #$c3 + cmp #$82 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + lda (ind1+4) + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt+4) + php ;flags after load/store sequence + eor #$c3 + cmp #$41 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + lda (ind1+6) + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt+6) + php ;flags after load/store sequence + eor #$c3 + cmp #0 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + cpx #$99 + trap_ne ;x altered during test + cpy #$66 + trap_ne ;y altered during test + + ldy #3 ;testing store result + ldx #0 +tstai2 lda abst,y + eor #$c3 + cmp abs1,y + trap_ne ;store to indirect data + txa + sta abst,y ;clear + dey + bpl tstai2 + tsx + cpx #$ff + trap_ne ;sp push/pop mismatch + next_test + +; testing STZ - zp / abs / zp,x / abs,x + ldy #123 ;protect y + ldx #4 ;precharge test area + lda #7 +tstz1 sta zpt,x + asl a + dex + bpl tstz1 + ldx #4 + set_a $55,$ff + stz zpt + stz zpt+1 + stz zpt+2 + stz zpt+3 + stz zpt+4 + tst_a $55,$ff +tstz2 lda zpt,x ;verify zeros stored + trap_ne ;non zero after STZ zp + dex + bpl tstz2 + ldx #4 ;precharge test area + lda #7 +tstz3 sta zpt,x + asl a + dex + bpl tstz3 + ldx #4 + set_a $aa,0 + stz zpt + stz zpt+1 + stz zpt+2 + stz zpt+3 + stz zpt+4 + tst_a $aa,0 +tstz4 lda zpt,x ;verify zeros stored + trap_ne ;non zero after STZ zp + dex + bpl tstz4 + + ldx #4 ;precharge test area + lda #7 +tstz5 sta abst,x + asl a + dex + bpl tstz5 + ldx #4 + set_a $55,$ff + stz abst + stz abst+1 + stz abst+2 + stz abst+3 + stz abst+4 + tst_a $55,$ff +tstz6 lda abst,x ;verify zeros stored + trap_ne ;non zero after STZ abs + dex + bpl tstz6 + ldx #4 ;precharge test area + lda #7 +tstz7 sta abst,x + asl a + dex + bpl tstz7 + ldx #4 + set_a $aa,0 + stz abst + stz abst+1 + stz abst+2 + stz abst+3 + stz abst+4 + tst_a $aa,0 +tstz8 lda abst,x ;verify zeros stored + trap_ne ;non zero after STZ abs + dex + bpl tstz8 + + ldx #4 ;precharge test area + lda #7 +tstz11 sta zpt,x + asl a + dex + bpl tstz11 + ldx #4 +tstz15 + set_a $55,$ff + stz zpt,x + tst_a $55,$ff + dex + bpl tstz15 + ldx #4 +tstz12 lda zpt,x ;verify zeros stored + trap_ne ;non zero after STZ zp + dex + bpl tstz12 + ldx #4 ;precharge test area + lda #7 +tstz13 sta zpt,x + asl a + dex + bpl tstz13 + ldx #4 +tstz16 + set_a $aa,0 + stz zpt,x + tst_a $aa,0 + dex + bpl tstz16 + ldx #4 +tstz14 lda zpt,x ;verify zeros stored + trap_ne ;non zero after STZ zp + dex + bpl tstz14 + + ldx #4 ;precharge test area + lda #7 +tstz21 sta abst,x + asl a + dex + bpl tstz21 + ldx #4 +tstz25 + set_a $55,$ff + stz abst,x + tst_a $55,$ff + dex + bpl tstz25 + ldx #4 +tstz22 lda abst,x ;verify zeros stored + trap_ne ;non zero after STZ zp + dex + bpl tstz22 + ldx #4 ;precharge test area + lda #7 +tstz23 sta abst,x + asl a + dex + bpl tstz23 + ldx #4 +tstz26 + set_a $aa,0 + stz abst,x + tst_a $aa,0 + dex + bpl tstz26 + ldx #4 +tstz24 lda abst,x ;verify zeros stored + trap_ne ;non zero after STZ zp + dex + bpl tstz24 + + cpy #123 + trap_ne ;y altered during test + tsx + cpx #$ff + trap_ne ;sp push/pop mismatch + next_test + +; testing BIT - zp,x / abs,x / # + ldy #$42 + ldx #3 + set_a $ff,0 + bit zp1,x ;00 - should set Z / clear NV + tst_a $ff,fz + dex + set_a 1,0 + bit zp1,x ;41 - should set V (M6) / clear NZ + tst_a 1,fv + dex + set_a 1,0 + bit zp1,x ;82 - should set N (M7) & Z / clear V + tst_a 1,fnz + dex + set_a 1,0 + bit zp1,x ;c3 - should set N (M7) & V (M6) / clear Z + tst_a 1,fnv + + set_a 1,$ff + bit zp1,x ;c3 - should set N (M7) & V (M6) / clear Z + tst_a 1,~fz + inx + set_a 1,$ff + bit zp1,x ;82 - should set N (M7) & Z / clear V + tst_a 1,~fv + inx + set_a 1,$ff + bit zp1,x ;41 - should set V (M6) / clear NZ + tst_a 1,~fnz + inx + set_a $ff,$ff + bit zp1,x ;00 - should set Z / clear NV + tst_a $ff,~fnv + + set_a $ff,0 + bit abs1,x ;00 - should set Z / clear NV + tst_a $ff,fz + dex + set_a 1,0 + bit abs1,x ;41 - should set V (M6) / clear NZ + tst_a 1,fv + dex + set_a 1,0 + bit abs1,x ;82 - should set N (M7) & Z / clear V + tst_a 1,fnz + dex + set_a 1,0 + bit abs1,x ;c3 - should set N (M7) & V (M6) / clear Z + tst_a 1,fnv + + set_a 1,$ff + bit abs1,x ;c3 - should set N (M7) & V (M6) / clear Z + tst_a 1,~fz + inx + set_a 1,$ff + bit abs1,x ;82 - should set N (M7) & Z / clear V + tst_a 1,~fv + inx + set_a 1,$ff + bit abs1,x ;41 - should set V (M6) / clear NZ + tst_a 1,~fnz + inx + set_a $ff,$ff + bit abs1,x ;00 - should set Z / clear NV + tst_a $ff,~fnv + + set_a $ff,0 + bit #$00 ;00 - should set Z + tst_a $ff,fz + dex + set_a 1,0 + bit #$41 ;41 - should clear Z + tst_a 1,0 +; *** DEBUG INFO *** +; if it fails the previous test and your BIT # has set the V flag +; see http://forum.6502.org/viewtopic.php?f=2&t=2241&p=27243#p27239 +; why it shouldn't alter N or V flags on a BIT # + dex + set_a 1,0 + bit #$82 ;82 - should set Z + tst_a 1,fz + dex + set_a 1,0 + bit #$c3 ;c3 - should clear Z + tst_a 1,0 + + set_a 1,$ff + bit #$c3 ;c3 - clear Z + tst_a 1,~fz + inx + set_a 1,$ff + bit #$82 ;82 - should set Z + tst_a 1,$ff + inx + set_a 1,$ff + bit #$41 ;41 - should clear Z + tst_a 1,~fz + inx + set_a $ff,$ff + bit #$00 ;00 - should set Z + tst_a $ff,$ff + + cpx #3 + trap_ne ;x altered during test + cpy #$42 + trap_ne ;y altered during test + tsx + cpx #$ff + trap_ne ;sp push/pop mismatch + next_test + +; testing TRB, TSB - zp / abs + +trbt macro ;\1 = memory, \2 = flags + sty \1 + load_flag \2 + pha + lda zpt+1 + plp + trb \1 + php + cmp zpt+1 + trap_ne ;accu was changed + pla + pha + ora #fz ;mask Z + cmp_flag \2|fz + trap_ne ;flags changed except Z + pla + and #fz + cmp zpt+2 + trap_ne ;Z flag invalid + lda zpt+3 + cmp zpt + trap_ne ;altered bits in memory wrong + endm + +tsbt macro ;\1 = memory, \2 = flags + sty \1 + load_flag \2 + pha + lda zpt+1 + plp + tsb \1 + php + cmp zpt+1 + trap_ne ;accu was changed + pla + pha + ora #fz ;mask Z + cmp_flag \2|fz + trap_ne ;flags changed except Z + pla + and #fz + cmp zpt+2 + trap_ne ;Z flag invalid + lda zpt+4 + cmp zpt + trap_ne ;altered bits in memory wrong + endm + + ldx #$c0 + ldy #0 ;op1 - memory save + ; zpt ;op1 - memory modifiable + stz zpt+1 ;op2 - accu + ; zpt+2 ;and flags + ; zpt+3 ;memory after reset + ; zpt+4 ;memory after set + +tbt1 tya + and zpt+1 ;set Z by anding the 2 operands + php + pla + and #fz ;mask Z + sta zpt+2 + tya ;reset op1 bits by op2 + eor #$ff + ora zpt+1 + eor #$ff + sta zpt+3 + tya ;set op1 bits by op2 + ora zpt+1 + sta zpt+4 + + trbt zpt,$ff + trbt abst,$ff + trbt zpt,0 + trbt abst,0 + tsbt zpt,$ff + tsbt abst,$ff + tsbt zpt,0 + tsbt abst,0 + + iny ;iterate op1 + bne tbt3 + inc zpt+1 ;iterate op2 + beq tbt2 +tbt3 jmp tbt1 +tbt2 + cpx #$c0 + trap_ne ;x altered during test + tsx + cpx #$ff + trap_ne ;sp push/pop mismatch + next_test + + if rkwl_wdc_op = 1 +; testing RMB, SMB - zp +rmbt macro ;\1 = bitnum + lda #$ff + sta zpt + set_a $a5,0 + rmb \1,zpt + tst_a $a5,0 + lda zpt + cmp #$ff-(1<<\1) + trap_ne ;wrong bits set or cleared + lda #1<<\1 + sta zpt + set_a $5a,$ff + rmb \1,zpt + tst_a $5a,$ff + lda zpt + trap_ne ;wrong bits set or cleared + endm +smbt macro ;\1 = bitnum + lda #$ff-(1<<\1) + sta zpt + set_a $a5,0 + smb \1,zpt + tst_a $a5,0 + lda zpt + cmp #$ff + trap_ne ;wrong bits set or cleared + lda #0 + sta zpt + set_a $5a,$ff + smb \1,zpt + tst_a $5a,$ff + lda zpt + cmp #1<<\1 + trap_ne ;wrong bits set or cleared + endm + + ldx #$ba ;protect x & y + ldy #$d0 + rmbt 0 + rmbt 1 + rmbt 2 + rmbt 3 + rmbt 4 + rmbt 5 + rmbt 6 + rmbt 7 + smbt 0 + smbt 1 + smbt 2 + smbt 3 + smbt 4 + smbt 5 + smbt 6 + smbt 7 + cpx #$ba + trap_ne ;x altered during test + cpy #$d0 + trap_ne ;y altered during test + tsx + cpx #$ff + trap_ne ;sp push/pop mismatch + next_test + endif + +; testing CMP - (zp) + ldx #$de ;protect x & y + ldy #$ad + set_a $80,0 + cmp (ind1+8) + tst_a $80,fc + set_a $7f,0 + cmp (ind1+8) + tst_a $7f,fzc + set_a $7e,0 + cmp (ind1+8) + tst_a $7e,fn + set_a $80,$ff + cmp (ind1+8) + tst_a $80,~fnz + set_a $7f,$ff + cmp (ind1+8) + tst_a $7f,~fn + set_a $7e,$ff + cmp (ind1+8) + tst_a $7e,~fzc + cpx #$de + trap_ne ;x altered during test + cpy #$ad + trap_ne ;y altered during test + tsx + cpx #$ff + trap_ne ;sp push/pop mismatch + next_test + +; testing logical instructions - AND EOR ORA (zp) + ldx #$42 ;protect x & y + + ldy #0 ;AND + lda indAN ;set indirect address + sta zpt + lda indAN+1 + sta zpt+1 +tand1 + set_ay absANa,0 + and (zpt) + tst_ay absrlo,absflo,0 + inc zpt + iny + cpy #4 + bne tand1 + dey + dec zpt +tand2 + set_ay absANa,$ff + and (zpt) + tst_ay absrlo,absflo,$ff-fnz + dec zpt + dey + bpl tand2 + + ldy #0 ;EOR + lda indEO ;set indirect address + sta zpt + lda indEO+1 + sta zpt+1 +teor1 + set_ay absEOa,0 + eor (zpt) + tst_ay absrlo,absflo,0 + inc zpt + iny + cpy #4 + bne teor1 + dey + dec zpt +teor2 + set_ay absEOa,$ff + eor (zpt) + tst_ay absrlo,absflo,$ff-fnz + dec zpt + dey + bpl teor2 + + ldy #0 ;ORA + lda indOR ;set indirect address + sta zpt + lda indOR+1 + sta zpt+1 +tora1 + set_ay absORa,0 + ora (zpt) + tst_ay absrlo,absflo,0 + inc zpt + iny + cpy #4 + bne tora1 + dey + dec zpt +tora2 + set_ay absORa,$ff + ora (zpt) + tst_ay absrlo,absflo,$ff-fnz + dec zpt + dey + bpl tora2 + + cpx #$42 + trap_ne ;x altered during test + tsx + cpx #$ff + trap_ne ;sp push/pop mismatch + next_test + + if I_flag = 3 + cli + endif + +; full binary add/subtract test - (zp) only +; iterates through all combinations of operands and carry input +; uses increments/decrements to predict result & result flags + cld + ldx #ad2 ;for indexed test + ldy #$ff ;max range + lda #0 ;start with adding zeroes & no carry + sta adfc ;carry in - for diag + sta ad1 ;operand 1 - accumulator + sta ad2 ;operand 2 - memory or immediate + sta ada2 ;non zp + sta adrl ;expected result bits 0-7 + sta adrh ;expected result bit 8 (carry out) + lda #$ff ;complemented operand 2 for subtract + sta sb2 + sta sba2 ;non zp + lda #2 ;expected Z-flag + sta adrf +tadd clc ;test with carry clear + jsr chkadd + inc adfc ;now with carry + inc adrl ;result +1 + php ;save N & Z from low result + php + pla ;accu holds expected flags + and #$82 ;mask N & Z + plp + bne tadd1 + inc adrh ;result bit 8 - carry +tadd1 ora adrh ;merge C to expected flags + sta adrf ;save expected flags except overflow + sec ;test with carry set + jsr chkadd + dec adfc ;same for operand +1 but no carry + inc ad1 + bne tadd ;iterate op1 + lda #0 ;preset result to op2 when op1 = 0 + sta adrh + inc ada2 + inc ad2 + php ;save NZ as operand 2 becomes the new result + pla + and #$82 ;mask N00000Z0 + sta adrf ;no need to check carry as we are adding to 0 + dec sb2 ;complement subtract operand 2 + dec sba2 + lda ad2 + sta adrl + bne tadd ;iterate op2 + + cpx #ad2 + trap_ne ;x altered during test + cpy #$ff + trap_ne ;y altered during test + tsx + cpx #$ff + trap_ne ;sp push/pop mismatch + next_test + +; decimal add/subtract test +; *** WARNING - tests documented behavior only! *** +; only valid BCD operands are tested, the V flag is ignored +; although V is declared as beeing valid on the 65C02 it has absolutely +; no use in BCD math. No sign = no overflow! +; iterates through all valid combinations of operands and carry input +; uses increments/decrements to predict result & carry flag + sed + ldx #ad2 ;for indexed test + ldy #$ff ;max range + lda #$99 ;start with adding 99 to 99 with carry + sta ad1 ;operand 1 - accumulator + sta ad2 ;operand 2 - memory or immediate + sta ada2 ;non zp + sta adrl ;expected result bits 0-7 + lda #1 ;set carry in & out + sta adfc ;carry in - for diag + sta adrh ;expected result bit 8 (carry out) + lda #$81 ;set N & C (99 + 99 + C = 99 + C) + sta adrf + lda #0 ;complemented operand 2 for subtract + sta sb2 + sta sba2 ;non zp +tdad sec ;test with carry set + jsr chkdad + dec adfc ;now with carry clear + lda adrl ;decimal adjust result + bne tdad1 ;skip clear carry & preset result 99 (9A-1) + dec adrh + lda #$99 + sta adrl + bne tdad3 +tdad1 and #$f ;lower nibble mask + bne tdad2 ;no decimal adjust needed + dec adrl ;decimal adjust (?0-6) + dec adrl + dec adrl + dec adrl + dec adrl + dec adrl +tdad2 dec adrl ;result -1 +tdad3 php ;save valid flags + pla + and #$82 ;N-----Z- + ora adrh ;N-----ZC + sta adrf + clc ;test with carry clear + jsr chkdad + inc adfc ;same for operand -1 but with carry + lda ad1 ;decimal adjust operand 1 + beq tdad5 ;iterate operand 2 + and #$f ;lower nibble mask + bne tdad4 ;skip decimal adjust + dec ad1 ;decimal adjust (?0-6) + dec ad1 + dec ad1 + dec ad1 + dec ad1 + dec ad1 +tdad4 dec ad1 ;operand 1 -1 + jmp tdad ;iterate op1 + +tdad5 lda #$99 ;precharge op1 max + sta ad1 + lda ad2 ;decimal adjust operand 2 + beq tdad7 ;end of iteration + and #$f ;lower nibble mask + bne tdad6 ;skip decimal adjust + dec ad2 ;decimal adjust (?0-6) + dec ad2 + dec ad2 + dec ad2 + dec ad2 + dec ad2 + inc sb2 ;complemented decimal adjust for subtract (?9+6) + inc sb2 + inc sb2 + inc sb2 + inc sb2 + inc sb2 +tdad6 dec ad2 ;operand 2 -1 + inc sb2 ;complemented operand for subtract + lda sb2 + sta sba2 ;copy as non zp operand + lda ad2 + sta ada2 ;copy as non zp operand + sta adrl ;new result since op1+carry=00+carry +op2=op2 + php ;save flags + pla + and #$82 ;N-----Z- + ora #1 ;N-----ZC + sta adrf + inc adrh ;result carry + jmp tdad ;iterate op2 + +tdad7 cpx #ad2 + trap_ne ;x altered during test + cpy #$ff + trap_ne ;y altered during test + tsx + cpx #$ff + trap_ne ;sp push/pop mismatch + cld + + lda test_case + cmp #test_num + trap_ne ;previous test is out of sequence + lda #$f0 ;mark opcode testing complete + sta test_case + +; final RAM integrity test +; verifies that none of the previous tests has altered RAM outside of the +; designated write areas. + check_ram +; *** DEBUG INFO *** +; to debug checksum errors uncomment check_ram in the next_test macro to +; narrow down the responsible opcode. +; may give false errors when monitor, OS or other background activity is +; allowed during previous tests. + + +; S U C C E S S ************************************************ +; ------------- + success ;if you get here everything went well +; ------------- +; S U C C E S S ************************************************ + jmp start ;run again + +; core subroutine of the decimal add/subtract test +; *** WARNING - tests documented behavior only! *** +; only valid BCD operands are tested, V flag is ignored +; iterates through all valid combinations of operands and carry input +; uses increments/decrements to predict result & carry flag +chkdad +; decimal ADC / SBC zp + php ;save carry for subtract + lda ad1 + adc ad2 ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc sb2 ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp +; decimal ADC / SBC abs + php ;save carry for subtract + lda ad1 + adc ada2 ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc sba2 ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp +; decimal ADC / SBC # + php ;save carry for subtract + lda ad2 + sta ex_adci+1 ;set ADC # operand + lda ad1 + jsr ex_adci ;execute ADC # in RAM + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda sb2 + sta ex_sbci+1 ;set SBC # operand + lda ad1 + jsr ex_sbci ;execute SBC # in RAM + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp +; decimal ADC / SBC zp,x + php ;save carry for subtract + lda ad1 + adc 0,x ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc sb2-ad2,x ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp +; decimal ADC / SBC abs,x + php ;save carry for subtract + lda ad1 + adc ada2-ad2,x ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc sba2-ad2,x ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp +; decimal ADC / SBC abs,y + php ;save carry for subtract + lda ad1 + adc ada2-$ff,y ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc sba2-$ff,y ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp +; decimal ADC / SBC (zp,x) + php ;save carry for subtract + lda ad1 + adc (lo adi2-ad2,x) ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc (lo sbi2-ad2,x) ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp +; decimal ADC / SBC (abs),y + php ;save carry for subtract + lda ad1 + adc (adiy2),y ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc (sbiy2),y ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp +; decimal ADC / SBC (zp) + php ;save carry for subtract + lda ad1 + adc (adi2) ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc (sbi2) ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp + rts + +; core subroutine of the full binary add/subtract test +; iterates through all combinations of operands and carry input +; uses increments/decrements to predict result & result flags +chkadd lda adrf ;add V-flag if overflow + and #$83 ;keep N-----ZC / clear V + pha + lda ad1 ;test sign unequal between operands + eor ad2 + bmi ckad1 ;no overflow possible - operands have different sign + lda ad1 ;test sign equal between operands and result + eor adrl + bpl ckad1 ;no overflow occured - operand and result have same sign + pla + ora #$40 ;set V + pha +ckad1 pla + sta adrf ;save expected flags +; binary ADC / SBC (zp) + php ;save carry for subtract + lda ad1 + adc (adi2) ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc (sbi2) ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + rts + +; target for the jump indirect test +ji_adr dw test_ji + dw ji_ret + + dey + dey +test_ji + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + plp + trap_cs ;flags loaded? + trap_vs + trap_mi + trap_eq + cmp #'I' ;registers loaded? + trap_ne + cpx #'N' + trap_ne + cpy #('D'-3) + trap_ne + pha ;save a,x + txa + pha + tsx + cpx #$fd ;check SP + trap_ne + pla ;restore x + tax + set_stat $ff + pla ;restore a + inx ;return registers with modifications + eor #$aa ;N=1, V=1, Z=0, C=1 + jmp (ji_tab+2) + nop + nop + trap ;runover protection + jmp start ;catastrophic error - cannot continue + +; target for the jump indirect test +jxi_adr dw trap_ind + dw trap_ind + dw test_jxi ;+4 + dw jxi_ret ;+6 + dw trap_ind + dw trap_ind + + dey + dey +test_jxi + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + plp + trap_cs ;flags loaded? + trap_vs + trap_mi + trap_eq + cmp #'X' ;registers loaded? + trap_ne + cpx #4 + trap_ne + cpy #('I'-3) + trap_ne + pha ;save a,x + txa + pha + tsx + cpx #$fd ;check SP + trap_ne + pla ;restore x + tax + set_stat $ff + pla ;restore a + inx ;return registers with modifications + inx + eor #$aa ;N=1, V=1, Z=0, C=1 + jmp (jxi_tab,x) + nop + nop + trap ;runover protection + jmp start ;catastrophic error - cannot continue + +; JMP (abs,x) with bad x + nop + nop +trap_ind + nop + nop + trap ;near miss indexed indirect jump + jmp start ;catastrophic error - cannot continue + +;trap in case of unexpected IRQ, NMI, BRK, RESET +nmi_trap + trap ;check stack for conditions at NMI + jmp start ;catastrophic error - cannot continue +res_trap + trap ;unexpected RESET + jmp start ;catastrophic error - cannot continue + + dey + dey +irq_trap ;BRK test or unextpected BRK or IRQ + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + ;next traps could be caused by unexpected BRK or IRQ + ;check stack for BREAK and originating location + ;possible jump/branch into weeds (uninitialized space) + cmp #$ff-'B' ;BRK pass 2 registers loaded? + beq break2 + cmp #'B' ;BRK pass 1 registers loaded? + trap_ne + cpx #'R' + trap_ne + cpy #'K'-3 + trap_ne + sta irq_a ;save registers during break test + stx irq_x + tsx ;test break on stack + lda $102,x + cmp_flag 0 ;break test should have B=1 & unused=1 on stack + trap_ne ;possible no break flag on stack + pla + cmp_flag intdis ;should have added interrupt disable + trap_ne + tsx + cpx #$fc ;sp -3? (return addr, flags) + trap_ne + lda $1ff ;propper return on stack + cmp #hi(brk_ret0) + trap_ne + lda $1fe + cmp #lo(brk_ret0) + trap_ne + load_flag $ff + pha + ldx irq_x + inx ;return registers with modifications + lda irq_a + eor #$aa + plp ;N=1, V=1, Z=1, C=1 but original flags should be restored + rti + trap ;runover protection + jmp start ;catastrophic error - cannot continue + +break2 ;BRK pass 2 + cpx #$ff-'R' + trap_ne + cpy #$ff-'K'-3 + trap_ne + sta irq_a ;save registers during break test + stx irq_x + tsx ;test break on stack + lda $102,x + cmp_flag $ff ;break test should have B=1 + trap_ne ;possibly no break flag on stack + pla + cmp_flag $ff-decmode ;actual passed flags should have decmode cleared + trap_ne + tsx + cpx #$fc ;sp -3? (return addr, flags) + trap_ne + lda $1ff ;propper return on stack + cmp #hi(brk_ret1) + trap_ne + lda $1fe + cmp #lo(brk_ret1) + trap_ne + load_flag intdis + pha + ldx irq_x + inx ;return registers with modifications + lda irq_a + eor #$aa + plp ;N=0, V=0, Z=0, C=0 but original flags should be restored + rti + trap ;runover protection + jmp start ;catastrophic error - cannot continue + + if report = 1 + include "report.i65" + endif + +;copy of data to initialize BSS segment + if load_data_direct != 1 +zp_init +zp1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR +zp7f_ db $7f ;test pattern for compare +;logical zeropage operands +zpOR_ db 0,$1f,$71,$80 ;test pattern for OR +zpAN_ db $0f,$ff,$7f,$80 ;test pattern for AND +zpEO_ db $ff,$0f,$8f,$8f ;test pattern for EOR +;indirect addressing pointers +ind1_ dw abs1 ;indirect pointer to pattern in absolute memory + dw abs1+1 + dw abs1+2 + dw abs1+3 + dw abs7f +inw1_ dw abs1-$f8 ;indirect pointer for wrap-test pattern +indt_ dw abst ;indirect pointer to store area in absolute memory + dw abst+1 + dw abst+2 + dw abst+3 +inwt_ dw abst-$f8 ;indirect pointer for wrap-test store +indAN_ dw absAN ;indirect pointer to AND pattern in absolute memory + dw absAN+1 + dw absAN+2 + dw absAN+3 +indEO_ dw absEO ;indirect pointer to EOR pattern in absolute memory + dw absEO+1 + dw absEO+2 + dw absEO+3 +indOR_ dw absOR ;indirect pointer to OR pattern in absolute memory + dw absOR+1 + dw absOR+2 + dw absOR+3 +;add/subtract indirect pointers +adi2_ dw ada2 ;indirect pointer to operand 2 in absolute memory +sbi2_ dw sba2 ;indirect pointer to complemented operand 2 (SBC) +adiy2_ dw ada2-$ff ;with offset for indirect indexed +sbiy2_ dw sba2-$ff +zp_end + if (zp_end - zp_init) != (zp_bss_end - zp_bss) + ;force assembler error if size is different + ERROR ERROR ERROR ;mismatch between bss and zeropage data + endif +data_init +ex_adc_ adc #0 ;execute immediate opcodes + rts +ex_sbc_ sbc #0 ;execute immediate opcodes + rts +abs1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR +abs7f_ db $7f ;test pattern for compare +;loads +fLDx_ db fn,fn,0,fz ;expected flags for load +;shifts +rASL_ ;expected result ASL & ROL -carry +rROL_ db $86,$04,$82,0 ; " +rROLc_ db $87,$05,$83,1 ;expected result ROL +carry +rLSR_ ;expected result LSR & ROR -carry +rROR_ db $61,$41,$20,0 ; " +rRORc_ db $e1,$c1,$a0,$80 ;expected result ROR +carry +fASL_ ;expected flags for shifts +fROL_ db fnc,fc,fn,fz ;no carry in +fROLc_ db fnc,fc,fn,0 ;carry in +fLSR_ +fROR_ db fc,0,fc,fz ;no carry in +fRORc_ db fnc,fn,fnc,fn ;carry in +;increments (decrements) +rINC_ db $7f,$80,$ff,0,1 ;expected result for INC/DEC +fINC_ db 0,fn,fn,fz,0 ;expected flags for INC/DEC +;logical memory operand +absOR_ db 0,$1f,$71,$80 ;test pattern for OR +absAN_ db $0f,$ff,$7f,$80 ;test pattern for AND +absEO_ db $ff,$0f,$8f,$8f ;test pattern for EOR +;logical accu operand +absORa_ db 0,$f1,$1f,0 ;test pattern for OR +absANa_ db $f0,$ff,$ff,$ff ;test pattern for AND +absEOa_ db $ff,$f0,$f0,$0f ;test pattern for EOR +;logical results +absrlo_ db 0,$ff,$7f,$80 +absflo_ db fz,fn,0,fn +data_end + if (data_end - data_init) != (data_bss_end - data_bss) + ;force assembler error if size is different + ERROR ERROR ERROR ;mismatch between bss and data + endif + +vec_init + dw nmi_trap +; dw res_trap + dw start + dw irq_trap +vec_bss equ $fffa + endif ;end of RAM init data + +; code at end of image due to the need to add blank space as required + if ($ff & (ji_ret - * - 2)) < ($ff & (jxi_ret - * - 2)) +; JMP (abs) when $xxff and $xx00 are from same page + ds lo(ji_ret - * - 2) + nop + nop +ji_px nop ;low address byte matched with ji_ret + nop + trap ;jmp indirect page cross bug + +; JMP (abs,x) when $xxff and $xx00 are from same page + ds lo(jxi_ret - * - 2) + nop + nop +jxi_px nop ;low address byte matched with jxi_ret + nop + trap ;jmp indexed indirect page cross bug + else +; JMP (abs,x) when $xxff and $xx00 are from same page + ds lo(jxi_ret - * - 2) + nop + nop +jxi_px nop ;low address byte matched with jxi_ret + nop + trap ;jmp indexed indirect page cross bug + +; JMP (abs) when $xxff and $xx00 are from same page + ds lo(ji_ret - * - 2) + nop + nop +ji_px nop ;low address byte matched with ji_ret + nop + trap ;jmp indirect page cross bug + endif + + if (load_data_direct = 1) & (ROM_vectors = 1) + org $fffa ;vectors + dw nmi_trap +; dw res_trap + dw start + dw irq_trap + endif + + end start Index: cpu65c02_true_cycle/trunk/released/asm/readme.txt =================================================================== --- cpu65c02_true_cycle/trunk/released/asm/readme.txt (nonexistent) +++ cpu65c02_true_cycle/trunk/released/asm/readme.txt (revision 23) @@ -0,0 +1,26 @@ +(July, 31th 2013) +It weas a heavy task to create/find an appropriate test bench on assembler level +useable by the end-user. +In 2012 Klaus Dormann creates and publish his amazing 6502 test suite written +in assembler. Thanks again to Klaus! +It uses the a65 assembler created by Frank A. Kingswood + (http://www.kingswood-consulting.co.uk/assemblers/) + +If you generate the HEX/BIN files for your project, please aware of the offset +of #10/$a bytes. + +I made a little change in both attached source files to allow running the +programs on systems without any os or monitor direcly from RAM. + +Klaus implemented an UNEXPECTED RESET TRAP which prevent the start of program +after RESET in default configuration. Default is now "RESET -> start". + +In both programs the lines + dw res_trap + dw start +should activated/deactivated by your requirements. + +(Sptember, 08th 2018 +I added the interrupt vector table to Bruce's decimal test. +All four tests: SUCCESS with v1.52RC + Index: cpu65c02_true_cycle/trunk/released/doc/65C02_OP code_table_A01.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: cpu65c02_true_cycle/trunk/released/doc/65C02_OP code_table_A01.pdf =================================================================== --- cpu65c02_true_cycle/trunk/released/doc/65C02_OP code_table_A01.pdf (nonexistent) +++ cpu65c02_true_cycle/trunk/released/doc/65C02_OP code_table_A01.pdf (revision 23)
cpu65c02_true_cycle/trunk/released/doc/65C02_OP code_table_A01.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: cpu65c02_true_cycle/trunk/released/doc/65C02_opcodes_cycles_testet_V0_94.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: cpu65c02_true_cycle/trunk/released/doc/65C02_opcodes_cycles_testet_V0_94.pdf =================================================================== --- cpu65c02_true_cycle/trunk/released/doc/65C02_opcodes_cycles_testet_V0_94.pdf (nonexistent) +++ cpu65c02_true_cycle/trunk/released/doc/65C02_opcodes_cycles_testet_V0_94.pdf (revision 23)
cpu65c02_true_cycle/trunk/released/doc/65C02_opcodes_cycles_testet_V0_94.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: cpu65c02_true_cycle/trunk/released/doc/HTML_r65c02_tc.7z =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: cpu65c02_true_cycle/trunk/released/doc/HTML_r65c02_tc.7z =================================================================== --- cpu65c02_true_cycle/trunk/released/doc/HTML_r65c02_tc.7z (nonexistent) +++ cpu65c02_true_cycle/trunk/released/doc/HTML_r65c02_tc.7z (revision 23)
cpu65c02_true_cycle/trunk/released/doc/HTML_r65c02_tc.7z Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: cpu65c02_true_cycle/trunk/released/doc/R65C02 IP Core Specification_V0_9.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: cpu65c02_true_cycle/trunk/released/doc/R65C02 IP Core Specification_V0_9.pdf =================================================================== --- cpu65c02_true_cycle/trunk/released/doc/R65C02 IP Core Specification_V0_9.pdf (nonexistent) +++ cpu65c02_true_cycle/trunk/released/doc/R65C02 IP Core Specification_V0_9.pdf (revision 23)
cpu65c02_true_cycle/trunk/released/doc/R65C02 IP Core Specification_V0_9.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: cpu65c02_true_cycle/trunk/released/doc/errata.txt =================================================================== --- cpu65c02_true_cycle/trunk/released/doc/errata.txt (nonexistent) +++ cpu65c02_true_cycle/trunk/released/doc/errata.txt (revision 23) @@ -0,0 +1,10 @@ +v1.52 2018/09/10 +FUNCTIONALITY: + no errata reported/opened + +TIMING: + no errata reported/opened + +SIGNALING: + no errata reported/opened + Index: cpu65c02_true_cycle/trunk/released/doc/src/__empty__ =================================================================== Index: cpu65c02_true_cycle/trunk/released/rtl/verilog/__empty__ =================================================================== Index: cpu65c02_true_cycle/trunk/released/rtl/vhdl/core.vhd =================================================================== --- cpu65c02_true_cycle/trunk/released/rtl/vhdl/core.vhd (nonexistent) +++ cpu65c02_true_cycle/trunk/released/rtl/vhdl/core.vhd (revision 23) @@ -0,0 +1,396 @@ +-- VHDL Entity r65c02_tc.core.symbol +-- +-- Created: +-- by - jens.Domain Users (ENTW-7HPZ200) +-- at - 11:09:21 08/01/13 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +entity core is + port( + clk_clk_i : in std_logic; + d_i : in std_logic_vector (7 downto 0); + irq_n_i : in std_logic; + nmi_n_i : in std_logic; + rdy_i : in std_logic; + rst_rst_n_i : in std_logic; + so_n_i : in std_logic; + a_o : out std_logic_vector (15 downto 0); + d_o : out std_logic_vector (7 downto 0); + rd_o : out std_logic; + sync_o : out std_logic; + wr_n_o : out std_logic; + wr_o : out std_logic + ); + +-- Declarations + +end core ; + +-- (C) 2008 - 2018 Jens Gutschmidt +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 1.8 2013/08/01 11:00:00 jens +-- - Change Block names to lower case +-- - Bug Fix RMB, SMB Bug - Bit position decoded wrong. Adding a priority encoder. +-- +-- Revision 1.7 2013/07/21 11:11:00 jens +-- - Changing the title block and internal revision history +-- +-- Revision 1.6 2009/01/04 10:20:47 eda +-- Changes for cosmetic issues only +-- +-- Revision 1.5 2009/01/04 09:23:10 eda +-- - Delete unused nets and blocks (same as R6502_TC) +-- - Rename blocks +-- +-- Revision 1.4 2009/01/03 16:53:02 eda +-- - Unused nets and blocks deleted +-- - Renamed blocks +-- +-- Revision 1.3 2009/01/03 16:42:02 eda +-- - Unused nets and blocks deleted +-- - Renamed blocks +-- +-- Revision 1.2 2008/12/31 19:31:24 eda +-- Production Release +-- +-- +-- +-- VHDL Architecture r65c02_tc.core.struct +-- +-- Created: +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 12:00:34 06.09.2018 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt +-- +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. +-- +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +library r65c02_tc; + +architecture struct of core is + + -- Architecture declarations + + -- Internal signal declarations + signal adr_nxt_pc_o_i : std_logic_vector(15 downto 0); + signal adr_o_i : std_logic_vector(15 downto 0); + signal adr_pc_o_i : std_logic_vector(15 downto 0); + signal adr_sp_o_i : std_logic_vector(15 downto 0); + signal ch_a_o_i : std_logic_vector(7 downto 0); + signal ch_b_o_i : std_logic_vector(7 downto 0); + signal d_alu_n_o_i : std_logic; + signal d_alu_o_i : std_logic_vector(7 downto 0); + signal d_alu_or_o_i : std_logic; + signal d_alu_prio_o_i : std_logic_vector(7 downto 0); + signal d_regs_in_o_i : std_logic_vector(7 downto 0); + signal d_regs_out_o_i : std_logic_vector(7 downto 0); + signal ld_o_i : std_logic_vector(1 downto 0); + signal ld_pc_o_i : std_logic; + signal ld_sp_o_i : std_logic; + signal load_regs_o_i : std_logic; + signal nmi_o_i : std_logic; + signal offset_o_i : std_logic_vector(15 downto 0); + signal q_a_o_i : std_logic_vector(7 downto 0); + signal q_x_o_i : std_logic_vector(7 downto 0); + signal q_y_o_i : std_logic_vector(7 downto 0); + signal reg_0flag_o_i : std_logic; + signal reg_1flag_o_i : std_logic; + signal reg_7flag_o_i : std_logic; + signal rst_nmi_o_i : std_logic; + signal sel_pc_in_o_i : std_logic; + signal sel_pc_val_o_i : std_logic_vector(1 downto 0); + signal sel_rb_in_o_i : std_logic_vector(1 downto 0); + signal sel_rb_out_o_i : std_logic_vector(1 downto 0); + signal sel_reg_o_i : std_logic_vector(1 downto 0); + signal sel_sp_as_o_i : std_logic; + signal sel_sp_in_o_i : std_logic; + signal var_shift_data_o_i : std_logic_vector(7 downto 0); + + + -- Component Declarations + component fsm_execution_unit + port ( + adr_nxt_pc_i : in std_logic_vector (15 downto 0); + adr_pc_i : in std_logic_vector (15 downto 0); + adr_sp_i : in std_logic_vector (15 downto 0); + clk_clk_i : in std_logic ; + d_alu_i : in std_logic_vector ( 7 downto 0 ); + d_alu_prio_i : in std_logic_vector (7 downto 0); + d_i : in std_logic_vector ( 7 downto 0 ); + d_regs_out_i : in std_logic_vector ( 7 downto 0 ); + irq_n_i : in std_logic ; + nmi_i : in std_logic ; + q_a_i : in std_logic_vector ( 7 downto 0 ); + q_x_i : in std_logic_vector ( 7 downto 0 ); + q_y_i : in std_logic_vector ( 7 downto 0 ); + rdy_i : in std_logic ; + reg_0flag_i : in std_logic ; + reg_1flag_i : in std_logic ; + reg_7flag_i : in std_logic ; + rst_rst_n_i : in std_logic ; + so_n_i : in std_logic ; + a_o : out std_logic_vector (15 downto 0); + adr_o : out std_logic_vector (15 downto 0); + ch_a_o : out std_logic_vector ( 7 downto 0 ); + ch_b_o : out std_logic_vector ( 7 downto 0 ); + d_o : out std_logic_vector ( 7 downto 0 ); + d_regs_in_o : out std_logic_vector ( 7 downto 0 ); + ld_o : out std_logic_vector ( 1 downto 0 ); + ld_pc_o : out std_logic ; + ld_sp_o : out std_logic ; + load_regs_o : out std_logic ; + offset_o : out std_logic_vector ( 15 downto 0 ); + rd_o : out std_logic ; + rst_nmi_o : out std_logic ; + sel_pc_in_o : out std_logic ; + sel_pc_val_o : out std_logic_vector ( 1 downto 0 ); + sel_rb_in_o : out std_logic_vector ( 1 downto 0 ); + sel_rb_out_o : out std_logic_vector ( 1 downto 0 ); + sel_reg_o : out std_logic_vector ( 1 downto 0 ); + sel_sp_as_o : out std_logic ; + sel_sp_in_o : out std_logic ; + sync_o : out std_logic ; + wr_n_o : out std_logic ; + wr_o : out std_logic + ); + end component; + component fsm_intnmi + port ( + clk_clk_i : in std_logic ; + nmi_n_i : in std_logic ; + rst_nmi_i : in std_logic ; + rst_rst_n_i : in std_logic ; + nmi_o : out std_logic + ); + end component; + component reg_pc + port ( + adr_i : in std_logic_vector (15 downto 0); + clk_clk_i : in std_logic ; + ld_i : in std_logic_vector (1 downto 0); + ld_pc_i : in std_logic ; + offset_i : in std_logic_vector (15 downto 0); + rst_rst_n_i : in std_logic ; + sel_pc_in_i : in std_logic ; + sel_pc_val_i : in std_logic_vector (1 downto 0); + adr_nxt_pc_o : out std_logic_vector (15 downto 0); + adr_pc_o : out std_logic_vector (15 downto 0) + ); + end component; + component reg_sp + port ( + adr_low_i : in std_logic_vector (7 downto 0); + clk_clk_i : in std_logic ; + ld_low_i : in std_logic ; + ld_sp_i : in std_logic ; + rst_rst_n_i : in std_logic ; + sel_sp_as_i : in std_logic ; + sel_sp_in_i : in std_logic ; + adr_sp_o : out std_logic_vector (15 downto 0) + ); + end component; + component regbank_axy + port ( + clk_clk_i : in std_logic ; + d_regs_in_i : in std_logic_vector (7 downto 0); + load_regs_i : in std_logic ; + rst_rst_n_i : in std_logic ; + sel_rb_in_i : in std_logic_vector (1 downto 0); + sel_rb_out_i : in std_logic_vector (1 downto 0); + sel_reg_i : in std_logic_vector (1 downto 0); + d_regs_out_o : out std_logic_vector (7 downto 0); + q_a_o : out std_logic_vector (7 downto 0); + q_x_o : out std_logic_vector (7 downto 0); + q_y_o : out std_logic_vector (7 downto 0) + ); + end component; + + -- Optional embedded configurations + -- pragma synthesis_off + for all : fsm_execution_unit use entity r65c02_tc.fsm_execution_unit; + for all : fsm_intnmi use entity r65c02_tc.fsm_intnmi; + for all : reg_pc use entity r65c02_tc.reg_pc; + for all : reg_sp use entity r65c02_tc.reg_sp; + for all : regbank_axy use entity r65c02_tc.regbank_axy; + -- pragma synthesis_on + + +begin + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + -- eb1 1 + var_shift_data_o_i <= x"01"; + + + -- ModuleWare code(v1.12) for instance 'U_11' of 'add' + u_11combo_proc: process (ch_a_o_i, ch_b_o_i) + variable temp_din0 : std_logic_vector(8 downto 0); + variable temp_din1 : std_logic_vector(8 downto 0); + variable temp_sum : unsigned(8 downto 0); + variable temp_carry : std_logic; + begin + temp_din0 := '0' & ch_a_o_i; + temp_din1 := '0' & ch_b_o_i; + temp_carry := '0'; + temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry; + d_alu_o_i <= conv_std_logic_vector(temp_sum(7 downto 0),8); + reg_0flag_o_i <= temp_sum(8) ; + end process u_11combo_proc; + + -- ModuleWare code(v1.12) for instance 'U_8' of 'inv' + reg_1flag_o_i <= not(d_alu_or_o_i); + + -- ModuleWare code(v1.12) for instance 'U_9' of 'inv' + reg_7flag_o_i <= not(d_alu_n_o_i); + + -- ModuleWare code(v1.12) for instance 'U_10' of 'inv' + d_alu_n_o_i <= not(d_alu_o_i(7)); + + -- ModuleWare code(v1.12) for instance 'U_5' of 'lshift' + u_5combo_proc : process (var_shift_data_o_i, ch_a_o_i) + variable temp_shift : std_logic_vector (3 downto 0); + variable temp_dout : std_logic_vector (7 downto 0); + variable temp_din : std_logic_vector (7 downto 0); + begin + temp_din := (others=> 'X'); + temp_shift := ch_a_o_i(3 downto 0); + temp_din := var_shift_data_o_i; + for i in 0 to 3 loop + if (i < 3) then + if (temp_shift(i) = '1') then + temp_dout := (others => '0'); + temp_dout(7 downto 2**i) := temp_din(7 - 2**i downto 0); + elsif (temp_shift(i) = '0') then + temp_dout := temp_din; + else + temp_dout := (others => 'X'); + end if; + else + if (temp_shift(i) = '1') then + temp_dout := (others => '0'); + elsif (temp_shift(i) = '0') then + temp_dout := temp_din; + else + temp_dout := (others => 'X'); + end if; + end if; + temp_din := temp_dout; + end loop; + d_alu_prio_o_i <= temp_dout; + end process u_5combo_proc; + + -- ModuleWare code(v1.12) for instance 'U_7' of 'por' + d_alu_or_o_i <= d_alu_o_i(0) or d_alu_o_i(1) or d_alu_o_i(2) or d_alu_o_i(3) or d_alu_o_i(4) or d_alu_o_i(5) or d_alu_o_i(6) or d_alu_o_i(7); + + -- Instance port mappings. + U_4 : fsm_execution_unit + port map ( + adr_nxt_pc_i => adr_nxt_pc_o_i, + adr_pc_i => adr_pc_o_i, + adr_sp_i => adr_sp_o_i, + clk_clk_i => clk_clk_i, + d_alu_i => d_alu_o_i, + d_alu_prio_i => d_alu_prio_o_i, + d_i => d_i, + d_regs_out_i => d_regs_out_o_i, + irq_n_i => irq_n_i, + nmi_i => nmi_o_i, + q_a_i => q_a_o_i, + q_x_i => q_x_o_i, + q_y_i => q_y_o_i, + rdy_i => rdy_i, + reg_0flag_i => reg_0flag_o_i, + reg_1flag_i => reg_1flag_o_i, + reg_7flag_i => reg_7flag_o_i, + rst_rst_n_i => rst_rst_n_i, + so_n_i => so_n_i, + a_o => a_o, + adr_o => adr_o_i, + ch_a_o => ch_a_o_i, + ch_b_o => ch_b_o_i, + d_o => d_o, + d_regs_in_o => d_regs_in_o_i, + ld_o => ld_o_i, + ld_pc_o => ld_pc_o_i, + ld_sp_o => ld_sp_o_i, + load_regs_o => load_regs_o_i, + offset_o => offset_o_i, + rd_o => rd_o, + rst_nmi_o => rst_nmi_o_i, + sel_pc_in_o => sel_pc_in_o_i, + sel_pc_val_o => sel_pc_val_o_i, + sel_rb_in_o => sel_rb_in_o_i, + sel_rb_out_o => sel_rb_out_o_i, + sel_reg_o => sel_reg_o_i, + sel_sp_as_o => sel_sp_as_o_i, + sel_sp_in_o => sel_sp_in_o_i, + sync_o => sync_o, + wr_n_o => wr_n_o, + wr_o => wr_o + ); + U_3 : fsm_intnmi + port map ( + clk_clk_i => clk_clk_i, + nmi_n_i => nmi_n_i, + rst_nmi_i => rst_nmi_o_i, + rst_rst_n_i => rst_rst_n_i, + nmi_o => nmi_o_i + ); + U_0 : reg_pc + port map ( + adr_i => adr_o_i, + clk_clk_i => clk_clk_i, + ld_i => ld_o_i, + ld_pc_i => ld_pc_o_i, + offset_i => offset_o_i, + rst_rst_n_i => rst_rst_n_i, + sel_pc_in_i => sel_pc_in_o_i, + sel_pc_val_i => sel_pc_val_o_i, + adr_nxt_pc_o => adr_nxt_pc_o_i, + adr_pc_o => adr_pc_o_i + ); + U_1 : reg_sp + port map ( + adr_low_i => adr_o_i(7 DOWNTO 0), + clk_clk_i => clk_clk_i, + ld_low_i => ld_o_i(0), + ld_sp_i => ld_sp_o_i, + rst_rst_n_i => rst_rst_n_i, + sel_sp_as_i => sel_sp_as_o_i, + sel_sp_in_i => sel_sp_in_o_i, + adr_sp_o => adr_sp_o_i + ); + U_2 : regbank_axy + port map ( + clk_clk_i => clk_clk_i, + d_regs_in_i => d_regs_in_o_i, + load_regs_i => load_regs_o_i, + rst_rst_n_i => rst_rst_n_i, + sel_rb_in_i => sel_rb_in_o_i, + sel_rb_out_i => sel_rb_out_o_i, + sel_reg_i => sel_reg_o_i, + d_regs_out_o => d_regs_out_o_i, + q_a_o => q_a_o_i, + q_x_o => q_x_o_i, + q_y_o => q_y_o_i + ); + +end struct; Index: cpu65c02_true_cycle/trunk/released/rtl/vhdl/fsm_execution_unit.vhd =================================================================== --- cpu65c02_true_cycle/trunk/released/rtl/vhdl/fsm_execution_unit.vhd (nonexistent) +++ cpu65c02_true_cycle/trunk/released/rtl/vhdl/fsm_execution_unit.vhd (revision 23) @@ -0,0 +1,6080 @@ +-- VHDL Entity r65c02_tc.fsm_execution_unit.symbol +-- +-- Created: +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 15:56:20 27.08.2018 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +entity fsm_execution_unit is + port( + adr_nxt_pc_i : in std_logic_vector (15 downto 0); + adr_pc_i : in std_logic_vector (15 downto 0); + adr_sp_i : in std_logic_vector (15 downto 0); + clk_clk_i : in std_logic; + d_alu_i : in std_logic_vector ( 7 downto 0 ); + d_alu_prio_i : in std_logic_vector (7 downto 0); + d_i : in std_logic_vector ( 7 downto 0 ); + d_regs_out_i : in std_logic_vector ( 7 downto 0 ); + irq_n_i : in std_logic; + nmi_i : in std_logic; + q_a_i : in std_logic_vector ( 7 downto 0 ); + q_x_i : in std_logic_vector ( 7 downto 0 ); + q_y_i : in std_logic_vector ( 7 downto 0 ); + rdy_i : in std_logic; + reg_0flag_i : in std_logic; + reg_1flag_i : in std_logic; + reg_7flag_i : in std_logic; + rst_rst_n_i : in std_logic; + so_n_i : in std_logic; + a_o : out std_logic_vector (15 downto 0); + adr_o : out std_logic_vector (15 downto 0); + ch_a_o : out std_logic_vector ( 7 downto 0 ); + ch_b_o : out std_logic_vector ( 7 downto 0 ); + d_o : out std_logic_vector ( 7 downto 0 ); + d_regs_in_o : out std_logic_vector ( 7 downto 0 ); + ld_o : out std_logic_vector ( 1 downto 0 ); + ld_pc_o : out std_logic; + ld_sp_o : out std_logic; + load_regs_o : out std_logic; + offset_o : out std_logic_vector ( 15 downto 0 ); + rd_o : out std_logic; + rst_nmi_o : out std_logic; + sel_pc_in_o : out std_logic; + sel_pc_val_o : out std_logic_vector ( 1 downto 0 ); + sel_rb_in_o : out std_logic_vector ( 1 downto 0 ); + sel_rb_out_o : out std_logic_vector ( 1 downto 0 ); + sel_reg_o : out std_logic_vector ( 1 downto 0 ); + sel_sp_as_o : out std_logic; + sel_sp_in_o : out std_logic; + sync_o : out std_logic; + wr_n_o : out std_logic; + wr_o : out std_logic + ); + +-- Declarations + +end fsm_execution_unit ; + +-- (C) 2008 - 2018 Jens Gutschmidt +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 1.1202 2018/09/10 12:14:00 jens +-- - RESET generates SYNC now, 1 dead cycle delayed +-- Revision 1.1202 RC 2018/09/09 03:00:00 jens +-- - ADC / SBC flags and A like R65C02 now +-- Revision 1.1202 BETA 2018/09/05 19:35:00 jens +-- - BBRx/BBSx internal cycles like real 65C02 now +-- - Bug Fix ADC and SBC in decimal mode (all op codes - +-- 1 cycle is missing +-- - Bug Fix ADC and SBC in decimal mode (all op codes - +-- "Overflow" flag was computed wrong) +-- Revision 1.1202 BETA 2018/09/02 18:49:00 jens +-- - Interrupt NMI and IRQ processing via FETCH stage now +-- Revision 1.1202 BETA 2018/08/30 15:39:00 jens +-- - Interrupt priority order is now: BRQ - NMI - IRQ +-- - Performance improvements on-going (Mealy -> Moore) +-- Revision 1.1202 BETA 2018/08/23 20:27:00 jens +-- - Bug Fixes All Branch Instructions +-- (BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS, BRA) +-- 3 cycles now if branch forward occur and the branch +-- instruction lies on a xxFEh location. +-- (BBR, BBS) 6 cycles now if branch forward occur and the +-- branch instruction lies on a xxFDh location. +-- - Bug Fix Hardware Interrupts NMI & IRQ - 7 cycles & "SYNC" now +-- - Bug Fix Now all cycles are delayable (WR and internal) +-- +-- Revision 1.1201 BETA 2014/04/19 14:44:00 jens +-- (never submitted to opencores) +-- - Bug Fix JMP ABS - produced a 6502 like JMP (IND) PCH. +-- When the ABS address data bytes cross the page +-- boundary (e.g. $02FE JMP hhll reads hh from +-- $02FF and ll from $0200, instead $02FF and $0300) +-- +-- Revision 1.12 RC 2013/07/31 11:53:00 jens +-- - Bug Fix CMP (IND) - wrongly decoded as function AND +-- - Bug Fix BRK should clear decimal flag P Reg +-- - Bug Fix JMP (ABS,X) - Low Address outputted twice - no High Address +-- - Bug Fix Unknown Ops - Used allways 1b2c NOP ($EA) - new NOPs created +-- - Bug Fix DECIMAL ADC and SBC (all op codes - "C" flag was computed wrong) +-- - Bug Fix INC/DEC ABS,X - N/Z flag wrongly computed +-- - Bug Fix RTI - should increment stack pointer (decremented) +-- - Bug Fix "E" & "B" flags (Bits 5 & 4) - should be always "1" in P Reg. Change "RES", "RTI", "IRQ" & "NMI" substates. +-- - Bug Fix ADC and SBC (all op codes - "Overflow" flag was computed wrong) +-- - Bug Fix RMB, SMB Bug - Bit position decoded wrong. +-- +-- Revision 1.11 2013/07/21 11:11:00 jens +-- - Changing the title block and internal revision history +-- - Bug Fix STA [(IND)] op$92 ($92 was missed in the connection list at state FETCH) +-- +-- Revision 1.10 2010/02/08 17:34:20 eda +-- BUGFIX for IRQn, NMIn and RTI +-- After detection of NMI or IRQ the address of the next instruction stacked wrong. +-- NMI now overwrites the vector address of IRQ if NMI asserted after IRQ and the +-- vector address is not loaded yet. +-- +-- +-- Revision 1.9 2010/02/08 17:32:19 eda +-- BUGFIX for IRQn, NMIn and RTI +-- After detection of NMI or IRQ the address of the next instruction stacked wrong. +-- NMI now overwrites the vector address of IRQ if NMI asserted after IRQ and the +-- vector address is not loaded yet. +-- +-- +-- Revision 1.8 2009/01/04 20:23:42 eda +-- *** EMERGENCY BUGFIX *** +-- - Signal rd_o was corrupted in last version. wr_o and wr_n are not effected. +-- - OP JMP (indirect) produced a 65C02 like jump. On 6502 a special case exist +-- when the (indirect) address cross the page boundary (e.g. JMP (02FF) reads from +-- $02FF and $0200, instead of $02FF and $0300) +-- +-- Revision 1.7 2009/01/04 16:54:59 eda +-- - Removed unused bits in ALU (zw_ALUx) +-- +-- Revision 1.6 2009/01/04 10:27:49 eda +-- Changes for cosmetic issues only +-- +-- Revision 1.5 2009/01/04 10:25:04 eda +-- Changes for cosmetic issues only +-- +-- Revision 1.4 2009/01/03 16:53:01 eda +-- - Unused nets and blocks deleted +-- - Re-arragend symbols in block FSM_Execution_Unit +-- - Renamed blocks +-- - Input SO implemented +-- +-- Revision 1.3 2009/01/03 16:42:02 eda +-- - Unused nets and blocks deleted +-- - Re-arragend symbols in block FSM_Execution_Unit +-- - Renamed blocks +-- - Input SO implemented +-- +-- Revision 1.2 2008/12/31 19:31:24 eda +-- Production Release +-- +-- +-- +-- VHDL Architecture r65c02_tc.fsm_execution_unit.fsm +-- +-- Created: +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 12:21:39 10.09.2018 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt +-- +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. +-- +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +architecture fsm of fsm_execution_unit is + + -- Architecture Declarations + signal reg_F : std_logic_vector( 7 DOWNTO 0 ); + signal reg_PC : std_logic_vector(15 DOWNTO 0); + signal reg_PC1 : std_logic_vector( 15 DOWNTO 0 ); + signal reg_sel_pc_in : std_logic; + signal reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 ); + signal reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 ); + signal reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 ); + signal reg_sel_reg : std_logic_vector( 1 DOWNTO 0 ); + signal reg_sel_sp_as : std_logic; + signal reg_sel_sp_in : std_logic; + signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 ); + signal sig_PC : std_logic_vector(15 DOWNTO 0); + signal sig_RD : std_logic; + signal sig_RWn : std_logic; + signal sig_SYNC : std_logic; + signal sig_WR : std_logic; + signal zw_100_a : std_logic; + signal zw_100_alu : std_logic; + signal zw_100_d : std_logic; + signal zw_50_a : std_logic; + signal zw_50_alu : std_logic; + signal zw_50_d : std_logic; + signal zw_ALU : std_logic_vector(9 DOWNTO 0); + signal zw_ALU1 : std_logic_vector(9 DOWNTO 0); + signal zw_ALU2 : std_logic_vector(9 DOWNTO 0); + signal zw_ALU3 : std_logic_vector(9 DOWNTO 0); + signal zw_ALU4 : std_logic_vector(9 DOWNTO 0); + signal zw_ALU5 : std_logic_vector(9 DOWNTO 0); + signal zw_ALU6 : std_logic_vector(9 DOWNTO 0); + signal zw_PC : std_logic_vector( 15 DOWNTO 0 ); + signal zw_REG_ALU : std_logic_vector( 8 DOWNTO 0 ); + signal zw_REG_OP : std_logic_vector( 7 DOWNTO 0 ); + signal zw_REG_sig_PC : std_logic_vector(15 DOWNTO 0); + signal zw_b1 : std_logic_vector( 7 DOWNTO 0 ); + signal zw_b2 : std_logic_vector( 7 DOWNTO 0 ); + signal zw_b3 : std_logic_vector( 7 DOWNTO 0 ); + signal zw_b4 : std_logic_vector( 7 DOWNTO 0 ); + signal zw_so : std_logic; + signal zw_w1 : std_logic_vector( 15 DOWNTO 0 ); + signal zw_w2 : std_logic_vector( 15 DOWNTO 0 ); + signal zw_w3 : std_logic_vector( 15 DOWNTO 0 ); + + subtype state_type is + std_logic_vector(7 downto 0); + + -- State vector declaration + attribute state_vector : string; + attribute state_vector of fsm : architecture is "current_state"; + + -- Hard encoding + constant s544 : state_type := "00000000"; + constant s545 : state_type := "00000001"; + constant s546 : state_type := "00000011"; + constant s547 : state_type := "00000010"; + constant s549 : state_type := "00000110"; + constant s550 : state_type := "00000111"; + constant RES : state_type := "00000101"; + constant FETCH : state_type := "00000100"; + constant s6 : state_type := "00001100"; + constant s7 : state_type := "00001101"; + constant s8 : state_type := "00001111"; + constant s9 : state_type := "00001110"; + constant s10 : state_type := "00001010"; + constant s13 : state_type := "00001011"; + constant s18 : state_type := "00001001"; + constant s19 : state_type := "00001000"; + constant s26 : state_type := "00011000"; + constant s27 : state_type := "00011001"; + constant s203 : state_type := "00011011"; + constant s204 : state_type := "00011010"; + constant s212 : state_type := "00011110"; + constant s216 : state_type := "00011111"; + constant s219 : state_type := "00011101"; + constant s220 : state_type := "00011100"; + constant s227 : state_type := "00010100"; + constant s228 : state_type := "00010101"; + constant s230 : state_type := "00010111"; + constant s231 : state_type := "00010110"; + constant s229 : state_type := "00010010"; + constant s512 : state_type := "00010011"; + constant s554 : state_type := "00010001"; + constant s578 : state_type := "00010000"; + constant s581 : state_type := "00110000"; + constant s582 : state_type := "00110001"; + constant s583 : state_type := "00110011"; + constant s584 : state_type := "00110010"; + constant s585 : state_type := "00110110"; + constant s586 : state_type := "00110111"; + constant s587 : state_type := "00110101"; + constant s580 : state_type := "00110100"; + constant s178 : state_type := "00111100"; + constant s194 : state_type := "00111101"; + constant s195 : state_type := "00111111"; + constant s196 : state_type := "00111110"; + constant s197 : state_type := "00111010"; + constant s198 : state_type := "00111011"; + constant s199 : state_type := "00111001"; + constant s200 : state_type := "00111000"; + constant s205 : state_type := "00101000"; + constant s206 : state_type := "00101001"; + constant s207 : state_type := "00101011"; + constant s208 : state_type := "00101010"; + constant s209 : state_type := "00101110"; + constant s213 : state_type := "00101111"; + constant s214 : state_type := "00101101"; + constant s513 : state_type := "00101100"; + constant s588 : state_type := "00100100"; + constant s589 : state_type := "00100101"; + constant s590 : state_type := "00100111"; + constant s591 : state_type := "00100110"; + constant s592 : state_type := "00100010"; + constant s593 : state_type := "00100011"; + constant s594 : state_type := "00100001"; + constant s595 : state_type := "00100000"; + constant s596 : state_type := "01100000"; + constant s597 : state_type := "01100001"; + constant s405 : state_type := "01100011"; + constant s408 : state_type := "01100010"; + constant s410 : state_type := "01100110"; + constant s411 : state_type := "01100111"; + constant s414 : state_type := "01100101"; + constant s415 : state_type := "01100100"; + constant s417 : state_type := "01101100"; + constant s419 : state_type := "01101101"; + constant s420 : state_type := "01101111"; + constant s598 : state_type := "01101110"; + constant s599 : state_type := "01101010"; + constant s600 : state_type := "01101011"; + constant s268 : state_type := "01101001"; + constant s305 : state_type := "01101000"; + constant s306 : state_type := "01111000"; + constant jmp1 : state_type := "01111001"; + constant jmp2_1 : state_type := "01111011"; + constant jmp4_12 : state_type := "01111010"; + constant jmp_ex : state_type := "01111110"; + constant jmp2_2 : state_type := "01111111"; + constant jmp3_1 : state_type := "01111101"; + constant s402 : state_type := "01111100"; + constant s421 : state_type := "01110100"; + constant s422 : state_type := "01110101"; + constant s423 : state_type := "01110111"; + constant s424 : state_type := "01110110"; + constant s362 : state_type := "01110010"; + constant s221 : state_type := "01110011"; + constant s232 : state_type := "01110001"; + constant s233 : state_type := "01110000"; + constant s234 : state_type := "01010000"; + constant s235 : state_type := "01010001"; + constant brk1 : state_type := "01010011"; + constant brk2 : state_type := "01010010"; + constant brk3 : state_type := "01010110"; + constant brk4 : state_type := "01010111"; + constant brk6 : state_type := "01010101"; + constant brk5 : state_type := "01010100"; + constant s425 : state_type := "01011100"; + constant s426 : state_type := "01011101"; + constant s427 : state_type := "01011111"; + constant s428 : state_type := "01011110"; + constant s429 : state_type := "01011010"; + constant s430 : state_type := "01011011"; + constant s431 : state_type := "01011001"; + constant s432 : state_type := "01011000"; + constant s433 : state_type := "01001000"; + constant s434 : state_type := "01001001"; + constant s236 : state_type := "01001011"; + constant s245 : state_type := "01001010"; + constant s246 : state_type := "01001110"; + constant s248 : state_type := "01001111"; + constant s345 : state_type := "01001101"; + constant s346 : state_type := "01001100"; + constant s252 : state_type := "01000100"; + constant s253 : state_type := "01000101"; + constant s435 : state_type := "01000111"; + constant s436 : state_type := "01000110"; + constant s437 : state_type := "01000010"; + constant s438 : state_type := "01000011"; + constant s439 : state_type := "01000001"; + constant s440 : state_type := "01000000"; + constant s441 : state_type := "11000000"; + constant s442 : state_type := "11000001"; + constant s443 : state_type := "11000011"; + constant s444 : state_type := "11000010"; + constant irq1 : state_type := "11000110"; + constant irq2 : state_type := "11000111"; + constant irq3 : state_type := "11000101"; + constant irq5b : state_type := "11000100"; + constant irq5a : state_type := "11001100"; + constant irq4 : state_type := "11001101"; + constant irq6 : state_type := "11001111"; + constant s11 : state_type := "11001110"; + constant s12 : state_type := "11001010"; + constant s20 : state_type := "11001011"; + constant s14 : state_type := "11001001"; + constant s21 : state_type := "11001000"; + constant s23 : state_type := "11011000"; + constant s15 : state_type := "11011001"; + constant s25 : state_type := "11011011"; + constant s28 : state_type := "11011010"; + constant s16 : state_type := "11011110"; + constant s30 : state_type := "11011111"; + constant s31 : state_type := "11011101"; + constant s32 : state_type := "11011100"; + constant s33 : state_type := "11010100"; + constant s34 : state_type := "11010101"; + constant s36 : state_type := "11010111"; + constant jmp3_2 : state_type := "11010110"; + constant s601 : state_type := "11010010"; + constant s602 : state_type := "11010011"; + constant s270 : state_type := "11010001"; + constant s307 : state_type := "11010000"; + constant s308 : state_type := "11110000"; + constant s271 : state_type := "11110001"; + constant s272 : state_type := "11110011"; + constant s309 : state_type := "11110010"; + constant RES7 : state_type := "11110110"; + + -- Declare current and next state signals + signal current_state : state_type; + signal next_state : state_type; + + -- Declare any pre-registered internal signals + signal d_o_cld : std_logic_vector ( 7 downto 0 ); + signal rd_o_cld : std_logic ; + signal sync_o_cld : std_logic ; + signal wr_n_o_cld : std_logic ; + signal wr_o_cld : std_logic ; + +begin + + ----------------------------------------------------------------- + clocked_proc : process ( + clk_clk_i, + rst_rst_n_i + ) + ----------------------------------------------------------------- + begin + if (rst_rst_n_i = '0') then + current_state <= RES; + -- Default Reset Values + d_o_cld <= X"00"; + rd_o_cld <= '1'; + sync_o_cld <= '0'; + wr_n_o_cld <= '1'; + wr_o_cld <= '0'; + reg_F <= "00110100"; + reg_PC <= X"0000"; + reg_PC1 <= X"0000"; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_rb_in <= "00"; + reg_sel_rb_out <= "00"; + reg_sel_reg <= "00"; + reg_sel_sp_as <= '0'; + reg_sel_sp_in <= '0'; + sig_PC <= X"0000"; + zw_PC <= X"0000"; + zw_REG_ALU <= '0' & X"00"; + zw_REG_OP <= X"00"; + zw_REG_sig_PC <= X"0000"; + zw_b1 <= X"00"; + zw_b2 <= X"00"; + zw_b3 <= X"00"; + zw_b4 <= X"00"; + zw_so <= '0'; + zw_w1 <= X"0000"; + zw_w2 <= X"0000"; + zw_w3 <= X"0000"; + elsif (clk_clk_i'event and clk_clk_i = '1') then + current_state <= next_state; + -- Default Assignment To Internals + reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0); + reg_PC <= reg_PC; + reg_PC1 <= reg_PC1; + reg_sel_pc_in <= reg_sel_pc_in; + reg_sel_pc_val <= reg_sel_pc_val; + reg_sel_rb_in <= reg_sel_rb_in; + reg_sel_rb_out <= reg_sel_rb_out; + reg_sel_reg <= reg_sel_reg; + reg_sel_sp_as <= reg_sel_sp_as; + reg_sel_sp_in <= reg_sel_sp_in; + sig_PC <= sig_PC; + zw_PC <= zw_PC; + zw_REG_ALU <= zw_REG_ALU; + zw_REG_OP <= zw_REG_OP; + zw_REG_sig_PC <= zw_REG_sig_PC; + zw_b1 <= zw_b1; + zw_b2 <= zw_b2; + zw_b3 <= zw_b3; + zw_b4 <= zw_b4; + zw_so <= (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6))); + zw_w1 <= zw_w1; + zw_w2 <= zw_w2; + zw_w3 <= zw_w3; + d_o_cld <= sig_D_OUT; + rd_o_cld <= sig_RD; + sync_o_cld <= sig_SYNC; + wr_n_o_cld <= sig_RWn; + wr_o_cld <= sig_WR; + + -- Combined Actions + case current_state is + when s544 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s545 => + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s546 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + end if; + when s547 => + zw_w1 (7 downto 0) <= d_i; + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '1'; + reg_sel_pc_val <= "11"; + end if; + when s549 => + reg_F(2) <= '1'; + reg_F(3) <= '0'; + reg_F(5) <= '1'; + if (rdy_i = '1') then + sig_PC <= d_i & zw_w1 (7 downto 0); + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s550 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + reg_sel_pc_in <= '1'; + reg_sel_pc_val <= "00"; + end if; + when RES => + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + when FETCH => + zw_REG_OP <= d_i; + if ((d_i = X"00") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((nmi_i = '1') and (rdy_i = '1')) then + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + sig_PC <= adr_nxt_pc_i; + zw_w3 <= adr_pc_i; + elsif ((irq_n_i = '0' and + reg_F(2) = '0') and (rdy_i = '1')) then + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + sig_PC <= adr_nxt_pc_i; + zw_w3 <= adr_pc_i; + elsif ((d_i = X"58") and (rdy_i = '1')) then + elsif ((d_i = X"28") and (rdy_i = '1')) then + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '0'; + elsif ((d_i = X"78") and (rdy_i = '1')) then + elsif ((d_i = X"69" or + d_i = X"65" or + d_i = X"75" or + d_i = X"6D" or + d_i = X"7D" or + d_i = X"79" or + d_i = X"61" or + d_i = X"71" or + d_i = X"72") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + reg_sel_reg <= "00"; + reg_sel_rb_in <= "11"; + elsif ((d_i = X"06" or + d_i = X"16" or + d_i = X"0E" or + d_i = X"1E" or + d_i (3 downto 0) = X"7" or + d_i = X"14" or + d_i = X"04" or + d_i = X"0C" or + d_i = X"1C") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"90" or + d_i = X"B0" or + d_i = X"F0" or + d_i = X"30" or + d_i = X"D0" or + d_i = X"10" or + d_i = X"50" or + d_i = X"70" or + d_i = X"80") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"24" or + d_i = X"2C" or + d_i = X"3C" or + d_i = X"34" or + d_i = X"89") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"18") and (rdy_i = '1')) then + elsif ((d_i = X"D8") and (rdy_i = '1')) then + elsif ((d_i = X"8F" or + d_i = X"9F" or + d_i = X"AF" or + d_i = X"BF" or + d_i = X"CF" or + d_i = X"DF" or + d_i = X"EF" or + d_i = X"FF" or + d_i = X"0F" or + d_i = X"1F" or + d_i = X"2F" or + d_i = X"3F" or + d_i = X"4F" or + d_i = X"5F" or + d_i = X"6F" or + d_i = X"7F") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"B8") and (rdy_i = '1')) then + elsif ((d_i = X"E0" or + d_i = X"E4" or + d_i = X"EC") and (rdy_i = '1')) then + reg_sel_rb_out <= "01"; + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"C0" or + d_i = X"C4" or + d_i = X"CC") and (rdy_i = '1')) then + reg_sel_rb_out <= "10"; + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"C6" or + d_i = X"D6" or + d_i = X"CE" or + d_i = X"DE") and (rdy_i = '1')) then + zw_b4 <= X"FF"; + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"CA") and (rdy_i = '1')) then + reg_sel_rb_out <= "01"; + reg_sel_reg <= "01"; + reg_sel_rb_in <= "11"; + zw_b4 <= X"FF"; + elsif ((d_i = X"88") and (rdy_i = '1')) then + reg_sel_rb_out <= "10"; + reg_sel_reg <= "10"; + reg_sel_rb_in <= "11"; + zw_b4 <= X"FF"; + elsif ((d_i = X"49" or + d_i = X"45" or + d_i = X"55" or + d_i = X"4D" or + d_i = X"5D" or + d_i = X"59" or + d_i = X"41" or + d_i = X"51" or + d_i = X"09" or + d_i = X"05" or + d_i = X"15" or + d_i = X"0D" or + d_i = X"1D" or + d_i = X"19" or + d_i = X"01" or + d_i = X"11" or + d_i = X"29" or + d_i = X"25" or + d_i = X"35" or + d_i = X"2D" or + d_i = X"3D" or + d_i = X"39" or + d_i = X"21" or + d_i = X"31" or + d_i = X"C9" or + d_i = X"C5" or + d_i = X"D5" or + d_i = X"CD" or + d_i = X"DD" or + d_i = X"D9" or + d_i = X"C1" or + d_i = X"D1" or + d_i = X"32" or + d_i = X"D2" or + d_i = X"52" or + d_i = X"12") and (rdy_i = '1')) then + reg_sel_rb_out <= "00"; + reg_sel_reg <= "00"; + reg_sel_rb_in <= "11"; + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"E6" or + d_i = X"F6" or + d_i = X"EE" or + d_i = X"FE") and (rdy_i = '1')) then + zw_b4 <= X"01"; + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"E8") and (rdy_i = '1')) then + reg_sel_rb_out <= "01"; + reg_sel_reg <= "01"; + reg_sel_rb_in <= "11"; + zw_b4 <= X"01"; + elsif ((d_i = X"C8") and (rdy_i = '1')) then + reg_sel_rb_out <= "10"; + reg_sel_reg <= "10"; + reg_sel_rb_in <= "11"; + zw_b4 <= X"01"; + elsif ((d_i = X"4C" or + d_i = X"6C" or + d_i = X"7C") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"20") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"A9" or + d_i = X"A5" or + d_i = X"B5" or + d_i = X"AD" or + d_i = X"BD" or + d_i = X"B9" or + d_i = X"A1" or + d_i = X"B1" or + d_i = X"B2") and (rdy_i = '1')) then + reg_sel_reg <= "00"; + reg_sel_rb_in <= "11"; + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"A2" or + d_i = X"A6" or + d_i = X"B6" or + d_i = X"AE" or + d_i = X"BE") and (rdy_i = '1')) then + reg_sel_reg <= "01"; + reg_sel_rb_in <= "11"; + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"A0" or + d_i = X"A4" or + d_i = X"B4" or + d_i = X"AC" or + d_i = X"BC") and (rdy_i = '1')) then + reg_sel_reg <= "10"; + reg_sel_rb_in <= "11"; + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"46" or + d_i = X"56" or + d_i = X"4E" or + d_i = X"5E") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"EA") and (rdy_i = '1')) then + elsif ((d_i = X"48") and (rdy_i = '1')) then + reg_sel_rb_out <= "00"; + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"08") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"7A") and (rdy_i = '1')) then + reg_sel_reg <= "10"; + reg_sel_rb_in <= "11"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '0'; + elsif ((d_i = X"26" or + d_i = X"36" or + d_i = X"2E" or + d_i = X"3E") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"66" or + d_i = X"76" or + d_i = X"6E" or + d_i = X"7E") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"40") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '0'; + elsif ((d_i = X"60") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '0'; + elsif ((d_i = X"E9" or + d_i = X"E5" or + d_i = X"F5" or + d_i = X"ED" or + d_i = X"FD" or + d_i = X"F9" or + d_i = X"E1" or + d_i = X"F1" or + d_i = X"F2") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + reg_sel_reg <= "00"; + reg_sel_rb_in <= "11"; + elsif ((d_i = X"38") and (rdy_i = '1')) then + elsif ((d_i = X"F8") and (rdy_i = '1')) then + elsif ((d_i = X"85" or + d_i = X"95" or + d_i = X"8D" or + d_i = X"9D" or + d_i = X"99" or + d_i = X"81" or + d_i = X"91" or + d_i = X"92") and (rdy_i = '1')) then + reg_sel_rb_out <= "00"; + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"86" or + d_i = X"96" or + d_i = X"8E") and (rdy_i = '1')) then + reg_sel_rb_out <= "01"; + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"84" or + d_i = X"94" or + d_i = X"8C") and (rdy_i = '1')) then + reg_sel_rb_out <= "10"; + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"AA") and (rdy_i = '1')) then + reg_sel_rb_out <= "00"; + reg_sel_reg <= "01"; + reg_sel_rb_in <= "00"; + reg_sel_sp_in <= '1'; + reg_sel_sp_as <= '0'; + elsif ((d_i = X"0A") and (rdy_i = '1')) then + reg_sel_rb_out <= "00"; + reg_sel_reg <= "00"; + reg_sel_rb_in <= "11"; + elsif ((d_i = X"4A") and (rdy_i = '1')) then + reg_sel_rb_out <= "00"; + reg_sel_reg <= "00"; + reg_sel_rb_in <= "11"; + elsif ((d_i = X"2A") and (rdy_i = '1')) then + reg_sel_rb_out <= "00"; + reg_sel_reg <= "00"; + reg_sel_rb_in <= "11"; + elsif ((d_i = X"6A") and (rdy_i = '1')) then + reg_sel_rb_out <= "00"; + reg_sel_reg <= "00"; + reg_sel_rb_in <= "11"; + elsif ((d_i = X"A8") and (rdy_i = '1')) then + reg_sel_rb_out <= "00"; + reg_sel_reg <= "10"; + reg_sel_rb_in <= "00"; + reg_sel_sp_in <= '1'; + reg_sel_sp_as <= '0'; + elsif ((d_i = X"98") and (rdy_i = '1')) then + reg_sel_rb_out <= "10"; + reg_sel_reg <= "00"; + reg_sel_rb_in <= "01"; + reg_sel_sp_in <= '1'; + reg_sel_sp_as <= '0'; + elsif ((d_i = X"BA") and (rdy_i = '1')) then + reg_sel_rb_out <= "01"; + reg_sel_reg <= "01"; + reg_sel_rb_in <= "11"; + reg_sel_sp_in <= '1'; + reg_sel_sp_as <= '0'; + elsif ((d_i = X"8A") and (rdy_i = '1')) then + reg_sel_rb_out <= "01"; + reg_sel_reg <= "00"; + reg_sel_rb_in <= "10"; + reg_sel_sp_in <= '1'; + reg_sel_sp_as <= '0'; + elsif ((d_i = X"9A") and (rdy_i = '1')) then + reg_sel_rb_out <= "01"; + reg_sel_reg <= "11"; + reg_sel_rb_in <= "11"; + reg_sel_sp_in <= '1'; + reg_sel_sp_as <= '0'; + elsif ((d_i = X"DA") and (rdy_i = '1')) then + reg_sel_rb_out <= "01"; + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"5A") and (rdy_i = '1')) then + reg_sel_rb_out <= "10"; + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"68") and (rdy_i = '1')) then + reg_sel_reg <= "00"; + reg_sel_rb_in <= "11"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '0'; + elsif ((d_i = X"FA") and (rdy_i = '1')) then + reg_sel_reg <= "01"; + reg_sel_rb_in <= "11"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '0'; + elsif ((d_i = X"9C" or + d_i = X"9E" or + d_i = X"64" or + d_i = X"74") and (rdy_i = '1')) then + reg_sel_rb_out <= "11"; + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"3A") and (rdy_i = '1')) then + reg_sel_rb_out <= "00"; + reg_sel_reg <= "00"; + reg_sel_rb_in <= "11"; + zw_b4 <= X"FF"; + elsif ((d_i = X"1A") and (rdy_i = '1')) then + reg_sel_rb_out <= "00"; + reg_sel_reg <= "00"; + reg_sel_rb_in <= "11"; + zw_b4 <= X"01"; + elsif ((d_i = X"EA") and (rdy_i = '1')) then + elsif ((d_i = X"02" or + d_i = X"22" or + d_i = X"42" or + d_i = X"62" or + d_i = X"82" or + d_i = X"C2" or + d_i = X"E2") and (rdy_i = '1')) then + elsif ((d_i = X"44") and (rdy_i = '1')) then + elsif ((d_i = X"54" or + d_i = X"D4" or + d_i = X"F4") and (rdy_i = '1')) then + elsif ((d_i = X"DC" or + d_i = X"FC") and (rdy_i = '1')) then + elsif ((d_i = X"5C") and (rdy_i = '1')) then + elsif ((d_i(3 downto 0) = X"3" or + d_i(3 downto 0) = X"B") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s6 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s7 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(0) <= '1'; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s8 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(3) <= '1'; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s9 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(2) <= '1'; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s10 => + if (rdy_i = '1' and + zw_REG_OP = X"9A") then + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"BA") then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s13 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(0) <= '0'; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s18 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(3) <= '0'; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s19 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(2) <= '0'; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s26 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(6) <= '0'; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s27 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s203 => + if (rdy_i = '1' and + (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR + zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR + zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR + zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then + sig_PC <= X"00" & d_i; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11" or + zw_REG_OP = X"12")) then + sig_PC <= adr_nxt_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51" or + zw_REG_OP = X"52")) then + sig_PC <= adr_nxt_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31" or + zw_REG_OP = X"32")) then + sig_PC <= adr_nxt_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or + zw_REG_OP = X"D2")) then + sig_PC <= adr_nxt_pc_i; + reg_F(7) <= zw_ALU(7); + reg_F(0) <= zw_ALU(8); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then + sig_PC <= adr_nxt_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B5" OR + zw_REG_OP = X"B4" OR + zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR + zw_REG_OP = X"35" OR + zw_REG_OP = X"D5")) then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"AD" OR + zw_REG_OP = X"AE" OR + zw_REG_OP = X"AC" OR + zw_REG_OP = X"4D" OR + zw_REG_OP = X"0D" OR + zw_REG_OP = X"2D" OR + zw_REG_OP = X"CD" OR + zw_REG_OP = X"EC" OR + zw_REG_OP = X"CC")) then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"BD" OR + zw_REG_OP = X"BC" OR + zw_REG_OP = X"5D" OR + zw_REG_OP = X"1D" OR + zw_REG_OP = X"3D" OR + zw_REG_OP = X"DD")) then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B9" OR + zw_REG_OP = X"BE" OR + zw_REG_OP = X"59" OR + zw_REG_OP = X"19" OR + zw_REG_OP = X"39" OR + zw_REG_OP = X"D9")) then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B1" OR + zw_REG_OP = X"51" OR + zw_REG_OP = X"11" OR + zw_REG_OP = X"31" OR + zw_REG_OP = X"D1")) then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"A1" OR + zw_REG_OP = X"41" OR + zw_REG_OP = X"01" OR + zw_REG_OP = X"21" OR + zw_REG_OP = X"C1")) then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"B6") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"32" OR + zw_REG_OP = X"D2" OR + zw_REG_OP = X"52" OR + zw_REG_OP = X"B2" OR + zw_REG_OP = X"12")) then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + end if; + when s204 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + end if; + when s212 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s216 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + end if; + when s219 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s220 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s227 => + if (rdy_i = '1') then + sig_PC <= X"00" & d_alu_i; + zw_b1 <= d_i; + end if; + when s228 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s230 => + if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11" or + zw_REG_OP = X"12")) then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51" or + zw_REG_OP = X"52")) then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31" or + zw_REG_OP = X"32")) then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or + zw_REG_OP = X"D2")) then + sig_PC <= adr_pc_i; + reg_F(7) <= zw_ALU(7); + reg_F(0) <= zw_ALU(8); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s231 => + if ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11" or + zw_REG_OP = X"12")) then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51" or + zw_REG_OP = X"52")) then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31" or + zw_REG_OP = X"32")) then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or + zw_REG_OP = X"D2")) then + sig_PC <= adr_pc_i; + reg_F(7) <= zw_ALU(7); + reg_F(0) <= zw_ALU(8); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1' AND + zw_b2(0) = '0') then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1') then + sig_PC <= zw_b3 & zw_b1; + end if; + when s229 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + zw_b1 <= d_i; + end if; + when s512 => + if (rdy_i = '1' and + zw_REG_OP = X"65") then + sig_PC <= X"00" & d_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"69" and + reg_F(3) = '0') then + sig_PC <= adr_nxt_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR + (NOT zw_ALU(7) AND (q_a_i(7)) AND (d_i(7))); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU(8); + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"75") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"6D") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"7D") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"79") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"71") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"61") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"69" and + reg_F(3) = '1') then + sig_PC <= adr_nxt_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= (zw_ALU5(3) XOR q_a_i(7)) AND (NOT (q_a_i(7) XOR d_i(7))); + reg_F(1) <= NOT (zw_ALU(7) OR zw_ALU(6) OR zw_ALU(5) OR + zw_ALU(4) OR zw_ALU(3) OR zw_ALU(2) OR zw_ALU(1) OR + zw_ALU(0)); + reg_F(0) <= zw_ALU4(4); + elsif (rdy_i = '1' and + zw_REG_OP = X"72") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + end if; + when s554 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + end if; + when s578 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s581 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + end if; + when s582 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s583 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s584 => + if (rdy_i = '1') then + sig_PC <= X"00" & d_alu_i; + zw_b1 <= d_i; + end if; + when s585 => + if (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '0') then + sig_PC <= adr_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR + (NOT zw_ALU(7) AND (q_a_i(7)) AND (d_i(7))); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU(8); + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '1') then + sig_PC <= adr_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= (zw_ALU5(3) XOR q_a_i(7)) AND (NOT (q_a_i(7) XOR d_i(7))); + reg_F(1) <= NOT (zw_ALU(7) OR zw_ALU(6) OR zw_ALU(5) OR + zw_ALU(4) OR zw_ALU(3) OR zw_ALU(2) OR zw_ALU(1) OR + zw_ALU(0)); + reg_F(0) <= zw_ALU4(4); + elsif (rdy_i = '1') then + sig_PC <= zw_b3 & zw_b1; + end if; + when s586 => + if (rdy_i = '1' and + reg_F(3) = '0') then + sig_PC <= adr_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR + (NOT zw_ALU(7) AND (q_a_i(7)) AND (d_i(7))); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU(8); + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1' and + reg_F(3) = '1') then + sig_PC <= adr_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= (zw_ALU5(3) XOR q_a_i(7)) AND (NOT (q_a_i(7) XOR d_i(7))); + reg_F(1) <= NOT (zw_ALU(7) OR zw_ALU(6) OR zw_ALU(5) OR + zw_ALU(4) OR zw_ALU(3) OR zw_ALU(2) OR zw_ALU(1) OR + zw_ALU(0)); + reg_F(0) <= zw_ALU4(4); + end if; + when s587 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s580 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + zw_b1 <= d_i; + end if; + when s178 => + if (rdy_i = '1' and + (zw_REG_OP = X"85" OR + zw_REG_OP = X"86" OR + zw_REG_OP = X"64" OR + zw_REG_OP = X"84")) then + sig_PC <= X"00" & d_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"95" OR + zw_REG_OP = X"74" OR + zw_REG_OP = X"94")) then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"8D" OR + zw_REG_OP = X"8E" OR + zw_REG_OP = X"9C" OR + zw_REG_OP = X"8C")) then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"9D" OR + zw_REG_OP = X"9E")) then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"99") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"91") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"81") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"96") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"92") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + end if; + when s194 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s195 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + end if; + when s196 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + end if; + when s197 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s198 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s199 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s200 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s205 => + if (rdy_i = '1') then + sig_PC <= X"00" & d_alu_i; + zw_b1 <= d_i; + end if; + when s206 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s207 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s208 => + if (rdy_i = '1') then + sig_PC <= zw_b3 & zw_b1; + end if; + when s209 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + end if; + when s213 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s214 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + zw_b1 <= d_i; + end if; + when s513 => + if (rdy_i = '1' and + zw_REG_OP = X"E5") then + sig_PC <= X"00" & d_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"E9" and + reg_F(3) = '0') then + sig_PC <= adr_nxt_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (d_i(7))) OR + (NOT zw_ALU(7) AND (q_a_i(7)) AND (NOT d_i(7))); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= (zw_ALU(8) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR + (zw_ALU(8) AND (q_a_i(7)) AND (d_i(7))) OR + (NOT zw_ALU(8) AND (q_a_i(7)) AND (NOT d_i(7))) OR + (zw_ALU(8) AND (q_a_i(7)) AND (NOT d_i(7))); + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"F5") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"ED") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"FD") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"F9") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"F1") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"E1") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"E9" and + reg_F(3) = '1') then + sig_PC <= adr_nxt_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= (zw_ALU2(3) XOR q_a_i(7)) AND (q_a_i(7) XOR d_i(7)); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= (zw_ALU2(4)); + elsif (rdy_i = '1' and + zw_REG_OP = X"F2") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + end if; + when s588 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + end if; + when s589 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s590 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + end if; + when s591 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s592 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s593 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s594 => + if (rdy_i = '1') then + sig_PC <= X"00" & d_alu_i; + zw_b1 <= d_i; + end if; + when s595 => + if (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '0') then + sig_PC <= adr_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (d_i(7))) OR + (NOT zw_ALU(7) AND (q_a_i(7)) AND (NOT d_i(7))); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= (zw_ALU(8) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR + (zw_ALU(8) AND (q_a_i(7)) AND (d_i(7))) OR + (NOT zw_ALU(8) AND (q_a_i(7)) AND (NOT d_i(7))) OR + (zw_ALU(8) AND (q_a_i(7)) AND (NOT d_i(7))); + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '1') then + sig_PC <= adr_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= (zw_ALU2(3) XOR q_a_i(7)) AND (q_a_i(7) XOR d_i(7)); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= (zw_ALU2(4)); + elsif (rdy_i = '1') then + sig_PC <= zw_b3 & zw_b1; + end if; + when s596 => + if (rdy_i = '1' and + reg_F(3) = '0') then + sig_PC <= adr_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (d_i(7))) OR + (NOT zw_ALU(7) AND (q_a_i(7)) AND (NOT d_i(7))); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= (zw_ALU(8) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR + (zw_ALU(8) AND (q_a_i(7)) AND (d_i(7))) OR + (NOT zw_ALU(8) AND (q_a_i(7)) AND (NOT d_i(7))) OR + (zw_ALU(8) AND (q_a_i(7)) AND (NOT d_i(7))); + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1' and + reg_F(3) = '1') then + sig_PC <= adr_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= (zw_ALU2(3) XOR q_a_i(7)) AND (q_a_i(7) XOR d_i(7)); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= (zw_ALU2(4)); + end if; + when s597 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + zw_b1 <= d_i; + end if; + when s405 => + if (rdy_i = '1' and + (zw_REG_OP = X"1E" or + zw_REG_OP = X"7E" or + zw_REG_OP = X"3E" or + zw_REG_OP = X"5E")) then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"06" or zw_REG_OP = X"66" or + zw_REG_OP = X"26" or zw_REG_OP = X"46" or + zw_REG_OP = X"04" or zw_REG_OP = X"14")) then + sig_PC <= X"00" & d_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"16" or + zw_REG_OP = X"76" or + zw_REG_OP = X"36" or + zw_REG_OP = X"56")) then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"0E" or + zw_REG_OP = X"6E" or + zw_REG_OP = X"2E" or + zw_REG_OP = X"4E"or + zw_REG_OP = X"0C" or + zw_REG_OP = X"1C")) then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + elsif (rdy_i = '1' and + zw_REG_OP (3 downto 0) = X"7") then + sig_PC <= X"00" & d_i; + end if; + when s408 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + end if; + when s410 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s411 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s414 => + if (rdy_i = '1') then + sig_PC <= zw_b3 & zw_b1; + end if; + when s417 => + if ((rdy_i = '1' and + (zw_REG_OP = X"06" or + zw_REG_OP = X"16" or + zw_REG_OP = X"0E" or + zw_REG_OP = X"1E")) and (rdy_i = '1')) then + zw_b1 <= d_i(6 downto 0) & '0'; + zw_b2(0) <= d_i(7); + elsif ((rdy_i = '1' and + (zw_REG_OP = X"46" or + zw_REG_OP = X"56" or + zw_REG_OP = X"4E" or + zw_REG_OP = X"5E")) and (rdy_i = '1')) then + zw_b1 <= '0' & d_i(7 downto 1); + zw_b2(0) <= d_i(0); + elsif ((rdy_i = '1' and + (zw_REG_OP = X"26" or + zw_REG_OP = X"36" or + zw_REG_OP = X"2E" or + zw_REG_OP = X"3E")) and (rdy_i = '1')) then + zw_b1 <= d_i(6 downto 0) & reg_F(0); + zw_b2(0) <= d_i(7); + elsif ((rdy_i = '1' and + (zw_REG_OP = X"66" or + zw_REG_OP = X"76" or + zw_REG_OP = X"6E" or + zw_REG_OP = X"7E")) and (rdy_i = '1')) then + zw_b1 <= reg_F(0) & d_i(7 downto 1); + zw_b2(0) <= d_i(0); + elsif ((rdy_i = '1' and + zw_REG_OP (7) = '0' and + zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then + elsif ((rdy_i = '1' and + zw_REG_OP (7) = '1' and + zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then + elsif ((rdy_i = '1' and + (zw_REG_OP = X"14" or + zw_REG_OP = X"1C")) and (rdy_i = '1')) then + zw_b1 <= d_i and q_a_i; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"04" or + zw_REG_OP = X"0C")) and (rdy_i = '1')) then + zw_b1 <= d_i and q_a_i; + end if; + when s419 => + if ((zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (((zw_REG_OP = X"14" or + zw_REG_OP = X"04" or + zw_REG_OP = X"0C" or + zw_REG_OP = X"1C")) and (rdy_i = '1')) then + reg_F(1) <= reg_1flag_i; + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1') then + reg_F(0) <= zw_b2(0); + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s420 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(0) <= q_a_i(7); + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s598 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(0) <= q_a_i(0); + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s599 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(0) <= q_a_i(0); + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s600 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(0) <= q_a_i(7); + reg_F(0) <= q_a_i(7); + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s268 => + zw_b1 <= d_i; + zw_b3 <= adr_nxt_pc_i (15 downto 8); + zw_b2 <= d_i; + if (rdy_i = '1' and ( + (reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or + (reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or + (reg_F(1) = '1' and zw_REG_OP = X"D0") or (reg_F(7) = '1' and zw_REG_OP = X"10") or + (reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) then + sig_PC <= adr_nxt_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1') then + sig_PC <= adr_nxt_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "10"; + end if; + when s305 => + if (rdy_i = '1' and + zw_b3 = adr_nxt_pc_i (15 downto 8)) then + sig_PC <= adr_nxt_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1') then + sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0); + end if; + when s306 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when jmp1 => + zw_b1 <= d_i; + if (rdy_i = '1' and + zw_REG_OP = X"4C") then + sig_PC <= adr_nxt_pc_i; + reg_sel_pc_in <= '1'; + reg_sel_pc_val <= "11"; + elsif (rdy_i = '1' and + zw_REG_OP = X"6C") then + sig_PC <= adr_nxt_pc_i; + reg_sel_pc_in <= '1'; + reg_sel_pc_val <= "00"; + elsif (rdy_i = '1' and + zw_REG_OP = X"7C") then + sig_PC <= adr_nxt_pc_i; + reg_sel_pc_in <= '1'; + reg_sel_pc_val <= "10"; + end if; + when jmp2_1 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + end if; + when jmp4_12 => + zw_b1 <= d_i; + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '1'; + reg_sel_pc_val <= "11"; + end if; + when jmp_ex => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when jmp2_2 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + end if; + when s402 => + zw_b1 <= d_i; + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s422 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s423 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '1'; + reg_sel_pc_val <= "11"; + end if; + when s424 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1 (7 downto 0); + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s362 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + end if; + when s221 => + if (rdy_i = '1' and + zw_REG_OP = X"34") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"3C") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"24") then + sig_PC <= X"00" & d_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"2C") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"89") then + sig_PC <= adr_nxt_pc_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s232 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s233 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s234 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(7) <= d_i(7); + reg_F(6) <= d_i(6); + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s235 => + if (rdy_i = '1' AND + zw_b2(0) = '0') then + sig_PC <= adr_pc_i; + reg_F(7) <= d_i(7); + reg_F(6) <= d_i(6); + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1') then + sig_PC <= zw_b3 & zw_b1; + end if; + when brk1 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when brk2 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when brk3 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when brk4 => + if (rdy_i = '1') then + sig_PC <= X"FFFE"; + end if; + when brk6 => + reg_F(2) <= '1'; + reg_F(3) <= '0'; + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when brk5 => + zw_b1 <= d_i; + if (rdy_i = '1') then + sig_PC <= X"FFFF"; + reg_sel_pc_in <= '1'; + reg_sel_pc_val <= "11"; + end if; + when s425 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s426 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s427 => + reg_F(7 downto 6) <= d_i(7 downto 6); + reg_F(3 downto 0) <= d_i(3 downto 0); + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + reg_sel_pc_in <= '1'; + reg_sel_pc_val <= "11"; + end if; + when s428 => + zw_b1 <= d_i; + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s429 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s430 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s431 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s432 => + zw_b1 <= d_i; + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + reg_sel_pc_in <= '1'; + reg_sel_pc_val <= "00"; + end if; + when s433 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + end if; + when s434 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s236 => + if (rdy_i = '1' and + (zw_REG_OP = X"C6" OR + zw_REG_OP = X"E6")) then + sig_PC <= X"00" & d_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"D6" OR + zw_REG_OP = X"F6")) then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"CE" OR + zw_REG_OP = X"EE")) then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"DE" OR + zw_REG_OP = X"FE")) then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + end if; + when s245 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + end if; + when s246 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s248 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s345 => + if (rdy_i = '1') then + sig_PC <= zw_b3 & zw_b1; + end if; + when s346 => + if (rdy_i = '1') then + zw_b1 <= d_alu_i; + end if; + when s253 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s435 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s436 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s437 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s438 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s440 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s441 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s443 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s444 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(7 downto 6) <= d_i(7 downto 6); + reg_F(3 downto 0) <= d_i(3 downto 0); + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when irq1 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when irq2 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when irq3 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when irq5b => + zw_b1 <= d_i; + if (rdy_i = '1') then + sig_PC <= X"FFFF"; + reg_sel_pc_in <= '1'; + reg_sel_pc_val <= "11"; + end if; + when irq5a => + zw_b1 <= d_i; + if (rdy_i = '1') then + sig_PC <= X"FFFB"; + reg_sel_pc_in <= '1'; + reg_sel_pc_val <= "11"; + end if; + when irq4 => + if (rdy_i = '1' and + nmi_i = '1') then + sig_PC <= X"FFFA"; + elsif (rdy_i = '1') then + sig_PC <= X"FFFE"; + end if; + when irq6 => + reg_F(2) <= '1'; + reg_F(3) <= '0'; + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s11 => + if (rdy_i = '1') then + sig_PC <= adr_nxt_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s20 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s23 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s28 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s33 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when jmp3_2 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + end if; + when s601 => + if (rdy_i = '1') then + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s602 => + if (rdy_i = '1') then + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s270 => + if (rdy_i = '1') then + sig_PC <= X"00" & d_i; + end if; + when s307 => + if (rdy_i = '1' and + zw_b3 = adr_nxt_pc_i (15 downto 8)) then + sig_PC <= adr_nxt_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1') then + sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0); + end if; + when s308 => + zw_b2 <= d_i; + zw_b3 <= adr_nxt_pc_i (15 downto 8); + if (rdy_i = '1' and ( + (zw_b1(0) = '0' and zw_REG_OP = X"8F") or + (zw_b1(1) = '0' and zw_REG_OP = X"9F") or + (zw_b1(2) = '0' and zw_REG_OP = X"AF") or + (zw_b1(3) = '0' and zw_REG_OP = X"BF") or + (zw_b1(4) = '0' and zw_REG_OP = X"CF") or + (zw_b1(5) = '0' and zw_REG_OP = X"DF") or + (zw_b1(6) = '0' and zw_REG_OP = X"EF") or + (zw_b1(7) = '0' and zw_REG_OP = X"FF") or + (zw_b1(0) = '1' and zw_REG_OP = X"0F") or + (zw_b1(1) = '1' and zw_REG_OP = X"1F") or + (zw_b1(2) = '1' and zw_REG_OP = X"2F") or + (zw_b1(3) = '1' and zw_REG_OP = X"3F") or + (zw_b1(4) = '1' and zw_REG_OP = X"4F") or + (zw_b1(5) = '1' and zw_REG_OP = X"5F") or + (zw_b1(6) = '1' and zw_REG_OP = X"6F") or + (zw_b1(7) = '1' and zw_REG_OP = X"7F"))) then + sig_PC <= adr_nxt_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1') then + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "10"; + end if; + when s272 => + zw_b1 <= d_i; + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + end if; + when s309 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when RES7 => + sig_PC <= adr_nxt_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + when others => + null; + end case; + end if; + end process clocked_proc; + + ----------------------------------------------------------------- + nextstate_proc : process ( + adr_nxt_pc_i, + current_state, + d_i, + irq_n_i, + nmi_i, + rdy_i, + reg_F, + zw_REG_OP, + zw_b1, + zw_b2, + zw_b3 + ) + ----------------------------------------------------------------- + begin + case current_state is + when s544 => + if (rdy_i = '1') then + next_state <= s550; + else + next_state <= s544; + end if; + when s545 => + if (rdy_i = '1') then + next_state <= s546; + else + next_state <= s545; + end if; + when s546 => + if (rdy_i = '1') then + next_state <= s547; + else + next_state <= s546; + end if; + when s547 => + if (rdy_i = '1') then + next_state <= s549; + else + next_state <= s547; + end if; + when s549 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s549; + end if; + when s550 => + if (rdy_i = '1') then + next_state <= s545; + else + next_state <= s550; + end if; + when RES => + next_state <= RES7; + when FETCH => + if ((d_i = X"00") and (rdy_i = '1')) then + next_state <= brk1; + elsif ((nmi_i = '1') and (rdy_i = '1')) then + next_state <= irq1; + elsif ((irq_n_i = '0' and + reg_F(2) = '0') and (rdy_i = '1')) then + next_state <= irq1; + elsif ((d_i = X"58") and (rdy_i = '1')) then + next_state <= s19; + elsif ((d_i = X"28") and (rdy_i = '1')) then + next_state <= s442; + elsif ((d_i = X"78") and (rdy_i = '1')) then + next_state <= s9; + elsif ((d_i = X"69" or + d_i = X"65" or + d_i = X"75" or + d_i = X"6D" or + d_i = X"7D" or + d_i = X"79" or + d_i = X"61" or + d_i = X"71" or + d_i = X"72") and (rdy_i = '1')) then + next_state <= s512; + elsif ((d_i = X"06" or + d_i = X"16" or + d_i = X"0E" or + d_i = X"1E" or + d_i (3 downto 0) = X"7" or + d_i = X"14" or + d_i = X"04" or + d_i = X"0C" or + d_i = X"1C") and (rdy_i = '1')) then + next_state <= s405; + elsif ((d_i = X"90" or + d_i = X"B0" or + d_i = X"F0" or + d_i = X"30" or + d_i = X"D0" or + d_i = X"10" or + d_i = X"50" or + d_i = X"70" or + d_i = X"80") and (rdy_i = '1')) then + next_state <= s268; + elsif ((d_i = X"24" or + d_i = X"2C" or + d_i = X"3C" or + d_i = X"34" or + d_i = X"89") and (rdy_i = '1')) then + next_state <= s221; + elsif ((d_i = X"18") and (rdy_i = '1')) then + next_state <= s13; + elsif ((d_i = X"D8") and (rdy_i = '1')) then + next_state <= s18; + elsif ((d_i = X"8F" or + d_i = X"9F" or + d_i = X"AF" or + d_i = X"BF" or + d_i = X"CF" or + d_i = X"DF" or + d_i = X"EF" or + d_i = X"FF" or + d_i = X"0F" or + d_i = X"1F" or + d_i = X"2F" or + d_i = X"3F" or + d_i = X"4F" or + d_i = X"5F" or + d_i = X"6F" or + d_i = X"7F") and (rdy_i = '1')) then + next_state <= s270; + elsif ((d_i = X"B8") and (rdy_i = '1')) then + next_state <= s26; + elsif ((d_i = X"E0" or + d_i = X"E4" or + d_i = X"EC") and (rdy_i = '1')) then + next_state <= s203; + elsif ((d_i = X"C0" or + d_i = X"C4" or + d_i = X"CC") and (rdy_i = '1')) then + next_state <= s203; + elsif ((d_i = X"C6" or + d_i = X"D6" or + d_i = X"CE" or + d_i = X"DE") and (rdy_i = '1')) then + next_state <= s236; + elsif ((d_i = X"CA") and (rdy_i = '1')) then + next_state <= s27; + elsif ((d_i = X"88") and (rdy_i = '1')) then + next_state <= s27; + elsif ((d_i = X"49" or + d_i = X"45" or + d_i = X"55" or + d_i = X"4D" or + d_i = X"5D" or + d_i = X"59" or + d_i = X"41" or + d_i = X"51" or + d_i = X"09" or + d_i = X"05" or + d_i = X"15" or + d_i = X"0D" or + d_i = X"1D" or + d_i = X"19" or + d_i = X"01" or + d_i = X"11" or + d_i = X"29" or + d_i = X"25" or + d_i = X"35" or + d_i = X"2D" or + d_i = X"3D" or + d_i = X"39" or + d_i = X"21" or + d_i = X"31" or + d_i = X"C9" or + d_i = X"C5" or + d_i = X"D5" or + d_i = X"CD" or + d_i = X"DD" or + d_i = X"D9" or + d_i = X"C1" or + d_i = X"D1" or + d_i = X"32" or + d_i = X"D2" or + d_i = X"52" or + d_i = X"12") and (rdy_i = '1')) then + next_state <= s203; + elsif ((d_i = X"E6" or + d_i = X"F6" or + d_i = X"EE" or + d_i = X"FE") and (rdy_i = '1')) then + next_state <= s236; + elsif ((d_i = X"E8") and (rdy_i = '1')) then + next_state <= s27; + elsif ((d_i = X"C8") and (rdy_i = '1')) then + next_state <= s27; + elsif ((d_i = X"4C" or + d_i = X"6C" or + d_i = X"7C") and (rdy_i = '1')) then + next_state <= jmp1; + elsif ((d_i = X"20") and (rdy_i = '1')) then + next_state <= s402; + elsif ((d_i = X"A9" or + d_i = X"A5" or + d_i = X"B5" or + d_i = X"AD" or + d_i = X"BD" or + d_i = X"B9" or + d_i = X"A1" or + d_i = X"B1" or + d_i = X"B2") and (rdy_i = '1')) then + next_state <= s203; + elsif ((d_i = X"A2" or + d_i = X"A6" or + d_i = X"B6" or + d_i = X"AE" or + d_i = X"BE") and (rdy_i = '1')) then + next_state <= s203; + elsif ((d_i = X"A0" or + d_i = X"A4" or + d_i = X"B4" or + d_i = X"AC" or + d_i = X"BC") and (rdy_i = '1')) then + next_state <= s203; + elsif ((d_i = X"46" or + d_i = X"56" or + d_i = X"4E" or + d_i = X"5E") and (rdy_i = '1')) then + next_state <= s405; + elsif ((d_i = X"EA") and (rdy_i = '1')) then + next_state <= s6; + elsif ((d_i = X"48") and (rdy_i = '1')) then + next_state <= s435; + elsif ((d_i = X"08") and (rdy_i = '1')) then + next_state <= s437; + elsif ((d_i = X"7A") and (rdy_i = '1')) then + next_state <= s439; + elsif ((d_i = X"26" or + d_i = X"36" or + d_i = X"2E" or + d_i = X"3E") and (rdy_i = '1')) then + next_state <= s405; + elsif ((d_i = X"66" or + d_i = X"76" or + d_i = X"6E" or + d_i = X"7E") and (rdy_i = '1')) then + next_state <= s405; + elsif ((d_i = X"40") and (rdy_i = '1')) then + next_state <= s425; + elsif ((d_i = X"60") and (rdy_i = '1')) then + next_state <= s430; + elsif ((d_i = X"E9" or + d_i = X"E5" or + d_i = X"F5" or + d_i = X"ED" or + d_i = X"FD" or + d_i = X"F9" or + d_i = X"E1" or + d_i = X"F1" or + d_i = X"F2") and (rdy_i = '1')) then + next_state <= s513; + elsif ((d_i = X"38") and (rdy_i = '1')) then + next_state <= s7; + elsif ((d_i = X"F8") and (rdy_i = '1')) then + next_state <= s8; + elsif ((d_i = X"85" or + d_i = X"95" or + d_i = X"8D" or + d_i = X"9D" or + d_i = X"99" or + d_i = X"81" or + d_i = X"91" or + d_i = X"92") and (rdy_i = '1')) then + next_state <= s178; + elsif ((d_i = X"86" or + d_i = X"96" or + d_i = X"8E") and (rdy_i = '1')) then + next_state <= s178; + elsif ((d_i = X"84" or + d_i = X"94" or + d_i = X"8C") and (rdy_i = '1')) then + next_state <= s178; + elsif ((d_i = X"AA") and (rdy_i = '1')) then + next_state <= s10; + elsif ((d_i = X"0A") and (rdy_i = '1')) then + next_state <= s420; + elsif ((d_i = X"4A") and (rdy_i = '1')) then + next_state <= s599; + elsif ((d_i = X"2A") and (rdy_i = '1')) then + next_state <= s600; + elsif ((d_i = X"6A") and (rdy_i = '1')) then + next_state <= s598; + elsif ((d_i = X"A8") and (rdy_i = '1')) then + next_state <= s10; + elsif ((d_i = X"98") and (rdy_i = '1')) then + next_state <= s10; + elsif ((d_i = X"BA") and (rdy_i = '1')) then + next_state <= s10; + elsif ((d_i = X"8A") and (rdy_i = '1')) then + next_state <= s10; + elsif ((d_i = X"9A") and (rdy_i = '1')) then + next_state <= s10; + elsif ((d_i = X"DA") and (rdy_i = '1')) then + next_state <= s435; + elsif ((d_i = X"5A") and (rdy_i = '1')) then + next_state <= s435; + elsif ((d_i = X"68") and (rdy_i = '1')) then + next_state <= s439; + elsif ((d_i = X"FA") and (rdy_i = '1')) then + next_state <= s439; + elsif ((d_i = X"9C" or + d_i = X"9E" or + d_i = X"64" or + d_i = X"74") and (rdy_i = '1')) then + next_state <= s178; + elsif ((d_i = X"3A") and (rdy_i = '1')) then + next_state <= s27; + elsif ((d_i = X"1A") and (rdy_i = '1')) then + next_state <= s27; + elsif ((d_i = X"EA") and (rdy_i = '1')) then + next_state <= s6; + elsif ((d_i = X"02" or + d_i = X"22" or + d_i = X"42" or + d_i = X"62" or + d_i = X"82" or + d_i = X"C2" or + d_i = X"E2") and (rdy_i = '1')) then + next_state <= s11; + elsif ((d_i = X"44") and (rdy_i = '1')) then + next_state <= s12; + elsif ((d_i = X"54" or + d_i = X"D4" or + d_i = X"F4") and (rdy_i = '1')) then + next_state <= s14; + elsif ((d_i = X"DC" or + d_i = X"FC") and (rdy_i = '1')) then + next_state <= s15; + elsif ((d_i = X"5C") and (rdy_i = '1')) then + next_state <= s16; + elsif ((d_i(3 downto 0) = X"3" or + d_i(3 downto 0) = X"B") and (rdy_i = '1')) then + next_state <= FETCH; + else + next_state <= FETCH; + end if; + when s6 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s6; + end if; + when s7 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s7; + end if; + when s8 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s8; + end if; + when s9 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s9; + end if; + when s10 => + if (rdy_i = '1' and + zw_REG_OP = X"9A") then + next_state <= FETCH; + elsif (rdy_i = '1' and + zw_REG_OP = X"BA") then + next_state <= FETCH; + elsif (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s10; + end if; + when s13 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s13; + end if; + when s18 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s18; + end if; + when s19 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s19; + end if; + when s26 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s26; + end if; + when s27 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s27; + end if; + when s203 => + if (rdy_i = '1' and + (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR + zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR + zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR + zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then + next_state <= s230; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11" or + zw_REG_OP = X"12")) then + next_state <= FETCH; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51" or + zw_REG_OP = X"52")) then + next_state <= FETCH; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31" or + zw_REG_OP = X"32")) then + next_state <= FETCH; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or + zw_REG_OP = X"D2")) then + next_state <= FETCH; + elsif (rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then + next_state <= FETCH; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B5" OR + zw_REG_OP = X"B4" OR + zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR + zw_REG_OP = X"35" OR + zw_REG_OP = X"D5")) then + next_state <= s219; + elsif (rdy_i = '1' and + (zw_REG_OP = X"AD" OR + zw_REG_OP = X"AE" OR + zw_REG_OP = X"AC" OR + zw_REG_OP = X"4D" OR + zw_REG_OP = X"0D" OR + zw_REG_OP = X"2D" OR + zw_REG_OP = X"CD" OR + zw_REG_OP = X"EC" OR + zw_REG_OP = X"CC")) then + next_state <= s204; + elsif (rdy_i = '1' and + (zw_REG_OP = X"BD" OR + zw_REG_OP = X"BC" OR + zw_REG_OP = X"5D" OR + zw_REG_OP = X"1D" OR + zw_REG_OP = X"3D" OR + zw_REG_OP = X"DD")) then + next_state <= s212; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B9" OR + zw_REG_OP = X"BE" OR + zw_REG_OP = X"59" OR + zw_REG_OP = X"19" OR + zw_REG_OP = X"39" OR + zw_REG_OP = X"D9")) then + next_state <= s212; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B1" OR + zw_REG_OP = X"51" OR + zw_REG_OP = X"11" OR + zw_REG_OP = X"31" OR + zw_REG_OP = X"D1")) then + next_state <= s216; + elsif (rdy_i = '1' and + (zw_REG_OP = X"A1" OR + zw_REG_OP = X"41" OR + zw_REG_OP = X"01" OR + zw_REG_OP = X"21" OR + zw_REG_OP = X"C1")) then + next_state <= s220; + elsif (rdy_i = '1' and + zw_REG_OP = X"B6") then + next_state <= s219; + elsif (rdy_i = '1' and + (zw_REG_OP = X"32" OR + zw_REG_OP = X"D2" OR + zw_REG_OP = X"52" OR + zw_REG_OP = X"B2" OR + zw_REG_OP = X"12")) then + next_state <= s229; + else + next_state <= s203; + end if; + when s204 => + if (rdy_i = '1') then + next_state <= s230; + else + next_state <= s204; + end if; + when s212 => + if (rdy_i = '1') then + next_state <= s231; + else + next_state <= s212; + end if; + when s216 => + if (rdy_i = '1') then + next_state <= s228; + else + next_state <= s216; + end if; + when s219 => + if (rdy_i = '1') then + next_state <= s230; + else + next_state <= s219; + end if; + when s220 => + if (rdy_i = '1') then + next_state <= s227; + else + next_state <= s220; + end if; + when s227 => + if (rdy_i = '1') then + next_state <= s204; + else + next_state <= s227; + end if; + when s228 => + if (rdy_i = '1') then + next_state <= s231; + else + next_state <= s228; + end if; + when s230 => + if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11" or + zw_REG_OP = X"12")) then + next_state <= FETCH; + elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51" or + zw_REG_OP = X"52")) then + next_state <= FETCH; + elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31" or + zw_REG_OP = X"32")) then + next_state <= FETCH; + elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or + zw_REG_OP = X"D2")) then + next_state <= FETCH; + elsif (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s230; + end if; + when s231 => + if ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11" or + zw_REG_OP = X"12")) then + next_state <= FETCH; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51" or + zw_REG_OP = X"52")) then + next_state <= FETCH; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31" or + zw_REG_OP = X"32")) then + next_state <= FETCH; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or + zw_REG_OP = X"D2")) then + next_state <= FETCH; + elsif (rdy_i = '1' AND + zw_b2(0) = '0') then + next_state <= FETCH; + elsif (rdy_i = '1') then + next_state <= s230; + else + next_state <= s231; + end if; + when s229 => + if (rdy_i = '1') then + next_state <= s204; + else + next_state <= s229; + end if; + when s512 => + if (rdy_i = '1' and + zw_REG_OP = X"65") then + next_state <= s586; + elsif (rdy_i = '1' and + zw_REG_OP = X"69" and + reg_F(3) = '0') then + next_state <= FETCH; + elsif (rdy_i = '1' and + zw_REG_OP = X"75") then + next_state <= s582; + elsif (rdy_i = '1' and + zw_REG_OP = X"6D") then + next_state <= s554; + elsif (rdy_i = '1' and + zw_REG_OP = X"7D") then + next_state <= s578; + elsif (rdy_i = '1' and + zw_REG_OP = X"79") then + next_state <= s578; + elsif (rdy_i = '1' and + zw_REG_OP = X"71") then + next_state <= s581; + elsif (rdy_i = '1' and + zw_REG_OP = X"61") then + next_state <= s583; + elsif (rdy_i = '1' and + zw_REG_OP = X"69" and + reg_F(3) = '1') then + next_state <= s601; + elsif (rdy_i = '1' and + zw_REG_OP = X"72") then + next_state <= s580; + else + next_state <= s512; + end if; + when s554 => + if (rdy_i = '1') then + next_state <= s586; + else + next_state <= s554; + end if; + when s578 => + if (rdy_i = '1') then + next_state <= s585; + else + next_state <= s578; + end if; + when s581 => + if (rdy_i = '1') then + next_state <= s587; + else + next_state <= s581; + end if; + when s582 => + if (rdy_i = '1') then + next_state <= s586; + else + next_state <= s582; + end if; + when s583 => + if (rdy_i = '1') then + next_state <= s584; + else + next_state <= s583; + end if; + when s584 => + if (rdy_i = '1') then + next_state <= s554; + else + next_state <= s584; + end if; + when s585 => + if (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '0') then + next_state <= FETCH; + elsif (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '1') then + next_state <= s601; + elsif (rdy_i = '1') then + next_state <= s586; + else + next_state <= s585; + end if; + when s586 => + if (rdy_i = '1' and + reg_F(3) = '0') then + next_state <= FETCH; + elsif (rdy_i = '1' and + reg_F(3) = '1') then + next_state <= s601; + else + next_state <= s586; + end if; + when s587 => + if (rdy_i = '1') then + next_state <= s585; + else + next_state <= s587; + end if; + when s580 => + if (rdy_i = '1') then + next_state <= s554; + else + next_state <= s580; + end if; + when s178 => + if (rdy_i = '1' and + (zw_REG_OP = X"85" OR + zw_REG_OP = X"86" OR + zw_REG_OP = X"64" OR + zw_REG_OP = X"84")) then + next_state <= s197; + elsif (rdy_i = '1' and + (zw_REG_OP = X"95" OR + zw_REG_OP = X"74" OR + zw_REG_OP = X"94")) then + next_state <= s198; + elsif (rdy_i = '1' and + (zw_REG_OP = X"8D" OR + zw_REG_OP = X"8E" OR + zw_REG_OP = X"9C" OR + zw_REG_OP = X"8C")) then + next_state <= s196; + elsif (rdy_i = '1' and + (zw_REG_OP = X"9D" OR + zw_REG_OP = X"9E")) then + next_state <= s194; + elsif (rdy_i = '1' and + zw_REG_OP = X"99") then + next_state <= s194; + elsif (rdy_i = '1' and + zw_REG_OP = X"91") then + next_state <= s195; + elsif (rdy_i = '1' and + zw_REG_OP = X"81") then + next_state <= s199; + elsif (rdy_i = '1' and + zw_REG_OP = X"96") then + next_state <= s198; + elsif (rdy_i = '1' and + zw_REG_OP = X"92") then + next_state <= s214; + else + next_state <= s178; + end if; + when s194 => + if (rdy_i = '1') then + next_state <= s208; + else + next_state <= s194; + end if; + when s195 => + if (rdy_i = '1') then + next_state <= s206; + else + next_state <= s195; + end if; + when s196 => + if (rdy_i = '1') then + next_state <= s200; + else + next_state <= s196; + end if; + when s197 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s197; + end if; + when s198 => + if (rdy_i = '1') then + next_state <= s207; + else + next_state <= s198; + end if; + when s199 => + if (rdy_i = '1') then + next_state <= s205; + else + next_state <= s199; + end if; + when s200 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s200; + end if; + when s205 => + if (rdy_i = '1') then + next_state <= s209; + else + next_state <= s205; + end if; + when s206 => + if (rdy_i = '1') then + next_state <= s208; + else + next_state <= s206; + end if; + when s207 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s207; + end if; + when s208 => + if (rdy_i = '1') then + next_state <= s213; + end if; + when s209 => + if (rdy_i = '1') then + next_state <= s213; + end if; + when s213 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s213; + end if; + when s214 => + if (rdy_i = '1') then + next_state <= s196; + else + next_state <= s214; + end if; + when s513 => + if (rdy_i = '1' and + zw_REG_OP = X"E5") then + next_state <= s596; + elsif (rdy_i = '1' and + zw_REG_OP = X"E9" and + reg_F(3) = '0') then + next_state <= FETCH; + elsif (rdy_i = '1' and + zw_REG_OP = X"F5") then + next_state <= s591; + elsif (rdy_i = '1' and + zw_REG_OP = X"ED") then + next_state <= s588; + elsif (rdy_i = '1' and + zw_REG_OP = X"FD") then + next_state <= s589; + elsif (rdy_i = '1' and + zw_REG_OP = X"F9") then + next_state <= s589; + elsif (rdy_i = '1' and + zw_REG_OP = X"F1") then + next_state <= s590; + elsif (rdy_i = '1' and + zw_REG_OP = X"E1") then + next_state <= s592; + elsif (rdy_i = '1' and + zw_REG_OP = X"E9" and + reg_F(3) = '1') then + next_state <= s602; + elsif (rdy_i = '1' and + zw_REG_OP = X"F2") then + next_state <= s597; + else + next_state <= s513; + end if; + when s588 => + if (rdy_i = '1') then + next_state <= s596; + else + next_state <= s588; + end if; + when s589 => + if (rdy_i = '1') then + next_state <= s595; + else + next_state <= s589; + end if; + when s590 => + if (rdy_i = '1') then + next_state <= s593; + else + next_state <= s590; + end if; + when s591 => + if (rdy_i = '1') then + next_state <= s596; + else + next_state <= s591; + end if; + when s592 => + if (rdy_i = '1') then + next_state <= s594; + else + next_state <= s592; + end if; + when s593 => + if (rdy_i = '1') then + next_state <= s595; + else + next_state <= s593; + end if; + when s594 => + if (rdy_i = '1') then + next_state <= s588; + else + next_state <= s594; + end if; + when s595 => + if (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '0') then + next_state <= FETCH; + elsif (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '1') then + next_state <= s602; + elsif (rdy_i = '1') then + next_state <= s596; + else + next_state <= s595; + end if; + when s596 => + if (rdy_i = '1' and + reg_F(3) = '0') then + next_state <= FETCH; + elsif (rdy_i = '1' and + reg_F(3) = '1') then + next_state <= s602; + else + next_state <= s596; + end if; + when s597 => + if (rdy_i = '1') then + next_state <= s588; + else + next_state <= s597; + end if; + when s405 => + if (rdy_i = '1' and + (zw_REG_OP = X"1E" or + zw_REG_OP = X"7E" or + zw_REG_OP = X"3E" or + zw_REG_OP = X"5E")) then + next_state <= s410; + elsif (rdy_i = '1' and + (zw_REG_OP = X"06" or zw_REG_OP = X"66" or + zw_REG_OP = X"26" or zw_REG_OP = X"46" or + zw_REG_OP = X"04" or zw_REG_OP = X"14")) then + next_state <= s415; + elsif (rdy_i = '1' and + (zw_REG_OP = X"16" or + zw_REG_OP = X"76" or + zw_REG_OP = X"36" or + zw_REG_OP = X"56")) then + next_state <= s411; + elsif (rdy_i = '1' and + (zw_REG_OP = X"0E" or + zw_REG_OP = X"6E" or + zw_REG_OP = X"2E" or + zw_REG_OP = X"4E"or + zw_REG_OP = X"0C" or + zw_REG_OP = X"1C")) then + next_state <= s408; + elsif (rdy_i = '1' and + zw_REG_OP (3 downto 0) = X"7") then + next_state <= s415; + else + next_state <= s405; + end if; + when s408 => + if (rdy_i = '1') then + next_state <= s415; + else + next_state <= s408; + end if; + when s410 => + if (rdy_i = '1') then + next_state <= s414; + else + next_state <= s410; + end if; + when s411 => + if (rdy_i = '1') then + next_state <= s415; + else + next_state <= s411; + end if; + when s414 => + if (rdy_i = '1') then + next_state <= s417; + else + next_state <= s414; + end if; + when s415 => + if (rdy_i = '1') then + next_state <= s417; + else + next_state <= s415; + end if; + when s417 => + if ((rdy_i = '1' and + (zw_REG_OP = X"06" or + zw_REG_OP = X"16" or + zw_REG_OP = X"0E" or + zw_REG_OP = X"1E")) and (rdy_i = '1')) then + next_state <= s419; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"46" or + zw_REG_OP = X"56" or + zw_REG_OP = X"4E" or + zw_REG_OP = X"5E")) and (rdy_i = '1')) then + next_state <= s419; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"26" or + zw_REG_OP = X"36" or + zw_REG_OP = X"2E" or + zw_REG_OP = X"3E")) and (rdy_i = '1')) then + next_state <= s419; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"66" or + zw_REG_OP = X"76" or + zw_REG_OP = X"6E" or + zw_REG_OP = X"7E")) and (rdy_i = '1')) then + next_state <= s419; + elsif ((rdy_i = '1' and + zw_REG_OP (7) = '0' and + zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then + next_state <= s419; + elsif ((rdy_i = '1' and + zw_REG_OP (7) = '1' and + zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then + next_state <= s419; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"14" or + zw_REG_OP = X"1C")) and (rdy_i = '1')) then + next_state <= s419; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"04" or + zw_REG_OP = X"0C")) and (rdy_i = '1')) then + next_state <= s419; + else + next_state <= s417; + end if; + when s419 => + if ((zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then + next_state <= FETCH; + elsif (((zw_REG_OP = X"14" or + zw_REG_OP = X"04" or + zw_REG_OP = X"0C" or + zw_REG_OP = X"1C")) and (rdy_i = '1')) then + next_state <= FETCH; + elsif (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s419; + end if; + when s420 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s420; + end if; + when s598 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s598; + end if; + when s599 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s599; + end if; + when s600 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s600; + end if; + when s268 => + if (rdy_i = '1' and ( + (reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or + (reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or + (reg_F(1) = '1' and zw_REG_OP = X"D0") or (reg_F(7) = '1' and zw_REG_OP = X"10") or + (reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) then + next_state <= FETCH; + elsif (rdy_i = '1') then + next_state <= s305; + else + next_state <= s268; + end if; + when s305 => + if (rdy_i = '1' and + zw_b3 = adr_nxt_pc_i (15 downto 8)) then + next_state <= FETCH; + elsif (rdy_i = '1') then + next_state <= s306; + else + next_state <= s305; + end if; + when s306 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s306; + end if; + when jmp1 => + if (rdy_i = '1' and + zw_REG_OP = X"4C") then + next_state <= jmp_ex; + elsif (rdy_i = '1' and + zw_REG_OP = X"6C") then + next_state <= jmp2_1; + elsif (rdy_i = '1' and + zw_REG_OP = X"7C") then + next_state <= jmp2_2; + else + next_state <= jmp1; + end if; + when jmp2_1 => + if (rdy_i = '1') then + next_state <= jmp3_1; + else + next_state <= jmp2_1; + end if; + when jmp4_12 => + if (rdy_i = '1') then + next_state <= jmp_ex; + else + next_state <= jmp4_12; + end if; + when jmp_ex => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= jmp_ex; + end if; + when jmp2_2 => + if (rdy_i = '1') then + next_state <= jmp3_2; + else + next_state <= jmp2_2; + end if; + when jmp3_1 => + if (rdy_i = '1') then + next_state <= jmp4_12; + else + next_state <= jmp3_1; + end if; + when s402 => + if (rdy_i = '1') then + next_state <= s421; + else + next_state <= s402; + end if; + when s421 => + if (rdy_i = '1') then + next_state <= s422; + else + next_state <= s421; + end if; + when s422 => + if (rdy_i = '1') then + next_state <= s423; + else + next_state <= s422; + end if; + when s423 => + if (rdy_i = '1') then + next_state <= s424; + else + next_state <= s423; + end if; + when s424 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s424; + end if; + when s362 => + if (rdy_i = '1') then + next_state <= s234; + else + next_state <= s362; + end if; + when s221 => + if (rdy_i = '1' and + zw_REG_OP = X"34") then + next_state <= s233; + elsif (rdy_i = '1' and + zw_REG_OP = X"3C") then + next_state <= s232; + elsif (rdy_i = '1' and + zw_REG_OP = X"24") then + next_state <= s234; + elsif (rdy_i = '1' and + zw_REG_OP = X"2C") then + next_state <= s362; + elsif (rdy_i = '1' and + zw_REG_OP = X"89") then + next_state <= FETCH; + else + next_state <= s221; + end if; + when s232 => + if (rdy_i = '1') then + next_state <= s235; + else + next_state <= s232; + end if; + when s233 => + if (rdy_i = '1') then + next_state <= s234; + else + next_state <= s233; + end if; + when s234 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s234; + end if; + when s235 => + if (rdy_i = '1' AND + zw_b2(0) = '0') then + next_state <= FETCH; + elsif (rdy_i = '1') then + next_state <= s234; + else + next_state <= s235; + end if; + when brk1 => + if (rdy_i = '1') then + next_state <= brk2; + else + next_state <= brk1; + end if; + when brk2 => + if (rdy_i = '1') then + next_state <= brk3; + else + next_state <= brk2; + end if; + when brk3 => + if (rdy_i = '1') then + next_state <= brk4; + else + next_state <= brk3; + end if; + when brk4 => + if (rdy_i = '1') then + next_state <= brk5; + else + next_state <= brk4; + end if; + when brk6 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= brk6; + end if; + when brk5 => + if (rdy_i = '1') then + next_state <= brk6; + else + next_state <= brk5; + end if; + when s425 => + if (rdy_i = '1') then + next_state <= s426; + else + next_state <= s425; + end if; + when s426 => + if (rdy_i = '1') then + next_state <= s427; + else + next_state <= s426; + end if; + when s427 => + if (rdy_i = '1') then + next_state <= s428; + else + next_state <= s427; + end if; + when s428 => + if (rdy_i = '1') then + next_state <= s429; + else + next_state <= s428; + end if; + when s429 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s429; + end if; + when s430 => + if (rdy_i = '1') then + next_state <= s431; + else + next_state <= s430; + end if; + when s431 => + if (rdy_i = '1') then + next_state <= s432; + else + next_state <= s431; + end if; + when s432 => + if (rdy_i = '1') then + next_state <= s433; + else + next_state <= s432; + end if; + when s433 => + if (rdy_i = '1') then + next_state <= s434; + else + next_state <= s433; + end if; + when s434 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s434; + end if; + when s236 => + if (rdy_i = '1' and + (zw_REG_OP = X"C6" OR + zw_REG_OP = X"E6")) then + next_state <= s346; + elsif (rdy_i = '1' and + (zw_REG_OP = X"D6" OR + zw_REG_OP = X"F6")) then + next_state <= s248; + elsif (rdy_i = '1' and + (zw_REG_OP = X"CE" OR + zw_REG_OP = X"EE")) then + next_state <= s245; + elsif (rdy_i = '1' and + (zw_REG_OP = X"DE" OR + zw_REG_OP = X"FE")) then + next_state <= s246; + else + next_state <= s236; + end if; + when s245 => + if (rdy_i = '1') then + next_state <= s346; + else + next_state <= s245; + end if; + when s246 => + if (rdy_i = '1') then + next_state <= s345; + else + next_state <= s246; + end if; + when s248 => + if (rdy_i = '1') then + next_state <= s346; + else + next_state <= s248; + end if; + when s345 => + if (rdy_i = '1') then + next_state <= s346; + else + next_state <= s345; + end if; + when s346 => + if (rdy_i = '1') then + next_state <= s252; + else + next_state <= s346; + end if; + when s252 => + if (rdy_i = '1') then + next_state <= s253; + else + next_state <= s252; + end if; + when s253 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s253; + end if; + when s435 => + if (rdy_i = '1') then + next_state <= s436; + else + next_state <= s435; + end if; + when s436 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s436; + end if; + when s437 => + if (rdy_i = '1') then + next_state <= s438; + else + next_state <= s437; + end if; + when s438 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s438; + end if; + when s439 => + if (rdy_i = '1') then + next_state <= s440; + else + next_state <= s439; + end if; + when s440 => + if (rdy_i = '1') then + next_state <= s441; + else + next_state <= s440; + end if; + when s441 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s441; + end if; + when s442 => + if (rdy_i = '1') then + next_state <= s443; + else + next_state <= s442; + end if; + when s443 => + if (rdy_i = '1') then + next_state <= s444; + else + next_state <= s443; + end if; + when s444 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s444; + end if; + when irq1 => + if (rdy_i = '1') then + next_state <= irq2; + else + next_state <= irq1; + end if; + when irq2 => + if (rdy_i = '1') then + next_state <= irq3; + else + next_state <= irq2; + end if; + when irq3 => + if (rdy_i = '1') then + next_state <= irq4; + else + next_state <= irq3; + end if; + when irq5b => + if (rdy_i = '1') then + next_state <= irq6; + else + next_state <= irq5b; + end if; + when irq5a => + if (rdy_i = '1') then + next_state <= irq6; + else + next_state <= irq5a; + end if; + when irq4 => + if (rdy_i = '1' and + nmi_i = '1') then + next_state <= irq5a; + elsif (rdy_i = '1') then + next_state <= irq5b; + else + next_state <= irq4; + end if; + when irq6 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= irq6; + end if; + when s11 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s11; + end if; + when s12 => + if (rdy_i = '1') then + next_state <= s20; + else + next_state <= s12; + end if; + when s20 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s20; + end if; + when s14 => + if (rdy_i = '1') then + next_state <= s21; + else + next_state <= s14; + end if; + when s21 => + if (rdy_i = '1') then + next_state <= s23; + else + next_state <= s21; + end if; + when s23 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s23; + end if; + when s15 => + if (rdy_i = '1') then + next_state <= s25; + else + next_state <= s15; + end if; + when s25 => + if (rdy_i = '1') then + next_state <= s28; + else + next_state <= s25; + end if; + when s28 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s28; + end if; + when s16 => + if (rdy_i = '1') then + next_state <= s30; + else + next_state <= s16; + end if; + when s30 => + if (rdy_i = '1') then + next_state <= s31; + else + next_state <= s30; + end if; + when s31 => + if (rdy_i = '1') then + next_state <= s32; + else + next_state <= s31; + end if; + when s32 => + if (rdy_i = '1') then + next_state <= s34; + else + next_state <= s32; + end if; + when s33 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s33; + end if; + when s34 => + if (rdy_i = '1') then + next_state <= s36; + else + next_state <= s34; + end if; + when s36 => + if (rdy_i = '1') then + next_state <= s33; + else + next_state <= s36; + end if; + when jmp3_2 => + if (rdy_i = '1') then + next_state <= jmp4_12; + else + next_state <= jmp3_2; + end if; + when s601 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s601; + end if; + when s602 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s602; + end if; + when s270 => + if (rdy_i = '1') then + next_state <= s271; + else + next_state <= s270; + end if; + when s307 => + if (rdy_i = '1' and + zw_b3 = adr_nxt_pc_i (15 downto 8)) then + next_state <= FETCH; + elsif (rdy_i = '1') then + next_state <= s309; + else + next_state <= s307; + end if; + when s308 => + if (rdy_i = '1' and ( + (zw_b1(0) = '0' and zw_REG_OP = X"8F") or + (zw_b1(1) = '0' and zw_REG_OP = X"9F") or + (zw_b1(2) = '0' and zw_REG_OP = X"AF") or + (zw_b1(3) = '0' and zw_REG_OP = X"BF") or + (zw_b1(4) = '0' and zw_REG_OP = X"CF") or + (zw_b1(5) = '0' and zw_REG_OP = X"DF") or + (zw_b1(6) = '0' and zw_REG_OP = X"EF") or + (zw_b1(7) = '0' and zw_REG_OP = X"FF") or + (zw_b1(0) = '1' and zw_REG_OP = X"0F") or + (zw_b1(1) = '1' and zw_REG_OP = X"1F") or + (zw_b1(2) = '1' and zw_REG_OP = X"2F") or + (zw_b1(3) = '1' and zw_REG_OP = X"3F") or + (zw_b1(4) = '1' and zw_REG_OP = X"4F") or + (zw_b1(5) = '1' and zw_REG_OP = X"5F") or + (zw_b1(6) = '1' and zw_REG_OP = X"6F") or + (zw_b1(7) = '1' and zw_REG_OP = X"7F"))) then + next_state <= FETCH; + elsif (rdy_i = '1') then + next_state <= s307; + else + next_state <= s308; + end if; + when s271 => + if (rdy_i = '1') then + next_state <= s272; + else + next_state <= s271; + end if; + when s272 => + if (rdy_i = '1') then + next_state <= s308; + else + next_state <= s272; + end if; + when s309 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s309; + end if; + when RES7 => + next_state <= s544; + when others => + next_state <= RES; + end case; + end process nextstate_proc; + + ----------------------------------------------------------------- + output_proc : process ( + adr_nxt_pc_i, + adr_pc_i, + adr_sp_i, + current_state, + d_alu_i, + d_alu_prio_i, + d_i, + d_regs_out_i, + irq_n_i, + nmi_i, + q_a_i, + q_x_i, + q_y_i, + rdy_i, + reg_F, + reg_sel_pc_in, + reg_sel_pc_val, + reg_sel_rb_in, + reg_sel_rb_out, + reg_sel_reg, + reg_sel_sp_as, + reg_sel_sp_in, + sig_PC, + zw_ALU, + zw_ALU1, + zw_ALU2, + zw_ALU3, + zw_ALU4, + zw_ALU5, + zw_ALU6, + zw_REG_OP, + zw_b1, + zw_b2, + zw_b3, + zw_b4, + zw_w1, + zw_w3 + ) + ----------------------------------------------------------------- + begin + -- Default Assignment + a_o <= sig_PC; + adr_o <= X"0000"; + ch_a_o <= X"00"; + ch_b_o <= X"00"; + d_regs_in_o <= X"00"; + ld_o <= "00"; + ld_pc_o <= '0'; + ld_sp_o <= '0'; + load_regs_o <= '0'; + offset_o <= X"0000"; + rst_nmi_o <= '0'; + sel_pc_in_o <= reg_sel_pc_in; + sel_pc_val_o <= reg_sel_pc_val; + sel_rb_in_o <= reg_sel_rb_in; + sel_rb_out_o <= reg_sel_rb_out; + sel_reg_o <= reg_sel_reg; + sel_sp_as_o <= reg_sel_sp_as; + sel_sp_in_o <= reg_sel_sp_in; + -- Default Assignment To Internals + sig_D_OUT <= X"00"; + sig_RD <= '1'; + sig_RWn <= '1'; + sig_SYNC <= '0'; + sig_WR <= '0'; + zw_100_a <= '0'; + zw_100_alu <= '0'; + zw_100_d <= '0'; + zw_50_a <= '0'; + zw_50_alu <= '0'; + zw_50_d <= '0'; + zw_ALU <= "00" & X"00"; + zw_ALU1 <= "00" & X"00"; + zw_ALU2 <= "00" & X"00"; + zw_ALU3 <= "00" & X"00"; + zw_ALU4 <= "00" & X"00"; + zw_ALU5 <= "00" & X"00"; + zw_ALU6 <= "00" & X"00"; + + -- Combined Actions + case current_state is + when s544 => + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s545 => + adr_o <= X"FFFB"; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s546 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s549 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + adr_o <= d_i & zw_w1 (7 downto 0); + ld_o <= "11"; + sig_SYNC <= '1'; + end if; + when s550 => + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when RES => + sig_SYNC <= '1'; + when FETCH => + sig_RWn <= '1'; + sig_RD <= '1'; + sig_SYNC <= NOT (rdy_i); + ld_pc_o <= '1'; + if ((d_i = X"00") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((nmi_i = '1') and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((irq_n_i = '0' and + reg_F(2) = '0') and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"58") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"28") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"78") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"69" or + d_i = X"65" or + d_i = X"75" or + d_i = X"6D" or + d_i = X"7D" or + d_i = X"79" or + d_i = X"61" or + d_i = X"71" or + d_i = X"72") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"06" or + d_i = X"16" or + d_i = X"0E" or + d_i = X"1E" or + d_i (3 downto 0) = X"7" or + d_i = X"14" or + d_i = X"04" or + d_i = X"0C" or + d_i = X"1C") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"90" or + d_i = X"B0" or + d_i = X"F0" or + d_i = X"30" or + d_i = X"D0" or + d_i = X"10" or + d_i = X"50" or + d_i = X"70" or + d_i = X"80") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"24" or + d_i = X"2C" or + d_i = X"3C" or + d_i = X"34" or + d_i = X"89") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"18") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"D8") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"8F" or + d_i = X"9F" or + d_i = X"AF" or + d_i = X"BF" or + d_i = X"CF" or + d_i = X"DF" or + d_i = X"EF" or + d_i = X"FF" or + d_i = X"0F" or + d_i = X"1F" or + d_i = X"2F" or + d_i = X"3F" or + d_i = X"4F" or + d_i = X"5F" or + d_i = X"6F" or + d_i = X"7F") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"B8") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"E0" or + d_i = X"E4" or + d_i = X"EC") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"C0" or + d_i = X"C4" or + d_i = X"CC") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"C6" or + d_i = X"D6" or + d_i = X"CE" or + d_i = X"DE") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"CA") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"88") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"49" or + d_i = X"45" or + d_i = X"55" or + d_i = X"4D" or + d_i = X"5D" or + d_i = X"59" or + d_i = X"41" or + d_i = X"51" or + d_i = X"09" or + d_i = X"05" or + d_i = X"15" or + d_i = X"0D" or + d_i = X"1D" or + d_i = X"19" or + d_i = X"01" or + d_i = X"11" or + d_i = X"29" or + d_i = X"25" or + d_i = X"35" or + d_i = X"2D" or + d_i = X"3D" or + d_i = X"39" or + d_i = X"21" or + d_i = X"31" or + d_i = X"C9" or + d_i = X"C5" or + d_i = X"D5" or + d_i = X"CD" or + d_i = X"DD" or + d_i = X"D9" or + d_i = X"C1" or + d_i = X"D1" or + d_i = X"32" or + d_i = X"D2" or + d_i = X"52" or + d_i = X"12") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"E6" or + d_i = X"F6" or + d_i = X"EE" or + d_i = X"FE") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"E8") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"C8") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"4C" or + d_i = X"6C" or + d_i = X"7C") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"20") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"A9" or + d_i = X"A5" or + d_i = X"B5" or + d_i = X"AD" or + d_i = X"BD" or + d_i = X"B9" or + d_i = X"A1" or + d_i = X"B1" or + d_i = X"B2") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"A2" or + d_i = X"A6" or + d_i = X"B6" or + d_i = X"AE" or + d_i = X"BE") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"A0" or + d_i = X"A4" or + d_i = X"B4" or + d_i = X"AC" or + d_i = X"BC") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"46" or + d_i = X"56" or + d_i = X"4E" or + d_i = X"5E") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"EA") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"48") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"08") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"7A") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"26" or + d_i = X"36" or + d_i = X"2E" or + d_i = X"3E") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"66" or + d_i = X"76" or + d_i = X"6E" or + d_i = X"7E") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"40") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"60") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"E9" or + d_i = X"E5" or + d_i = X"F5" or + d_i = X"ED" or + d_i = X"FD" or + d_i = X"F9" or + d_i = X"E1" or + d_i = X"F1" or + d_i = X"F2") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"38") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"F8") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"85" or + d_i = X"95" or + d_i = X"8D" or + d_i = X"9D" or + d_i = X"99" or + d_i = X"81" or + d_i = X"91" or + d_i = X"92") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"86" or + d_i = X"96" or + d_i = X"8E") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"84" or + d_i = X"94" or + d_i = X"8C") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"AA") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"0A") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"4A") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"2A") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"6A") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"A8") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"98") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"BA") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"8A") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"9A") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"DA") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"5A") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"68") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"FA") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"9C" or + d_i = X"9E" or + d_i = X"64" or + d_i = X"74") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"3A") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"1A") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"EA") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"02" or + d_i = X"22" or + d_i = X"42" or + d_i = X"62" or + d_i = X"82" or + d_i = X"C2" or + d_i = X"E2") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"44") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"54" or + d_i = X"D4" or + d_i = X"F4") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"DC" or + d_i = X"FC") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i = X"5C") and (rdy_i = '1')) then + ld_o <= "11"; + elsif ((d_i(3 downto 0) = X"3" or + d_i(3 downto 0) = X"B") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + sig_SYNC <= '1'; + end if; + when s6 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s7 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s8 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s9 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s10 => + if (rdy_i = '1' and + zw_REG_OP = X"9A") then + adr_o <= X"01" & d_regs_out_i; + ld_o <= "11"; + ld_sp_o <= '1'; + sig_SYNC <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"BA") then + d_regs_in_o <= adr_sp_i (7 downto 0); + ch_a_o <= adr_sp_i (7 downto 0); + ch_b_o <= X"00"; + load_regs_o <= '1'; + sig_SYNC <= '1'; + elsif (rdy_i = '1') then + ch_a_o <= d_regs_out_i; + ch_b_o <= X"00"; + load_regs_o <= '1'; + sig_SYNC <= '1'; + end if; + when s13 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s18 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s19 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s26 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s27 => + if (rdy_i = '1') then + d_regs_in_o <= d_alu_i; + ch_a_o <= d_regs_out_i; + ch_b_o <= zw_b4; + load_regs_o <= '1'; + sig_SYNC <= '1'; + end if; + when s203 => + if (rdy_i = '1' and + (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR + zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR + zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR + zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11" or + zw_REG_OP = X"12")) then + ld_o <= "11"; + ld_pc_o <= '1'; + d_regs_in_o <= d_i OR q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i OR q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51" or + zw_REG_OP = X"52")) then + ld_o <= "11"; + ld_pc_o <= '1'; + d_regs_in_o <= d_i XOR q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i XOR q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31" or + zw_REG_OP = X"32")) then + ld_o <= "11"; + ld_pc_o <= '1'; + d_regs_in_o <= d_i AND q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i AND q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or + zw_REG_OP = X"D2")) then + ld_o <= "11"; + ld_pc_o <= '1'; + zw_ALU (8 downto 0) <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1; + sig_SYNC <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then + ld_o <= "11"; + ld_pc_o <= '1'; + d_regs_in_o <= d_i; + load_regs_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B5" OR + zw_REG_OP = X"B4" OR + zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR + zw_REG_OP = X"35" OR + zw_REG_OP = X"D5")) then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"AD" OR + zw_REG_OP = X"AE" OR + zw_REG_OP = X"AC" OR + zw_REG_OP = X"4D" OR + zw_REG_OP = X"0D" OR + zw_REG_OP = X"2D" OR + zw_REG_OP = X"CD" OR + zw_REG_OP = X"EC" OR + zw_REG_OP = X"CC")) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"BD" OR + zw_REG_OP = X"BC" OR + zw_REG_OP = X"5D" OR + zw_REG_OP = X"1D" OR + zw_REG_OP = X"3D" OR + zw_REG_OP = X"DD")) then + ld_o <= "11"; + ld_pc_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B9" OR + zw_REG_OP = X"BE" OR + zw_REG_OP = X"59" OR + zw_REG_OP = X"19" OR + zw_REG_OP = X"39" OR + zw_REG_OP = X"D9")) then + ld_o <= "11"; + ld_pc_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= q_y_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B1" OR + zw_REG_OP = X"51" OR + zw_REG_OP = X"11" OR + zw_REG_OP = X"31" OR + zw_REG_OP = X"D1")) then + ch_a_o <= d_i; + ch_b_o <= X"01"; + elsif (rdy_i = '1' and + (zw_REG_OP = X"A1" OR + zw_REG_OP = X"41" OR + zw_REG_OP = X"01" OR + zw_REG_OP = X"21" OR + zw_REG_OP = X"C1")) then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"B6") then + ch_a_o <= d_i; + ch_b_o <= q_y_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"32" OR + zw_REG_OP = X"D2" OR + zw_REG_OP = X"52" OR + zw_REG_OP = X"B2" OR + zw_REG_OP = X"12")) then + ch_a_o <= d_i; + ch_b_o <= X"01"; + end if; + when s204 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s212 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= "0000000" & zw_b2(0); + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s216 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= q_y_i; + end if; + when s219 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s227 => + if (rdy_i = '1') then + ch_a_o <= zw_b1; + ch_b_o <= X"01"; + end if; + when s228 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= "0000000" & zw_b2(0); + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s230 => + if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11" or + zw_REG_OP = X"12")) then + d_regs_in_o <= d_i OR q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i OR q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51" or + zw_REG_OP = X"52")) then + d_regs_in_o <= d_i XOR q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i XOR q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31" or + zw_REG_OP = X"32")) then + d_regs_in_o <= d_i AND q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i AND q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or + zw_REG_OP = X"D2")) then + zw_ALU (8 downto 0) <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1; + sig_SYNC <= '1'; + elsif (rdy_i = '1') then + d_regs_in_o <= d_i; + load_regs_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + end if; + when s231 => + if ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11" or + zw_REG_OP = X"12")) then + d_regs_in_o <= d_i OR q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i OR q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51" or + zw_REG_OP = X"52")) then + d_regs_in_o <= d_i XOR q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i XOR q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31" or + zw_REG_OP = X"32")) then + d_regs_in_o <= d_i AND q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i AND q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or + zw_REG_OP = X"D2")) then + zw_ALU (8 downto 0) <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1; + sig_SYNC <= '1'; + elsif (rdy_i = '1' AND + zw_b2(0) = '0') then + d_regs_in_o <= d_i; + load_regs_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + end if; + when s512 => + ld_pc_o <= '1'; + if (rdy_i = '1' and + zw_REG_OP = X"65") then + ld_o <= "11"; + elsif (rdy_i = '1' and + zw_REG_OP = X"69" and + reg_F(3) = '0') then + ld_o <= "11"; + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0); + sig_SYNC <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"75") then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"6D") then + ld_o <= "11"; + elsif (rdy_i = '1' and + zw_REG_OP = X"7D") then + ld_o <= "11"; + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"79") then + ld_o <= "11"; + ch_a_o <= d_i; + ch_b_o <= q_y_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"71") then + ch_a_o <= d_i; + ch_b_o <= X"01"; + elsif (rdy_i = '1' and + zw_REG_OP = X"61") then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"69" and + reg_F(3) = '1') then + ld_o <= "11"; + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + + zw_ALU(7 downto 4) <= unsigned (zw_ALU5(3 downto 0)) + unsigned (zw_ALU4(8 downto 5)); + zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU3(8 downto 5)); + + zw_ALU4(8 downto 5) <= '0' & ((zw_ALU4(4))) & ((zw_ALU4(4))) & '0'; + zw_ALU4(4) <= zw_ALU5(4) OR + (zw_ALU5(3) AND zw_ALU5(2)) OR + (zw_ALU5(3) AND zw_ALU5(1)); + zw_ALU5(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU3(4)); + + zw_ALU3(8 downto 5) <= '0' & ((zw_ALU3(4))) & ((zw_ALU3(4))) & '0'; + zw_ALU3(4) <= zw_ALU1(4) OR + (zw_ALU1(3) AND zw_ALU1(2)) OR + (zw_ALU1(3) AND zw_ALU1(1)); + zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0); + elsif (rdy_i = '1' and + zw_REG_OP = X"72") then + ch_a_o <= d_i; + ch_b_o <= X"01"; + end if; + when s554 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s578 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= X"01"; + ld_o <= "11"; + end if; + when s581 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= q_y_i; + end if; + when s582 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s584 => + if (rdy_i = '1') then + ch_a_o <= zw_b1; + ch_b_o <= X"01"; + end if; + when s585 => + if (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '0') then + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0); + sig_SYNC <= '1'; + elsif (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '1') then + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + + zw_ALU(7 downto 4) <= unsigned (zw_ALU5(3 downto 0)) + unsigned (zw_ALU4(8 downto 5)); + zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU3(8 downto 5)); + + zw_ALU4(8 downto 5) <= '0' & ((zw_ALU4(4))) & ((zw_ALU4(4))) & '0'; + zw_ALU4(4) <= zw_ALU5(4) OR + (zw_ALU5(3) AND zw_ALU5(2)) OR + (zw_ALU5(3) AND zw_ALU5(1)); + zw_ALU5(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU3(4)); + + zw_ALU3(8 downto 5) <= '0' & ((zw_ALU3(4))) & ((zw_ALU3(4))) & '0'; + zw_ALU3(4) <= zw_ALU1(4) OR + (zw_ALU1(3) AND zw_ALU1(2)) OR + (zw_ALU1(3) AND zw_ALU1(1)); + zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0); + end if; + when s586 => + if (rdy_i = '1' and + reg_F(3) = '0') then + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0); + sig_SYNC <= '1'; + elsif (rdy_i = '1' and + reg_F(3) = '1') then + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + + zw_ALU(7 downto 4) <= unsigned (zw_ALU5(3 downto 0)) + unsigned (zw_ALU4(8 downto 5)); + zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU3(8 downto 5)); + + zw_ALU4(8 downto 5) <= '0' & ((zw_ALU4(4))) & ((zw_ALU4(4))) & '0'; + zw_ALU4(4) <= zw_ALU5(4) OR + (zw_ALU5(3) AND zw_ALU5(2)) OR + (zw_ALU5(3) AND zw_ALU5(1)); + zw_ALU5(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU3(4)); + + zw_ALU3(8 downto 5) <= '0' & ((zw_ALU3(4))) & ((zw_ALU3(4))) & '0'; + zw_ALU3(4) <= zw_ALU1(4) OR + (zw_ALU1(3) AND zw_ALU1(2)) OR + (zw_ALU1(3) AND zw_ALU1(1)); + zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0); + end if; + when s587 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= X"01"; + ld_o <= "11"; + end if; + when s178 => + if (rdy_i = '1' and + (zw_REG_OP = X"85" OR + zw_REG_OP = X"86" OR + zw_REG_OP = X"64" OR + zw_REG_OP = X"84")) then + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= d_regs_out_i; + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"95" OR + zw_REG_OP = X"74" OR + zw_REG_OP = X"94")) then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"8D" OR + zw_REG_OP = X"8E" OR + zw_REG_OP = X"9C" OR + zw_REG_OP = X"8C")) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"9D" OR + zw_REG_OP = X"9E")) then + ld_o <= "11"; + ld_pc_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"99") then + ld_o <= "11"; + ld_pc_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= q_y_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"91") then + ch_a_o <= d_i; + ch_b_o <= X"01"; + elsif (rdy_i = '1' and + zw_REG_OP = X"81") then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"96") then + ch_a_o <= d_i; + ch_b_o <= q_y_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"92") then + ch_a_o <= d_i; + ch_b_o <= X"01"; + end if; + when s194 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= "0000000" & zw_b2(0); + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s195 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= q_y_i; + end if; + when s196 => + if (rdy_i = '1') then + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= d_regs_out_i; + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s197 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s198 => + if (rdy_i = '1') then + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= d_regs_out_i; + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s200 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s205 => + if (rdy_i = '1') then + ch_a_o <= zw_b1; + ch_b_o <= X"01"; + end if; + when s206 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= "0000000" & zw_b2(0); + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s207 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s208 => + if (rdy_i = '1') then + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= d_regs_out_i; + end if; + when s209 => + if (rdy_i = '1') then + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= d_regs_out_i; + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s213 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s513 => + ld_pc_o <= '1'; + if (rdy_i = '1' and + zw_REG_OP = X"E5") then + ld_o <= "11"; + elsif (rdy_i = '1' and + zw_REG_OP = X"E9" and + reg_F(3) = '0') then + ld_o <= "11"; + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0); + sig_SYNC <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"F5") then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"ED") then + ld_o <= "11"; + elsif (rdy_i = '1' and + zw_REG_OP = X"FD") then + ld_o <= "11"; + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"F9") then + ld_o <= "11"; + ch_a_o <= d_i; + ch_b_o <= q_y_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"F1") then + ch_a_o <= d_i; + ch_b_o <= X"01"; + elsif (rdy_i = '1' and + zw_REG_OP = X"E1") then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"E9" and + reg_F(3) = '1') then + ld_o <= "11"; + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + + zw_ALU(7 downto 0) <= unsigned (( zw_ALU2(3 downto 0)) & ( zw_ALU1(3 downto 0))) - + unsigned (zw_ALU6(7 downto 0)); + + zw_ALU6(7 downto 0) <= '0' & + (NOT zw_ALU2(4)) & + (NOT zw_ALU2(4)) & + '0' & + '0' & + (NOT zw_ALU1(4)) & + (NOT zw_ALU1(4)) & + '0'; + + zw_ALU2(5 downto 0) <= unsigned ("00" & q_a_i(7 downto 4)) + unsigned ("00" & NOT (d_i(7 downto 4))) + + (zw_ALU1(4)); + zw_ALU1(5 downto 0) <= unsigned ("00" & q_a_i(3 downto 0)) + unsigned ("00" & NOT (d_i(3 downto 0))) + + reg_F(0); + elsif (rdy_i = '1' and + zw_REG_OP = X"F2") then + ch_a_o <= d_i; + ch_b_o <= X"01"; + end if; + when s588 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s589 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= X"01"; + ld_o <= "11"; + end if; + when s590 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= q_y_i; + end if; + when s591 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s593 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= X"01"; + ld_o <= "11"; + end if; + when s594 => + if (rdy_i = '1') then + ch_a_o <= zw_b1; + ch_b_o <= X"01"; + end if; + when s595 => + if (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '0') then + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0); + sig_SYNC <= '1'; + elsif (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '1') then + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + + zw_ALU(7 downto 0) <= unsigned (( zw_ALU2(3 downto 0)) & ( zw_ALU1(3 downto 0))) - + unsigned (zw_ALU6(7 downto 0)); + + zw_ALU6(7 downto 0) <= '0' & + (NOT zw_ALU2(4)) & + (NOT zw_ALU2(4)) & + '0' & + '0' & + (NOT zw_ALU1(4)) & + (NOT zw_ALU1(4)) & + '0'; + + zw_ALU2(5 downto 0) <= unsigned ("00" & q_a_i(7 downto 4)) + unsigned ("00" & NOT (d_i(7 downto 4))) + + (zw_ALU1(4)); + zw_ALU1(5 downto 0) <= unsigned ("00" & q_a_i(3 downto 0)) + unsigned ("00" & NOT (d_i(3 downto 0))) + + reg_F(0); + end if; + when s596 => + if (rdy_i = '1' and + reg_F(3) = '0') then + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0); + sig_SYNC <= '1'; + elsif (rdy_i = '1' and + reg_F(3) = '1') then + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + + zw_ALU(7 downto 0) <= unsigned (( zw_ALU2(3 downto 0)) & ( zw_ALU1(3 downto 0))) - + unsigned (zw_ALU6(7 downto 0)); + + zw_ALU6(7 downto 0) <= '0' & + (NOT zw_ALU2(4)) & + (NOT zw_ALU2(4)) & + '0' & + '0' & + (NOT zw_ALU1(4)) & + (NOT zw_ALU1(4)) & + '0'; + + zw_ALU2(5 downto 0) <= unsigned ("00" & q_a_i(7 downto 4)) + unsigned ("00" & NOT (d_i(7 downto 4))) + + (zw_ALU1(4)); + zw_ALU1(5 downto 0) <= unsigned ("00" & q_a_i(3 downto 0)) + unsigned ("00" & NOT (d_i(3 downto 0))) + + reg_F(0); + end if; + when s405 => + if (rdy_i = '1' and + (zw_REG_OP = X"1E" or + zw_REG_OP = X"7E" or + zw_REG_OP = X"3E" or + zw_REG_OP = X"5E")) then + ld_o <= "11"; + ld_pc_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"06" or zw_REG_OP = X"66" or + zw_REG_OP = X"26" or zw_REG_OP = X"46" or + zw_REG_OP = X"04" or zw_REG_OP = X"14")) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"16" or + zw_REG_OP = X"76" or + zw_REG_OP = X"36" or + zw_REG_OP = X"56")) then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"0E" or + zw_REG_OP = X"6E" or + zw_REG_OP = X"2E" or + zw_REG_OP = X"4E"or + zw_REG_OP = X"0C" or + zw_REG_OP = X"1C")) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP (3 downto 0) = X"7") then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s408 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s410 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= "0000000" & zw_b2(0); + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s411 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s417 => + if ((rdy_i = '1' and + (zw_REG_OP = X"06" or + zw_REG_OP = X"16" or + zw_REG_OP = X"0E" or + zw_REG_OP = X"1E")) and (rdy_i = '1')) then + sig_D_OUT <= d_i(6 downto 0) & '0'; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"46" or + zw_REG_OP = X"56" or + zw_REG_OP = X"4E" or + zw_REG_OP = X"5E")) and (rdy_i = '1')) then + sig_D_OUT <= '0' & d_i(7 downto 1); + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"26" or + zw_REG_OP = X"36" or + zw_REG_OP = X"2E" or + zw_REG_OP = X"3E")) and (rdy_i = '1')) then + sig_D_OUT <= d_i(6 downto 0) & reg_F(0); + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"66" or + zw_REG_OP = X"76" or + zw_REG_OP = X"6E" or + zw_REG_OP = X"7E")) and (rdy_i = '1')) then + sig_D_OUT <= reg_F(0) & d_i(7 downto 1); + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + elsif ((rdy_i = '1' and + zw_REG_OP (7) = '0' and + zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then + sig_D_OUT <= d_i and NOT (d_alu_prio_i); + ch_a_o <= "00000" & zw_REG_OP (6 downto 4) ; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + elsif ((rdy_i = '1' and + zw_REG_OP (7) = '1' and + zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then + sig_D_OUT <= d_i or d_alu_prio_i; + ch_a_o <= "00000" & zw_REG_OP (6 downto 4) ; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"14" or + zw_REG_OP = X"1C")) and (rdy_i = '1')) then + sig_D_OUT <= d_i and NOT (q_a_i); + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"04" or + zw_REG_OP = X"0C")) and (rdy_i = '1')) then + sig_D_OUT <= d_i or q_a_i; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + end if; + when s419 => + if ((zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then + sig_SYNC <= '1'; + elsif (((zw_REG_OP = X"14" or + zw_REG_OP = X"04" or + zw_REG_OP = X"0C" or + zw_REG_OP = X"1C")) and (rdy_i = '1')) then + ch_a_o <= zw_b1; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + elsif (rdy_i = '1') then + ch_a_o <= zw_b1; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + end if; + when s420 => + if (rdy_i = '1') then + ch_a_o <= q_a_i (6 downto 0) & '0'; + ch_b_o <= X"00"; + d_regs_in_o <= q_a_i (6 downto 0) & '0'; + load_regs_o <= '1'; + sig_SYNC <= '1'; + end if; + when s598 => + if (rdy_i = '1') then + ch_a_o <= reg_F(0) & q_a_i (7 downto 1); + ch_b_o <= X"00"; + d_regs_in_o <= reg_F(0) & q_a_i (7 downto 1); + load_regs_o <= '1'; + sig_SYNC <= '1'; + end if; + when s599 => + if (rdy_i = '1') then + ch_a_o <= '0' & q_a_i (7 downto 1); + ch_b_o <= X"00"; + d_regs_in_o <= '0' & q_a_i (7 downto 1); + load_regs_o <= '1'; + sig_SYNC <= '1'; + end if; + when s600 => + if (rdy_i = '1') then + ch_a_o <= q_a_i (6 downto 0) & reg_F(0); + ch_b_o <= X"00"; + d_regs_in_o <= q_a_i (6 downto 0) & reg_F(0); + load_regs_o <= '1'; + sig_SYNC <= '1'; + end if; + when s268 => + ld_pc_o <= '1'; + if (rdy_i = '1' and ( + (reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or + (reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or + (reg_F(1) = '1' and zw_REG_OP = X"D0") or (reg_F(7) = '1' and zw_REG_OP = X"10") or + (reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) then + ld_o <= "11"; + sig_SYNC <= '1'; + elsif (rdy_i = '1') then + ld_o <= "11"; + end if; + when s305 => + offset_o <= (zw_b2(7) & zw_b2(7) & + zw_b2(7) & zw_b2(7) & zw_b2(7) & + zw_b2(7) & zw_b2(7) & zw_b2(7) & + zw_b2(7) & zw_b2(6 downto 0)); + ld_pc_o <= '1'; + if (rdy_i = '1' and + zw_b3 = adr_nxt_pc_i (15 downto 8)) then + ld_o <= "11"; + sig_SYNC <= '1'; + elsif (rdy_i = '1') then + ld_o <= "11"; + end if; + when s306 => + offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & + zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & + zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0)); + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when jmp1 => + ld_pc_o <= '1'; + when jmp2_1 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + adr_o <= d_i & zw_b1; + ld_o <= "11"; + end if; + when jmp_ex => + ld_pc_o <= '1'; + if (rdy_i = '1') then + adr_o <= d_i & zw_b1; + ld_o <= "11"; + sig_SYNC <= '1'; + end if; + when jmp2_2 => + offset_o <= (X"00" & q_x_i); + ld_pc_o <= '1'; + if (rdy_i = '1') then + adr_o <= d_i & zw_b1; + ld_o <= "11"; + end if; + when s402 => + ld_sp_o <= '1'; + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s421 => + if (rdy_i = '1') then + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= adr_pc_i (15 downto 8); + end if; + when s422 => + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= adr_pc_i (7 downto 0); + end if; + when s424 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + adr_o <= d_i & zw_b1; + ld_o <= "11"; + sig_SYNC <= '1'; + end if; + when s362 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s221 => + if (rdy_i = '1' and + zw_REG_OP = X"34") then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"3C") then + ld_o <= "11"; + ld_pc_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"24") then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"2C") then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"89") then + ch_a_o <= q_a_i AND d_i; + ch_b_o <= X"00"; + ld_o <= "11"; + ld_pc_o <= '1'; + sig_SYNC <= '1'; + end if; + when s232 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= "0000000" & zw_b2(0); + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s233 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s234 => + if (rdy_i = '1') then + ch_a_o <= q_a_i AND d_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + end if; + when s235 => + if (rdy_i = '1' AND + zw_b2(0) = '0') then + ch_a_o <= q_a_i AND d_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + end if; + when brk1 => + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= adr_nxt_pc_i (15 downto 8); + end if; + when brk2 => + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= adr_nxt_pc_i (7 downto 0); + end if; + when brk3 => + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= reg_F OR X"30"; + end if; + when brk6 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + adr_o <= d_i & zw_b1; + ld_o <= "11"; + sig_SYNC <= '1'; + end if; + when s425 => + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s426 => + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s427 => + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s429 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + adr_o <= d_i & zw_b1; + ld_o <= "11"; + sig_SYNC <= '1'; + end if; + when s430 => + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s431 => + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s433 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + adr_o <= d_i & zw_b1; + ld_o <= "11"; + end if; + when s434 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s236 => + ld_pc_o <= '1'; + if (rdy_i = '1' and + (zw_REG_OP = X"C6" OR + zw_REG_OP = X"E6")) then + ld_o <= "11"; + elsif (rdy_i = '1' and + (zw_REG_OP = X"D6" OR + zw_REG_OP = X"F6")) then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"CE" OR + zw_REG_OP = X"EE")) then + ld_o <= "11"; + elsif (rdy_i = '1' and + (zw_REG_OP = X"DE" OR + zw_REG_OP = X"FE")) then + ld_o <= "11"; + ch_a_o <= d_i; + ch_b_o <= q_x_i; + end if; + when s245 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s246 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= "0000000" & zw_b2(0); + ld_o <= "11"; + end if; + when s248 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s346 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= zw_b4; + end if; + when s252 => + if (rdy_i = '1') then + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= zw_b1; + end if; + when s253 => + if (rdy_i = '1') then + ch_a_o <= zw_b1; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + end if; + when s435 => + if (rdy_i = '1') then + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= d_regs_out_i; + ld_o <= "11"; + ld_sp_o <= '1'; + end if; + when s436 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s437 => + ld_sp_o <= '1'; + if (rdy_i = '1') then + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= reg_F OR X"30"; + ld_o <= "11"; + end if; + when s438 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s439 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_sp_o <= '1'; + end if; + when s441 => + if (rdy_i = '1') then + d_regs_in_o <= d_i; + load_regs_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + end if; + when s442 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_sp_o <= '1'; + end if; + when s444 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when irq1 => + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= zw_w3 (15 downto 8); + end if; + when irq2 => + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= zw_w3 (7 downto 0); + end if; + when irq3 => + ld_sp_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= (reg_F AND X"EF"); + end if; + when irq6 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + adr_o <= d_i & zw_b1; + rst_nmi_o <= '1'; + ld_o <= "11"; + sig_SYNC <= '1'; + end if; + when s11 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + sig_SYNC <= '1'; + end if; + when s12 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s20 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s14 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s23 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s15 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s25 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s28 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s16 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s30 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s33 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when jmp3_2 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s601 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s602 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s270 => + ld_pc_o <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + end if; + when s307 => + offset_o <= (zw_b2(7) & zw_b2(7) & + zw_b2(7) & zw_b2(7) & zw_b2(7) & + zw_b2(7) & zw_b2(7) & zw_b2(7) & + zw_b2(7) & zw_b2(6 downto 0)); + ld_pc_o <= '1'; + if (rdy_i = '1' and + zw_b3 = adr_nxt_pc_i (15 downto 8)) then + ld_o <= "11"; + sig_SYNC <= '1'; + elsif (rdy_i = '1') then + ld_o <= "11"; + end if; + when s308 => + ld_pc_o <= '1'; + if (rdy_i = '1' and ( + (zw_b1(0) = '0' and zw_REG_OP = X"8F") or + (zw_b1(1) = '0' and zw_REG_OP = X"9F") or + (zw_b1(2) = '0' and zw_REG_OP = X"AF") or + (zw_b1(3) = '0' and zw_REG_OP = X"BF") or + (zw_b1(4) = '0' and zw_REG_OP = X"CF") or + (zw_b1(5) = '0' and zw_REG_OP = X"DF") or + (zw_b1(6) = '0' and zw_REG_OP = X"EF") or + (zw_b1(7) = '0' and zw_REG_OP = X"FF") or + (zw_b1(0) = '1' and zw_REG_OP = X"0F") or + (zw_b1(1) = '1' and zw_REG_OP = X"1F") or + (zw_b1(2) = '1' and zw_REG_OP = X"2F") or + (zw_b1(3) = '1' and zw_REG_OP = X"3F") or + (zw_b1(4) = '1' and zw_REG_OP = X"4F") or + (zw_b1(5) = '1' and zw_REG_OP = X"5F") or + (zw_b1(6) = '1' and zw_REG_OP = X"6F") or + (zw_b1(7) = '1' and zw_REG_OP = X"7F"))) then + ld_o <= "11"; + sig_SYNC <= '1'; + elsif (rdy_i = '1') then + ld_o <= "11"; + end if; + when s309 => + offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & + zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & + zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0)); + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when RES7 => + ld_o <= "11"; + ld_pc_o <= '1'; + + ld_sp_o <= '1'; + sig_RWn <= '1'; + sig_RD <= '1'; + when others => + null; + end case; + end process output_proc; + + -- Concurrent Statements + -- Clocked output assignments + d_o <= d_o_cld; + rd_o <= rd_o_cld; + sync_o <= sync_o_cld; + wr_n_o <= wr_n_o_cld; + wr_o <= wr_o_cld; +end fsm; Index: cpu65c02_true_cycle/trunk/released/rtl/vhdl/fsm_intnmi.vhd =================================================================== --- cpu65c02_true_cycle/trunk/released/rtl/vhdl/fsm_intnmi.vhd (nonexistent) +++ cpu65c02_true_cycle/trunk/released/rtl/vhdl/fsm_intnmi.vhd (revision 23) @@ -0,0 +1,167 @@ +-- VHDL Entity r65c02_tc.fsm_intnmi.symbol +-- +-- Created: +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 12:35:56 10.09.2018 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +entity fsm_intnmi is + port( + clk_clk_i : in std_logic; + nmi_n_i : in std_logic; + rst_nmi_i : in std_logic; + rst_rst_n_i : in std_logic; + nmi_o : out std_logic + ); + +-- Declarations + +end fsm_intnmi ; + +-- (C) 2008 - 2013 Jens Gutschmidt +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 1.8 2018/09/01 18:07:00 jens +-- - NMI = '0' need at least 1 cycles for correct +-- operation now (2 cycles in the past) +-- +-- Revision 1.7 2013/07/21 11:11:00 jens +-- - Changing the title block and internal revision history +-- +-- Revision 1.6 2009/01/04 10:20:47 eda +-- Changes for cosmetic issues only +-- +-- Revision 1.5 2009/01/04 09:23:10 eda +-- - Delete unused nets and blocks (same as R6502_TC) +-- - Rename blocks +-- +-- Revision 1.4 2009/01/03 16:53:02 eda +-- - Unused nets and blocks deleted +-- - Renamed blocks +-- +-- Revision 1.3 2009/01/03 16:42:02 eda +-- - Unused nets and blocks deleted +-- - Renamed blocks +-- +-- Revision 1.2 2008/12/31 19:31:24 eda +-- Production Release +-- +-- +-- +-- VHDL Architecture r65c02_tc.fsm_intnmi.fsm +-- +-- Created: +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 12:35:56 10.09.2018 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +-- COPYRIGHT (C) 2008 - 2013 by Jens Gutschmidt +-- +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. +-- +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +architecture fsm of fsm_intnmi is + + type state_type is ( + idle, + idle1, + IMP + ); + + -- State vector declaration + attribute state_vector : string; + attribute state_vector of fsm : architecture is "current_state"; + + -- Declare current and next state signals + signal current_state : state_type; + signal next_state : state_type; + + -- Declare any pre-registered internal signals + signal nmi_o_cld : std_logic ; + +begin + + ----------------------------------------------------------------- + clocked_proc : process ( + clk_clk_i, + rst_rst_n_i + ) + ----------------------------------------------------------------- + begin + if (rst_rst_n_i = '0') then + current_state <= idle; + -- Default Reset Values + nmi_o_cld <= '0'; + elsif (clk_clk_i'event and clk_clk_i = '1') then + current_state <= next_state; + -- Default Assignment To Internals + nmi_o_cld <= '0'; + + -- Combined Actions + case current_state is + when idle1 => + if (nmi_n_i = '0') then + nmi_o_cld <= '1'; + end if; + when IMP => + nmi_o_cld <= '1'; + if (rst_nmi_i = '1') then + nmi_o_cld <= '0'; + end if; + when others => + null; + end case; + end if; + end process clocked_proc; + + ----------------------------------------------------------------- + nextstate_proc : process ( + current_state, + nmi_n_i, + rst_nmi_i + ) + ----------------------------------------------------------------- + begin + case current_state is + when idle => + if (nmi_n_i = '1') then + next_state <= idle1; + else + next_state <= idle; + end if; + when idle1 => + if (nmi_n_i = '0') then + next_state <= IMP; + else + next_state <= idle1; + end if; + when IMP => + if (rst_nmi_i = '1') then + next_state <= idle; + else + next_state <= IMP; + end if; + when others => + next_state <= idle; + end case; + end process nextstate_proc; + + -- Concurrent Statements + -- Clocked output assignments + nmi_o <= nmi_o_cld; +end fsm; Index: cpu65c02_true_cycle/trunk/released/rtl/vhdl/r65c02_tc.vhd =================================================================== --- cpu65c02_true_cycle/trunk/released/rtl/vhdl/r65c02_tc.vhd (nonexistent) +++ cpu65c02_true_cycle/trunk/released/rtl/vhdl/r65c02_tc.vhd (revision 23) @@ -0,0 +1,175 @@ +-- VHDL Entity r65c02_tc.r65c02_tc.symbol +-- +-- Created: +-- by - remoteghost.UNKNOWN (ENTW-7HPZ200) +-- at - 10:24:26 07/21/13 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +entity r65c02_tc is + port( + clk_clk_i : in std_logic; + d_i : in std_logic_vector (7 downto 0); + irq_n_i : in std_logic; + nmi_n_i : in std_logic; + rdy_i : in std_logic; + rst_rst_n_i : in std_logic; + so_n_i : in std_logic; + a_o : out std_logic_vector (15 downto 0); + d_o : out std_logic_vector (7 downto 0); + rd_o : out std_logic; + sync_o : out std_logic; + wr_n_o : out std_logic; + wr_o : out std_logic + ); + +-- Declarations + +end r65c02_tc ; + +-- (C) 2008 - 2018 Jens Gutschmidt +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 1.52 2018/09/10 12:14:00 jens +-- - RESET generates SYNC now, 1 dead cycle delayed +-- Revision 1.52 RC 2018/09/09 03:00:00 jens +-- - ADC / SBC flags and A like R65C02 now +-- Revision 1.52 BETA 2018/09/05 19:35:00 jens +-- - BBRx/BBSx internal cycles like real 65C02 now +-- - Bug Fix ADC and SBC in decimal mode (all op codes - +-- 1 cycle is missing +-- - Bug Fix ADC and SBC in decimal mode (all op codes - +-- "Overflow" flag was computed wrong) +-- Revision 1.52 BETA 2018/09/02 18:49:00 jens +-- - Interrupt NMI and IRQ processing via FETCH stage now +-- Revision 1.52 BETA 2018/08/30 15:39:00 jens +-- - Interrupt priority order is now: BRQ - NMI - IRQ +-- - Performance improvements on-going (Mealy -> Moore) +-- Revision 1.52 BETA 2018/08/23 20:27:00 jens +-- - Bug Fixes All Branch Instructions +-- (BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS, BRA) +-- 3 cycles now if branch forward occur and the branch +-- instruction lies on a xxFEh location. +-- (BBR, BBS) 6 cycles now if branch forward occur and the +-- branch instruction lies on a xxFDh location. +-- - Bug Fix Hardware Interrupts NMI & IRQ - 7 cycles & "SYNC" now +-- - Bug Fix Now all cycles are delayable (WR and internal) +-- +-- Revision 1.51 RC 2014/04/19 14:44:00 jens +-- (never submitted to opencores) +-- - Bug Fix JMP ABS - produced a 6502 like JMP (IND) PCH. +-- When the ABS address data bytes cross the page +-- boundary (e.g. $02FE JMP hhll reads hh from +-- $02FF and ll from $0200, instead $02FF and $0300) +-- +-- Revision 1.5 RC 2013/08/01 11:00:00 jens +-- - Change Block name to lower case +-- - Bug Fix CMP (IND) - wrongly decoded as function AND +-- - Bug Fix BRK should clear decimal flag in P Reg +-- - Bug Fix JMP (ABS,X) - Low Address outputted twice - no High Address +-- - Bug Fix Unknown Ops - Used always 1b2c NOP ($EA) - new NOPs created +-- - Bug Fix DECIMAL ADC and SBC (all op codes - "C" flag was computed wrong) +-- - Bug Fix INC/DEC ABS,X - N/Z flag wrongly computed +-- - Bug Fix RTI - should increment stack pointer +-- - Bug Fix "E" & "B" flags (Bits 5 & 4) - should be always "1" in P Reg. Change "RES", "RTI", "IRQ" & "NMI" substates. +-- - Bug Fix ADC and SBC (all sub codes - "Overflow" flag was computed wrong) +-- - Bug Fix RMB, SMB Bug - Bit position decoded wrong +-- +-- Revision 1.4 2013/07/21 11:11:00 jens +-- - Changing the title block and internal revision history +-- - Bug Fix STA [(IND)] op$92 ($92 was missed in the connection list at state FETCH) +-- +-- Revision 1.3 2009/01/04 10:20:50 eda +-- Changes for cosmetic issues only +-- +-- Revision 1.2 2009/01/04 09:23:12 eda +-- - Delete unused nets and blocks (same as R6502_TC) +-- - Rename blocks +-- - Re-arrage FSM symbols in block FSM_Execution_Unit +-- +-- Revision 1.1 2009/01/03 16:36:48 eda +-- -- no description -- +-- +-- +-- +-- VHDL Architecture r65c02_tc.r65c02_tc.struct +-- +-- Created: +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 12:21:16 10.09.2018 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt +-- +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. +-- +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +library r65c02_tc; + +architecture struct of r65c02_tc is + + -- Architecture declarations + + -- Internal signal declarations + + + -- Component Declarations + component core + port ( + clk_clk_i : in std_logic ; + d_i : in std_logic_vector (7 downto 0); + irq_n_i : in std_logic ; + nmi_n_i : in std_logic ; + rdy_i : in std_logic ; + rst_rst_n_i : in std_logic ; + so_n_i : in std_logic ; + a_o : out std_logic_vector (15 downto 0); + d_o : out std_logic_vector (7 downto 0); + rd_o : out std_logic ; + sync_o : out std_logic ; + wr_n_o : out std_logic ; + wr_o : out std_logic + ); + end component; + + -- Optional embedded configurations + -- pragma synthesis_off + for all : core use entity r65c02_tc.core; + -- pragma synthesis_on + + +begin + + -- Instance port mappings. + U_0 : core + port map ( + clk_clk_i => clk_clk_i, + d_i => d_i, + irq_n_i => irq_n_i, + nmi_n_i => nmi_n_i, + rdy_i => rdy_i, + rst_rst_n_i => rst_rst_n_i, + so_n_i => so_n_i, + a_o => a_o, + d_o => d_o, + rd_o => rd_o, + sync_o => sync_o, + wr_n_o => wr_n_o, + wr_o => wr_o + ); + +end struct; Index: cpu65c02_true_cycle/trunk/released/rtl/vhdl/reg_pc.vhd =================================================================== --- cpu65c02_true_cycle/trunk/released/rtl/vhdl/reg_pc.vhd (nonexistent) +++ cpu65c02_true_cycle/trunk/released/rtl/vhdl/reg_pc.vhd (revision 23) @@ -0,0 +1,237 @@ +-- VHDL Entity r65c02_tc.reg_pc.symbol +-- +-- Created: +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 11:59:59 06.09.2018 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +entity reg_pc is + port( + adr_i : in std_logic_vector (15 downto 0); + clk_clk_i : in std_logic; + ld_i : in std_logic_vector (1 downto 0); + ld_pc_i : in std_logic; + offset_i : in std_logic_vector (15 downto 0); + rst_rst_n_i : in std_logic; + sel_pc_in_i : in std_logic; + sel_pc_val_i : in std_logic_vector (1 downto 0); + adr_nxt_pc_o : out std_logic_vector (15 downto 0); + adr_pc_o : out std_logic_vector (15 downto 0) + ); + +-- Declarations + +end reg_pc ; + +-- (C) 2008 - 2018 Jens Gutschmidt +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 1.7 2013/07/21 11:11:00 jens +-- - Changing the title block and internal revision history +-- +-- Revision 1.6 2009/01/04 10:20:47 eda +-- Changes for cosmetic issues only +-- +-- Revision 1.5 2009/01/04 09:23:10 eda +-- - Delete unused nets and blocks (same as R6502_TC) +-- - Rename blocks +-- +-- Revision 1.4 2009/01/03 16:53:02 eda +-- - Unused nets and blocks deleted +-- - Renamed blocks +-- +-- Revision 1.3 2009/01/03 16:42:02 eda +-- - Unused nets and blocks deleted +-- - Renamed blocks +-- +-- Revision 1.2 2008/12/31 19:31:24 eda +-- Production Release +-- +-- +-- +-- VHDL Architecture r65c02_tc.reg_pc.struct +-- +-- Created: +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 11:59:59 06.09.2018 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt +-- +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. +-- +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + + +architecture struct of reg_pc is + + -- Architecture declarations + + -- Internal signal declarations + signal adr_pc_high_o_i : std_logic_vector(7 downto 0); + signal adr_pc_low_o_i : std_logic_vector(7 downto 0); + signal adr_pc_o_i : std_logic_vector(15 downto 0); + signal ci_o_i : std_logic; + signal cout_pc_o_i : std_logic; + signal load3_o_i : std_logic; + signal load_o_i : std_logic; + signal offset_high_o_i : std_logic_vector(7 downto 0); + signal offset_low_o_i : std_logic_vector(7 downto 0); + signal val_o_i : std_logic_vector(7 downto 0); + signal val_one : std_logic_vector(7 downto 0); + signal val_zero : std_logic_vector(7 downto 0); + + -- Implicit buffer signal declarations + signal adr_nxt_pc_o_internal : std_logic_vector (15 downto 0); + signal adr_pc_o_internal : std_logic_vector (15 downto 0); + + + -- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff' + signal mw_U_0reg_cval : std_logic_vector(7 downto 0); + + -- ModuleWare signal declarations(v1.12) for instance 'U_4' of 'adff' + signal mw_U_4reg_cval : std_logic_vector(7 downto 0); + + -- ModuleWare signal declarations(v1.12) for instance 'U_3' of 'split' + signal mw_U_3temp_din : std_logic_vector(15 downto 0); + + -- ModuleWare signal declarations(v1.12) for instance 'U_5' of 'split' + signal mw_U_5temp_din : std_logic_vector(15 downto 0); + + +begin + + -- ModuleWare code(v1.12) for instance 'U_2' of 'add' + u_2combo_proc: process (adr_pc_low_o_i, val_o_i) + variable temp_din0 : std_logic_vector(8 downto 0); + variable temp_din1 : std_logic_vector(8 downto 0); + variable temp_sum : unsigned(8 downto 0); + variable temp_carry : std_logic; + begin + temp_din0 := '0' & adr_pc_low_o_i; + temp_din1 := '0' & val_o_i; + temp_carry := '0'; + temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry; + adr_nxt_pc_o_internal(7 DOWNTO 0) <= conv_std_logic_vector(temp_sum(7 downto 0),8); + cout_pc_o_i <= temp_sum(8) ; + end process u_2combo_proc; + + -- ModuleWare code(v1.12) for instance 'U_11' of 'add' + u_11combo_proc: process (adr_pc_high_o_i, offset_high_o_i, ci_o_i) + variable temp_din0 : std_logic_vector(8 downto 0); + variable temp_din1 : std_logic_vector(8 downto 0); + variable temp_sum : unsigned(8 downto 0); + variable temp_carry : std_logic; + begin + temp_din0 := '0' & adr_pc_high_o_i; + temp_din1 := '0' & offset_high_o_i; + temp_carry := ci_o_i; + temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry; + adr_nxt_pc_o_internal(15 DOWNTO 8) <= conv_std_logic_vector(temp_sum(7 downto 0),8); + end process u_11combo_proc; + + -- ModuleWare code(v1.12) for instance 'U_0' of 'adff' + adr_pc_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval; + u_0seq_proc: process (clk_clk_i, rst_rst_n_i) + begin + if (rst_rst_n_i = '0') then + mw_U_0reg_cval <= "00000000"; + elsif (clk_clk_i'event and clk_clk_i='1') then + if (load_o_i = '1') then + mw_U_0reg_cval <= adr_nxt_pc_o_internal(7 DOWNTO 0); + end if; + end if; + end process u_0seq_proc; + + -- ModuleWare code(v1.12) for instance 'U_4' of 'adff' + adr_pc_o_internal(15 DOWNTO 8) <= mw_U_4reg_cval; + u_4seq_proc: process (clk_clk_i, rst_rst_n_i) + begin + if (rst_rst_n_i = '0') then + mw_U_4reg_cval <= "00000000"; + elsif (clk_clk_i'event and clk_clk_i='1') then + if (load3_o_i = '1') then + mw_U_4reg_cval <= adr_nxt_pc_o_internal(15 DOWNTO 8); + end if; + end if; + end process u_4seq_proc; + + -- ModuleWare code(v1.12) for instance 'U_6' of 'and' + load_o_i <= ld_pc_i and ld_i(0); + + -- ModuleWare code(v1.12) for instance 'U_7' of 'and' + load3_o_i <= ld_pc_i and ld_i(1); + + -- ModuleWare code(v1.12) for instance 'U_10' of 'and' + ci_o_i <= cout_pc_o_i and ld_pc_i; + + -- ModuleWare code(v1.12) for instance 'U_1' of 'constval' + val_zero <= "00000000"; + + -- ModuleWare code(v1.12) for instance 'U_9' of 'constval' + val_one <= "00000001"; + + -- ModuleWare code(v1.12) for instance 'U_8' of 'mux' + u_8combo_proc: process(adr_pc_o_internal, adr_i, sel_pc_in_i) + begin + case sel_pc_in_i is + when '0' => adr_pc_o_i <= adr_pc_o_internal; + when '1' => adr_pc_o_i <= adr_i; + when others => adr_pc_o_i <= (others => 'X'); + end case; + end process u_8combo_proc; + + -- ModuleWare code(v1.12) for instance 'U_13' of 'mux' + u_13combo_proc: process(val_one, val_zero, offset_low_o_i, + sel_pc_val_i) + begin + case sel_pc_val_i is + when "00" => val_o_i <= val_one; + when "01" => val_o_i <= val_zero; + when "10" => val_o_i <= offset_low_o_i; + when "11" => val_o_i <= val_zero; + when others => val_o_i <= (others => 'X'); + end case; + end process u_13combo_proc; + + -- ModuleWare code(v1.12) for instance 'U_3' of 'split' + mw_U_3temp_din <= adr_pc_o_i; + u_3combo_proc: process (mw_U_3temp_din) + variable temp_din: std_logic_vector(15 downto 0); + begin + temp_din := mw_U_3temp_din(15 downto 0); + adr_pc_low_o_i <= temp_din(7 downto 0); + adr_pc_high_o_i <= temp_din(15 downto 8); + end process u_3combo_proc; + + -- ModuleWare code(v1.12) for instance 'U_5' of 'split' + mw_U_5temp_din <= offset_i; + u_5combo_proc: process (mw_U_5temp_din) + variable temp_din: std_logic_vector(15 downto 0); + begin + temp_din := mw_U_5temp_din(15 downto 0); + offset_low_o_i <= temp_din(7 downto 0); + offset_high_o_i <= temp_din(15 downto 8); + end process u_5combo_proc; + + -- Instance port mappings. + + -- Implicit buffered output assignments + adr_nxt_pc_o <= adr_nxt_pc_o_internal; + adr_pc_o <= adr_pc_o_internal; + +end struct; Index: cpu65c02_true_cycle/trunk/released/rtl/vhdl/reg_sp.vhd =================================================================== --- cpu65c02_true_cycle/trunk/released/rtl/vhdl/reg_sp.vhd (nonexistent) +++ cpu65c02_true_cycle/trunk/released/rtl/vhdl/reg_sp.vhd (revision 23) @@ -0,0 +1,161 @@ +-- VHDL Entity r65c02_tc.reg_sp.symbol +-- +-- Created: +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 12:04:08 06.09.2018 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +entity reg_sp is + port( + adr_low_i : in std_logic_vector (7 downto 0); + clk_clk_i : in std_logic; + ld_low_i : in std_logic; + ld_sp_i : in std_logic; + rst_rst_n_i : in std_logic; + sel_sp_as_i : in std_logic; + sel_sp_in_i : in std_logic; + adr_sp_o : out std_logic_vector (15 downto 0) + ); + +-- Declarations + +end reg_sp ; + +-- (C) 2008 - 2018 Jens Gutschmidt +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 1.7 2013/07/21 11:11:00 jens +-- - Changing the title block and internal revision history +-- +-- Revision 1.6 2009/01/04 10:20:47 eda +-- Changes for cosmetic issues only +-- +-- Revision 1.5 2009/01/04 09:23:10 eda +-- - Delete unused nets and blocks (same as R6502_TC) +-- - Rename blocks +-- +-- Revision 1.4 2009/01/03 16:53:02 eda +-- - Unused nets and blocks deleted +-- - Renamed blocks +-- +-- Revision 1.3 2009/01/03 16:42:02 eda +-- - Unused nets and blocks deleted +-- - Renamed blocks +-- +-- Revision 1.2 2008/12/31 19:31:24 eda +-- Production Release +-- +-- +-- +-- VHDL Architecture r65c02_tc.reg_sp.struct +-- +-- Created: +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 12:04:08 06.09.2018 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt +-- +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. +-- +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + + +architecture struct of reg_sp is + + -- Architecture declarations + + -- Internal signal declarations + signal adr_sp_low_o_i : std_logic_vector(7 downto 0); + signal load_o_i : std_logic; + signal result_low1_o_i : std_logic_vector(7 downto 0); + signal result_low_o_i : std_logic_vector(7 downto 0); + signal sp_as_n_o_i : std_logic; + signal val_one : std_logic_vector(7 downto 0); + + -- Implicit buffer signal declarations + signal adr_sp_o_internal : std_logic_vector (15 downto 0); + + + -- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff' + signal mw_U_0reg_cval : std_logic_vector(7 downto 0); + + +begin + + -- ModuleWare code(v1.12) for instance 'U_11' of 'addsub' + u_11combo_proc: process (adr_sp_low_o_i, val_one, sp_as_n_o_i) + variable temp_din0 : std_logic_vector(8 downto 0); + variable temp_din1 : std_logic_vector(8 downto 0); + variable temp_sum : unsigned(8 downto 0); + variable temp_carry : std_logic; + begin + temp_din0 := '0' & adr_sp_low_o_i; + temp_din1 := '0' & val_one; + temp_carry := '0'; + if (sp_as_n_o_i = '1') then + temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry; + else + temp_sum := unsigned(temp_din0) - unsigned(temp_din1) - temp_carry; + end if; + result_low_o_i <= conv_std_logic_vector(temp_sum(7 downto 0),8); + end process u_11combo_proc; + + -- ModuleWare code(v1.12) for instance 'U_0' of 'adff' + adr_sp_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval; + u_0seq_proc: process (clk_clk_i, rst_rst_n_i) + begin + if (rst_rst_n_i = '0') then + mw_U_0reg_cval <= "00000000"; + elsif (clk_clk_i'event and clk_clk_i='1') then + if (load_o_i = '1') then + mw_U_0reg_cval <= result_low1_o_i; + end if; + end if; + end process u_0seq_proc; + + -- ModuleWare code(v1.12) for instance 'U_6' of 'and' + load_o_i <= ld_sp_i and ld_low_i; + + -- ModuleWare code(v1.12) for instance 'U_3' of 'buff' + adr_sp_o_internal(15 DOWNTO 8) <= val_one; + + -- ModuleWare code(v1.12) for instance 'U_4' of 'constval' + val_one <= "00000001"; + + -- ModuleWare code(v1.12) for instance 'U_2' of 'inv' + sp_as_n_o_i <= not(sel_sp_as_i); + + -- ModuleWare code(v1.12) for instance 'U_8' of 'mux' + u_8combo_proc: process(result_low_o_i, adr_low_i, sel_sp_in_i) + begin + case sel_sp_in_i is + when '0' => result_low1_o_i <= result_low_o_i; + when '1' => result_low1_o_i <= adr_low_i; + when others => result_low1_o_i <= (others => 'X'); + end case; + end process u_8combo_proc; + + -- ModuleWare code(v1.12) for instance 'U_10' of 'tap' + adr_sp_low_o_i <= adr_sp_o_internal(7 downto 0); + + -- Instance port mappings. + + -- Implicit buffered output assignments + adr_sp_o <= adr_sp_o_internal; + +end struct; Index: cpu65c02_true_cycle/trunk/released/rtl/vhdl/regbank_axy.vhd =================================================================== --- cpu65c02_true_cycle/trunk/released/rtl/vhdl/regbank_axy.vhd (nonexistent) +++ cpu65c02_true_cycle/trunk/released/rtl/vhdl/regbank_axy.vhd (revision 23) @@ -0,0 +1,207 @@ +-- VHDL Entity r65c02_tc.regbank_axy.symbol +-- +-- Created: +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 20:45:48 27.08.2018 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +entity regbank_axy is + port( + clk_clk_i : in std_logic; + d_regs_in_i : in std_logic_vector (7 downto 0); + load_regs_i : in std_logic; + rst_rst_n_i : in std_logic; + sel_rb_in_i : in std_logic_vector (1 downto 0); + sel_rb_out_i : in std_logic_vector (1 downto 0); + sel_reg_i : in std_logic_vector (1 downto 0); + d_regs_out_o : out std_logic_vector (7 downto 0); + q_a_o : out std_logic_vector (7 downto 0); + q_x_o : out std_logic_vector (7 downto 0); + q_y_o : out std_logic_vector (7 downto 0) + ); + +-- Declarations + +end regbank_axy ; + +-- (C) 2008 - 2018 Jens Gutschmidt +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 1.7 2013/07/21 11:11:00 jens +-- - Changing the title block and internal revision history +-- +-- Revision 1.6 2009/01/04 10:20:47 eda +-- Changes for cosmetic issues only +-- +-- Revision 1.5 2009/01/04 09:23:10 eda +-- - Delete unused nets and blocks (same as R6502_TC) +-- - Rename blocks +-- +-- Revision 1.4 2009/01/03 16:53:02 eda +-- - Unused nets and blocks deleted +-- - Renamed blocks +-- +-- Revision 1.3 2009/01/03 16:42:02 eda +-- - Unused nets and blocks deleted +-- - Renamed blocks +-- +-- Revision 1.2 2008/12/31 19:31:24 eda +-- Production Release +-- +-- +-- +-- VHDL Architecture r65c02_tc.regbank_axy.struct +-- +-- Created: +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 12:04:48 06.09.2018 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- +-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt +-- +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. +-- +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + + +architecture struct of regbank_axy is + + -- Architecture declarations + + -- Internal signal declarations + signal ld : std_logic_vector(2 downto 0); + signal load1_o_i : std_logic; + signal load2_o_i : std_logic; + signal load_o_i : std_logic; + signal q_mux_o_i : std_logic_vector(7 downto 0); + signal val_zero : std_logic_vector(7 downto 0); + + -- Implicit buffer signal declarations + signal q_a_o_internal : std_logic_vector (7 downto 0); + signal q_x_o_internal : std_logic_vector (7 downto 0); + signal q_y_o_internal : std_logic_vector (7 downto 0); + + + -- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff' + signal mw_U_0reg_cval : std_logic_vector(7 downto 0); + + -- ModuleWare signal declarations(v1.12) for instance 'U_4' of 'adff' + signal mw_U_4reg_cval : std_logic_vector(7 downto 0); + + -- ModuleWare signal declarations(v1.12) for instance 'U_5' of 'adff' + signal mw_U_5reg_cval : std_logic_vector(7 downto 0); + + +begin + + -- ModuleWare code(v1.12) for instance 'U_0' of 'adff' + q_a_o_internal <= mw_U_0reg_cval; + u_0seq_proc: process (clk_clk_i, rst_rst_n_i) + begin + if (rst_rst_n_i = '0') then + mw_U_0reg_cval <= "00000000"; + elsif (clk_clk_i'event and clk_clk_i='1') then + if (load_o_i = '1') then + mw_U_0reg_cval <= q_mux_o_i; + end if; + end if; + end process u_0seq_proc; + + -- ModuleWare code(v1.12) for instance 'U_4' of 'adff' + q_x_o_internal <= mw_U_4reg_cval; + u_4seq_proc: process (clk_clk_i, rst_rst_n_i) + begin + if (rst_rst_n_i = '0') then + mw_U_4reg_cval <= "00000000"; + elsif (clk_clk_i'event and clk_clk_i='1') then + if (load1_o_i = '1') then + mw_U_4reg_cval <= q_mux_o_i; + end if; + end if; + end process u_4seq_proc; + + -- ModuleWare code(v1.12) for instance 'U_5' of 'adff' + q_y_o_internal <= mw_U_5reg_cval; + u_5seq_proc: process (clk_clk_i, rst_rst_n_i) + begin + if (rst_rst_n_i = '0') then + mw_U_5reg_cval <= "00000000"; + elsif (clk_clk_i'event and clk_clk_i='1') then + if (load2_o_i = '1') then + mw_U_5reg_cval <= q_mux_o_i; + end if; + end if; + end process u_5seq_proc; + + -- ModuleWare code(v1.12) for instance 'U_6' of 'and' + load_o_i <= load_regs_i and ld(0); + + -- ModuleWare code(v1.12) for instance 'U_7' of 'and' + load1_o_i <= load_regs_i and ld(1); + + -- ModuleWare code(v1.12) for instance 'U_8' of 'and' + load2_o_i <= load_regs_i and ld(2); + + -- ModuleWare code(v1.12) for instance 'U_11' of 'constval' + val_zero <= "00000000"; + + -- ModuleWare code(v1.12) for instance 'U_1' of 'decoder1' + u_1combo_proc: process (sel_reg_i) + begin + ld <= (others => '0'); + case sel_reg_i is + when "00" => ld(0) <= '1'; + when "01" => ld(1) <= '1'; + when "10" => ld(2) <= '1'; + when others => ld <= (others => '0'); + end case; + end process u_1combo_proc; + + -- ModuleWare code(v1.12) for instance 'U_2' of 'mux' + u_2combo_proc: process(q_a_o_internal, q_x_o_internal, q_y_o_internal, + val_zero, sel_rb_out_i) + begin + case sel_rb_out_i is + when "00" => d_regs_out_o <= q_a_o_internal; + when "01" => d_regs_out_o <= q_x_o_internal; + when "10" => d_regs_out_o <= q_y_o_internal; + when "11" => d_regs_out_o <= val_zero; + when others => d_regs_out_o <= (others => 'X'); + end case; + end process u_2combo_proc; + + -- ModuleWare code(v1.12) for instance 'U_3' of 'mux' + u_3combo_proc: process(q_a_o_internal, q_y_o_internal, q_x_o_internal, + d_regs_in_i, sel_rb_in_i) + begin + case sel_rb_in_i is + when "00" => q_mux_o_i <= q_a_o_internal; + when "01" => q_mux_o_i <= q_y_o_internal; + when "10" => q_mux_o_i <= q_x_o_internal; + when "11" => q_mux_o_i <= d_regs_in_i; + when others => q_mux_o_i <= (others => 'X'); + end case; + end process u_3combo_proc; + + -- Instance port mappings. + + -- Implicit buffered output assignments + q_a_o <= q_a_o_internal; + q_x_o <= q_x_o_internal; + q_y_o <= q_y_o_internal; + +end struct;

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