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/dct_idct/trunk/dct/Bench/bmp_generator.vhd
0,0 → 1,401
---------------------------------------------------------------------
---- ----
---- DCT IP core ----
---- ----
---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
---- Company: Unicore Systems http://unicore.co.ua ----
---- ----
---- Downloaded from: http://www.opencores.org ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2006-2010 Unicore Systems LTD ----
---- www.unicore.co.ua ----
---- o.uzenkov@unicore.co.ua ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED "AS IS" ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.math_real.all;
 
entity BMP_GENERATOR is
generic( SIGNED_DATA : integer:= 0; -- input data - 0 - unsigned, 1 - signed
RANDOM:integer:=1 );
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
START: out STD_LOGIC;
DATA: out STD_LOGIC_VECTOR (7 downto 0):=x"01"
);
end BMP_GENERATOR;
 
 
architecture BMP_GENERATOR of BMP_GENERATOR is
type TLUT is array(0 to 2047 ) of integer;
Constant ROMBMP:Tlut:=( (
 
-- data patterns
108,-25,-127,-72,72,127, 25,-109,
108,-25,-127,-72,72,127, 25,-109,
108,-25,-127,-72,72,127, 25,-109,
108,-25,-127,-72,72,127, 25,-109,
108,-25,-127,-72,72,127, 25,-109,
108,-25,-127,-72,72,127, 25,-109,
108,-25,-127,-72,72,127, 25,-109,
108,-25,-127,-72,72,127, 25,-109,
127,127,127,127, 127,127,127,127,
52,52,52,52,52,52,52,52,
-52,-52,-52,-52,-52,-52,-52,-52,
-127,-127,-127,-127,-127,-127,-127,-127,
-127,-127,-127,-127,-127,-127,-127,-127,
-52,-52,-52,-52,-52,-52,-52,-52,
52,52,52,52,52,52,52,52,
127,127,127,127, 127,127,127,127,
127,52,-52,-127,-127,-52,52, 127,
127,52,-52,-127,-127,-52,52, 127,
127,52,-52,-127,-127,-52,52, 127,
127,52,-52,-127,-127,-52,52, 127,
127,52,-52,-127,-127,-52,52, 127,
127,52,-52,-127,-127,-52,52, 127,
127,52,-52,-127,-127,-52,52, 127,
127,52,-52,-127,-127,-52,52, 127,
52,-127,127,-52,-52,127,-127,52,
52,-127,127,-52,-52,127,-127,52,
52,-127,127,-52,-52,127,-127,52,
52,-127,127,-52,-52,127,-127,52,
52,-127,127,-52,-52,127,-127,52,
52,-127,127,-52,-52,127,-127,52,
52,-127,127,-52,-52,127,-127,52,
52,-127,127,-52,-52,127,-127,52,
127,90,0,-90,-127,-90,0,90,
127,90,0,-90,-127,-90,0,90,
127,90,0,-90,-127,-90,0,90,
127,90,0,-90,-127,-90,0,90,
127,90,0,-90,-127,-90,0,90,
127,90,0,-90,-127,-90,0,90,
127,90,0,-90,-127,-90,0,90,
127,90,0,-90,-127,-90,0,90,
127,-127,127,-127,127,-127,127,-127,
127,-127,127,-127,127,-127,127,-127,
127,-127,127,-127,127,-127,127,-127,
127,-127,127,-127,127,-127,127,-127,
127,-127,127,-127,127,-127,127,-127,
127,-127,127,-127,127,-127,127,-127,
127,-127,127,-127,127,-127,127,-127,
127,-127,127,-127,127,-127,127,-127,
127,-117,90,-49,0,-49,90,117,
127,-117,90,-49,0,-49,90,117,
127,-117,90,-49,0,-49,90,117,
127,-117,90,-49,0,-49,90,117,
127,-117,90,-49,0,-49,90,117,
127,-117,90,-49,0,-49,90,117,
127,-117,90,-49,0,-49,90,117,
127,-117,90,-49,0,-49,90,117,
0,117,90,-49,-127,-49,90,117,
0,117,90,-49,-127,-49,90,117,
0,117,90,-49,-127,-49,90,117,
0,117,90,-49,-127,-49,90,117,
0,117,90,-49,-127,-49,90,117,
0,117,90,-49,-127,-49,90,117,
0,117,90,-49,-127,-49,90,117,
0,117,90,-49,-127,-49,90,117,
127,-90, 0,90,-127,90,0,-90,
127,-90, 0,90,-127,90,0,-90,
127,-90, 0,90,-127,90,0,-90,
127,-90, 0,90,-127,90,0,-90,
127,-90, 0,90,-127,90,0,-90,
127,-90, 0,90,-127,90,0,-90,
127,-90, 0,90,-127,90,0,-90,
127,-90, 0,90,-127,90,0,-90,
127,-90,-90,127,-90,-90,127,-90,
127,-90,-90,127,-90,-90,127,-90,
127,-90,-90,127,-90,-90,127,-90,
127,-90,-90,127,-90,-90,127,-90,
127,-90,-90,127,-90,-90,127,-90,
127,-90,-90,127,-90,-90,127,-90,
127,-90,-90,127,-90,-90,127,-90,
127,-90,-90,127,-90,-90,127,-90,
127,90,0,-90,-127,-90,0,90,
127,90,0,-90,-127,-90,0,90,
127,90,0,-90,-127,-90,0,90,
127,90,0,-90,-127,-90,0,90,
127,90,0,-90,-127,-90,0,90,
127,90,0,-90,-127,-90,0,90,
127,90,0,-90,-127,-90,0,90,
127,90,0,-90,-127,-90,0,90,
128,128,128,128, 128,128,128,128,
128,128,128,128, 128,128,128,128,
128,128,128,128, 128,128,128,128,
128,128,128,128, 128,128,128,128,
128,128,128,128, 128,128,128,128,
128,128,128,128, 128,128,128,128,
128,128,128,128, 128,128,128,128,
128,128,128,128, 128,128,128,128,
127,127,127,127, 127,127,127,127,
127,127,127,127, 127,127,127,127,
127,127,127,127, 127,127,127,127,
127,127,127,127, 127,127,127,127,
127,127,127,127, 127,127,127,127,
127,127,127,127, 127,127,127,127,
127,127,127,127, 127,127,127,127,
127,127,127,127, 127,127,127,127,
127,127,127,127,127,127,127,127,
117,117,117,117,117,117,117,117,
90,90,90,90, 90,90,90,90,
49,49,49,49,49,49,49,49,
0,0,0,0,0,0,0,0,
49,49,49,49,49,49,49,49,
90,90,90,90, 90,90,90,90,
117,117,117,117,117,117,117,117,
127, 117, 90, 49,00,49,90,117,
127, 117, 90, 49,00,49,90,117,
127, 117, 90, 49,00,49,90,117,
127, 117, 90, 49,00,49,90,117,
127, 117, 90, 49,00,49,90,117,
127, 117, 90, 49,00,49,90,117,
127, 117, 90, 49,00,49,90,117,
127, 117, 90, 49,00,49,90,117,
127,127,127,127,127,127,127,127,
90,90,90,90, 90,90,90,90,
0,0,0,0,0,0,0,0,
-90,-90,-90,-90, -90,-90,-90,-90,
-127,-127,-127,-127,-127,-127,-127,-127,
-90,-90,-90,-90, -90,-90,-90,-90,
0,0,0,0,0,0,0,0,
90,90,90,90, 90,90,90,90,
255, 255, 255, 255, 255, 255, 255, 255,
255, 255, 255, 255, 255, 255, 255, 255,
255, 255, 255, 255, 255, 255, 255, 255,
255, 255, 255, 255, 255, 255, 255, 255,
255, 255, 255, 255, 255, 255, 255, 255,
255, 255, 255, 255, 255, 255, 255, 255,
255, 255, 255, 255, 255, 255, 255, 255,
255, 255, 255, 255, 255, 255, 255, 255,
--
0,255,0,255,0,255,0,255,
0,255,0,255,0,255,0,255,
0,255,0,255,0,255,0,255,
0,255,0,255,0,255,0,255,
0,255,0,255,0,255,0,255,
0,255,0,255,0,255,0,255,
0,255,0,255,0,255,0,255,
0,255,0,255,0,255,0,255,
0,127,0,127, 0,127,0,127,
0,127,0,127, 0,127,0,127,
0,127,0,127, 0,127,0,127,
0,127,0,127, 0,127,0,127,
0,127,0,127, 0,127,0,127,
0,127,0,127, 0,127,0,127,
0,127,0,127, 0,127,0,127,
0,127,0,127,0,127,0,127,
0,0,0,0,0,0,0,0, --3
255,255,255,255,255,255,255,255,
0,0,0,0,0,0,0,0,
255,255,255,255,255,255,255,255,
0,0,0,0,0,0,0,0,
255,255,255,255,255,255,255,255,
0,0,0,0,0,0,0,0,
255,255,255,255,255,255,255,255,
255, 255, 255, 255, 255, 255, 255, 255,
255, 255, 255, 255, 255, 255, 255, 255,
255, 255, 255, 255, 255, 255, 255, 255,
255, 255, 255, 255, 255, 255, 255, 255,
0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,
183, 160, 94, 153, 194, 163, 132, 165,
183, 153, 116, 176, 187, 166, 130, 169,
179, 168, 171, 182, 179, 165, 131, 167,
177, 177, 179, 177, 179, 165, 131, 167,
178, 178, 179, 176, 182, 164, 130, 171,
179, 180, 180, 179, 183, 169, 132, 169,
179, 179, 180, 182, 183, 170, 129, 172,
180, 179, 181, 179, 181, 170, 130, 169,
0,32,64,96,128, 160,192,224,
224,192,160,128,96, 64,32, 0,
0,32,64,96,128, 160,192,224,
224,192,160,128,96, 64,32, 0,
0,32,64,96,128, 160,192,224,
224,192,160,128,96, 64,32, 0,
0,32,64,96,128, 160,192,224,
224,192,160,128,96, 64,32, 0,
128, 128, 128, 128, 128, 128, 128, 128,
128, 128, 128, 128, 128, 128, 128, 128,
128, 128, 192, 192, 192, 192, 128, 128,
128, 128, 192, 192, 192, 192, 128, 128,
128, 128, 192, 192, 192, 192, 128, 128,
128, 128, 192, 192, 192, 192, 128, 128,
128, 128, 128, 128, 128, 128, 128, 128,
128, 128, 128, 128, 128, 128, 128, 128,
90,100,110,120,130,140,150,160,
91,101,111,121,131,141,151,161,
92,102,112,122,132,142,152,162,
93,103,113,123,133,143,153,163,
90,100,110,120,130,140,150,160,
91,101,111,121,131,141,151,161,
92,102,112,122,132,142,152,162,
93,103,113,123,133,143,153,163,
0,32,64,96,128, 160,192,224,
0,32,64,96,128, 160,192,224,
0,32,64,96,128, 160,192,224,
0,32,64,96,128, 160,192,224,
0,32,64,96,128, 160,192,224,
0,32,64,96,128, 160,192,224,
0,32,64,96,128, 160,192,224,
0,32,64,96,128, 160,192,224,
183, 160, 94, 153, 194, 163, 132, 165,
183, 153, 116, 176, 187, 166, 130, 169,
179, 168, 171, 182, 179, 165, 131, 167,
177, 177, 179, 177, 179, 165, 131, 167,
178, 178, 179, 176, 182, 164, 130, 171,
179, 180, 180, 179, 183, 169, 132, 169,
179, 179, 180, 182, 183, 170, 129, 173,
180, 179, 181, 179, 181, 170, 130, 169,
159, 128, 198, 128, 128, 128, 140, 128,
128, 128, 128, 128, 128, 128, 128, 128,
198, 128, 155, 128, 128, 128, 166, 128,
128, 128, 128, 128, 128, 128, 128, 128,
128, 128, 128, 128, 128, 128, 128, 128,
128, 128, 128, 128, 128, 128, 128, 128,
140, 128, 156, 128, 128, 128, 132, 128,
128, 128, 128, 128, 128, 128, 128, 128,
others=>127
));
signal dr,DATAi: STD_LOGIC_VECTOR (7 downto 0);
signal index: integer range 0 to 2048;
begin
process(clk) --Generator of random images
variable a,b:integer:=333;
variable s:real;
variable d,d1,d2,d3,d4,do:integer:=0;
begin
if clk='1' then
UNIFORM( a,b,s);
d4:=d3;
d3:=d2;
d2:=d1;
d1:=d;
d:=integer(s*2.0**8);
--some LP filtering
do :=(d +4*d1+ 6*d2+4*d3+d4)/16;
dr<=conv_std_logic_vector(do,8) ;
end if;
end process;
DATA_OUTPUT:process(CLK,RST)
variable delay: integer;
variable STARTi: STD_LOGIC;
variable startdel:boolean;
begin
if RST='1' then
startdel:=false;
STARTi:='0';
delay:=0;
elsif CLK='1' and CLK'event and delay<10000 then
delay:=delay+1;
if delay=10 or delay=11 then--or delay=500 or delay= 501 or delay=800 or delay= 801 then
STARTi:='1' ;
elsif delay=12 then --or delay= 502 or delay= 802 then
STARTi:='0';
startdel:=true;
end if;
end if;
if RST='1' then
index<=0;
elsif CLK='1' and CLK'event and startdel then
if RANDOM=0 then
DATAi<=CONV_STD_LOGIC_VECTOR(INTEGER(ROMBMP(index)),8) after 7 ns;
index<=(index+1) mod 2048;
else
DATAi<=dr;
end if;
end if;
START<=STARTi after 5 ns;
end process;
DATA<= unsigned(DATAi)-UNSIGNED(X"80") when SIGNED_DATA=0 else DATAi;
end BMP_GENERATOR;
/dct_idct/trunk/dct/Bench/dct_beh.vhd
0,0 → 1,295
---------------------------------------------------------------------
---- ----
---- DCT IP core ----
---- ----
---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
---- Company: Unicore Systems http://unicore.co.ua ----
---- ----
---- Downloaded from: http://www.opencores.org ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2006-2010 Unicore Systems LTD ----
---- www.unicore.co.ua ----
---- o.uzenkov@unicore.co.ua ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED "AS IS" ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
 
entity DCT_BEH is
generic( SIGNED_DATA: integer);
port (
DATAIN: in STD_LOGIC_VECTOR (7 downto 0);
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
EN: in STD_LOGIC;
START: in STD_LOGIC;
READY : out STD_LOGIC:='0';
DATAOUT: out STD_LOGIC_VECTOR ( 11 downto 0) --:=x"0000"
);
end DCT_BEH;
 
 
architecture DCT_BEH of DCT_BEH is
type TLUT2 is array(0 to 255 ) of real;
type TLUT3 is array(0 to 63 ) of real;
type TLUT1 is array(0 to 255 ) of std_logic_vector(7 downto 0);
constant LATENCY:integer:=3; -- 40; --51;
constant c : real := 0.7071;
constant c0 : real := 0.9808;
constant c1 : real := 0.8315;
constant c2 : real := 0.5556;
constant c3 : real := 0.1951;
constant c4 : real := 0.9239;
constant c5 : real := 0.3827;
Constant c6 : real := 0.7071;
constant c0i : real := -0.9808;
constant c1i : real := -0.8315;
constant c2i : real := -0.5556;
constant c3i : real := -0.1951;
constant c4i : real := -0.9239;
constant c5i : real := -0.3827;
Constant c6i : real := -0.7071;
Constant ROM3:Tlut3:=( (
c,c,c,c,c,c,c,c,
c0,c1,c2,c3,c3i,c2i,c1i,c0i,
c4,c5,c5i,c4i,c4i,c5i,c5,c4,
c1,c3i,c0i,c2i,c2,c0,c3,c1i,
c6,c6i,c6i,c6,c6,c6i,c6i,c6,
c2,c0i,c3,c1,c1i,c3i,c0,c2i,
c5,c4i,c4,c5i,c5i,c4,c4i,c5,
c3,c2i,c1,c0i,c0,c1i,c2,c3i
));
Constant ROM4:Tlut3:=( (
c,c0,c4,c1,c6,c2,c5,c3,
c,c1,c5,c3i,c6i,c0i,c4i,c2i,
c,c2,c5i,c0i,c6i,c3,c4,c1,
c,c3,c4i,c2i,c6,c1,c5i,c0i,
c,c3i,c4i,c2,c6,c1i,c5i,c0,
c,c2i,c5i,c0,c6i,c3i,c4,c1i,
c,c1i,c5,c3,c6i,c0,c4i,c2,
c,c0i,c4,c1i,c6,c2i,c5,c3i
));
signal RESET: std_logic;
signal COEF : STD_LOGIC_VECTOR (6 downto 0);
signal X,X11,DATAINi: STD_LOGIC_VECTOR (7 downto 0);
signal Y1,y2: STD_LOGIC_VECTOR (15 downto 0);
signal Y,DATAOUTi: STD_LOGIC_VECTOR (11 downto 0);
signal K1,K2,X1,k8,couna: INTEGER;
signal k3,k4,k7: real;
signal ram00,ramres,ramt : tlut3;
signal prov,prov1: std_logic_vector (7 downto 0);
signal inarray,inarray0,tmpar1,tmpar2,tmpar3: tlut3;
signal index: integer range 0 to 63;
signal CLK64,eoutput,indataready,indataready2, startdel,startd1,startd2, startfix,readyi:boolean;
signal delay,cycle: integer:=0;
begin
G1: if SIGNED_DATA=1 generate
DATAINi<=DATAIN;
end generate;
G0: if SIGNED_DATA=0 generate
DATAINi<=unsigned (DATAIN) - 128;
end generate;
DATA_INPUT: process(CLK,RST,START)
variable index: integer range 0 to 64;
begin
if RST='1' or START='1' then
index:=0; indataready<=false;
for i in 0 to 63 loop
inarray0(i)<=0.0;
end loop;
elsif CLK='1' and CLK'event then
if en='1' then
inarray0(index)<=REAL(CONV_INTEGER(SIGNED(DATAINi)));
index:=(index+1) mod 64;
if index=63 then
indataready<=true;
else
indataready<=false;
end if;
end if;
end if;
end process;
DATAREADY:process(CLK)
begin
if CLK'event and CLK='1' then
if en='1' then
indataready2<=indataready;
if indataready2 then
inarray<=inarray0;
end if;
end if;
end if;
end process;
DCT: process --Discrete Cosine Transform calculation
variable cc0,cc1,cc2,cc3,cc4,cc5,cc6: real;
variable ac0,ac1,ac2,ac3,ac4,ac5,ac6,ac7: real;
variable s,i,j,k: integer;
begin
for s in 0 to 7 loop
for j in 0 to 7 loop
ac0:= 0.0;
for i in 0 to 7 loop
cc0 := rom3(s*8 + i);
cc1 := (inarray(j + i*8)); -- - 128.0);
ac0 := ac0 + cc0 * cc1;
end loop;
ram00(s*8 +j) <= ac0;
ramt(j*8 +s)<=ac0/2.0;
wait for 1 ps;
end loop;
end loop;
wait for 5 ps;
for s in 0 to 7 loop
for j in 0 to 7 loop
ac0:= 0.0;
for i in 0 to 7 loop
cc0 := ram00(s*8 + i);
cc1 := rom3(j*8 + i);
ac0 := ac0 + cc0 * cc1;
end loop;
ramres(s*8 +j) <= ac0/8.0; --results
wait for 1 ps;
end loop;
end loop;
wait on indataready2;
end process;
-- CLK64<= indataready ;
DATA_OUTPUT:process(CLK,RST,START)
-- variable delay: integer;
begin
if RST='1' or START='1' then
startfix<=false;
elsif START='0' and START'event then
startfix<=true;
end if;
if RST='1' or START='1' then
eoutput<=false;
startdel<=false;
delay<=0;
elsif rising_edge(CLK) and startd2 then
if en='1' then
startdel<=(delay=LATENCY); --momemt of 1 st result ready
delay<=delay+1;
if startdel then
eoutput<=true;
end if;
end if;
end if;
if RST='1' or START='1' then
cycle<=0;
readyi<=false;
elsif rising_edge(CLK) and eoutput then
if en='1' then
cycle<=(cycle+1) mod 64;
end if;
end if;
readyi<= cycle = 63 or startdel; -- 63
if readyi then READY<= '1' ; else READY<= '0'; end if;
if RST='1' or STARTDel then
index<=0;
elsif CLK='1' and CLK'event and eoutput then --
if en='1' then
index<=(index+1) mod 64;
end if;
end if;
end process;
process(clk,rst)
begin
if RST='1' or STARTDel then
DATAOUT<= (others => '0');
elsif CLK='1' and CLK'event and eoutput then --
if en='1' then
DATAOUT<=CONV_STD_LOGIC_VECTOR(INTEGER( tmpar2(index)),12); -- 12
DATAOUTi<=CONV_STD_LOGIC_VECTOR(INTEGER( ramt((index-14) mod 64)),12); -- 16
end if;
end if;
end process;
RESULT_ARRAY: process(readyi,CLK)
begin
if CLK='1' and CLK'event and readyi then
if en='1' then
tmpar2<=tmpar1;
end if;
end if;
end process ;
DELAYED:process ( indataready2,START,RESET) --delay for 128 cycles
begin
if START='1' or RESET='1' then
startd2<=false;
startd1<=false;
elsif indataready2 and indataready2'event then
if en='1' then
for i in 0 to 63 loop
tmpar1(i)<=ramres(i)*2.0; --SCALING !!!
end loop;
startd2<=startd1;
startd1<=STARTFIX;
end if;
end if;
end process;
end DCT_BEH;
/dct_idct/trunk/dct/Bench/test_dct.vhd
0,0 → 1,199
---------------------------------------------------------------------
---- ----
---- DCT IP core ----
---- ----
---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
---- Company: Unicore Systems http://unicore.co.ua ----
---- ----
---- Downloaded from: http://www.opencores.org ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2006-2010 Unicore Systems LTD ----
---- www.unicore.co.ua ----
---- o.uzenkov@unicore.co.ua ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED "AS IS" ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.math_real.all;
 
entity TEST_DCT is
generic( SIGNED_DATA : integer:= 1; -- input data - 0 - unsigned, 1 - signed
RANDOM:integer:=0; --1 - random test data ; 0 - predefined
scale_out:integer:=0 );
 
end TEST_DCT;
 
 
 
architecture TEST_DCT of TEST_DCT is
 
signal DATAIN : STD_LOGIC_VECTOR (7 downto 0);
signal DCT,dct1 : STD_LOGIC_VECTOR (11 downto 0);
signal DCTi : STD_LOGIC_VECTOR (11 downto 0);
signal DCTRES : integer;
signal DCTRES_STD : integer;
signal DCT_STD : STD_LOGIC_VECTOR (11 downto 0);
signal ERROR : integer;
signal QUADMEAN : REAL;
signal READY,ready1 : STD_LOGIC;
signal READY_STD : STD_LOGIC;
signal START,EN : STD_LOGIC;
signal CLK,clk1 : STD_LOGIC;
signal RST : STD_LOGIC;
signal r,rb,max, serror1, num,num1, serror : integer;
component DCT_AAN is
generic(
d_signed:integer:=1; --1 input data signed; 0 - unsigned, and for compression 1/2 is subtracted
scale_out:integer:=1); -- 1 output data are scaled; 0 - genuine DCT
port(
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
START: in STD_LOGIC; -- after this impulse the 0-th datum is sampled
EN: in STD_LOGIC; -- operation enable to slow-down the calculations
DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
RDY : out STD_LOGIC;
DATA_OUT : out STD_LOGIC_VECTOR(11 downto 0)
);
end component;
component DCT_BEH
generic( SIGNED_DATA: integer);
port (
CLK : in STD_LOGIC;
DATAIN : in STD_LOGIC_VECTOR (7 downto 0);
RST : in STD_LOGIC;
EN: in STD_LOGIC;
START : in STD_LOGIC;
DATAOUT : out STD_LOGIC_VECTOR (11 downto 0);
READY : out STD_LOGIC := '0'
);
end component;
component BMP_GENERATOR
generic( SIGNED_DATA : integer:= 0; -- input data - 0 - unsigned, 1 - signed
RANDOM:integer:=1 );
port (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
DATA : out STD_LOGIC_VECTOR (7 downto 0);
START : out STD_LOGIC
);
end component;
begin
process begin CLK<='0'; wait for 5ns;CLK<='1'; wait for 5ns;
end process;
process begin RST<='1'; wait for 50ns;RST<='0'; wait;
end process;
en <= '1';
clk1 <= clk;
U1 : BMP_GENERATOR
generic map( SIGNED_DATA, -- input data - 0 - unsigned, 1 - signed
RANDOM)
port map(
CLK => CLK,
DATA => DATAIN,
RST => RST,
START => START
);
U2 : DCT_AAN
generic map( d_SIGNED => SIGNED_DATA, scale_out =>scale_out )
port map(
CLK => CLK1,
DATA_IN => DATAIN,
EN => EN,
DATA_OUT => DCT,
RDY => READY,
RST => RST,
START => START
);
U3 : DCT_BEH
generic map( SIGNED_DATA => SIGNED_DATA)
port map(
CLK => CLK,
DATAIN => DATAIN,
DATAOUT => DCT_STD,
EN => EN,
READY => READY_STD,
RST => RST,
START => START
);
r<=CONV_INTEGER(SIGNED(DCT));
rb<=CONV_INTEGER(SIGNED(DCT_STD));
ERROR <= r - rb;
ERROR_CALC:process(start,error, READY_STD,clk)
variable SUMERROR:integer;
variable start_acc:boolean:=false;
begin
if start = '1' or RST='1' then
max <= 0; serror1 <= 0; num <= 0; serror <= 0;
QUADMEAN<=0.0; SUMERROR:=0;
start_acc:=false;
end if;
if READY='1' then
start_acc:=true;
end if;
if READY_STD = '0' and READY_STD'event then
num <= num + 1;
serror <= 0;
serror1 <= serror;
if start_acc then
SUMERROR:=serror; -- SUMERROR +
end if;
if num>0 then
QUADMEAN<=SQRT(REAL(SUMERROR)/(64.0*REAL(num)));
end if;
if max < serror then
max <= serror;
num1 <= num;
end if;
end if;
if clk = '1' and clk'event and start_acc then
serror <= serror + (error * error); --
end if;
end process;
end TEST_DCT;
/dct_idct/trunk/dct/RTL/DCT8AAN1.vhd
0,0 → 1,333
---------------------------------------------------------------------
---- ----
---- DCT IP core ----
---- ----
---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
---- Company: Unicore Systems http://unicore.co.ua ----
---- ----
---- Downloaded from: http://www.opencores.org ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2006-2010 Unicore Systems LTD ----
---- www.unicore.co.ua ----
---- o.uzenkov@unicore.co.ua ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED "AS IS" ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-- DESCRIPTION:
--
-- FUNCTION Discrete Cosine Transform of 8 samples using algorithm by
-- Arai, Agui, and Nakajama
-- input data bit width: 8 bit , signed or unsigned
-- output data bit width: 10 bit
-- coefficient bit width: 11 bit
-- Synthesable for FPGAs of any vendor, preferably for Xilinx FPGA
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
 
entity DCT8AAN1 is
generic( d_signed:integer:=1;--1 input data signed 0 - unsigned, and for compression 1/2 is subtracted
scale_out:integer:=1); -- 1 output data are scaled 0 - genuine DCT
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
START: in STD_LOGIC; -- after this impulse the 0-th datum is sampled
EN: in STD_LOGIC; -- operation enable to slow-down the calculations
DATA_IN: in STD_LOGIC_VECTOR (7 downto 0);
RDY: out STD_LOGIC; -- delayed START impulse, after it the 0-th result is outputted
DATA_OUT: out STD_LOGIC_VECTOR (9 downto 0) -- output data
);
end DCT8AAN1;
 
 
architecture STAGE of DCT8AAN1 is
type Tarr8 is array(0 to 7) of STD_LOGIC_VECTOR (10 downto 0);
type Tarr16 is array (0 to 15) of STD_LOGIC_VECTOR (7 downto 0);
signal sr16:TARR16:=(others=>(others=>'0')); -- SRL16 array
constant S:Tarr8:=--(0.5/sqrt(2.0), 0.25/cos(pii*1.0),0.25/cos(pii*2.0),0.25/cos(pii*3.0),
-- 0.25/cos(pii*4.0),0.25/cos(pii*5.0),0.25/cos(pii*6.0),0.25/cos(pii*7.0));
(conv_std_logic_vector(integer(0.35355*2.0**9),11),
conv_std_logic_vector(integer(0.2549*2.0**9),11),
conv_std_logic_vector(integer(0.2706*2.0**9),11),
conv_std_logic_vector(integer(0.30067*2.0**9),11),
conv_std_logic_vector(integer(0.35355*2.0**9),11),
conv_std_logic_vector(integer(0.44999*2.0**9),11),
conv_std_logic_vector(integer(0.65328*2.0**9),11),
conv_std_logic_vector(integer(1.2815*2.0**9),11) );
constant m1 : STD_LOGIC_VECTOR (10 downto 0) := conv_std_logic_vector(integer(0.70711*2.0**9),11); --cos(pii*4.0); --
constant m2 : STD_LOGIC_VECTOR (10 downto 0) := conv_std_logic_vector(integer(0.38268*2.0**9),11);--cos(pii*6.0); --
constant m3 : STD_LOGIC_VECTOR (10 downto 0) := conv_std_logic_vector(integer(0.5412 *2.0**9),11);--(cos(pii*2.0) - cos(pii*6.0)); --
constant m4 : STD_LOGIC_VECTOR (10 downto 0) := conv_std_logic_vector(integer(1.3066*2.0**9),11);--cos(pii*2.0) + cos(pii*6.0); --
constant zeros : STD_LOGIC_VECTOR (5 downto 0) := (others => '0');
constant a1_2 : STD_LOGIC_VECTOR (7 downto 0) := "10"&zeros;
signal sr: STD_LOGIC_VECTOR (10 downto 0) ;
signal cycle,ad1,cycle6: integer range 0 to 7;
signal cycles: integer range 0 to 31;
signal di,a1,a2,a3,a4: STD_LOGIC_VECTOR (7 downto 0);
signal bp,bm,b1,b2,b3,b4,b6:STD_LOGIC_VECTOR (8 downto 0);
signal cp,cm,c1,c2,c3,c4:STD_LOGIC_VECTOR (10 downto 0);
signal dp,dm:STD_LOGIC_VECTOR (11 downto 0);
signal rd:STD_LOGIC_VECTOR (11 downto 0);
signal ep:STD_LOGIC_VECTOR (22 downto 0);
signal e27:STD_LOGIC_VECTOR (10 downto 0);
signal m1_4:STD_LOGIC_VECTOR (10 downto 0);
signal fp,fm,f45,s7,s07,spt:STD_LOGIC_VECTOR (11 downto 0);
signal SP : STD_LOGIC_VECTOR (22 downto 0);
begin
UU_COUN0:process(CLK,RST)
begin
if RST = '1' then
cycle <=0;
cycle6 <=(-6) mod 8;
ad1<= ( - 5) mod 8;
cycles <=16;
RDY<='0';
elsif CLK = '1' and CLK'event then
if en = '1' then
RDY<='0';
if START = '1' then
cycle <=0;
cycle6 <=(-6) mod 8;
ad1<= ( - 5) mod 8;
cycles <=0;
elsif en = '1' then
cycle<=(cycle +1) mod 8 ;
cycle6<=(cycle6 +1) mod 8 ;
ad1<=(ad1 +1) mod 8;
if cycles=15 then
RDY<='1';
end if;
if cycles/=17 then
cycles<=(cycles +1) ;
end if;
end if;
end if;
end if;
end process;
SRL16_a:process(CLK) begin -- SRL16
if CLK'event and CLK='1' then
if en='1' and (cycle=1 or cycle=2 or cycle=3 or cycle=4) then
sr16<=di & sr16(0 to 14); -- shift SRL16
end if;
end if;
end process;
a1<= sr16(ad1); -- output from SRL16
SM_B:process(clk,rst)
begin
if RST = '1' then
di <= (others => '0');
bp <= (others => '0');
bm <= (others => '0');
elsif CLK = '1' and CLK'event then
if en = '1' then
if d_signed =0 then
di<=unsigned(DATA_IN) - unsigned( a1_2);
else
di<=DATA_IN;
end if;
bp<=SXT(di,9) + a1;
bm<=a1 - SXT(di,9);
end if;
end if;
end process;
SM_C:process(clk,rst)
begin
if RST = '1' then
b1 <= (others => '0');
b2 <= (others => '0');
b3 <= (others => '0');
b4 <= (others => '0');
b6 <= (others => '0');
cp <= (others => '0');
cm <= (others => '0');
c1 <= (others => '0');
elsif CLK = '1' and CLK'event then
if en = '1' then
b1<=bp;
b2<=b1;
if cycle = 2 then
b3<=b4;
else
b3<=b2;
end if;
b4<=b3;
b6<=bm;
case cycle is
when 0|1|7 =>cp<=SXT(bm,11)+b6;
when 2|3 =>cp<= SXT(b2,11)+b3;
when others=> cp<=cp+c1;
end case;
c1<=cp;
if cycle=2 or cycle=3 then
cm<=SXT(b2,11) - b3;
else
cm<=cp - c1;
end if;
end if;
end if;
end process;
SM_D:process(clk,rst)
begin
if RST = '1' then
c2 <= (others => '0');
c3 <= (others => '0');
c4 <= (others => '0');
--s6 <= (others => '0');
dp <= (others => '0');
dm <= (others => '0');
elsif CLK = '1' and CLK'event then
if en = '1' then
if cycle=3 or cycle=4 or cycle=5 then
c2<=cm;
end if;
if cycle = 1 then
c3<=c1;
end if;
if cycle = 2 then
c4<=SXT(b6,11);
elsif cycle=5 then
c4<=c2;
end if;
if cycle = 4 then
dp<= SXT(cm, 12)+c2(10 downto 0);
else
dp<= ep(20 downto 9)+c4(10 downto 0);
end if;
if cycle = 2 then
dm<= c3(10 downto 0) - SXT(cp, 12);
elsif cycle=3 or cycle =7 then
dm<= c4(10 downto 0) - ep(20 downto 9);
end if;
end if;
end if;
end process;
MPU1:process(clk,rst)
begin
if CLK = '1' and CLK'event then
if en = '1' then
case cycle is
when 1|5 => m1_4<=m1;
when 2 => m1_4<=m4;
when 3 => m1_4<=m2;
when others => m1_4<=m3;
end case ;
case cycle is
when 1|2 => rd<= SXT(cp,12);
when 3 => rd<=dm;
when 4 => rd<= SXT(c3,12);
when others => rd<=dp;
end case ;
ep<=rd*m1_4;
e27<= ep(19 downto 9);
end if;
end if;
end process;
SM_F:process(clk,rst)
begin
if RST = '1' then
fp <= (others => '0');
fm <= (others => '0');
f45 <= (others => '0');
s7 <= (others => '0');
elsif CLK = '1' and CLK'event then
if en = '1' then
case cycle is
when 3 => fp<=ep(19 downto 9) + SXT(c4,12);
when 5 => fp<=ep(19 downto 9) + SXT(e27,12);
when 6|0 => fp<=fp + f45;
when 7 => fp<=e27 +f45;
when others=> null;
end case;
if cycle=4 then
f45<=fp;
elsif cycle=6 then
f45<=SXT(e27,12);
elsif cycle=7 or cycle=0 then
f45<=SXT(dm,12);
end if;
fm<=f45 - fp;
if cycle=7 then
s7<=fm;
end if;
end if;
end if;
end process;
MPU2:process(clk,rst)
begin
if CLK = '1' and CLK'event then
if en = '1' then
sr<=s(cycle6);
case cycle is
when 6 => s07<= SXT(c1,12);
when 7|3 => s07<=fp;
when 0 => s07<= SXT(dp,12);
when 1 => s07<= SXT(fm,12);
when 2 => s07<= SXT(c2,12);
when 4 => s07<= SXT(f45,12);
when others => s07<=s7;
end case ;
if scale_out =0 then
sp<=s07*sr;
DATA_OUT <=sp(18 downto 9);
else
spt<=s07;
DATA_OUT <= spt(10 downto 1);
end if;
end if;
end if;
end process;
end STAGE;
/dct_idct/trunk/dct/RTL/DCT8AAN2.vhd
0,0 → 1,332
---------------------------------------------------------------------
---- ----
---- DCT IP core ----
---- ----
---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
---- Company: Unicore Systems http://unicore.co.ua ----
---- ----
---- Downloaded from: http://www.opencores.org ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2006-2010 Unicore Systems LTD ----
---- www.unicore.co.ua ----
---- o.uzenkov@unicore.co.ua ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED "AS IS" ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-- DESCRIPTION:
--
-- FUNCTION Discrete Cosine Transform of 8 samples using algorithm by
-- Arai, Agui, and Nakajama
-- input data bit width: 10 bit , signed or unsigned
-- output data bit width: 12 bit
-- coefficient bit width: 11 bit
-- Synthesable for FPGAs of any vendor, preferably for Xilinx FPGA
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
 
entity DCT8AAN2 is
generic( d_signed:integer:=1; --1 input data signed; 0 - unsigned, and for compression 1/2 is subtracted
scale_out:integer:=0); -- 1 output data are scaled; 0 - genuine DCT
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
START: in STD_LOGIC; -- after this impulse the 0-th datum is sampled
EN: in STD_LOGIC; -- operation enable to slow-down the calculations
DATA_IN: in STD_LOGIC_VECTOR (9 downto 0);
RDY: out STD_LOGIC; -- delayed START impulse, after it the 0-th result is outpitted
DATA_OUT: out STD_LOGIC_VECTOR (11 downto 0) -- output data
);
end DCT8AAN2;
 
 
architecture STAGE of DCT8AAN2 is
type Tarr8 is array(0 to 7) of STD_LOGIC_VECTOR (10 downto 0);
type Tarr16 is array (0 to 15) of STD_LOGIC_VECTOR (9 downto 0);
signal sr16:TARR16:=(others=>(others=>'0')); -- SRL16
constant S:Tarr8:=--(0.5/sqrt(2.0), 0.25/cos(pii*1.0),0.25/cos(pii*2.0),0.25/cos(pii*3.0),
-- 0.25/cos(pii*4.0),0.25/cos(pii*5.0),0.25/cos(pii*6.0),0.25/cos(pii*7.0));
(conv_std_logic_vector(integer(0.35355*2.0**9),11),
conv_std_logic_vector(integer(0.2549*2.0**9),11),
conv_std_logic_vector(integer(0.2706*2.0**9),11),
conv_std_logic_vector(integer(0.30067*2.0**9),11),
conv_std_logic_vector(integer(0.35355*2.0**9),11),
conv_std_logic_vector(integer(0.44999*2.0**9),11),
conv_std_logic_vector(integer(0.65328*2.0**9),11),
conv_std_logic_vector(integer(1.2815*2.0**9),11) );
constant m1 : STD_LOGIC_VECTOR (10 downto 0) := conv_std_logic_vector(integer(0.70711*2.0**9),11); --cos(pii*4.0); --
constant m2 : STD_LOGIC_VECTOR (10 downto 0) := conv_std_logic_vector(integer(0.38268*2.0**9),11);--cos(pii*6.0); --
constant m3 : STD_LOGIC_VECTOR (10 downto 0) := conv_std_logic_vector(integer(0.5412 *2.0**9),11);--(cos(pii*2.0) - cos(pii*6.0)); --
constant m4 : STD_LOGIC_VECTOR (10 downto 0) := conv_std_logic_vector(integer(1.3066*2.0**9),11);--cos(pii*2.0) + cos(pii*6.0); --
constant zeros : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
constant a1_2 : STD_LOGIC_VECTOR (9 downto 0) := "10"&zeros;
signal sr: STD_LOGIC_VECTOR (10 downto 0) ;
signal cycle,ad1,cycle6: integer range 0 to 7;
signal cycles: integer range 0 to 16;
signal di,a1,a2,a3,a4: STD_LOGIC_VECTOR (9 downto 0);
signal bp,bm,b1,b2,b3,b4,b6:STD_LOGIC_VECTOR (10 downto 0);
signal cp,cm,c1,c2,c3,c4:STD_LOGIC_VECTOR (12 downto 0);
signal dp,dm:STD_LOGIC_VECTOR (12 downto 0);
signal rd:STD_LOGIC_VECTOR (12 downto 0);
signal ep:STD_LOGIC_VECTOR (23 downto 0);
signal e27:STD_LOGIC_VECTOR (12 downto 0);
signal m1_4:STD_LOGIC_VECTOR (10 downto 0);
signal fp,fm,f45,s7,s07,spt:STD_LOGIC_VECTOR (13 downto 0);
signal SP : STD_LOGIC_VECTOR (24 downto 0);
begin
UU_COUN0:process(CLK,RST)
begin
if RST = '1' then
cycle <=0;
cycle6 <=(-6) mod 8;
ad1<= ( - 5) mod 8;
cycles <=16;
RDY<='0';
elsif CLK = '1' and CLK'event then
if en = '1' then
RDY<='0';
if START = '1' then
cycle <=0;
cycle6 <=(-6) mod 8;
ad1<= ( - 5) mod 8;
cycles <=0;
elsif en = '1' then
cycle<=(cycle +1) mod 8 ;
cycle6<=(cycle6 +1) mod 8 ;
ad1<=(ad1 +1) mod 8;
if cycles=15 then
RDY<='1';
end if;
if cycles/=16 then
cycles<=(cycles +1) ;
end if;
end if;
end if;
end if;
end process;
SRL16_a:process(CLK) begin -- SRL16
if CLK'event and CLK='1' then
if en='1' and (cycle=1 or cycle=2 or cycle=3 or cycle=4) then
sr16<=di & sr16(0 to 14); -- shift SRL16
end if;
end if;
end process;
a1<= sr16(ad1); -- output from SRL16
SM_B:process(clk,rst)
begin
if RST = '1' then
di <= (others => '0');
bp <= (others => '0');
bm <= (others => '0');
elsif CLK = '1' and CLK'event then
if en = '1' then
if d_signed =0 then
di<=unsigned(DATA_IN) - unsigned( a1_2);
else
di<=DATA_IN;
end if;
bp<=SXT(di,11) + a1;
bm<=a1 - SXT(di,11);
end if;
end if;
end process;
SM_C:process(clk,rst)
begin
if RST = '1' then
b1 <= (others => '0');
b2 <= (others => '0');
b3 <= (others => '0');
b4 <= (others => '0');
b6 <= (others => '0');
cp <= (others => '0');
cm <= (others => '0');
c1 <= (others => '0');
elsif CLK = '1' and CLK'event then
if en = '1' then
b1<=bp;
b2<=b1;
if cycle = 2 then
b3<=b4;
else
b3<=b2;
end if;
b4<=b3;
b6<=bm;
case cycle is
when 0|1|7 =>cp<=SXT(bm,13)+b6;
when 2|3 =>cp<= SXT(b2,13)+b3;
when others=> cp<=cp+c1;
end case;
c1<=cp;
if cycle=2 or cycle=3 then
cm<=SXT(b2,13) - b3;
else
cm<=cp - c1;
end if;
end if;
end if;
end process;
SM_D:process(clk,rst)
begin
if RST = '1' then
c2 <= (others => '0');
c3 <= (others => '0');
c4 <= (others => '0');
dp <= (others => '0');
dm <= (others => '0');
elsif CLK = '1' and CLK'event then
if en = '1' then
if cycle=3 or cycle=4 or cycle=5 then
c2<=cm;
end if;
if cycle = 1 then
c3<=c1;
end if;
if cycle = 2 then
c4<=SXT(b6,13);
elsif cycle=5 then
c4<=c2;
end if;
if cycle = 4 then
dp<= SXT(cm, 13)+c2(12 downto 0);
else
dp<= ep(21 downto 9)+c4(12 downto 0);
end if;
if cycle = 2 then
dm<= c3(12 downto 0) - SXT(cp, 13);
elsif cycle=3 or cycle =7 then
dm<= c4(12 downto 0) - ep(21 downto 9);
end if;
end if;
end if;
end process;
MPU1:process(clk,rst)
begin
if CLK = '1' and CLK'event then
if en = '1' then
case cycle is
when 1|5 => m1_4<=m1;
when 2 => m1_4<=m4;
when 3 => m1_4<=m2;
when others => m1_4<=m3;
end case ;
case cycle is
when 1|2 => rd<= SXT(cp,13);
when 3 => rd<=dm;
when 4 => rd<= SXT(c3,13);
when others => rd<=dp;
end case ;
ep<=rd*m1_4;
e27<= ep(21 downto 9);
end if;
end if;
end process;
SM_F:process(clk,rst)
begin
if RST = '1' then
fp <= (others => '0');
fm <= (others => '0');
f45 <= (others => '0');
s7 <= (others => '0');
elsif CLK = '1' and CLK'event then
if en = '1' then
case cycle is
when 3 => fp<=ep(21 downto 9) + SXT(c4,14);
when 5 => fp<=ep(21 downto 9) + SXT(e27,14);
when 6|0 => fp<=fp + f45;
when 7 => fp<=e27 +f45;
when others=> null;
end case;
if cycle=4 then
f45<=fp;
elsif cycle=6 then
f45<=SXT(e27,14);
elsif cycle=7 or cycle=0 then
f45<=SXT(dm,14);
end if;
fm<=f45 - fp;
if cycle=7 then
s7<=fm;
end if;
end if;
end if;
end process;
MPU2:process(clk,rst)
begin
if CLK = '1' and CLK'event then
if en = '1' then
sr<=s(cycle6);
case cycle is
when 6 => s07<= SXT(c1,14);
when 7|3 => s07<=fp;
when 0 => s07<= SXT(dp,14);
when 1 => s07<= SXT(fm,14);
when 2 => s07<= SXT(c2,14);
when 4 => s07<= SXT(f45,14);
when others => s07<=s7;
end case ;
if scale_out =0 then
sp<=s07*sr;
DATA_OUT <=sp(20 downto 9);
else
spt<=s07;
DATA_OUT <= spt(12 downto 1);
end if;
end if;
end if;
end process;
end STAGE;
/dct_idct/trunk/dct/RTL/DCT_BUF.vhd
0,0 → 1,137
---------------------------------------------------------------------
---- ----
---- DCT IP core ----
---- ----
---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
---- Company: Unicore Systems http://unicore.co.ua ----
---- ----
---- Downloaded from: http://www.opencores.org ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2006-2010 Unicore Systems LTD ----
---- www.unicore.co.ua ----
---- o.uzenkov@unicore.co.ua ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED "AS IS" ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--DESCRIPTION:
--
-- FUNCTION 64 data are stored to the FIFO buffer
-- 64 data read from FIFO taps in the transposed order.
-- Synthesable for Xilinx FPGAs.
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
 
entity DCT_BUF is
generic( wi: integer:= 10 -- input data width
);
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
START: in STD_LOGIC; -- after this impulse the 0-th datum is sampled
EN: in STD_LOGIC; -- operation enable to slow-down the calculations
DATA_IN: in STD_LOGIC_VECTOR (wi-1 downto 0);
RDY: out STD_LOGIC; -- delayed START impulse, after it the 0-th result is outputted
DATA_OUT: out STD_LOGIC_VECTOR (wi-1 downto 0) -- output data
);
end DCT_BUF;
 
 
architecture SRL16 of DCT_BUF is
constant rnd: STD_LOGIC:='0';
type Tarr100 is array (0 to 99) of STD_LOGIC_VECTOR (wi -1 downto 0);
type Tarr64i is array (0 to 63) of integer range 0 to 127 ;
constant Addrr:Tarr64i:=
(49,50-8, 51-16,52-24, 53-32,54-40,55-48,56-56,
56, 57-8, 58-16,59-24, 60-32,61-40,62-48,63-56,
63, 64-8, 65-16,66-24, 67-32,68-40,69-48,70-56,
70, 71-8, 72-16,73-24, 74-32,75-40,76-48,77-56,
77, 78-8, 79-16,80-24, 81-32,82-40,83-48,84-56,
84, 85-8, 86-16,87-24, 88-32,89-40,90-48,91-56,
91, 92-8, 93-16,94-24, 95-32,96-40,97-48,98-56,
98, 99-8,100-16,101-24,102-32,103-40,104-48,105-56);
 
signal cycle,ad1: integer range 0 to 63;
signal ad2: integer range 0 to 99;
signal cycles: integer range 0 to 63;
begin
UU_COUN:process(CLK,RST)
begin
if RST = '1' then
ad1<= ( - 5) mod 64;
cycles <=63;
RDY<='0';
elsif CLK = '1' and CLK'event then
if en = '1' then
RDY<='0';
if START = '1' then
ad1<= ( - 48) mod 64;
cycles <=0;
elsif en = '1' then
ad1<=(ad1 +1) mod 64;
RDY<='0';
if cycles/=63 then
cycles<=(cycles +1) ;
end if;
if cycles=48 then
RDY<='1';
ad1 <=0;
end if;
end if;
end if;
end if;
end process;
SRL16_a:process(CLK) begin -- SRL16
if CLK'event and CLK='1' then
if en='1' then
sr64<=DATA_IN & sr64(0 to 98); -- shift SRL16
ad2<= Addrr(ad1) ; --FIFO address recoding
end if;
end if;
end process;
DATA_OUT <=sr64(ad2); -- output from SRL16
end SRL16;
/dct_idct/trunk/dct/RTL/DCT_AAN.vhd
0,0 → 1,169
---------------------------------------------------------------------
---- ----
---- DCT IP core ----
---- ----
---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
---- Company: Unicore Systems http://unicore.co.ua ----
---- ----
---- Downloaded from: http://www.opencores.org ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2006-2010 Unicore Systems LTD ----
---- www.unicore.co.ua ----
---- o.uzenkov@unicore.co.ua ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED "AS IS" ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-- DESCRIPTION:
--
-- FUNCTION 2-D Discrete Cosine Transform of for 8x8 samples using algorithm by
-- Arai, Agui, and Nakajama
-- input data bit width: 8 bit , signed or unsigned
-- output data bit width: 12 bit
-- coefficient bit width: 11 bit.
-- When output data are scaled then the number of multipliers is equal to 2.
-- Buffer memories are based on FIFO
-- Synthesable for FPGAs of any vendor, preferably for Xilinx FPGA
--
--
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity DCT_AAN is
generic(
d_signed:integer:=1; --1 input data signed; 0 - unsigned, and for compression 1/2 is subtracted
scale_out:integer:=0); -- 1 output data are scaled; 0 - genuine DCT
port(
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
START: in STD_LOGIC; -- after this impulse the 0-th datum is sampled
EN: in STD_LOGIC; -- operation enable to slow-down the calculations
DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
RDY : out STD_LOGIC;
DATA_OUT : out STD_LOGIC_VECTOR(11 downto 0)
);
end DCT_AAN;
 
architecture CONSTR of DCT_AAN is
component DCT8AAN1 is
generic( d_signed:integer:=1; --1 input data signed 0 - unsigned, and for compression 1/2 is subtracted
scale_out:integer:=0); -- 1 output data are scaled 0 - genuine DCT
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
START: in STD_LOGIC; -- after this impulse the 0-th datum is sampled
EN: in STD_LOGIC; -- operation enable to slow-down the calculations
DATA_IN: in STD_LOGIC_VECTOR (7 downto 0);
RDY: out STD_LOGIC; -- delayed START impulse, after it the 0-th result is outputted
DATA_OUT: out STD_LOGIC_VECTOR (9 downto 0) -- output data
);
end component ;
component DCT8AAN2 is
generic( d_signed:integer:=1; --1 input data signed; 0 - unsigned, and for compression 1/2 is subtracted
scale_out:integer:=0); -- 1 output data are scaled; 0 - genuine DCT
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
START: in STD_LOGIC; -- after this impulse the 0-th datum is sampled
EN: in STD_LOGIC; -- operation enable to slow-down the calculations
DATA_IN: in STD_LOGIC_VECTOR (9 downto 0);
RDY: out STD_LOGIC; -- delayed START impulse, after it the 0-th result is outpitted
DATA_OUT: out STD_LOGIC_VECTOR (11 downto 0) -- output data
);
end component;
component DCT_BUF is
generic( wi: integer:= 10 -- input data width
);
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
START: in STD_LOGIC; -- after this impulse the 0-th datum is sampled
EN: in STD_LOGIC; -- operation enable to slow-down the calculations
DATA_IN: in STD_LOGIC_VECTOR (wi-1 downto 0);
RDY: out STD_LOGIC; -- delayed START impulse, after it the 0-th result is outputted
DATA_OUT: out STD_LOGIC_VECTOR (wi-1 downto 0) -- output data
);
end component ;
signal rdy1,rdy2,rdy3 : STD_LOGIC;
signal data1,data1r: STD_LOGIC_VECTOR (9 downto 0);
signal data2: STD_LOGIC_VECTOR (11 downto 0);
begin
U_ST1: DCT8AAN1
generic map( d_signed=>d_signed, --1 input data signed 0 - unsigned, and for compression 1/2 is subtracted
scale_out=>scale_out) -- 1 output data are scaled 0 - genuine DCT
port map(CLK, RST,
START =>START, -- after this impulse the 0-th datum is sampled
EN =>EN, -- operation enable to slow-down the calculations
DATA_IN =>DATA_IN,
RDY =>rdy1, -- delayed START impulse, just after it the 0-th result is outputted
DATA_OUT=>data1 -- output data
);
U_B1:DCT_BUF
generic map( wi=> 10 -- input data width
)
port map(CLK, RST,
START=>rdy1, -- after this impulse the 0-th datum is sampled
EN=>EN, -- operation enable to slow-down the calculations
DATA_IN=>data1,
RDY=>rdy2, -- delayed START impulse, after it the 0-th result is outputted
DATA_OUT=>data1r -- output data
);
U_ST2: DCT8AAN2
generic map( d_signed=>1, --1 input data signed 0 - unsigned, and for compression 1/2 is subtracted
scale_out=>scale_out) -- 1 output data are scaled 0 - genuine DCT
port map(CLK, RST,
START =>rdy2, -- after this impulse the 0-th datum is sampled
EN =>EN, -- operation enable to slow-down the calculations
DATA_IN =>data1r,
RDY =>rdy3, -- delayed START impulse, after it the 0-th result is outputted
DATA_OUT=>data2 -- output data
);
U_B2:DCT_BUF
generic map( wi=> 12 -- input data width
)
port map(CLK, RST,
START=>rdy3, -- after this impulse the 0-th datum is sampled
EN=>EN, -- operation enable to slow-down the calculations
DATA_IN=>data2,
RDY=>RDY, -- delayed START impulse, after it the 0-th result is outputted
DATA_OUT=>DATA_OUT -- output data
);
 
end CONSTR;
/dct_idct/trunk/dct/Doc/dct_um.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/dct_idct/trunk/dct/Doc/dct_um.pdf
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