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URL https://opencores.org/ocsvn/dqpskmap/dqpskmap/trunk

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/trunk/test/d_encoder_d_decoder_tb.vhd
0,0 → 1,168
 
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY d_encoder_d_decoder_tb IS
END d_encoder_d_decoder_tb;
ARCHITECTURE behavior OF d_encoder_d_decoder_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT d_encoder_d_decoder
PORT(
tx_tetra_clk_36_KHz : IN std_logic;
tx_tetra_clk_18_KHz : IN std_logic;
tx_tetra_rst : IN std_logic;
tx_tetra_bit_stream_input : IN std_logic;
tx_tetra_valid_input : IN std_logic;
tx_tetra_debug_dbit_output : OUT std_logic_vector(1 downto 0);
tx_tetra_diffPhaseEncoder_output_0 : OUT std_logic_vector(7 downto 0);
tx_tetra_diffPhaseEncoder_output_1 : OUT std_logic_vector(7 downto 0);
rx_clk_18_KHz : IN std_logic;
rx_rst : IN std_logic;
rx_en : IN std_logic;
rx_a_k : OUT std_logic_vector(7 downto 0);
rx_b_k : OUT std_logic_vector(7 downto 0);
rx_i_k : IN std_logic_vector(7 downto 0);
rx_q_k : IN std_logic_vector(7 downto 0)
);
END COMPONENT;
 
--Inputs
signal tx_tetra_clk_36_KHz : std_logic := '0';
signal tx_tetra_clk_18_KHz : std_logic := '0';
signal tx_tetra_rst : std_logic := '0';
signal tx_tetra_bit_stream_input : std_logic := '0';
signal tx_tetra_valid_input : std_logic := '0';
signal rx_clk_18_KHz : std_logic := '0';
signal rx_rst : std_logic := '0';
signal rx_en : std_logic := '0';
signal rx_i_k : std_logic_vector(7 downto 0) := (others => '0');
signal rx_q_k : std_logic_vector(7 downto 0) := (others => '0');
 
--Outputs
signal tx_tetra_debug_dbit_output : std_logic_vector(1 downto 0);
signal tx_tetra_diffPhaseEncoder_output_0 : std_logic_vector(7 downto 0);
signal tx_tetra_diffPhaseEncoder_output_1 : std_logic_vector(7 downto 0);
signal rx_a_k : std_logic_vector(7 downto 0);
signal rx_b_k : std_logic_vector(7 downto 0);
signal start_decoding : std_logic;
constant tetra_clk_36_KHz_period : time := 27.778 us;
constant tetra_clk_18_KHz_period : time := 55.556 us;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: d_encoder_d_decoder PORT MAP (
tx_tetra_clk_36_KHz => tx_tetra_clk_36_KHz,
tx_tetra_clk_18_KHz => tx_tetra_clk_18_KHz,
tx_tetra_rst => tx_tetra_rst,
tx_tetra_bit_stream_input => tx_tetra_bit_stream_input,
tx_tetra_valid_input => tx_tetra_valid_input,
tx_tetra_debug_dbit_output => tx_tetra_debug_dbit_output,
tx_tetra_diffPhaseEncoder_output_0 => tx_tetra_diffPhaseEncoder_output_0,
tx_tetra_diffPhaseEncoder_output_1 => tx_tetra_diffPhaseEncoder_output_1,
rx_clk_18_KHz => rx_clk_18_KHz,
rx_rst => rx_rst,
rx_en => rx_en,
rx_a_k => rx_a_k,
rx_b_k => rx_b_k,
rx_i_k => rx_i_k,
rx_q_k => rx_q_k
);
tetra_clk_36_KHz_process :process
begin
tx_tetra_clk_36_KHz <= '0';
wait for tetra_clk_36_KHz_period/2;
tx_tetra_clk_36_KHz <= '1';
wait for tetra_clk_36_KHz_period/2;
end process;
tetra_clk_18_KHz_process :process
begin
tx_tetra_clk_18_KHz <= '0';
rx_clk_18_KHz <= '0';
wait for tetra_clk_18_KHz_period/2;
tx_tetra_clk_18_KHz <= '1';
rx_clk_18_KHz <= '1';
wait for tetra_clk_18_KHz_period/2;
end process;
rx_i_k <= tx_tetra_diffPhaseEncoder_output_0 when start_decoding = '1' else (others=>'0');
rx_q_k <= tx_tetra_diffPhaseEncoder_output_1 when start_decoding = '1' else (others=>'0');
rx_en <= '1' when start_decoding = '1' else '0';
decode_tx: process
begin
wait for 166.668 us;
start_decoding <= '1';
wait;
end process;
 
-- Stimulus process
stim_proc: process
begin
tx_tetra_rst <= '1';
rx_rst <= '1';
wait for tetra_clk_18_KHz_period*2;
tx_tetra_rst <= '0';
rx_rst <= '0';
 
tx_tetra_valid_input <= '1';
tx_tetra_bit_stream_input <= '1';
wait for tetra_clk_36_KHz_period;
tx_tetra_bit_stream_input <= '0';
wait for tetra_clk_36_KHz_period;
tx_tetra_bit_stream_input <= '1';
wait for tetra_clk_36_KHz_period;
tx_tetra_bit_stream_input <= '1';
wait for tetra_clk_36_KHz_period;
 
tx_tetra_bit_stream_input <= '0';
wait for tetra_clk_36_KHz_period;
tx_tetra_bit_stream_input <= '0';
wait for tetra_clk_36_KHz_period;
tx_tetra_bit_stream_input <= '1';
wait for tetra_clk_36_KHz_period;
tx_tetra_bit_stream_input <= '1';
wait for tetra_clk_36_KHz_period*50;
wait;
 
-- insert stimulus here
 
wait;
end process;
 
END;
/trunk/rtl/TETRA_phy.vhd
0,0 → 1,111
 
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity TETRA_phy is
 
port(tetra_clk_36_KHz : in std_logic;
tetra_clk_18_KHz : in std_logic;
tetra_rst : in std_logic;
tetra_bit_stream_input : in STD_LOGIC;
tetra_valid_input : in STD_LOGIC;
tetra_debug_dbit_output : out std_logic_vector(1 downto 0);
tetra_diffPhaseEncoder_output_0 : out std_logic_vector(7 downto 0);
tetra_diffPhaseEncoder_output_1 : out std_logic_vector(7 downto 0)
);
end TETRA_phy;
 
architecture Behavioral of TETRA_phy is
 
component dataConverter is
Port (clk_36_KHz : in STD_LOGIC;
rst : in std_logic;
bit_stream_input : in STD_LOGIC;
valid_input : in STD_LOGIC;
dbit_output : out std_logic_vector(1 downto 0));
end component;
 
component biPolarEncoder is
Port (bit_input : in std_logic;
valid_input : in STD_LOGIC;
bi_polar_output : out std_logic_vector(1 downto 0));
end component;
 
component diffPhaseEncoder is
port(clk_18_KHz: in std_logic;
rst: in std_logic;
en: in std_logic;
a_k : in std_logic;
b_k : in std_logic;
i_k : out std_logic_vector(7 downto 0);
q_k : out std_logic_vector(7 downto 0));
end component;
signal dc_dbit_output_tmp : std_logic_vector(1 downto 0);
signal valid_input_diffPhaseEncoder_1_s : std_logic;
signal valid_input_diffPhaseEncoder_2_s : std_logic;
signal tetra_diffPhaseEncoder_output_0_tmp : std_logic_vector(7 downto 0);
signal tetra_diffPhaseEncoder_output_1_tmp : std_logic_vector(7 downto 0);
 
begin
DCONV: dataConverter port map (tetra_clk_36_KHz,
tetra_rst,
tetra_bit_stream_input,
tetra_valid_input,
dc_dbit_output_tmp);
 
PHENC: diffPhaseEncoder port map (tetra_clk_18_KHz,
tetra_rst,
valid_input_diffPhaseEncoder_2_s, --valid_input_diffPhaseEncoder_s,
dc_dbit_output_tmp(1),
dc_dbit_output_tmp(0),
tetra_diffPhaseEncoder_output_0_tmp,
tetra_diffPhaseEncoder_output_1_tmp);
tetra_debug_dbit_output <= dc_dbit_output_tmp;
tetra_diffPhaseEncoder_output_0 <= tetra_diffPhaseEncoder_output_0_tmp;
tetra_diffPhaseEncoder_output_1 <= tetra_diffPhaseEncoder_output_1_tmp;
delay_biPolarEncoder_1: process(tetra_clk_18_KHz, tetra_valid_input)
variable valid_input_diffPhaseEncoder_v : std_logic := '0';
begin
if falling_edge(tetra_clk_36_KHz) then
valid_input_diffPhaseEncoder_v := tetra_valid_input;
end if;
valid_input_diffPhaseEncoder_1_s <= valid_input_diffPhaseEncoder_v;
end process;
 
delay_biPolarEncoder_2: process(tetra_clk_18_KHz, tetra_valid_input, valid_input_diffPhaseEncoder_1_s)
variable valid_input_diffPhaseEncoder_v : std_logic := '0';
begin
if falling_edge(tetra_clk_36_KHz) then
valid_input_diffPhaseEncoder_v := valid_input_diffPhaseEncoder_1_s;
end if;
valid_input_diffPhaseEncoder_2_s <= valid_input_diffPhaseEncoder_v;
end process;
end Behavioral;
 
/trunk/rtl/diffPhaseDecoder.vhd
0,0 → 1,60
 
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity diffPhaseDecoder is
port(clk_18_KHz: in std_logic;
rst: in std_logic;
en: in std_logic;
a_k : out std_logic_vector(7 downto 0);
b_k : out std_logic_vector(7 downto 0);
i_k : in std_logic_vector(7 downto 0);
q_k : in std_logic_vector(7 downto 0));
end diffPhaseDecoder;
 
architecture Behavioral of diffPhaseDecoder is
 
begin
 
phase_decoder: process(clk_18_KHz, en, i_k, q_k)
variable i_k_old : signed(7 downto 0) := (others=>'0');
variable q_k_old : signed(7 downto 0) := (others=>'0');
variable a_k_tmp : signed(15 downto 0) := (others=>'0');
variable b_k_tmp : signed(15 downto 0) := (others=>'0');
begin
if falling_edge(clk_18_KHz) and en = '1' then
if rst = '1' then
i_k_old := "00000001";
q_k_old := "00000000";
else
a_k_tmp := signed(i_k)*i_k_old + signed(q_k)*q_k_old;
b_k_tmp := i_k_old*signed(q_k) - signed(i_k)*q_k_old;
i_k_old := signed(i_k);
q_k_old := signed(q_k);
end if;
end if;
a_k <= std_logic_vector(sxt(std_logic_vector(a_k_tmp), a_k'length));
b_k <= std_logic_vector(sxt(std_logic_vector(b_k_tmp), b_k'length));
end process;
 
end Behavioral;
 
/trunk/rtl/dataConverter.vhd
0,0 → 1,51
 
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity dataConverter is
Port (clk_36_KHz : in STD_LOGIC;
rst : in std_logic;
bit_stream_input : in STD_LOGIC;
valid_input : in STD_LOGIC;
dbit_output : out std_logic_vector(1 downto 0));
end dataConverter;
 
architecture Behavioral of dataConverter is
signal s_reg_s : std_logic_vector(1 downto 0);
begin
shift_reg: process(clk_36_KHz, rst, bit_stream_input)
variable s_reg_v : std_logic_vector(1 downto 0) := (others=>'0');
begin
if rst = '1' then
s_reg_v := (others=>'0');
elsif falling_edge(clk_36_KHz) and valid_input = '1' then
s_reg_v(1) := s_reg_v(0);
s_reg_v(0) := bit_stream_input;
end if;
s_reg_s <= s_reg_v;
end process;
dbit_output <= s_reg_s;
end Behavioral;
 
/trunk/rtl/diffPhaseEncoder.vhd
0,0 → 1,221
 
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity diffPhaseEncoder is
port(clk_18_KHz: in std_logic;
rst: in std_logic;
en: in std_logic;
a_k : in std_logic;
b_k : in std_logic;
i_k : out std_logic_vector(7 downto 0);
q_k : out std_logic_vector(7 downto 0));
end diffPhaseEncoder;
 
architecture Behavioral of diffPhaseEncoder is
-- constellation values arranged as fixed point 8-bit, 6-bit fractional.
 
constant c_minus_0_7 : std_logic_vector(7 downto 0) := "10100101";
constant c_plus_0_7 : std_logic_vector(7 downto 0) := "01011011";
constant c_plus_1 : std_logic_vector(7 downto 0) := "01111111";
constant c_minus_1 : std_logic_vector(7 downto 0) := "10000000";
constant c_plus_0 : std_logic_vector(7 downto 0) := "00000000";
type state is (plus_0_plus_1,
plus_0_7_plus_0_7,
plus_1_plus_0,
plus_0_7_minus_0_7,
plus_0_minus_1,
minus_0_7_minus_0_7,
minus_1_plus_0,
minus_0_7_plus_0_7);
signal pr_state : state;
signal nx_state : state;
begin
 
fsm_seq: process(clk_18_KHz, rst)
begin
if falling_edge(clk_18_KHz) then
if rst = '1' then
pr_state <= plus_1_plus_0;
else
pr_state <= nx_state;
end if;
end if;
end process;
 
fsm_comb: process(pr_state, a_k, b_k, en)
begin
case pr_state is
when plus_0_plus_1 =>
i_k <= c_plus_0;
q_k <= c_plus_1;
 
if en = '1' then
if (a_k = '0' and b_k = '0') then
nx_state <= minus_0_7_plus_0_7;
elsif (a_k = '0' and b_k = '1') then
nx_state <= minus_0_7_minus_0_7;
elsif (a_k = '1' and b_k = '0') then
nx_state <= plus_0_7_plus_0_7;
else -- 1, 1
nx_state <= plus_0_7_minus_0_7;
end if;
else
nx_state <= plus_0_plus_1;
end if;
when plus_0_7_plus_0_7 =>
i_k <= c_plus_0_7;
q_k <= c_plus_0_7;
if en = '1' then
if (a_k = '0' and b_k = '0') then
nx_state <= plus_0_plus_1;
elsif (a_k = '0' and b_k = '1') then
nx_state <= minus_1_plus_0;
elsif (a_k = '1' and b_k = '0') then
nx_state <= plus_1_plus_0;
else -- 1, 1
nx_state <= plus_0_minus_1;
end if;
else
nx_state <= plus_0_7_plus_0_7;
end if;
when plus_1_plus_0 =>
i_k <= c_plus_1;
q_k <= c_plus_0;
if en = '1' then
if (a_k = '0' and b_k = '0') then
nx_state <= plus_0_7_plus_0_7;
elsif (a_k = '0' and b_k = '1') then
nx_state <= minus_0_7_plus_0_7;
elsif (a_k = '1' and b_k = '0') then
nx_state <= plus_0_7_minus_0_7;
else -- 1, 1
nx_state <= minus_0_7_minus_0_7;
end if;
else
nx_state <= plus_1_plus_0;
end if;
when plus_0_7_minus_0_7 =>
i_k <= c_plus_0_7;
q_k <= c_minus_0_7;
if en = '1' then
if (a_k = '0' and b_k = '0') then
nx_state <= plus_1_plus_0;
elsif (a_k = '0' and b_k = '1') then
nx_state <= plus_0_plus_1;
elsif (a_k = '1' and b_k = '0') then
nx_state <= plus_0_minus_1;
else -- 1, 1
nx_state <= minus_1_plus_0;
end if;
else
nx_state <= plus_0_7_minus_0_7;
end if;
when plus_0_minus_1 =>
i_k <= c_plus_0;
q_k <= c_minus_1;
if en = '1' then
if (a_k = '0' and b_k = '0') then
nx_state <= plus_0_7_minus_0_7;
elsif (a_k = '0' and b_k = '1') then
nx_state <= plus_0_7_plus_0_7;
elsif (a_k = '1' and b_k = '0') then
nx_state <= minus_0_7_minus_0_7;
else -- 1, 1
nx_state <= minus_0_7_plus_0_7;
end if;
else
nx_state <= plus_0_minus_1;
end if;
when minus_0_7_minus_0_7 =>
i_k <= c_minus_0_7;
q_k <= c_minus_0_7;
if en = '1' then
if (a_k = '0' and b_k = '0') then
nx_state <= plus_0_minus_1;
elsif (a_k = '0' and b_k = '1') then
nx_state <= plus_1_plus_0;
elsif (a_k = '1' and b_k = '0') then
nx_state <= minus_1_plus_0;
else -- 1, 1
nx_state <= plus_0_plus_1;
end if;
else
nx_state <= minus_0_7_minus_0_7;
end if;
when minus_1_plus_0 =>
i_k <= c_minus_1;
q_k <= c_plus_0;
if en = '1' then
if (a_k = '0' and b_k = '0') then
nx_state <= minus_0_7_minus_0_7;
elsif (a_k = '0' and b_k = '1') then
nx_state <= plus_0_7_minus_0_7;
elsif (a_k = '1' and b_k = '0') then
nx_state <= minus_0_7_plus_0_7;
else -- 1, 1
nx_state <= plus_0_7_plus_0_7;
end if;
else
nx_state <= minus_1_plus_0;
end if;
when minus_0_7_plus_0_7 =>
i_k <= c_minus_0_7;
q_k <= c_plus_0_7;
if en = '1' then
if (a_k = '0' and b_k = '0') then
nx_state <= minus_1_plus_0;
elsif (a_k = '0' and b_k = '1') then
nx_state <= plus_0_minus_1;
elsif (a_k = '1' and b_k = '0') then
nx_state <= plus_0_plus_1;
else -- 1, 1
nx_state <= plus_1_plus_0;
end if;
else
nx_state <= minus_0_7_plus_0_7;
end if;
end case;
end process;
 
 
end Behavioral;
 
/trunk/rtl/d_encoder_d_decoder.vhd
0,0 → 1,85
 
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity d_encoder_d_decoder is
port(tx_tetra_clk_36_KHz : in std_logic;
tx_tetra_clk_18_KHz : in std_logic;
tx_tetra_rst : in std_logic;
tx_tetra_bit_stream_input : in STD_LOGIC;
tx_tetra_valid_input : in STD_LOGIC;
tx_tetra_debug_dbit_output : out std_logic_vector(1 downto 0);
tx_tetra_diffPhaseEncoder_output_0 : out std_logic_vector(7 downto 0);
tx_tetra_diffPhaseEncoder_output_1 : out std_logic_vector(7 downto 0);
rx_clk_18_KHz: in std_logic;
rx_rst: in std_logic;
rx_en: in std_logic;
rx_a_k : out std_logic_vector(7 downto 0);
rx_b_k : out std_logic_vector(7 downto 0);
rx_i_k : in std_logic_vector(7 downto 0);
rx_q_k : in std_logic_vector(7 downto 0)
);
end d_encoder_d_decoder;
 
architecture Behavioral of d_encoder_d_decoder is
 
component TETRA_phy is
port(tetra_clk_36_KHz : in std_logic;
tetra_clk_18_KHz : in std_logic;
tetra_rst : in std_logic;
tetra_bit_stream_input : in STD_LOGIC;
tetra_valid_input : in STD_LOGIC;
tetra_debug_dbit_output : out std_logic_vector(1 downto 0);
tetra_diffPhaseEncoder_output_0 : out std_logic_vector(7 downto 0);
tetra_diffPhaseEncoder_output_1 : out std_logic_vector(7 downto 0)
);
end component;
 
component diffPhaseDecoder is
port(clk_18_KHz: in std_logic;
rst: in std_logic;
en: in std_logic;
a_k : out std_logic_vector(7 downto 0);
b_k : out std_logic_vector(7 downto 0);
i_k : in std_logic_vector(7 downto 0);
q_k : in std_logic_vector(7 downto 0));
end component;
 
begin
 
TETRA_TX : TETRA_phy port map (tx_tetra_clk_36_KHz,
tx_tetra_clk_18_KHz,
tx_tetra_rst,
tx_tetra_bit_stream_input,
tx_tetra_valid_input,
tx_tetra_debug_dbit_output,
tx_tetra_diffPhaseEncoder_output_0,
tx_tetra_diffPhaseEncoder_output_1);
TETRA_RX : diffPhaseDecoder port map (rx_clk_18_KHz,
rx_rst,
rx_en,
rx_a_k,
rx_b_k,
rx_i_k,
rx_q_k);
 
end Behavioral;
 

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