OpenCores

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/example_design/FONT_MEM_prod.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/example_design/FONT_MEM_exdes.ucf =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/example_design/FONT_MEM_exdes.ucf (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/example_design/FONT_MEM_exdes.ucf (revision 2) @@ -0,0 +1,57 @@ +################################################################################ +# +# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +################################################################################ + +# Tx Core Period Constraint. This constraint can be modified, and is +# valid as long as it is met after place and route. +NET "CLKA" TNM_NET = "CLKA"; + +TIMESPEC "TS_CLKA" = PERIOD "CLKA" 25 MHZ; + +################################################################################

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/example_design/FONT_MEM_exdes.ucf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/example_design/FONT_MEM_exdes.xdc =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/example_design/FONT_MEM_exdes.xdc (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/example_design/FONT_MEM_exdes.xdc (revision 2) @@ -0,0 +1,54 @@ +################################################################################ +# +# (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +################################################################################ + +# Core Period Constraint. This constraint can be modified, and is +# valid as long as it is met after place and route. +create_clock -name "TS_CLKA" -period 20.0 [ get_ports CLKA ] +################################################################################

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/example_design/FONT_MEM_exdes.xdc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/example_design/FONT_MEM_exdes.vhd =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/example_design/FONT_MEM_exdes.vhd (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/example_design/FONT_MEM_exdes.vhd (revision 2) @@ -0,0 +1,163 @@ + + + + + + + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7.1 Core - Top-level core wrapper +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: FONT_MEM_exdes.vhd +-- +-- Description: +-- This is the actual BMG core wrapper. +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: August 31, 2005 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY UNISIM; +USE UNISIM.VCOMPONENTS.ALL; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +ENTITY FONT_MEM_exdes IS + PORT ( + --Inputs - Port A + + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + + DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + + DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + CLKA : IN STD_LOGIC + + + ); + +END FONT_MEM_exdes; + + +ARCHITECTURE xilinx OF FONT_MEM_exdes IS + + COMPONENT BUFG IS + PORT ( + I : IN STD_ULOGIC; + O : OUT STD_ULOGIC + ); + END COMPONENT; + + COMPONENT FONT_MEM IS + PORT ( + --Port A + + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + + DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + + DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + + CLKA : IN STD_LOGIC + + + + ); + END COMPONENT; + + SIGNAL CLKA_buf : STD_LOGIC; + SIGNAL CLKB_buf : STD_LOGIC; + SIGNAL S_ACLK_buf : STD_LOGIC; + +BEGIN + + bufg_A : BUFG + PORT MAP ( + I => CLKA, + O => CLKA_buf + ); + + + + bmg0 : FONT_MEM + PORT MAP ( + --Port A + + WEA => WEA, + ADDRA => ADDRA, + + DINA => DINA, + + DOUTA => DOUTA, + + CLKA => CLKA_buf + + + ); + +END xilinx;

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/example_design/FONT_MEM_exdes.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/random.vhd =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/random.vhd (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/random.vhd (revision 2) @@ -0,0 +1,112 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_2 Core - Random Number Generator +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: random.vhd +-- +-- Description: +-- Random Generator +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + + + + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + + +ENTITY RANDOM IS + GENERIC ( WIDTH : INTEGER := 32; + SEED : INTEGER :=2 + ); + + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR + ); +END RANDOM; + +ARCHITECTURE BEHAVIORAL OF RANDOM IS +BEGIN + PROCESS(CLK) + VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH); + VARIABLE TEMP : STD_LOGIC := '0'; + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH); + ELSE + IF(EN = '1') THEN + TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2); + RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0); + RAND_TEMP(0) := TEMP; + END IF; + END IF; + END IF; + RANDOM_NUM <= RAND_TEMP; + END PROCESS; +END ARCHITECTURE;

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/random.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/vcs_session.tcl =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/vcs_session.tcl (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/vcs_session.tcl (revision 2) @@ -0,0 +1,82 @@ + + + + + + + + +#-------------------------------------------------------------------------------- +#-- +#-- BMG core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: vcs_session.tcl +# +# Description: +# This is the VCS wave form file. +# +#-------------------------------------------------------------------------------- +if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } { + gui_open_db -design V1 -file bmg_vcs.vpd -nosource +} +gui_set_precision 1ps +gui_set_time_units 1ps + +gui_open_window Wave +gui_sg_create FONT_MEM_Group +gui_list_add_group -id Wave.1 {FONT_MEM_Group} + + gui_sg_addsignal -group FONT_MEM_Group /FONT_MEM_tb/status + gui_sg_addsignal -group FONT_MEM_Group /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/CLKA + gui_sg_addsignal -group FONT_MEM_Group /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/ADDRA + gui_sg_addsignal -group FONT_MEM_Group /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/DINA + gui_sg_addsignal -group FONT_MEM_Group /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/WEA + gui_sg_addsignal -group FONT_MEM_Group /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/DOUTA + +gui_zoom -window Wave.1 -full

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/vcs_session.tcl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simcmds.tcl =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simcmds.tcl (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simcmds.tcl (revision 2) @@ -0,0 +1,62 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + + + + + + +wcfg new +isim set radix hex +wave add /FONT_MEM_tb/status + wave add /FONT_MEM_tb/FONT_MEM_synth_inst/BMG_PORT/CLKA + wave add /FONT_MEM_tb/FONT_MEM_synth_inst/BMG_PORT/ADDRA + wave add /FONT_MEM_tb/FONT_MEM_synth_inst/BMG_PORT/DINA + wave add /FONT_MEM_tb/FONT_MEM_synth_inst/BMG_PORT/WEA + wave add /FONT_MEM_tb/FONT_MEM_synth_inst/BMG_PORT/DOUTA +run all +quit

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simcmds.tcl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simulate_mti.bat =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simulate_mti.bat (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simulate_mti.bat (revision 2) @@ -0,0 +1,3 @@ +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simulate_mti.bat Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/wave_ncsim.sv =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/wave_ncsim.sv (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/wave_ncsim.sv (revision 2) @@ -0,0 +1,20 @@ + + + + + + + + + +window new WaveWindow -name "Waves for BMG Example Design" +waveform using "Waves for BMG Example Design" + + waveform add -signals /FONT_MEM_tb/status + waveform add -signals /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/CLKA + waveform add -signals /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/ADDRA + waveform add -signals /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/DINA + waveform add -signals /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/WEA + waveform add -signals /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/DOUTA + +console submit -using simulator -wait no "run"

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/wave_ncsim.sv Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/ucli_commands.key =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/ucli_commands.key (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/ucli_commands.key (revision 2) @@ -0,0 +1,4 @@ +dump -file bmg_vcs.vpd -type VPD +dump -add FONT_MEM_tb +run +quit

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/ucli_commands.key Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simulate_mti.sh =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simulate_mti.sh (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simulate_mti.sh (revision 2) @@ -0,0 +1,3 @@ +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simulate_mti.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simulate_ncsim.sh =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simulate_ncsim.sh (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simulate_ncsim.sh (revision 2) @@ -0,0 +1,71 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +cp ../../../FONT_MEM.mif . + + +mkdir work +echo "Compiling Core VHDL UNISIM/Behavioral model" +ncvhdl -v93 -work work ../../../FONT_MEM.vhd \ + ../../example_design/FONT_MEM_exdes.vhd + +echo "Compiling Test Bench Files" + +ncvhdl -v93 -work work ../bmg_tb_pkg.vhd +ncvhdl -v93 -work work ../random.vhd +ncvhdl -v93 -work work ../data_gen.vhd +ncvhdl -v93 -work work ../addr_gen.vhd +ncvhdl -v93 -work work ../checker.vhd +ncvhdl -v93 -work work ../bmg_stim_gen.vhd +ncvhdl -v93 -work work ../FONT_MEM_synth.vhd +ncvhdl -v93 -work work ../FONT_MEM_tb.vhd + +echo "Elaborating Design" +ncelab -access +rwc work.FONT_MEM_tb + +echo "Simulating Design" +ncsim -gui -input @"simvision -input wave_ncsim.sv" work.FONT_MEM_tb

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simulate_ncsim.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simulate_vcs.sh =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simulate_vcs.sh (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simulate_vcs.sh (revision 2) @@ -0,0 +1,70 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +#!/bin/sh +cp ../../../FONT_MEM.mif . +rm -rf simv* csrc DVEfiles AN.DB + +echo "Compiling Core VHDL UNISIM/Behavioral model" +vhdlan ../../../FONT_MEM.vhd +vhdlan ../../example_design/FONT_MEM_exdes.vhd + +echo "Compiling Test Bench Files" +vhdlan ../bmg_tb_pkg.vhd +vhdlan ../random.vhd +vhdlan ../data_gen.vhd +vhdlan ../addr_gen.vhd +vhdlan ../checker.vhd +vhdlan ../bmg_stim_gen.vhd +vhdlan ../FONT_MEM_synth.vhd +vhdlan ../FONT_MEM_tb.vhd + +echo "Elaborating Design" +vcs +vcs+lic+wait -debug FONT_MEM_tb + +echo "Simulating Design" +./simv -ucli -i ucli_commands.key +dve -session vcs_session.tcl

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simulate_vcs.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/wave_mti.do =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/wave_mti.do (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/wave_mti.do (revision 2) @@ -0,0 +1,35 @@ + + + + + + + + +onerror {resume} +quietly WaveActivateNextPane {} 0 + + add wave -noupdate /FONT_MEM_tb/status + add wave -noupdate /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/CLKA + add wave -noupdate /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/ADDRA + add wave -noupdate /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/DINA + add wave -noupdate /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/WEA + add wave -noupdate /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/DOUTA + +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +configure wave -namecolwidth 197 +configure wave -valuecolwidth 106 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {9464063 ps}

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/wave_mti.do Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simulate_isim.sh =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simulate_isim.sh (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simulate_isim.sh (revision 2) @@ -0,0 +1,70 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +cp ../../../FONT_MEM.mif . + + +echo "Compiling Core VHDL UNISIM/Behavioral model" +vhpcomp -work work ../../../FONT_MEM.vhd +vhpcomp -work work ../../example_design/FONT_MEM_exdes.vhd + +echo "Compiling Test Bench Files" + +vhpcomp -work work ../bmg_tb_pkg.vhd +vhpcomp -work work ../random.vhd +vhpcomp -work work ../data_gen.vhd +vhpcomp -work work ../addr_gen.vhd +vhpcomp -work work ../checker.vhd +vhpcomp -work work ../bmg_stim_gen.vhd +vhpcomp -work work ../FONT_MEM_synth.vhd +vhpcomp -work work ../FONT_MEM_tb.vhd + +fuse work.FONT_MEM_tb -L unisims -L xilinxcorelib -o FONT_MEM_tb.exe + + +./FONT_MEM_tb.exe -gui -tclbatch simcmds.tcl

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simulate_isim.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simulate_mti.do =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simulate_mti.do (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simulate_mti.do (revision 2) @@ -0,0 +1,75 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +cp ../../../FONT_MEM.mif . + vlib work +vmap work work + +echo "Compiling Core VHDL UNISIM/Behavioral model" +vcom -work work ../../../FONT_MEM.vhd \ + ../../example_design/FONT_MEM_exdes.vhd + +echo "Compiling Test Bench Files" + +vcom -work work ../bmg_tb_pkg.vhd +vcom -work work ../random.vhd +vcom -work work ../data_gen.vhd +vcom -work work ../addr_gen.vhd +vcom -work work ../checker.vhd +vcom -work work ../bmg_stim_gen.vhd +vcom -work work ../FONT_MEM_synth.vhd +vcom -work work ../FONT_MEM_tb.vhd + +vsim -novopt -t ps -L XilinxCoreLib -L unisim work.FONT_MEM_tb + +#Disabled waveform to save the disk space +add log -r /* +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/functional/simulate_mti.do Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/data_gen.vhd =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/data_gen.vhd (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/data_gen.vhd (revision 2) @@ -0,0 +1,140 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_2 Core - Data Generator +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: data_gen.vhd +-- +-- Description: +-- Data Generator +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.BMG_TB_PKG.ALL; + +ENTITY DATA_GEN IS + GENERIC ( DATA_GEN_WIDTH : INTEGER := 32; + DOUT_WIDTH : INTEGER := 32; + DATA_PART_CNT : INTEGER := 1; + SEED : INTEGER := 2 + ); + + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR + ); +END DATA_GEN; + +ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS + CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8); + SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0); + SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0); + SIGNAL LOCAL_CNT : INTEGER :=1; + SIGNAL DATA_GEN_I : STD_LOGIC :='0'; +BEGIN + + LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0); + DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH)); + DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN; + + PROCESS(CLK) + BEGIN + IF(RISING_EDGE (CLK)) THEN + IF(EN ='1' AND (DATA_PART_CNT =1)) THEN + LOCAL_CNT <=1; + ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN + IF(LOCAL_CNT = 1) THEN + LOCAL_CNT <= LOCAL_CNT+1; + ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN + LOCAL_CNT <= LOCAL_CNT+1; + ELSE + LOCAL_CNT <= 1; + END IF; + ELSE + LOCAL_CNT <= 1; + END IF; + END IF; + END PROCESS; + + RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE + RAND_GEN_INST:ENTITY work.RANDOM + GENERIC MAP( + WIDTH => 8, + SEED => (SEED+N) + ) + PORT MAP( + CLK => CLK, + RST => RST, + EN => DATA_GEN_I, + RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N) + ); + END GENERATE RAND_GEN; + +END ARCHITECTURE; +

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/data_gen.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/addr_gen.vhd =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/addr_gen.vhd (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/addr_gen.vhd (revision 2) @@ -0,0 +1,117 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_2 Core - Address Generator +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: addr_gen.vhd +-- +-- Description: +-- Address Generator +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.ALL; + +ENTITY ADDR_GEN IS + GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ; + RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0'); + RST_INC : INTEGER := 0); + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + LOAD :IN STD_LOGIC; + LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0'); + ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR + ); +END ADDR_GEN; + +ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS + SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0'); +BEGIN + ADDR_OUT <= ADDR_TEMP; + PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 ); + ELSE + IF(EN='1') THEN + IF(LOAD='1') THEN + ADDR_TEMP <=LOAD_VALUE; + ELSE + IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN + ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 ); + ELSE + ADDR_TEMP <= ADDR_TEMP + '1'; + END IF; + END IF; + END IF; + END IF; + END IF; + END PROCESS; +END ARCHITECTURE;

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/addr_gen.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/checker.vhd =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/checker.vhd (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/checker.vhd (revision 2) @@ -0,0 +1,161 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_2 Core - Checker +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: checker.vhd +-- +-- Description: +-- Checker +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.BMG_TB_PKG.ALL; + +ENTITY CHECKER IS + GENERIC ( WRITE_WIDTH : INTEGER :=32; + READ_WIDTH : INTEGER :=32 + ); + + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR + STATUS : OUT STD_LOGIC:= '0' + ); +END CHECKER; + +ARCHITECTURE CHECKER_ARCH OF CHECKER IS + SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); + SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); + SIGNAL EN_R : STD_LOGIC := '0'; + SIGNAL EN_2R : STD_LOGIC := '0'; +--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT +--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) +--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) + CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); + CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); + SIGNAL ERR_HOLD : STD_LOGIC :='0'; + SIGNAL ERR_DET : STD_LOGIC :='0'; +BEGIN + PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST= '1') THEN + EN_R <= '0'; + EN_2R <= '0'; + DATA_IN_R <= (OTHERS=>'0'); + ELSE + EN_R <= EN; + EN_2R <= EN_R; + DATA_IN_R <= DATA_IN; + END IF; + END IF; + END PROCESS; + + EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN + GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, + DOUT_WIDTH => READ_WIDTH, + DATA_PART_CNT => DATA_PART_CNT, + SEED => 2 + ) + PORT MAP ( + CLK => CLK, + RST => RST, + EN => EN_2R, + DATA_OUT => EXPECTED_DATA + ); + + PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(EN_2R='1') THEN + IF(EXPECTED_DATA = DATA_IN_R) THEN + ERR_DET<='0'; + ELSE + ERR_DET<= '1'; + END IF; + END IF; + END IF; + END PROCESS; + + PROCESS(CLK,RST) + BEGIN + IF(RST='1') THEN + ERR_HOLD <= '0'; + ELSIF(RISING_EDGE(CLK)) THEN + ERR_HOLD <= ERR_HOLD OR ERR_DET ; + END IF; + END PROCESS; + + STATUS <= ERR_HOLD; + +END ARCHITECTURE; + + +

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/checker.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/vcs_session.tcl =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/vcs_session.tcl (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/vcs_session.tcl (revision 2) @@ -0,0 +1,82 @@ + + + + + + + +#-------------------------------------------------------------------------------- +#-- +#-- BMG Generator v8.4 Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: vcs_session.tcl +# +# Description: +# This is the VCS wave form file. +# +#-------------------------------------------------------------------------------- + +if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } { + gui_open_db -design V1 -file bmg_vcs.vpd -nosource +} +gui_set_precision 1ps +gui_set_time_units 1ps + +gui_open_window Wave +gui_sg_create FONT_MEM_Group +gui_list_add_group -id Wave.1 {FONT_MEM_Group} + + gui_sg_addsignal -group FONT_MEM_Group /FONT_MEM_tb/status + gui_sg_addsignal -group FONT_MEM_Group /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/CLKA + gui_sg_addsignal -group FONT_MEM_Group /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/ADDRA + gui_sg_addsignal -group FONT_MEM_Group /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/DINA + gui_sg_addsignal -group FONT_MEM_Group /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/WEA + gui_sg_addsignal -group FONT_MEM_Group /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/DOUTA + +gui_zoom -window Wave.1 -full

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/vcs_session.tcl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simcmds.tcl =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simcmds.tcl (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simcmds.tcl (revision 2) @@ -0,0 +1,62 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + + + + + + +wcfg new +isim set radix hex +wave add /FONT_MEM_tb/status + wave add /FONT_MEM_tb/FONT_MEM_synth_inst/BMG_PORT/CLKA + wave add /FONT_MEM_tb/FONT_MEM_synth_inst/BMG_PORT/ADDRA + wave add /FONT_MEM_tb/FONT_MEM_synth_inst/BMG_PORT/DINA + wave add /FONT_MEM_tb/FONT_MEM_synth_inst/BMG_PORT/WEA + wave add /FONT_MEM_tb/FONT_MEM_synth_inst/BMG_PORT/DOUTA +run all +quit

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simcmds.tcl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simulate_mti.bat =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simulate_mti.bat (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simulate_mti.bat (revision 2) @@ -0,0 +1,3 @@ +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simulate_mti.bat Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/wave_ncsim.sv =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/wave_ncsim.sv (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/wave_ncsim.sv (revision 2) @@ -0,0 +1,19 @@ + + + + + + + + +window new WaveWindow -name "Waves for BMG Example Design" +waveform using "Waves for BMG Example Design" + + + waveform add -signals /FONT_MEM_tb/status + waveform add -signals /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/CLKA + waveform add -signals /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/ADDRA + waveform add -signals /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/DINA + waveform add -signals /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/WEA + waveform add -signals /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/DOUTA +console submit -using simulator -wait no "run"

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/wave_ncsim.sv Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/ucli_commands.key =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/ucli_commands.key (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/ucli_commands.key (revision 2) @@ -0,0 +1,4 @@ +dump -file bmg_vcs.vpd -type VPD +dump -add FONT_MEM_tb +run +quit

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/ucli_commands.key Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simulate_mti.sh =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simulate_mti.sh (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simulate_mti.sh (revision 2) @@ -0,0 +1,3 @@ +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simulate_mti.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simulate_ncsim.sh =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simulate_ncsim.sh (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simulate_ncsim.sh (revision 2) @@ -0,0 +1,79 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +set work work +#-------------------------------------------------------------------------------- +cp ../../../FONT_MEM.mif . +mkdir work + + +ncvhdl -v93 -work work ../../implement/results/routed.vhd + +echo "Compiling Test Bench Files" + +ncvhdl -v93 -work work ../bmg_tb_pkg.vhd +ncvhdl -v93 -work work ../random.vhd +ncvhdl -v93 -work work ../data_gen.vhd +ncvhdl -v93 -work work ../addr_gen.vhd +ncvhdl -v93 -work work ../checker.vhd +ncvhdl -v93 -work work ../bmg_stim_gen.vhd +ncvhdl -v93 -work work ../FONT_MEM_synth.vhd +ncvhdl -v93 -work work ../FONT_MEM_tb.vhd + +echo "Compiling SDF file" +ncsdfc ../../implement/results/routed.sdf -output ./routed.sdf.X + +echo "Generating SDF command file" +echo 'COMPILED_SDF_FILE = "routed.sdf.X",' > sdf.cmd +echo 'SCOPE = :FONT_MEM_synth_inst:BMG_PORT,' >> sdf.cmd +echo 'MTM_CONTROL = "MAXIMUM";' >> sdf.cmd + + +echo "Elaborating Design" +ncelab -access +rwc -sdf_cmd_file sdf.cmd $work.FONT_MEM_tb + +echo "Simulating Design" +ncsim -gui -input @"simvision -input wave_ncsim.sv" $work.FONT_MEM_tb

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simulate_ncsim.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simulate_vcs.sh =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simulate_vcs.sh (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simulate_vcs.sh (revision 2) @@ -0,0 +1,71 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +#!/bin/sh +cp ../../../FONT_MEM.mif . + +rm -rf simv* csrc DVEfiles AN.DB + +echo "Compiling Core VHDL UNISIM/Behavioral model" +vhdlan ../../implement/results/routed.vhd + +echo "Compiling Test Bench Files" +vhdlan ../bmg_tb_pkg.vhd +vhdlan ../random.vhd +vhdlan ../data_gen.vhd +vhdlan ../addr_gen.vhd +vhdlan ../checker.vhd +vhdlan ../bmg_stim_gen.vhd +vhdlan ../FONT_MEM_synth.vhd +vhdlan ../FONT_MEM_tb.vhd + + +echo "Elaborating Design" +vcs +neg_tchk +vcs+lic+wait -debug FONT_MEM_tb + +echo "Simulating Design" +./simv -ucli -i ucli_commands.key +dve -session vcs_session.tcl

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simulate_vcs.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/wave_mti.do =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/wave_mti.do (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/wave_mti.do (revision 2) @@ -0,0 +1,35 @@ + + + + + + + + +onerror {resume} +quietly WaveActivateNextPane {} 0 + + + add wave -noupdate /FONT_MEM_tb/status + add wave -noupdate /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/CLKA + add wave -noupdate /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/ADDRA + add wave -noupdate /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/DINA + add wave -noupdate /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/WEA + add wave -noupdate /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port/DOUTA +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {9464063 ps}

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/wave_mti.do Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simulate_isim.sh =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simulate_isim.sh (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simulate_isim.sh (revision 2) @@ -0,0 +1,69 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +cp ../../../FONT_MEM.mif . + + +echo "Compiling Core VHDL UNISIM/Behavioral model" +vhpcomp -work work ../../implement/results/routed.vhd + +echo "Compiling Test Bench Files" + +vhpcomp -work work ../bmg_tb_pkg.vhd +vhpcomp -work work ../random.vhd +vhpcomp -work work ../data_gen.vhd +vhpcomp -work work ../addr_gen.vhd +vhpcomp -work work ../checker.vhd +vhpcomp -work work ../bmg_stim_gen.vhd +vhpcomp -work work ../FONT_MEM_synth.vhd +vhpcomp -work work ../FONT_MEM_tb.vhd + + + fuse -L simprim work.FONT_MEM_tb -o FONT_MEM_tb.exe + +./FONT_MEM_tb.exe -sdftyp /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port=../../implement/results/routed.sdf -gui -tclbatch simcmds.tcl

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simulate_isim.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simulate_mti.do =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simulate_mti.do (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simulate_mti.do (revision 2) @@ -0,0 +1,76 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +set work work +#-------------------------------------------------------------------------------- +cp ../../../FONT_MEM.mif . + +vlib work +vmap work work + +echo "Compiling Core VHDL UNISIM/Behavioral model" +vcom -work work ../../implement/results/routed.vhd + +echo "Compiling Test Bench Files" + +vcom -work work ../bmg_tb_pkg.vhd +vcom -work work ../random.vhd +vcom -work work ../data_gen.vhd +vcom -work work ../addr_gen.vhd +vcom -work work ../checker.vhd +vcom -work work ../bmg_stim_gen.vhd +vcom -work work ../FONT_MEM_synth.vhd +vcom -work work ../FONT_MEM_tb.vhd + + vsim -novopt -t ps -L simprim +transport_int_delays -sdftyp /FONT_MEM_tb/FONT_MEM_synth_inst/bmg_port=../../implement/results/routed.sdf $work.FONT_MEM_tb -novopt + +#Disabled waveform to save the disk space +add log -r /* +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/timing/simulate_mti.do Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/FONT_MEM_synth.vhd =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/FONT_MEM_synth.vhd (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/FONT_MEM_synth.vhd (revision 2) @@ -0,0 +1,287 @@ + + + + + + + + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_2 Core - Synthesizable Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: FONT_MEM_synth.vhd +-- +-- Description: +-- Synthesizable Testbench +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE IEEE.STD_LOGIC_MISC.ALL; + +LIBRARY STD; +USE STD.TEXTIO.ALL; + +--LIBRARY unisim; +--USE unisim.vcomponents.ALL; + +LIBRARY work; +USE work.ALL; +USE work.BMG_TB_PKG.ALL; + +ENTITY FONT_MEM_synth IS +PORT( + CLK_IN : IN STD_LOGIC; + RESET_IN : IN STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA + ); +END ENTITY; + +ARCHITECTURE FONT_MEM_synth_ARCH OF FONT_MEM_synth IS + + +COMPONENT FONT_MEM_exdes + PORT ( + --Inputs - Port A + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + CLKA : IN STD_LOGIC + + + ); + +END COMPONENT; + + + SIGNAL CLKA: STD_LOGIC := '0'; + SIGNAL RSTA: STD_LOGIC := '0'; + SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); + SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ADDRA: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ADDRA_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DOUTA: STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL CHECKER_EN : STD_LOGIC:='0'; + SIGNAL CHECKER_EN_R : STD_LOGIC:='0'; + SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0'); + SIGNAL clk_in_i: STD_LOGIC; + + SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1'; + SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1'; + SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1'; + + SIGNAL ITER_R0 : STD_LOGIC := '0'; + SIGNAL ITER_R1 : STD_LOGIC := '0'; + SIGNAL ITER_R2 : STD_LOGIC := '0'; + + SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + + BEGIN + +-- clk_buf: bufg +-- PORT map( +-- i => CLK_IN, +-- o => clk_in_i +-- ); + clk_in_i <= CLK_IN; + CLKA <= clk_in_i; + + RSTA <= RESET_SYNC_R3 AFTER 50 ns; + + + PROCESS(clk_in_i) + BEGIN + IF(RISING_EDGE(clk_in_i)) THEN + RESET_SYNC_R1 <= RESET_IN; + RESET_SYNC_R2 <= RESET_SYNC_R1; + RESET_SYNC_R3 <= RESET_SYNC_R2; + END IF; + END PROCESS; + + +PROCESS(CLKA) +BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + ISSUE_FLAG_STATUS<= (OTHERS => '0'); + ELSE + ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG; + END IF; + END IF; +END PROCESS; + +STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS; + + + + BMG_DATA_CHECKER_INST: ENTITY work.CHECKER + GENERIC MAP ( + WRITE_WIDTH => 8, + READ_WIDTH => 8 ) + PORT MAP ( + CLK => CLKA, + RST => RSTA, + EN => CHECKER_EN_R, + DATA_IN => DOUTA, + STATUS => ISSUE_FLAG(0) + ); + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RSTA='1') THEN + CHECKER_EN_R <= '0'; + ELSE + CHECKER_EN_R <= CHECKER_EN AFTER 50 ns; + END IF; + END IF; + END PROCESS; + + + BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN + PORT MAP( + CLK => clk_in_i, + RST => RSTA, + ADDRA => ADDRA, + DINA => DINA, + WEA => WEA, + CHECK_DATA => CHECKER_EN + ); + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + STATUS(8) <= '0'; + iter_r2 <= '0'; + iter_r1 <= '0'; + iter_r0 <= '0'; + ELSE + STATUS(8) <= iter_r2; + iter_r2 <= iter_r1; + iter_r1 <= iter_r0; + iter_r0 <= STIMULUS_FLOW(8); + END IF; + END IF; + END PROCESS; + + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + STIMULUS_FLOW <= (OTHERS => '0'); + ELSIF(WEA(0)='1') THEN + STIMULUS_FLOW <= STIMULUS_FLOW+1; + END IF; + END IF; + END PROCESS; + + + + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + WEA_R <= (OTHERS=>'0') AFTER 50 ns; + DINA_R <= (OTHERS=>'0') AFTER 50 ns; + + + ELSE + WEA_R <= WEA AFTER 50 ns; + DINA_R <= DINA AFTER 50 ns; + + END IF; + END IF; + END PROCESS; + + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + ADDRA_R <= (OTHERS=> '0') AFTER 50 ns; + ELSE + ADDRA_R <= ADDRA AFTER 50 ns; + END IF; + END IF; + END PROCESS; + + + BMG_PORT: FONT_MEM_exdes PORT MAP ( + --Port A + WEA => WEA_R, + ADDRA => ADDRA_R, + DINA => DINA_R, + DOUTA => DOUTA, + CLKA => CLKA + + ); +END ARCHITECTURE;

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/FONT_MEM_synth.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/FONT_MEM_tb.vhd =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/FONT_MEM_tb.vhd (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/FONT_MEM_tb.vhd (revision 2) @@ -0,0 +1,129 @@ +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_2 Core - Top File for the Example Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- Filename: FONT_MEM_tb.vhd +-- Description: +-- Testbench Top +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.ALL; + +ENTITY FONT_MEM_tb IS +END ENTITY; + + +ARCHITECTURE FONT_MEM_tb_ARCH OF FONT_MEM_tb IS + SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL CLK : STD_LOGIC := '1'; + SIGNAL RESET : STD_LOGIC; + + BEGIN + + + CLK_GEN: PROCESS BEGIN + CLK <= NOT CLK; + WAIT FOR 100 NS; + CLK <= NOT CLK; + WAIT FOR 100 NS; + END PROCESS; + + RST_GEN: PROCESS BEGIN + RESET <= '1'; + WAIT FOR 1000 NS; + RESET <= '0'; + WAIT; + END PROCESS; + + +--STOP_SIM: PROCESS BEGIN +-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS +-- ASSERT FALSE +-- REPORT "END SIMULATION TIME REACHED" +-- SEVERITY FAILURE; +--END PROCESS; +-- +PROCESS BEGIN + WAIT UNTIL STATUS(8)='1'; + IF( STATUS(7 downto 0)/="0") THEN + ASSERT false + REPORT "Simulation Failed" + SEVERITY FAILURE; + ELSE + ASSERT false + REPORT "Test Completed Successfully" + SEVERITY FAILURE; + END IF; +END PROCESS; + + FONT_MEM_synth_inst:ENTITY work.FONT_MEM_synth + PORT MAP( + CLK_IN => CLK, + RESET_IN => RESET, + STATUS => STATUS + ); + +END ARCHITECTURE;

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/FONT_MEM_tb.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/bmg_stim_gen.vhd =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/bmg_stim_gen.vhd (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/bmg_stim_gen.vhd (revision 2) @@ -0,0 +1,243 @@ + + + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_2 Core - Stimulus Generator For Single Port Ram +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: bmg_stim_gen.vhd +-- +-- Description: +-- Stimulus Generation For SRAM +-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the +-- simulation ends +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_MISC.ALL; + +LIBRARY work; +USE work.ALL; + +USE work.BMG_TB_PKG.ALL; + + +ENTITY REGISTER_LOGIC_SRAM IS + PORT( + Q : OUT STD_LOGIC; + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + D : IN STD_LOGIC + ); +END REGISTER_LOGIC_SRAM; + +ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS + SIGNAL Q_O : STD_LOGIC :='0'; +BEGIN + Q <= Q_O; + FF_BEH: PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST ='1') THEN + Q_O <= '0'; + ELSE + Q_O <= D; + END IF; + END IF; + END PROCESS; +END REGISTER_ARCH; + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_MISC.ALL; + +LIBRARY work; +USE work.ALL; +USE work.BMG_TB_PKG.ALL; + + +ENTITY BMG_STIM_GEN IS + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + ADDRA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0'); + DINA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0'); + CHECK_DATA: OUT STD_LOGIC:='0' + ); +END BMG_STIM_GEN; + + +ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS + + CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(8,8); + SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0'); + SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0'); + SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DINA_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DO_WRITE : STD_LOGIC := '0'; + SIGNAL DO_READ : STD_LOGIC := '0'; + SIGNAL COUNT_NO : INTEGER :=0; + SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0'); +BEGIN + WRITE_ADDR_INT(11 DOWNTO 0) <= WRITE_ADDR(11 DOWNTO 0); + READ_ADDR_INT(11 DOWNTO 0) <= READ_ADDR(11 DOWNTO 0); + ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ; + DINA <= DINA_INT ; + + CHECK_DATA <= DO_READ; + +RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN + GENERIC MAP( + C_MAX_DEPTH => 4096 + ) + PORT MAP( + CLK => CLK, + RST => RST, + EN => DO_READ, + LOAD => '0', + LOAD_VALUE => ZERO, + ADDR_OUT => READ_ADDR + ); + +WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN + GENERIC MAP( + C_MAX_DEPTH => 4096 ) + PORT MAP( + CLK => CLK, + RST => RST, + EN => DO_WRITE, + LOAD => '0', + LOAD_VALUE => ZERO, + ADDR_OUT => WRITE_ADDR + ); + +WR_DATA_GEN_INST:ENTITY work.DATA_GEN + GENERIC MAP ( + DATA_GEN_WIDTH => 8, + DOUT_WIDTH => 8, + DATA_PART_CNT => DATA_PART_CNT_A, + SEED => 2 + ) + PORT MAP ( + CLK => CLK, + RST => RST, + EN => DO_WRITE, + DATA_OUT => DINA_INT + ); + +WR_RD_PROCESS: PROCESS (CLK) +BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + DO_WRITE <= '0'; + DO_READ <= '0'; + COUNT_NO <= 0 ; + ELSIF(COUNT_NO < 4) THEN + DO_WRITE <= '1'; + DO_READ <= '0'; + COUNT_NO <= COUNT_NO + 1; + ELSIF(COUNT_NO< 8) THEN + DO_WRITE <= '0'; + DO_READ <= '1'; + COUNT_NO <= COUNT_NO + 1; + ELSIF(COUNT_NO=8) THEN + DO_WRITE <= '0'; + DO_READ <= '0'; + COUNT_NO <= 0 ; + END IF; + END IF; +END PROCESS; + +BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE +BEGIN + DFF_RIGHT: IF I=0 GENERATE + BEGIN + SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM + PORT MAP( + Q => DO_READ_REG(0), + CLK => CLK, + RST => RST, + D => DO_READ + ); + END GENERATE DFF_RIGHT; + DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE + BEGIN + SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM + PORT MAP( + Q => DO_READ_REG(I), + CLK => CLK, + RST => RST, + D => DO_READ_REG(I-1) + ); + END GENERATE DFF_OTHERS; +END GENERATE BEGIN_SHIFT_REG; + + WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ; + +END ARCHITECTURE;

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/bmg_stim_gen.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/bmg_tb_pkg.vhd =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/bmg_tb_pkg.vhd (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/bmg_tb_pkg.vhd (revision 2) @@ -0,0 +1,200 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_2 Core - Testbench Package +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: bmg_tb_pkg.vhd +-- +-- Description: +-- BMG Testbench Package files +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +PACKAGE BMG_TB_PKG IS + + FUNCTION DIVROUNDUP ( + DATA_VALUE : INTEGER; + DIVISOR : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC_VECTOR; + FALSE_CASE : STD_LOGIC_VECTOR) + RETURN STD_LOGIC_VECTOR; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STRING; + FALSE_CASE :STRING) + RETURN STRING; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC; + FALSE_CASE :STD_LOGIC) + RETURN STD_LOGIC; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : INTEGER; + FALSE_CASE : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION LOG2ROUNDUP ( + DATA_VALUE : INTEGER) + RETURN INTEGER; + +END BMG_TB_PKG; + +PACKAGE BODY BMG_TB_PKG IS + + FUNCTION DIVROUNDUP ( + DATA_VALUE : INTEGER; + DIVISOR : INTEGER) + RETURN INTEGER IS + VARIABLE DIV : INTEGER; + BEGIN + DIV := DATA_VALUE/DIVISOR; + IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN + DIV := DIV+1; + END IF; + RETURN DIV; + END DIVROUNDUP; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC_VECTOR; + FALSE_CASE : STD_LOGIC_VECTOR) + RETURN STD_LOGIC_VECTOR IS + BEGIN + IF NOT CONDITION THEN + RETURN FALSE_CASE; + ELSE + RETURN TRUE_CASE; + END IF; + END IF_THEN_ELSE; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC; + FALSE_CASE : STD_LOGIC) + RETURN STD_LOGIC IS + BEGIN + IF NOT CONDITION THEN + RETURN FALSE_CASE; + ELSE + RETURN TRUE_CASE; + END IF; + END IF_THEN_ELSE; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : INTEGER; + FALSE_CASE : INTEGER) + RETURN INTEGER IS + VARIABLE RETVAL : INTEGER := 0; + BEGIN + IF CONDITION=FALSE THEN + RETVAL:=FALSE_CASE; + ELSE + RETVAL:=TRUE_CASE; + END IF; + RETURN RETVAL; + END IF_THEN_ELSE; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STRING; + FALSE_CASE : STRING) + RETURN STRING IS + BEGIN + IF NOT CONDITION THEN + RETURN FALSE_CASE; + ELSE + RETURN TRUE_CASE; + END IF; + END IF_THEN_ELSE; + ------------------------------- + FUNCTION LOG2ROUNDUP ( + DATA_VALUE : INTEGER) + RETURN INTEGER IS + VARIABLE WIDTH : INTEGER := 0; + VARIABLE CNT : INTEGER := 1; + BEGIN + IF (DATA_VALUE <= 1) THEN + WIDTH := 1; + ELSE + WHILE (CNT < DATA_VALUE) LOOP + WIDTH := WIDTH + 1; + CNT := CNT *2; + END LOOP; + END IF; + RETURN WIDTH; + END LOG2ROUNDUP; + +END BMG_TB_PKG;

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/simulation/bmg_tb_pkg.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/doc/blk_mem_gen_v7_2_vinfo.html =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/doc/blk_mem_gen_v7_2_vinfo.html (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/doc/blk_mem_gen_v7_2_vinfo.html (revision 2) @@ -0,0 +1,237 @@ + + +blk_mem_gen_v7_2_vinfo + + + +










    +CHANGE LOG for LogiCORE Block Memory Generator V7.2








    +








    +                Core name: Xilinx LogiCORE Block Memory Generator








    +                Version: 7.2








    +                Release: ISE 14.2 / Vivado 2012.2








    +                Release Date: July 25, 2012








    +








    +--------------------------------------------------------------------------------








    +








    +Table of Contents








    +








    +1. INTRODUCTION








    +2. DEVICE SUPPORT








    +3. NEW FEATURES HISTORY








    +4. RESOLVED ISSUES








    +5. KNOWN ISSUES & LIMITATIONS








    +6. TECHNICAL SUPPORT & FEEDBACK








    +7. CORE RELEASE HISTORY








    +8. LEGAL DISCLAIMER








    +








    +--------------------------------------------------------------------------------








    +








    +








    +1. INTRODUCTION








    +








    +For installation instructions for this release, please go to:








    +








    +  www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm








    +








    +For system requirements:








    +








    +   www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm








    +








    +This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.2








    +solution. For the latest core updates, see the product page at:








    +








    + www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm








    +








    +








    +................................................................................








    +








    +








    +2. DEVICE SUPPORT








    +








    +








    +  2.1 ISE








    +








    +  The following device families are supported by the core for this release.








    +








    +  All 7 Series devices








    +  Zynq-7000 devices








    +  All Virtex-6 devices








    +  All Spartan-6 devices








    +  All Virtex-5 devices








    +  All Spartan-3 devices








    +  All Virtex-4 devices








    +








    +








    +  2.2 Vivado








    +  All 7 Series devices








    +  Zynq-7000 devices








    +








    +................................................................................








    +








    +3. NEW FEATURES HISTORY








    +








    +








    +  3.1 ISE








    +








    +    - ISE 14.2 software support








    +








    +








    +  3.2 Vivado








    +








    +    - 2012.2 software support








    +








    +








    +................................................................................








    +








    +








    +4. RESOLVED ISSUES








    +








    +








    +The following issues are resolved in Block Memory Generator v7.2:








    +








    +  4.1 ISE








    +








    +








    +  4.2 Vivado








    +








    +








    +................................................................................








    +








    +








    +5. KNOWN ISSUES & LIMITATIONS








    +








    +








    +  5.1 ISE








    +








    +    The following are known issues for v7.2 of this core at time of release:








    +








    +    1. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First)








    +      Work around: The user must review the possible scenarios that causes the collission and revise








    +       their design to avoid those situations.








    +      - CR588505








    +








    +      Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with








    +            Write Mode = Read First in conjunction with asynchronous clocking








    +








    +    2. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.








    +








    +    3. Core does not generate for large memories. Depending on the








    +       machine the ISE CORE Generator software runs on, the maximum size of the memory that








    +       can be generated will vary.  For example, a Dual Pentium-4 server








    +       with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes








    +      - CR 415768








    +      - AR 24034








    +








    +








    +  5.2 Vivado








    +








    +    The following are known issues for v7.2 of this core at time of release:








    +








    +    1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen








    +       ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.








    +








    +       CR 665836








    +








    +  The most recent information, including known issues, workarounds, and resolutions for








    +  this version is provided in the IP Release Notes User Guide located at








    +








    +         www.xilinx.com/support/documentation/user_guides/xtp025.pdf








    +








    +................................................................................








    +








    +








    +6. TECHNICAL SUPPORT & FEEDBACK








    +








    +To obtain technical support, create a WebCase at www.xilinx.com/support.








    +Questions are routed to a team with expertise using this product.








    +








    +Xilinx provides technical support for use of this product when used








    +according to the guidelines described in the core documentation, and








    +cannot guarantee timing, functionality, or support of this product for








    +designs that do not follow specified guidelines.








    +








    +








    +








    +7. CORE RELEASE HISTORY








    +








    +Date        By            Version      Description








    +================================================================================








    +07/25/2012  Xilinx, Inc.  7.2          ISE 14.2 and Vivado 2012.2 support;








    +04/24/2012  Xilinx, Inc.  7.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support








    +01/18/2011  Xilinx, Inc.  6.3          ISE 13.4 support;Artix7L*, AArtix-7* device support








    +06/22/2011  Xilinx, Inc.  6.2          ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;








    +03/01/2011  Xilinx, Inc.  6.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support








    +09/21/2010  Xilinx, Inc.  4.3          ISE 12.3 support








    +07/23/2010  Xilinx, Inc.  4.2          ISE 12.2 support








    +04/19/2010  Xilinx, Inc.  4.1          ISE 12.1 support








    +03/09/2010  Xilinx, Inc.  3.3 rev 2    Fix for V6 Memory collision issue








    +12/02/2009  Xilinx, Inc.  3.3 rev 1    ISE 11.4 support; Spartan-6 Low Power








    +                                       Device support; Automotive Spartan 3A








    +                                       DSP device support








    +09/16/2009  Xilinx, Inc.  3.3          Revised to v3.3








    +06/24/2009  Xilinx, Inc.  3.2          Revised to v3.2








    +04/24/2009  Xilinx, Inc.  3.1          Revised to v3.1








    +09/19/2008  Xilinx, Inc.  2.8          Revised to v2.8








    +03/24/2008  Xilinx, Inc.  2.7          10.1 support; Revised to v2.7








    +10/03/2007  Xilinx, Inc.  2.6          Revised to v2.6








    +07/2007     Xilinx, Inc.  2.5          Revised to v2.5








    +04/2007     Xilinx, Inc.  2.4          Revised to v2.4 rev 1








    +02/2007     Xilinx, Inc.  2.4          Revised to v2.4








    +11/2006     Xilinx, Inc.  2.3          Revised to v2.3








    +09/2006     Xilinx, Inc.  2.2          Revised to v2.2








    +06/2006     Xilinx, Inc.  2.1          Revised to v2.1








    +01/2006     Xilinx, Inc.  1.1          Initial release








    +================================================================================








    +








    +8. Legal Disclaimer








    +








    +(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.








    +








    +  This file contains confidential and proprietary information








    +  of Xilinx, Inc. and is protected under U.S. and








    +  international copyright and other intellectual property








    +  laws.








    +








    +  DISCLAIMER








    +  This disclaimer is not a license and does not grant any








    +  rights to the materials distributed herewith. Except as








    +  otherwise provided in a valid license issued to you by








    +  Xilinx, and to the maximum extent permitted by applicable








    +  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND








    +  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES








    +  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING








    +  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-








    +  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and








    +  (2) Xilinx shall not be liable (whether in contract or tort,








    +  including negligence, or under any other theory of








    +  liability) for any loss or damage of any kind or nature








    +  related to, arising under or in connection with these








    +  materials, including for any direct, or any indirect,








    +  special, incidental, or consequential loss or damage








    +  (including loss of data, profits, goodwill, or any type of








    +  loss or damage suffered as a result of any action brought








    +  by a third party) even if such damage or loss was








    +  reasonably foreseeable or Xilinx had been advised of the








    +  possibility of the same.








    +








    +  CRITICAL APPLICATIONS








    +  Xilinx products are not designed or intended to be fail-








    +  safe, or for use in any application requiring fail-safe








    +  performance, such as life-support or safety devices or








    +  systems, Class III medical devices, nuclear facilities,








    +  applications related to the deployment of airbags, or any








    +  other applications that could lead to death, personal








    +  injury, or severe property or environmental damage








    +  (individually and collectively, "Critical








    +  Applications"). Customer assumes the sole risk and








    +  liability of any use of Xilinx products in Critical








    +  Applications, subject only to applicable laws and








    +  regulations governing limitations on product liability.








    +








    +  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS








    +  PART OF THIS FILE AT ALL TIMES.








    +








    +

+ + Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/doc/pg058-blk-mem-gen.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/doc/pg058-blk-mem-gen.pdf =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/doc/pg058-blk-mem-gen.pdf (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/doc/pg058-blk-mem-gen.pdf (revision 2)

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/doc/pg058-blk-mem-gen.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/blk_mem_gen_v7_2_readme.txt =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/blk_mem_gen_v7_2_readme.txt (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/blk_mem_gen_v7_2_readme.txt (revision 2) @@ -0,0 +1,226 @@ +CHANGE LOG for LogiCORE Block Memory Generator V7.2 + + Core name: Xilinx LogiCORE Block Memory Generator + Version: 7.2 + Release: ISE 14.2 / Vivado 2012.2 + Release Date: July 25, 2012 + +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURES HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.2 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm + + +................................................................................ + + +2. DEVICE SUPPORT + + + 2.1 ISE + + The following device families are supported by the core for this release. + + All 7 Series devices + Zynq-7000 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Spartan-3 devices + All Virtex-4 devices + + + 2.2 Vivado + All 7 Series devices + Zynq-7000 devices + +................................................................................ + +3. NEW FEATURES HISTORY + + + 3.1 ISE + + - ISE 14.2 software support + + + 3.2 Vivado + + - 2012.2 software support + + +................................................................................ + + +4. RESOLVED ISSUES + + +The following issues are resolved in Block Memory Generator v7.2: + + 4.1 ISE + + + 4.2 Vivado + + +................................................................................ + + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + The following are known issues for v7.2 of this core at time of release: + + 1. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First) + Work around: The user must review the possible scenarios that causes the collission and revise + their design to avoid those situations. + - CR588505 + + Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with + Write Mode = Read First in conjunction with asynchronous clocking + + 2. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3. + + 3. Core does not generate for large memories. Depending on the + machine the ISE CORE Generator software runs on, the maximum size of the memory that + can be generated will vary. For example, a Dual Pentium-4 server + with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes + - CR 415768 + - AR 24034 + + + 5.2 Vivado + + The following are known issues for v7.2 of this core at time of release: + + 1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen + ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work. + + CR 665836 + + The most recent information, including known issues, workarounds, and resolutions for + this version is provided in the IP Release Notes User Guide located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + +................................................................................ + + +6. TECHNICAL SUPPORT & FEEDBACK + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +07/25/2012 Xilinx, Inc. 7.2 ISE 14.2 and Vivado 2012.2 support; +04/24/2012 Xilinx, Inc. 7.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support +01/18/2011 Xilinx, Inc. 6.3 ISE 13.4 support;Artix7L*, AArtix-7* device support +06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support; +03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support +09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support +07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support +04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support +03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue +12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power + Device support; Automotive Spartan 3A + DSP device support +09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3 +06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2 +04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1 +09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8 +03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7 +10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6 +07/2007 Xilinx, Inc. 2.5 Revised to v2.5 +04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1 +02/2007 Xilinx, Inc. 2.4 Revised to v2.4 +11/2006 Xilinx, Inc. 2.3 Revised to v2.3 +09/2006 Xilinx, Inc. 2.2 Revised to v2.2 +06/2006 Xilinx, Inc. 2.1 Revised to v2.1 +01/2006 Xilinx, Inc. 1.1 Initial release +================================================================================ + +8. Legal Disclaimer + +(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/implement.bat =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/implement.bat (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/implement.bat (revision 2) @@ -0,0 +1,48 @@ + + + + + + + + +rem Clean up the results directory +rmdir /S /Q results +mkdir results + +rem Synthesize the VHDL Wrapper Files + + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +copy FONT_MEM_exdes.ngc .\results\ + + +rem Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +copy ..\..\FONT_MEM.ngc results\ + + +rem Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\FONT_MEM_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' +ngdbuild -p xc3s500e-fg320-4 FONT_MEM_exdes + +echo 'Running map' +map FONT_MEM_exdes -o mapped.ncd -pr i + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level VHDL model' +netgen -ofmt vhdl -sim -tm FONT_MEM_exdes -pcf mapped.pcf -w routed.ncd routed.vhd

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/implement.bat Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/planAhead_ise.bat =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/planAhead_ise.bat (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/planAhead_ise.bat (revision 2) @@ -0,0 +1,55 @@ +#!/bin/sh +rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +rem +rem This file contains confidential and proprietary information +rem of Xilinx, Inc. and is protected under U.S. and +rem international copyright and other intellectual property +rem laws. +rem +rem DISCLAIMER +rem This disclaimer is not a license and does not grant any +rem rights to the materials distributed herewith. Except as +rem otherwise provided in a valid license issued to you by +rem Xilinx, and to the maximum extent permitted by applicable +rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +rem (2) Xilinx shall not be liable (whether in contract or tort, +rem including negligence, or under any other theory of +rem liability) for any loss or damage of any kind or nature +rem related to, arising under or in connection with these +rem materials, including for any direct, or any indirect, +rem special, incidental, or consequential loss or damage +rem (including loss of data, profits, goodwill, or any type of +rem loss or damage suffered as a result of any action brought +rem by a third party) even if such damage or loss was +rem reasonably foreseeable or Xilinx had been advised of the +rem possibility of the same. +rem +rem CRITICAL APPLICATIONS +rem Xilinx products are not designed or intended to be fail- +rem safe, or for use in any application requiring fail-safe +rem performance, such as life-support or safety devices or +rem systems, Class III medical devices, nuclear facilities, +rem applications related to the deployment of airbags, or any +rem other applications that could lead to death, personal +rem injury, or severe property or environmental damage +rem (individually and collectively, "Critical +rem Applications"). Customer assumes the sole risk and +rem liability of any use of Xilinx products in Critical +rem Applications, subject only to applicable laws and +rem regulations governing limitations on product liability. +rem +rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +rem PART OF THIS FILE AT ALL TIMES. + +rem ----------------------------------------------------------------------------- +rem Script to synthesize and implement the Coregen FIFO Generator +rem ----------------------------------------------------------------------------- +rmdir /S /Q results +mkdir results +cd results +copy ..\..\..\FONT_MEM.ngc . +planAhead -mode batch -source ..\planAhead_ise.tcl

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/planAhead_ise.bat Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/implement.sh =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/implement.sh (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/implement.sh (revision 2) @@ -0,0 +1,48 @@ + + + + + + + + +#!/bin/sh + +# Clean up the results directory +rm -rf results +mkdir results + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +cp FONT_MEM_exdes.ngc ./results/ + + +# Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +cp ../../FONT_MEM.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/FONT_MEM_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' +ngdbuild -p xc3s500e-fg320-4 FONT_MEM_exdes + +echo 'Running map' +map FONT_MEM_exdes -o mapped.ncd -pr i + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level VHDL model' +netgen -ofmt vhdl -sim -tm FONT_MEM_exdes -pcf mapped.pcf -w routed.ncd routed.vhd

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/implement.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/xst.scr =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/xst.scr (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/xst.scr (revision 2) @@ -0,0 +1,13 @@ +run +-ifmt VHDL +-ent FONT_MEM_exdes +-p xc3s500e-fg320-4 +-ifn xst.prj +-write_timing_constraints No +-iobuf YES +-max_fanout 100 +-ofn FONT_MEM_exdes +-ofmt NGC +-bus_delimiter () +-hierarchy_separator / +-case Maintain

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/xst.scr Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/planAhead_ise.sh =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/planAhead_ise.sh (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/planAhead_ise.sh (revision 2) @@ -0,0 +1,55 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the Coregen FIFO Generator +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +cp ../../../FONT_MEM.ngc . +planAhead -mode batch -source ../planAhead_ise.tcl

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/planAhead_ise.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/xst.prj =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/xst.prj (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/xst.prj (revision 2) @@ -0,0 +1 @@ +work ../example_design/FONT_MEM_exdes.vhd

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/xst.prj Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/planAhead_ise.tcl =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/planAhead_ise.tcl (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/planAhead_ise.tcl (revision 2) @@ -0,0 +1,67 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + +set device xc3s500efg320-4 +set projName FONT_MEM +set design FONT_MEM +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module FONT_MEM_exdes +add_files -norecurse {../../example_design/FONT_MEM_exdes.vhd} +add_files -norecurse {./FONT_MEM.ngc} +import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/FONT_MEM_exdes.xdc} +set_property top FONT_MEM_exdes [get_property srcset [current_run]] +synth_design +opt_design +place_design +route_design +write_sdf -rename_top_module FONT_MEM_exdes -file routed.sdf +write_vhdl -mode sim routed.vhd +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file report.drc +write_bitstream -bitgen_options {-g UnconstrainedPins:Allow}

fat_32_file_parser/trunk/ipcore_dir/FONT_MEM/implement/planAhead_ise.tcl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM_synth.vhd =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM_synth.vhd (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM_synth.vhd (revision 2) @@ -0,0 +1,81 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used solely -- +-- for design, simulation, implementation and creation of design files -- +-- limited to Xilinx devices or technologies. Use with non-Xilinx -- +-- devices or technologies is expressly prohibited and immediately -- +-- terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- +-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- +-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- +-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- +-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- +-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- +-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- +-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- +-- PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support appliances, -- +-- devices, or systems. Use in such applications are expressly -- +-- prohibited. -- +-- -- +-- (c) Copyright 1995-2014 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- +-- Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.2 -- +-- -- +-- The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port -- +-- Block Memory and Single Port Block Memory LogiCOREs, but is not a -- +-- direct drop-in replacement. It should be used in all new Xilinx -- +-- designs. The core supports RAM and ROM functions over a wide range of -- +-- widths and depths. Use this core to generate block memories with -- +-- symmetric or asymmetric read and write port widths, as well as cores -- +-- which can perform simultaneous write operations to separate -- +-- locations, and simultaneous read operations from the same location. -- +-- For more information on differences in interface and feature support -- +-- between this core and the Dual Port Block Memory and Single Port -- +-- Block Memory LogiCOREs, please consult the data sheet. -- +-------------------------------------------------------------------------------- +-- Synthesized Netlist Wrapper +-- This file is provided to wrap around the synthesized netlist (if appropriate) + +-- Interfaces: +-- CLK.ACLK +-- AXI4 Interconnect Clock Input +-- RST.ARESETN +-- AXI4 Interconnect Reset Input +-- AXI_SLAVE_S_AXI +-- AXI_SLAVE +-- AXILite_SLAVE_S_AXI +-- AXILite_SLAVE +-- BRAM_PORTA +-- BRAM_PORTA +-- BRAM_PORTB +-- BRAM_PORTB + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +ENTITY FONT_MEM IS + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END FONT_MEM; + +ARCHITECTURE spartan3e OF FONT_MEM IS +BEGIN + + -- WARNING: This file provides an entity declaration with empty architecture, it + -- does not support direct instantiation. Please use an instantiation + -- template (VHO) to instantiate the IP within a design. + +END spartan3e; Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM.ngc =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM.ngc (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM.ngc (revision 2) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$07g44<,[o}e~g`n;"2*73>(-80!?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?012305=789:;<=>?012345678OLMJKHIFGDEB56789:MJKHIFGDEBC@EMKOIIOKMECGB1D3382:;<=>?01234C67?1KJNLOM86234567?9:;<=>?0123356789:;<==9D713456789>;7=>?01234567N9:N=8;654;2A56789:N<=>?0123230B89:;<=>?07A;G36789:;<9>40123456789=H<=9LCB53451DKJ=HON9?011076568JL;<=9LCBD@GF1789=H<=HL4193456789=;;=?<61234517?:;;<=>?01237542=12;??<=21::EF>789:;<=>?01274>6789:;=>=<3G107567?J;?0123B301>M:;<=??06A@G26789L=::896E23452739:;<=>8CBA@356689:?<=;;8J0124@F17?9:;<=>?012345769=:0<=>?01:@25678923<=>?0123456789O;<=>?09A@G56789:;<=>?89G;<56789:;8=5?01234F0789I;<=>?0B4@43E789:;<=>?07A3456BKJIHON8?012345E1>?I;<=>;0:234567M?83O;K?8B2345670J2H4=>?0123G5>D09:;I=67E9:3456789:;<=6L8163?56789:NONMLCBA@456D>9:=O=>?012@2301K9:;<=>9CBA@<56789:;<=>?0B:@G16<89:;<=HL622@B55189:;<==91713456789=8=;=?0153541699:;<=>?01237357<91;<=89675@456789:8:K8<01234565>O<9<=>?00145470;8:;<=><6G40456789:?<6>?0B40556789:;=<>?0123456789:;J=>?0122456789:;<=>?0132347789:;<=:?;123GFEBK9:;<=>?012F230189:;<5MJC923456?KL234HM70123456B89:;<=>?0528457789:;<==>1030447789O=:;9967G33F60KJI<<=>?015076@4;:;;<=9LCGA405=788;;=<>LC623435689::?;>?0123B5@789:;<=?<6B40556799:;<=>?0123456382:;?10132367;8;:=<=?62237476989;?<>?3032545788:;J;8867D32367N?>;7=><1032750189:8=3140556498;:?==>01205476;9;8:=>8CBD@350189:401125601>9<=<=>?01234A1789=:=<>>1053457698;:=?9;<=>?061036678O<8=5H?3723456798:;<=>?003252BCL>:HOKMLCBA74>67?99=:>>?79;BEDG>0>:;;N?8C620251DK9=HO:8LC6233F60KJ=;?;>?1012342739:?<=H=>?012@GABA>9:;<=>>3210765089:N:;99674F42ED8=:0<=9LCBA@GF1789IHOIHJEBA345EDLMNMINM?01D52301>?L;<=MLCEDE@FE789=O8=5?09:3<=E1>J:;<=>7C7A;456789:;I=K?01234F>789:;4N>?8BA@45ED89:;<=M;0:23G5>DK1:;<=>?81234567M;:3OH>7C123456?09:;<=>?BC@AFGDEN9:;:NMLCB63?56D>?<=:;8L0125A@C1>?<=<=>96745A@0189:N:?>?01234561>J2;<5M90123<16<89I=:;8L01234501>??014523CD89:;<=6;0123456789<=O5M90123?K?<=<5M?0B4523018JI;78J?C9:;<=6DK9:;O5678925G=67K12345>?8B23G=>?01:3<=>?C72F2F6DK9:;O;:?;12@<=>?0J:=:=>L89:;L812F25E7>L:HO=>J652845E?0J<=:=89012345678J<;<=>789G;<=678923456789:345C?01:345K?01G105=78L:;?0D:;<=>?01:;?C7A32F6?K9I=:NM96B252F67K?;7=>I0123456789:345678123456?89:;<56789:E<=>?0123456I01234=>?012349>401D3456789:;<=H>1032456789L;<=>?1032547698;:=1033456798;:=419373578>NH;=9?672342BD?9=;H:>?06F@3517K>9;<:JL715326778>NH;=9?12474>64>::;ONHLC7132367KJLHO;=?D623GF@DK>:8:>>?CBD@G357;8:;ONHLC7135627397C74523E?89:H:=>?014@456D>??I3<=>J0BGFA30D8=:0<5M70145A30D09IH<=89E74@<5E189<=I;8L09A;4501M?70145A30D092;8=5?8B:343EDKJ2;ON>?07A@GF>7K?:;<;MLCB:3G=678?IHON6?01:343EDKJ2;4=>;0:2;G@6789I=:;K967234567>J23O;>?0123G@01>?:;<=>?09A5236789:;:NMLCB63?5>CLJIHONM8012E2201>><1015236689:93124G16<8J:=I=M701G54F61M9:3<=K90B25A5E?0J2H:;>?07A345C?01O3456J0145A30D<91;O;>?0B4523E7K1:;?I;O;>?0B4523CD092?<6>K71233FEDK>:=?<>?7BA@G26499:;;NMLC6227367>?<=:I>K71233FEDK>:9O=O=M709A;G367>J:;<=>JB9DAF@6789:=ONML85284C6A89:;<=>?0BA@GFED89:;?0123B5C1>?<;<=>?F1D34561>?<=:;8967452301>?=;<=>96745230382;;J=??0123561698;:==>?1032541499:;4HHIFGDF<567899;71032547689:;<=>?0122547699:;<=>>0123456789::=1123456789L;<9>4103254@698;:=10D3456798;:=1032547698L;<=>?012345@698;:<=>?15926?OIX\^1MIJ]A=32>586<2;96D@_UU8B@ATE48;1<3?;;009MKVR\3koho31083:46<93CE\XZ5wdc?4?69<919<=>?01A5G=61K9:;;67234=>701IHO5>?0123456789:?<6?67GF2301>9:;<5M967452567K?<=:;:?;23;B5678>I;;NMLC123456D>:9=O=>?0125BABDK9:;<=>>37A@G56789:?L=:;=?0134@ABC?8:;=>=<102255678O2;<=>?0123`>5t=9:njj==0,624>2=AGZ^X7JFA=194;773=0BB][[:EKA86<768;087AZTQWW>AIF4:0;24?>528256789;??012345679:9;<=?>0030767789:;<=>?012305=1;O9=<=>?023345679::;<=?<3210556789:;<=>>003342EDN>98:>>?0B40550382<=:=>?C9:;<=>FM9:;O;8L8125G567>?I3O;89C125G301>?<=O=>?0123G301K9>;7;896723<56D>?<=:;>7012@2301ML?0B:;G56789:H:;896B2@G56D>?<=:9>467452301>?<<<=>?01234201>?<=<=>?0210456789:;<:8967454567N9:;<=>?41952301M9O=:;896745A5@789:=:;89E1G52301>?<=I=H?01234567N9O=:;8?01274>01N9:;J;896745B567;?IHONM93123B301??<=J=>?CBAEGFE1;9:;;NJKDEA@35273?==:K>9312E2311>O:8==>I67552C679:I:?;MLCB40456CLMNMHIJK712@GCED?=:0;=J8015@GFED?9<8<=9LCBA@355689=HONML713045EDKMLNO=J801D523@1>?L;8=58C15@GFE7KJ:M:;9967552C60K9=HONM?302342EDKJI;ON>?06A@GFE7K>9;<:M;0:5@G3548:9;<=>?30327307>?:;:IJKD7234567>MNOHIJK612345B1;?N;<=>?0163?=>?09:;<5MJC923456BJ1LINH>?012F<=>B0123I=>?0B43G36789O<;K9838;0A16<0123456789:3456789:;<=H789:;456789L;<=>?012345>?0123<=>?01234C67<91345678B234F>?01234N>?07452@01>?:;?6D234@078J:?<66789:;B=>?01234567F12345>?0123456789:;<=>?09:;<=>?0123B=>?01:;<=?>;98JJUSS2mcem1950?30?=?09:;<=>BK1:;<=>?CDA345678;ONIHKJE3234567M1O?<66I89234450N>9:<=>?6EFG@A0789:;:IJKDEFG@36789N<5<7290;656709O;4=>?0107A7E709:;4=>?81G34567092345K?8528E0G2I4?6=83:1<7>58;88>>>I89:;4744:::<45680300666?0L2M<=>?022;<>GCL[K7<374AEFQE9776k1JHI\N<0394;?>99B@ATF48437LJKR@>1:==FLMXJ0>07;@FGVD:3611JHI\N<4<;?DBCZH6=255NDEPB828?3HNO^L27>99B@ATF40437LJKRC>3:<=FLMXI0<>1b:CG@WD;980;245NDEPA847902KOH_L31?:8EABUJ58546OKDS@?7;>GCL[H7;364AEFQF9>902KOH_L39?18EIJ?3K_XSD@IO528G56DK9:;<=M967G523E789I=:;M967A3456789:3O;K?01A523E78?I;<=M967A305=D8J<;78J<=:;8L01:34F01>??074FA3018J<;<5M96745G=6382I=<=>?0D2FG=6789:;J09A5456?012N<=>?892F4567812345HIFGDEBC@ANO>;7N8<19AE456498;8:;89012@G354;?IH<=>LCDDG@AED89::?;MLCBA@4560KJIHO9>4C743456789:;<=M789A5250189IJ4HOL012345CA112MNOK?0123?419@23678J8;4=6?2B234F0189:;O5>?01A5450D89:3ONM781:;4567M;:;<=>?01274>E1>?O=:;>961234=EDK1:;<=M967G523670J:;:NMLCB2@G567>JIHON>L81232F273J2N4N>?0123L812345>D89:;<=>?09A@G561KJO945M7012525>D>=:0ONM?011254769<=;<=9L0115GF1789O=::9967D3451CKJIHON9?01D52311>?L;8=5LCB2@G5678J23456?89234301>?I;<=>L67G52@0789:;<5>?0B232F678J<;I;M;0:A@GF670J:;:NMLCB234567K??01234=>7M923<=>?C7452F6DK9:;O;896B63?FEDK99:<=>8CBA@G551K9:MIKJL7123456798:<<8CBA@316015@GFEDK9;8<=HLEGFGGF1789:;:>=90123451DKJIH;=89015@GFED<91HONMLCBA@GFE789:;<=>?F1D@GFE789:;J=H?01234567KJIHONM?012E456789:?<6MLCBAE4CEDKJIHONMI0G2345EDKJIHONMLCBA@GFEDKJ:;<=>?012E4CEDKJ:;<=:?;BAE456789LH:>??0124G56489I<<=>IC7124FE089:<=10524560KJIOONM80528GCE08?9:<=9LCGA4467789=HOKM801307370KJIH;=>?015G@27C?9:;<=9KC62457=D@LI@SAGLEOQF[Q_WM=1H@F>9;BNH5=613JF@>:>:;BNH6]>EKCH;O>:5LLJC2@1110327567;8;:=3123GFEDNJIHO=>?7BA@GFED?9:;J;897745B567N?<=;;84DHC?4;016:FJE959>2NBN1>16:FJF979>2NBN1<18:FJF95=87<0HDL33?48@JG;87<0HBO31?48@JG;:720HBO33;2=2>BHI595:6J@B=2=2>BHJ5;5:6J@B=0=<>BHJ591<384DN@?7;5?01234561;8:;<:>?0123426789:;=>8L01234201>?<=::>?0GA74>@789:;<=>?0123456789?CBA@GFEDK9:;<;M701234567K9:;<=>?C123A3273OLMJKHIFGDEB56789:MJKHIFGDEBC@789:;4)eXiqcTxt~j=0.`[gsmVybvh36,b]`khkhfVigg0>#c^ffbdsk|Vnjxl3?,b]gmvgedlU|m`Pbit\gjjk59&hSig|acnf[rgufVhczR|nnfg>4)eXmekico{inl\`lt:'aefi"m}ahe,@jereld"MX/Fkw[Wcwgz%c{Rmcidlw+lvdg{oThd| tlr,[fa($jUnbllce^11flrXimnyi~}20-a\bdkndp7x|l|{ao1/gZnf{VkseRgk=1.`[mgtWldj1="l_icp[`he59&hSeo|_hliafrbz{7; nQgar]nahYh}}z~xR|jgr]b95*dWakxS`kb_nwwtprXzlmxSo3?,b]kevYj}qUdyy~zt^pfcvYf59&hSeo|_lw{[jssx|~T~hi|_c?3(fYoizUyijmja<2/gZnf{Vxnknkm=1.`[mgtW{ym0>#c^jbwZtt|k7; nQgar]pkcrbkjUbb}{{_sgdwZg:8%iTdl}PsndwafeXg|~{yyQ}efq\f86+kVceeyQiimg\jdkb5OEEXRCJM/ojb)eXagcmRxnl<2/gZoia}hTzlb20-a\mkrbzokhiRzvpd?3(fYkghnTecg{_gkoa87+kVgnaRzvpd?3(fYj}qU{e}kciog\wqg`mz7; nQrho\p|vb58&hSknd^fftqnXi4>;5;"l_sgb`Zbbx}bTn0:?97.`[wcflV}bhyfPa<:/gZtbimU|eizg_c?;(fYu{}U{~da}iu{\e8EB$jUyyQrhmqmqXj4IN nQ}su]w}uc:[PDH nQ}supbiZg:8%iT~~z}al]a95*dWzcfSnaclhqjkkYd`li`1LBC,b]vw`Yeq}oT{ho20-a\qvcXjp~nSzkm=1.`[pubWmommxb{_ecwe87+kVxiRklc<2/gZstmVydjyklc<2/gZqbiV}bhyf21-a\s`dX`nd0?#c^uqmqcXllzdRo241;5(fYpz`~nSikti]a916>>%iT{g{e^ol``Yf5^XBXHQIISQW(fYpz`~nS`ake^`>SWOSMVLB^^Z#c^uqmqcX`ndRo28-a\swosmV}bhyfPb<:/gZ~cmchikobim{>wugu|hd8ip?l;GMMPZKBE%hggRcjm^efjZp0W;&pq<5H3:EM@2=NF@^T<=94IOKW[5703@DBXR>=7:KMMQY7;>1BBDZP0558MKOSW9?<7D@FT^253>OIA]U;;:5FNHV\4=11BBDZP1558MKOSW8?<7D@FT^353>OIA]U:;:5FNHV\5=1B69JJLRX9J=0ECG[_0F4?LHN\V;N;6GAIU]2B2=NF@^T>=94IOKW[7703@DBXR<=7:KMMQY5;>1BBDZP2558MKOSW;?<7D@FT^053>OIA]U9;:5FNHV\6=11BBDZP3558MKOSW:?<7D@FT^153>OIA]U8;:5FNHV\7=178;HLJPZ5F?2CEEYQ5vk_M68TDTSi2ZBBRLZSHF[f>VNFVH^_COBE79SWAIIMj1YM@L>6^Q7[V2692YC^HIPEYVQEFRXFNIn7^F]EF]NMKYTASO:?6]FM^ALHIOTAFDTOEKLK79PKPTDM>1X^[OC_@58WWPFDVH?7^]]A59PWWD13Z^JXX];;U[SA3c<]9%syQmlj]nahY`mgoymya}/flbplpbjdm%blzfvd]ahnYjmdUlic!yamkg*fusz&xjaaa`pZ2^*wgj&{%x?Rgaiu,qeh)cx{kf"i~;x5,qeh0b3\:$t~zPbmi\i`kXoldn~lz`r.emeqoqmkgl"co{iwg\fimXelgTkh` v`nj`+et|{%ym`b`oqY2Y+tfe'x$>Qfnhv-vdk(lyxja#j4y6-vdkd3\YN^RXFSH@OA6=QKJ30ZDKX_U[SA6=PMH90[HLm;VPJP@YAA[Y_o6Y]IUG\IJBBWHi0[_G[E^OL@@YE9m1SEAGAX,ZGF%6)9)Y_YO.?.0"BWFON>2RXXAGM7:ZPPZAIL>1S_YQYCB`8\ZEHZLUBBKA9;Yfa[Lba3QncS]|fmWgqwlii991Sh`QBakmqR`ttafd:<6Vkm^OjjjtQm{ybcc=4Xrv0?\ct02koho30?;8eabui5;;2o5ndepb847=8730mij}a=32:==flmxj0<07;`fgvd:5611jhi|n<2<;?dbczh6?255ndepb808?3hno~l29>99b`atf4>437ljkr`>;:==flmxj040>8:`ooZkbeVmnbRijndpjgZet|{;37obd_lgn[bciWyxbaRyfduj\54>Qfnhv\574%><:4bmi\i`kXoldTz:Q=_yqw56=edbUfi`Qfnqww[gjhkb;?7obd_lgn[jssx|~Tnaalk59`hng03mcem1>17:fjjd:66>1oeco32?58`lhf4:4<7igaa=6=3>bnfh6>2:5kioc?2;?69gmkg;?720hb{{a=2=<>bh}}k7=364dnwwe94902ndyyo33?:8`jssi5>546j`uuc?1;>qbi5:1<384wdc?4;{GHyim7MNwb98E>1<6sZ3o6<454==8n6lk92zl26d<63g;9n784$00;>4443tY2n7?=c;33=?74;<>9i7oj669Pbc<6=00;6<=<550f>dc1l2Y2n7?:9;295652<;o1mh8i;e`;>5<628qX5i4>2b824<<6;:??>h4ne748rQ76:3:1=7?521yP=a<6:j0:<44>32776`=:09v555=82w/==o5419af=<728o187"6910i46T85;6x7g<4i3??68;5}%313?73:2.3;7ln;%;`>g?<,8;;6<5+11d957b5<#99i1=>>4n02a>5=5<#99i1=>>4n02a>7=54i01;>5<#99i1=>>4n02a>1=5<#99i1=>>4n02a>3=6=4+11a95665<#99i1=>>4n02a>==5<#99i1=>>4n02a>d=5<#99i1=9k4n02a>5=o6=4+11a951c5<#99i1=9k4n02a>7=i6=4+11a951c54i06b>5<#99i1=9k4n02a>1=26=4+11a951c5<#99i1=9k4n02a>3=<6=4+11a951c5<5<#99i1=894n02a>4=6=4+11a95015<#99i1=894n02a>6=5<#99i1=894n02a>0=5<#99i1=894n02a>2=:183!7603;:o6F>259K54d198ag>N6:=1C=6;u<8;1:>17=<;0??7:;:|&242<6=h1/ni4:0:&aa?3?3-hm695+c184<>"d93?=7)m=:008 f5=;j1/o948d:&`1?d<,j<1>95+c6842>"d03;h7)m6:3c8 fg==;1/oo4>e:&`g?203-io6>j4$bg9f3=#ko0n7)j?:6d8 a7=9o1/h?4l;%f0>7b<,m>1>>5+d481f>"c>38m7)j8:308 a>=?>1/h44;8:&ge?473-ni6:l4$ea960=#lm0=7)jj:e9'`c<6l2.n<79n;%g2>07<,l81>;5+e2867>"b<3287)k::218 `0=0=1/i:4=c:&f6=#n9087)h>:29'b7<43-l86>5+f580?!`22:1/j;4<;%d4>6=#n1087)h6:29'bd<43-li6>5+fb80?!`c2;1/jh4=;%325?133-;:?7<4$037>7=#9;;1=?>4$001>4473`2n6=44i8194?=nj:0;66gm4;29?l76=3:17d?>6;29?l76m3:17d?>f;29?l3c290/==m55b9m55d=821b9o4?:%33g?3d3g;;n7?4;h45>5<#99i19n5a11`96>=n><0;6)??c;7`?k77j3907d8;:18'55e==j1e==l54:9j26<72-;;o7;l;o33f?3<3`<96=4+11a91f=i99h1:65f6083>!77k3?h7c??b;58?l07290/==m55b9m55d=021b9k4?:%33g?3d3g;;n774;h7f>5<#99i19n5a11`9e>=n=h0;6)??c;7`?k77j3h07d8n:18'55e=>01e==l50:9j2=<72-;;o786;o33f?7<3`=86=4+11a92<=i99h1>65f7383>!77k3<27c??b;18?l16290/==m5689m55d=<21b;=4?:%33g?0>3g;;n7;4;h4e>5<#99i1:45a11`92>=n>l0;6)??c;4:?k77j3=07d8k:18'55e=>01e==l58:9j2f<72-;;o786;o33f??<3`!77k3<27c??b;`8?lg4290/==m5a39m55d=821bm<4?:%33g?g53g;;n7?4;hc3>5<#99i1m?5a11`96>=n1o0;6)??c;c1?k77j3907do7:18'55e=i>1e==l50:9je3<72-;;o7o8;o33f?7<3`k>6=4+11a9e2=i99h1>65fa583>!77k3k<7c??b;18?jgc290/==m5ab9m55d=821dmo4?:%33g?gd3g;;n7?4;ncb>5<#99i1mn5a11`96>=hi00;6)??c;c`?k77j3907bl=:18'55e=j81e==l50:9lf5<72-;;o7l>;o33f?7<3fkm6=4+11a9f4=i99h1>65`ad83>!77k3h:7c??b;18?xd69h0;6>>50;2x 47?28:n7E?=4:J25g=]?<0=w>6538875?252=91894r$024>43f3-ho6894$cg91<=#jo0i;6*l0;:8 f7=;<1/o?4>0:&`7?223-i?6984$b7954=#k?0396*l7;58 f>=9=1/o44;b:&`e??b3-ii63:&g5?7f3-n9645+d280a>"c<3;<7)j::3;8 a0=5:&g4><,l:18k5+e0802>"b:38<7)k<:258 `2=<01/i84<4:&f2?2f3-o<6?64$d:9<3=#m00::6*ja;12?!ce21;0(hm54d9'aa<43-on6>5+eg80?!`72:1/j<4<;%d1>6=#n:087)h;:29'b0<43-l=6>5+f680?!`?2:1/j44<;%db>6=#nk087)hl:29'ba<53-ln6?5+103931=#9891>6*>1581?!7593;9<6*>238265=n0l0;66g63;29?ld42900eo:50;9j543=831b=<850;9j54c=831b=!77k3?h7c??b;08?l02290/==m55b9m55d=;21b:94?:%33g?3d3g;;n7:4;h40>5<#99i19n5a11`91>=n>;0;6)??c;7`?k77j3<07d8>:18'55e==j1e==l57:9j25<72-;;o7;l;o33f?><3`?m6=4+11a91f=i99h1565f5d83>!77k3?h7c??b;c8?l3f290/==m55b9m55d=j21b:l4?:%33g?0>3g;;n7>4;h4;>5<#99i1:45a11`95>=n?:0;6)??c;4:?k77j3807d9=:18'55e=>01e==l53:9j34<72-;;o786;o33f?2<3`=;6=4+11a92<=i99h1965f6g83>!77k3<27c??b;48?l0b290/==m5689m55d=?21b:i4?:%33g?0>3g;;n764;h4`>5<#99i1:45a11`9=>=n>k0;6)??c;4:?k77j3k07d88:18'55e=>01e==l5b:9je6<72-;;o7o=;o33f?6<3`k:6=4+11a9e7=i99h1=65fa183>!77k3k97c??b;08?l?a290/==m5a39m55d=;21bm54?:%33g?g03g;;n7>4;hc5>5<#99i1m:5a11`95>=ni<0;6)??c;c4?k77j3807do;:18'55e=i>1e==l53:9lea<72-;;o7ol;o33f?6<3fki6=4+11a9ef=i99h1=65`a`83>!77k3kh7c??b;08?jg>290/==m5ab9m55d=;21dn?4?:%33g?d63g;;n7>4;n`3>5<#99i1n<5a11`95>=hio0;6)??c;`2?k77j3807boj:18'55e=j81e==l53:9~w4632908w0?=6;33<>;6900i?63>1`8a7>{t99?1<7;<32=?1734;:578i;<32=?0b34;:578k;<32=?0d34;:578m;<32=?0034;:57o7;<32=?g134;:57o:;<32=?g334;:577<;<32=?d334;:57?>5:?25<<69?16=<7510d8947f2?k01901;0170?>a;322>;69h0:=k5rs073>5<5sW;><63>188b=>{t9<;1<75383>7}Y9<801vP>529>54?=im1v<;;:181[72<27:=l4n9:p503=838pR<;:;<32e?gf3ty:9;4?:3y]500<58;j6ll4}r36=6=4<{_372>;69003i63>1`8;a>{t9==1<74983>7}Y9=201vP>489>54?=i81v<:n:181[73i27:=44n3:p51d=838pR<:m;<32e??a3ty:8n4?:3y]51e<58;j6l>4}r37`?6=:rT:8i5210c9e4=z{8>m6=4={_37b>;69h0j?6s|13g94?5|V88n70?>9;7b?876i3?j7p}>3383>6}Y9:80154g==o1v<=;:180[74<27:=4490:?25d<182wx=>;50;1xZ45234;:578>;<32e?063ty:?;4?:2y]560<58;26;<4=03b>3453z\272=:9831:>5210c926=z{8936=4<{_30<>;6900=863>1`850>{t9:31<7=t^01:?87613<>70?>a;46?xu6;h0;6>uQ12c8947>2?<012g9>54?==k16=1d9~yk>a290:wE?>b:m=5<728qC=5<6sA;:n6sa9383>4}O98h0qc7<:182M76j2we594?:0yK54d6=4>{I32f>{i1?0;6b:m==<728qC=5<6sA;:n6sa9`83>4}O98h0qc7m:182M76j2we5n4?:0yK54d{I32f>{i1l0;6b:me5<728qC=5<6sA;:n6saa383>4}O98h0qco<:182M76j2wem94?:0yK54d6=4>{I32f>{ii?0;6b:me=<728qC=5<6sA;:n6saa`83>4}O98h0qcom:182M76j2wemn4?:0yK54d{I32f>{iil0;6 + + +

+ + + + + + + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: fat_32_file_parser/trunk/ipcore_dir/coregen.cgc =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/coregen.cgc (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/coregen.cgc (revision 2) @@ -0,0 +1,850 @@ + + + xilinx.com + project + coregen + 1.0 + + + FONT_MEM + + + FONT_MEM + Native + AXI4_Full + Memory_Slave + false + 4 + Single_Port_RAM + false + No_ECC + false + false + false + Single_Bit_Error_Injection + false + 9 + Minimum_Area + 8kx2 + false + 8 + 4096 + 8 + WRITE_FIRST + Always_Enabled + 8 + 8 + WRITE_FIRST + Always_Enabled + false + false + false + false + false + false + false + false + 0 + true + /home/craig/Documents/CW/Git_Repos/hw_client/coe_dir/lat0-12.coe + true + 0 + false + false + CE + 0 + false + false + CE + 0 + SYNC + false + 100 + 50 + 100 + 50 + 100 + 100 + ALL + false + false + spartan3 + spartan3e + /home/craig/Documents/CW/Git_Repos/hw_client/ipcore_dir/tmp/_cg/ + 0 + 1 + 0 + 0 + 4 + 0 + 9 + 1 + 1 + 1 + FONT_MEM.mif + 1 + 0 + SYNC + 0 + CE + 0 + 0 + 0 + 0 + 0 + 1 + WRITE_FIRST + 8 + 8 + 4096 + 4096 + 12 + 0 + CE + 0 + 0 + 0 + 0 + 0 + 1 + WRITE_FIRST + 8 + 8 + 4096 + 4096 + 12 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ALL + 0 + 0 + 0 + 0 + + + + + coregen + ./ + ./tmp/ + ./tmp/_cg/ + + + xc3s500e + spartan3e + fg320 + -4 + + + BusFormatAngleBracketNotRipped + VHDL + true + Other + false + false + false + Ngc + false + + + Behavioral + VHDL + false + + + 2012-06-25+21:54 + + + + + apply_current_project_options_generator + + + customization_generator + + ./FONT_MEM.mif + mif + Sun Nov 02 04:45:56 GMT 2014 + 0xEF3BADEA + generationID_4013899584 + + + ./summary.log + unknown + Sun Nov 02 04:45:55 GMT 2014 + 0xCEDB5840 + generationID_4013899584 + + + + model_parameter_resolution_generator + + ./FONT_MEM.mif + mif + Sun Nov 02 04:46:02 GMT 2014 + 0xEF3BADEA + generationID_4013899584 + + + ./summary.log + unknown + Sun Nov 02 04:46:02 GMT 2014 + 0xCEDB5840 + generationID_4013899584 + + + + ip_xco_generator + + ./FONT_MEM.xco + xco + Sun Nov 02 04:46:03 GMT 2014 + 0xF71CAD35 + generationID_4013899584 + + + + associated_files_generator + + ./FONT_MEM/blk_mem_gen_v7_2_readme.txt + ignore + txt + Sat Jul 21 06:10:41 GMT 2012 + 0x5661B352 + generationID_4013899584 + + + ./FONT_MEM/doc/blk_mem_gen_v7_2_vinfo.html + ignore + unknown + Sat Jul 21 06:10:41 GMT 2012 + 0x4D7A616C + generationID_4013899584 + + + ./FONT_MEM/doc/pg058-blk-mem-gen.pdf + ignore + pdf + Sat Jul 21 06:10:41 GMT 2012 + 0xAE5E57E0 + generationID_4013899584 + + + + ejava_generator + + ./FONT_MEM/example_design/FONT_MEM_exdes.ucf + ignore + ucf + Sun Nov 02 04:46:04 GMT 2014 + 0xC44C6B6D + generationID_4013899584 + + + ./FONT_MEM/example_design/FONT_MEM_exdes.vhd + ignore + vhdl + Sun Nov 02 04:46:04 GMT 2014 + 0x7FC356B8 + generationID_4013899584 + + + ./FONT_MEM/example_design/FONT_MEM_exdes.xdc + ignore + xdc + Sun Nov 02 04:46:04 GMT 2014 + 0x7684D6D4 + generationID_4013899584 + + + ./FONT_MEM/example_design/FONT_MEM_prod.vhd + ignore + vhdl + Sun Nov 02 04:46:04 GMT 2014 + 0x1DDE4393 + generationID_4013899584 + + + ./FONT_MEM/implement/implement.bat + ignore + unknown + Sun Nov 02 04:46:04 GMT 2014 + 0xBC5E1D06 + generationID_4013899584 + + + ./FONT_MEM/implement/implement.sh + ignore + unknown + Sun Nov 02 04:46:05 GMT 2014 + 0x72C4E759 + generationID_4013899584 + + + ./FONT_MEM/implement/planAhead_ise.bat + ignore + unknown + Sun Nov 02 04:46:05 GMT 2014 + 0xE0D88582 + generationID_4013899584 + + + ./FONT_MEM/implement/planAhead_ise.sh + ignore + unknown + Sun Nov 02 04:46:05 GMT 2014 + 0x494196CB + generationID_4013899584 + + + ./FONT_MEM/implement/planAhead_ise.tcl + ignore + tcl + Sun Nov 02 04:46:05 GMT 2014 + 0x2FD6CA93 + generationID_4013899584 + + + ./FONT_MEM/implement/xst.prj + ignore + unknown + Sun Nov 02 04:46:05 GMT 2014 + 0x8E6483AC + generationID_4013899584 + + + ./FONT_MEM/implement/xst.scr + ignore + unknown + Sun Nov 02 04:46:05 GMT 2014 + 0xF05187B7 + generationID_4013899584 + + + ./FONT_MEM/simulation/FONT_MEM_synth.vhd + ignore + vhdl + Sun Nov 02 04:46:04 GMT 2014 + 0x1B990604 + generationID_4013899584 + + + ./FONT_MEM/simulation/FONT_MEM_tb.vhd + ignore + vhdl + Sun Nov 02 04:46:04 GMT 2014 + 0xFC0A0849 + generationID_4013899584 + + + ./FONT_MEM/simulation/addr_gen.vhd + ignore + vhdl + Sun Nov 02 04:46:04 GMT 2014 + 0x886696A8 + generationID_4013899584 + + + ./FONT_MEM/simulation/bmg_stim_gen.vhd + ignore + vhdl + Sun Nov 02 04:46:04 GMT 2014 + 0xE85BEE6B + generationID_4013899584 + + + ./FONT_MEM/simulation/bmg_tb_pkg.vhd + ignore + vhdl + Sun Nov 02 04:46:04 GMT 2014 + 0xD4F2B061 + generationID_4013899584 + + + ./FONT_MEM/simulation/checker.vhd + ignore + vhdl + Sun Nov 02 04:46:04 GMT 2014 + 0x2A8E7144 + generationID_4013899584 + + + ./FONT_MEM/simulation/data_gen.vhd + ignore + vhdl + Sun Nov 02 04:46:04 GMT 2014 + 0xE0759FCA + generationID_4013899584 + + + ./FONT_MEM/simulation/functional/simcmds.tcl + ignore + tcl + Sun Nov 02 04:46:04 GMT 2014 + 0x8A4B21FE + generationID_4013899584 + + + ./FONT_MEM/simulation/functional/simulate_isim.sh + ignore + unknown + Sun Nov 02 04:46:04 GMT 2014 + 0x7460DE3C + generationID_4013899584 + + + ./FONT_MEM/simulation/functional/simulate_mti.bat + ignore + unknown + Sun Nov 02 04:46:05 GMT 2014 + 0x86EA5D67 + generationID_4013899584 + + + ./FONT_MEM/simulation/functional/simulate_mti.do + ignore + unknown + Sun Nov 02 04:46:05 GMT 2014 + 0xF4B80CB7 + generationID_4013899584 + + + ./FONT_MEM/simulation/functional/simulate_mti.sh + ignore + unknown + Sun Nov 02 04:46:05 GMT 2014 + 0x86EA5D67 + generationID_4013899584 + + + ./FONT_MEM/simulation/functional/simulate_ncsim.sh + ignore + unknown + Sun Nov 02 04:46:04 GMT 2014 + 0x81A78B41 + generationID_4013899584 + + + ./FONT_MEM/simulation/functional/simulate_vcs.sh + ignore + unknown + Sun Nov 02 04:46:04 GMT 2014 + 0xCFF64775 + generationID_4013899584 + + + ./FONT_MEM/simulation/functional/ucli_commands.key + ignore + unknown + Sun Nov 02 04:46:04 GMT 2014 + 0x349B455F + generationID_4013899584 + + + ./FONT_MEM/simulation/functional/vcs_session.tcl + ignore + tcl + Sun Nov 02 04:46:04 GMT 2014 + 0x7ED2A016 + generationID_4013899584 + + + ./FONT_MEM/simulation/functional/wave_mti.do + ignore + unknown + Sun Nov 02 04:46:04 GMT 2014 + 0x8701B374 + generationID_4013899584 + + + ./FONT_MEM/simulation/functional/wave_ncsim.sv + ignore + unknown + Sun Nov 02 04:46:04 GMT 2014 + 0x9B388413 + generationID_4013899584 + + + ./FONT_MEM/simulation/random.vhd + ignore + vhdl + Sun Nov 02 04:46:04 GMT 2014 + 0xE1CDC376 + generationID_4013899584 + + + ./FONT_MEM/simulation/timing/simcmds.tcl + ignore + tcl + Sun Nov 02 04:46:04 GMT 2014 + 0x8A4B21FE + generationID_4013899584 + + + ./FONT_MEM/simulation/timing/simulate_isim.sh + ignore + unknown + Sun Nov 02 04:46:04 GMT 2014 + 0xE8EBF448 + generationID_4013899584 + + + ./FONT_MEM/simulation/timing/simulate_mti.bat + ignore + unknown + Sun Nov 02 04:46:05 GMT 2014 + 0x86EA5D67 + generationID_4013899584 + + + ./FONT_MEM/simulation/timing/simulate_mti.do + ignore + unknown + Sun Nov 02 04:46:05 GMT 2014 + 0x1467B52A + generationID_4013899584 + + + ./FONT_MEM/simulation/timing/simulate_mti.sh + ignore + unknown + Sun Nov 02 04:46:05 GMT 2014 + 0x86EA5D67 + generationID_4013899584 + + + ./FONT_MEM/simulation/timing/simulate_ncsim.sh + ignore + unknown + Sun Nov 02 04:46:04 GMT 2014 + 0x205E9C3B + generationID_4013899584 + + + ./FONT_MEM/simulation/timing/simulate_vcs.sh + ignore + unknown + Sun Nov 02 04:46:04 GMT 2014 + 0xFFF8316A + generationID_4013899584 + + + ./FONT_MEM/simulation/timing/ucli_commands.key + ignore + unknown + Sun Nov 02 04:46:04 GMT 2014 + 0x349B455F + generationID_4013899584 + + + ./FONT_MEM/simulation/timing/vcs_session.tcl + ignore + tcl + Sun Nov 02 04:46:04 GMT 2014 + 0x30D5140D + generationID_4013899584 + + + ./FONT_MEM/simulation/timing/wave_mti.do + ignore + unknown + Sun Nov 02 04:46:04 GMT 2014 + 0xC1F74616 + generationID_4013899584 + + + ./FONT_MEM/simulation/timing/wave_ncsim.sv + ignore + unknown + Sun Nov 02 04:46:04 GMT 2014 + 0x4441FE12 + generationID_4013899584 + + + + ngc_netlist_generator + + ./FONT_MEM.ngc + ngc + Sun Nov 02 04:46:55 GMT 2014 + 0x84C21EC2 + generationID_4013899584 + + + + obfuscate_netlist_generator + + + padded_implementation_netlist_generator + + + instantiation_template_generator + + ./FONT_MEM.vho + vho + Sun Nov 02 04:46:55 GMT 2014 + 0xD074038C + generationID_4013899584 + + + + synthesis_instantiation_wrapper_generator + + ./FONT_MEM_synth.vhd + vhdl + vhdlSynthesis + Sun Nov 02 04:46:56 GMT 2014 + 0x0050F6A9 + generationID_4013899584 + + + + structural_simulation_model_generator + + ./FONT_MEM.vhd + vhdl + Sun Nov 02 04:46:56 GMT 2014 + 0x3A0E3D60 + generationID_4013899584 + + + + all_documents_generator + + + asy_generator + + ./FONT_MEM.asy + asy + Sun Nov 02 04:47:01 GMT 2014 + 0x7C90C72F + generationID_4013899584 + + + ./FONT_MEM.mif + mif + Sun Nov 02 04:47:01 GMT 2014 + 0xEF3BADEA + generationID_4013899584 + + + ./summary.log + unknown + Sun Nov 02 04:47:01 GMT 2014 + 0xCEDB5840 + generationID_4013899584 + + + + xmdf_generator + + ./FONT_MEM_xmdf.tcl + tclXmdf + tcl + Sun Nov 02 04:47:01 GMT 2014 + 0x9A77B47A + generationID_4013899584 + + + + synthesis_ise_generator + + ./FONT_MEM.gise + ignore + gise + Sun Nov 02 04:47:05 GMT 2014 + 0xD9CAE07F + generationID_4013899584 + + + ./FONT_MEM.xise + ignore + xise + Sun Nov 02 04:47:05 GMT 2014 + 0xBC2C616B + generationID_4013899584 + + + + ise_generator + + ./FONT_MEM.gise + ignore + gise + Sun Nov 02 04:47:09 GMT 2014 + 0xE1F46F43 + generationID_4013899584 + + + ./FONT_MEM.xise + ignore + xise + Sun Nov 02 04:47:09 GMT 2014 + 0x7AC6A9F7 + generationID_4013899584 + + + + deliver_readme_generator + + + flist_generator + + ./FONT_MEM_flist.txt + ignore + txtFlist + txt + Sun Nov 02 04:47:09 GMT 2014 + 0x2405973F + generationID_4013899584 + + + + view_readme_generator + + + + + + blk_mem_gen_v7_2 + + + blk_mem_gen_v7_2 + Native + AXI4_Full + Memory_Slave + false + 4 + Single_Port_RAM + false + No_ECC + false + false + false + Single_Bit_Error_Injection + false + 9 + Minimum_Area + 8kx2 + false + 8 + 4096 + 8 + WRITE_FIRST + Always_Enabled + 8 + 8 + WRITE_FIRST + Always_Enabled + false + false + false + false + false + false + false + false + 0 + true + /home/craig/Documents/craigs/projectV/nexys2/ps2 keyboard/ps2keyboard/lat0-12.coe + true + 0 + false + false + CE + 0 + false + false + CE + 0 + SYNC + false + 100 + 50 + 100 + 50 + 100 + 100 + ALL + false + false + + + + + coregen + ./ + ./tmp/ + ./tmp/_cg/ + + + xc3s500e + spartan3e + fg320 + -4 + + + BusFormatAngleBracketNotRipped + VHDL + true + Other + false + false + false + Ngc + false + + + Behavioral + VHDL + false + + + 2012-06-25+21:54 + + + + + + + + + coregen + ./ + ./tmp/ + ./tmp/_cg/ + + + xc3s500e + spartan3e + fg320 + -4 + + + BusFormatAngleBracketNotRipped + VHDL + true + Other + false + false + false + Ngc + false + + + Behavioral + VHDL + false + + + + + Index: fat_32_file_parser/trunk/ipcore_dir/summary.log =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/summary.log (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/summary.log (revision 2) @@ -0,0 +1,18 @@ + +User Configuration +------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : 8 +Port A Write Width : 8 +Memory Depth : 4096 +-------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : 2 +-------------------------------------------------------------- +Clock A Frequency : 100 +Port A Enable Rate : 100 +Port A Write Rate : 50 +---------------------------------------------------------- +Estimated Power for IP : 10.400848 mW +---------------------------------------------------------- Index: fat_32_file_parser/trunk/ipcore_dir/FONT_MEM.mif =================================================================== --- fat_32_file_parser/trunk/ipcore_dir/FONT_MEM.mif (nonexistent) +++ fat_32_file_parser/trunk/ipcore_dir/FONT_MEM.mif (revision 2) @@ -0,0 +1,3072 @@ +01111110 +11000011 +10011001 +10011001 +11110011 +11100111 +11100111 +11111111 +11100111 +11100111 +01111110 +00000000 +00000000 +00000000 +00000000 +01110110 +11011100 +00000000 +01110110 +11011100 +00000000 +00000000 +00000000 +00000000 +01101110 +11011000 +11011000 +11011000 +11011000 +11011110 +11011000 +11011000 +11011000 +01101110 +00000000 +00000000 +00000000 +00000000 +00000000 +01101110 +11011011 +11011011 +11011111 +11011000 +11011011 +01101110 +00000000 +00000000 +00000000 +00000000 +00010000 +00111000 +01111100 +11111110 +01111100 +00111000 +00010000 +00000000 +00000000 +00000000 +10001000 +10001000 +11111000 +10001000 +10001000 +00000000 +00111110 +00001000 +00001000 +00001000 +00001000 +00000000 +11111000 +10000000 +11100000 +10000000 +10000000 +00000000 +00111110 +00100000 +00111000 +00100000 +00100000 +00000000 +01111000 +10000000 +10000000 +10000000 +01111000 +00000000 +00111100 +00100010 +00111110 +00100100 +00100010 +00000000 +10000000 +10000000 +10000000 +10000000 +11111000 +00000000 +00111110 +00100000 +00111000 +00100000 +00100000 +00000000 +00100010 +10001000 +00100010 +10001000 +00100010 +10001000 +00100010 +10001000 +00100010 +10001000 +00100010 +10001000 +01010101 +10101010 +01010101 +10101010 +01010101 +10101010 +01010101 +10101010 +01010101 +10101010 +01010101 +10101010 +11101110 +10111011 +11101110 +10111011 +11101110 +10111011 +11101110 +10111011 +11101110 +10111011 +11101110 +10111011 +11111111 +11111111 +11111111 +11111111 +11111111 +11111111 +11111111 +11111111 +11111111 +11111111 +11111111 +11111111 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11111111 +11111111 +11111111 +11111111 +11111111 +11111111 +11111111 +11111111 +11111111 +11111111 +11111111 +11111111 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11110000 +11110000 +11110000 +11110000 +11110000 +11110000 +11110000 +11110000 +11110000 +11110000 +11110000 +11110000 +00001111 +00001111 +00001111 +00001111 +00001111 +00001111 +00001111 +00001111 +00001111 +00001111 +00001111 +00001111 +10001000 +11001000 +10101000 +10011000 +10001000 +00000000 +00100000 +00100000 +00100000 +00100000 +00111110 +00000000 +10001000 +10001000 +01010000 +01010000 +00100000 +00000000 +00111110 +00001000 +00001000 +00001000 +00001000 +00000000 +00000000 +00000000 +00000110 +00001100 +00011000 +00110000 +01111110 +00000000 +01111110 +00000000 +00000000 +00000000 +00000000 +00000000 +01100000 +00110000 +00011000 +00001100 +01111110 +00000000 +01111110 +00000000 +00000000 +00000000 +00000000 +00000000 +00000110 +00001100 +11111110 +00111000 +11111110 +01100000 +11000000 +00000000 +00000000 +00000000 +00000000 +00000010 +00001110 +00111110 +01111110 +11111110 +01111110 +00111110 +00001110 +00000010 +00000000 +00000000 +00000000 +10000000 +11100000 +11110000 +11111100 +11111110 +11111100 +11110000 +11100000 +10000000 +00000000 +00000000 +00000000 +00011000 +00111100 +01111110 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00000000 +00000000 +00000000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +01111110 +00111100 +00011000 +00000000 +00000000 +00000000 +00000000 +00000000 +00011000 +00001100 +11111110 +00001100 +00011000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00110000 +01100000 +11111110 +01100000 +00110000 +00000000 +00000000 +00000000 +00000000 +00000000 +00011000 +00111100 +01111110 +00011000 +00011000 +00011000 +01111110 +00111100 +00011000 +00000000 +00000000 +00000000 +00000000 +00000000 +00101000 +01101100 +11111110 +01101100 +00101000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000110 +00000110 +00110110 +01100110 +11111110 +01100000 +00110000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11000000 +01111100 +01101110 +01101100 +01101100 +01101100 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00011000 +00111100 +00111100 +00111100 +00011000 +00011000 +00000000 +00011000 +00011000 +00000000 +00000000 +00000000 +00110110 +00110110 +00010100 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +01101100 +11111110 +01101100 +01101100 +01101100 +11111110 +01101100 +00000000 +00000000 +00000000 +00010000 +01111100 +11010110 +01110000 +00111000 +00011100 +11010110 +01111100 +00010000 +00000000 +00000000 +00000000 +00000000 +00000000 +01100010 +01100110 +00001100 +00011000 +00110000 +01100110 +11000110 +00000000 +00000000 +00000000 +00111000 +01101100 +00111000 +00111000 +01110010 +11111110 +11001100 +11001100 +01110110 +00000000 +00000000 +00011100 +00011100 +00001100 +00011000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00001100 +00011000 +00110000 +00110000 +00110000 +00110000 +00110000 +00011000 +00001100 +00000000 +00000000 +00000000 +00110000 +00011000 +00001100 +00001100 +00001100 +00001100 +00001100 +00011000 +00110000 +00000000 +00000000 +00000000 +00000000 +00000000 +01101100 +00111000 +11111110 +00111000 +01101100 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00011000 +00011000 +01111110 +00011000 +00011000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00001100 +00001100 +00001100 +00011000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11111110 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00011000 +00011000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000110 +00001100 +00011000 +00110000 +01100000 +11000000 +00000000 +00000000 +00000000 +00000000 +01111100 +11000110 +11000110 +11000110 +11010110 +11000110 +11000110 +11000110 +01111100 +00000000 +00000000 +00000000 +00011000 +01111000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +01111110 +00000000 +00000000 +00000000 +01111100 +11000110 +11000110 +00001100 +00011000 +00110000 +01100000 +11000110 +11111110 +00000000 +00000000 +00000000 +01111100 +11000110 +00000110 +00000110 +00111100 +00000110 +00000110 +11000110 +01111100 +00000000 +00000000 +00000000 +00001100 +00011100 +00111100 +01101100 +11001100 +11111110 +00001100 +00001100 +00001100 +00000000 +00000000 +00000000 +11111110 +11000000 +11000000 +11000000 +11111100 +00000110 +00000110 +11000110 +01111100 +00000000 +00000000 +00000000 +01111100 +11000110 +11000000 +11000000 +11111100 +11000110 +11000110 +11000110 +01111100 +00000000 +00000000 +00000000 +11111110 +11000110 +00001100 +00011000 +00110000 +00110000 +00110000 +00110000 +00110000 +00000000 +00000000 +00000000 +01111100 +11000110 +11000110 +11000110 +01111100 +11000110 +11000110 +11000110 +01111100 +00000000 +00000000 +00000000 +01111100 +11000110 +11000110 +11000110 +01111110 +00000110 +00000110 +11000110 +01111100 +00000000 +00000000 +00000000 +00000000 +00000000 +00001100 +00001100 +00000000 +00000000 +00001100 +00001100 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00001100 +00001100 +00000000 +00000000 +00001100 +00001100 +00001100 +00011000 +00000000 +00000000 +00001100 +00011000 +00110000 +01100000 +11000000 +01100000 +00110000 +00011000 +00001100 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11111110 +00000000 +11111110 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +01100000 +00110000 +00011000 +00001100 +00000110 +00001100 +00011000 +00110000 +01100000 +00000000 +00000000 +00000000 +01111100 +11000110 +11000110 +00001100 +00011000 +00011000 +00000000 +00011000 +00011000 +00000000 +00000000 +00000000 +01111100 +11000110 +11000110 +11011110 +11011110 +11011110 +11011100 +11000000 +01111110 +00000000 +00000000 +00000000 +00111000 +01101100 +11000110 +11000110 +11000110 +11111110 +11000110 +11000110 +11000110 +00000000 +00000000 +00000000 +11111100 +01100110 +01100110 +01100110 +01111100 +01100110 +01100110 +01100110 +11111100 +00000000 +00000000 +00000000 +00111100 +01100110 +11000000 +11000000 +11000000 +11000000 +11000000 +01100110 +00111100 +00000000 +00000000 +00000000 +11111000 +01101100 +01100110 +01100110 +01100110 +01100110 +01100110 +01101100 +11111000 +00000000 +00000000 +00000000 +11111110 +01100110 +01100000 +01100000 +01111100 +01100000 +01100000 +01100110 +11111110 +00000000 +00000000 +00000000 +11111110 +01100110 +01100000 +01100000 +01111100 +01100000 +01100000 +01100000 +11110000 +00000000 +00000000 +00000000 +01111100 +11000110 +11000110 +11000000 +11000000 +11001110 +11000110 +11000110 +01111100 +00000000 +00000000 +00000000 +11000110 +11000110 +11000110 +11000110 +11111110 +11000110 +11000110 +11000110 +11000110 +00000000 +00000000 +00000000 +00111100 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00111100 +00000000 +00000000 +00000000 +00111100 +00011000 +00011000 +00011000 +00011000 +00011000 +11011000 +11011000 +01110000 +00000000 +00000000 +00000000 +11000110 +11001100 +11011000 +11110000 +11110000 +11011000 +11001100 +11000110 +11000110 +00000000 +00000000 +00000000 +11110000 +01100000 +01100000 +01100000 +01100000 +01100000 +01100010 +01100110 +11111110 +00000000 +00000000 +00000000 +11000110 +11000110 +11101110 +11111110 +11010110 +11010110 +11010110 +11000110 +11000110 +00000000 +00000000 +00000000 +11000110 +11000110 +11100110 +11100110 +11110110 +11011110 +11001110 +11001110 +11000110 +00000000 +00000000 +00000000 +01111100 +11000110 +11000110 +11000110 +11000110 +11000110 +11000110 +11000110 +01111100 +00000000 +00000000 +00000000 +11111100 +01100110 +01100110 +01100110 +01111100 +01100000 +01100000 +01100000 +11110000 +00000000 +00000000 +00000000 +01111100 +11000110 +11000110 +11000110 +11000110 +11000110 +11000110 +11010110 +01111100 +00000110 +00000000 +00000000 +11111100 +01100110 +01100110 +01100110 +01111100 +01111000 +01101100 +01100110 +11100110 +00000000 +00000000 +00000000 +01111100 +11000110 +11000000 +01100000 +00111000 +00001100 +00000110 +11000110 +01111100 +00000000 +00000000 +00000000 +01111110 +01011010 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00111100 +00000000 +00000000 +00000000 +11000110 +11000110 +11000110 +11000110 +11000110 +11000110 +11000110 +11000110 +01111100 +00000000 +00000000 +00000000 +11000110 +11000110 +11000110 +11000110 +11000110 +11000110 +01101100 +00111000 +00010000 +00000000 +00000000 +00000000 +11000110 +11000110 +11010110 +11010110 +11010110 +11111110 +11101110 +11000110 +11000110 +00000000 +00000000 +00000000 +11000110 +11000110 +01101100 +00111000 +00111000 +00111000 +01101100 +11000110 +11000110 +00000000 +00000000 +00000000 +01100110 +01100110 +01100110 +01100110 +00111100 +00011000 +00011000 +00011000 +00111100 +00000000 +00000000 +00000000 +11111110 +11000110 +10001100 +00011000 +00110000 +01100000 +11000010 +11000110 +11111110 +00000000 +00000000 +00000000 +01111100 +01100000 +01100000 +01100000 +01100000 +01100000 +01100000 +01100000 +01111100 +00000000 +00000000 +00000000 +00000000 +00000000 +11000000 +01100000 +00110000 +00011000 +00001100 +00000110 +00000000 +00000000 +00000000 +00000000 +01111100 +00001100 +00001100 +00001100 +00001100 +00001100 +00001100 +00001100 +01111100 +00000000 +00000000 +00000000 +00011000 +00111100 +01100110 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11111111 +00011100 +00011100 +00011000 +00001100 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +01111000 +00001100 +01111100 +11001100 +11011100 +01110110 +00000000 +00000000 +00000000 +11100000 +01100000 +01100000 +01111100 +01100110 +01100110 +01100110 +01100110 +11111100 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +01111100 +11000110 +11000000 +11000000 +11000110 +01111100 +00000000 +00000000 +00000000 +00011100 +00001100 +00001100 +01111100 +11001100 +11001100 +11001100 +11001100 +01111110 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +01111100 +11000110 +11111110 +11000000 +11000110 +01111100 +00000000 +00000000 +00000000 +00011100 +00110110 +00110000 +00110000 +11111100 +00110000 +00110000 +00110000 +01111000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +01110110 +11001110 +11000110 +11000110 +01111110 +00000110 +11000110 +01111100 +00000000 +11100000 +01100000 +01100000 +01101100 +01110110 +01100110 +01100110 +01100110 +11100110 +00000000 +00000000 +00000000 +00011000 +00011000 +00000000 +00111000 +00011000 +00011000 +00011000 +00011000 +00111100 +00000000 +00000000 +00000000 +00000000 +00001100 +00001100 +00000000 +00011100 +00001100 +00001100 +00001100 +11001100 +11001100 +01111000 +00000000 +11100000 +01100000 +01100000 +01100110 +01101100 +01111000 +01101100 +01100110 +11100110 +00000000 +00000000 +00000000 +01110000 +00110000 +00110000 +00110000 +00110000 +00110000 +00110000 +00110100 +00011000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +01101100 +11111110 +11010110 +11010110 +11000110 +11000110 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11011100 +01100110 +01100110 +01100110 +01100110 +01100110 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +01111100 +11000110 +11000110 +11000110 +11000110 +01111100 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11011100 +01100110 +01100110 +01100110 +01111100 +01100000 +01100000 +11110000 +00000000 +00000000 +00000000 +00000000 +01110110 +11001100 +11001100 +11001100 +01111100 +00001100 +00001100 +00011110 +00000000 +00000000 +00000000 +00000000 +11011100 +01100110 +01100000 +01100000 +01100000 +11110000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +01111100 +11000110 +01110000 +00011100 +11000110 +01111100 +00000000 +00000000 +00000000 +00110000 +00110000 +00110000 +11111100 +00110000 +00110000 +00110000 +00110110 +00011100 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11001100 +11001100 +11001100 +11001100 +11001100 +01110110 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11000110 +11000110 +11000110 +01101100 +00111000 +00010000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11000110 +11000110 +11010110 +11010110 +11111110 +01101100 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11000110 +01101100 +00111000 +00111000 +01101100 +11000110 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11000110 +11000110 +11000110 +11001110 +01110110 +00000110 +11000110 +01111100 +00000000 +00000000 +00000000 +00000000 +11111110 +10001100 +00011000 +00110000 +01100010 +11111110 +00000000 +00000000 +00000000 +00001110 +00011000 +00011000 +00011000 +01110000 +00011000 +00011000 +00011000 +00001110 +00000000 +00000000 +00000000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00000000 +00000000 +00000000 +01110000 +00011000 +00011000 +00011000 +00001110 +00011000 +00011000 +00011000 +01110000 +00000000 +00000000 +00000000 +01110110 +11011100 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +01100110 +01100110 +00000000 +01100110 +01100110 +01100110 +00111100 +00011000 +00011000 +00111100 +00000000 +00000000 +00110000 +00011000 +00000000 +00111000 +01101100 +11000110 +11000110 +11111110 +11000110 +11000110 +00000000 +00000000 +00011000 +00110000 +00000000 +00111000 +01101100 +11000110 +11000110 +11111110 +11000110 +11000110 +00000000 +00000000 +00111000 +01101100 +00111000 +00000000 +01111100 +11000110 +11000110 +11111110 +11000110 +11000110 +00000000 +00000000 +01110110 +11011100 +00000000 +00111000 +01101100 +11000110 +11000110 +11111110 +11000110 +11000110 +00000000 +00000000 +01101100 +01101100 +00000000 +00111000 +01101100 +11000110 +11000110 +11111110 +11000110 +11000110 +00000000 +00000000 +00111000 +01101100 +00111000 +00000000 +01111100 +11000110 +11000110 +11111110 +11000110 +11000110 +00000000 +00000000 +01111110 +11011000 +11011000 +11011000 +11011000 +11111110 +11011000 +11011000 +11011000 +11011110 +00000000 +00000000 +00000000 +00111100 +01100110 +11000000 +11000000 +11000000 +11000110 +01100110 +00111100 +00011000 +11001100 +00111000 +00011000 +00001100 +00000000 +11111110 +01100110 +01100000 +01111100 +01100000 +01100110 +11111110 +00000000 +00000000 +00011000 +00110000 +00000000 +11111110 +01100110 +01100000 +01111100 +01100000 +01100110 +11111110 +00000000 +00000000 +00111000 +01101100 +00000000 +11111110 +01100110 +01100000 +01111100 +01100000 +01100110 +11111110 +00000000 +00000000 +01101100 +01101100 +00000000 +11111110 +01100110 +01100000 +01111100 +01100000 +01100110 +11111110 +00000000 +00000000 +00011000 +00001100 +00000000 +00111100 +00011000 +00011000 +00011000 +00011000 +00011000 +00111100 +00000000 +00000000 +00011000 +00110000 +00000000 +00111100 +00011000 +00011000 +00011000 +00011000 +00011000 +00111100 +00000000 +00000000 +00111100 +01100110 +00000000 +00111100 +00011000 +00011000 +00011000 +00011000 +00011000 +00111100 +00000000 +00000000 +01100110 +01100110 +00000000 +00111100 +00011000 +00011000 +00011000 +00011000 +00011000 +00111100 +00000000 +00000000 +00000000 +11111000 +01101100 +01100110 +01100110 +11110110 +01100110 +01100110 +01101100 +11111000 +00000000 +00000000 +01110110 +11011100 +00000000 +11000110 +11100110 +11110110 +11011110 +11001110 +11000110 +11000110 +00000000 +00000000 +00110000 +00011000 +00000000 +01111100 +11000110 +11000110 +11000110 +11000110 +11000110 +01111100 +00000000 +00000000 +00011000 +00110000 +00000000 +01111100 +11000110 +11000110 +11000110 +11000110 +11000110 +01111100 +00000000 +00000000 +00111000 +01101100 +00000000 +01111100 +11000110 +11000110 +11000110 +11000110 +11000110 +01111100 +00000000 +00000000 +01110110 +11011100 +00000000 +01111100 +11000110 +11000110 +11000110 +11000110 +11000110 +01111100 +00000000 +00000000 +01101100 +01101100 +00000000 +01111100 +11000110 +11000110 +11000110 +11000110 +11000110 +01111100 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +01101100 +00111000 +00111000 +01101100 +00000000 +00000000 +00000000 +00000000 +00000000 +01111110 +11000110 +11001110 +11011110 +11010110 +11110110 +11100110 +11000110 +11111100 +00000000 +00000000 +00110000 +00011000 +00000000 +11000110 +11000110 +11000110 +11000110 +11000110 +11000110 +01111100 +00000000 +00000000 +00011000 +00110000 +00000000 +11000110 +11000110 +11000110 +11000110 +11000110 +11000110 +01111100 +00000000 +00000000 +00111000 +01101100 +00000000 +11000110 +11000110 +11000110 +11000110 +11000110 +11000110 +01111100 +00000000 +00000000 +01101100 +01101100 +00000000 +11000110 +11000110 +11000110 +11000110 +11000110 +11000110 +01111100 +00000000 +00000000 +00001100 +00011000 +00000000 +01100110 +01100110 +01100110 +00111100 +00011000 +00011000 +00111100 +00000000 +00000000 +00000000 +11110000 +01100000 +01111100 +01100110 +01100110 +01100110 +01111100 +01100000 +11110000 +00000000 +00000000 +00000000 +01111100 +11000110 +11000110 +11000110 +11001100 +11000110 +11000110 +11010110 +11011100 +10000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +10000010 +11111110 +00000000 +00000000 +00000000 +00000000 +00011000 +00011000 +00000000 +00011000 +00011000 +00111100 +00111100 +00111100 +00011000 +00000000 +00000000 +00010000 +01111100 +11010110 +11010000 +11010000 +11010110 +01111100 +00010000 +00000000 +00000000 +00000000 +00111000 +01101100 +01100000 +01100000 +11110000 +01100000 +01100110 +11110110 +01101100 +00000000 +00000000 +00000000 +00111100 +01100010 +01100000 +11111000 +01100000 +11111000 +01100000 +01100010 +00111100 +00000000 +00000000 +00000000 +01100110 +01100110 +00111100 +00011000 +01111110 +00011000 +00111100 +00011000 +00011000 +00000000 +00000000 +01101100 +00111000 +00000000 +01111100 +11000110 +11000000 +01111100 +00000110 +11000110 +01111100 +00000000 +00000000 +01111100 +11000110 +11000110 +01100000 +01111100 +11000110 +11000110 +01111100 +00001100 +11000110 +11000110 +01111100 +00000000 +01101100 +00111000 +00000000 +01111100 +11000110 +01110000 +00011100 +11000110 +01111100 +00000000 +00000000 +01111110 +10000001 +10011001 +10100101 +10100001 +10100001 +10100101 +10011001 +10000001 +01111110 +00000000 +00000000 +00111100 +01101100 +01101100 +00111110 +00000000 +01111110 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00110110 +01101100 +11011000 +01101100 +00110110 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +01111110 +00000110 +00000110 +00000110 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +01111110 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +01111110 +10000001 +10111001 +10100101 +10100101 +10111001 +10100101 +10100101 +10000001 +01111110 +00000000 +00000000 +11111111 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00111000 +01101100 +00111000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00011000 +00011000 +01111110 +00011000 +00011000 +00000000 +01111110 +00000000 +00000000 +00000000 +00111000 +01101100 +00011000 +00110000 +01111100 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00111000 +01101100 +00011000 +01101100 +00111000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +01101100 +00111000 +00000000 +11111110 +11000110 +00001100 +00111000 +01100010 +11000110 +11111110 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11001100 +11001100 +11001100 +11001100 +11001100 +11110110 +11000000 +11000000 +00000000 +01111111 +11011011 +11011011 +11011011 +01111011 +00011011 +00011011 +00011011 +00011011 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00011000 +00011000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +01101100 +00111000 +00000000 +11111110 +10001100 +00011000 +00110000 +01100010 +11111110 +00000000 +00000000 +00000000 +00110000 +01110000 +00110000 +00110000 +01111000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00111000 +01101100 +01101100 +00111000 +00000000 +01111100 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11011000 +01101100 +00110110 +01101100 +11011000 +00000000 +00000000 +00000000 +00000000 +00000000 +01101110 +11011011 +11011011 +11011111 +11011000 +11011000 +11011001 +11011111 +01101110 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +01101100 +11011010 +11011110 +11011000 +11011010 +01101100 +00000000 +00000000 +01100110 +01100110 +00000000 +01100110 +01100110 +00111100 +00011000 +00011000 +00011000 +00111100 +00000000 +00000000 +00000000 +00000000 +00000000 +00110000 +00110000 +00000000 +00110000 +00110000 +01100000 +11000110 +11000110 +01111100 +00000000 +00000000 +11111111 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00011111 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011111 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00000000 +00000000 +00000000 +00000000 +00000000 +00011111 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011111 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00000000 +00000000 +00000000 +00000000 +00000000 +11111000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00011000 +00011000 +00011000 +00011000 +00011000 +11111000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11111111 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00011000 +00011000 +00011000 +00011000 +00011000 +11111111 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11111000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +11111000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00000000 +00000000 +00000000 +00000000 +00000000 +11111111 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +11111111 +00011000 +00011000 +00011000 +00011000 +00011000 +00011000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11111111 +00000000 +00000000 +00000000 +00000000 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +01111100 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00111111 +00110000 +00111111 +00000000 +00000000 +00000000 +00000000 +00000000 +01101100 +01101100 +01101100 +01101100 +01101111 +01100000 +01111111 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +01111100 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +00000000 +00000000 +00000000 +00000000 +01111111 +01100000 +01101111 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +01101111 +01100000 +01101111 +01101100 +01101100 +01101100 +01101100 +01101100 +00000000 +00000000 +00000000 +00000000 +11111100 +00001100 +11111100 +00000000 +00000000 +00000000 +00000000 +00000000 +01101100 +01101100 +01101100 +01101100 +11101100 +00001100 +11111100 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11111111 +00000000 +11111111 +00000000 +00000000 +00000000 +00000000 +00000000 +01101100 +01101100 +01101100 +01101100 +11101111 +00000000 +11111111 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11111100 +00001100 +11101100 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +11101100 +00001100 +11101100 +01101100 +01101100 +01101100 +01101100 +01101100 +00000000 +00000000 +00000000 +00000000 +11111111 +00000000 +11101111 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +01101100 +11101111 +00000000 +11101111 +01101100 +01101100 +01101100 +01101100 +01101100 +01100000 +00110000 +00011000 +00000000 +01111000 +00001100 +01111100 +11001100 +11011100 +01110110 +00000000 +00000000 +00011000 +00110000 +01100000 +00000000 +01111000 +00001100 +01111100 +11001100 +11011100 +01110110 +00000000 +00000000 +00110000 +01111000 +11001100 +00000000 +01111000 +00001100 +01111100 +11001100 +11011100 +01110110 +00000000 +00000000 +00000000 +01110110 +11011100 +00000000 +01111000 +00001100 +01111100 +11001100 +11011100 +01110110 +00000000 +00000000 +00000000 +01101100 +01101100 +00000000 +01111000 +00001100 +01111100 +11001100 +11011100 +01110110 +00000000 +00000000 +00111000 +01101100 +00111000 +00000000 +01111000 +00001100 +01111100 +11001100 +11011100 +01110110 +00000000 +00000000 +00000000 +00000000 +00000000 +01111110 +11011011 +00011011 +01111111 +11011000 +11011011 +01111110 +00000000 +00000000 +00000000 +00000000 +00000000 +01111100 +11000110 +11000000 +11000000 +11000110 +01111100 +00011000 +01101100 +00111000 +00110000 +00011000 +00001100 +00000000 +01111100 +11000110 +11111110 +11000000 +11000110 +01111100 +00000000 +00000000 +00001100 +00011000 +00110000 +00000000 +01111100 +11000110 +11111110 +11000000 +11000110 +01111100 +00000000 +00000000 +00010000 +00111000 +01101100 +00000000 +01111100 +11000110 +11111110 +11000000 +11000110 +01111100 +00000000 +00000000 +00000000 +01101100 +01101100 +00000000 +01111100 +11000110 +11111110 +11000000 +11000110 +01111100 +00000000 +00000000 +01100000 +00110000 +00011000 +00000000 +00111000 +00011000 +00011000 +00011000 +00011000 +00111100 +00000000 +00000000 +00001100 +00011000 +00110000 +00000000 +00111000 +00011000 +00011000 +00011000 +00011000 +00111100 +00000000 +00000000 +00011000 +00111100 +01100110 +00000000 +00111000 +00011000 +00011000 +00011000 +00011000 +00111100 +00000000 +00000000 +00000000 +01101100 +01101100 +00000000 +00111000 +00011000 +00011000 +00011000 +00011000 +00111100 +00000000 +00000000 +01111000 +00110000 +01111000 +00001100 +01111110 +11000110 +11000110 +11000110 +11000110 +01111100 +00000000 +00000000 +00000000 +01110110 +11011100 +00000000 +11011100 +01100110 +01100110 +01100110 +01100110 +01100110 +00000000 +00000000 +01100000 +00110000 +00011000 +00000000 +01111100 +11000110 +11000110 +11000110 +11000110 +01111100 +00000000 +00000000 +00001100 +00011000 +00110000 +00000000 +01111100 +11000110 +11000110 +11000110 +11000110 +01111100 +00000000 +00000000 +00010000 +00111000 +01101100 +00000000 +01111100 +11000110 +11000110 +11000110 +11000110 +01111100 +00000000 +00000000 +00000000 +01110110 +11011100 +00000000 +01111100 +11000110 +11000110 +11000110 +11000110 +01111100 +00000000 +00000000 +00000000 +01101100 +01101100 +00000000 +01111100 +11000110 +11000110 +11000110 +11000110 +01111100 +00000000 +00000000 +00000000 +00000000 +00011000 +00011000 +00000000 +01111110 +00000000 +00011000 +00011000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +01111110 +11001110 +11011110 +11110110 +11100110 +11111100 +00000000 +00000000 +11000000 +01100000 +00110000 +00000000 +11001100 +11001100 +11001100 +11001100 +11001100 +01110110 +00000000 +00000000 +00001100 +00011000 +00110000 +00000000 +11001100 +11001100 +11001100 +11001100 +11001100 +01110110 +00000000 +00000000 +00110000 +01111000 +11001100 +00000000 +11001100 +11001100 +11001100 +11001100 +11001100 +01110110 +00000000 +00000000 +00000000 +11001100 +11001100 +00000000 +11001100 +11001100 +11001100 +11001100 +11001100 +01110110 +00000000 +00000000 +00001100 +00011000 +00110000 +00000000 +11000110 +11000110 +11000110 +11001110 +01110110 +00000110 +11000110 +01111100 +00000000 +11110000 +01100000 +01100000 +01111000 +01101100 +01101100 +01101100 +01111000 +01100000 +01100000 +11110000 +00000000 +11000110 +11000110 +00000000 +11000110 +11000110 +11000110 +11001110 +01110110 +00000110 +11000110 +01111100 Index: fat_32_file_parser/trunk/SDCard.vhd =================================================================== --- fat_32_file_parser/trunk/SDCard.vhd (nonexistent) +++ fat_32_file_parser/trunk/SDCard.vhd (revision 2) @@ -0,0 +1,656 @@ +--********************************************************************** +-- Copyright 2012 by XESS Corp . +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +--********************************************************************** + +--********************************************************************* +-- SD MEMORY CARD INTERFACE +-- +-- Reads/writes a single or multiple blocks of data to/from an SD Flash card. +-- +-- Based on work by by Steven J. Merrifield, June 2008: +-- http : //stevenmerrifield.com/tools/sd.vhd +-- +-- Most of what I learned about interfacing to SD/SDHC cards came from here: +-- http://elm-chan.org/docs/mmc/mmc_e.html +-- +-- OPERATION +-- +-- Set-up: +-- First of all, you have to give the controller a clock signal on the clk_i +-- input with a higher frequency than the serial clock sent to the SD card +-- through the sclk_o output. You can set generic parameters for the +-- controller to tell it the master clock frequency (100 MHz), the SCLK +-- frequency for initialization (400 KHz), the SCLK frequency for normal +-- operation (25 MHz), the size of data sectors in the Flash memory (512 bytes), +-- and the type of card (either SD or SDHC). I typically use a 100 MHz +-- clock if I'm running an SD card with a 25 Mbps serial data stream. +-- +-- Initialize it: +-- Pulsing the reset_i input high and then bringing it low again will make +-- the controller initialize the SD card so it will work in SPI mode. +-- Basically, it sends the card the commands CMD0, CMD8 and then ACMD41 (which +-- is CMD55 followed by CMD41). The busy_o output will be high during the +-- initialization and will go low once it is done. +-- +-- After the initialization command sequence, the SD card will send back an R1 +-- response byte. If only the IDLE bit of the R1 response is set, then the +-- controller will repeatedly re-try the ACMD41 command while busy_o remains +-- high. +-- +-- If any other bit of the R1 response is set, then an error occurred. The +-- controller will stall, lower busy_o, and output the R1 response code on the +-- error_o bus. You'll have to pulse reset_i to unfreeze the controller. +-- +-- If the R1 response is all zeroes (i.e., no errors occurred during the +-- initialization), then the controller will lower busy_o and wait for a +-- read or write operation from the host. The controller will only accept new +-- operations when busy_o is low. +-- +-- Write data: +-- To write a data block to the SD card, the address of a block is placed +-- on the addr_i input bus and the wr_i input is raised. The address and +-- write strobe can be removed once busy_o goes high to indicate the write +-- operation is underway. The data to be written to the SD card is passed as +-- follows: +-- +-- 1. The controller requests a byte of data by raising the hndShk_o output. +-- 2. The host applies the next byte to the data_i input bus and raises the +-- hndShk_i input. +-- 3. The controller accepts the byte and lowers the hndShk_o output. +-- 4. The host lowers the hndShk_i input. +-- +-- This sequence of steps is repeated until all BLOCK_SIZE_G bytes of the +-- data block are passed from the host to the controller. Once all the data +-- is passed, the sector on the SD card will be written and the busy_o output +-- will be lowered. +-- +-- Read data: +-- To read a block of data from the SD card, the address of a block is +-- placed on the addr_i input bus and the rd_i input is raised. The address +-- and read strobe can be removed once busy_o goes high to indicate the read +-- operation is underway. The data read from the SD card is passed to the +-- host as follows: +-- +-- 1. The controller raises the hndShk_o output when the next data byte is available. +-- 2. The host reads the byte from the data_o output bus and raises the hndShk_i input. +-- 3. The controller lowers the hndShk_o output. +-- 4. The host lowers the hndShk_i input. +-- +-- This sequence of steps is repeated until all BLOCK_SIZE_G bytes of the +-- data block are passed from the controller to the host. Once all the data +-- is read, the busy_o output will be lowered. +-- +-- Handle errors: +-- If an error is detected during either a read or write operation, then the +-- controller will stall, lower busy_o, and output an error code on the +-- error_o bus. You'll have to pulse reset_i to unfreeze the controller. That +-- may seem a bit excessive, but it does guarantee that you can't ignore any +-- errors that occur. +-- +-- TODO: +-- +-- * Implement multi-block read and write commands. +-- * Allow host to send/receive SPI commands/data directly to +-- the SD card through the controller. +-- ********************************************************************* + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.CommonPckg.all; + +package SdCardPckg is + + type CardType_t is (SD_CARD_E, SDHC_CARD_E); -- Define the different types of SD cards. + + component SdCardCtrl is + generic ( + FREQ_G : real := 100.0; -- Master clock frequency (MHz). + INIT_SPI_FREQ_G : real := 0.4; -- Slow SPI clock freq. during initialization (MHz). + SPI_FREQ_G : real := 25.0; -- Operational SPI freq. to the SD card (MHz). + BLOCK_SIZE_G : natural := 512; -- Number of bytes in an SD card block or sector. + CARD_TYPE_G : CardType_t := SD_CARD_E -- Type of SD card connected to this controller. + ); + port ( + -- Host-side interface signals. + clk_i : in std_logic; -- Master clock. + reset_i : in std_logic := '0'; -- active-high, synchronous reset. + rd_i : in std_logic := '0'; -- active-high read block request. + wr_i : in std_logic := '0'; -- active-high write block request. + continue_i : in std_logic := '0'; -- If true, inc address and continue R/W. + addr_i : in std_logic_vector(31 downto 0) := x"00000000"; -- Block address. + data_i : in std_logic_vector(7 downto 0) := x"00"; -- Data to write to block. + data_o : out std_logic_vector(7 downto 0) := x"00"; -- Data read from block. + busy_o : out std_logic; -- High when controller is busy performing some operation. + hndShk_i : in std_logic; -- High when host has data to give or has taken data. + hndShk_o : out std_logic; -- High when controller has taken data or has data to give. + error_o : out std_logic_vector(15 downto 0) := (others => '0'); + -- I/O signals to the external SD card. + cs_bo : out std_logic := '1'; -- Active-low chip-select. + sclk_o : out std_logic := '0'; -- Serial clock to SD card. + mosi_o : out std_logic := '1'; -- Serial data output to SD card. + miso_i : in std_logic := '0' -- Serial data input from SD card. + ); + end component; + +end package; + + + + +library ieee; +use ieee.math_real.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.CommonPckg.all; +use work.SdCardPckg.all; + +entity SdCardCtrl is + generic ( + FREQ_G : real := 100.0; -- Master clock frequency (MHz). + INIT_SPI_FREQ_G : real := 0.4; -- Slow SPI clock freq. during initialization (MHz). + SPI_FREQ_G : real := 25.0; -- Operational SPI freq. to the SD card (MHz). + BLOCK_SIZE_G : natural := 512; -- Number of bytes in an SD card block or sector. + CARD_TYPE_G : CardType_t := SD_CARD_E -- Type of SD card connected to this controller. + ); + port ( + -- Host-side interface signals. + clk_i : in std_logic; -- Master clock. + reset_i : in std_logic := '0'; -- active-high, synchronous reset. + rd_i : in std_logic := '0'; -- active-high read block request. + wr_i : in std_logic := '0'; -- active-high write block request. + continue_i : in std_logic := '0'; -- If true, inc address and continue R/W. + addr_i : in std_logic_vector(31 downto 0) := x"00000000"; -- Block address. + data_i : in std_logic_vector(7 downto 0) := x"00"; -- Data to write to block. + data_o : out std_logic_vector(7 downto 0) := x"00"; -- Data read from block. + busy_o : out std_logic; -- High when controller is busy performing some operation. + hndShk_i : in std_logic; -- High when host has data to give or has taken data. + hndShk_o : out std_logic; -- High when controller has taken data or has data to give. + error_o : out std_logic_vector(15 downto 0) := (others => '0'); + -- I/O signals to the external SD card. + cs_bo : out std_logic := '1'; -- Active-low chip-select. + sclk_o : out std_logic := '0'; -- Serial clock to SD card. + mosi_o : out std_logic := '1'; -- Serial data output to SD card. + miso_i : in std_logic := '0'; -- Serial data input from SD card. + state_debug_o : out std_logic_vector(4 downto 0) + ); +end entity; + + + +architecture arch of SdCardCtrl is + + signal sclk_r : std_logic := '0'; -- Register output drives SD card clock. + signal hndShk_r : std_logic := '0'; -- Register output drives handshake output to host. + + signal state_debug : unsigned(4 downto 0); + +begin + + state_debug_o <= std_logic_vector(state_debug); + + process(clk_i) -- FSM process for the SD card controller. + + type FsmState_t is ( -- States of the SD card controller FSM. + START_INIT, -- Send initialization clock pulses to the deselected SD card. + SEND_CMD0, -- Put the SD card in the IDLE state. + CHK_CMD0_RESPONSE, -- Check card's R1 response to the CMD0. + SEND_CMD8, -- This command is needed to initialize SDHC cards. + GET_CMD8_RESPONSE, -- Get the R7 response to CMD8. + SEND_CMD55, -- Send CMD55 to the SD card. + SEND_CMD41, -- Send CMD41 to the SD card. + CHK_ACMD41_RESPONSE, -- Check if the SD card has left the IDLE state. + WAIT_FOR_HOST_RW, -- Wait for the host to issue a read or write command. + RD_BLK, -- Read a block of data from the SD card. + WR_BLK, -- Write a block of data to the SD card. + WR_WAIT, -- Wait for SD card to finish writing the data block. + START_TX, -- Start sending command/data. + TX_BITS, -- Shift out remaining command/data bits. + GET_CMD_RESPONSE, -- Get the R1 response of the SD card to a command. + RX_BITS, -- Receive response/data from the SD card. + DESELECT, -- De-select the SD card and send some clock pulses (Must enter with sclk at zero.) + PULSE_SCLK, -- Issue some clock pulses. (Must enter with sclk at zero.) + REPORT_ERROR -- Report error and stall until reset. + ); + variable state_v : FsmState_t := START_INIT; -- Current state of the FSM. + variable rtnState_v : FsmState_t; -- State FSM returns to when FSM subroutine completes. + + -- Timing constants based on the master clock frequency and the SPI SCLK frequencies. + constant CLKS_PER_INIT_SCLK_C : real := FREQ_G / INIT_SPI_FREQ_G; + constant CLKS_PER_SCLK_C : real := FREQ_G / SPI_FREQ_G; + constant MAX_CLKS_PER_SCLK_C : real := realmax(CLKS_PER_INIT_SCLK_C, CLKS_PER_SCLK_C); + constant MAX_CLKS_PER_SCLK_PHASE_C : natural := integer(round(MAX_CLKS_PER_SCLK_C / 2.0)); + constant INIT_SCLK_PHASE_PERIOD_C : natural := integer(round(CLKS_PER_INIT_SCLK_C / 2.0)); + constant SCLK_PHASE_PERIOD_C : natural := integer(round(CLKS_PER_SCLK_C / 2.0)); + constant DELAY_BETWEEN_BLOCK_RW_C : natural := SCLK_PHASE_PERIOD_C; + + -- Registers for generating slow SPI SCLK from the faster master clock. + variable clkDivider_v : natural range 0 to MAX_CLKS_PER_SCLK_PHASE_C; -- Holds the SCLK period. + variable sclkPhaseTimer_v : natural range 0 to MAX_CLKS_PER_SCLK_PHASE_C; -- Counts down to zero, then SCLK toggles. + + constant NUM_INIT_CLKS_C : natural := 160; -- Number of initialization clocks to SD card. + variable bitCnt_v : natural range 0 to NUM_INIT_CLKS_C; -- Tx/Rx bit counter. + + constant CRC_SZ_C : natural := 2; -- Number of CRC bytes for read/write blocks. + -- When reading blocks of data, get 0xFE + [DATA_BLOCK] + [CRC]. + constant RD_BLK_SZ_C : natural := 1 + BLOCK_SIZE_G + CRC_SZ_C; + -- When writing blocks of data, send 0xFF + 0xFE + [DATA BLOCK] + [CRC] then receive response byte. + constant WR_BLK_SZ_C : natural := 1 + 1 + BLOCK_SIZE_G + CRC_SZ_C + 1; + variable byteCnt_v : natural range 0 to IntMax(WR_BLK_SZ_C, RD_BLK_SZ_C); -- Tx/Rx byte counter. + + -- Command bytes for various SD card operations. + subtype Cmd_t is std_logic_vector(7 downto 0); + constant CMD0_C : Cmd_t := std_logic_vector(to_unsigned(16#40# + 0, Cmd_t'length)); + constant CMD8_C : Cmd_t := std_logic_vector(to_unsigned(16#40# + 8, Cmd_t'length)); + constant CMD55_C : Cmd_t := std_logic_vector(to_unsigned(16#40# + 55, Cmd_t'length)); + constant CMD41_C : Cmd_t := std_logic_vector(to_unsigned(16#40# + 41, Cmd_t'length)); + constant READ_BLK_CMD_C : Cmd_t := std_logic_vector(to_unsigned(16#40# + 17, Cmd_t'length)); + constant WRITE_BLK_CMD_C : Cmd_t := std_logic_vector(to_unsigned(16#40# + 24, Cmd_t'length)); + + -- Except for CMD0 and CMD8, SD card ops don't need a CRC, so use a fake one for that slot in the command. + constant FAKE_CRC_C : std_logic_vector(7 downto 0) := x"FF"; + + variable addr_v : unsigned(addr_i'range); -- Address of current block for R/W operations. + + -- Maximum Tx to SD card consists of command + address + CRC. Data Tx is just a single byte. + variable tx_v : std_logic_vector(CMD0_C'length + addr_v'length + FAKE_CRC_C'length - 1 downto 0); -- Data/command to SD card. + alias txCmd_v is tx_v; -- Command transmission shift register. + alias txData_v is tx_v(tx_v'high downto tx_v'high - data_i'length + 1); -- Data byte transmission shift register. + + variable rx_v : std_logic_vector(data_i'range); -- Data/response byte received from SD card. + -- Various response codes. + subtype Response_t is std_logic_vector(rx_v'range); + constant ACTIVE_NO_ERRORS_C : Response_t := "00000000"; -- Normal R1 code after initialization. + constant IDLE_NO_ERRORS_C : Response_t := "00000001"; -- Normal R1 code after CMD0. + constant DATA_ACCEPTED_C : Response_t := "---00101"; -- SD card accepts data block from host. + constant DATA_REJ_CRC_C : Response_t := "---01011"; -- SD card rejects data block from host due to CRC error. + constant DATA_REJ_WERR_C : Response_t := "---01101"; -- SD card rejects data block from host due to write error. + -- Various tokens. + subtype Token_t is std_logic_vector(rx_v'range); + constant NO_TOKEN_C : Token_t := x"FF"; -- Received before the SD card responds to a block read command. + constant START_TOKEN_C : Token_t := x"FE"; -- Starting byte preceding a data block. + + -- Flags that are set/cleared to affect the operation of the FSM. + variable getCmdResponse_v : boolean; -- When true, get R1 response to command sent to SD card. + variable rtnData_v : boolean; -- When true, signal to host when a data byte arrives from SD card. + variable doDeselect_v : boolean; -- When true, de-select SD card after a command is issued. + + begin + + if rising_edge(clk_i) then + + case( state_v ) is + + when START_INIT => + state_debug <= to_unsigned(0, 5); + when SEND_CMD0 => + state_debug <= to_unsigned(1, 5); + when CHK_CMD0_RESPONSE => + state_debug <= to_unsigned(2, 5); + when SEND_CMD8 => + state_debug <= to_unsigned(3, 5); + when GET_CMD8_RESPONSE => + state_debug <= to_unsigned(4, 5); + when SEND_CMD55 => + state_debug <= to_unsigned(5, 5); + when SEND_CMD41 => + state_debug <= to_unsigned(6, 5); + when CHK_ACMD41_RESPONSE => + state_debug <= to_unsigned(7, 5); + when WAIT_FOR_HOST_RW => + state_debug <= to_unsigned(8, 5); + when RD_BLK => + state_debug <= to_unsigned(9, 5); + when WR_BLK => + state_debug <= to_unsigned(10, 5); + when WR_WAIT => + state_debug <= to_unsigned(11, 5); + when START_TX => + state_debug <= to_unsigned(12, 5); + when TX_BITS => + state_debug <= to_unsigned(13, 5); + when GET_CMD_RESPONSE => + state_debug <= to_unsigned(14, 5); + when RX_BITS => + state_debug <= to_unsigned(15, 5); + when DESELECT => + state_debug <= to_unsigned(16, 5); + when PULSE_SCLK => + state_debug <= to_unsigned(17, 5); + when REPORT_ERROR => + state_debug <= to_unsigned(18, 5); + + end case ; + + if reset_i = YES then -- Perform a reset. + state_v := START_INIT; -- Send the FSM to the initialization entry-point. + sclkPhaseTimer_v := 0; -- Don't delay the initialization right after reset. + busy_o <= YES; -- Busy while the SD card interface is being initialized. + + elsif sclkPhaseTimer_v /= 0 then + -- Setting the clock phase timer to a non-zero value delays any further actions + -- and generates the slower SPI clock from the faster master clock. + sclkPhaseTimer_v := sclkPhaseTimer_v - 1; + + -- Clock phase timer has reached zero, so check handshaking sync. between host and controller. + + -- Handshaking lets the host control the flow of data to/from the SD card controller. + -- Handshaking between the SD card controller and the host proceeds as follows: + -- 1: Controller raises its handshake and waits. + -- 2: Host sees controller handshake and raises its handshake in acknowledgement. + -- 3: Controller sees host handshake acknowledgement and lowers its handshake. + -- 4: Host sees controller lower its handshake and removes its handshake. + -- + -- Handshaking is bypassed when the controller FSM is initializing the SD card. + + elsif state_v /= START_INIT and hndShk_r = '1' and hndShk_i = '0' then + null; -- Waiting for the host to acknowledge handshake. + elsif state_v /= START_INIT and hndShk_r = '1' and hndShk_i = '1' then + txData_v := data_i; -- Get any data passed from the host. + hndShk_r <= '0'; -- The host acknowledged, so lower the controller handshake. + elsif state_v /= START_INIT and hndShk_r = '0' and hndShk_i = '1' then + null; -- Waiting for the host to lower its handshake. + elsif (state_v = START_INIT) or (hndShk_r = '0' and hndShk_i = '0') then + -- Both handshakes are low, so the controller operations can proceed. + + busy_o <= YES; -- Busy by default. Only false when waiting for R/W from host or stalled by error. + + case state_v is + + when START_INIT => -- Deselect the SD card and send it a bunch of clock pulses with MOSI high. + error_o <= (others => '0'); -- Clear error flags. + clkDivider_v := INIT_SCLK_PHASE_PERIOD_C - 1; -- Use slow SPI clock freq during init. + sclkPhaseTimer_v := INIT_SCLK_PHASE_PERIOD_C - 1; -- and set the duration of the next clock phase. + sclk_r <= '0'; -- Start with low clock to the SD card. + hndShk_r <= '0'; -- Initialize handshake signal. + addr_v := (others => '0'); -- Initialize address. + rtnData_v := false; -- No data is returned to host during initialization. + bitCnt_v := NUM_INIT_CLKS_C; -- Generate this many clock pulses. + state_v := DESELECT; -- De-select the SD card and pulse SCLK. + rtnState_v := SEND_CMD0; -- Then go to this state after the clock pulses are done. + + when SEND_CMD0 => -- Put the SD card in the IDLE state. + cs_bo <= '0'; -- Enable the SD card. + txCmd_v := CMD0_C & x"00000000" & x"95"; -- 0x95 is the correct CRC for this command. + bitCnt_v := txCmd_v'length; -- Set bit counter to the size of the command. + getCmdResponse_v := true; -- Sending a command that generates a response. + doDeselect_v := true; -- De-select SD card after this command finishes. + state_v := START_TX; -- Go to FSM subroutine to send the command. + rtnState_v := CHK_CMD0_RESPONSE; -- Then check the response to the command. + + when CHK_CMD0_RESPONSE => -- Check card's R1 response to the CMD0. + if rx_v = IDLE_NO_ERRORS_C then + state_v := SEND_CMD8; -- Continue init if SD card is in IDLE state with no errors + else + state_v := SEND_CMD0; -- Otherwise, try CMD0 again. + end if; + + when SEND_CMD8 => -- This command is needed to initialize SDHC cards. + cs_bo <= '0'; -- Enable the SD card. + txCmd_v := CMD8_C & x"000001aa" & x"87"; -- 0x87 is the correct CRC for this command. + bitCnt_v := txCmd_v'length; -- Set bit counter to the size of the command. + getCmdResponse_v := true; -- Sending a command that generates a response. + doDeselect_v := false; -- Don't de-select, need to get the R7 response sent from the SD card. + state_v := START_TX; -- Go to FSM subroutine to send the command. + rtnState_v := GET_CMD8_RESPONSE; -- Then go to this state after the command is sent. + + when GET_CMD8_RESPONSE => -- Get the R7 response to CMD8. + cs_bo <= '0'; -- The SD card should already be enabled, but let's be explicit. + bitCnt_v := 31; -- Four bytes (32 bits) in R7 response. + getCmdResponse_v := false; -- Not sending a command that generates a response. + doDeselect_v := true; -- De-select card to end the command after getting the four bytes. + state_v := RX_BITS; -- Go to FSM subroutine to get the R7 response. + rtnState_v := SEND_CMD55; -- Then go here (we don't care what the actual R7 response is). + + when SEND_CMD55 => -- Send CMD55 as preamble of ACMD41 initialization command. + cs_bo <= '0'; -- Enable the SD card. + txCmd_v := CMD55_C & x"00000000" & FAKE_CRC_C; + bitCnt_v := txCmd_v'length; -- Set bit counter to the size of the command. + getCmdResponse_v := true; -- Sending a command that generates a response. + doDeselect_v := true; -- De-select SD card after this command finishes. + state_v := START_TX; -- Go to FSM subroutine to send the command. + rtnState_v := SEND_CMD41; -- Then go to this state after the command is sent. + + when SEND_CMD41 => -- Send the SD card the initialization command. + cs_bo <= '0'; -- Enable the SD card. + txCmd_v := CMD41_C & x"40000000" & FAKE_CRC_C; + bitCnt_v := txCmd_v'length; -- Set bit counter to the size of the command. + getCmdResponse_v := true; -- Sending a command that generates a response. + doDeselect_v := true; -- De-select SD card after this command finishes. + state_v := START_TX; -- Go to FSM subroutine to send the command. + rtnState_v := CHK_ACMD41_RESPONSE; -- Then check the response to the command. + + when CHK_ACMD41_RESPONSE => + -- The CMD55, CMD41 sequence should cause the SD card to leave the IDLE state + -- and become ready for SPI read/write operations. If still IDLE, then repeat the CMD55, CMD41 sequence. + -- If one of the R1 error flags is set, then report the error and stall. + if rx_v = ACTIVE_NO_ERRORS_C then -- Not IDLE, no errors. + state_v := WAIT_FOR_HOST_RW; -- Start processing R/W commands from the host. + elsif rx_v = IDLE_NO_ERRORS_C then -- Still IDLE but no errors. + state_v := SEND_CMD55; -- Repeat the CMD55, CMD41 sequence. + else -- Some error occurred. + state_v := REPORT_ERROR; -- Report the error and stall. + end if; + + when WAIT_FOR_HOST_RW => -- Wait for the host to read or write a block of data from the SD card. + clkDivider_v := SCLK_PHASE_PERIOD_C - 1; -- Set SPI clock frequency for normal operation. + getCmdResponse_v := true; -- Get R1 response to any commands issued to the SD card. + if rd_i = YES then -- send READ command and address to the SD card. + cs_bo <= '0'; -- Enable the SD card. + if continue_i = YES then -- Multi-block read. Use stored address. + if CARD_TYPE_G = SD_CARD_E then -- SD cards use byte-addressing, + addr_v := addr_v + BLOCK_SIZE_G; -- so add block-size to get next block address. + else -- SDHC cards use block-addressing, + addr_v := addr_v + 1; -- so just increment current block address. + end if; + txCmd_v := READ_BLK_CMD_C & std_logic_vector(addr_v) & FAKE_CRC_C; + else -- Single-block read. + txCmd_v := READ_BLK_CMD_C & addr_i & FAKE_CRC_C; -- Use address supplied by host. + addr_v := unsigned(addr_i); -- Store address for multi-block operations. + end if; + bitCnt_v := txCmd_v'length; -- Set bit counter to the size of the command. + byteCnt_v := RD_BLK_SZ_C; + state_v := START_TX; -- Go to FSM subroutine to send the command. + rtnState_v := RD_BLK; -- Then go to this state to read the data block. + elsif wr_i = YES then -- send WRITE command and address to the SD card. + cs_bo <= '0'; -- Enable the SD card. + if continue_i = YES then -- Multi-block write. Use stored address. + if CARD_TYPE_G = SD_CARD_E then -- SD cards use byte-addressing, + addr_v := addr_v + BLOCK_SIZE_G; -- so add block-size to get next block address. + else -- SDHC cards use block-addressing, + addr_v := addr_v + 1; -- so just increment current block address. + end if; + txCmd_v := WRITE_BLK_CMD_C & std_logic_vector(addr_v) & FAKE_CRC_C; + else -- Single-block write. + txCmd_v := WRITE_BLK_CMD_C & addr_i & FAKE_CRC_C; -- Use address supplied by host. + addr_v := unsigned(addr_i); -- Store address for multi-block operations. + end if; + bitCnt_v := txCmd_v'length; -- Set bit counter to the size of the command. + byteCnt_v := WR_BLK_SZ_C; -- Set number of bytes to write. + state_v := START_TX; -- Go to this FSM subroutine to send the command ... + rtnState_v := WR_BLK; -- then go to this state to write the data block. + else -- Do nothing and wait for command from host. + cs_bo <= '1'; -- Deselect the SD card. + busy_o <= '0'; -- SD card interface is waiting for R/W from host, so it's not busy. + state_v := WAIT_FOR_HOST_RW; -- Keep waiting for command from host. + end if; + + when RD_BLK => -- Read a block of data from the SD card. + -- Some default values for these... + rtnData_v := false; -- Data is only returned to host in one place. + bitCnt_v := rx_v'length - 1; -- Receiving byte-sized data. + state_v := RX_BITS; -- Call the bit receiver routine. + rtnState_v := RD_BLK; -- Return here when done receiving a byte. + if byteCnt_v = RD_BLK_SZ_C then -- Initial read to prime the pump. + byteCnt_v := byteCnt_v - 1; + elsif byteCnt_v = RD_BLK_SZ_C -1 then -- Then look for the data block start token. + if rx_v = NO_TOKEN_C then -- Receiving 0xFF means the card hasn't responded yet. Keep trying. + null; + elsif rx_v = START_TOKEN_C then + rtnData_v := true; -- Found the start token, so now start returning data byes to the host. + byteCnt_v := byteCnt_v - 1; + else -- Getting anything else means something strange has happened. + state_v := REPORT_ERROR; + end if; + elsif byteCnt_v >= 3 then -- Now bytes of data from the SD card are received. + rtnData_v := true; -- Return this data to the host. + byteCnt_v := byteCnt_v - 1; + elsif byteCnt_v = 2 then -- Receive the 1st CRC byte at the end of the data block. + byteCnt_v := byteCnt_v - 1; + elsif byteCnt_v = 1 then -- Receive the 2nd + byteCnt_v := byteCnt_v - 1; + else -- Reading is done, so deselect the SD card. + sclk_r <= '0'; + bitCnt_v := 2; + state_v := DESELECT; + rtnState_v := WAIT_FOR_HOST_RW; + end if; + + when WR_BLK => -- Write a block of data to the SD card. + -- Some default values for these... + getCmdResponse_v := false; -- Sending data bytes so there's no command response from SD card. + bitCnt_v := txData_v'length; -- Transmitting byte-sized data. + state_v := START_TX; -- Call the bit transmitter routine. + rtnState_v := WR_BLK; -- Return here when done transmitting a byte. + if byteCnt_v = WR_BLK_SZ_C then + txData_v := NO_TOKEN_C; -- Hold MOSI high for one byte before data block goes out. + elsif byteCnt_v = WR_BLK_SZ_C - 1 then -- Send start token. + txData_v := START_TOKEN_C; -- Starting token for data block. + elsif byteCnt_v >= 4 then -- Now send bytes in the data block. + hndShk_r <= '1'; -- Signal host to provide data. + -- The transmit shift register is loaded with data from host in the handshaking section above. + elsif byteCnt_v = 3 or byteCnt_v = 2 then -- Send two phony CRC bytes at end of packet. + txData_v := FAKE_CRC_C; + elsif byteCnt_v = 1 then + bitCnt_v := rx_v'length - 1; + state_v := RX_BITS; -- Get response of SD card to the write operation. + rtnState_v := WR_WAIT; + else -- Check received response byte. + if std_match(rx_v, DATA_ACCEPTED_C) then -- Data block was accepted. + state_v := WR_WAIT; -- Wait for the SD card to finish writing the data into Flash. + else -- Data block was rejected. + error_o(15 downto 8) <= rx_v; + state_v := REPORT_ERROR; -- Report the error. + end if; + end if; + byteCnt_v := byteCnt_v - 1; + + when WR_WAIT => -- Wait for SD card to finish writing the data block. + -- The SD card will pull MISO low while it is busy, and raise it when it is done. + sclk_r <= not sclk_r; -- Toggle the SPI clock... + sclkPhaseTimer_v := clkDivider_v; -- and set the duration of the next clock phase. + if sclk_r = '1' and miso_i = '1' then -- Data block has been written, so deselect the SD card. + bitCnt_v := 2; + state_v := DESELECT; + rtnState_v := WAIT_FOR_HOST_RW; + end if; + + when START_TX => + -- Start sending command/data by lowering SCLK and outputing MSB of command/data + -- so it has plenty of setup before the rising edge of SCLK. + sclk_r <= '0'; -- Lower the SCLK (although it should already be low). + sclkPhaseTimer_v := clkDivider_v; -- Set the duration of the low SCLK. + mosi_o <= tx_v(tx_v'high); -- Output MSB of command/data. + tx_v := tx_v(tx_v'high-1 downto 0) & ONE; -- Shift command/data register by one bit. + bitCnt_v := bitCnt_v - 1; -- The first bit has been sent, so decrement bit counter. + state_v := TX_BITS; -- Go here to shift out the rest of the command/data bits. + + when TX_BITS => -- Shift out remaining command/data bits and (possibly) get response from SD card. + sclk_r <= not sclk_r; -- Toggle the SPI clock... + sclkPhaseTimer_v := clkDivider_v; -- and set the duration of the next clock phase. + if sclk_r = '1' then + -- SCLK is going to be flipped from high to low, so output the next command/data bit + -- so it can setup while SCLK is low. + if bitCnt_v /= 0 then -- Keep sending bits until the bit counter hits zero. + mosi_o <= tx_v(tx_v'high); + tx_v := tx_v(tx_v'high-1 downto 0) & ONE; + bitCnt_v := bitCnt_v - 1; + else + if getCmdResponse_v then + state_v := GET_CMD_RESPONSE; -- Get a response to the command from the SD card. + bitCnt_v := Response_t'length - 1; -- Length of the expected response. + else + state_v := rtnState_v; -- Return to calling state (no need to get a response). + sclkPhaseTimer_v := 0; -- Clear timer so next SPI op can begin ASAP with SCLK low. + end if; + end if; + end if; + + when GET_CMD_RESPONSE => -- Get the response of the SD card to a command. + if sclk_r = '1' and miso_i = '0' then -- MISO will be held high by SD card until 1st bit of R1 response, which is 0. + -- Shift in the MSB bit of the response. + rx_v := rx_v(rx_v'high-1 downto 0) & miso_i; + bitCnt_v := bitCnt_v - 1; + state_v := RX_BITS; -- Now receive the reset of the response. + end if; + sclk_r <= not sclk_r; -- Toggle the SPI clock... + sclkPhaseTimer_v := clkDivider_v; -- and set the duration of the next clock phase. + + when RX_BITS => -- Receive bits from the SD card. + if sclk_r = '1' then -- Bits enter after the rising edge of SCLK. + rx_v := rx_v(rx_v'high-1 downto 0) & miso_i; + if bitCnt_v /= 0 then -- More bits left to receive. + bitCnt_v := bitCnt_v - 1; + else -- Last bit has been received. + if rtnData_v then -- Send the received data to the host. + data_o <= rx_v; -- Output received data to the host. + hndShk_r <= '1'; -- Signal to the host that the data is ready. + end if; + if doDeselect_v then + bitCnt_v := 1; + state_v := DESELECT; -- De-select SD card before returning. + else + state_v := rtnState_v; -- Otherwise, return to calling state without de-selecting. + end if; + end if; + end if; + sclk_r <= not sclk_r; -- Toggle the SPI clock... + sclkPhaseTimer_v := clkDivider_v; -- and set the duration of the next clock phase. + + when DESELECT => -- De-select the SD card and send some clock pulses (Must enter with sclk at zero.) + doDeselect_v := false; -- Once the de-select is done, clear the flag that caused it. + cs_bo <= '1'; -- De-select the SD card. + mosi_o <= '1'; -- Keep the data input of the SD card pulled high. + state_v := PULSE_SCLK; -- Pulse the clock so the SD card will see the de-select. + sclk_r <= '0'; -- Clock is set low so the next rising edge will see the new CS and MOSI + sclkPhaseTimer_v := clkDivider_v; -- Set the duration of the next clock phase. + + when PULSE_SCLK => -- Issue some clock pulses. (Must enter with sclk at zero.) + if sclk_r = '1' then + if bitCnt_v /= 0 then + bitCnt_v := bitCnt_v - 1; + else -- Return to the calling routine when the pulse counter reaches zero. + state_v := rtnState_v; + end if; + end if; + sclk_r <= not sclk_r; -- Toggle the SPI clock... + sclkPhaseTimer_v := clkDivider_v; -- and set the duration of the next clock phase. + + when REPORT_ERROR => -- Report the error code and stall here until a reset occurs. + error_o(rx_v'range) <= rx_v; -- Output the SD card response as the error code. + busy_o <= '0'; -- Not busy. + + when others => + state_v := START_INIT; + end case; + end if; + end if; + end process; + + sclk_o <= sclk_r; -- Output the generated SPI clock for the SD card. + hndShk_o <= hndShk_r; -- Output the generated handshake to the host. + +end architecture; Index: fat_32_file_parser/trunk/sseg.vhd =================================================================== --- fat_32_file_parser/trunk/sseg.vhd (nonexistent) +++ fat_32_file_parser/trunk/sseg.vhd (revision 2) @@ -0,0 +1,98 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity sseg is + Port ( + CLK : in STD_LOGIC; + + VAL_IN : in STD_LOGIC_VECTOR (15 downto 0); + + SSEG_OUT : out STD_LOGIC_VECTOR(7 downto 0); + AN_OUT : out STD_LOGIC_VECTOR(3 downto 0)); + +end sseg; + +architecture Behavioral of sseg is + +constant C_clk_div_400hz : std_logic_vector(19 downto 0) := X"1E847"; + +signal clk_div_counter : std_logic_vector(19 downto 0) := (others => '0'); +signal clk_400hz : std_logic := '0'; +signal digit_pattern_array : std_logic_vector(7 downto 0) := "00000000"; +signal current_segment : std_logic_vector(1 downto 0) := "00"; +signal cathode_select : std_logic_vector(3 downto 0) := "0000"; +signal current_digit : std_logic_vector(3 downto 0) := "0000"; + +begin + + SSEG_OUT <= digit_pattern_array; + AN_OUT <= cathode_select; + + -- Slows up CLK from 50MHz to MUX_CLK 400Hz. + process(CLK) + begin + if rising_edge(CLK) then + if clk_div_counter = C_clk_div_400hz then + clk_div_counter <= (others => '0'); + clk_400hz <= '1'; + else + clk_div_counter <= clk_div_counter + 1; + clk_400hz <= '0'; + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + case current_digit is + when "0000" => digit_pattern_array <= "00000011"; + when "0001" => digit_pattern_array <= "10011111"; + when "0010" => digit_pattern_array <= "00100101"; + when "0011" => digit_pattern_array <= "00001101"; + when "0100" => digit_pattern_array <= "10011001"; + when "0101" => digit_pattern_array <= "01001001"; + when "0110" => digit_pattern_array <= "01000001"; + when "0111" => digit_pattern_array <= "00011111"; + when "1000" => digit_pattern_array <= "00000001"; + when "1001" => digit_pattern_array <= "00011001"; + when "1010" => digit_pattern_array <= "00010001"; + when "1011" => digit_pattern_array <= "11000001"; + when "1100" => digit_pattern_array <= "01100011"; + when "1101" => digit_pattern_array <= "10000101"; + when "1110" => digit_pattern_array <= "01100001"; + when "1111" => digit_pattern_array <= "01110001"; + when others => null; + end case; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if clk_400hz = '1' then + current_segment <= current_segment + 1; + + case current_segment is + when "00" => + cathode_select <= "1110"; + current_digit <= VAL_IN(3 downto 0); + when "01" => + cathode_select <= "1101"; + current_digit <= VAL_IN(7 downto 4); + when "10" => + cathode_select <= "1011"; + current_digit <= VAL_IN(11 downto 8); + when "11" => + cathode_select <= "0111"; + current_digit <= VAL_IN(15 downto 12); + when others => null; + end case; + end if; + end if; + end process; + +end Behavioral; + Index: fat_32_file_parser/trunk/ClkGen.vhd =================================================================== --- fat_32_file_parser/trunk/ClkGen.vhd (nonexistent) +++ fat_32_file_parser/trunk/ClkGen.vhd (revision 2) @@ -0,0 +1,158 @@ +---------------------------------------------------------------------------------- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License +-- as published by the Free Software Foundation; either version 2 +-- of the License, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA +-- 02111-1307, USA. +-- +-- �2011 - X Engineering Software Systems Corp. (www.xess.com) +---------------------------------------------------------------------------------- + +---------------------------------------------------------------------------------- +-- Modules for generating a clock frequency from a master clock and for transferring +-- a clock signal from the clock network to a logic input or an output pin. +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +package ClkGenPckg is + + --********************************************************************** + -- Generate a clock frequency from a master clock. + --********************************************************************** + component ClkGen is + generic ( + BASE_FREQ_G : real := 12.0; -- Input frequency in MHz. + CLK_MUL_G : natural range 1 to 32 := 25; -- Frequency multiplier. + CLK_DIV_G : natural range 1 to 32 := 3 -- Frequency divider. + ); + port ( + i : in std_logic; -- Clock input (12 MHz by default). + o : out std_logic; -- Generated clock output (100 MHz by default). + o_b : out std_logic; -- Negative-phase generated clock output (inverse of 'o' output). + clkToLogic_o : out std_logic -- Clock signal that can go to an output pin or logic-gate input. + ); + end component; + + --********************************************************************** + -- Send a clock signal to an output pin or some logic that's not + -- on an FPGA clock network. + --********************************************************************** + component ClkToLogic is + port ( + clk_i : in std_logic; -- Positive-phase of clock input. + clk_ib : in std_logic; -- Negative-phase of clock input. + clk_o : out std_logic -- Clock output that's suitable as a logic input. + ); + end component; + +end package; + + +library IEEE, UNISIM; +use IEEE.STD_LOGIC_1164.all; +use work.CommonPckg.all; +use work.ClkGenPckg.all; +use UNISIM.VComponents.all; + +--********************************************************************** +-- Generate a clock frequency from a master clock. +--********************************************************************** +entity ClkGen is + generic ( + BASE_FREQ_G : real := 12.0; -- Input frequency in MHz. + CLK_MUL_G : natural range 1 to 32 := 25; -- Frequency multiplier. + CLK_DIV_G : natural range 1 to 32 := 3 -- Frequency divider. + ); + port ( + i : in std_logic; -- Clock input (12 MHz by default). + o : out std_logic; -- Generated clock output (100 MHz by default). + o_b : out std_logic; -- Negative-phase generated clock output (inverse of 'o' output). + clkToLogic_o : out std_logic -- Clock signal that can go to an output pin or logic-gate input. + ); +end entity; + +architecture arch of ClkGen is + signal genClkP_s : std_logic; -- Positive phase of generated clock. + signal genClkN_s : std_logic; -- Negative phase of generated clock. +begin + + u0 : DCM_SP + generic map ( + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => CLK_DIV_G, -- Can be any interger from 1 to 32 + CLKFX_MULTIPLY => CLK_MUL_G, -- Can be any integer from 1 to 32 + CLKIN_DIVIDE_BY_2 => false, -- TRUE/FALSE to enable CLKIN divide by two feature + CLKIN_PERIOD => 1000.0 / BASE_FREQ_G, -- Specify period of input clock in ns + CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE + CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE, 1X or 2X + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL + DUTY_CYCLE_CORRECTION => true, -- Duty cycle correction, TRUE or FALSE + PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 + STARTUP_WAIT => false) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE + port map ( + RST => '0', -- DCM asynchronous reset input + CLKIN => i, -- Clock input (from IBUFG, BUFG or DCM) + CLKFX => genClkP_s, -- Positive-phase of generated clock output + CLKFX180 => genClkN_s -- Negative-phase of generated clock output. + ); + + o <= genClkP_s; + o_b <= genClkN_s; + + -- Create a clock signal that can go to an output pin or to a logic-gate input. + u1 : ClkToLogic + port map ( + clk_i => genClkP_s, + clk_ib => genClkN_s, + clk_o => clkToLogic_o + ); +end architecture; + + +library IEEE, UNISIM; +use IEEE.STD_LOGIC_1164.all; +use work.CommonPckg.all; +use UNISIM.VComponents.all; + +--********************************************************************** +-- Send a clock signal to an output pin or some logic that's not +-- on an FPGA clock network. +--********************************************************************** +entity ClkToLogic is + port ( + clk_i : in std_logic; -- Positive-phase of clock input. + clk_ib : in std_logic; -- Negative-phase of clock input. + clk_o : out std_logic -- Clock output that's suitable as a logic input. + ); +end entity; + +architecture arch of ClkToLogic is +begin + -- Use ODDR2 to transfer clock signal from FPGA's clock network to the logic fabric. + -- (This stops the synthesis tools from complaining about using a clock as an input + -- to a logic gate or when driving a pin for an external clock signal.) + u1 : ODDR2 + port map ( + Q => clk_o, + C0 => clk_i, + C1 => clk_ib, + CE => YES, + D0 => ONE, + D1 => ZERO, + R => ZERO, + S => ZERO + ); +end architecture; Index: fat_32_file_parser/trunk/hw_client.xise =================================================================== --- fat_32_file_parser/trunk/hw_client.xise (nonexistent) +++ fat_32_file_parser/trunk/hw_client.xise (revision 2) @@ -0,0 +1,394 @@ + + + +

+ + + + + + + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: fat_32_file_parser/trunk/FONT_MEM.vhd =================================================================== --- fat_32_file_parser/trunk/FONT_MEM.vhd (nonexistent) +++ fat_32_file_parser/trunk/FONT_MEM.vhd (revision 2) @@ -0,0 +1,141 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used solely -- +-- for design, simulation, implementation and creation of design files -- +-- limited to Xilinx devices or technologies. Use with non-Xilinx -- +-- devices or technologies is expressly prohibited and immediately -- +-- terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- +-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- +-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- +-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- +-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- +-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- +-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- +-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- +-- PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support appliances, -- +-- devices, or systems. Use in such applications are expressly -- +-- prohibited. -- +-- -- +-- (c) Copyright 1995-2014 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file FONT_MEM.vhd when simulating +-- the core, FONT_MEM. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; +-- synthesis translate_on +ENTITY FONT_MEM IS + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END FONT_MEM; + +ARCHITECTURE FONT_MEM_a OF FONT_MEM IS +-- synthesis translate_off +COMPONENT wrapped_FONT_MEM + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END COMPONENT; + +-- Configuration specification + FOR ALL : wrapped_FONT_MEM USE ENTITY XilinxCoreLib.blk_mem_gen_v7_2(behavioral) + GENERIC MAP ( + c_addra_width => 12, + c_addrb_width => 12, + c_algorithm => 1, + c_axi_id_width => 4, + c_axi_slave_type => 0, + c_axi_type => 1, + c_byte_size => 9, + c_common_clk => 0, + c_default_data => "0", + c_disable_warn_bhv_coll => 0, + c_disable_warn_bhv_range => 0, + c_enable_32bit_address => 0, + c_family => "spartan3", + c_has_axi_id => 0, + c_has_ena => 0, + c_has_enb => 0, + c_has_injecterr => 0, + c_has_mem_output_regs_a => 0, + c_has_mem_output_regs_b => 0, + c_has_mux_output_regs_a => 0, + c_has_mux_output_regs_b => 0, + c_has_regcea => 0, + c_has_regceb => 0, + c_has_rsta => 0, + c_has_rstb => 0, + c_has_softecc_input_regs_a => 0, + c_has_softecc_output_regs_b => 0, + c_init_file_name => "FONT_MEM.mif", + c_inita_val => "0", + c_initb_val => "0", + c_interface_type => 0, + c_load_init_file => 1, + c_mem_type => 0, + c_mux_pipeline_stages => 0, + c_prim_type => 1, + c_read_depth_a => 4096, + c_read_depth_b => 4096, + c_read_width_a => 8, + c_read_width_b => 8, + c_rst_priority_a => "CE", + c_rst_priority_b => "CE", + c_rst_type => "SYNC", + c_rstram_a => 0, + c_rstram_b => 0, + c_sim_collision_check => "ALL", + c_use_byte_wea => 0, + c_use_byte_web => 0, + c_use_default_data => 1, + c_use_ecc => 0, + c_use_softecc => 0, + c_wea_width => 1, + c_web_width => 1, + c_write_depth_a => 4096, + c_write_depth_b => 4096, + c_write_mode_a => "WRITE_FIRST", + c_write_mode_b => "WRITE_FIRST", + c_write_width_a => 8, + c_write_width_b => 8, + c_xdevicefamily => "spartan3e" + ); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_FONT_MEM + PORT MAP ( + clka => clka, + wea => wea, + addra => addra, + dina => dina, + douta => douta + ); +-- synthesis translate_on + +END FONT_MEM_a; Index: fat_32_file_parser/trunk/ctrm.vhd =================================================================== --- fat_32_file_parser/trunk/ctrm.vhd (nonexistent) +++ fat_32_file_parser/trunk/ctrm.vhd (revision 2) @@ -0,0 +1,64 @@ +-- Hi Emacs, this is -*- mode: vhdl; -*- +---------------------------------------------------------------------------------------------------- +-- +-- Up Syncronous counter of N bits with a/syncronous reset +-- +-- Copyright (c) 2007 Javier Valcarce Garc�a, javier.valcarce@gmail.com +-- $Id$ +-- +---------------------------------------------------------------------------------------------------- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU Lesser General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. + +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU Lesser General Public License for more details. +-- +-- You should have received a copy of the GNU Lesser General Public License +-- along with this program. If not, see . +---------------------------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity ctrm is + generic ( + M : integer := 08); + port ( + reset : in std_logic; -- asyncronous reset + clk : in std_logic; + ce : in std_logic; -- enable counting + rs : in std_logic; -- syncronous reset + do : out integer range (M-1) downto 0 + ); +end ctrm; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +architecture arch of ctrm is + signal c : integer range (M-1) downto 0; +begin + + do <= c; + + process(reset, clk) + begin + if reset = '1' then + c <= 0; + + elsif rising_edge(clk) then + if ce = '1' then + if rs = '1' then + c <= 0; + else + c <= c + 1; + end if; + end if; + end if; + end process; + +end arch; Index: fat_32_file_parser/trunk/Nexys2_500General.ucf =================================================================== --- fat_32_file_parser/trunk/Nexys2_500General.ucf (nonexistent) +++ fat_32_file_parser/trunk/Nexys2_500General.ucf (revision 2) @@ -0,0 +1,246 @@ +## This file is a general .ucf for Nexys2 rev A board +## To use it in a project: +## - remove or comment the lines corresponding to unused pins +## - rename the used signals according to the project + +## Signals Led<7>Led<4> are assigned to pins which change type from s3e500 to other dies using the same package +## Both versions are provided in this file. +## Keep only the appropriate one, and remove or comment the other one. + +## Clock pin for Nexys 2 Board +NET "CLK_IN" LOC = "B8"; # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0 +TIMESPEC ts_clk = PERIOD "CLK_IN" 20 ns HIGH 50 %; + +#NET "clk1" LOC = "U9"; # Bank = 2, Pin name = IO_L13P_2/D4/GCLK14, Type = DUAL/GCLK, Sch name = GCLK1 + +## onBoard USB controller +## NOTE: DEPP and DSTM net names use some of the same pins, if trying to use both DEPP and DSTM use a signle net name for each shared pin. + +## Data bus for both the DEPP and DSTM interfaces uncomment lines 20-27 if using either one +#NET "DB<0>" LOC = "R14"; # Bank = 2, Pin name = IO_L24N_2/A20, Type = DUAL, Sch name = U-FD0 +#NET "DB<1>" LOC = "R13"; # Bank = 2, Pin name = IO_L22N_2/A22, Type = DUAL, Sch name = U-FD1 +#NET "DB<2>" LOC = "P13"; # Bank = 2, Pin name = IO_L22P_2/A23, Type = DUAL, Sch name = U-FD2 +#NET "DB<3>" LOC = "T12"; # Bank = 2, Pin name = IO_L20P_2, Type = I/O, Sch name = U-FD3 +#NET "DB<4>" LOC = "N11"; # Bank = 2, Pin name = IO_L18N_2, Type = I/O, Sch name = U-FD4 +#NET "DB<5>" LOC = "R11"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = U-FD5 +#NET "DB<6>" LOC = "P10"; # Bank = 2, Pin name = IO_L15N_2/D1/GCLK3, Type = DUAL/GCLK, Sch name = U-FD6 +#NET "DB<7>" LOC = "R10"; # Bank = 2, Pin name = IO_L15P_2/D2/GCLK2, Type = DUAL/GCLK, Sch name = U-FD7 + +## If using the DEPP interface uncomment lines 30-33 +#NET "EppWRITE" LOC = "V16"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-FLAGC +#NET "EppASTB" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA +#NET "EppDSTB" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB +#NET "EppWAIT" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD + +## If using the DSTM interface uncomment lines 36-45 +#NET "DstmIFCLK" LOC = "T15"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = U-IFCLK +#NET "DstmSLCS" LOC = "T16"; # Bank = 2, Pin name = IO_L26P_2/VS0/A17, Type = DUAL, Sch name = U-SLCS +#NET "DstmFLAGA" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA +#NET "DstmFLAGB" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB +#NET "DstmADR<0>" LOC = "T14"; # Bank = 2, Pin name = IO_L24P_2/A21, Type = DUAL, Sch name = U-FIFOAD0 +#NET "DstmADR<1>" LOC = "V13"; # Bank = 2, Pin name = IO_L19N_2/VREF_2, Type = VREF, Sch name = U-FIFOAD1 +#NET "DstmSLRD" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD +#NET "DstmSLWR" LOC = "V9"; # Bank = 2, Pin name = IO_L13N_2/D3/GCLK15, Type = DUAL/GCLK, Sch name = U-SLWR +#NET "DstmSLOE" LOC = "V15"; # Bank = 2, Pin name = IO_L25P_2/VS2/A19, Type = DUAL, Sch name = U-SLOE +#NET "DstmPKTEND" LOC = "V12"; # Bank = 2, Pin name = IO_L19P_2, Type = I/O, Sch name = U-PKTEND + +#NET "UsbMode" LOC = "U15"; # Bank = 2, Pin name = IO_L25N_2/VS1/A18, Type = DUAL, Sch name = U-INT0# +#NET "UsbRdy" LOC = "U13"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-RDY + +## onBoard Cellular RAM and StrataFlash +#NET "MemOE" LOC = "T2"; # Bank = 3, Pin name = IO_L24P_3, Type = I/O, Sch name = OE +#NET "MemWR" LOC = "N7"; # Bank = 2, Pin name = IO_L07P_2, Type = I/O, Sch name = WE + +#NET "RamAdv" LOC = "J4"; # Bank = 3, Pin name = IO_L11N_3/LHCLK1, Type = LHCLK, Sch name = MT-ADV +#NET "RamCS" LOC = "R6"; # Bank = 2, Pin name = IO_L05P_2, Type = I/O, Sch name = MT-CE +#NET "RamClk" LOC = "H5"; # Bank = 3, Pin name = IO_L08N_3, Type = I/O, Sch name = MT-CLK +#NET "RamCRE" LOC = "P7"; # Bank = 2, Pin name = IO_L07N_2, Type = I/O, Sch name = MT-CRE +#NET "RamLB" LOC = "K5"; # Bank = 3, Pin name = IO_L14N_3/LHCLK7, Type = LHCLK, Sch name = MT-LB +#NET "RamUB" LOC = "K4"; # Bank = 3, Pin name = IO_L13N_3/LHCLK5, Type = LHCLK, Sch name = MT-UB +#NET "RamWait" LOC = "F5"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = MT-WAIT + +#NET "FlashRp" LOC = "T5"; # Bank = 2, Pin name = IO_L04N_2, Type = I/O, Sch name = RP# +#NET "FlashCS" LOC = "R5"; # Bank = 2, Pin name = IO_L04P_2, Type = I/O, Sch name = ST-CE +#NET "FlashStSts" LOC = "D3"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = ST-STS + +#NET "MemAdr<1>" LOC = "J1"; # Bank = 3, Pin name = IO_L12P_3/LHCLK2, Type = LHCLK, Sch name = ADR1 +#NET "MemAdr<2>" LOC = "J2"; # Bank = 3, Pin name = IO_L12N_3/LHCLK3/IRDY2, Type = LHCLK, Sch name = ADR2 +#NET "MemAdr<3>" LOC = "H4"; # Bank = 3, Pin name = IO_L09P_3, Type = I/O, Sch name = ADR3 +#NET "MemAdr<4>" LOC = "H1"; # Bank = 3, Pin name = IO_L10N_3, Type = I/O, Sch name = ADR4 +#NET "MemAdr<5>" LOC = "H2"; # Bank = 3, Pin name = IO_L10P_3, Type = I/O, Sch name = ADR5 +#NET "MemAdr<6>" LOC = "J5"; # Bank = 3, Pin name = IO_L11P_3/LHCLK0, Type = LHCLK, Sch name = ADR6 +#NET "MemAdr<7>" LOC = "H3"; # Bank = 3, Pin name = IO_L09N_3, Type = I/O, Sch name = ADR7 +#NET "MemAdr<8>" LOC = "H6"; # Bank = 3, Pin name = IO_L08P_3, Type = I/O, Sch name = ADR8 +#NET "MemAdr<9>" LOC = "F1"; # Bank = 3, Pin name = IO_L05P_3, Type = I/O, Sch name = ADR9 +#NET "MemAdr<10>" LOC = "G3"; # Bank = 3, Pin name = IO_L06P_3, Type = I/O, Sch name = ADR10 +#NET "MemAdr<11>" LOC = "G6"; # Bank = 3, Pin name = IO_L07P_3, Type = I/O, Sch name = ADR11 +#NET "MemAdr<12>" LOC = "G5"; # Bank = 3, Pin name = IO_L07N_3, Type = I/O, Sch name = ADR12 +#NET "MemAdr<13>" LOC = "G4"; # Bank = 3, Pin name = IO_L06N_3/VREF_3, Type = VREF, Sch name = ADR13 +#NET "MemAdr<14>" LOC = "F2"; # Bank = 3, Pin name = IO_L05N_3, Type = I/O, Sch name = ADR14 +#NET "MemAdr<15>" LOC = "E1"; # Bank = 3, Pin name = IO_L03N_3, Type = I/O, Sch name = ADR15 +#NET "MemAdr<16>" LOC = "M5"; # Bank = 3, Pin name = IO_L19P_3, Type = I/O, Sch name = ADR16 +#NET "MemAdr<17>" LOC = "E2"; # Bank = 3, Pin name = IO_L03P_3, Type = I/O, Sch name = ADR17 +#NET "MemAdr<18>" LOC = "C2"; # Bank = 3, Pin name = IO_L01N_3, Type = I/O, Sch name = ADR18 +#NET "MemAdr<19>" LOC = "C1"; # Bank = 3, Pin name = IO_L01P_3, Type = I/O, Sch name = ADR19 +#NET "MemAdr<20>" LOC = "D2"; # Bank = 3, Pin name = IO_L02N_3/VREF_3, Type = VREF, Sch name = ADR20 +#NET "MemAdr<21>" LOC = "K3"; # Bank = 3, Pin name = IO_L13P_3/LHCLK4/TRDY2, Type = LHCLK, Sch name = ADR21 +#NET "MemAdr<22>" LOC = "D1"; # Bank = 3, Pin name = IO_L02P_3, Type = I/O, Sch name = ADR22 +#NET "MemAdr<23>" LOC = "K6"; # Bank = 3, Pin name = IO_L14P_3/LHCLK6, Type = LHCLK, Sch name = ADR23 + +#NET "MemDB<0>" LOC = "L1"; # Bank = 3, Pin name = IO_L15P_3, Type = I/O, Sch name = DB0 +#NET "MemDB<1>" LOC = "L4"; # Bank = 3, Pin name = IO_L16N_3, Type = I/O, Sch name = DB1 +#NET "MemDB<2>" LOC = "L6"; # Bank = 3, Pin name = IO_L17P_3, Type = I/O, Sch name = DB2 +#NET "MemDB<3>" LOC = "M4"; # Bank = 3, Pin name = IO_L18P_3, Type = I/O, Sch name = DB3 +#NET "MemDB<4>" LOC = "N5"; # Bank = 3, Pin name = IO_L20N_3, Type = I/O, Sch name = DB4 +#NET "MemDB<5>" LOC = "P1"; # Bank = 3, Pin name = IO_L21N_3, Type = I/O, Sch name = DB5 +#NET "MemDB<6>" LOC = "P2"; # Bank = 3, Pin name = IO_L21P_3, Type = I/O, Sch name = DB6 +#NET "MemDB<7>" LOC = "R2"; # Bank = 3, Pin name = IO_L23N_3, Type = I/O, Sch name = DB7 +#NET "MemDB<8>" LOC = "L3"; # Bank = 3, Pin name = IO_L16P_3, Type = I/O, Sch name = DB8 +#NET "MemDB<9>" LOC = "L5"; # Bank = 3, Pin name = IO_L17N_3/VREF_3, Type = VREF, Sch name = DB9 +#NET "MemDB<10>" LOC = "M3"; # Bank = 3, Pin name = IO_L18N_3, Type = I/O, Sch name = DB10 +#NET "MemDB<11>" LOC = "M6"; # Bank = 3, Pin name = IO_L19N_3, Type = I/O, Sch name = DB11 +#NET "MemDB<12>" LOC = "L2"; # Bank = 3, Pin name = IO_L15N_3, Type = I/O, Sch name = DB12 +#NET "MemDB<13>" LOC = "N4"; # Bank = 3, Pin name = IO_L20P_3, Type = I/O, Sch name = DB13 +#NET "MemDB<14>" LOC = "R3"; # Bank = 3, Pin name = IO_L23P_3, Type = I/O, Sch name = DB14 +#NET "MemDB<15>" LOC = "T1"; # Bank = 3, Pin name = IO_L24N_3, Type = I/O, Sch name = DB15 + +## 7 segment display +NET "SSEG_OUT<7>" LOC = "L18"; # Bank = 1, Pin name = IO_L10P_1, Type = I/O, Sch name = CA +NET "SSEG_OUT<6>" LOC = "F18"; # Bank = 1, Pin name = IO_L19P_1, Type = I/O, Sch name = CB +NET "SSEG_OUT<5>" LOC = "D17"; # Bank = 1, Pin name = IO_L23P_1/HDC, Type = DUAL, Sch name = CC +NET "SSEG_OUT<4>" LOC = "D16"; # Bank = 1, Pin name = IO_L23N_1/LDC0, Type = DUAL, Sch name = CD +NET "SSEG_OUT<3>" LOC = "G14"; # Bank = 1, Pin name = IO_L20P_1, Type = I/O, Sch name = CE +NET "SSEG_OUT<2>" LOC = "J17"; # Bank = 1, Pin name = IO_L13P_1/A6/RHCLK4/IRDY1, Type = RHCLK/DUAL, Sch name = CF +NET "SSEG_OUT<1>" LOC = "H14"; # Bank = 1, Pin name = IO_L17P_1, Type = I/O, Sch name = CG +NET "SSEG_OUT<0>" LOC = "C17"; # Bank = 1, Pin name = IO_L24N_1/LDC2, Type = DUAL, Sch name = DP + +NET "AN_OUT<0>" LOC = "F17"; # Bank = 1, Pin name = IO_L19N_1, Type = I/O, Sch name = AN0 +NET "AN_OUT<1>" LOC = "H17"; # Bank = 1, Pin name = IO_L16N_1/A0, Type = DUAL, Sch name = AN1 +NET "AN_OUT<2>" LOC = "C18"; # Bank = 1, Pin name = IO_L24P_1/LDC1, Type = DUAL, Sch name = AN2 +NET "AN_OUT<3>" LOC = "F15"; # Bank = 1, Pin name = IO_L21P_1, Type = I/O, Sch name = AN3 + +## Leds +NET "LED_OUT<0>" LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0 +NET "LED_OUT<1>" LOC = "J15"; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1 +NET "LED_OUT<2>" LOC = "K15"; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2 +NET "LED_OUT<3>" LOC = "K14"; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3 +NET "LED_OUT<4>" LOC = "E17"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD4 +NET "LED_OUT<5>" LOC = "P15"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD5 +NET "LED_OUT<6>" LOC = "F4"; # Bank = 3, Pin name = IO, Type = I/O, Sch name = LD6 +NET "LED_OUT<7>" LOC = "R4"; # Bank = 3, Pin name = IO/VREF_3, Type = VREF, Sch name = LD7 + +## Switches +NET "SW_IN<0>" LOC = "G18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW0 +NET "SW_IN<1>" LOC = "H18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = SW1 +NET "SW_IN<2>" LOC = "K18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW2 +NET "SW_IN<3>" LOC = "K17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW3 +NET "SW_IN<4>" LOC = "L14"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW4 +NET "SW_IN<5>" LOC = "L13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW5 +NET "SW_IN<6>" LOC = "N17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW6 +NET "SW_IN<7>" LOC = "R17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW7 + +## Buttons +NET "BUTTON_IN<0>" LOC = "B18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN0 +NET "BUTTON_IN<1>" LOC = "D18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = BTN1 +NET "BUTTON_IN<2>" LOC = "E18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN2 +NET "BUTTON_IN<3>" LOC = "H13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN3 + +## VGA Connector +NET "vgaRed<0>" LOC = "R9"; # Bank = 2, Pin name = IO/D5, Type = DUAL, Sch name = RED0 +NET "vgaRed<1>" LOC = "T8"; # Bank = 2, Pin name = IO_L10N_2, Type = I/O, Sch name = RED1 +NET "vgaRed<2>" LOC = "R8"; # Bank = 2, Pin name = IO_L10P_2, Type = I/O, Sch name = RED2 +NET "vgaGreen<0>" LOC = "N8"; # Bank = 2, Pin name = IO_L09N_2, Type = I/O, Sch name = GRN0 +NET "vgaGreen<1>" LOC = "P8"; # Bank = 2, Pin name = IO_L09P_2, Type = I/O, Sch name = GRN1 +NET "vgaGreen<2>" LOC = "P6"; # Bank = 2, Pin name = IO_L05N_2, Type = I/O, Sch name = GRN2 +NET "vgaBlue<0>" LOC = "U5"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = BLU1 +NET "vgaBlue<1>" LOC = "U4"; # Bank = 2, Pin name = IO_L03P_2/DOUT/BUSY, Type = DUAL, Sch name = BLU2 + +NET "Hsync" LOC = "T4"; # Bank = 2, Pin name = IO_L03N_2/MOSI/CSI_B, Type = DUAL, Sch name = HSYNC +NET "Vsync" LOC = "U3"; # Bank = 2, Pin name = IO_L01P_2/CSO_B, Type = DUAL, Sch name = VSYNC + +## PS/2 connector +#NET "PS2C_INOUT" LOC = "R12"; # Bank = 2, Pin name = IO_L20N_2, Type = I/O, Sch name = PS2C +#NET "PS2D_INOUT" LOC = "P11"; # Bank = 2, Pin name = IO_L18P_2, Type = I/O, Sch name = PS2D + +## FX2 connector +#NET "PIO<0>" LOC = "B4"; # Bank = 0, Pin name = IO_L24N_0, Type = I/O, Sch name = R-IO1 +#NET "PIO<1>" LOC = "A4"; # Bank = 0, Pin name = IO_L24P_0, Type = I/O, Sch name = R-IO2 +#NET "PIO<2>" LOC = "C3"; # Bank = 0, Pin name = IO_L25P_0, Type = I/O, Sch name = R-IO3 +#NET "PIO<3>" LOC = "C4"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO4 +#NET "PIO<4>" LOC = "B6"; # Bank = 0, Pin name = IO_L20P_0, Type = I/O, Sch name = R-IO5 +#NET "PIO<5>" LOC = "D5"; # Bank = 0, Pin name = IO_L23N_0/VREF_0, Type = VREF, Sch name = R-IO6 +#NET "PIO<6>" LOC = "C5"; # Bank = 0, Pin name = IO_L23P_0, Type = I/O, Sch name = R-IO7 +#NET "PIO<7>" LOC = "F7"; # Bank = 0, Pin name = IO_L19P_0, Type = I/O, Sch name = R-IO8 +#NET "PIO<8>" LOC = "E7"; # Bank = 0, Pin name = IO_L19N_0/VREF_0, Type = VREF, Sch name = R-IO9 +#NET "PIO<9>" LOC = "A6"; # Bank = 0, Pin name = IO_L20N_0, Type = I/O, Sch name = R-IO10 +#NET "PIO<10>" LOC = "C7"; # Bank = 0, Pin name = IO_L18P_0, Type = I/O, Sch name = R-IO11 +#NET "PIO<11>" LOC = "F8"; # Bank = 0, Pin name = IO_L17N_0, Type = I/O, Sch name = R-IO12 +#NET "PIO<12>" LOC = "D7"; # Bank = 0, Pin name = IO_L18N_0/VREF_0, Type = VREF, Sch name = R-IO13 +#NET "PIO<13>" LOC = "E8"; # Bank = 0, Pin name = IO_L17P_0, Type = I/O, Sch name = R-IO14 +#NET "PIO<14>" LOC = "E9"; # Bank = 0, Pin name = IO_L15P_0, Type = I/O, Sch name = R-IO15 +#NET "PIO<15>" LOC = "C9"; # Bank = 0, Pin name = IO_L14P_0/GCLK10, Type = GCLK, Sch name = R-IO16 +#NET "PIO<16>" LOC = "A8"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO17 +#NET "PIO<17>" LOC = "G9"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO18 +#NET "PIO<18>" LOC = "F9"; # Bank = 0, Pin name = IO_L15N_0, Type = I/O, Sch name = R-IO19 +#NET "PIO<19>" LOC = "D10"; # Bank = 0, Pin name = IO_L11P_0/GCLK4, Type = GCLK, Sch name = R-IO20 +#NET "PIO<20>" LOC = "A10"; # Bank = 0, Pin name = IO_L12N_0/GCLK7, Type = GCLK, Sch name = R-IO21 +#NET "PIO<21>" LOC = "B10"; # Bank = 0, Pin name = IO_L12P_0/GCLK6, Type = GCLK, Sch name = R-IO22 +#NET "PIO<22>" LOC = "A11"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO23 +#NET "PIO<23>" LOC = "D11"; # Bank = 0, Pin name = IO_L09N_0, Type = I/O, Sch name = R-IO24 +#NET "PIO<24>" LOC = "E10"; # Bank = 0, Pin name = IO_L11N_0/GCLK5, Type = GCLK, Sch name = R-IO25 +#NET "PIO<25>" LOC = "B11"; # Bank = 0, Pin name = IO/VREF_0, Type = VREF, Sch name = R-IO26 +#NET "PIO<26>" LOC = "C11"; # Bank = 0, Pin name = IO_L09P_0, Type = I/O, Sch name = R-IO27 +#NET "PIO<27>" LOC = "E11"; # Bank = 0, Pin name = IO_L08P_0, Type = I/O, Sch name = R-IO28 +#NET "PIO<28>" LOC = "F11"; # Bank = 0, Pin name = IO_L08N_0, Type = I/O, Sch name = R-IO29 +#NET "PIO<29>" LOC = "E12"; # Bank = 0, Pin name = IO_L06N_0, Type = I/O, Sch name = R-IO30 +#NET "PIO<30>" LOC = "F12"; # Bank = 0, Pin name = IO_L06P_0, Type = I/O, Sch name = R-IO31 +#NET "PIO<31>" LOC = "A13"; # Bank = 0, Pin name = IO_L05P_0, Type = I/O, Sch name = R-IO32 +#NET "PIO<32>" LOC = "B13"; # Bank = 0, Pin name = IO_L05N_0/VREF_0, Type = VREF, Sch name = R-IO33 +#NET "PIO<33>" LOC = "E13"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO34 +#NET "PIO<34>" LOC = "A14"; # Bank = 0, Pin name = IO_L04N_0, Type = I/O, Sch name = R-IO35 +#NET "PIO<35>" LOC = "C14"; # Bank = 0, Pin name = IO_L03N_0/VREF_0, Type = VREF, Sch name = R-IO36 +#NET "PIO<36>" LOC = "D14"; # Bank = 0, Pin name = IO_L03P_0, Type = I/O, Sch name = R-IO37 +#NET "PIO<37>" LOC = "B14"; # Bank = 0, Pin name = IO_L04P_0, Type = I/O, Sch name = R-IO38 +#NET "PIO<38>" LOC = "A16"; # Bank = 0, Pin name = IO_L01N_0, Type = I/O, Sch name = R-IO39 +#NET "PIO<39>" LOC = "B16"; # Bank = 0, Pin name = IO_L01P_0, Type = I/O, Sch name = R-IO40 + +## 12 pin connectors +##JA +#NET "DEBUG_OUT<0>" LOC = "L15"; # Bank = 1, Pin name = IO_L09N_1/A11, Type = DUAL, Sch name = JA1 +#NET "DEBUG_OUT<1>" LOC = "K12"; # Bank = 1, Pin name = IO_L11N_1/A9/RHCLK1, Type = RHCLK/DUAL, Sch name = JA2 +#NET "DEBUG_OUT<2>" LOC = "L17"; # Bank = 1, Pin name = IO_L10N_1/VREF_1, Type = VREF, Sch name = JA3 +#NET "DEBUG_OUT<3>" LOC = "M15"; # Bank = 1, Pin name = IO_L07P_1, Type = I/O, Sch name = JA4 +#NET "DEBUG_OUT<4>" LOC = "K13"; # Bank = 1, Pin name = IO_L11P_1/A10/RHCLK0, Type = RHCLK/DUAL, Sch name = JA7 +#NET "DEBUG_OUT<5>" LOC = "L16"; # Bank = 1, Pin name = IO_L09P_1/A12, Type = DUAL, Sch name = JA8 +#NET "DEBUG_OUT<6>" LOC = "M14"; # Bank = 1, Pin name = IO_L05P_1, Type = I/O, Sch name = JA9 +#NET "DEBUG_OUT<7>" LOC = "M16"; # Bank = 1, Pin name = IO_L07N_1, Type = I/O, Sch name = JA10 + +##JB +#NET "JB<0>" LOC = "M13"; # Bank = 1, Pin name = IO_L05N_1/VREF_1, Type = VREF, Sch name = JB1 +#NET "JB<1>" LOC = "R18"; # Bank = 1, Pin name = IO_L02P_1/A14, Type = DUAL, Sch name = JB2 +#NET "JB<2>" LOC = "R15"; # Bank = 1, Pin name = IO_L03P_1, Type = I/O, Sch name = JB3 +#NET "JB<3>" LOC = "T17"; # Bank = 1, Pin name = IO_L01N_1/A15, Type = DUAL, Sch name = JB4 +#NET "JB<4>" LOC = "P17"; # Bank = 1, Pin name = IO_L06P_1, Type = I/O, Sch name = JB7 +#NET "JB<5>" LOC = "R16"; # Bank = 1, Pin name = IO_L03N_1/VREF_1, Type = VREF, Sch name = JB8 +#NET "RX_IN" LOC = "T18"; # Bank = 1, Pin name = IO_L02N_1/A13, Type = DUAL, Sch name = JB9 +#NET "TX_OUT" LOC = "U18"; # Bank = 1, Pin name = IO_L01P_1/A16, Type = DUAL, Sch name = JB10 + +##JC +#NET "JC<0>" LOC = "G15"; # Bank = 1, Pin name = IO_L18P_1, Type = I/O, Sch name = JC1 +#NET "JC<1>" LOC = "J16"; # Bank = 1, Pin name = IO_L13N_1/A5/RHCLK5, Type = RHCLK/DUAL, Sch name = JC2 +NET "SD_CS_OUT" LOC = "G13"; # Bank = 1, Pin name = IO_L20N_1, Type = I/O, Sch name = JC3 +NET "SD_MOSI_OUT" LOC = "H16"; # Bank = 1, Pin name = IO_L16P_1, Type = I/O, Sch name = JC4 +#NET "JC<4>" LOC = "H15"; # Bank = 1, Pin name = IO_L17N_1, Type = I/O, Sch name = JC7 +NET "SD_CLK_OUT" LOC = "F14"; # Bank = 1, Pin name = IO_L21N_1, Type = I/O, Sch name = JC8 +NET "SD_PRESENT_BAR_IN" LOC = "G16"; # Bank = 1, Pin name = IO_L18N_1, Type = I/O, Sch name = JC9 +NET "SD_MISO_IN" LOC = "J12"; # Bank = 1, Pin name = IO_L15P_1/A2, Type = DUAL, Sch name = JC10 + +##JD - NOTE: For other JD pins see LD(3:0) above under "Leds" +#NET "JD<0>" LOC = "J13"; # Bank = 1, Pin name = IO_L15N_1/A1, Type = DUAL, Sch name = JD1 +#NET "JD<1>" LOC = "M18"; # Bank = 1, Pin name = IO_L08N_1, Type = I/O, Sch name = JD2 +#NET "JD<2>" LOC = "N18"; # Bank = 1, Pin name = IO_L08P_1, Type = I/O, Sch name = JD3 +#NET "JD<3>" LOC = "P18"; # Bank = 1, Pin name = IO_L06N_1, Type = I/O, Sch name = JD4 + +## RS232 connector +#NET "RsRx" LOC = "U6"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = RS-RX +#NET "RsTx" LOC = "P9"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = RS-TX \ No newline at end of file Index: fat_32_file_parser/trunk/top_ps2keyboard.vhd =================================================================== --- fat_32_file_parser/trunk/top_ps2keyboard.vhd (nonexistent) +++ fat_32_file_parser/trunk/top_ps2keyboard.vhd (revision 2) @@ -0,0 +1,471 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: CW +-- +-- Create Date: 21:25:31 10/06/2014 +-- Design Name: +-- Module Name: hw_client - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use work.CommonPckg.all; +use work.SdCardPckg.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity hw_client is + Port ( CLK_IN : in STD_LOGIC; + + -- DEBUG Signals + LED_OUT : out STD_LOGIC_VECTOR (7 downto 0); + SSEG_OUT : out STD_LOGIC_VECTOR (7 downto 0); + AN_OUT : out STD_LOGIC_VECTOR (3 downto 0); + SW_IN : in STD_LOGIC_VECTOR (7 downto 0); + BUTTON_IN : in STD_LOGIC_VECTOR (3 downto 0); + vgaRed : out STD_LOGIC_VECTOR (2 downto 0); + vgaGreen : out STD_LOGIC_VECTOR (2 downto 0); + vgaBlue : out STD_LOGIC_VECTOR (1 downto 0); + Hsync : out STD_LOGIC; + Vsync : out STD_LOGIC; + + -- SD Signals + SD_PRESENT_BAR_IN : in STD_LOGIC; + SD_MOSI_OUT : out STD_LOGIC; + SD_MISO_IN : in STD_LOGIC; + SD_CLK_OUT : out STD_LOGIC; + SD_CS_OUT : out STD_LOGIC); +end hw_client; + +architecture Behavioral of hw_client is + + COMPONENT clk_mod + Port ( CLK_50MHz_IN : in STD_LOGIC; + CLK_25Mhz_OUT : out STD_LOGIC); + END COMPONENT; + + COMPONENT sseg + PORT ( + CLK : in STD_LOGIC; + VAL_IN : in STD_LOGIC_VECTOR (15 downto 0); + SSEG_OUT : out STD_LOGIC_VECTOR(7 downto 0); + AN_OUT : out STD_LOGIC_VECTOR(3 downto 0)); + END COMPONENT; + + COMPONENT SdCardInit + Port ( CLK_IN : in STD_LOGIC; + RESET_IN : in STD_LOGIC; + + SD_PRESENT_BAR_IN : in STD_LOGIC; + SD_INIT_OUT : out STD_LOGIC; + SD_BLOCK_RD_OUT : out STD_LOGIC; + SD_BLOCK_ADDR_OUT : out STD_LOGIC_VECTOR (31 downto 0); + SD_DATA_IN : in STD_LOGIC_VECTOR (7 downto 0); + SD_BUSY_IN : in STD_LOGIC; + SD_BYTE_RD_OUT : out STD_LOGIC; + SD_BYTE_RD_ACK_IN : in STD_LOGIC; + SD_ERROR_IN : in STD_LOGIC_VECTOR (15 downto 0); + SD_INIT_CMPLT_OUT : out STD_LOGIC; + + FAT_BEGIN_ADDR_OUT : out STD_LOGIC_VECTOR (31 downto 0); + SECTORS_PER_FAT_OUT : out STD_LOGIC_VECTOR (31 downto 0); + CLUSTER_BEGIN_ADDR_OUT : out STD_LOGIC_VECTOR (31 downto 0); + SECTORS_PER_CLUSTER_OUT : out STD_LOGIC_VECTOR (7 downto 0); + ROOT_DIR_FIRST_CLUSTER_OUT : out STD_LOGIC_VECTOR (31 downto 0)); + END COMPONENT; + + COMPONENT SdCardReadWrite + Port ( CLK_IN : in STD_LOGIC; + RESET_IN : in STD_LOGIC; + + FAT_BEGIN_ADDR_IN : in STD_LOGIC_VECTOR (31 downto 0); + SECTORS_PER_FAT_IN : in STD_LOGIC_VECTOR (31 downto 0); + CLUSTER_BEGIN_ADDR_IN : in STD_LOGIC_VECTOR (31 downto 0); + SECTORS_PER_CLUSTER_IN : in STD_LOGIC_VECTOR (7 downto 0); + ROOT_DIR_FIRST_CLUSTER_IN : in STD_LOGIC_VECTOR (31 downto 0); + + SD_INIT_CMPLT_IN : in STD_LOGIC; + + SD_BLOCK_RD_OUT : out STD_LOGIC; + SD_BLOCK_ADDR_OUT : out STD_LOGIC_VECTOR (31 downto 0); + SD_DATA_IN : in STD_LOGIC_VECTOR (7 downto 0); + SD_BUSY_IN : in STD_LOGIC; + SD_BYTE_RD_OUT : out STD_LOGIC; + SD_BYTE_RD_ACK_IN : in STD_LOGIC; + + GET_NEXT_DIRENT_IN : in STD_LOGIC; + NEXT_DIRENT_DONE_OUT : out STD_LOGIC; + DIRENT_IS_FOLDER_OUT : out STD_LOGIC; + RD_DIRENT_NAME_CHAR_IN : in STD_LOGIC; + DIRENT_CHAR_OUT : out STD_LOGIC_VECTOR(7 downto 0); + END_OF_DIRENT_NAME_OUT : out STD_LOGIC; + NO_MORE_DIRENTS_OUT : out STD_LOGIC; + + DEBUG_IN : in STD_LOGIC_VECTOR(7 downto 0); + DEBUG_OUT : out STD_LOGIC_VECTOR(15 downto 0); + DEBUG_OUT2 : out STD_LOGIC_VECTOR(7 downto 0)); + END COMPONENT; + + COMPONENT SdCardCtrl + generic ( + FREQ_G : real := 100.0; -- Master clock frequency (MHz). + INIT_SPI_FREQ_G : real := 0.4; -- Slow SPI clock freq. during initialization (MHz). + SPI_FREQ_G : real := 25.0; -- Operational SPI freq. to the SD card (MHz). + BLOCK_SIZE_G : natural := 512; -- Number of bytes in an SD card block or sector. + CARD_TYPE_G : CardType_t := SD_CARD_E -- Type of SD card connected to this controller. + ); + port ( + -- Host-side interface signals. + clk_i : in std_logic; -- Master clock. + reset_i : in std_logic := NO; -- active-high, synchronous reset. + rd_i : in std_logic := NO; -- active-high read block request. + wr_i : in std_logic := NO; -- active-high write block request. + continue_i : in std_logic := NO; -- If true, inc address and continue R/W. + addr_i : in std_logic_vector(31 downto 0) := x"00000000"; -- Block address. + data_i : in std_logic_vector(7 downto 0) := x"00"; -- Data to write to block. + data_o : out std_logic_vector(7 downto 0) := x"00"; -- Data read from block. + busy_o : out std_logic; -- High when controller is busy performing some operation. + hndShk_i : in std_logic; -- High when host has data to give or has taken data. + hndShk_o : out std_logic; -- High when controller has taken data or has data to give. + error_o : out std_logic_vector(15 downto 0) := (others => NO); + -- I/O signals to the external SD card. + cs_bo : out std_logic := HI; -- Active-low chip-select. + sclk_o : out std_logic := LO; -- Serial clock to SD card. + mosi_o : out std_logic := HI; -- Serial data output to SD card. + miso_i : in std_logic := ZERO; -- Serial data input from SD card. + state_debug_o : out std_logic_vector(4 downto 0) + ); + END COMPONENT; + + COMPONENT vga80x40 + PORT ( + reset : in std_logic; + clk25MHz : in std_logic; + TEXT_A : out std_logic_vector(11 downto 0); + TEXT_D : in std_logic_vector(7 downto 0); + FONT_A : out std_logic_vector(11 downto 0); + FONT_D : in std_logic_vector(7 downto 0); + -- + ocrx : in std_logic_vector(7 downto 0); + ocry : in std_logic_vector(7 downto 0); + octl : in std_logic_vector(7 downto 0); + -- + R : out std_logic; + G : out std_logic; + B : out std_logic; + hsync : out std_logic; + vsync : out std_logic); + END COMPONENT; + + COMPONENT FONT_MEM + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); + END COMPONENT; + + COMPONENT TDP_RAM + Generic (G_DATA_A_SIZE :natural :=32; + G_ADDR_A_SIZE :natural :=9; + G_RELATION :natural :=3; + G_INIT_FILE :string :="");--log2(SIZE_A/SIZE_B) + Port ( CLK_A_IN : in STD_LOGIC; + WE_A_IN : in STD_LOGIC; + ADDR_A_IN : in STD_LOGIC_VECTOR (G_ADDR_A_SIZE-1 downto 0); + DATA_A_IN : in STD_LOGIC_VECTOR (G_DATA_A_SIZE-1 downto 0); + DATA_A_OUT : out STD_LOGIC_VECTOR (G_DATA_A_SIZE-1 downto 0); + CLK_B_IN : in STD_LOGIC; + WE_B_IN : in STD_LOGIC; + ADDR_B_IN : in STD_LOGIC_VECTOR (G_ADDR_A_SIZE+G_RELATION-1 downto 0); + DATA_B_IN : in STD_LOGIC_VECTOR (G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0); + DATA_B_OUT : out STD_LOGIC_VECTOR (G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0)); + END COMPONENT; + +subtype slv is std_logic_vector; + +signal clk_25MHz : std_logic; + +-------------------------- DEBUG ------------------------------------ + +signal sseg_data : std_logic_vector(15 downto 0) := (others => '0'); +signal leds, switches : std_logic_vector(7 downto 0) := (others => '0'); +signal debug_in, debug_out2 : std_logic_vector(7 downto 0) := (others => '0'); +signal debug_out : std_logic_vector(15 downto 0) := (others => '0'); +signal buttons, buttons_prev, buttons_edge : std_logic_vector(3 downto 0) := (others => '0'); +signal debounce_count : unsigned(15 downto 0) := (others => '0'); +signal repeat_count : unsigned(21 downto 0) := (others => '0'); +signal debug_we : std_logic := '0'; +signal debug_wr_data : std_logic_vector(7 downto 0) := (others => '0'); +signal r, g, b : std_logic := '0'; +signal font_addr, debug_addr : std_logic_vector(11 downto 0); +signal font_data, debug_data : std_logic_vector(7 downto 0); +signal debug_wr_addr : unsigned(11 downto 0) := (others => '0'); + +------------------------ SD CARD SIGNALS ------------------------------- + +signal sd_mosi, sd_miso, sd_cs, sd_clk, sd_init_cmplt : std_logic; +signal sd_busy, sd_present, sd_init, sd_rd_block, sd_rd_block_init_proc : std_logic := '0'; +signal sd_rd_block_rd_proc, rd_byte, rd_byte_init_proc, rd_byte_rd_proc, rd_byte_ack : std_logic := '0'; +signal sd_init_attempts_counter : unsigned(3 downto 0) := X"0"; +signal sd_error : std_logic_vector(15 downto 0) := (others => '0'); +signal sd_data, block_rd_data : std_logic_vector(7 downto 0) := (others => '0'); +signal sd_block_addr, sd_block_addr_init_proc, sd_block_addr_rd_proc : std_logic_vector(31 downto 0) := (others => '0'); + +signal sectors_per_cluster : std_logic_vector(7 downto 0); +signal fat_begin_lba, cluster_begin_lba : std_logic_vector(31 downto 0); +signal sectors_per_fat, root_dir_cluster : std_logic_vector(31 downto 0); +signal read_dirent_name, dirent_found, rd_dirent_char, end_of_dirent_name : std_logic := '0'; +signal dirent_is_folder, no_more_dirents : std_logic := '0'; + +begin + + clk_mod_Inst : clk_mod + PORT MAP ( CLK_50MHz_IN => CLK_IN, + CLK_25Mhz_OUT => clk_25MHz); + +----------------------- DEBUG I/O ---------------------------------- + + LED_OUT <= leds; + switches <= SW_IN; + + sseg_inst : sseg + PORT MAP ( + CLK => clk_25MHz, + VAL_IN => sseg_data, + SSEG_OUT => SSEG_OUT, + AN_OUT => AN_OUT); + + process(clk_25MHz) + begin + if rising_edge(clk_25MHz) then + leds(7 downto 0) <= debug_out2(7 downto 0); + --leds(6) <= sd_init_cmplt; + --leds(7) <= not(SD_PRESENT_BAR_IN); + end if; + end process; + + debug_in <= "0000000"&buttons(1); + sseg_data <= debug_out; + --sseg_data <= sd_error; + + process(clk_25MHz) + begin + if rising_edge(clk_25MHz) then + repeat_count <= repeat_count + 1; + debounce_count <= debounce_count + 1; + buttons_prev <= buttons; + if debounce_count = X"0000" then + buttons <= BUTTON_IN; + end if; + if buttons_prev(0) = '0' and buttons(0) = '1' then + buttons_edge(0) <= '1'; + elsif repeat_count = X"00000"&"00" and buttons(0) = '1' then + buttons_edge(0) <= '1'; + else + buttons_edge(0) <= '0'; + end if; + if buttons_prev(1) = '0' and buttons(1) = '1' then + buttons_edge(1) <= '1'; + else + buttons_edge(1) <= '0'; + end if; + if buttons_prev(3) = '0' and buttons(3) = '1' then + buttons_edge(3) <= '1'; + else + buttons_edge(3) <= '0'; + end if; + end if; + end process; + + vgaRed <= r&r&r; + vgaGreen <= g&g&g; + vgaBlue <= b&b; + + vga80x40_inst : vga80x40 + PORT MAP ( + reset => '0', + clk25MHz => clk_25MHz, + TEXT_A => debug_addr, + TEXT_D => debug_data, + FONT_A => font_addr, + FONT_D => font_data, + + ocrx => X"00", + ocry => X"00", + octl => "11100111", + + R => r, + G => g, + B => b, + hsync => Hsync, + vsync => Vsync); + + Font_Mem_inst : FONT_MEM + PORT MAP ( + clka => clk_25MHz, + wea => "0", + addra => font_addr, + dina => (others => '0'), + douta => font_data); + + rd_dirent_char <= read_dirent_name; + + process(clk_25MHz) + begin + if rising_edge(clk_25MHz) then +-- if dirent_found = '1' then +-- leds(6) <= dirent_is_folder; +-- end if; + if dirent_found = '1' then + read_dirent_name <= '1'; + elsif end_of_dirent_name = '1' then + read_dirent_name <= '0'; + end if; + if read_dirent_name = '1' then + debug_we <= '1'; + elsif end_of_dirent_name = '1' then + debug_we <= '0'; + end if; + if read_dirent_name = '1' then + if debug_wr_addr = X"C80" then + debug_wr_addr <= (others => '0'); + else + debug_wr_addr <= debug_wr_addr + 1; + end if; + end if; + end if; + end process; + + debug_buf : TDP_RAM + Generic Map ( G_DATA_A_SIZE => debug_data'length, + G_ADDR_A_SIZE => debug_addr'length, + G_RELATION => 0, --log2(SIZE_A/SIZE_B) + G_INIT_FILE => "./coe_dir/ascii_space.coe") + Port Map ( CLK_A_IN => clk_25MHz, + WE_A_IN => '0', + ADDR_A_IN => debug_addr, + DATA_A_IN => X"00", + DATA_A_OUT => debug_data, + CLK_B_IN => clk_25MHz, + WE_B_IN => debug_we, + ADDR_B_IN => slv(debug_wr_addr), + DATA_B_IN => debug_wr_data, + DATA_B_OUT => open); + +--------------------------------------------------------- + + SD_CS_OUT <= sd_cs; + SD_CLK_OUT <= sd_clk; + SD_MOSI_OUT <= sd_mosi; + sd_miso <= SD_MISO_IN; + + SdCardCtrl_Inst : SdCardCtrl + generic map ( + FREQ_G => 25.0, -- Master clock frequency (MHz). + INIT_SPI_FREQ_G => 0.4, -- Slow SPI clock freq. during initialization (MHz). + SPI_FREQ_G => 5.0, -- Operational SPI freq. to the SD card (MHz). + BLOCK_SIZE_G => 512, -- Number of bytes in an SD card block or sector. + CARD_TYPE_G => SD_CARD_E -- Type of SD card connected to this controller. + ) + port map ( + -- Host-side interface signals. + clk_i => clk_25MHz, + reset_i => sd_init, + rd_i => sd_rd_block, + wr_i => '0', + continue_i => '0', + addr_i => sd_block_addr, + data_i => X"00", + data_o => sd_data, + busy_o => sd_busy, + hndShk_i => rd_byte, + hndShk_o => rd_byte_ack, + error_o => sd_error, + -- I/O signals to the external SD card. + cs_bo => sd_cs, + sclk_o => sd_clk, + mosi_o => sd_mosi, + miso_i => sd_miso, + state_debug_o => open); --leds(4 downto 0)); + + with sd_init_cmplt select + rd_byte <= rd_byte_init_proc when '0', + rd_byte_rd_proc when others; + + with sd_init_cmplt select + sd_rd_block <= sd_rd_block_init_proc when '0', + sd_rd_block_rd_proc when others; + + with sd_init_cmplt select + sd_block_addr <= sd_block_addr_init_proc when '0', + sd_block_addr_rd_proc when others; + + SdCardInit_Inst : SdCardInit + Port Map( CLK_IN => clk_25MHz, + RESET_IN => buttons_edge(3), + + SD_PRESENT_BAR_IN => SD_PRESENT_BAR_IN, + SD_INIT_OUT => sd_init, + SD_BLOCK_RD_OUT => sd_rd_block_init_proc, + SD_BLOCK_ADDR_OUT => sd_block_addr_init_proc, + SD_DATA_IN => sd_data, + SD_BUSY_IN => sd_busy, + SD_BYTE_RD_OUT => rd_byte_init_proc, + SD_BYTE_RD_ACK_IN => rd_byte_ack, + SD_ERROR_IN => sd_error, + SD_INIT_CMPLT_OUT => sd_init_cmplt, + + FAT_BEGIN_ADDR_OUT => fat_begin_lba, + SECTORS_PER_FAT_OUT => sectors_per_fat, + CLUSTER_BEGIN_ADDR_OUT => cluster_begin_lba, + SECTORS_PER_CLUSTER_OUT => sectors_per_cluster, + ROOT_DIR_FIRST_CLUSTER_OUT => root_dir_cluster); + + SdCardReadWrite_Inst : SdCardReadWrite + Port Map( CLK_IN => clk_25MHz, + RESET_IN => buttons_edge(3), + + FAT_BEGIN_ADDR_IN => fat_begin_lba, + SECTORS_PER_FAT_IN => sectors_per_fat, + CLUSTER_BEGIN_ADDR_IN => cluster_begin_lba, + SECTORS_PER_CLUSTER_IN => sectors_per_cluster, + ROOT_DIR_FIRST_CLUSTER_IN => root_dir_cluster, + + SD_INIT_CMPLT_IN => sd_init_cmplt, + + SD_BLOCK_RD_OUT => sd_rd_block_rd_proc, + SD_BLOCK_ADDR_OUT => sd_block_addr_rd_proc, + SD_DATA_IN => sd_data, + SD_BUSY_IN => sd_busy, + SD_BYTE_RD_OUT => rd_byte_rd_proc, + SD_BYTE_RD_ACK_IN => rd_byte_ack, + + GET_NEXT_DIRENT_IN => buttons_edge(0), + NEXT_DIRENT_DONE_OUT => dirent_found, + DIRENT_IS_FOLDER_OUT => dirent_is_folder, + RD_DIRENT_NAME_CHAR_IN => rd_dirent_char, + DIRENT_CHAR_OUT => debug_wr_data, + END_OF_DIRENT_NAME_OUT => end_of_dirent_name, + NO_MORE_DIRENTS_OUT => no_more_dirents, + + DEBUG_IN => debug_in, + DEBUG_OUT => debug_out, + DEBUG_OUT2 => debug_out2); + +end Behavioral; + Index: fat_32_file_parser/trunk/SdCardReadWrite.vhd =================================================================== --- fat_32_file_parser/trunk/SdCardReadWrite.vhd (nonexistent) +++ fat_32_file_parser/trunk/SdCardReadWrite.vhd (revision 2) @@ -0,0 +1,1085 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15:20:06 11/16/2014 +-- Design Name: +-- Module Name: SdCardReadWrite - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +library UNISIM; +use UNISIM.VComponents.all; + +entity SdCardReadWrite is + Port ( CLK_IN : in STD_LOGIC; + RESET_IN : in STD_LOGIC; + + FAT_BEGIN_ADDR_IN : in STD_LOGIC_VECTOR (31 downto 0); + SECTORS_PER_FAT_IN : in STD_LOGIC_VECTOR (31 downto 0); + CLUSTER_BEGIN_ADDR_IN : in STD_LOGIC_VECTOR (31 downto 0); + SECTORS_PER_CLUSTER_IN : in STD_LOGIC_VECTOR (7 downto 0); + ROOT_DIR_FIRST_CLUSTER_IN : in STD_LOGIC_VECTOR (31 downto 0); + + SD_INIT_CMPLT_IN : in STD_LOGIC; + + SD_BLOCK_RD_OUT : out STD_LOGIC; + SD_BLOCK_ADDR_OUT : out STD_LOGIC_VECTOR (31 downto 0); + SD_DATA_IN : in STD_LOGIC_VECTOR (7 downto 0); + SD_BUSY_IN : in STD_LOGIC; + SD_BYTE_RD_OUT : out STD_LOGIC; + SD_BYTE_RD_ACK_IN : in STD_LOGIC; + + GET_NEXT_DIRENT_IN : in STD_LOGIC; + NEXT_DIRENT_DONE_OUT : out STD_LOGIC; + DIRENT_IS_FOLDER_OUT : out STD_LOGIC; + RD_DIRENT_NAME_CHAR_IN : in STD_LOGIC; + DIRENT_CHAR_OUT : out STD_LOGIC_VECTOR(7 downto 0); + END_OF_DIRENT_NAME_OUT : out STD_LOGIC; + NO_MORE_DIRENTS_OUT : out STD_LOGIC; + + DEBUG_IN : in STD_LOGIC_VECTOR(7 downto 0); + DEBUG_OUT : out STD_LOGIC_VECTOR(15 downto 0); + DEBUG_OUT2 : out STD_LOGIC_VECTOR(7 downto 0)); +end SdCardReadWrite; + +architecture Behavioral of SdCardReadWrite is + + COMPONENT TDP_RAM + Generic (G_DATA_A_SIZE :natural :=32; + G_ADDR_A_SIZE :natural :=9; + G_RELATION :natural :=3; + G_INIT_FILE :string :="");--log2(SIZE_A/SIZE_B) + Port ( CLK_A_IN : in STD_LOGIC; + WE_A_IN : in STD_LOGIC; + ADDR_A_IN : in STD_LOGIC_VECTOR (G_ADDR_A_SIZE-1 downto 0); + DATA_A_IN : in STD_LOGIC_VECTOR (G_DATA_A_SIZE-1 downto 0); + DATA_A_OUT : out STD_LOGIC_VECTOR (G_DATA_A_SIZE-1 downto 0); + CLK_B_IN : in STD_LOGIC; + WE_B_IN : in STD_LOGIC; + ADDR_B_IN : in STD_LOGIC_VECTOR (G_ADDR_A_SIZE+G_RELATION-1 downto 0); + DATA_B_IN : in STD_LOGIC_VECTOR (G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0); + DATA_B_OUT : out STD_LOGIC_VECTOR (G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0)); + END COMPONENT; + + COMPONENT lifo is + Generic ( G_LOG2_DEPTH : natural := 6; + G_DATA_SIZE : natural := 8 ); -- LOG2(lifo depth) + Port ( CLK_IN : in STD_LOGIC; + RESET_IN : in STD_LOGIC; + CACHE_ADDR_IN : in STD_LOGIC; + GOTO_CACHE_IN : in STD_LOGIC; + WR_DATA_IN : in STD_LOGIC_VECTOR ((G_DATA_SIZE - 1) downto 0); + WR_EN_IN : in STD_LOGIC; + RD_DATA_OUT : out STD_LOGIC_VECTOR ((G_DATA_SIZE - 1) downto 0); + RD_EN_IN : in STD_LOGIC; + EMPTY_OUT : out STD_LOGIC; + FULL_OUT : out STD_LOGIC); + END COMPONENT; + +subtype slv is std_logic_vector; + +constant C_unused_entry : std_logic_vector(7 downto 0) := X"E5"; +constant C_end_of_directory : std_logic_vector(7 downto 0) := X"00"; +constant C_file_name_type : std_logic_vector(7 downto 0) := X"0F"; +constant C_folder_type : std_logic_vector(7 downto 0) := X"10"; +constant C_file_type : std_logic_vector(7 downto 0) := X"20"; +constant C_attrib_offset : unsigned(4 downto 0) := "01011"; +constant C_lsb_word_lsb_offset : unsigned(4 downto 0) := "11010"; +constant C_lsb_word_msb_offset : unsigned(4 downto 0) := "11011"; +constant C_msb_word_lsb_offset : unsigned(4 downto 0) := "10100"; +constant C_msb_word_msb_offset : unsigned(4 downto 0) := "10101"; + +signal sd_init_cmplt, sd_block_rd, perform_block_rd, block_rd_cmplt : std_logic := '0'; +signal sd_busy, rd_byte, rd_byte_ack, get_next_dirent : std_logic := '0'; +signal sd_data, block_rd_data : std_logic_vector(7 downto 0) := (others => '0'); + +signal fat_begin_addr, sectors_per_fat : unsigned(31 downto 0); +signal sd_block_addr : unsigned(31 downto 0); +signal cluster_begin_addr : unsigned(31 downto 0); +signal find_dirent_addr, find_dirent_addr_rd, find_dirent_addr_cache : unsigned(8 downto 0) := (others => '0'); +signal find_dirent_addr_rd_slv : std_logic_vector(8 downto 0); + +signal dirent_found, dirent_is_folder : std_logic := '0'; +signal dirent_lifo_we, dirent_lifo_rst, dirent_lifo_cache_addr : std_logic := '0'; +signal dirent_lifo_goto_cache, dirent_lifo_full, dirent_lifo_empty : std_logic := '0'; + +signal folder_addr, folder_addr_tmp, folder_addr_final : unsigned(31 downto 0) := X"00000000"; +signal sectors_per_cluster, spc_counter : std_logic_vector(7 downto 0) := X"00"; + +signal bp_lifo_rst, bp_lifo_we, bp_lifo_rd, bp_lifo_empty : std_logic := '0'; +signal bp_lifo_block_data : std_logic_vector(31 downto 0) := (others => '0'); + +signal find_addr_lifo_rst, find_addr_lifo_we, find_addr_lifo_rd, find_addr_lifo_empty : std_logic := '0'; + +signal end_of_dirents : std_logic := '0'; +signal sectors_per_cluster_zero_indexed, find_dirent_block_num, find_dirent_block_num_rd : unsigned(7 downto 0) := X"00"; +signal current_cluster, current_cluster_buf, current_cluster_rd : unsigned(31 downto 0) := X"00000000"; +signal current_cluster_fat_block_addr, current_cluster_tmp, next_cluster_lba : unsigned(31 downto 0) := X"00000000"; +signal current_cluster_lifo_rst, current_cluster_lifo_we, current_cluster_lifo_rd : std_logic := '0'; +signal current_cluster_lifo_empty : std_logic := '0'; +signal current_cluster_rd_slv : std_logic_vector(31 downto 0); + +signal find_dirent_block_lifo_rst, find_dirent_block_lifo_we, find_dirent_block_lifo_rd : std_logic := '0'; +signal find_dirent_block_lifo_empty : std_logic := '0'; +signal find_dirent_block_num_rd_slv : std_logic_vector(7 downto 0); + +signal file_counter :unsigned(15 downto 0) := (others => '0'); +signal debug : std_logic := '0'; + +type MAIN_ROUTINE is ( REPORT_ERROR, + WAIT_FOR_INIT_CMPLT, + IDLE_W_BLOCK_RD, + IDLE_NO_BLOCK_RD, + + FIND_NEXT_DIRENT0, + FIND_NEXT_DIRENT1, + FIND_NEXT_DIRENT2, + FIND_NEXT_DIRENT3, + FIND_NEXT_DIRENT4, + FIND_NEXT_DIRENT5, + FIND_NEXT_DIRENT6, + + PARSE_NAME_DIRENT0, + PARSE_NAME_DIRENT1, + PARSE_NAME_DIRENT2, + PARSE_NAME_DIRENT3, + PARSE_NAME_DIRENT4, + PARSE_NAME_DIRENT5, + PARSE_NAME_DIRENT6, + PARSE_NAME_DIRENT7, + PARSE_NAME_DIRENT8, + PARSE_NAME_DIRENT9, + PARSE_NAME_DIRENT10, + PARSE_NAME_DIRENT11, + PARSE_NAME_DIRENT12, + PARSE_NAME_DIRENT13, + PARSE_NAME_DIRENT14, + PARSE_NAME_DIRENT15, + PARSE_NAME_DIRENT16, + PARSE_NAME_DIRENT17, + + HANDLE_FILE_DIRENT0, + + HANDLE_END_OF_DIR0, + HANDLE_END_OF_DIR1, + HANDLE_END_OF_DIR2, + HANDLE_END_OF_DIR3, + + HANDLE_FOLDER_DIRENT0, + HANDLE_FOLDER_DIRENT1, + HANDLE_FOLDER_DIRENT2, + HANDLE_FOLDER_DIRENT3, + HANDLE_FOLDER_DIRENT4, + HANDLE_FOLDER_DIRENT5, + HANDLE_FOLDER_DIRENT6, + HANDLE_FOLDER_DIRENT7, + HANDLE_FOLDER_DIRENT8, + HANDLE_FOLDER_DIRENT9, + + HANDLE_INTERNAL_ADDR_INC0, + HANDLE_INTERNAL_ADDR_INC1, + HANDLE_INTERNAL_ADDR_INC2, + HANDLE_INTERNAL_ADDR_INC3, + HANDLE_INTERNAL_ADDR_INC4, + HANDLE_INTERNAL_ADDR_INC5, + HANDLE_INTERNAL_ADDR_INC6, + HANDLE_INTERNAL_ADDR_INC7, + + FIND_NEXT_CLUSTER0, + FIND_NEXT_CLUSTER1, + FIND_NEXT_CLUSTER2, + FIND_NEXT_CLUSTER3, + FIND_NEXT_CLUSTER4, + FIND_NEXT_CLUSTER5, + FIND_NEXT_CLUSTER6, + FIND_NEXT_CLUSTER7, + FIND_NEXT_CLUSTER8, + FIND_NEXT_CLUSTER9, + + HANDLE_END_OF_DIRENTS0, + HANDLE_END_OF_DIRENTS1); + +signal rw_state, rw_next_state, rw_state_cached : MAIN_ROUTINE := WAIT_FOR_INIT_CMPLT; + +signal block_rd_we : std_logic := '0'; +signal block_wr_addr, block_rd_addr : unsigned(8 downto 0) := (others => '0'); + +type BLOCK_RD_ROUTINE is ( IDLE, + WAIT_UNTIL_NOT_BUSY, + WAIT_UNTIL_BLOCK_READ_ACKD, + READ_BYTE0, + READ_BYTE1, + READ_BYTE2, + READ_BYTE3, + READ_BYTE4 + ); +signal br_state, br_next_state : BLOCK_RD_ROUTINE; + +signal state_debug_sig : unsigned(5 downto 0); +signal state_debug_sig2 : unsigned(1 downto 0); + +begin + + sd_init_cmplt <= SD_INIT_CMPLT_IN; + SD_BLOCK_RD_OUT <= sd_block_rd; + SD_BLOCK_ADDR_OUT <= slv(sd_block_addr); + sd_data <= SD_DATA_IN; + sd_busy <= SD_BUSY_IN; + SD_BYTE_RD_OUT <= rd_byte; + rd_byte_ack <= SD_BYTE_RD_ACK_IN; + + fat_begin_addr <= unsigned(FAT_BEGIN_ADDR_IN); + sectors_per_fat <= unsigned(SECTORS_PER_FAT_IN); + cluster_begin_addr <= unsigned(CLUSTER_BEGIN_ADDR_IN); + get_next_dirent <= GET_NEXT_DIRENT_IN; + sectors_per_cluster <= SECTORS_PER_CLUSTER_IN; + sectors_per_cluster_zero_indexed <= unsigned(SECTORS_PER_CLUSTER_IN) - 1; + + NEXT_DIRENT_DONE_OUT <= dirent_found; + DIRENT_IS_FOLDER_OUT <= dirent_is_folder; + END_OF_DIRENT_NAME_OUT <= dirent_lifo_empty; + NO_MORE_DIRENTS_OUT <= end_of_dirents; + +-- debug_state: process(CLK_IN) +-- begin +-- if rising_edge(CLK_IN) then +-- case (br_state) is +-- when IDLE => +-- state_debug_sig <= to_unsigned(0, 6); +-- when WAIT_UNTIL_NOT_BUSY => +-- state_debug_sig <= to_unsigned(1, 6); +-- when WAIT_UNTIL_BLOCK_READ_ACKD => +-- state_debug_sig <= to_unsigned(2, 6); +-- when READ_BYTE0 => +-- state_debug_sig <= to_unsigned(3, 6); +-- when READ_BYTE1 => +-- state_debug_sig <= to_unsigned(4, 6); +-- when READ_BYTE2 => +-- state_debug_sig <= to_unsigned(5, 6); +-- when READ_BYTE3 => +-- state_debug_sig <= to_unsigned(6, 6); +-- when READ_BYTE4 => +-- state_debug_sig <= to_unsigned(7, 6); +-- end case; +-- end if; +-- end process; + + debug_state: process(CLK_IN) + begin + if rising_edge(CLK_IN) then + case( rw_state ) is + + when REPORT_ERROR => + state_debug_sig <= to_unsigned(0, 6); + when WAIT_FOR_INIT_CMPLT => + state_debug_sig <= to_unsigned(1, 6); + when IDLE_W_BLOCK_RD => + state_debug_sig <= to_unsigned(2, 6); + when IDLE_NO_BLOCK_RD => + state_debug_sig <= to_unsigned(3, 6); + when FIND_NEXT_DIRENT0 => + state_debug_sig <= to_unsigned(4, 6); + when FIND_NEXT_DIRENT1 => + state_debug_sig <= to_unsigned(5, 6); + when FIND_NEXT_DIRENT2 => + state_debug_sig <= to_unsigned(6, 6); + when FIND_NEXT_DIRENT3 => + state_debug_sig <= to_unsigned(7, 6); + when FIND_NEXT_DIRENT4 => + state_debug_sig <= to_unsigned(8, 6); + when FIND_NEXT_DIRENT5 => + state_debug_sig <= to_unsigned(9, 6); + when FIND_NEXT_DIRENT6 => + state_debug_sig <= to_unsigned(10, 6); + when PARSE_NAME_DIRENT0 => + state_debug_sig <= to_unsigned(11, 6); + when PARSE_NAME_DIRENT1 => + state_debug_sig <= to_unsigned(12, 6); + when PARSE_NAME_DIRENT2 => + state_debug_sig <= to_unsigned(13, 6); + when PARSE_NAME_DIRENT3 => + state_debug_sig <= to_unsigned(14, 6); + when PARSE_NAME_DIRENT4 => + state_debug_sig <= to_unsigned(15, 6); + when PARSE_NAME_DIRENT5 => + state_debug_sig <= to_unsigned(16, 6); + when PARSE_NAME_DIRENT6 => + state_debug_sig <= to_unsigned(17, 6); + when PARSE_NAME_DIRENT7 => + state_debug_sig <= to_unsigned(18, 6); + when PARSE_NAME_DIRENT8 => + state_debug_sig <= to_unsigned(19, 6); + when PARSE_NAME_DIRENT9 => + state_debug_sig <= to_unsigned(20, 6); + when PARSE_NAME_DIRENT10 => + state_debug_sig <= to_unsigned(21, 6); + when PARSE_NAME_DIRENT11 => + state_debug_sig <= to_unsigned(22, 6); + when PARSE_NAME_DIRENT12 => + state_debug_sig <= to_unsigned(23, 6); + when PARSE_NAME_DIRENT13 => + state_debug_sig <= to_unsigned(24, 6); + when PARSE_NAME_DIRENT14 => + state_debug_sig <= to_unsigned(25, 6); + when PARSE_NAME_DIRENT15 => + state_debug_sig <= to_unsigned(26, 6); + when PARSE_NAME_DIRENT16 => + state_debug_sig <= to_unsigned(27, 6); + when PARSE_NAME_DIRENT17 => + state_debug_sig <= to_unsigned(28, 6); + when HANDLE_FILE_DIRENT0 => + state_debug_sig <= to_unsigned(29, 6); + when HANDLE_END_OF_DIR0 => + state_debug_sig <= to_unsigned(30, 6); + when HANDLE_END_OF_DIR1 => + state_debug_sig <= to_unsigned(31, 6); + when HANDLE_END_OF_DIR2 => + state_debug_sig <= to_unsigned(32, 6); + when HANDLE_END_OF_DIR3 => + state_debug_sig <= to_unsigned(33, 6); + when HANDLE_FOLDER_DIRENT0 => + state_debug_sig <= to_unsigned(34, 6); + when HANDLE_FOLDER_DIRENT1 => + state_debug_sig <= to_unsigned(35, 6); + when HANDLE_FOLDER_DIRENT2 => + state_debug_sig <= to_unsigned(36, 6); + when HANDLE_FOLDER_DIRENT3 => + state_debug_sig <= to_unsigned(37, 6); + when HANDLE_FOLDER_DIRENT4 => + state_debug_sig <= to_unsigned(38, 6); + when HANDLE_FOLDER_DIRENT5 => + state_debug_sig <= to_unsigned(39, 6); + when HANDLE_FOLDER_DIRENT6 => + state_debug_sig <= to_unsigned(40, 6); + when HANDLE_FOLDER_DIRENT7 => + state_debug_sig <= to_unsigned(41, 6); + when HANDLE_FOLDER_DIRENT8 => + state_debug_sig <= to_unsigned(42, 6); + when HANDLE_FOLDER_DIRENT9 => + state_debug_sig <= to_unsigned(43, 6); + when HANDLE_INTERNAL_ADDR_INC0 => + state_debug_sig <= to_unsigned(44, 6); + when HANDLE_INTERNAL_ADDR_INC1 => + state_debug_sig <= to_unsigned(45, 6); + when HANDLE_INTERNAL_ADDR_INC2 => + state_debug_sig <= to_unsigned(46, 6); + when HANDLE_INTERNAL_ADDR_INC3 => + state_debug_sig <= to_unsigned(47, 6); + when HANDLE_INTERNAL_ADDR_INC4 => + state_debug_sig <= to_unsigned(48, 6); + when HANDLE_INTERNAL_ADDR_INC5 => + state_debug_sig <= to_unsigned(49, 6); + when HANDLE_INTERNAL_ADDR_INC6 => + state_debug_sig <= to_unsigned(50, 6); + when HANDLE_INTERNAL_ADDR_INC7 => + state_debug_sig <= to_unsigned(51, 6); + when FIND_NEXT_CLUSTER0 => + state_debug_sig <= to_unsigned(52, 6); + when FIND_NEXT_CLUSTER1 => + state_debug_sig <= to_unsigned(53, 6); + when FIND_NEXT_CLUSTER2 => + state_debug_sig <= to_unsigned(54, 6); + when FIND_NEXT_CLUSTER3 => + state_debug_sig <= to_unsigned(55, 6); + when FIND_NEXT_CLUSTER4 => + state_debug_sig <= to_unsigned(56, 6); + when FIND_NEXT_CLUSTER5 => + state_debug_sig <= to_unsigned(57, 6); + when FIND_NEXT_CLUSTER6 => + state_debug_sig <= to_unsigned(58, 6); + when FIND_NEXT_CLUSTER7 => + state_debug_sig <= to_unsigned(59, 6); + when FIND_NEXT_CLUSTER8 => + state_debug_sig <= to_unsigned(60, 6); + when FIND_NEXT_CLUSTER9 => + state_debug_sig <= to_unsigned(61, 6); + when HANDLE_END_OF_DIRENTS0 => + state_debug_sig <= to_unsigned(62, 6); + when HANDLE_END_OF_DIRENTS1 => + state_debug_sig <= to_unsigned(63, 6); + end case; + end if; + end process; + + debug_state2: process(CLK_IN) + begin + if rising_edge(CLK_IN) then + case( rw_state_cached ) is + + when FIND_NEXT_DIRENT2 => + state_debug_sig2 <= to_unsigned(0, 2); + when PARSE_NAME_DIRENT15 => + state_debug_sig2 <= to_unsigned(1, 2); + when IDLE_NO_BLOCK_RD => + state_debug_sig2 <= to_unsigned(2, 2); + when others => + state_debug_sig2 <= to_unsigned(3, 2); + end case; + end if; + end process; + +-------- FSM OUTPUT -------- + + BLOCK_RD: process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if rw_state = WAIT_FOR_INIT_CMPLT then + sd_block_addr <= cluster_begin_addr; + elsif rw_state = HANDLE_FOLDER_DIRENT9 then + sd_block_addr <= folder_addr_final; + elsif rw_state = HANDLE_END_OF_DIR0 then + sd_block_addr <= unsigned(bp_lifo_block_data); + elsif rw_state = HANDLE_END_OF_DIRENTS0 then + sd_block_addr <= cluster_begin_addr; + elsif rw_state = HANDLE_INTERNAL_ADDR_INC1 then + sd_block_addr <= sd_block_addr + 1; + elsif rw_state = FIND_NEXT_CLUSTER1 then + sd_block_addr <= current_cluster_fat_block_addr; + elsif rw_state = HANDLE_INTERNAL_ADDR_INC6 then + sd_block_addr <= next_cluster_lba; + end if; + if rw_state = FIND_NEXT_DIRENT0 then + perform_block_rd <= '1'; + elsif rw_state = HANDLE_INTERNAL_ADDR_INC1 then + perform_block_rd <= '1'; + elsif rw_state = FIND_NEXT_CLUSTER1 then + perform_block_rd <= '1'; + elsif rw_state = HANDLE_INTERNAL_ADDR_INC6 then + perform_block_rd <= '1'; + else + perform_block_rd <= '0'; + end if; + if rw_state = FIND_NEXT_DIRENT2 then + block_rd_addr <= find_dirent_addr; + elsif rw_state = FIND_NEXT_DIRENT3 then + block_rd_addr <= find_dirent_addr(8 downto 5) & C_attrib_offset; + elsif rw_state = PARSE_NAME_DIRENT1 then + block_rd_addr <= find_dirent_addr(8 downto 5) & to_unsigned(30, 5); + elsif rw_state = PARSE_NAME_DIRENT2 then + block_rd_addr <= find_dirent_addr(8 downto 5) & to_unsigned(28,5); + elsif rw_state = PARSE_NAME_DIRENT3 then + block_rd_addr <= find_dirent_addr(8 downto 5) & to_unsigned(24,5); + elsif rw_state = PARSE_NAME_DIRENT4 then + block_rd_addr <= find_dirent_addr(8 downto 5) & to_unsigned(22,5); + elsif rw_state = PARSE_NAME_DIRENT5 then + block_rd_addr <= find_dirent_addr(8 downto 5) & to_unsigned(20,5); + elsif rw_state = PARSE_NAME_DIRENT6 then + block_rd_addr <= find_dirent_addr(8 downto 5) & to_unsigned(18,5); + elsif rw_state = PARSE_NAME_DIRENT7 then + block_rd_addr <= find_dirent_addr(8 downto 5) & to_unsigned(16,5); + elsif rw_state = PARSE_NAME_DIRENT8 then + block_rd_addr <= find_dirent_addr(8 downto 5) & to_unsigned(14,5); + elsif rw_state = PARSE_NAME_DIRENT9 then + block_rd_addr <= find_dirent_addr(8 downto 5) & to_unsigned(9, 5); + elsif rw_state = PARSE_NAME_DIRENT10 then + block_rd_addr <= find_dirent_addr(8 downto 5) & to_unsigned(7, 5); + elsif rw_state = PARSE_NAME_DIRENT11 then + block_rd_addr <= find_dirent_addr(8 downto 5) & to_unsigned(5, 5); + elsif rw_state = PARSE_NAME_DIRENT12 then + block_rd_addr <= find_dirent_addr(8 downto 5) & to_unsigned(3, 5); + elsif rw_state = PARSE_NAME_DIRENT13 then + block_rd_addr <= find_dirent_addr(8 downto 5) & to_unsigned(1, 5); + elsif rw_state = PARSE_NAME_DIRENT15 then + block_rd_addr <= find_dirent_addr(8 downto 5) & C_attrib_offset; + elsif rw_state = HANDLE_FOLDER_DIRENT0 then + block_rd_addr <= find_dirent_addr(8 downto 5) & C_lsb_word_lsb_offset; + elsif rw_state = HANDLE_FOLDER_DIRENT1 then + block_rd_addr <= find_dirent_addr(8 downto 5) & C_lsb_word_msb_offset; + elsif rw_state = HANDLE_FOLDER_DIRENT2 then + block_rd_addr <= find_dirent_addr(8 downto 5) & C_msb_word_lsb_offset; + elsif rw_state = HANDLE_FOLDER_DIRENT3 then + block_rd_addr <= find_dirent_addr(8 downto 5) & C_msb_word_msb_offset; + elsif rw_state = FIND_NEXT_CLUSTER3 then + block_rd_addr <= current_cluster_buf(6 downto 0) & "00"; + elsif rw_state = FIND_NEXT_CLUSTER4 then + block_rd_addr <= current_cluster_buf(6 downto 0) & "01"; + elsif rw_state = FIND_NEXT_CLUSTER5 then + block_rd_addr <= current_cluster_buf(6 downto 0) & "10"; + elsif rw_state = FIND_NEXT_CLUSTER6 then + block_rd_addr <= current_cluster_buf(6 downto 0) & "11"; + end if; + if rw_state = FIND_NEXT_CLUSTER2 then + current_cluster_buf <= current_cluster; + end if; + if rw_state = FIND_NEXT_DIRENT6 then + rw_state_cached <= FIND_NEXT_DIRENT2; + elsif rw_state = PARSE_NAME_DIRENT14 then + rw_state_cached <= PARSE_NAME_DIRENT15; + elsif rw_state = HANDLE_FILE_DIRENT0 then + rw_state_cached <= IDLE_NO_BLOCK_RD; + end if; + if rw_state = HANDLE_FILE_DIRENT0 then + file_counter <= file_counter + 1; + elsif rw_state = HANDLE_END_OF_DIRENTS1 and DEBUG_IN(0) = '1' then + file_counter <= (others => '0'); + end if; + if rw_state = HANDLE_FOLDER_DIRENT9 then + find_dirent_addr <= (others => '0'); + elsif rw_state = HANDLE_END_OF_DIR0 then + find_dirent_addr <= find_dirent_addr_rd; + elsif rw_state = HANDLE_END_OF_DIRENTS0 then + find_dirent_addr <= (others => '0'); + elsif rw_state = HANDLE_INTERNAL_ADDR_INC0 then + find_dirent_addr <= find_dirent_addr + "000100000"; + end if; + if rw_state = HANDLE_FOLDER_DIRENT0 then + find_dirent_addr_cache <= find_dirent_addr + "000100000"; + end if; + if rw_state = HANDLE_INTERNAL_ADDR_INC1 then + if find_dirent_block_num = sectors_per_cluster_zero_indexed then + find_dirent_block_num <= (others => '0'); + else + find_dirent_block_num <= find_dirent_block_num + 1; + end if; + elsif rw_state = HANDLE_FOLDER_DIRENT9 then + find_dirent_block_num <= (others => '0'); + elsif rw_state = HANDLE_END_OF_DIR0 then + find_dirent_block_num <= find_dirent_block_num_rd; + end if; + end if; + end process; + + DIRENT_LIFO: process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if rw_next_state = PARSE_NAME_DIRENT0 then + dirent_lifo_rst <= '1'; + else + dirent_lifo_rst <= '0'; + end if; + if rw_state = PARSE_NAME_DIRENT2 then + dirent_lifo_we <= '1'; + elsif rw_state = HANDLE_INTERNAL_ADDR_INC0 then + dirent_lifo_we <= '0'; + end if; + end if; + end process; + + dirent_name_lifo : lifo + Generic Map ( G_LOG2_DEPTH => 7, + G_DATA_SIZE => block_rd_data'length ) + Port Map ( CLK_IN => CLK_IN, + RESET_IN => dirent_lifo_rst, + CACHE_ADDR_IN => dirent_lifo_cache_addr, + GOTO_CACHE_IN => dirent_lifo_goto_cache, + WR_DATA_IN => block_rd_data, + WR_EN_IN => dirent_lifo_we, + RD_DATA_OUT => DIRENT_CHAR_OUT, + RD_EN_IN => RD_DIRENT_NAME_CHAR_IN, + EMPTY_OUT => dirent_lifo_empty, + FULL_OUT => dirent_lifo_full); + + HANDLE_FOLDER_DIRENT: process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if rw_next_state = HANDLE_FOLDER_DIRENT0 or rw_next_state = HANDLE_FILE_DIRENT0 then + dirent_found <= '1'; + else + dirent_found <= '0'; + end if; + if rw_next_state = HANDLE_FOLDER_DIRENT0 then + dirent_is_folder <= '1'; + else + dirent_is_folder <= '0'; + end if; + if rw_state = HANDLE_FOLDER_DIRENT2 then + folder_addr(7 downto 0) <= unsigned(block_rd_data); + elsif rw_state = HANDLE_FOLDER_DIRENT3 then + folder_addr(15 downto 8) <= unsigned(block_rd_data); + elsif rw_state = HANDLE_FOLDER_DIRENT4 then + folder_addr(23 downto 16) <= unsigned(block_rd_data); + elsif rw_state = HANDLE_FOLDER_DIRENT5 then + folder_addr(31 downto 24) <= unsigned(block_rd_data); + end if; + if rw_state = HANDLE_FOLDER_DIRENT6 then + folder_addr_tmp <= (folder_addr - 2); + elsif rw_state = HANDLE_FOLDER_DIRENT7 then + folder_addr_tmp(31 downto 1) <= folder_addr_tmp(30 downto 0); + folder_addr_tmp(0) <= '0'; + end if; + if rw_state = HANDLE_FOLDER_DIRENT8 then + folder_addr_final <= folder_addr_tmp + cluster_begin_addr; + end if; + if rw_state = HANDLE_FOLDER_DIRENT7 or rw_state = HANDLE_INTERNAL_ADDR_INC4 then + spc_counter(7 downto 1) <= spc_counter(6 downto 0); + spc_counter(0) <= '0'; + else + spc_counter <= X"02"; + end if; + + + + end if; + end process; + + HANDLE_BP_CACHING: process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if rw_state = HANDLE_FOLDER_DIRENT0 then + bp_lifo_we <= '1'; + else + bp_lifo_we <= '0'; + end if; + if rw_next_state = HANDLE_END_OF_DIR0 then + bp_lifo_rd <= '1'; + else + bp_lifo_rd <= '0'; + end if; + end if; + end process; + + sd_block_pointer_lifo : lifo + Generic Map ( G_LOG2_DEPTH => 5, + G_DATA_SIZE => sd_block_addr'length ) + Port Map ( CLK_IN => CLK_IN, + RESET_IN => bp_lifo_rst, + CACHE_ADDR_IN => '0', + GOTO_CACHE_IN => '0', + WR_DATA_IN => slv(sd_block_addr), + WR_EN_IN => bp_lifo_we, + RD_DATA_OUT => bp_lifo_block_data, + RD_EN_IN => bp_lifo_rd, + EMPTY_OUT => bp_lifo_empty, + FULL_OUT => open); + + find_addr_lifo_we <= bp_lifo_we; + find_addr_lifo_rd <= bp_lifo_rd; + find_dirent_addr_rd <= unsigned(find_dirent_addr_rd_slv); + + find_dirent_addr_lifo : lifo + Generic Map ( G_LOG2_DEPTH => 5, + G_DATA_SIZE => find_dirent_addr'length ) + Port Map ( CLK_IN => CLK_IN, + RESET_IN => find_addr_lifo_rst, + CACHE_ADDR_IN => '0', + GOTO_CACHE_IN => '0', + WR_DATA_IN => slv(find_dirent_addr_cache), + WR_EN_IN => find_addr_lifo_we, + RD_DATA_OUT => find_dirent_addr_rd_slv, + RD_EN_IN => find_addr_lifo_rd, + EMPTY_OUT => find_addr_lifo_empty, + FULL_OUT => open); + + HANDLE_END_FLAG: process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if rw_state = HANDLE_END_OF_DIRENTS0 then + end_of_dirents <= '1'; + elsif rw_state = FIND_NEXT_DIRENT0 then + end_of_dirents <= '0'; + end if; + end if; + end process; + + GOTO_NEXT_CLUSTER: process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if rw_state = FIND_NEXT_CLUSTER0 then + current_cluster_fat_block_addr <= fat_begin_addr + RESIZE(current_cluster(31 downto 7), 32); + end if; + if rw_state = FIND_NEXT_CLUSTER5 then + current_cluster(7 downto 0) <= unsigned(block_rd_data); + elsif rw_state = FIND_NEXT_CLUSTER6 then + current_cluster(15 downto 8) <= unsigned(block_rd_data); + elsif rw_state = FIND_NEXT_CLUSTER7 then + current_cluster(23 downto 16) <= unsigned(block_rd_data); + elsif rw_state = FIND_NEXT_CLUSTER8 then + current_cluster(31 downto 24) <= unsigned(block_rd_data); -- TODO Check if equal to 0FFFFFFF (end of cluster) ? + elsif rw_state = HANDLE_FOLDER_DIRENT6 then + current_cluster <= folder_addr; + elsif rw_state = WAIT_FOR_INIT_CMPLT or rw_state = HANDLE_END_OF_DIRENTS0 then + current_cluster <= X"00000002"; -- TODO Set to ROOT_DIR_FIRST_CLUSTER_IN ? + elsif rw_state = HANDLE_END_OF_DIR0 then + current_cluster <= current_cluster_rd; + end if; + if rw_state = HANDLE_INTERNAL_ADDR_INC3 then + current_cluster_tmp <= (current_cluster - 2); + elsif rw_state = HANDLE_INTERNAL_ADDR_INC4 then + current_cluster_tmp(31 downto 1) <= current_cluster_tmp(30 downto 0); + current_cluster_tmp(0) <= '0'; + end if; + if rw_state = HANDLE_INTERNAL_ADDR_INC5 then + next_cluster_lba <= current_cluster_tmp + cluster_begin_addr; + end if; + end if; + end process; + + current_cluster_lifo_we <= bp_lifo_we; + current_cluster_lifo_rd <= bp_lifo_rd; + current_cluster_rd <= unsigned(current_cluster_rd_slv); + + current_cluster_lifo : lifo + Generic Map ( G_LOG2_DEPTH => 5, + G_DATA_SIZE => current_cluster'length ) + Port Map ( CLK_IN => CLK_IN, + RESET_IN => current_cluster_lifo_rst, + CACHE_ADDR_IN => '0', + GOTO_CACHE_IN => '0', + WR_DATA_IN => slv(current_cluster), + WR_EN_IN => current_cluster_lifo_we, + RD_DATA_OUT => current_cluster_rd_slv, + RD_EN_IN => current_cluster_lifo_rd, + EMPTY_OUT => current_cluster_lifo_empty, + FULL_OUT => open); + + find_dirent_block_lifo_we <= bp_lifo_we; + find_dirent_block_lifo_rd <= bp_lifo_rd; + find_dirent_block_num_rd <= unsigned(find_dirent_block_num_rd_slv); + + find_dirent_block_num_lifo : lifo + Generic Map ( G_LOG2_DEPTH => 5, + G_DATA_SIZE => find_dirent_block_num'length ) + Port Map ( CLK_IN => CLK_IN, + RESET_IN => find_dirent_block_lifo_rst, + CACHE_ADDR_IN => '0', + GOTO_CACHE_IN => '0', + WR_DATA_IN => slv(find_dirent_block_num), + WR_EN_IN => find_dirent_block_lifo_we, + RD_DATA_OUT => find_dirent_block_num_rd_slv, + RD_EN_IN => find_dirent_block_lifo_rd, + EMPTY_OUT => find_dirent_block_lifo_empty, + FULL_OUT => open); + + LIFO_RST_PROC : process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if rw_state = HANDLE_END_OF_DIRENTS0 then + find_dirent_block_lifo_rst <= '1'; + current_cluster_lifo_rst <= '1'; + find_addr_lifo_rst <= '1'; + bp_lifo_rst <= '1'; + else + find_dirent_block_lifo_rst <= '0'; + current_cluster_lifo_rst <= '0'; + find_addr_lifo_rst <= '0'; + bp_lifo_rst <= '0'; + end if; + end if; + end process; + +----------- MAIN FSM ------------ + + MAIN_ROUTINE_SYNC: process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if RESET_IN = '0' then + rw_state <= rw_next_state; + else + rw_state <= IDLE_W_BLOCK_RD; + end if; + end if; + end process; + + MAIN_ROUTINE_DECODE: process ( sd_init_cmplt, + block_rd_cmplt, + block_rd_cmplt + ) + begin + rw_next_state <= rw_state; -- default is to stay in current state + case (rw_state) is + when REPORT_ERROR => + rw_next_state <= WAIT_FOR_INIT_CMPLT; + when WAIT_FOR_INIT_CMPLT => + if sd_init_cmplt = '1' then + rw_next_state <= IDLE_W_BLOCK_RD; + end if; + + when IDLE_W_BLOCK_RD => + if get_next_dirent = '1' then + rw_next_state <= FIND_NEXT_DIRENT0; + end if; + when IDLE_NO_BLOCK_RD => + if get_next_dirent = '1' then + rw_next_state <= FIND_NEXT_DIRENT2; + end if; + + when FIND_NEXT_DIRENT0 => + rw_next_state <= FIND_NEXT_DIRENT1; + when FIND_NEXT_DIRENT1 => + if block_rd_cmplt = '1' then + rw_next_state <= FIND_NEXT_DIRENT2; + end if; + when FIND_NEXT_DIRENT2 => + rw_next_state <= FIND_NEXT_DIRENT3; + when FIND_NEXT_DIRENT3 => + rw_next_state <= FIND_NEXT_DIRENT4; + when FIND_NEXT_DIRENT4 => + if block_rd_data = C_unused_entry then + rw_next_state <= FIND_NEXT_DIRENT6; + elsif block_rd_data = C_end_of_directory then + rw_next_state <= HANDLE_END_OF_DIR0; + else + rw_next_state <= FIND_NEXT_DIRENT5; + end if; + when FIND_NEXT_DIRENT5 => + if block_rd_data /= C_file_name_type then + rw_next_state <= FIND_NEXT_DIRENT6; + else + rw_next_state <= PARSE_NAME_DIRENT0; + end if; + when FIND_NEXT_DIRENT6 => + rw_next_state <= HANDLE_INTERNAL_ADDR_INC0; + + when PARSE_NAME_DIRENT0 => + rw_next_state <= PARSE_NAME_DIRENT1; + when PARSE_NAME_DIRENT1 => + rw_next_state <= PARSE_NAME_DIRENT2; + when PARSE_NAME_DIRENT2 => + rw_next_state <= PARSE_NAME_DIRENT3; + when PARSE_NAME_DIRENT3 => + rw_next_state <= PARSE_NAME_DIRENT4; + when PARSE_NAME_DIRENT4 => + rw_next_state <= PARSE_NAME_DIRENT5; + when PARSE_NAME_DIRENT5 => + rw_next_state <= PARSE_NAME_DIRENT6; + when PARSE_NAME_DIRENT6 => + rw_next_state <= PARSE_NAME_DIRENT7; + when PARSE_NAME_DIRENT7 => + rw_next_state <= PARSE_NAME_DIRENT8; + when PARSE_NAME_DIRENT8 => + rw_next_state <= PARSE_NAME_DIRENT9; + when PARSE_NAME_DIRENT9 => + rw_next_state <= PARSE_NAME_DIRENT10; + when PARSE_NAME_DIRENT10 => + rw_next_state <= PARSE_NAME_DIRENT11; + when PARSE_NAME_DIRENT11 => + rw_next_state <= PARSE_NAME_DIRENT12; + when PARSE_NAME_DIRENT12 => + rw_next_state <= PARSE_NAME_DIRENT13; + when PARSE_NAME_DIRENT13 => + rw_next_state <= PARSE_NAME_DIRENT14; + when PARSE_NAME_DIRENT14 => + rw_next_state <= HANDLE_INTERNAL_ADDR_INC0; + when PARSE_NAME_DIRENT15 => + rw_next_state <= PARSE_NAME_DIRENT16; + when PARSE_NAME_DIRENT16 => + rw_next_state <= PARSE_NAME_DIRENT17; + when PARSE_NAME_DIRENT17 => + if block_rd_data = C_file_name_type then + rw_next_state <= PARSE_NAME_DIRENT1; + elsif block_rd_data(7 downto 4) = C_folder_type(7 downto 4) then + rw_next_state <= HANDLE_FOLDER_DIRENT0; + elsif block_rd_data(7 downto 4) = C_file_type(7 downto 4) then + rw_next_state <= HANDLE_FILE_DIRENT0; -- TODO create 'else' case to prevent lockups + end if; + + when HANDLE_FILE_DIRENT0 => + rw_next_state <= HANDLE_INTERNAL_ADDR_INC0; + + when HANDLE_END_OF_DIR0 => + if bp_lifo_empty = '0' then + rw_next_state <= HANDLE_END_OF_DIR1; + else + rw_next_state <= HANDLE_END_OF_DIRENTS0; + end if; + when HANDLE_END_OF_DIR1 => + rw_next_state <= HANDLE_END_OF_DIR2; + when HANDLE_END_OF_DIR2 => + rw_next_state <= HANDLE_END_OF_DIR3; + when HANDLE_END_OF_DIR3 => + rw_next_state <= IDLE_W_BLOCK_RD; + + when HANDLE_FOLDER_DIRENT0 => + rw_next_state <= HANDLE_FOLDER_DIRENT1; + when HANDLE_FOLDER_DIRENT1 => + rw_next_state <= HANDLE_FOLDER_DIRENT2; + when HANDLE_FOLDER_DIRENT2 => + rw_next_state <= HANDLE_FOLDER_DIRENT3; + when HANDLE_FOLDER_DIRENT3 => + rw_next_state <= HANDLE_FOLDER_DIRENT4; + when HANDLE_FOLDER_DIRENT4 => + rw_next_state <= HANDLE_FOLDER_DIRENT5; + when HANDLE_FOLDER_DIRENT5 => + rw_next_state <= HANDLE_FOLDER_DIRENT6; + when HANDLE_FOLDER_DIRENT6 => + rw_next_state <= HANDLE_FOLDER_DIRENT7; + when HANDLE_FOLDER_DIRENT7 => + if spc_counter = sectors_per_cluster then + rw_next_state <= HANDLE_FOLDER_DIRENT8; + end if; + when HANDLE_FOLDER_DIRENT8 => + rw_next_state <= HANDLE_FOLDER_DIRENT9; + when HANDLE_FOLDER_DIRENT9 => + rw_next_state <= IDLE_W_BLOCK_RD; + + when HANDLE_END_OF_DIRENTS0 => + rw_next_state <= HANDLE_END_OF_DIRENTS1; + when HANDLE_END_OF_DIRENTS1 => + if DEBUG_IN(0) = '1' then + rw_next_state <= IDLE_W_BLOCK_RD; + end if; + + when HANDLE_INTERNAL_ADDR_INC0 => + if find_dirent_addr(8 downto 5) = "1111" then + rw_next_state <= HANDLE_INTERNAL_ADDR_INC1; + else + rw_next_state <= rw_state_cached; + end if; + when HANDLE_INTERNAL_ADDR_INC1 => + if find_dirent_block_num = sectors_per_cluster_zero_indexed then + rw_next_state <= FIND_NEXT_CLUSTER0; + else + rw_next_state <= HANDLE_INTERNAL_ADDR_INC2; + end if; + when HANDLE_INTERNAL_ADDR_INC2 => + if block_rd_cmplt = '1' then + rw_next_state <= rw_state_cached; + end if; + when HANDLE_INTERNAL_ADDR_INC3 => + rw_next_state <= HANDLE_INTERNAL_ADDR_INC4; + when HANDLE_INTERNAL_ADDR_INC4 => + if spc_counter = sectors_per_cluster then + rw_next_state <= HANDLE_INTERNAL_ADDR_INC5; + end if; + when HANDLE_INTERNAL_ADDR_INC5 => + rw_next_state <= HANDLE_INTERNAL_ADDR_INC6; + when HANDLE_INTERNAL_ADDR_INC6 => + rw_next_state <= HANDLE_INTERNAL_ADDR_INC7; + when HANDLE_INTERNAL_ADDR_INC7 => + if block_rd_cmplt = '1' then + rw_next_state <= rw_state_cached; + end if; + + when FIND_NEXT_CLUSTER0 => + rw_next_state <= FIND_NEXT_CLUSTER1; + when FIND_NEXT_CLUSTER1 => + rw_next_state <= FIND_NEXT_CLUSTER2; + when FIND_NEXT_CLUSTER2 => + if block_rd_cmplt = '1' then + rw_next_state <= FIND_NEXT_CLUSTER3; + end if; + when FIND_NEXT_CLUSTER3 => + rw_next_state <= FIND_NEXT_CLUSTER4; + when FIND_NEXT_CLUSTER4 => + rw_next_state <= FIND_NEXT_CLUSTER5; + when FIND_NEXT_CLUSTER5 => + rw_next_state <= FIND_NEXT_CLUSTER6; + when FIND_NEXT_CLUSTER6 => + rw_next_state <= FIND_NEXT_CLUSTER7; + when FIND_NEXT_CLUSTER7 => + rw_next_state <= FIND_NEXT_CLUSTER8; + when FIND_NEXT_CLUSTER8 => + rw_next_state <= FIND_NEXT_CLUSTER9; + when FIND_NEXT_CLUSTER9 => + rw_next_state <= HANDLE_INTERNAL_ADDR_INC3; + + end case; + end process; + +----------- BLOCK READ FSM ------------ + + BLOCK_READ_SYNC: process(CLK_IN) + begin + if rising_edge(CLK_IN) then + br_state <= br_next_state; + end if; + end process; + + BLOCK_READ_FLAGS: process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if br_state = READ_BYTE0 and rd_byte_ack = '1' then + block_rd_we <= '1'; + else + block_rd_we <= '0'; + end if; + if br_state = READ_BYTE1 then + rd_byte <= '1'; + elsif br_state = READ_BYTE2 and rd_byte_ack = '0' then + rd_byte <= '0'; + end if; + if br_state = IDLE then + block_wr_addr <= (others => '0'); + elsif br_state = READ_BYTE1 then + block_wr_addr <= block_wr_addr + 1; + end if; + if br_state = READ_BYTE4 then + block_rd_cmplt <= '1'; + else + block_rd_cmplt <= '0'; + end if; + if br_state = WAIT_UNTIL_BLOCK_READ_ACKD then + sd_block_rd <= '1'; + else + sd_block_rd <= '0'; + end if; + end if; + end process; + + BLOCK_READ_DECODE: process (br_state, perform_block_rd, rd_byte_ack, block_wr_addr) + begin + br_next_state <= br_state; -- default is to stay in current state + case (br_state) is + when IDLE => + if perform_block_rd = '1' then + br_next_state <= WAIT_UNTIL_NOT_BUSY; + end if; + when WAIT_UNTIL_NOT_BUSY => + if sd_busy = '0' then + br_next_state <= WAIT_UNTIL_BLOCK_READ_ACKD; + end if; + when WAIT_UNTIL_BLOCK_READ_ACKD => + if sd_busy = '1' then + br_next_state <= READ_BYTE0; + end if; + when READ_BYTE0 => + if rd_byte_ack = '1' then + br_next_state <= READ_BYTE1; + end if; + when READ_BYTE1 => + br_next_state <= READ_BYTE2; + when READ_BYTE2 => + if rd_byte_ack = '0' then + br_next_state <= READ_BYTE3; + end if; + when READ_BYTE3 => + if block_wr_addr = "000000000" then + br_next_state <= READ_BYTE4; + else + br_next_state <= READ_BYTE0; + end if; + when READ_BYTE4 => + br_next_state <= IDLE; + end case; + end process; + + Block_Ram_Inst : TDP_RAM + Generic Map ( G_DATA_A_SIZE => sd_data'length, + G_ADDR_A_SIZE => block_wr_addr'length, + G_RELATION => 0, + G_INIT_FILE => "") --log2(SIZE_A/SIZE_B) + Port Map ( CLK_A_IN => CLK_IN, + WE_A_IN => block_rd_we, + ADDR_A_IN => slv(block_wr_addr), + DATA_A_IN => sd_data, + DATA_A_OUT => open, + CLK_B_IN => CLK_IN, + WE_B_IN => '0', + ADDR_B_IN => slv(block_rd_addr), + DATA_B_IN => X"00", + DATA_B_OUT => block_rd_data); + + --DEBUG_OUT2(0) <= '1' when rw_state = PARSE_NAME_DIRENT17 else '0'; + + DEBUG_OUT2(5 downto 0) <= slv(state_debug_sig); + DEBUG_OUT2(7) <= sd_busy; + + + DEBUG_OUT <= slv(file_counter(15 downto 0)); + +end Behavioral; + Index: fat_32_file_parser/trunk/CLK_Mod.vhd =================================================================== --- fat_32_file_parser/trunk/CLK_Mod.vhd (nonexistent) +++ fat_32_file_parser/trunk/CLK_Mod.vhd (revision 2) @@ -0,0 +1,90 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 10:16:23 10/19/2014 +-- Design Name: +-- Module Name: clk_mod - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +library UNISIM; +use UNISIM.VComponents.all; + +entity clk_mod is + Port ( CLK_50MHz_IN : in STD_LOGIC; + CLK_25Mhz_OUT : out STD_LOGIC); +end clk_mod; + +architecture Behavioral of clk_mod is + +signal clk0_div2out_bufg, clk0_2xout_tmp, clk0_2xout_bufg :std_logic:='0'; + +begin + + --CLK_100Mhz_OUT <= clk0_2xout_bufg; + + U0_BUFG : BUFG + port map (I => clk0_2xout_tmp, O => clk0_2xout_bufg); + + U1_BUFG : BUFG + port map (I => clk0_div2out_bufg, O => CLK_25Mhz_OUT); + + DCM_SP_inst : DCM_SP + generic map ( + CLKDV_DIVIDE => 2.0, -- CLKDV divide value (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16). + CLKFX_DIVIDE => 1, -- Divide value on CLKFX outputs - D - (1-32) + CLKFX_MULTIPLY => 2, -- Multiply value on CLKFX outputs - M - (2-32) + CLKIN_DIVIDE_BY_2 => FALSE, -- CLKIN divide by two (TRUE/FALSE) + CLKIN_PERIOD => 20.0, -- Input clock period specified in nS + CLKOUT_PHASE_SHIFT => "NONE", -- Output phase shift (NONE, FIXED, VARIABLE) + CLK_FEEDBACK => "2X", -- Feedback source (NONE, 1X, 2X) + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS + DFS_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value + DLL_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value + DSS_MODE => "NONE", -- Unsupported - Do not change value + DUTY_CYCLE_CORRECTION => TRUE, -- Unsupported - Do not change value + FACTORY_JF => X"c080", -- Unsupported - Do not change value + PHASE_SHIFT => 0, -- Amount of fixed phase shift (-255 to 255) + STARTUP_WAIT => FALSE -- Delay configock frequency clock output + ) + port map ( + CLK2X180 => open, -- 1-bit output: 2X clock frequency, 180 degree clock output + CLK90 => open, -- 1-bit output: 90 degree clock output + CLKDV => clk0_div2out_bufg, -- 1-bit output: Divided clock output + CLKFX => open, -- 1-bit output: Digital Frequency Synthesizer output (DFS) + CLKFX180 => open, -- 1-bit output: 180 degree CLKFX output + LOCKED => open, -- 1-bit output: DCM_SP Lock Output + PSDONE => open, -- 1-bit output: Phase shift done output + STATUS => open, -- 8-bit output: DCM_SP status output + CLKFB => clk0_2xout_bufg, -- 1-bit input: Cl DONE until DCM_SP LOCKED (TRUE/FALSE) + CLK0 => open, -- 1-bit output: 0 degree clock output + CLK180 => open, -- 1-bit output: 180 degree clock output + CLK270 => open, -- 1-bit output: 270 degree clock output + CLK2X => clk0_2xout_tmp, -- 1-bit output: 2X clock feedback input + CLKIN => CLK_50MHz_IN, -- 1-bit input: Clock input + DSSEN => '0', -- 1-bit input: Unsupported, specify to GND. + PSCLK => '0', -- 1-bit input: Phase shift clock input + PSEN => '0', -- 1-bit input: Phase shift enable + PSINCDEC => '0', -- 1-bit input: Phase shift increment/decrement input + RST => '0' -- 1-bit input: Active high reset input + ); + +end Behavioral; + Index: fat_32_file_parser/trunk/SyncToClk.vhd =================================================================== --- fat_32_file_parser/trunk/SyncToClk.vhd (nonexistent) +++ fat_32_file_parser/trunk/SyncToClk.vhd (revision 2) @@ -0,0 +1,107 @@ +---------------------------------------------------------------------------------- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License +-- as published by the Free Software Foundation; either version 2 +-- of the License, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA +-- 02111-1307, USA. +-- +-- �2011 - X Engineering Software Systems Corp. (www.xess.com) +---------------------------------------------------------------------------------- + +---------------------------------------------------------------------------------- +-- Modules for passing bits into a clock domain. +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +package SyncToClockPckg is + + -- Pass a bit into a clock domain. + component SyncToClock is + port ( + clk_i : in std_logic; -- Clock for the domain being entered. + unsynced_i : in std_logic; -- Signal that is entering domain. + synced_o : out std_logic -- Signal sync'ed to clock domain + ); + end component; + + -- Pass a bus into a clock domain. + component SyncBusToClock is + port ( + clk_i : in std_logic; -- Clock for the domain being entered. + unsynced_i : in std_logic_vector; -- Bus signal that is entering domain. + synced_o : out std_logic_vector -- Bus signal sync'ed to clock domain + ); + end component; + +end package; + + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity SyncToClock is + port ( + clk_i : in std_logic; -- Clock for the domain being entered. + unsynced_i : in std_logic; -- Signal that is entering domain. + synced_o : out std_logic -- Signal sync'ed to clock domain + ); +end entity; + + +architecture arch of SyncToClock is + constant syncStages_c : natural := 2; -- Number of stages in the sync'ing register. + -- This is the sync'ing shift register. The index indicates the number of clocked flip-flops the incoming signal + -- has passed through, so sync_r(1) is one clk_i cycle stage, sync_r(2) is two cycles, etc. + signal sync_r : std_logic_vector(syncStages_c downto 1); +begin + process(clk_i) + begin + if rising_edge(clk_i) then + -- Shift the unsync'ed signal into one end of the sync'ing register. + sync_r <= sync_r(syncStages_c-1 downto 1) & unsynced_i; + end if; + end process; + -- Output the sync'ed signal from the other end of the shift register. + synced_o <= sync_r(syncStages_c); +end architecture; + + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use work.SyncToClockPckg.all; + +entity SyncBusToClock is + port ( + clk_i : in std_logic; -- Clock for the domain being entered. + unsynced_i : in std_logic_vector; -- Bus signal that is entering domain. + synced_o : out std_logic_vector -- Bus signal sync'ed to clock domain + ); +end entity; + + +architecture arch of SyncBusToClock is +begin + SyncLoop : for i in unsynced_i'range generate + begin + USyncBit : component SyncToClock + port map( + clk_i => clk_i, + unsynced_i => unsynced_i(i), + synced_o => synced_o(i) + ); + end generate; +end architecture; Index: fat_32_file_parser/trunk/uart.vhd =================================================================== --- fat_32_file_parser/trunk/uart.vhd (nonexistent) +++ fat_32_file_parser/trunk/uart.vhd (revision 2) @@ -0,0 +1,264 @@ +---------------------------------------------------------------------------------- +-- Creation Date: 21:12:48 05/06/2010 +-- Module Name: RS232/UART Interface - Behavioral +-- Used TAB of 4 Spaces +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity uart is +generic ( + CLK_FREQ : integer := 50; -- Main frequency (MHz) + SER_FREQ : integer := 9600 -- Baud rate (bps) +); +port ( + -- Control + clk : in std_logic; -- Main clock + rst : in std_logic; -- Main reset + -- External Interface + rx : in std_logic; -- RS232 received serial data + tx : out std_logic; -- RS232 transmitted serial data + -- RS232/UART Configuration + par_en : in std_logic; -- Parity bit enable + -- uPC Interface + tx_req : in std_logic; -- Request SEND of data + tx_end : out std_logic; -- Data SENDED + tx_data : in std_logic_vector(7 downto 0); -- Data to transmit + rx_ready : out std_logic; -- Received data ready to uPC read + rx_data : out std_logic_vector(7 downto 0) -- Received data +); +end uart; + +architecture Behavioral of uart is + + -- Constants + constant UART_IDLE : std_logic := '1'; + constant UART_START : std_logic := '0'; + constant PARITY_EN : std_logic := '1'; + constant RST_LVL : std_logic := '1'; + + -- Types + type state is (idle,data,parity,stop1,stop2); -- Stop1 and Stop2 are inter frame gap signals + + -- RX Signals + signal rx_fsm : state; -- Control of reception + signal rx_clk_en : std_logic; -- Received clock enable + signal rx_rcv_init : std_logic; -- Start of reception + signal rx_par_bit : std_logic; -- Calculated Parity bit + signal rx_data_deb : std_logic; -- Debounce RX data + signal rx_data_tmp : std_logic_vector(7 downto 0); -- Serial to parallel converter + signal rx_data_cnt : std_logic_vector(2 downto 0); -- Count received bits + + -- TX Signals + signal tx_fsm : state; -- Control of transmission + signal tx_clk_en : std_logic; -- Transmited clock enable + signal tx_par_bit : std_logic; -- Calculated Parity bit + signal tx_data_tmp : std_logic_vector(7 downto 0); -- Parallel to serial converter + signal tx_data_cnt : std_logic_vector(2 downto 0); -- Count transmited bits + +begin + + tx_clk_gen:process(clk) + variable counter : integer range 0 to conv_integer((CLK_FREQ*1_000_000)/SER_FREQ-1); + begin + if clk'event and clk = '1' then + -- Normal Operation + if counter = (CLK_FREQ*1_000_000)/SER_FREQ-1 then + tx_clk_en <= '1'; + counter := 0; + else + tx_clk_en <= '0'; + counter := counter + 1; + end if; + -- Reset condition + if rst = RST_LVL then + tx_clk_en <= '0'; + counter := 0; + end if; + end if; + end process; + + tx_proc:process(clk) + variable data_cnt : std_logic_vector(2 downto 0); + begin + if clk'event and clk = '1' then + if tx_clk_en = '1' then + -- Default values + tx_end <= '0'; + tx <= UART_IDLE; + -- FSM description + case tx_fsm is + -- Wait to transfer data + when idle => + -- Send Init Bit + if tx_req = '1' then + tx <= UART_START; + tx_data_tmp <= tx_data; + tx_fsm <= data; + tx_data_cnt <= (others=>'1'); + tx_par_bit <= '0'; + end if; + -- Data receive + when data => + tx <= tx_data_tmp(0); + tx_par_bit <= tx_par_bit xor tx_data_tmp(0); + if tx_data_cnt = 0 then + if par_en = PARITY_EN then + tx_fsm <= parity; + else + tx_fsm <= stop1; + end if; + tx_data_cnt <= (others=>'1'); + else + tx_data_tmp <= '0' & tx_data_tmp(7 downto 1); + tx_data_cnt <= tx_data_cnt - 1; + end if; + when parity => + tx <= tx_par_bit; + tx_fsm <= stop1; + -- End of communication + when stop1 => + -- Send Stop Bit + tx <= UART_IDLE; + tx_fsm <= stop2; + when stop2 => + -- Send Stop Bit + tx_end <= '1'; + tx <= UART_IDLE; + tx_fsm <= idle; + -- Invalid States + when others => null; + end case; + -- Reset condition + if rst = RST_LVL then + tx_fsm <= idle; + tx_par_bit <= '0'; + tx_data_tmp <= (others=>'0'); + tx_data_cnt <= (others=>'0'); + end if; + end if; + end if; + end process; + + rx_debounceer:process(clk) + variable deb_buf : std_logic_vector(3 downto 0); + begin + if clk'event and clk = '1' then + -- Debounce logic + if deb_buf = "0000" then + rx_data_deb <= '0'; + elsif deb_buf = "1111" then + rx_data_deb <= '1'; + end if; + -- Data storage to debounce + deb_buf := deb_buf(2 downto 0) & rx; + end if; + end process; + + rx_start_detect:process(clk) + variable rx_data_old : std_logic; + begin + if clk'event and clk = '1' then + -- Falling edge detection + if rx_data_old = '1' and rx_data_deb = '0' and rx_fsm = idle then + rx_rcv_init <= '1'; + else + rx_rcv_init <= '0'; + end if; + -- Default assignments + rx_data_old := rx_data_deb; + -- Reset condition + if rst = RST_LVL then + rx_data_old := '0'; + rx_rcv_init <= '0'; + end if; + end if; + end process; + + + rx_clk_gen:process(clk) + variable counter : integer range 0 to conv_integer((CLK_FREQ*1_000_000)/SER_FREQ-1); + begin + if clk'event and clk = '1' then + -- Normal Operation + if counter = (CLK_FREQ*1_000_000)/SER_FREQ-1 or rx_rcv_init = '1' then + rx_clk_en <= '1'; + counter := 0; + else + rx_clk_en <= '0'; + counter := counter + 1; + end if; + -- Reset condition + if rst = RST_LVL then + rx_clk_en <= '0'; + counter := 0; + end if; + end if; + end process; + + rx_proc:process(clk) + begin + if clk'event and clk = '1' then + -- Default values + rx_ready <= '0'; + -- Enable on UART rate + if rx_clk_en = '1' then + -- FSM description + case rx_fsm is + -- Wait to transfer data + when idle => + if rx_data_deb = UART_START then + rx_fsm <= data; + end if; + rx_par_bit <= '0'; + rx_data_cnt <= (others=>'0'); + -- Data receive + when data => + -- Check data to generate parity + if par_en = PARITY_EN then + rx_par_bit <= rx_par_bit xor rx; + end if; + + if rx_data_cnt = 7 then + -- Data path + rx_data(7) <= rx; + for i in 0 to 6 loop + rx_data(i) <= rx_data_tmp(6-i); + end loop; + + -- With parity verification + if par_en = PARITY_EN then + rx_fsm <= parity; + -- Without parity verification + else + rx_ready <= '1'; + rx_fsm <= idle; + end if; + else + rx_data_tmp <= rx_data_tmp(6 downto 0) & rx; + rx_data_cnt <= rx_data_cnt + 1; + end if; + when parity => + -- Check received parity + rx_fsm <= idle; + if rx_par_bit = rx then + rx_ready <= '1'; + end if; + when others => null; + end case; + -- Reset condition + if rst = RST_LVL then + rx_fsm <= idle; + rx_ready <= '0'; + rx_data <= (others=>'0'); + rx_data_tmp <= (others=>'0'); + rx_data_cnt <= (others=>'0'); + end if; + end if; + end if; + end process; + +end Behavioral; + Index: fat_32_file_parser/trunk/README.md =================================================================== --- fat_32_file_parser/trunk/README.md (nonexistent) +++ fat_32_file_parser/trunk/README.md (revision 2) @@ -0,0 +1,10 @@ +# VHDL_FAT_32_Parser +Hardware transversal of FAT32 Filesystem + +## Dependencies +- Xilinx ISE +- Numato Mimas V2 [link](http://numato.com/mimas-v2-spartan-6-fpga-development-board-with-ddr-sdram/) +- SD Card formatted as FAT32 + +## Notes +Currently under development Index: fat_32_file_parser/trunk/TB_lifo.vhd =================================================================== --- fat_32_file_parser/trunk/TB_lifo.vhd (nonexistent) +++ fat_32_file_parser/trunk/TB_lifo.vhd (revision 2) @@ -0,0 +1,233 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 22:03:37 11/18/2014 +-- Design Name: +-- Module Name: /home/craig/Documents/CW/Git_Repos/sd_card/TB_lifo.vhd +-- Project Name: hw_client +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: lifo +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY TB_lifo IS +END TB_lifo; + +ARCHITECTURE behavior OF TB_lifo IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT lifo + PORT( + CLK_IN : IN std_logic; + RESET_IN : IN std_logic; + CACHE_ADDR_IN : IN std_logic; + GOTO_CACHE_IN : IN std_logic; + WR_DATA_IN : IN std_logic_vector(7 downto 0); + WR_EN_IN : IN std_logic; + RD_DATA_OUT : OUT std_logic_vector(7 downto 0); + RD_EN_IN : IN std_logic; + EMPTY_OUT : OUT std_logic; + FULL_OUT : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal CLK_IN : std_logic := '0'; + signal RESET_IN : std_logic := '0'; + signal CACHE_ADDR_IN : std_logic := '0'; + signal GOTO_CACHE_IN : std_logic := '0'; + signal WR_DATA_IN : std_logic_vector(7 downto 0) := (others => '0'); + signal WR_EN_IN : std_logic := '0'; + signal RD_EN_IN : std_logic := '0'; + + --Outputs + signal RD_DATA_OUT : std_logic_vector(7 downto 0); + signal EMPTY_OUT : std_logic; + signal FULL_OUT : std_logic; + + -- Clock period definitions + constant CLK_IN_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: lifo PORT MAP ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + CACHE_ADDR_IN => CACHE_ADDR_IN, + GOTO_CACHE_IN => GOTO_CACHE_IN, + WR_DATA_IN => WR_DATA_IN, + WR_EN_IN => WR_EN_IN, + RD_DATA_OUT => RD_DATA_OUT, + RD_EN_IN => RD_EN_IN, + EMPTY_OUT => EMPTY_OUT, + FULL_OUT => FULL_OUT + ); + + -- Clock process definitions + CLK_IN_process :process + begin + CLK_IN <= '0'; + wait for CLK_IN_period/2; + CLK_IN <= '1'; + wait for CLK_IN_period/2; + end process; + +-- stim_proc: process +-- begin +-- +-- wait for CLK_IN_period*10; +-- +-- WR_DATA_IN <= X"81"; +-- WR_EN_IN <= '1'; +-- wait for CLK_IN_period; +-- WR_EN_IN <= '0'; +-- wait for CLK_IN_period * 5; +-- +-- WR_DATA_IN <= X"82"; +-- WR_EN_IN <= '1'; +-- wait for CLK_IN_period; +-- WR_EN_IN <= '0'; +-- wait for CLK_IN_period * 5; +-- +-- WR_DATA_IN <= X"83"; +-- WR_EN_IN <= '1'; +-- wait for CLK_IN_period; +-- WR_EN_IN <= '0'; +-- wait for CLK_IN_period * 25; +-- +-- RD_EN_IN <= '1'; +-- wait for CLK_IN_period; +-- RD_EN_IN <= '0'; +-- wait for CLK_IN_period * 5; +-- +-- RD_EN_IN <= '1'; +-- wait for CLK_IN_period; +-- RD_EN_IN <= '0'; +-- wait for CLK_IN_period * 5; +-- +-- RD_EN_IN <= '1'; +-- wait for CLK_IN_period; +-- RD_EN_IN <= '0'; +-- wait for CLK_IN_period * 5; +-- +-- wait; +-- end process; + + -- Stimulus process + stim_proc: process + begin + + wait for CLK_IN_period*10; + + WR_DATA_IN <= X"01"; + WR_EN_IN <= '1'; + wait for CLK_IN_period; + WR_EN_IN <= '0'; + + WR_DATA_IN <= X"02"; + WR_EN_IN <= '1'; + wait for CLK_IN_period; + WR_EN_IN <= '0'; + + WR_DATA_IN <= X"03"; + WR_EN_IN <= '1'; + wait for CLK_IN_period; + WR_EN_IN <= '0'; + + WR_DATA_IN <= X"11"; + WR_EN_IN <= '1'; + wait for CLK_IN_period; + WR_EN_IN <= '0'; + + WR_DATA_IN <= X"12"; + WR_EN_IN <= '1'; + wait for CLK_IN_period; + WR_DATA_IN <= X"13"; + WR_EN_IN <= '1'; + wait for CLK_IN_period; + WR_DATA_IN <= X"14"; + WR_EN_IN <= '1'; + wait for CLK_IN_period; + WR_EN_IN <= '0'; + + wait for CLK_IN_period; + RD_EN_IN <= '1'; + wait for CLK_IN_period; + RD_EN_IN <= '0'; + + wait for CLK_IN_period; + RD_EN_IN <= '1'; + wait for CLK_IN_period; + RD_EN_IN <= '0'; + + wait for CLK_IN_period; + RD_EN_IN <= '1'; + wait for CLK_IN_period; + RD_EN_IN <= '0'; + + wait for CLK_IN_period; + RD_EN_IN <= '1'; + wait for CLK_IN_period; + RD_EN_IN <= '0'; + + wait for CLK_IN_period * 2; + RD_EN_IN <= '0'; + wait for CLK_IN_period * 4; + + CACHE_ADDR_IN <= '1'; + wait for CLK_IN_period; + CACHE_ADDR_IN <= '0'; + + RD_EN_IN <= '1'; + wait for CLK_IN_period * 20; + RD_EN_IN <= '0'; + + wait for CLK_IN_period; + GOTO_CACHE_IN <= '1'; + wait for CLK_IN_period; + GOTO_CACHE_IN <= '0'; + + wait for CLK_IN_period * 20; + RD_EN_IN <= '1'; + wait for CLK_IN_period * 20; + RD_EN_IN <= '0'; + + wait for CLK_IN_period; + GOTO_CACHE_IN <= '1'; + wait for CLK_IN_period; + GOTO_CACHE_IN <= '0'; + + wait for CLK_IN_period; + RESET_IN <= '1'; + wait for CLK_IN_period; + RESET_IN <= '0'; + + wait; + end process; + +END; Index: fat_32_file_parser/trunk/losr.vhd =================================================================== --- fat_32_file_parser/trunk/losr.vhd (nonexistent) +++ fat_32_file_parser/trunk/losr.vhd (revision 2) @@ -0,0 +1,63 @@ +-- Hi Emacs, this is -*- mode: vhdl -*- +---------------------------------------------------------------------------------------------------- +-- +-- Registro de desplazamiento a la izquierda, entrada paralelo, salida serie +-- +-- Copyright (c) 2007 Javier Valcarce Garc�a, javier.valcarce@gmail.com +-- $Id$ +-- +---------------------------------------------------------------------------------------------------- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU Lesser General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. + +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU Lesser General Public License for more details. +-- +-- You should have received a copy of the GNU Lesser General Public License +-- along with this program. If not, see . +---------------------------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + + +entity losr is + generic ( + N : integer := 4); + port ( + reset : in std_logic; + clk : in std_logic; + load : in std_logic; + ce : in std_logic; + do : out std_logic; + di : in std_logic_vector(N-1 downto 0)); +end losr; + + +architecture arch of losr is +begin + + process(reset, clk) + variable data : std_logic_vector(N-1 downto 0); + begin + if reset = '1' then + data := (others => '0'); + elsif rising_edge(clk) then + if load = '1' then + data := di; + elsif ce = '1' then + data := data(N-2 downto 0) & "0"; + end if; + end if; + + do <= data(N-1); + end process; + +end arch; Index: fat_32_file_parser/trunk/vga80x40.vhd =================================================================== --- fat_32_file_parser/trunk/vga80x40.vhd (nonexistent) +++ fat_32_file_parser/trunk/vga80x40.vhd (revision 2) @@ -0,0 +1,303 @@ +-- Hi Emacs, this is -*- mode: vhdl; -*- +---------------------------------------------------------------------------------------------------- +-- +-- Monocrome Text Mode Video Controller VHDL Macro +-- 80x40 characters. Pixel resolution is 640x480/60Hz +-- +-- Copyright (c) 2007 Javier Valcarce Garca, javier.valcarce@gmail.com +-- $Id$ +-- +---------------------------------------------------------------------------------------------------- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU Lesser General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. + +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU Lesser General Public License for more details. +-- +-- You should have received a copy of the GNU Lesser General Public License +-- along with this program. If not, see . +---------------------------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity vga80x40 is + port ( + reset : in std_logic; + clk25MHz : in std_logic; + TEXT_A : out std_logic_vector(11 downto 0); -- text buffer + TEXT_D : in std_logic_vector(07 downto 0); + FONT_A : out std_logic_vector(11 downto 0); -- font buffer + FONT_D : in std_logic_vector(07 downto 0); + -- + ocrx : in std_logic_vector(07 downto 0); -- OUTPUT regs + ocry : in std_logic_vector(07 downto 0); + octl : in std_logic_vector(07 downto 0); + -- + R : out std_logic; + G : out std_logic; + B : out std_logic; + hsync : out std_logic; + vsync : out std_logic + ); +end vga80x40; + + + +architecture rtl of vga80x40 is + + signal R_int : std_logic; + signal G_int : std_logic; + signal B_int : std_logic; + signal hsync_int : std_logic; + signal vsync_int : std_logic; + + signal blank : std_logic; + signal hctr : integer range 793 downto 0; + signal vctr : integer range 524 downto 0; + -- character/pixel position on the screen + signal scry : integer range 039 downto 0; -- chr row < 40 (6 bits) + signal scrx : integer range 079 downto 0; -- chr col < 80 (7 bits) + signal chry : integer range 011 downto 0; -- chr high < 12 (4 bits) + signal chrx : integer range 007 downto 0; -- chr width < 08 (3 bits) + + signal losr_ce : std_logic; + signal losr_ld : std_logic; + signal losr_do : std_logic; + signal y : std_logic; -- character luminance pixel value (0 or 1) + + -- control io register + signal ctl : std_logic_vector(7 downto 0); + signal vga_en : std_logic; + signal cur_en : std_logic; + signal cur_mode : std_logic; + signal cur_blink : std_logic; + signal ctl_r : std_logic; + signal ctl_g : std_logic; + signal ctl_b : std_logic; + + component ctrm + generic ( + M : integer := 08); + port ( + reset : in std_logic; -- asyncronous reset + clk : in std_logic; + ce : in std_logic; -- enable counting + rs : in std_logic; -- syncronous reset + do : out integer range (M-1) downto 0 + ); + end component; + + component losr + generic ( + N : integer := 04); + port ( + reset : in std_logic; + clk : in std_logic; + load : in std_logic; + ce : in std_logic; + do : out std_logic; + di : in std_logic_vector(N-1 downto 0)); + end component; + +begin + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- hsync generator, initialized with '1' + process (reset, clk25MHz) + begin + if reset = '1' then + hsync_int <= '1'; + elsif rising_edge(clk25MHz) then + + if (hctr > 663) and (hctr < 757) then + hsync_int <= '0'; + else + hsync_int <= '1'; + end if; + + end if; + end process; + + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- vsync generator, initialized with '1' + process (reset, clk25MHz) + begin + if reset = '1' then + vsync_int <= '1'; + elsif rising_edge(clk25MHz) then + if (vctr > 499) and (vctr < 502) then + vsync_int <= '0'; + else + vsync_int <= '1'; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- Blank signal, 0 = no draw, 1 = visible/draw zone + blank <= '0' when (hctr > 639) or (vctr > 479) else '1'; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- flip-flips for sync of R, G y B signal, initialized with '0' + process (reset, clk25MHz) + begin + if reset = '1' then + R <= '0'; + G <= '0'; + B <= '0'; + elsif rising_edge(clk25MHz) then + R <= R_int; + G <= G_int; + B <= B_int; + end if; + end process; + + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + -- Control register. Individual control signal + cur_mode <= octl(4); + cur_blink <= octl(5); + cur_en <= octl(6); + vga_en <= octl(7); + ctl_r <= octl(2); + ctl_g <= octl(1); + ctl_b <= octl(0); + + -- counters, hctr, vctr, srcx, srcy, chrx, chry + -- TODO: OPTIMIZE THIS + counters : block + signal hctr_ce : std_logic; + signal hctr_rs : std_logic; + signal vctr_ce : std_logic; + signal vctr_rs : std_logic; + + signal chrx_ce : std_logic; + signal chrx_rs : std_logic; + signal chry_ce : std_logic; + signal chry_rs : std_logic; + signal scrx_ce : std_logic; + signal scrx_rs : std_logic; + signal scry_ce : std_logic; + signal scry_rs : std_logic; + + signal hctr_639 : std_logic; + signal vctr_479 : std_logic; + signal chrx_007 : std_logic; + signal chry_011 : std_logic; + signal scrx_079 : std_logic; + + -- RAM read, ROM read + signal ram_tmp : integer range 3200 downto 0; --12 bits + signal rom_tmp : integer range 3070 downto 0; + + begin + + U_HCTR : ctrm generic map (M => 794) port map ( + reset =>reset, clk=>clk25MHz, ce =>hctr_ce, rs =>hctr_rs, do => hctr); + + U_VCTR : ctrm generic map (M => 525) port map (reset, clk25MHz, vctr_ce, vctr_rs, vctr); + + hctr_ce <= '1'; + hctr_rs <= '1' when hctr = 793 else '0'; + vctr_ce <= '1' when hctr = 663 else '0'; + vctr_rs <= '1' when vctr = 524 else '0'; + + U_CHRX: ctrm generic map (M => 008) port map (reset, clk25MHz, chrx_ce, chrx_rs, chrx); + U_CHRY: ctrm generic map (M => 012) port map (reset, clk25MHz, chry_ce, chry_rs, chry); + U_SCRX: ctrm generic map (M => 080) port map (reset, clk25MHz, scrx_ce, scrx_rs, scrx); + U_SCRY: ctrm generic map (M => 040) port map (reset, clk25MHz, scry_ce, scry_rs, scry); + + hctr_639 <= '1' when hctr = 639 else '0'; + vctr_479 <= '1' when vctr = 479 else '0'; + chrx_007 <= '1' when chrx = 007 else '0'; + chry_011 <= '1' when chry = 011 else '0'; + scrx_079 <= '1' when scrx = 079 else '0'; + + chrx_rs <= chrx_007 or hctr_639; + chry_rs <= chry_011 or vctr_479; + scrx_rs <= hctr_639; + scry_rs <= vctr_479; + + chrx_ce <= '1' and blank; + scrx_ce <= chrx_007; + chry_ce <= hctr_639 and blank; + scry_ce <= chry_011 and hctr_639; + + + ram_tmp <= scry * 80 + scrx + 1 when ((scrx_079 = '0')) else + scry * 80 when ((chry_011 = '0') and (scrx_079 = '1')) else + 0 when ((chry_011 = '1') and (scrx_079 = '1')); + + TEXT_A <= std_logic_vector(TO_UNSIGNED(ram_tmp, 12)); + + rom_tmp <= TO_INTEGER(unsigned(TEXT_D)) * 12 + chry; + FONT_A <= std_logic_vector(TO_UNSIGNED(rom_tmp, 12)); + + end block; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + + U_LOSR : losr generic map (N => 8) + port map (reset, clk25MHz, losr_ld, losr_ce, losr_do, FONT_D); + + losr_ce <= blank; + losr_ld <= '1' when (chrx = 007) else '0'; + + -- video out, vga_en control signal enable/disable vga signal + R_int <= (ctl_r and y) and blank; + G_int <= (ctl_g and y) and blank; + B_int <= (ctl_b and y) and blank; + + hsync <= hsync_int and vga_en; + vsync <= vsync_int and vga_en; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + + -- Hardware Cursor + hw_cursor : block + signal small : std_logic; + signal curen2 : std_logic; + signal slowclk : std_logic; + signal curpos : std_logic; + signal yint : std_logic; + signal crx_tmp : integer range 079 downto 0; + signal cry_tmp : integer range 039 downto 0; + signal crx : integer range 079 downto 0; + signal cry : integer range 039 downto 0; + signal counter : unsigned(22 downto 0); + begin + + -- slowclk for blink hardware cursor + counter <= counter + 1 when rising_edge(clk25MHz); + slowclk <= counter(22); --2.98Hz + + crx <= TO_INTEGER(unsigned(ocrx(6 downto 0))); + cry <= TO_INTEGER(unsigned(ocry(5 downto 0))); + + -- + curpos <= '1' when (scry = cry) and (scrx = crx) else '0'; + small <= '1' when (chry > 8) else '0'; + curen2 <= (slowclk or (not cur_blink)) and cur_en; + yint <= '1' when cur_mode = '0' else small; + y <= (yint and curpos and curen2) xor losr_do; + + end block; + +end rtl; Index: fat_32_file_parser/trunk/hw_client.gise =================================================================== --- fat_32_file_parser/trunk/hw_client.gise (nonexistent) +++ fat_32_file_parser/trunk/hw_client.gise (revision 2) @@ -0,0 +1,30 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + Index: fat_32_file_parser/trunk/SdCardInit.vhd =================================================================== --- fat_32_file_parser/trunk/SdCardInit.vhd (nonexistent) +++ fat_32_file_parser/trunk/SdCardInit.vhd (revision 2) @@ -0,0 +1,593 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: CW +-- +-- Create Date: 12:30:20 11/16/2014 +-- Design Name: +-- Module Name: SdCardInit - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +library UNISIM; +use UNISIM.VComponents.all; + +entity SdCardInit is + Port ( CLK_IN : in STD_LOGIC; + RESET_IN : in STD_LOGIC; + + SD_PRESENT_BAR_IN : in STD_LOGIC; + SD_INIT_OUT : out STD_LOGIC; + SD_BLOCK_RD_OUT : out STD_LOGIC; + SD_BLOCK_ADDR_OUT : out STD_LOGIC_VECTOR (31 downto 0); + SD_DATA_IN : in STD_LOGIC_VECTOR (7 downto 0); + SD_BUSY_IN : in STD_LOGIC; + SD_BYTE_RD_OUT : out STD_LOGIC; + SD_BYTE_RD_ACK_IN : in STD_LOGIC; + SD_ERROR_IN : in STD_LOGIC_VECTOR (15 downto 0); + SD_INIT_CMPLT_OUT : out STD_LOGIC; + + FAT_BEGIN_ADDR_OUT : out STD_LOGIC_VECTOR (31 downto 0); + SECTORS_PER_FAT_OUT : out STD_LOGIC_VECTOR (31 downto 0); + CLUSTER_BEGIN_ADDR_OUT : out STD_LOGIC_VECTOR (31 downto 0); + SECTORS_PER_CLUSTER_OUT : out STD_LOGIC_VECTOR (7 downto 0); + ROOT_DIR_FIRST_CLUSTER_OUT : out STD_LOGIC_VECTOR (31 downto 0)); +end SdCardInit; + +architecture Behavioral of SdCardInit is + + COMPONENT TDP_RAM + Generic (G_DATA_A_SIZE :natural :=32; + G_ADDR_A_SIZE :natural :=9; + G_RELATION :natural :=3; + G_INIT_FILE :string :="");--log2(SIZE_A/SIZE_B) + Port ( CLK_A_IN : in STD_LOGIC; + WE_A_IN : in STD_LOGIC; + ADDR_A_IN : in STD_LOGIC_VECTOR (G_ADDR_A_SIZE-1 downto 0); + DATA_A_IN : in STD_LOGIC_VECTOR (G_DATA_A_SIZE-1 downto 0); + DATA_A_OUT : out STD_LOGIC_VECTOR (G_DATA_A_SIZE-1 downto 0); + CLK_B_IN : in STD_LOGIC; + WE_B_IN : in STD_LOGIC; + ADDR_B_IN : in STD_LOGIC_VECTOR (G_ADDR_A_SIZE+G_RELATION-1 downto 0); + DATA_B_IN : in STD_LOGIC_VECTOR (G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0); + DATA_B_OUT : out STD_LOGIC_VECTOR (G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0)); + END COMPONENT; + +subtype slv is std_logic_vector; + +------------------------ INIT FSM ----------------------------------- + +constant C_500_ms_startup_delay : unsigned(25 downto 0) := "10"&X"FAF080"; -- zero indexed +constant C_sd_init_attempts : unsigned(3 downto 0) := X"2"; -- zero indexed +constant C_mbr_veracity : std_logic_vector(15 downto 0) := X"AA55"; +constant C_bytes_per_sector : std_logic_vector(15 downto 0) := X"0200"; +constant C_volume_signature : std_logic_vector(15 downto 0) := X"AA55"; + +signal startup_delay_counter : unsigned(25 downto 0) := C_500_ms_startup_delay; +signal startup_delay_cmplt : std_logic := '0'; +signal sd_busy, sd_present, sd_init, sd_rd_block, rd_byte, rd_byte_ack : std_logic := '0'; +signal sd_init_attempts_counter : unsigned(3 downto 0) := X"0"; +signal sd_error : std_logic_vector(15 downto 0) := (others => '0'); +signal sd_data, block_rd_data : std_logic_vector(7 downto 0) := (others => '0'); +signal sd_block_addr : std_logic_vector(31 downto 0) := (others => '0'); +signal init_cmplt : std_logic; + +signal mbr_veracity : std_logic_vector(15 downto 0) := (others => '0'); +signal lba_block_addr : std_logic_vector(31 downto 0) := (others => '0'); +signal num_reserved_sectors, vol_signature : std_logic_vector(15 downto 0); +signal bytes_per_sector : std_logic_vector(15 downto 0); +signal sectors_per_fat : std_logic_vector(30 downto 0); + +signal sectors_per_cluster : unsigned(7 downto 0); +signal fat_begin_lba, cluster_begin_lba : unsigned(31 downto 0); +signal root_dir_cluster : unsigned(31 downto 0); + +type MAIN_ROUTINE is ( REPORT_ERROR, + WAIT_FOR_SD_UNPLUGGED, + IDLE, + SD_INIT0, + SD_INIT1, + SD_INIT2, + SD_INIT3, + CHECK_FILE_SYS_VERACITY0, + CHECK_FILE_SYS_VERACITY1, + CHECK_FILE_SYS_VERACITY2, + CHECK_FILE_SYS_VERACITY3, + CHECK_FILE_SYS_VERACITY4, + CHECK_FILE_SYS_VERACITY5, + CHECK_FILE_SYS_VERACITY6, + GET_LBA_START_ADDR0, + GET_LBA_START_ADDR1, + GET_LBA_START_ADDR2, + GET_LBA_START_ADDR3, + GET_LBA_START_ADDR4, + GET_LBA_START_ADDR5, + GET_LBA_START_ADDR6, + GET_VOLUME_ID_DATA0, + GET_VOLUME_ID_DATA1, + GET_VOLUME_ID_DATA2, + GET_VOLUME_ID_DATA3, + GET_VOLUME_ID_DATA4, + GET_VOLUME_ID_DATA5, + GET_VOLUME_ID_DATA6, + GET_VOLUME_ID_DATA7, + GET_VOLUME_ID_DATA8, + GET_VOLUME_ID_DATA9, + GET_VOLUME_ID_DATA10, + GET_VOLUME_ID_DATA11, + GET_VOLUME_ID_DATA12, + GET_VOLUME_ID_DATA13, + GET_VOLUME_ID_DATA14, + GET_VOLUME_ID_DATA15, + GET_VOLUME_ID_DATA16, + GET_VOLUME_ID_DATA17, + GET_VOLUME_ID_DATA18, + GET_VOLUME_ID_DATA19, + GET_VOLUME_ID_DATA20, + GET_VOLUME_ID_DATA21, + GET_VOLUME_ID_DATA22, + GET_VOLUME_ID_DATA23, + SD_INIT_CMPLT); + +signal ir_state, ir_next_state : MAIN_ROUTINE := IDLE; + +------------------------ BLOCK RD ----------------------------------- + +signal perform_block_rd, block_rd_we : std_logic := '0'; +signal block_wr_addr, block_rd_addr : unsigned(8 downto 0); + +type BLOCK_RD_ROUTINE is ( IDLE, + READ_BYTE0, + READ_BYTE1, + READ_BYTE2, + READ_BYTE3 ); +signal br_state, br_next_state : BLOCK_RD_ROUTINE; + +begin + + SD_INIT_OUT <= sd_init; + SD_BLOCK_RD_OUT <= sd_rd_block; + SD_BLOCK_ADDR_OUT <= sd_block_addr; + sd_data <= SD_DATA_IN; + sd_busy <= SD_BUSY_IN; + SD_BYTE_RD_OUT <= rd_byte; + rd_byte_ack <= SD_BYTE_RD_ACK_IN; + sd_error <= SD_ERROR_IN; + SD_INIT_CMPLT_OUT <= init_cmplt; + + SECTORS_PER_FAT_OUT <= '0'§ors_per_fat; + FAT_BEGIN_ADDR_OUT <= slv(fat_begin_lba); + CLUSTER_BEGIN_ADDR_OUT <= slv(cluster_begin_lba); + SECTORS_PER_CLUSTER_OUT <= slv(sectors_per_cluster); + ROOT_DIR_FIRST_CLUSTER_OUT <= slv(root_dir_cluster); + + STARTUP_DELAY: process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if ir_state = IDLE then + if sd_present = '1' and startup_delay_counter /= "00"&X"000000" then + startup_delay_counter <= startup_delay_counter - 1; + else + startup_delay_counter <= C_500_ms_startup_delay; + end if; + else + startup_delay_counter <= C_500_ms_startup_delay; + end if; + if startup_delay_counter = X"000000" then + startup_delay_cmplt <= '1'; + else + startup_delay_cmplt <= '0'; + end if; + end if; + end process; + + SD_CARD_PRESENT: process(CLK_IN) + begin + if rising_edge(CLK_IN) then + sd_present <= not SD_PRESENT_BAR_IN; + end if; + end process; + + SD_INIT_FLAGS: process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if ir_state = SD_INIT0 then + sd_init <= '1'; + else + sd_init <= '0'; + end if; + if ir_state = SD_INIT2 then + sd_init_attempts_counter <= sd_init_attempts_counter + 1; + end if; + end if; + end process; + + SD_RD_BLOCK_FLAGS: process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if ir_state = CHECK_FILE_SYS_VERACITY0 then + sd_rd_block <= '1'; + elsif ir_state = GET_LBA_START_ADDR6 then + sd_rd_block <= '1'; + else + sd_rd_block <= '0'; + end if; + if ir_state = CHECK_FILE_SYS_VERACITY0 then + sd_block_addr <= X"00000000"; + elsif ir_state = GET_LBA_START_ADDR6 then + sd_block_addr <= lba_block_addr; + else + sd_block_addr <= X"00000000"; + end if; + if ir_state = CHECK_FILE_SYS_VERACITY2 then + block_rd_addr <= "1"&X"FE"; + elsif ir_state = CHECK_FILE_SYS_VERACITY3 then + block_rd_addr <= "1"&X"FF"; + elsif ir_state = GET_LBA_START_ADDR0 then + block_rd_addr <= "1"&X"C6"; + elsif ir_state = GET_LBA_START_ADDR1 then + block_rd_addr <= "1"&X"C7"; + elsif ir_state = GET_LBA_START_ADDR2 then + block_rd_addr <= "1"&X"C8"; + elsif ir_state = GET_LBA_START_ADDR3 then + block_rd_addr <= "1"&X"C9"; + elsif ir_state = GET_VOLUME_ID_DATA2 then + block_rd_addr <= "0"&X"0D"; + elsif ir_state = GET_VOLUME_ID_DATA3 then + block_rd_addr <= "0"&X"0E"; + elsif ir_state = GET_VOLUME_ID_DATA4 then + block_rd_addr <= "0"&X"0F"; + elsif ir_state = GET_VOLUME_ID_DATA5 then + block_rd_addr <= "0"&X"24"; + elsif ir_state = GET_VOLUME_ID_DATA6 then + block_rd_addr <= "0"&X"25"; + elsif ir_state = GET_VOLUME_ID_DATA7 then + block_rd_addr <= "0"&X"26"; + elsif ir_state = GET_VOLUME_ID_DATA8 then + block_rd_addr <= "0"&X"27"; + elsif ir_state = GET_VOLUME_ID_DATA9 then + block_rd_addr <= "0"&X"2C"; + elsif ir_state = GET_VOLUME_ID_DATA10 then + block_rd_addr <= "0"&X"2D"; + elsif ir_state = GET_VOLUME_ID_DATA11 then + block_rd_addr <= "0"&X"2E"; + elsif ir_state = GET_VOLUME_ID_DATA12 then + block_rd_addr <= "0"&X"2F"; + elsif ir_state = GET_VOLUME_ID_DATA13 then + block_rd_addr <= "1"&X"FE"; + elsif ir_state = GET_VOLUME_ID_DATA14 then + block_rd_addr <= "1"&X"FF"; + elsif ir_state = GET_VOLUME_ID_DATA15 then + block_rd_addr <= "0"&X"0B"; + elsif ir_state = GET_VOLUME_ID_DATA16 then + block_rd_addr <= "0"&X"0C"; + else + block_rd_addr <= (others => '0'); + end if; + if ir_state = CHECK_FILE_SYS_VERACITY4 then + mbr_veracity(7 downto 0) <= block_rd_data; + elsif ir_state = CHECK_FILE_SYS_VERACITY5 then + mbr_veracity(15 downto 8) <= block_rd_data; + end if; + end if; + end process; + + LBA_SETUP: process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if ir_state = GET_LBA_START_ADDR2 then + lba_block_addr(7 downto 0) <= block_rd_data; + elsif ir_state = GET_LBA_START_ADDR3 then + lba_block_addr(15 downto 8) <= block_rd_data; + elsif ir_state = GET_LBA_START_ADDR4 then + lba_block_addr(23 downto 16) <= block_rd_data; + elsif ir_state = GET_LBA_START_ADDR5 then + lba_block_addr(31 downto 24) <= block_rd_data; + end if; + end if; + end process; + + VOLUME_DATA: process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if ir_state = GET_VOLUME_ID_DATA4 then + sectors_per_cluster <= unsigned(block_rd_data); + elsif ir_state = GET_VOLUME_ID_DATA5 then + num_reserved_sectors(7 downto 0) <= block_rd_data; + elsif ir_state = GET_VOLUME_ID_DATA6 then + num_reserved_sectors(15 downto 8) <= block_rd_data; + elsif ir_state = GET_VOLUME_ID_DATA7 then + sectors_per_fat(7 downto 0) <= block_rd_data; + elsif ir_state = GET_VOLUME_ID_DATA8 then + sectors_per_fat(15 downto 8) <= block_rd_data; + elsif ir_state = GET_VOLUME_ID_DATA9 then + sectors_per_fat(23 downto 16) <= block_rd_data; + elsif ir_state = GET_VOLUME_ID_DATA10 then + sectors_per_fat(30 downto 24) <= block_rd_data(6 downto 0); + elsif ir_state = GET_VOLUME_ID_DATA11 then + root_dir_cluster(7 downto 0) <= unsigned(block_rd_data); + elsif ir_state = GET_VOLUME_ID_DATA12 then + root_dir_cluster(15 downto 8) <= unsigned(block_rd_data); + elsif ir_state = GET_VOLUME_ID_DATA13 then + root_dir_cluster(23 downto 16) <= unsigned(block_rd_data); + elsif ir_state = GET_VOLUME_ID_DATA14 then + root_dir_cluster(31 downto 24) <= unsigned(block_rd_data); + elsif ir_state = GET_VOLUME_ID_DATA15 then + vol_signature(7 downto 0) <= block_rd_data; + elsif ir_state = GET_VOLUME_ID_DATA16 then + vol_signature(15 downto 8) <= block_rd_data; + elsif ir_state = GET_VOLUME_ID_DATA17 then + bytes_per_sector(7 downto 0) <= block_rd_data; + elsif ir_state = GET_VOLUME_ID_DATA18 then + bytes_per_sector(15 downto 8) <= block_rd_data; + end if; + if ir_state = GET_VOLUME_ID_DATA20 then + fat_begin_lba <= unsigned(lba_block_addr) + RESIZE(unsigned(num_reserved_sectors), 32); + end if; + if ir_state = GET_VOLUME_ID_DATA21 then + cluster_begin_lba <= fat_begin_lba; + elsif ir_state = GET_VOLUME_ID_DATA22 then + cluster_begin_lba <= cluster_begin_lba + unsigned(sectors_per_fat&"0"); + end if; + end if; + end process; + + CMPLT_FLAG: process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if ir_state = SD_INIT_CMPLT then + init_cmplt <= '1'; + else + init_cmplt <= '0'; + end if; + end if; + end process; + + INIT_ROUTINE_SYNC: process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if RESET_IN = '0' then + ir_state <= ir_next_state; + else + ir_state <= IDLE; + end if; + end if; + end process; + + INIT_ROUTINE_DECODE: process ( ir_state, + sd_error, + sd_present, + startup_delay_cmplt, + sd_busy, + sd_init_attempts_counter, + mbr_veracity, + bytes_per_sector, + vol_signature ) + begin + ir_next_state <= ir_state; -- default is to stay in current state + case (ir_state) is + when REPORT_ERROR => + ir_next_state <= WAIT_FOR_SD_UNPLUGGED; + when WAIT_FOR_SD_UNPLUGGED => + if sd_present = '0' then + ir_next_state <= IDLE; + end if; + when IDLE => + if startup_delay_cmplt = '1' then + ir_next_state <= SD_INIT0; + end if; + when SD_INIT0 => + if sd_busy = '1' then + ir_next_state <= SD_INIT1; + end if; + when SD_INIT1 => + if sd_busy = '0' then + if sd_error = X"0000" then + ir_next_state <= CHECK_FILE_SYS_VERACITY0; + else + ir_next_state <= SD_INIT2; + end if; + end if; + when SD_INIT2 => + if sd_init_attempts_counter = C_sd_init_attempts then + ir_next_state <= SD_INIT3; + else + ir_next_state <= SD_INIT0; + end if; + when SD_INIT3 => + ir_next_state <= REPORT_ERROR; + when CHECK_FILE_SYS_VERACITY0 => + if sd_busy = '1' then + ir_next_state <= CHECK_FILE_SYS_VERACITY1; + end if; + when CHECK_FILE_SYS_VERACITY1 => + ir_next_state <= CHECK_FILE_SYS_VERACITY2; + when CHECK_FILE_SYS_VERACITY2 => + if sd_busy = '0' then + ir_next_state <= CHECK_FILE_SYS_VERACITY3; + end if; + when CHECK_FILE_SYS_VERACITY3 => + ir_next_state <= CHECK_FILE_SYS_VERACITY4; + when CHECK_FILE_SYS_VERACITY4 => + ir_next_state <= CHECK_FILE_SYS_VERACITY5; + when CHECK_FILE_SYS_VERACITY5 => + ir_next_state <= CHECK_FILE_SYS_VERACITY6; + when CHECK_FILE_SYS_VERACITY6 => + if mbr_veracity = C_mbr_veracity then + ir_next_state <= GET_LBA_START_ADDR0; + else + ir_next_state <= REPORT_ERROR; + end if; + when GET_LBA_START_ADDR0 => + ir_next_state <= GET_LBA_START_ADDR1; + when GET_LBA_START_ADDR1 => + ir_next_state <= GET_LBA_START_ADDR2; + when GET_LBA_START_ADDR2 => + ir_next_state <= GET_LBA_START_ADDR3; + when GET_LBA_START_ADDR3 => + ir_next_state <= GET_LBA_START_ADDR4; + when GET_LBA_START_ADDR4 => + ir_next_state <= GET_LBA_START_ADDR5; + when GET_LBA_START_ADDR5 => + ir_next_state <= GET_LBA_START_ADDR6; + when GET_LBA_START_ADDR6 => + if sd_busy = '1' then + ir_next_state <= GET_VOLUME_ID_DATA0; + end if; + when GET_VOLUME_ID_DATA0 => + ir_next_state <= GET_VOLUME_ID_DATA1; + when GET_VOLUME_ID_DATA1 => + if sd_busy = '0' then + ir_next_state <= GET_VOLUME_ID_DATA2; + end if; + when GET_VOLUME_ID_DATA2 => + ir_next_state <= GET_VOLUME_ID_DATA3; + when GET_VOLUME_ID_DATA3 => + ir_next_state <= GET_VOLUME_ID_DATA4; + when GET_VOLUME_ID_DATA4 => + ir_next_state <= GET_VOLUME_ID_DATA5; + when GET_VOLUME_ID_DATA5 => + ir_next_state <= GET_VOLUME_ID_DATA6; + when GET_VOLUME_ID_DATA6 => + ir_next_state <= GET_VOLUME_ID_DATA7; + when GET_VOLUME_ID_DATA7 => + ir_next_state <= GET_VOLUME_ID_DATA8; + when GET_VOLUME_ID_DATA8 => + ir_next_state <= GET_VOLUME_ID_DATA9; + when GET_VOLUME_ID_DATA9 => + ir_next_state <= GET_VOLUME_ID_DATA10; + when GET_VOLUME_ID_DATA10 => + ir_next_state <= GET_VOLUME_ID_DATA11; + when GET_VOLUME_ID_DATA11 => + ir_next_state <= GET_VOLUME_ID_DATA12; + when GET_VOLUME_ID_DATA12 => + ir_next_state <= GET_VOLUME_ID_DATA13; + when GET_VOLUME_ID_DATA13 => + ir_next_state <= GET_VOLUME_ID_DATA14; + when GET_VOLUME_ID_DATA14 => + ir_next_state <= GET_VOLUME_ID_DATA15; + when GET_VOLUME_ID_DATA15 => + ir_next_state <= GET_VOLUME_ID_DATA16; + when GET_VOLUME_ID_DATA16 => + ir_next_state <= GET_VOLUME_ID_DATA17; + when GET_VOLUME_ID_DATA17 => + ir_next_state <= GET_VOLUME_ID_DATA18; + when GET_VOLUME_ID_DATA18 => + ir_next_state <= GET_VOLUME_ID_DATA19; + when GET_VOLUME_ID_DATA19 => + if bytes_per_sector /= C_bytes_per_sector or vol_signature /= C_volume_signature then + ir_next_state <= REPORT_ERROR; + else + ir_next_state <= GET_VOLUME_ID_DATA20; + end if; + when GET_VOLUME_ID_DATA20 => + ir_next_state <= GET_VOLUME_ID_DATA21; + when GET_VOLUME_ID_DATA21 => + ir_next_state <= GET_VOLUME_ID_DATA22; + when GET_VOLUME_ID_DATA22 => + ir_next_state <= GET_VOLUME_ID_DATA23; + when GET_VOLUME_ID_DATA23 => + ir_next_state <= SD_INIT_CMPLT; + when SD_INIT_CMPLT => + ir_next_state <= SD_INIT_CMPLT; + end case; + end process; + + BLOCK_READ_SYNC: process(CLK_IN) + begin + if rising_edge(CLK_IN) then + br_state <= br_next_state; + end if; + end process; + + BLOCK_READ_TRIG: process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if ir_state = CHECK_FILE_SYS_VERACITY0 and sd_busy = '1' then + perform_block_rd <= '1'; + elsif ir_state = GET_LBA_START_ADDR6 and sd_busy = '1' then + perform_block_rd <= '1'; + else + perform_block_rd <= '0'; + end if; + end if; + end process; + + BLOCK_READ_FLAGS: process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if br_state = READ_BYTE0 and rd_byte_ack = '1' then + block_rd_we <= '1'; + else + block_rd_we <= '0'; + end if; + if br_state = READ_BYTE1 then + rd_byte <= '1'; + elsif br_state = READ_BYTE2 and rd_byte_ack = '0' then + rd_byte <= '0'; + end if; + if br_state = IDLE then + block_wr_addr <= (others => '0'); + elsif br_state = READ_BYTE1 then + block_wr_addr <= block_wr_addr + 1; + end if; + end if; + end process; + + BLOCK_READ_DECODE: process (br_state, perform_block_rd, rd_byte_ack, block_wr_addr) + begin + br_next_state <= br_state; -- default is to stay in current state + case (br_state) is + when IDLE => + if perform_block_rd = '1' then + br_next_state <= READ_BYTE0; + end if; + when READ_BYTE0 => + if rd_byte_ack = '1' then + br_next_state <= READ_BYTE1; + end if; + when READ_BYTE1 => + br_next_state <= READ_BYTE2; + when READ_BYTE2 => + if rd_byte_ack = '0' then + br_next_state <= READ_BYTE3; + end if; + when READ_BYTE3 => + if block_wr_addr = "000000000" then + br_next_state <= IDLE; + else + br_next_state <= READ_BYTE0; + end if; + end case; + end process; + + TDP_RAM_Inst : TDP_RAM + Generic Map ( G_DATA_A_SIZE => sd_data'length, + G_ADDR_A_SIZE => block_wr_addr'length, + G_RELATION => 0, + G_INIT_FILE => "") --log2(SIZE_A/SIZE_B) + Port Map ( CLK_A_IN => CLK_IN, + WE_A_IN => block_rd_we, + ADDR_A_IN => slv(block_wr_addr), + DATA_A_IN => sd_data, + DATA_A_OUT => open, + CLK_B_IN => CLK_IN, + WE_B_IN => '0', + ADDR_B_IN => slv(block_rd_addr), + DATA_B_IN => X"00", + DATA_B_OUT => block_rd_data); + +end Behavioral; + Index: fat_32_file_parser/trunk/coe_dir/tmp.coe =================================================================== --- fat_32_file_parser/trunk/coe_dir/tmp.coe (nonexistent) +++ fat_32_file_parser/trunk/coe_dir/tmp.coe (revision 2) @@ -0,0 +1,258 @@ + memory_initialization_radix=16; + memory_initialization_vector= +00, ; 00 -- nothing? +F9, ; 01 -- F9 +00, ; 02 -- nothing? +F5, ; 03 -- F5 +F3, ; 04 -- F3 +F1, ; 05 -- F1 +F2, ; 06 -- F2 +FC, ; 07 -- F12 +00, ; 08 -- nothing? +FA, ; 09 -- F10 +F8, ; 0A -- F8 +F6, ; 06 -- F6 +F4, ; 0C -- F4 +09, ; 0D --tab (HT control code) +60, ; 0E --` +00, ; 0F -- nothing? +00, ; 10 -- nothing? +00, ; 11 -- nothing? +00, ; 12 -- nothing? +00, ; 13 -- nothing? +00, ; 14 -- nothing? +71, ; 15 --q +31, ; 16 --1 +00, ; 17 -- nothing? +00, ; 18 -- nothing? +00, ; 19 -- nothing? +7A, ; 1A --z +73, ; 1B --s +61, ; 1C --a +77, ; 1D --w +32, ; 1E --2 +00, ; 1F -- nothing? +00, ; 20 -- nothing? +63, ; 21 --c +78, ; 22 --x +64, ; 23 --d +65, ; 24 --e +34, ; 25 --4 +33, ; 26 --3 +00, ; 27 -- nothing? +00, ; 28 -- nothing? +20, ; 29 --space +76, ; 2A --v +66, ; 2B --f +74, ; 2C --t +72, ; 2D --r +35, ; 2E --5 +00, ; 2F -- nothing? +00, ; 30 -- nothing? +6E, ; 31 --n +62, ; 32 --b +68, ; 33 --h +67, ; 34 --g +79, ; 35 --y +36, ; 36 --6 +00, ; 37 -- nothing? +00, ; 38 -- nothing? +00, ; 39 -- nothing? +6D, ; 3A --m +6A, ; 3B --j +75, ; 3C --u +37, ; 3D --7 +38, ; 3E --8 +00, ; 3F -- nothing? +00, ; 40 -- nothing? +2C, ; 41 --, +6B, ; 42 --k +69, ; 43 --i +6F, ; 44 --o +30, ; 45 --0 +39, ; 46 --9 +00, ; 47 -- nothing? +00, ; 48 -- nothing? +2E, ; 49 --. +2F, ; 4A --/ +6C, ; 4B --l +3B, ; 4C --; +70, ; 4D --p +2D, ; 4E --- +00, ; 4F -- nothing? +00, ; 50 -- nothing? +00, ; 51 -- nothing? +27, ; 52 --' +00, ; 53 -- nothing? +5B, ; 54 --[ +3D, ; 55 --= +00, ; 56 -- nothing? +00, ; 57 -- nothing? +00, ; 58 -- nothing? +00, ; 59 -- nothing? +0D, ; 5A --enter (CR control code) +5D, ; 5B --] +00, ; 5C -- nothing? +5C, ; 5D --\ +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +08, ; 66 --backspace (BS control code) +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +1B, ; 76 --escape (ESC control code) +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +7E, ; 0E --` +00, ; 0F -- nothing? +00, ; 10 -- nothing? +00, ; 11 -- nothing? +00, ; 12 -- nothing? +00, ; 13 -- nothing? +00, ; 14 -- nothing? +51, ; 15 --Q +21, ; 16 --1 +00, ; 17 -- nothing? +00, ; 18 -- nothing? +00, ; 19 -- nothing? +5A, ; 1A --Z +53, ; 1B --S +41, ; 1C --A +57, ; 1D --W +40, ; 1E --2 +00, ; 1F -- nothing? +00, ; 20 -- nothing? +43, ; 21 --C +58, ; 22 --X +44, ; 23 --D +45, ; 24 --E +24, ; 25 --4 +23, ; 26 --3 +00, ; 27 -- nothing? +00, ; 28 -- nothing? +20, ; 29 --space +56, ; 2A --V +46, ; 2B --F +54, ; 2C --T +52, ; 2D --R +25, ; 2E --5 +00, ; 2F -- nothing? +00, ; 30 -- nothing? +4E, ; 31 --N +42, ; 32 --B +48, ; 33 --H +47, ; 34 --G +59, ; 35 --Y +5E, ; 36 --6 +00, ; 37 -- nothing? +00, ; 38 -- nothing? +00, ; 39 -- nothing? +4D, ; 3A --M +4A, ; 3B --J +55, ; 3C --U +26, ; 3D --7 +2A, ; 3E --8 +00, ; 3F -- nothing? +00, ; 40 -- nothing? +3C, ; 41 --, +4B, ; 42 --K +49, ; 43 --I +4F, ; 44 --O +29, ; 45 --0 +28, ; 46 --9 +00, ; 47 -- nothing? +00, ; 48 -- nothing? +3E, ; 49 --. +3F, ; 4A --/ +4C, ; 4B --L +3A, ; 4C --; +50, ; 4D --P +5F, ; 4E --- +00, ; 4F -- nothing? +00, ; 50 -- nothing? +00, ; 51 -- nothing? +22, ; 52 --' +00, ; 53 -- nothing? +7B, ; 54 --[ +2B, ; 55 --= +00, ; 56 -- nothing? +00, ; 57 -- nothing? +00, ; 58 -- nothing? +00, ; 59 -- nothing? +0D, ; 5A --enter (CR control code) +7D, ; 5B --] +00, ; 5C -- nothing? +7C, ; 5D --\ +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? +00, ; 4F -- nothing? \ No newline at end of file Index: fat_32_file_parser/trunk/coe_dir/lat0-12.coe =================================================================== --- fat_32_file_parser/trunk/coe_dir/lat0-12.coe (nonexistent) +++ fat_32_file_parser/trunk/coe_dir/lat0-12.coe (revision 2) @@ -0,0 +1,3078 @@ +; DO NOT EDIT THIS FILE BY HAND +; This file has been generated automaticaly by psf2coe utility. +; Original file: lat0-12.psfu + + memory_initialization_radix=16; + memory_initialization_vector= +7E, +C3, +99, +99, +F3, +E7, +E7, +FF, +E7, +E7, +7E, +00, +00, +00, +00, +76, +DC, +00, +76, +DC, +00, +00, +00, +00, +6E, +D8, +D8, +D8, +D8, +DE, +D8, +D8, +D8, +6E, +00, +00, +00, +00, +00, +6E, +DB, +DB, +DF, +D8, +DB, +6E, +00, +00, +00, +00, +10, +38, +7C, +FE, +7C, +38, +10, +00, +00, +00, +88, +88, +F8, +88, +88, +00, +3E, +08, +08, +08, +08, +00, +F8, +80, +E0, +80, +80, +00, +3E, +20, +38, +20, +20, +00, +78, +80, +80, +80, +78, +00, +3C, +22, +3E, +24, +22, +00, +80, +80, +80, +80, +F8, +00, +3E, +20, +38, +20, +20, +00, +22, +88, +22, +88, +22, +88, +22, +88, +22, +88, +22, +88, +55, +AA, +55, +AA, +55, +AA, +55, +AA, +55, +AA, +55, +AA, +EE, +BB, +EE, +BB, +EE, +BB, +EE, +BB, +EE, +BB, +EE, +BB, +FF, +FF, +FF, +FF, +FF, +FF, +FF, +FF, +FF, +FF, +FF, +FF, +00, +00, +00, +00, +00, +00, +FF, +FF, +FF, +FF, +FF, +FF, +FF, +FF, +FF, +FF, +FF, +FF, +00, +00, +00, +00, +00, +00, +F0, +F0, +F0, +F0, +F0, +F0, +F0, +F0, +F0, +F0, +F0, +F0, +0F, +0F, +0F, +0F, +0F, +0F, +0F, +0F, +0F, +0F, +0F, +0F, +88, +C8, +A8, +98, +88, +00, +20, +20, +20, +20, +3E, +00, +88, +88, +50, +50, +20, +00, +3E, +08, +08, +08, +08, +00, +00, +00, +06, +0C, +18, +30, +7E, +00, +7E, +00, +00, +00, +00, +00, +60, +30, +18, +0C, +7E, +00, +7E, +00, +00, +00, +00, +00, +06, +0C, +FE, +38, +FE, +60, +C0, +00, +00, +00, +00, +02, +0E, +3E, +7E, +FE, +7E, +3E, +0E, +02, +00, +00, +00, +80, +E0, +F0, +FC, +FE, +FC, +F0, +E0, +80, +00, +00, +00, +18, +3C, +7E, +18, +18, +18, +18, +18, +18, +00, +00, +00, +18, +18, +18, +18, +18, +18, +7E, +3C, +18, +00, +00, +00, +00, +00, +18, +0C, +FE, +0C, +18, +00, +00, +00, +00, +00, +00, +00, +30, +60, +FE, +60, +30, +00, +00, +00, +00, +00, +18, +3C, +7E, +18, +18, +18, +7E, +3C, +18, +00, +00, +00, +00, +00, +28, +6C, +FE, +6C, +28, +00, +00, +00, +00, +00, +06, +06, +36, +66, +FE, +60, +30, +00, +00, +00, +00, +00, +00, +00, +C0, +7C, +6E, +6C, +6C, +6C, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +18, +3C, +3C, +3C, +18, +18, +00, +18, +18, +00, +00, +00, +36, +36, +14, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +6C, +FE, +6C, +6C, +6C, +FE, +6C, +00, +00, +00, +10, +7C, +D6, +70, +38, +1C, +D6, +7C, +10, +00, +00, +00, +00, +00, +62, +66, +0C, +18, +30, +66, +C6, +00, +00, +00, +38, +6C, +38, +38, +72, +FE, +CC, +CC, +76, +00, +00, +1C, +1C, +0C, +18, +00, +00, +00, +00, +00, +00, +00, +00, +00, +0C, +18, +30, +30, +30, +30, +30, +18, +0C, +00, +00, +00, +30, +18, +0C, +0C, +0C, +0C, +0C, +18, +30, +00, +00, +00, +00, +00, +6C, +38, +FE, +38, +6C, +00, +00, +00, +00, +00, +00, +00, +18, +18, +7E, +18, +18, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +0C, +0C, +0C, +18, +00, +00, +00, +00, +00, +00, +FE, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +18, +18, +00, +00, +00, +00, +00, +06, +0C, +18, +30, +60, +C0, +00, +00, +00, +00, +7C, +C6, +C6, +C6, +D6, +C6, +C6, +C6, +7C, +00, +00, +00, +18, +78, +18, +18, +18, +18, +18, +18, +7E, +00, +00, +00, +7C, +C6, +C6, +0C, +18, +30, +60, +C6, +FE, +00, +00, +00, +7C, +C6, +06, +06, +3C, +06, +06, +C6, +7C, +00, +00, +00, +0C, +1C, +3C, +6C, +CC, +FE, +0C, +0C, +0C, +00, +00, +00, +FE, +C0, +C0, +C0, +FC, +06, +06, +C6, +7C, +00, +00, +00, +7C, +C6, +C0, +C0, +FC, +C6, +C6, +C6, +7C, +00, +00, +00, +FE, +C6, +0C, +18, +30, +30, +30, +30, +30, +00, +00, +00, +7C, +C6, +C6, +C6, +7C, +C6, +C6, +C6, +7C, +00, +00, +00, +7C, +C6, +C6, +C6, +7E, +06, +06, +C6, +7C, +00, +00, +00, +00, +00, +0C, +0C, +00, +00, +0C, +0C, +00, +00, +00, +00, +00, +00, +0C, +0C, +00, +00, +0C, +0C, +0C, +18, +00, +00, +0C, +18, +30, +60, +C0, +60, +30, +18, +0C, +00, +00, +00, +00, +00, +00, +FE, +00, +FE, +00, +00, +00, +00, +00, +00, +60, +30, +18, +0C, +06, +0C, +18, +30, +60, +00, +00, +00, +7C, +C6, +C6, +0C, +18, +18, +00, +18, +18, +00, +00, +00, +7C, +C6, +C6, +DE, +DE, +DE, +DC, +C0, +7E, +00, +00, +00, +38, +6C, +C6, +C6, +C6, +FE, +C6, +C6, +C6, +00, +00, +00, +FC, +66, +66, +66, +7C, +66, +66, +66, +FC, +00, +00, +00, +3C, +66, +C0, +C0, +C0, +C0, +C0, +66, +3C, +00, +00, +00, +F8, +6C, +66, +66, +66, +66, +66, +6C, +F8, +00, +00, +00, +FE, +66, +60, +60, +7C, +60, +60, +66, +FE, +00, +00, +00, +FE, +66, +60, +60, +7C, +60, +60, +60, +F0, +00, +00, +00, +7C, +C6, +C6, +C0, +C0, +CE, +C6, +C6, +7C, +00, +00, +00, +C6, +C6, +C6, +C6, +FE, +C6, +C6, +C6, +C6, +00, +00, +00, +3C, +18, +18, +18, +18, +18, +18, +18, +3C, +00, +00, +00, +3C, +18, +18, +18, +18, +18, +D8, +D8, +70, +00, +00, +00, +C6, +CC, +D8, +F0, +F0, +D8, +CC, +C6, +C6, +00, +00, +00, +F0, +60, +60, +60, +60, +60, +62, +66, +FE, +00, +00, +00, +C6, +C6, +EE, +FE, +D6, +D6, +D6, +C6, +C6, +00, +00, +00, +C6, +C6, +E6, +E6, +F6, +DE, +CE, +CE, +C6, +00, +00, +00, +7C, +C6, +C6, +C6, +C6, +C6, +C6, +C6, +7C, +00, +00, +00, +FC, +66, +66, +66, +7C, +60, +60, +60, +F0, +00, +00, +00, +7C, +C6, +C6, +C6, +C6, +C6, +C6, +D6, +7C, +06, +00, +00, +FC, +66, +66, +66, +7C, +78, +6C, +66, +E6, +00, +00, +00, +7C, +C6, +C0, +60, +38, +0C, +06, +C6, +7C, +00, +00, +00, +7E, +5A, +18, +18, +18, +18, +18, +18, +3C, +00, +00, +00, +C6, +C6, +C6, +C6, +C6, +C6, +C6, +C6, +7C, +00, +00, +00, +C6, +C6, +C6, +C6, +C6, +C6, +6C, +38, +10, +00, +00, +00, +C6, +C6, +D6, +D6, +D6, +FE, +EE, +C6, +C6, +00, +00, +00, +C6, +C6, +6C, +38, +38, +38, +6C, +C6, +C6, +00, +00, +00, +66, +66, +66, +66, +3C, +18, +18, +18, +3C, +00, +00, +00, +FE, +C6, +8C, +18, +30, +60, +C2, +C6, +FE, +00, +00, +00, +7C, +60, +60, +60, +60, +60, +60, +60, +7C, +00, +00, +00, +00, +00, +C0, +60, +30, +18, +0C, +06, +00, +00, +00, +00, +7C, +0C, +0C, +0C, +0C, +0C, +0C, +0C, +7C, +00, +00, +00, +18, +3C, +66, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +FF, +1C, +1C, +18, +0C, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +78, +0C, +7C, +CC, +DC, +76, +00, +00, +00, +E0, +60, +60, +7C, +66, +66, +66, +66, +FC, +00, +00, +00, +00, +00, +00, +7C, +C6, +C0, +C0, +C6, +7C, +00, +00, +00, +1C, +0C, +0C, +7C, +CC, +CC, +CC, +CC, +7E, +00, +00, +00, +00, +00, +00, +7C, +C6, +FE, +C0, +C6, +7C, +00, +00, +00, +1C, +36, +30, +30, +FC, +30, +30, +30, +78, +00, +00, +00, +00, +00, +00, +76, +CE, +C6, +C6, +7E, +06, +C6, +7C, +00, +E0, +60, +60, +6C, +76, +66, +66, +66, +E6, +00, +00, +00, +18, +18, +00, +38, +18, +18, +18, +18, +3C, +00, +00, +00, +00, +0C, +0C, +00, +1C, +0C, +0C, +0C, +CC, +CC, +78, +00, +E0, +60, +60, +66, +6C, +78, +6C, +66, +E6, +00, +00, +00, +70, +30, +30, +30, +30, +30, +30, +34, +18, +00, +00, +00, +00, +00, +00, +6C, +FE, +D6, +D6, +C6, +C6, +00, +00, +00, +00, +00, +00, +DC, +66, +66, +66, +66, +66, +00, +00, +00, +00, +00, +00, +7C, +C6, +C6, +C6, +C6, +7C, +00, +00, +00, +00, +00, +00, +DC, +66, +66, +66, +7C, +60, +60, +F0, +00, +00, +00, +00, +76, +CC, +CC, +CC, +7C, +0C, +0C, +1E, +00, +00, +00, +00, +DC, +66, +60, +60, +60, +F0, +00, +00, +00, +00, +00, +00, +7C, +C6, +70, +1C, +C6, +7C, +00, +00, +00, +30, +30, +30, +FC, +30, +30, +30, +36, +1C, +00, +00, +00, +00, +00, +00, +CC, +CC, +CC, +CC, +CC, +76, +00, +00, +00, +00, +00, +00, +C6, +C6, +C6, +6C, +38, +10, +00, +00, +00, +00, +00, +00, +C6, +C6, +D6, +D6, +FE, +6C, +00, +00, +00, +00, +00, +00, +C6, +6C, +38, +38, +6C, +C6, +00, +00, +00, +00, +00, +00, +C6, +C6, +C6, +CE, +76, +06, +C6, +7C, +00, +00, +00, +00, +FE, +8C, +18, +30, +62, +FE, +00, +00, +00, +0E, +18, +18, +18, +70, +18, +18, +18, +0E, +00, +00, +00, +18, +18, +18, +18, +18, +18, +18, +18, +18, +00, +00, +00, +70, +18, +18, +18, +0E, +18, +18, +18, +70, +00, +00, +00, +76, +DC, +00, +00, +00, +00, +00, +00, +00, +00, +00, +66, +66, +00, +66, +66, +66, +3C, +18, +18, +3C, +00, +00, +30, +18, +00, +38, +6C, +C6, +C6, +FE, +C6, +C6, +00, +00, +18, +30, +00, +38, +6C, +C6, +C6, +FE, +C6, +C6, +00, +00, +38, +6C, +38, +00, +7C, +C6, +C6, +FE, +C6, +C6, +00, +00, +76, +DC, +00, +38, +6C, +C6, +C6, +FE, +C6, +C6, +00, +00, +6C, +6C, +00, +38, +6C, +C6, +C6, +FE, +C6, +C6, +00, +00, +38, +6C, +38, +00, +7C, +C6, +C6, +FE, +C6, +C6, +00, +00, +7E, +D8, +D8, +D8, +D8, +FE, +D8, +D8, +D8, +DE, +00, +00, +00, +3C, +66, +C0, +C0, +C0, +C6, +66, +3C, +18, +CC, +38, +18, +0C, +00, +FE, +66, +60, +7C, +60, +66, +FE, +00, +00, +18, +30, +00, +FE, +66, +60, +7C, +60, +66, +FE, +00, +00, +38, +6C, +00, +FE, +66, +60, +7C, +60, +66, +FE, +00, +00, +6C, +6C, +00, +FE, +66, +60, +7C, +60, +66, +FE, +00, +00, +18, +0C, +00, +3C, +18, +18, +18, +18, +18, +3C, +00, +00, +18, +30, +00, +3C, +18, +18, +18, +18, +18, +3C, +00, +00, +3C, +66, +00, +3C, +18, +18, +18, +18, +18, +3C, +00, +00, +66, +66, +00, +3C, +18, +18, +18, +18, +18, +3C, +00, +00, +00, +F8, +6C, +66, +66, +F6, +66, +66, +6C, +F8, +00, +00, +76, +DC, +00, +C6, +E6, +F6, +DE, +CE, +C6, +C6, +00, +00, +30, +18, +00, +7C, +C6, +C6, +C6, +C6, +C6, +7C, +00, +00, +18, +30, +00, +7C, +C6, +C6, +C6, +C6, +C6, +7C, +00, +00, +38, +6C, +00, +7C, +C6, +C6, +C6, +C6, +C6, +7C, +00, +00, +76, +DC, +00, +7C, +C6, +C6, +C6, +C6, +C6, +7C, +00, +00, +6C, +6C, +00, +7C, +C6, +C6, +C6, +C6, +C6, +7C, +00, +00, +00, +00, +00, +00, +6C, +38, +38, +6C, +00, +00, +00, +00, +00, +7E, +C6, +CE, +DE, +D6, +F6, +E6, +C6, +FC, +00, +00, +30, +18, +00, +C6, +C6, +C6, +C6, +C6, +C6, +7C, +00, +00, +18, +30, +00, +C6, +C6, +C6, +C6, +C6, +C6, +7C, +00, +00, +38, +6C, +00, +C6, +C6, +C6, +C6, +C6, +C6, +7C, +00, +00, +6C, +6C, +00, +C6, +C6, +C6, +C6, +C6, +C6, +7C, +00, +00, +0C, +18, +00, +66, +66, +66, +3C, +18, +18, +3C, +00, +00, +00, +F0, +60, +7C, +66, +66, +66, +7C, +60, +F0, +00, +00, +00, +7C, +C6, +C6, +C6, +CC, +C6, +C6, +D6, +DC, +80, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +82, +FE, +00, +00, +00, +00, +18, +18, +00, +18, +18, +3C, +3C, +3C, +18, +00, +00, +10, +7C, +D6, +D0, +D0, +D6, +7C, +10, +00, +00, +00, +38, +6C, +60, +60, +F0, +60, +66, +F6, +6C, +00, +00, +00, +3C, +62, +60, +F8, +60, +F8, +60, +62, +3C, +00, +00, +00, +66, +66, +3C, +18, +7E, +18, +3C, +18, +18, +00, +00, +6C, +38, +00, +7C, +C6, +C0, +7C, +06, +C6, +7C, +00, +00, +7C, +C6, +C6, +60, +7C, +C6, +C6, +7C, +0C, +C6, +C6, +7C, +00, +6C, +38, +00, +7C, +C6, +70, +1C, +C6, +7C, +00, +00, +7E, +81, +99, +A5, +A1, +A1, +A5, +99, +81, +7E, +00, +00, +3C, +6C, +6C, +3E, +00, +7E, +00, +00, +00, +00, +00, +00, +00, +00, +00, +36, +6C, +D8, +6C, +36, +00, +00, +00, +00, +00, +00, +00, +00, +00, +7E, +06, +06, +06, +00, +00, +00, +00, +00, +00, +00, +00, +7E, +00, +00, +00, +00, +00, +00, +7E, +81, +B9, +A5, +A5, +B9, +A5, +A5, +81, +7E, +00, +00, +FF, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +38, +6C, +38, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +18, +18, +7E, +18, +18, +00, +7E, +00, +00, +00, +38, +6C, +18, +30, +7C, +00, +00, +00, +00, +00, +00, +00, +38, +6C, +18, +6C, +38, +00, +00, +00, +00, +00, +00, +6C, +38, +00, +FE, +C6, +0C, +38, +62, +C6, +FE, +00, +00, +00, +00, +00, +00, +CC, +CC, +CC, +CC, +CC, +F6, +C0, +C0, +00, +7F, +DB, +DB, +DB, +7B, +1B, +1B, +1B, +1B, +00, +00, +00, +00, +00, +00, +00, +18, +18, +00, +00, +00, +00, +00, +00, +6C, +38, +00, +FE, +8C, +18, +30, +62, +FE, +00, +00, +00, +30, +70, +30, +30, +78, +00, +00, +00, +00, +00, +00, +38, +6C, +6C, +38, +00, +7C, +00, +00, +00, +00, +00, +00, +00, +00, +00, +D8, +6C, +36, +6C, +D8, +00, +00, +00, +00, +00, +6E, +DB, +DB, +DF, +D8, +D8, +D9, +DF, +6E, +00, +00, +00, +00, +00, +00, +6C, +DA, +DE, +D8, +DA, +6C, +00, +00, +66, +66, +00, +66, +66, +3C, +18, +18, +18, +3C, +00, +00, +00, +00, +00, +30, +30, +00, +30, +30, +60, +C6, +C6, +7C, +00, +00, +FF, +00, +00, +00, +00, +00, +00, +00, +00, +00, +18, +18, +18, +18, +18, +18, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +1F, +00, +00, +00, +00, +00, +00, +18, +18, +18, +18, +18, +1F, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +18, +18, +18, +18, +18, +18, +18, +18, +18, +18, +18, +18, +18, +18, +18, +18, +18, +18, +18, +00, +00, +00, +00, +00, +1F, +18, +18, +18, +18, +18, +18, +18, +18, +18, +18, +18, +1F, +18, +18, +18, +18, +18, +18, +00, +00, +00, +00, +00, +F8, +00, +00, +00, +00, +00, +00, +18, +18, +18, +18, +18, +F8, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +FF, +00, +00, +00, +00, +00, +00, +18, +18, +18, +18, +18, +FF, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +F8, +18, +18, +18, +18, +18, +18, +18, +18, +18, +18, +18, +F8, +18, +18, +18, +18, +18, +18, +00, +00, +00, +00, +00, +FF, +18, +18, +18, +18, +18, +18, +18, +18, +18, +18, +18, +FF, +18, +18, +18, +18, +18, +18, +00, +00, +00, +00, +00, +00, +00, +FF, +00, +00, +00, +00, +6C, +6C, +6C, +6C, +6C, +6C, +7C, +00, +00, +00, +00, +00, +00, +00, +00, +00, +3F, +30, +3F, +00, +00, +00, +00, +00, +6C, +6C, +6C, +6C, +6F, +60, +7F, +00, +00, +00, +00, +00, +00, +00, +00, +00, +7C, +6C, +6C, +6C, +6C, +6C, +6C, +6C, +6C, +6C, +6C, +6C, +6C, +6C, +6C, +6C, +6C, +6C, +6C, +6C, +00, +00, +00, +00, +7F, +60, +6F, +6C, +6C, +6C, +6C, +6C, +6C, +6C, +6C, +6C, +6F, +60, +6F, +6C, +6C, +6C, +6C, +6C, +00, +00, +00, +00, +FC, +0C, +FC, +00, +00, +00, +00, +00, +6C, +6C, +6C, +6C, +EC, +0C, +FC, +00, +00, +00, +00, +00, +00, +00, +00, +00, +FF, +00, +FF, +00, +00, +00, +00, +00, +6C, +6C, +6C, +6C, +EF, +00, +FF, +00, +00, +00, +00, +00, +00, +00, +00, +00, +FC, +0C, +EC, +6C, +6C, +6C, +6C, +6C, +6C, +6C, +6C, +6C, +EC, +0C, +EC, +6C, +6C, +6C, +6C, +6C, +00, +00, +00, +00, +FF, +00, +EF, +6C, +6C, +6C, +6C, +6C, +6C, +6C, +6C, +6C, +EF, +00, +EF, +6C, +6C, +6C, +6C, +6C, +60, +30, +18, +00, +78, +0C, +7C, +CC, +DC, +76, +00, +00, +18, +30, +60, +00, +78, +0C, +7C, +CC, +DC, +76, +00, +00, +30, +78, +CC, +00, +78, +0C, +7C, +CC, +DC, +76, +00, +00, +00, +76, +DC, +00, +78, +0C, +7C, +CC, +DC, +76, +00, +00, +00, +6C, +6C, +00, +78, +0C, +7C, +CC, +DC, +76, +00, +00, +38, +6C, +38, +00, +78, +0C, +7C, +CC, +DC, +76, +00, +00, +00, +00, +00, +7E, +DB, +1B, +7F, +D8, +DB, +7E, +00, +00, +00, +00, +00, +7C, +C6, +C0, +C0, +C6, +7C, +18, +6C, +38, +30, +18, +0C, +00, +7C, +C6, +FE, +C0, +C6, +7C, +00, +00, +0C, +18, +30, +00, +7C, +C6, +FE, +C0, +C6, +7C, +00, +00, +10, +38, +6C, +00, +7C, +C6, +FE, +C0, +C6, +7C, +00, +00, +00, +6C, +6C, +00, +7C, +C6, +FE, +C0, +C6, +7C, +00, +00, +60, +30, +18, +00, +38, +18, +18, +18, +18, +3C, +00, +00, +0C, +18, +30, +00, +38, +18, +18, +18, +18, +3C, +00, +00, +18, +3C, +66, +00, +38, +18, +18, +18, +18, +3C, +00, +00, +00, +6C, +6C, +00, +38, +18, +18, +18, +18, +3C, +00, +00, +78, +30, +78, +0C, +7E, +C6, +C6, +C6, +C6, +7C, +00, +00, +00, +76, +DC, +00, +DC, +66, +66, +66, +66, +66, +00, +00, +60, +30, +18, +00, +7C, +C6, +C6, +C6, +C6, +7C, +00, +00, +0C, +18, +30, +00, +7C, +C6, +C6, +C6, +C6, +7C, +00, +00, +10, +38, +6C, +00, +7C, +C6, +C6, +C6, +C6, +7C, +00, +00, +00, +76, +DC, +00, +7C, +C6, +C6, +C6, +C6, +7C, +00, +00, +00, +6C, +6C, +00, +7C, +C6, +C6, +C6, +C6, +7C, +00, +00, +00, +00, +18, +18, +00, +7E, +00, +18, +18, +00, +00, +00, +00, +00, +00, +00, +7E, +CE, +DE, +F6, +E6, +FC, +00, +00, +C0, +60, +30, +00, +CC, +CC, +CC, +CC, +CC, +76, +00, +00, +0C, +18, +30, +00, +CC, +CC, +CC, +CC, +CC, +76, +00, +00, +30, +78, +CC, +00, +CC, +CC, +CC, +CC, +CC, +76, +00, +00, +00, +CC, +CC, +00, +CC, +CC, +CC, +CC, +CC, +76, +00, +00, +0C, +18, +30, +00, +C6, +C6, +C6, +CE, +76, +06, +C6, +7C, +00, +F0, +60, +60, +78, +6C, +6C, +6C, +78, +60, +60, +F0, +00, +C6, +C6, +00, +C6, +C6, +C6, +CE, +76, +06, +C6, +7C; \ No newline at end of file Index: fat_32_file_parser/trunk/coe_dir/ascii_space.coe =================================================================== --- fat_32_file_parser/trunk/coe_dir/ascii_space.coe (nonexistent) +++ fat_32_file_parser/trunk/coe_dir/ascii_space.coe (revision 2) @@ -0,0 +1,4096 @@ +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 +00100000 \ No newline at end of file Index: fat_32_file_parser/trunk/coe_dir/keycode_ascii_translate.coe =================================================================== --- fat_32_file_parser/trunk/coe_dir/keycode_ascii_translate.coe (nonexistent) +++ fat_32_file_parser/trunk/coe_dir/keycode_ascii_translate.coe (revision 2) @@ -0,0 +1,258 @@ + memory_initialization_radix=16; + memory_initialization_vector= +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +09, +60, +00, +00, +00, +00, +00, +00, +71, +31, +00, +00, +00, +7A, +73, +61, +77, +32, +00, +00, +63, +78, +64, +65, +34, +33, +00, +00, +20, +76, +66, +74, +72, +35, +00, +00, +6E, +62, +68, +67, +79, +36, +00, +00, +00, +6D, +6A, +75, +37, +38, +00, +00, +2C, +6B, +69, +6F, +30, +39, +00, +00, +2E, +2F, +6C, +3B, +70, +2D, +00, +00, +00, +27, +00, +5B, +3D, +00, +00, +00, +00, +0D, +5D, +00, +5C, +00, +00, +00, +00, +00, +00, +00, +00, +88, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +1B, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +7E, +00, +00, +00, +00, +00, +00, +51, +21, +00, +00, +00, +5A, +53, +41, +57, +40, +00, +00, +43, +58, +44, +45, +24, +23, +00, +00, +20, +56, +46, +54, +52, +25, +00, +00, +4E, +42, +48, +47, +59, +5E, +00, +00, +00, +4D, +4A, +55, +26, +2A, +00, +00, +3C, +4B, +49, +4F, +29, +28, +00, +00, +3E, +3F, +4C, +3A, +50, +5F, +00, +00, +00, +22, +00, +7B, +2B, +00, +00, +00, +00, +0D, +7D, +00, +7C, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00, +00; \ No newline at end of file Index: fat_32_file_parser/trunk/TDP_RAM.vhd =================================================================== --- fat_32_file_parser/trunk/TDP_RAM.vhd (nonexistent) +++ fat_32_file_parser/trunk/TDP_RAM.vhd (revision 2) @@ -0,0 +1,111 @@ +---------------------------------------------------------------------------------- +-- Company: SDO +-- Engineer: CW +-- +-- Create Date: 13:26:28 09/05/2013 +-- Design Name: +-- Module Name: TDport_RAM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +library std; +use std.textio.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity TDP_RAM is + Generic (G_DATA_A_SIZE :natural :=32; + G_ADDR_A_SIZE :natural :=9; + G_RELATION :natural :=3; + G_INIT_FILE :string :="");--log2(SIZE_A/SIZE_B) + Port ( CLK_A_IN : in STD_LOGIC; + WE_A_IN : in STD_LOGIC; + ADDR_A_IN : in STD_LOGIC_VECTOR (G_ADDR_A_SIZE-1 downto 0); + DATA_A_IN : in STD_LOGIC_VECTOR (G_DATA_A_SIZE-1 downto 0); + DATA_A_OUT : out STD_LOGIC_VECTOR (G_DATA_A_SIZE-1 downto 0); + CLK_B_IN : in STD_LOGIC; + WE_B_IN : in STD_LOGIC; + ADDR_B_IN : in STD_LOGIC_VECTOR (G_ADDR_A_SIZE+G_RELATION-1 downto 0); + DATA_B_IN : in STD_LOGIC_VECTOR (G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0); + DATA_B_OUT : out STD_LOGIC_VECTOR (G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0)); + + attribute ram_style : string; + attribute ram_style of TDP_RAM : entity is "block"; + +end TDP_RAM; + +architecture Behavioral of TDP_RAM is + +subtype slv is std_logic_vector; + +type RAM_TYPE is array(2**(G_ADDR_A_SIZE+G_RELATION)-1 downto 0) of std_logic_vector(G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0); + +impure function InitRamFromFile (RamFileName : in string) return RAM_TYPE is + FILE RamFile : text; + variable RamFileLine : line; + variable RAM : RAM_TYPE; + variable tmp : bit_vector(G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0); +begin + if RamFileName = "" then + for I in 0 to (2**(G_ADDR_A_SIZE+G_RELATION))-1 loop + RAM(I) := (others => '0'); + end loop; + return RAM; + else + file_open(RamFile, RamFileName, READ_MODE); + for I in 0 to (2**(G_ADDR_A_SIZE+G_RELATION))-1 loop + readline(RamFile, RamFileLine); + read(RamFileLine, tmp); + RAM(I) := To_StdLogicVector(tmp); + end loop; + return RAM; + end if; +end InitRamFromFile; + +shared variable memory : RAM_TYPE := InitRamFromFile(G_INIT_FILE); + +begin + +process(CLK_A_IN) begin + if rising_edge(CLK_A_IN) then + if G_RELATION = 0 then + if WE_A_IN = '1' then + memory(to_integer(unsigned(ADDR_A_IN))) := DATA_A_IN; + end if; + DATA_A_OUT <= memory(to_integer(unsigned(ADDR_A_IN))); + else + for I in 0 to 2**G_RELATION-1 loop + DATA_A_OUT(G_DATA_A_SIZE/(2**G_RELATION)*(I+1)-1 downto G_DATA_A_SIZE/(2**G_RELATION)*(I)) <= memory(to_integer(unsigned(ADDR_A_IN) & to_unsigned(I,G_RELATION))); + if WE_A_IN = '1' then + memory(to_integer(unsigned(ADDR_A_IN) & to_unsigned(I,G_RELATION))) := DATA_A_IN(G_DATA_A_SIZE/(2**G_RELATION)*(I+1)-1 downto G_DATA_A_SIZE/(2**G_RELATION)*(I)); + end if; + end loop; + end if; + end if; +end process; + +process(CLK_B_IN) begin + if rising_edge(CLK_B_IN) then + if WE_B_IN = '1' then + memory(to_integer(unsigned(ADDR_B_IN))) := DATA_B_IN; + end if; + DATA_B_OUT <= memory(to_integer(unsigned(ADDR_B_IN))); + end if; +end process; + +end Behavioral; + Index: fat_32_file_parser/trunk/Common.vhd =================================================================== --- fat_32_file_parser/trunk/Common.vhd (nonexistent) +++ fat_32_file_parser/trunk/Common.vhd (revision 2) @@ -0,0 +1,157 @@ +---------------------------------------------------------------------------------- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License +-- as published by the Free Software Foundation; either version 2 +-- of the License, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA +-- 02111-1307, USA. +-- +-- �1997-2011 - X Engineering Software Systems Corp. (www.xess.com) +---------------------------------------------------------------------------------- + +---------------------------------------------------------------------------------- +-- Commonly-used functions and constants. +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +package CommonPckg is + + constant YES : std_logic := '1'; + constant NO : std_logic := '0'; + constant HI : std_logic := '1'; + constant LO : std_logic := '0'; + constant ONE : std_logic := '1'; + constant ZERO : std_logic := '0'; + constant HIZ : std_logic := 'Z'; + + -- Types of FPGA chips. + constant SPARTAN2_G : natural := 1; + constant SPARTAN2E_G : natural := 2; + constant SPARTAN3_G : natural := 3; + + -- Convert a Boolean to a std_logic. + function BooleanToStdLogic(b : in boolean) return std_logic; + + -- Find the base-2 logarithm of a number. + function Log2(v : in natural) return natural; + + -- Select one of two integers based on a Boolean. + function IntSelect(s : in boolean; a : in integer; b : in integer) return integer; + + -- Select one of two reals based on a Boolean. + function RealSelect(s : in boolean; a : in real; b : in real) return real; + + -- Convert a binary number to a graycode number. + function BinaryToGray(b : in std_logic_vector) return std_logic_vector; + + -- Convert a graycode number to a binary number. + function GrayToBinary(g : in std_logic_vector) return std_logic_vector; + + -- Find the maximum of two integers. + function IntMax(a : in integer; b : in integer) return integer; + +end package; + + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + + +package body CommonPckg is + + -- Convert a Boolean to a std_logic. + function BooleanToStdLogic(b : in boolean) return std_logic is + variable s : std_logic; + begin + if b then + s := '1'; + else + s := '0'; + end if; + return s; + end function BooleanToStdLogic; + + -- Find the base 2 logarithm of a number. + function Log2(v : in natural) return natural is + variable n : natural; + variable logn : natural; + begin + n := 1; + for i in 0 to 128 loop + logn := i; + exit when (n >= v); + n := n * 2; + end loop; + return logn; + end function Log2; + + -- Select one of two integers based on a Boolean. + function IntSelect(s : in boolean; a : in integer; b : in integer) return integer is + begin + if s then + return a; + else + return b; + end if; + return a; + end function IntSelect; + + -- Select one of two reals based on a Boolean. + function RealSelect(s : in boolean; a : in real; b : in real) return real is + begin + if s then + return a; + else + return b; + end if; + return a; + end function RealSelect; + + -- Convert a binary number to a graycode number. + function BinaryToGray(b : in std_logic_vector) return std_logic_vector is + variable g : std_logic_vector(b'range); + begin + for i in b'low to b'high-1 loop + g(i) := b(i) xor b(i+1); + end loop; + g(b'high) := b(b'high); + return g; + end function BinaryToGray; + + -- Convert a graycode number to a binary number. + function GrayToBinary(g : in std_logic_vector) return std_logic_vector is + variable b : std_logic_vector(g'range); + begin + b(b'high) := g(b'high); + for i in g'high-1 downto g'low loop + b(i) := b(i+1) xor g(i); + end loop; + return b; + end function GrayToBinary; + + -- Find the maximum of two integers. + function IntMax(a : in integer; b : in integer) return integer is + begin + if a > b then + return a; + else + return b; + end if; + return a; + end function IntMax; + +end package body; Index: fat_32_file_parser/trunk/lifo.vhd =================================================================== --- fat_32_file_parser/trunk/lifo.vhd (nonexistent) +++ fat_32_file_parser/trunk/lifo.vhd (revision 2) @@ -0,0 +1,160 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 21:09:44 11/18/2014 +-- Design Name: +-- Module Name: lifo - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity lifo is + Generic ( G_LOG2_DEPTH : natural := 6; + G_DATA_SIZE : natural := 8 ); -- LOG2(lifo depth) + Port ( CLK_IN : in STD_LOGIC; + RESET_IN : in STD_LOGIC; + CACHE_ADDR_IN : in STD_LOGIC; + GOTO_CACHE_IN : in STD_LOGIC; + WR_DATA_IN : in STD_LOGIC_VECTOR ((G_DATA_SIZE - 1) downto 0); + WR_EN_IN : in STD_LOGIC; + RD_DATA_OUT : out STD_LOGIC_VECTOR ((G_DATA_SIZE - 1) downto 0); + RD_EN_IN : in STD_LOGIC; + EMPTY_OUT : out STD_LOGIC; + FULL_OUT : out STD_LOGIC); + + attribute ram_style : string; + attribute ram_style of lifo : entity is "block"; + +end lifo; + +architecture Behavioral of lifo is + + COMPONENT TDP_RAM + Generic (G_DATA_A_SIZE :natural :=32; + G_ADDR_A_SIZE :natural :=9; + G_RELATION :natural :=3; + G_INIT_FILE :string :="");--log2(SIZE_A/SIZE_B) + Port ( CLK_A_IN : in STD_LOGIC; + WE_A_IN : in STD_LOGIC; + ADDR_A_IN : in STD_LOGIC_VECTOR (G_ADDR_A_SIZE-1 downto 0); + DATA_A_IN : in STD_LOGIC_VECTOR (G_DATA_A_SIZE-1 downto 0); + DATA_A_OUT : out STD_LOGIC_VECTOR (G_DATA_A_SIZE-1 downto 0); + CLK_B_IN : in STD_LOGIC; + WE_B_IN : in STD_LOGIC; + ADDR_B_IN : in STD_LOGIC_VECTOR (G_ADDR_A_SIZE+G_RELATION-1 downto 0); + DATA_B_IN : in STD_LOGIC_VECTOR (G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0); + DATA_B_OUT : out STD_LOGIC_VECTOR (G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0)); + END COMPONENT; + +subtype slv is std_logic_vector; + +constant C_max : unsigned((G_LOG2_DEPTH - 1) downto 0) := (others => '1'); +constant C_min : unsigned((G_LOG2_DEPTH - 1) downto 0) := (others => '0'); + +signal wr_addr : unsigned((G_LOG2_DEPTH - 1) downto 0) := C_min; +signal rd_addr : unsigned((G_LOG2_DEPTH - 1) downto 0) := C_min; +signal cached_addr : unsigned((G_LOG2_DEPTH - 1) downto 0) := (others => '0'); +signal zeros : std_logic_vector((G_DATA_SIZE - 1) downto 0) := (others => '0'); + +begin + + process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if RESET_IN = '1' then + wr_addr <= (others => '0'); + rd_addr <= (others => '0'); + elsif GOTO_CACHE_IN = '0' then + if WR_EN_IN = '1' then + if wr_addr /= C_max then + wr_addr <= wr_addr + 1; + end if; + if rd_addr /= C_max and wr_addr /= C_min then + rd_addr <= rd_addr + 1; + end if; + elsif RD_EN_IN = '1' then + if rd_addr /= C_min then + rd_addr <= rd_addr - 1; + end if; + if wr_addr /= C_min and rd_addr /= C_max then + wr_addr <= wr_addr - 1; + end if; + end if; + else + wr_addr <= cached_addr + 1; + rd_addr <= cached_addr; + end if; + end if; + end process; + + process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if CACHE_ADDR_IN = '1' then + cached_addr <= rd_addr; + elsif RESET_IN = '1' then + cached_addr <= (others => '0'); + end if; + end if; + end process; + + process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if RESET_IN = '1' then + EMPTY_OUT <= '1'; + elsif WR_EN_IN = '1' or GOTO_CACHE_IN = '1' then + EMPTY_OUT <= '0'; + elsif wr_addr = C_min then + EMPTY_OUT <= '1'; + end if; + end if; + end process; + + process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if RD_EN_IN = '1' then + FULL_OUT <= '0'; + elsif rd_addr = C_max then + FULL_OUT <= '1'; + end if; + end if; + end process; + + TDP_RAM_Inst : TDP_RAM + Generic Map ( G_DATA_A_SIZE => G_DATA_SIZE, + G_ADDR_A_SIZE => G_LOG2_DEPTH, + G_RELATION => 0, --log2(SIZE_A/SIZE_B) + G_INIT_FILE => "") + Port Map ( CLK_A_IN => CLK_IN, + WE_A_IN => WR_EN_IN, + ADDR_A_IN => slv(wr_addr), + DATA_A_IN => WR_DATA_IN, + DATA_A_OUT => open, + CLK_B_IN => CLK_IN, + WE_B_IN => '0', + ADDR_B_IN => slv(rd_addr), + DATA_B_IN => zeros, + DATA_B_OUT => RD_DATA_OUT); + +end Behavioral; + Index: fat_32_file_parser/trunk/user_input_handler.vhd =================================================================== --- fat_32_file_parser/trunk/user_input_handler.vhd (nonexistent) +++ fat_32_file_parser/trunk/user_input_handler.vhd (revision 2) @@ -0,0 +1,329 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 10:39:01 10/19/2014 +-- Design Name: +-- Module Name: user_input_handler - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity user_input_handler is + Port ( CLK_IN : in STD_LOGIC; + RX_IN : in STD_LOGIC; + TX_OUT : out STD_LOGIC; + TEXT_ADDR_IN : in STD_LOGIC_VECTOR (11 downto 0); + TEXT_DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0); + FONT_ADDR_IN : in STD_LOGIC_VECTOR (11 downto 0); + FONT_DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0); + CURSORPOS_X_OUT : out STD_LOGIC_VECTOR (7 downto 0); + CURSORPOS_Y_OUT : out STD_LOGIC_VECTOR (7 downto 0); + DEBUG_OUT : out STD_LOGIC_VECTOR(7 downto 0); + DEBUG_OUT2 : out STD_LOGIC_VECTOR(7 downto 0)); +end user_input_handler; + +architecture Behavioral of user_input_handler is + + COMPONENT uart + Generic ( + CLK_FREQ : integer := 50; -- Main frequency (MHz) + SER_FREQ : integer := 9600 -- Baud rate (bps) + ); + Port ( + -- Control + clk : in std_logic; -- Main clock + rst : in std_logic; -- Main reset + -- External Interface + rx : in std_logic; -- RS232 received serial data + tx : out std_logic; -- RS232 transmitted serial data + -- RS232/UART Configuration + par_en : in std_logic; -- Parity bit enable + -- uPC Interface + tx_req : in std_logic; -- Request SEND of data + tx_end : out std_logic; -- Data SENDED + tx_data : in std_logic_vector(7 downto 0); -- Data to transmit + rx_ready : out std_logic; -- Received data ready to uPC read + rx_data : out std_logic_vector(7 downto 0) -- Received data + ); + END COMPONENT; + + COMPONENT TDP_RAM + Generic (G_DATA_A_SIZE :natural :=32; + G_ADDR_A_SIZE :natural :=9; + G_RELATION :natural :=3; + G_INIT_FILE :string :="");--log2(SIZE_A/SIZE_B) + Port ( CLK_A_IN : in STD_LOGIC; + WE_A_IN : in STD_LOGIC; + ADDR_A_IN : in STD_LOGIC_VECTOR (G_ADDR_A_SIZE-1 downto 0); + DATA_A_IN : in STD_LOGIC_VECTOR (G_DATA_A_SIZE-1 downto 0); + DATA_A_OUT : out STD_LOGIC_VECTOR (G_DATA_A_SIZE-1 downto 0); + CLK_B_IN : in STD_LOGIC; + WE_B_IN : in STD_LOGIC; + ADDR_B_IN : in STD_LOGIC_VECTOR (G_ADDR_A_SIZE+G_RELATION-1 downto 0); + DATA_B_IN : in STD_LOGIC_VECTOR (G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0); + DATA_B_OUT : out STD_LOGIC_VECTOR (G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0)); + END COMPONENT; + + COMPONENT FONT_MEM + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); + END COMPONENT; + +subtype slv is std_logic_vector; + +constant C_backspace_cmnd : std_logic_vector(7 downto 0) := X"80"; +constant C_esc_cmnd : std_logic_vector(7 downto 0) := X"81"; +constant C_enter_cmnd : std_logic_vector(7 downto 0) := X"82"; + +constant C_space_char : std_logic_vector(7 downto 0) := X"20"; + +constant C_max_char : std_logic_vector(11 downto 0) := X"C2F"; -- 3119 (zero indexed) +constant C_page_height : std_logic_vector(7 downto 0) := X"26"; -- 39 (zero indexed) +constant C_page_width : std_logic_vector(7 downto 0) := X"4F"; -- 80 (zero indexed) +constant C_page_width_p1 : std_logic_vector(7 downto 0) := X"50"; -- 80 + +signal char_buf_wr, char_cmd_wr : std_logic := '0'; +signal char_buf_wr_addr : unsigned(11 downto 0) := (others => '0'); +signal char_buf_wr_data : std_logic_vector(7 downto 0) := (others => '0'); +signal ocrx, ocry : unsigned(7 downto 0) := (others => '0'); + +signal keyboard_data, keyboard_data_buf : std_logic_vector(7 downto 0) := (others => '0'); +signal keyboard_rd : std_logic := '0'; + +signal char_buf_x_coord : unsigned(7 downto 0); + +signal debug2 : unsigned(7 downto 0) := (others => '0'); + +type HANDLE_KEYBOARD_ST is ( IDLE, + HANDLE_CHARACTER_S0, + HANDLE_CHARACTER_S1, + HANDLE_COMMAND, + HANDLE_BACKSPACE_S0, + HANDLE_BACKSPACE_S1, + HANDLE_ENTER_S0, + HANDLE_ENTER_S1); + +signal hk_state, hk_next_state : HANDLE_KEYBOARD_ST := IDLE; + +begin + + debug2 <= unsigned(keyboard_data); + + ---- CONVERT UART DATA TO KEYBOARD DATA ---- + + uart_inst : uart + GENERIC MAP ( + CLK_FREQ => 100, + SER_FREQ => 9600) + Port Map ( + clk => CLK_IN, + rst => '0', + rx => RX_IN, + tx => TX_OUT, + par_en => '1', + tx_req => '0', + tx_end => open, + tx_data => (others => '0'), + rx_ready => keyboard_rd, + rx_data => keyboard_data); + + ---- HANDLE KEYBOARD DATA ---- + + SYNC_PROC: process(CLK_IN) + begin + if rising_edge(CLK_IN) then + hk_state <= hk_next_state; + end if; + end process; + + process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if hk_state = IDLE and keyboard_rd = '1' then + keyboard_data_buf <= keyboard_data; + end if; + end if; + end process; + + process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if hk_state = HANDLE_CHARACTER_S0 then + char_buf_wr <= '1'; + elsif hk_state = HANDLE_BACKSPACE_S1 then + char_buf_wr <= '1'; + else + char_buf_wr <= '0'; + end if; + end if; + end process; + + process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if hk_state = HANDLE_CHARACTER_S0 then + char_buf_wr_data <= keyboard_data_buf; + elsif hk_state = HANDLE_BACKSPACE_S1 then + char_buf_wr_data <= C_space_char; + end if; + end if; + end process; + + process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if hk_state = HANDLE_CHARACTER_S1 then + char_buf_wr_addr <= char_buf_wr_addr + 1; + elsif hk_state = HANDLE_BACKSPACE_S0 then + char_buf_wr_addr <= char_buf_wr_addr - 1; + elsif hk_state = HANDLE_ENTER_S1 then + char_buf_wr_addr <= char_buf_wr_addr + RESIZE(char_buf_x_coord, 12); + end if; + end if; + end process; + + process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if hk_state = HANDLE_ENTER_S0 then + char_buf_x_coord <= unsigned(C_page_width_p1) - unsigned(ocrx); + end if; + end if; + end process; + + NEXT_STATE_DECODE: process (hk_state, keyboard_rd, keyboard_data(7), keyboard_data_buf) + begin + hk_next_state <= hk_state; --default is to stay in current state + case (hk_state) is + when IDLE => + if keyboard_rd = '1' then + if keyboard_data(7) = '0' then + if slv(char_buf_wr_addr) /= C_max_char then + hk_next_state <= HANDLE_CHARACTER_S0; + else + hk_next_state <= IDLE; + end if; + else + hk_next_state <= HANDLE_COMMAND; + end if; + end if; + when HANDLE_CHARACTER_S0 => + hk_next_state <= HANDLE_CHARACTER_S1; + when HANDLE_CHARACTER_S1 => + hk_next_state <= IDLE; + when HANDLE_COMMAND => + if keyboard_data_buf = C_backspace_cmnd then + if slv(char_buf_wr_addr) /= X"00" then + hk_next_state <= HANDLE_BACKSPACE_S0; + else + hk_next_state <= IDLE; + end if; + elsif keyboard_data_buf = C_enter_cmnd then + hk_next_state <= HANDLE_ENTER_S0; + else + hk_next_state <= IDLE; + end if; + when HANDLE_BACKSPACE_S0 => + hk_next_state <= HANDLE_BACKSPACE_S1; + when HANDLE_BACKSPACE_S1 => + hk_next_state <= IDLE; + when HANDLE_ENTER_S0 => + hk_next_state <= HANDLE_ENTER_S1; + when HANDLE_ENTER_S1 => + hk_next_state <= IDLE; + when others => + hk_next_state <= IDLE; + end case; + end process; + + + DEBUG_OUT <= slv(char_buf_x_coord); + DEBUG_OUT2 <= slv(debug2); + + ---- HANDLE CURSOR POSITION ---- + + CURSORPOS_X_OUT <= slv(ocrx); + CURSORPOS_Y_OUT <= slv(ocry); + + process(CLK_IN) + begin + if rising_edge(CLK_IN) then + if hk_state = HANDLE_CHARACTER_S1 then + if slv(ocrx) = C_page_width and slv(ocry) /= C_page_height then + ocrx <= X"00"; + else + ocrx <= ocrx + 1; + end if; + if slv(ocrx) = C_page_width then + if slv(ocry) /= C_page_height then + ocry <= ocry + 1; + end if; + end if; + elsif hk_state = HANDLE_BACKSPACE_S1 then + if slv(ocrx) = X"00" and slv(ocry) /= X"00" then + ocrx <= unsigned(C_page_width); + else + ocrx <= ocrx - 1; + end if; + if slv(ocrx) = X"00" then + if ocry /= X"00" then + ocry <= ocry - 1; + end if; + end if; + elsif hk_state = HANDLE_ENTER_S0 and slv(ocry) /= C_page_height then + ocrx <= X"00"; + ocry <= ocry + 1; + end if; + end if; + end process; + + ---- SCREEN MEMORY ---- + + char_buf : TDP_RAM + Generic Map ( G_DATA_A_SIZE => TEXT_DATA_OUT'length, + G_ADDR_A_SIZE => TEXT_ADDR_IN'length, + G_RELATION => 0, --log2(SIZE_A/SIZE_B) + G_INIT_FILE => "./coe_dir/ascii_space.coe") + Port Map ( CLK_A_IN => CLK_IN, + WE_A_IN => '0', + ADDR_A_IN => TEXT_ADDR_IN, + DATA_A_IN => X"00", + DATA_A_OUT => TEXT_DATA_OUT, + CLK_B_IN => CLK_IN, + WE_B_IN => char_buf_wr, + ADDR_B_IN => slv(char_buf_wr_addr), + DATA_B_IN => char_buf_wr_data, + DATA_B_OUT => open); + + Font_Mem_inst : FONT_MEM + PORT MAP ( + clka => CLK_IN, + wea => "0", + addra => FONT_ADDR_IN, + dina => (others => '0'), + douta => FONT_DATA_OUT); + +end Behavioral; +

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