OpenCores
URL https://opencores.org/ocsvn/fpuvhdl/fpuvhdl/trunk

Subversion Repositories fpuvhdl

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /fpuvhdl/trunk/fpuvhdl/multiplier
    from Rev 4 to Rev 5
    ↔ Reverse comparison
  •

Rev 4 → Rev 5

/fpmul_single_cycle.vhd
0,0 → 1,342
-- VHDL Entity HAVOC.FPmul.symbol
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
-- using Mentor Graphics FPGA Advantage tools.
--
-- Visit "http://fpga.mty.itesm.mx" for more info.
--
-- 2003-2004. V1.0
--
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ENTITY FPmul IS
PORT(
FP_A : IN std_logic_vector (31 DOWNTO 0);
FP_B : IN std_logic_vector (31 DOWNTO 0);
clk : IN std_logic;
FP_Z : OUT std_logic_vector (31 DOWNTO 0)
);
 
-- Declarations
 
END FPmul ;
 
--
-- VHDL Architecture HAVOC.FPmul.single_cycle
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
-- using Mentor Graphics FPGA Advantage tools.
--
-- Visit "http://fpga.mty.itesm.mx" for more info.
--
-- Copyright 2003-2004. V1.0
--
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ARCHITECTURE single_cycle OF FPmul IS
 
-- Architecture declarations
-- Non hierarchical truthtable declarations
 
 
-- Internal signal declarations
SIGNAL A_EXP : std_logic_vector(7 DOWNTO 0);
SIGNAL A_SIG : std_logic_vector(31 DOWNTO 0);
SIGNAL A_SIGN : std_logic;
SIGNAL A_isINF : std_logic;
SIGNAL A_isNaN : std_logic;
SIGNAL A_isZ : std_logic;
SIGNAL B_EXP : std_logic_vector(7 DOWNTO 0);
SIGNAL B_SIG : std_logic_vector(31 DOWNTO 0);
SIGNAL B_SIGN : std_logic;
SIGNAL B_isINF : std_logic;
SIGNAL B_isNaN : std_logic;
SIGNAL B_isZ : std_logic;
SIGNAL EXP_addout : std_logic_vector(7 DOWNTO 0);
SIGNAL EXP_in : std_logic_vector(7 DOWNTO 0);
SIGNAL EXP_out : std_logic_vector(7 DOWNTO 0);
SIGNAL EXP_out_norm : std_logic_vector(7 DOWNTO 0);
SIGNAL EXP_out_round : std_logic_vector(7 DOWNTO 0);
SIGNAL SIGN_out : std_logic;
SIGNAL SIG_in : std_logic_vector(27 DOWNTO 0);
SIGNAL SIG_isZ : std_logic;
SIGNAL SIG_out : std_logic_vector(22 DOWNTO 0);
SIGNAL SIG_out_norm : std_logic_vector(27 DOWNTO 0);
SIGNAL SIG_out_norm2 : std_logic_vector(27 DOWNTO 0);
SIGNAL SIG_out_round : std_logic_vector(27 DOWNTO 0);
SIGNAL dout : std_logic;
SIGNAL isINF : std_logic;
SIGNAL isINF_tab : std_logic;
SIGNAL isNaN : std_logic;
SIGNAL isZ : std_logic;
SIGNAL isZ_tab : std_logic;
SIGNAL prod : std_logic_vector(63 DOWNTO 0);
 
 
-- Component Declarations
COMPONENT FPnormalize
GENERIC (
SIG_width : integer := 28
);
PORT (
SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
EXP_in : IN std_logic_vector (7 DOWNTO 0);
SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
EXP_out : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT FPround
GENERIC (
SIG_width : integer := 28
);
PORT (
SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
EXP_in : IN std_logic_vector (7 DOWNTO 0);
SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
EXP_out : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT PackFP
PORT (
SIGN : IN std_logic ;
EXP : IN std_logic_vector (7 DOWNTO 0);
SIG : IN std_logic_vector (22 DOWNTO 0);
isNaN : IN std_logic ;
isINF : IN std_logic ;
isZ : IN std_logic ;
FP : OUT std_logic_vector (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT UnpackFP
PORT (
FP : IN std_logic_vector (31 DOWNTO 0);
SIG : OUT std_logic_vector (31 DOWNTO 0);
EXP : OUT std_logic_vector (7 DOWNTO 0);
SIGN : OUT std_logic ;
isNaN : OUT std_logic ;
isINF : OUT std_logic ;
isZ : OUT std_logic ;
isDN : OUT std_logic
);
END COMPONENT;
 
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : FPnormalize USE ENTITY work.FPnormalize;
FOR ALL : FPround USE ENTITY work.FPround;
FOR ALL : PackFP USE ENTITY work.PackFP;
FOR ALL : UnpackFP USE ENTITY work.UnpackFP;
-- pragma synthesis_on
 
 
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 1 eb1
-- eb1 1
SIG_in <= prod(47 DOWNTO 20);
 
-- HDL Embedded Text Block 2 eb2
-- eb2
SIG_out <= SIG_out_norm2(25 DOWNTO 3);
 
-- HDL Embedded Text Block 3 eb3
-- eb3 3
PROCESS(isZ,isINF_tab, A_EXP, B_EXP, EXP_out)
BEGIN
IF isZ='0' THEN
IF isINF_tab='1' THEN
isINF <= '1';
ELSIF EXP_out=X"FF" THEN
isINF <='1';
ELSIF (A_EXP(7)='1' AND B_EXP(7)='1' AND (EXP_out(7)='0')) THEN
isINF <='1';
ELSE
isINF <= '0';
END IF;
ELSE
isINF <= '0';
END IF;
END PROCESS;
 
-- HDL Embedded Block 4 eb4
-- Non hierarchical truthtable
---------------------------------------------------------------------------
eb4_truth_process: PROCESS(A_isINF, A_isNaN, A_isZ, B_isINF, B_isNaN, B_isZ)
---------------------------------------------------------------------------
BEGIN
-- Block 1
IF (A_isINF = '0') AND (A_isNaN = '0') AND (A_isZ = '0') AND (B_isINF = '0') AND (B_isNaN = '0') AND (B_isZ = '0') THEN
isZ_tab <= '0';
isINF_tab <= '0';
isNaN <= '0';
ELSIF (A_isINF = '1') AND (B_isZ = '1') THEN
isZ_tab <= '0';
isINF_tab <= '0';
isNaN <= '1';
ELSIF (A_isZ = '1') AND (B_isINF = '1') THEN
isZ_tab <= '0';
isINF_tab <= '0';
isNaN <= '1';
ELSIF (A_isINF = '1') THEN
isZ_tab <= '0';
isINF_tab <= '1';
isNaN <= '0';
ELSIF (B_isINF = '1') THEN
isZ_tab <= '0';
isINF_tab <= '1';
isNaN <= '0';
ELSIF (A_isNaN = '1') THEN
isZ_tab <= '0';
isINF_tab <= '0';
isNaN <= '1';
ELSIF (B_isNaN = '1') THEN
isZ_tab <= '0';
isINF_tab <= '0';
isNaN <= '1';
ELSIF (A_isZ = '1') THEN
isZ_tab <= '1';
isINF_tab <= '0';
isNaN <= '0';
ELSIF (B_isZ = '1') THEN
isZ_tab <= '1';
isINF_tab <= '0';
isNaN <= '0';
ELSE
isZ_tab <= '0';
isINF_tab <= '0';
isNaN <= '0';
END IF;
 
END PROCESS eb4_truth_process;
 
-- Architecture concurrent statements
 
 
-- HDL Embedded Text Block 5 eb5
-- eb5 5
EXP_in <= (NOT EXP_addout(7)) & EXP_addout(6 DOWNTO 0);
 
-- HDL Embedded Text Block 6 eb6
-- eb6 6
PROCESS(SIG_out_norm2,A_EXP,B_EXP, EXP_out)
BEGIN
IF ( EXP_out(7)='1' AND
( (A_EXP(7)='0' AND NOT (A_EXP=X"7F")) AND
(B_EXP(7)='0' AND NOT (B_EXP=X"7F")) ) ) OR
(SIG_out_norm2(26 DOWNTO 3)=X"000000") THEN
-- Underflow or zero significand
SIG_isZ <= '1';
ELSE
SIG_isZ <= '0';
END IF;
END PROCESS;
 
 
-- ModuleWare code(v1.1) for instance 'I4' of 'add'
I4combo: PROCESS (A_EXP, B_EXP, dout)
VARIABLE mw_I4t0 : std_logic_vector(8 DOWNTO 0);
VARIABLE mw_I4t1 : std_logic_vector(8 DOWNTO 0);
VARIABLE mw_I4sum : unsigned(8 DOWNTO 0);
VARIABLE mw_I4carry : std_logic;
BEGIN
mw_I4t0 := '0' & A_EXP;
mw_I4t1 := '0' & B_EXP;
mw_I4carry := dout;
mw_I4sum := unsigned(mw_I4t0) + unsigned(mw_I4t1) + mw_I4carry;
EXP_addout <= conv_std_logic_vector(mw_I4sum(7 DOWNTO 0),8);
END PROCESS I4combo;
 
-- ModuleWare code(v1.1) for instance 'I2' of 'mult'
I2combo : PROCESS (A_SIG, B_SIG)
VARIABLE dtemp : unsigned(63 DOWNTO 0);
BEGIN
dtemp := (unsigned(A_SIG) * unsigned(B_SIG));
prod <= std_logic_vector(dtemp);
END PROCESS I2combo;
 
-- ModuleWare code(v1.1) for instance 'I7' of 'or'
isZ <= SIG_isZ OR isZ_tab;
 
-- ModuleWare code(v1.1) for instance 'I6' of 'vdd'
dout <= '1';
 
-- ModuleWare code(v1.1) for instance 'I3' of 'xor'
SIGN_out <= A_SIGN XOR B_SIGN;
 
-- Instance port mappings.
I9 : FPnormalize
GENERIC MAP (
SIG_width => 28
)
PORT MAP (
SIG_in => SIG_in,
EXP_in => EXP_in,
SIG_out => SIG_out_norm,
EXP_out => EXP_out_norm
);
I10 : FPnormalize
GENERIC MAP (
SIG_width => 28
)
PORT MAP (
SIG_in => SIG_out_round,
EXP_in => EXP_out_round,
SIG_out => SIG_out_norm2,
EXP_out => EXP_out
);
I11 : FPround
GENERIC MAP (
SIG_width => 28
)
PORT MAP (
SIG_in => SIG_out_norm,
EXP_in => EXP_out_norm,
SIG_out => SIG_out_round,
EXP_out => EXP_out_round
);
I5 : PackFP
PORT MAP (
SIGN => SIGN_out,
EXP => EXP_out,
SIG => SIG_out,
isNaN => isNaN,
isINF => isINF,
isZ => isZ,
FP => FP_Z
);
I0 : UnpackFP
PORT MAP (
FP => FP_A,
SIG => A_SIG,
EXP => A_EXP,
SIGN => A_SIGN,
isNaN => A_isNaN,
isINF => A_isINF,
isZ => A_isZ,
isDN => OPEN
);
I1 : UnpackFP
PORT MAP (
FP => FP_B,
SIG => B_SIG,
EXP => B_EXP,
SIGN => B_SIGN,
isNaN => B_isNaN,
isINF => B_isINF,
isZ => B_isZ,
isDN => OPEN
);
 
END single_cycle;
/fpmul_pipeline.vhd
0,0 → 1,229
-- VHDL Entity HAVOC.FPmul.symbol
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
-- using Mentor Graphics FPGA Advantage tools.
--
-- Visit "http://fpga.mty.itesm.mx" for more info.
--
-- 2003-2004. V1.0
--
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ENTITY FPmul IS
PORT(
FP_A : IN std_logic_vector (31 DOWNTO 0);
FP_B : IN std_logic_vector (31 DOWNTO 0);
clk : IN std_logic;
FP_Z : OUT std_logic_vector (31 DOWNTO 0)
);
 
-- Declarations
 
END FPmul ;
 
--
-- VHDL Architecture HAVOC.FPmul.pipeline
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
-- using Mentor Graphics FPGA Advantage tools.
--
-- Visit "http://fpga.mty.itesm.mx" for more info.
--
-- Copyright 2003-2004. V1.0
--
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ARCHITECTURE pipeline OF FPmul IS
 
-- Architecture declarations
 
-- Internal signal declarations
SIGNAL A_EXP : std_logic_vector(7 DOWNTO 0);
SIGNAL A_SIG : std_logic_vector(31 DOWNTO 0);
SIGNAL B_EXP : std_logic_vector(7 DOWNTO 0);
SIGNAL B_SIG : std_logic_vector(31 DOWNTO 0);
SIGNAL EXP_in : std_logic_vector(7 DOWNTO 0);
SIGNAL EXP_neg : std_logic;
SIGNAL EXP_neg_stage2 : std_logic;
SIGNAL EXP_out_round : std_logic_vector(7 DOWNTO 0);
SIGNAL EXP_pos : std_logic;
SIGNAL EXP_pos_stage2 : std_logic;
SIGNAL SIGN_out : std_logic;
SIGNAL SIGN_out_stage1 : std_logic;
SIGNAL SIGN_out_stage2 : std_logic;
SIGNAL SIG_in : std_logic_vector(27 DOWNTO 0);
SIGNAL SIG_out_round : std_logic_vector(27 DOWNTO 0);
SIGNAL isINF_stage1 : std_logic;
SIGNAL isINF_stage2 : std_logic;
SIGNAL isINF_tab : std_logic;
SIGNAL isNaN : std_logic;
SIGNAL isNaN_stage1 : std_logic;
SIGNAL isNaN_stage2 : std_logic;
SIGNAL isZ_tab : std_logic;
SIGNAL isZ_tab_stage1 : std_logic;
SIGNAL isZ_tab_stage2 : std_logic;
 
 
-- Component Declarations
COMPONENT FPmul_stage1
PORT (
FP_A : IN std_logic_vector (31 DOWNTO 0);
FP_B : IN std_logic_vector (31 DOWNTO 0);
clk : IN std_logic ;
A_EXP : OUT std_logic_vector (7 DOWNTO 0);
A_SIG : OUT std_logic_vector (31 DOWNTO 0);
B_EXP : OUT std_logic_vector (7 DOWNTO 0);
B_SIG : OUT std_logic_vector (31 DOWNTO 0);
SIGN_out_stage1 : OUT std_logic ;
isINF_stage1 : OUT std_logic ;
isNaN_stage1 : OUT std_logic ;
isZ_tab_stage1 : OUT std_logic
);
END COMPONENT;
COMPONENT FPmul_stage2
PORT (
A_EXP : IN std_logic_vector (7 DOWNTO 0);
A_SIG : IN std_logic_vector (31 DOWNTO 0);
B_EXP : IN std_logic_vector (7 DOWNTO 0);
B_SIG : IN std_logic_vector (31 DOWNTO 0);
SIGN_out_stage1 : IN std_logic ;
clk : IN std_logic ;
isINF_stage1 : IN std_logic ;
isNaN_stage1 : IN std_logic ;
isZ_tab_stage1 : IN std_logic ;
EXP_in : OUT std_logic_vector (7 DOWNTO 0);
EXP_neg_stage2 : OUT std_logic ;
EXP_pos_stage2 : OUT std_logic ;
SIGN_out_stage2 : OUT std_logic ;
SIG_in : OUT std_logic_vector (27 DOWNTO 0);
isINF_stage2 : OUT std_logic ;
isNaN_stage2 : OUT std_logic ;
isZ_tab_stage2 : OUT std_logic
);
END COMPONENT;
COMPONENT FPmul_stage3
PORT (
EXP_in : IN std_logic_vector (7 DOWNTO 0);
EXP_neg_stage2 : IN std_logic ;
EXP_pos_stage2 : IN std_logic ;
SIGN_out_stage2 : IN std_logic ;
SIG_in : IN std_logic_vector (27 DOWNTO 0);
clk : IN std_logic ;
isINF_stage2 : IN std_logic ;
isNaN_stage2 : IN std_logic ;
isZ_tab_stage2 : IN std_logic ;
EXP_neg : OUT std_logic ;
EXP_out_round : OUT std_logic_vector (7 DOWNTO 0);
EXP_pos : OUT std_logic ;
SIGN_out : OUT std_logic ;
SIG_out_round : OUT std_logic_vector (27 DOWNTO 0);
isINF_tab : OUT std_logic ;
isNaN : OUT std_logic ;
isZ_tab : OUT std_logic
);
END COMPONENT;
COMPONENT FPmul_stage4
PORT (
EXP_neg : IN std_logic ;
EXP_out_round : IN std_logic_vector (7 DOWNTO 0);
EXP_pos : IN std_logic ;
SIGN_out : IN std_logic ;
SIG_out_round : IN std_logic_vector (27 DOWNTO 0);
clk : IN std_logic ;
isINF_tab : IN std_logic ;
isNaN : IN std_logic ;
isZ_tab : IN std_logic ;
FP_Z : OUT std_logic_vector (31 DOWNTO 0)
);
END COMPONENT;
 
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : FPmul_stage1 USE ENTITY work.FPmul_stage1;
FOR ALL : FPmul_stage2 USE ENTITY work.FPmul_stage2;
FOR ALL : FPmul_stage3 USE ENTITY work.FPmul_stage3;
FOR ALL : FPmul_stage4 USE ENTITY work.FPmul_stage4;
-- pragma synthesis_on
 
 
BEGIN
 
-- Instance port mappings.
I1 : FPmul_stage1
PORT MAP (
FP_A => FP_A,
FP_B => FP_B,
clk => clk,
A_EXP => A_EXP,
A_SIG => A_SIG,
B_EXP => B_EXP,
B_SIG => B_SIG,
SIGN_out_stage1 => SIGN_out_stage1,
isINF_stage1 => isINF_stage1,
isNaN_stage1 => isNaN_stage1,
isZ_tab_stage1 => isZ_tab_stage1
);
I2 : FPmul_stage2
PORT MAP (
A_EXP => A_EXP,
A_SIG => A_SIG,
B_EXP => B_EXP,
B_SIG => B_SIG,
SIGN_out_stage1 => SIGN_out_stage1,
clk => clk,
isINF_stage1 => isINF_stage1,
isNaN_stage1 => isNaN_stage1,
isZ_tab_stage1 => isZ_tab_stage1,
EXP_in => EXP_in,
EXP_neg_stage2 => EXP_neg_stage2,
EXP_pos_stage2 => EXP_pos_stage2,
SIGN_out_stage2 => SIGN_out_stage2,
SIG_in => SIG_in,
isINF_stage2 => isINF_stage2,
isNaN_stage2 => isNaN_stage2,
isZ_tab_stage2 => isZ_tab_stage2
);
I3 : FPmul_stage3
PORT MAP (
EXP_in => EXP_in,
EXP_neg_stage2 => EXP_neg_stage2,
EXP_pos_stage2 => EXP_pos_stage2,
SIGN_out_stage2 => SIGN_out_stage2,
SIG_in => SIG_in,
clk => clk,
isINF_stage2 => isINF_stage2,
isNaN_stage2 => isNaN_stage2,
isZ_tab_stage2 => isZ_tab_stage2,
EXP_neg => EXP_neg,
EXP_out_round => EXP_out_round,
EXP_pos => EXP_pos,
SIGN_out => SIGN_out,
SIG_out_round => SIG_out_round,
isINF_tab => isINF_tab,
isNaN => isNaN,
isZ_tab => isZ_tab
);
I4 : FPmul_stage4
PORT MAP (
EXP_neg => EXP_neg,
EXP_out_round => EXP_out_round,
EXP_pos => EXP_pos,
SIGN_out => SIGN_out,
SIG_out_round => SIG_out_round,
clk => clk,
isINF_tab => isINF_tab,
isNaN => isNaN,
isZ_tab => isZ_tab,
FP_Z => FP_Z
);
 
END pipeline;
/fpmul_stage1_struct.vhd
0,0 → 1,201
-- VHDL Entity HAVOC.FPmul_stage1.interface
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
-- using Mentor Graphics FPGA Advantage tools.
--
-- Visit "http://fpga.mty.itesm.mx" for more info.
--
-- 2003-2004. V1.0
--
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ENTITY FPmul_stage1 IS
PORT(
FP_A : IN std_logic_vector (31 DOWNTO 0);
FP_B : IN std_logic_vector (31 DOWNTO 0);
clk : IN std_logic;
A_EXP : OUT std_logic_vector (7 DOWNTO 0);
A_SIG : OUT std_logic_vector (31 DOWNTO 0);
B_EXP : OUT std_logic_vector (7 DOWNTO 0);
B_SIG : OUT std_logic_vector (31 DOWNTO 0);
SIGN_out_stage1 : OUT std_logic;
isINF_stage1 : OUT std_logic;
isNaN_stage1 : OUT std_logic;
isZ_tab_stage1 : OUT std_logic
);
 
-- Declarations
 
END FPmul_stage1 ;
 
--
-- VHDL Architecture HAVOC.FPmul_stage1.struct
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
-- using Mentor Graphics FPGA Advantage tools.
--
-- Visit "http://fpga.mty.itesm.mx" for more info.
--
-- Copyright 2003-2004. V1.0
--
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
 
ARCHITECTURE struct OF FPmul_stage1 IS
 
-- Architecture declarations
-- Non hierarchical truthtable declarations
 
 
-- Internal signal declarations
SIGNAL A_EXP_int : std_logic_vector(7 DOWNTO 0);
SIGNAL A_SIGN : std_logic;
SIGNAL A_SIG_int : std_logic_vector(31 DOWNTO 0);
SIGNAL A_isINF : std_logic;
SIGNAL A_isNaN : std_logic;
SIGNAL A_isZ : std_logic;
SIGNAL B_EXP_int : std_logic_vector(7 DOWNTO 0);
SIGNAL B_SIGN : std_logic;
SIGNAL B_SIG_int : std_logic_vector(31 DOWNTO 0);
SIGNAL B_isINF : std_logic;
SIGNAL B_isNaN : std_logic;
SIGNAL B_isZ : std_logic;
SIGNAL SIGN_out_int : std_logic;
SIGNAL isINF_int : std_logic;
SIGNAL isNaN_int : std_logic;
SIGNAL isZ_tab_int : std_logic;
 
 
-- Component Declarations
COMPONENT UnpackFP
PORT (
FP : IN std_logic_vector (31 DOWNTO 0);
SIG : OUT std_logic_vector (31 DOWNTO 0);
EXP : OUT std_logic_vector (7 DOWNTO 0);
SIGN : OUT std_logic ;
isNaN : OUT std_logic ;
isINF : OUT std_logic ;
isZ : OUT std_logic ;
isDN : OUT std_logic
);
END COMPONENT;
 
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : UnpackFP USE ENTITY work.UnpackFP;
-- pragma synthesis_on
 
 
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 1 latch
-- latch 1
PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
SIGN_out_stage1 <= SIGN_out_int;
A_EXP <= A_EXP_int;
A_SIG <= A_SIG_int;
isINF_stage1 <= isINF_int;
isNaN_stage1 <= isNaN_int;
isZ_tab_stage1 <= isZ_tab_int;
B_EXP <= B_EXP_int;
B_SIG <= B_SIG_int;
END IF;
END PROCESS;
 
-- HDL Embedded Block 2 exceptions
-- Non hierarchical truthtable
---------------------------------------------------------------------------
exceptions_truth_process: PROCESS(A_isINF, A_isNaN, A_isZ, B_isINF, B_isNaN, B_isZ)
---------------------------------------------------------------------------
BEGIN
-- Block 1
IF (A_isINF = '0') AND (A_isNaN = '0') AND (A_isZ = '0') AND (B_isINF = '0') AND (B_isNaN = '0') AND (B_isZ = '0') THEN
isZ_tab_int <= '0';
isINF_int <= '0';
isNaN_int <= '0';
ELSIF (A_isINF = '1') AND (B_isZ = '1') THEN
isZ_tab_int <= '0';
isINF_int <= '0';
isNaN_int <= '1';
ELSIF (A_isZ = '1') AND (B_isINF = '1') THEN
isZ_tab_int <= '0';
isINF_int <= '0';
isNaN_int <= '1';
ELSIF (A_isINF = '1') THEN
isZ_tab_int <= '0';
isINF_int <= '1';
isNaN_int <= '0';
ELSIF (B_isINF = '1') THEN
isZ_tab_int <= '0';
isINF_int <= '1';
isNaN_int <= '0';
ELSIF (A_isNaN = '1') THEN
isZ_tab_int <= '0';
isINF_int <= '0';
isNaN_int <= '1';
ELSIF (B_isNaN = '1') THEN
isZ_tab_int <= '0';
isINF_int <= '0';
isNaN_int <= '1';
ELSIF (A_isZ = '1') THEN
isZ_tab_int <= '1';
isINF_int <= '0';
isNaN_int <= '0';
ELSIF (B_isZ = '1') THEN
isZ_tab_int <= '1';
isINF_int <= '0';
isNaN_int <= '0';
ELSE
isZ_tab_int <= '0';
isINF_int <= '0';
isNaN_int <= '0';
END IF;
 
END PROCESS exceptions_truth_process;
 
-- Architecture concurrent statements
 
 
 
-- ModuleWare code(v1.1) for instance 'I3' of 'xor'
SIGN_out_int <= A_SIGN XOR B_SIGN;
 
-- Instance port mappings.
I0 : UnpackFP
PORT MAP (
FP => FP_A,
SIG => A_SIG_int,
EXP => A_EXP_int,
SIGN => A_SIGN,
isNaN => A_isNaN,
isINF => A_isINF,
isZ => A_isZ,
isDN => OPEN
);
I1 : UnpackFP
PORT MAP (
FP => FP_B,
SIG => B_SIG_int,
EXP => B_EXP_int,
SIGN => B_SIGN,
isNaN => B_isNaN,
isINF => B_isINF,
isZ => B_isZ,
isDN => OPEN
);
 
END struct;
/fpmul_stage2_struct.vhd
0,0 → 1,143
-- VHDL Entity HAVOC.FPmul_stage2.interface
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
-- using Mentor Graphics FPGA Advantage tools.
--
-- Visit "http://fpga.mty.itesm.mx" for more info.
--
-- 2003-2004. V1.0
--
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ENTITY FPmul_stage2 IS
PORT(
A_EXP : IN std_logic_vector (7 DOWNTO 0);
A_SIG : IN std_logic_vector (31 DOWNTO 0);
B_EXP : IN std_logic_vector (7 DOWNTO 0);
B_SIG : IN std_logic_vector (31 DOWNTO 0);
SIGN_out_stage1 : IN std_logic;
clk : IN std_logic;
isINF_stage1 : IN std_logic;
isNaN_stage1 : IN std_logic;
isZ_tab_stage1 : IN std_logic;
EXP_in : OUT std_logic_vector (7 DOWNTO 0);
EXP_neg_stage2 : OUT std_logic;
EXP_pos_stage2 : OUT std_logic;
SIGN_out_stage2 : OUT std_logic;
SIG_in : OUT std_logic_vector (27 DOWNTO 0);
isINF_stage2 : OUT std_logic;
isNaN_stage2 : OUT std_logic;
isZ_tab_stage2 : OUT std_logic
);
 
-- Declarations
 
END FPmul_stage2 ;
 
--
-- VHDL Architecture HAVOC.FPmul_stage2.struct
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
-- using Mentor Graphics FPGA Advantage tools.
--
-- Visit "http://fpga.mty.itesm.mx" for more info.
--
-- Copyright 2003-2004. V1.0
--
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
 
ARCHITECTURE struct OF FPmul_stage2 IS
 
-- Architecture declarations
 
-- Internal signal declarations
SIGNAL EXP_in_int : std_logic_vector(7 DOWNTO 0);
SIGNAL EXP_neg_int : std_logic;
SIGNAL EXP_pos_int : std_logic;
SIGNAL SIG_in_int : std_logic_vector(27 DOWNTO 0);
SIGNAL dout : std_logic;
SIGNAL dout1 : std_logic_vector(7 DOWNTO 0);
SIGNAL prod : std_logic_vector(63 DOWNTO 0);
 
 
 
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 1 sig
-- eb1 1
SIG_in_int <= prod(47 DOWNTO 20);
 
-- HDL Embedded Text Block 2 inv
-- eb5 5
EXP_in_int <= (NOT dout1(7)) & dout1(6 DOWNTO 0);
 
-- HDL Embedded Text Block 3 latch
-- eb2 2
PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
EXP_in <= EXP_in_int;
SIG_in <= SIG_in_int;
EXP_pos_stage2 <= EXP_pos_int;
EXP_neg_stage2 <= EXP_neg_int;
END IF;
END PROCESS;
 
-- HDL Embedded Text Block 4 latch2
-- latch2 4
PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
isINF_stage2 <= isINF_stage1;
isNaN_stage2 <= isNaN_stage1;
isZ_tab_stage2 <= isZ_tab_stage1;
SIGN_out_stage2 <= SIGN_out_stage1;
END IF;
END PROCESS;
 
-- HDL Embedded Text Block 5 eb1
-- exp_pos 5
EXP_pos_int <= A_EXP(7) AND B_EXP(7);
-- EXP_neg_int <= NOT(A_EXP(7) OR B_EXP(7));
EXP_neg_int <= '1' WHEN ( (A_EXP(7)='0' AND NOT (A_EXP=X"7F")) AND (B_EXP(7)='0' AND NOT (B_EXP=X"7F")) ) ELSE '0';
 
 
-- ModuleWare code(v1.1) for instance 'I4' of 'add'
I4combo: PROCESS (A_EXP, B_EXP, dout)
VARIABLE mw_I4t0 : std_logic_vector(8 DOWNTO 0);
VARIABLE mw_I4t1 : std_logic_vector(8 DOWNTO 0);
VARIABLE mw_I4sum : unsigned(8 DOWNTO 0);
VARIABLE mw_I4carry : std_logic;
BEGIN
mw_I4t0 := '0' & A_EXP;
mw_I4t1 := '0' & B_EXP;
mw_I4carry := dout;
mw_I4sum := unsigned(mw_I4t0) + unsigned(mw_I4t1) + mw_I4carry;
dout1 <= conv_std_logic_vector(mw_I4sum(7 DOWNTO 0),8);
END PROCESS I4combo;
 
-- ModuleWare code(v1.1) for instance 'I2' of 'mult'
I2combo : PROCESS (A_SIG, B_SIG)
VARIABLE dtemp : unsigned(63 DOWNTO 0);
BEGIN
dtemp := (unsigned(A_SIG) * unsigned(B_SIG));
prod <= std_logic_vector(dtemp);
END PROCESS I2combo;
 
-- ModuleWare code(v1.1) for instance 'I6' of 'vdd'
dout <= '1';
 
-- Instance port mappings.
 
END struct;
/fpmul_stage3_struct.vhd
0,0 → 1,149
-- VHDL Entity HAVOC.FPmul_stage3.interface
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
-- using Mentor Graphics FPGA Advantage tools.
--
-- Visit "http://fpga.mty.itesm.mx" for more info.
--
-- 2003-2004. V1.0
--
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ENTITY FPmul_stage3 IS
PORT(
EXP_in : IN std_logic_vector (7 DOWNTO 0);
EXP_neg_stage2 : IN std_logic;
EXP_pos_stage2 : IN std_logic;
SIGN_out_stage2 : IN std_logic;
SIG_in : IN std_logic_vector (27 DOWNTO 0);
clk : IN std_logic;
isINF_stage2 : IN std_logic;
isNaN_stage2 : IN std_logic;
isZ_tab_stage2 : IN std_logic;
EXP_neg : OUT std_logic;
EXP_out_round : OUT std_logic_vector (7 DOWNTO 0);
EXP_pos : OUT std_logic;
SIGN_out : OUT std_logic;
SIG_out_round : OUT std_logic_vector (27 DOWNTO 0);
isINF_tab : OUT std_logic;
isNaN : OUT std_logic;
isZ_tab : OUT std_logic
);
 
-- Declarations
 
END FPmul_stage3 ;
 
--
-- VHDL Architecture HAVOC.FPmul_stage3.struct
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
-- using Mentor Graphics FPGA Advantage tools.
--
-- Visit "http://fpga.mty.itesm.mx" for more info.
--
-- Copyright 2003-2004. V1.0
--
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ARCHITECTURE struct OF FPmul_stage3 IS
 
-- Architecture declarations
 
-- Internal signal declarations
SIGNAL EXP_out : std_logic_vector(7 DOWNTO 0);
SIGNAL EXP_out_norm : std_logic_vector(7 DOWNTO 0);
SIGNAL SIG_out : std_logic_vector(27 DOWNTO 0);
SIGNAL SIG_out_norm : std_logic_vector(27 DOWNTO 0);
 
 
-- Component Declarations
COMPONENT FPnormalize
GENERIC (
SIG_width : integer := 28
);
PORT (
SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
EXP_in : IN std_logic_vector (7 DOWNTO 0);
SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
EXP_out : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT FPround
GENERIC (
SIG_width : integer := 28
);
PORT (
SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
EXP_in : IN std_logic_vector (7 DOWNTO 0);
SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
EXP_out : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
 
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : FPnormalize USE ENTITY work.FPnormalize;
FOR ALL : FPround USE ENTITY work.FPround;
-- pragma synthesis_on
 
 
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 1 latch
-- latch 1
PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
EXP_out_round <= EXP_out;
SIG_out_round <= SIG_out;
END IF;
END PROCESS;
 
-- HDL Embedded Text Block 2 latch2
-- latch2 2
PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
isINF_tab <= isINF_stage2;
isNaN <= isNaN_stage2;
isZ_tab <= isZ_tab_stage2;
SIGN_out <= SIGN_out_stage2;
EXP_pos <= EXP_pos_stage2;
EXP_neg <= EXP_neg_stage2;
END IF;
END PROCESS;
 
 
-- Instance port mappings.
I9 : FPnormalize
GENERIC MAP (
SIG_width => 28
)
PORT MAP (
SIG_in => SIG_in,
EXP_in => EXP_in,
SIG_out => SIG_out_norm,
EXP_out => EXP_out_norm
);
I11 : FPround
GENERIC MAP (
SIG_width => 28
)
PORT MAP (
SIG_in => SIG_out_norm,
EXP_in => EXP_out_norm,
SIG_out => SIG_out,
EXP_out => EXP_out
);
 
END struct;
/fpmul_stage4_struct.vhd
0,0 → 1,161
-- VHDL Entity HAVOC.FPmul_stage4.interface
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
-- using Mentor Graphics FPGA Advantage tools.
--
-- Visit "http://fpga.mty.itesm.mx" for more info.
--
-- 2003-2004. V1.0
--
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ENTITY FPmul_stage4 IS
PORT(
EXP_neg : IN std_logic;
EXP_out_round : IN std_logic_vector (7 DOWNTO 0);
EXP_pos : IN std_logic;
SIGN_out : IN std_logic;
SIG_out_round : IN std_logic_vector (27 DOWNTO 0);
clk : IN std_logic;
isINF_tab : IN std_logic;
isNaN : IN std_logic;
isZ_tab : IN std_logic;
FP_Z : OUT std_logic_vector (31 DOWNTO 0)
);
 
-- Declarations
 
END FPmul_stage4 ;
 
--
-- VHDL Architecture HAVOC.FPmul_stage4.struct
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
-- using Mentor Graphics FPGA Advantage tools.
--
-- Visit "http://fpga.mty.itesm.mx" for more info.
--
-- Copyright 2003-2004. V1.0
--
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ARCHITECTURE struct OF FPmul_stage4 IS
 
-- Architecture declarations
 
-- Internal signal declarations
SIGNAL EXP_out : std_logic_vector(7 DOWNTO 0);
SIGNAL FP : std_logic_vector(31 DOWNTO 0);
SIGNAL SIG_isZ : std_logic;
SIGNAL SIG_out : std_logic_vector(22 DOWNTO 0);
SIGNAL SIG_out_norm2 : std_logic_vector(27 DOWNTO 0);
SIGNAL isINF : std_logic;
SIGNAL isZ : std_logic;
 
 
-- Component Declarations
COMPONENT FPnormalize
GENERIC (
SIG_width : integer := 28
);
PORT (
SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
EXP_in : IN std_logic_vector (7 DOWNTO 0);
SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
EXP_out : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT PackFP
PORT (
SIGN : IN std_logic ;
EXP : IN std_logic_vector (7 DOWNTO 0);
SIG : IN std_logic_vector (22 DOWNTO 0);
isNaN : IN std_logic ;
isINF : IN std_logic ;
isZ : IN std_logic ;
FP : OUT std_logic_vector (31 DOWNTO 0)
);
END COMPONENT;
 
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : FPnormalize USE ENTITY work.FPnormalize;
FOR ALL : PackFP USE ENTITY work.PackFP;
-- pragma synthesis_on
 
 
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 1 trim
-- trim 1
SIG_out <= SIG_out_norm2(25 DOWNTO 3);
 
-- HDL Embedded Text Block 2 zero
-- zero 2
SIG_isZ <= '1' WHEN ((SIG_out_norm2(26 DOWNTO 3)=X"000000") OR
(EXP_neg='1' AND EXP_out(7)='1')) ELSE '0';
 
-- HDL Embedded Text Block 3 isINF_logic
-- isINF_logic 3
PROCESS(isZ,isINF_tab, EXP_pos, EXP_out)
BEGIN
IF isZ='0' THEN
IF isINF_tab='1' THEN
isINF <= '1';
ELSIF EXP_out=X"FF" THEN
isINF <='1';
ELSIF ((EXP_pos='1') AND (EXP_out(7)='0')) THEN
isINF <='1';
ELSE
isINF <= '0';
END IF;
ELSE
isINF <= '0';
END IF;
END PROCESS;
 
-- HDL Embedded Text Block 4 latch
-- latch 4
PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
FP_Z <= FP;
END IF;
END PROCESS;
 
 
-- ModuleWare code(v1.1) for instance 'I2' of 'or'
isZ <= SIG_isZ OR isZ_tab;
 
-- Instance port mappings.
I1 : FPnormalize
GENERIC MAP (
SIG_width => 28
)
PORT MAP (
SIG_in => SIG_out_round,
EXP_in => EXP_out_round,
SIG_out => SIG_out_norm2,
EXP_out => EXP_out
);
I3 : PackFP
PORT MAP (
SIGN => SIGN_out,
EXP => EXP_out,
SIG => SIG_out,
isNaN => isNaN,
isINF => isINF,
isZ => isZ,
FP => FP
);
 
END struct;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.