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URL https://opencores.org/ocsvn/i2c_to_wb/i2c_to_wb/trunk

Subversion Repositories i2c_to_wb

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Rev 4 → Rev 5

/i2c_to_wb/trunk/src/i2c_to_wb_fsm.v
39,39 → 39,39
input i2c_clk,
input i2c_clk_rise,
input i2c_clk_fall,
 
input i2c_r_w_bit,
input i2c_ack_out,
output i2c_ack_done,
output tip_addr_byte,
output tip_read_byte,
output tip_write_byte,
output tip_wr_ack,
output tip_rd_ack,
output tip_addr_ack,
output i2c_ack_done,
 
output tip_addr_byte,
output tip_read_byte,
output tip_write_byte,
output tip_wr_ack,
output tip_rd_ack,
output tip_addr_ack,
 
output [7:0] state_out,
output i2c_error,
input wb_clk_i,
input wb_rst_i
 
input wb_clk_i,
input wb_rst_i
);
 
// --------------------------------------------------------------------
// wires
wire xmt_byte_done;
 
wire tip_ack;
 
 
// --------------------------------------------------------------------
// start & stop & ack
 
wire start_detected = i2c_data_fall & i2c_clk;
wire stop_detected = i2c_data_rise & i2c_clk;
 
 
// --------------------------------------------------------------------
// state machine
 
86,7 → 86,7
 
reg [7:0] state;
reg [7:0] next_state;
 
always @(posedge wb_clk_i or posedge wb_rst_i)
if(wb_rst_i)
state <= STATE_IDLE;
98,18 → 98,18
STATE_IDLE: if( start_detected )
next_state = STATE_ADDR_BYTE;
else
next_state = STATE_IDLE;
next_state = STATE_IDLE;
 
STATE_ADDR_BYTE: if( xmt_byte_done )
next_state = STATE_ADDR_ACK;
else if( start_detected | stop_detected )
else if( stop_detected )
next_state = STATE_ERROR;
else
else
next_state = STATE_ADDR_BYTE;
 
STATE_ADDR_ACK: if(i2c_ack_out)
next_state = STATE_IDLE;
else
else
if( i2c_ack_done )
if( i2c_r_w_bit )
next_state = STATE_READ;
119,7 → 119,7
next_state = STATE_ERROR;
else
next_state = STATE_ADDR_ACK;
 
STATE_WRITE: if( xmt_byte_done )
next_state = STATE_WR_ACK;
else if( start_detected )
128,14 → 128,14
next_state = STATE_IDLE;
else
next_state = STATE_WRITE;
 
STATE_WR_ACK: if( i2c_ack_done )
next_state = STATE_WRITE;
next_state = STATE_WRITE;
else if( start_detected | stop_detected )
next_state = STATE_ERROR;
else
next_state = STATE_WR_ACK;
 
STATE_READ: if( xmt_byte_done )
next_state = STATE_RD_ACK;
else if( start_detected )
144,43 → 144,48
next_state = STATE_IDLE;
else
next_state = STATE_READ;
 
STATE_RD_ACK: if( i2c_ack_done )
if(i2c_data)
next_state = STATE_IDLE;
next_state = STATE_IDLE;
else
next_state = STATE_READ;
next_state = STATE_READ;
else if( start_detected | stop_detected )
next_state = STATE_ERROR;
else
next_state = STATE_RD_ACK;
 
STATE_ERROR: next_state = STATE_IDLE;
 
default: next_state = STATE_ERROR;
endcase
 
 
// --------------------------------------------------------------------
// bit counter
// bit counter
reg [3:0] bit_count;
assign xmt_byte_done = (bit_count == 4'h7) & i2c_clk_rise;
 
assign xmt_byte_done = (bit_count == 4'h7) & i2c_clk_rise;
assign tip_ack = (bit_count == 4'h8);
assign i2c_ack_done = tip_ack & i2c_clk_rise;
 
always @(posedge wb_clk_i)
if( wb_rst_i | i2c_ack_done | start_detected )
bit_count <= 4'hf;
else if( i2c_clk_fall )
bit_count <= bit_count + 1;
// --------------------------------------------------------------------
// outputs
 
 
// --------------------------------------------------------------------
// debug
wire i2c_start_error = (state == STATE_ADDR_BYTE) & start_detected;
 
 
// --------------------------------------------------------------------
// outputs
 
assign state_out = state;
 
assign tip_addr_byte = (state == STATE_ADDR_BYTE);
assign tip_addr_ack = (state == STATE_ADDR_ACK);
assign tip_read_byte = (state == STATE_READ);
188,9 → 193,8
assign tip_wr_ack = tip_addr_ack | (state == STATE_WR_ACK);
assign tip_rd_ack = (state == STATE_RD_ACK);
 
assign i2c_error = (state == STATE_ERROR);
assign i2c_error = (state == STATE_ERROR) | i2c_start_error;
 
endmodule
 
 
/i2c_to_wb/trunk/src/i2c_to_wb_top.v
34,7 → 34,7
#(
parameter DW = 32,
parameter AW = 8
)
)
(
input i2c_data_in,
input i2c_clk_in,
42,7 → 42,7
output i2c_clk_out,
output i2c_data_oe,
output i2c_clk_oe,
 
input [(DW-1):0] wb_data_i,
output [(DW-1):0] wb_data_o,
output [(AW-1):0] wb_addr_o,
53,79 → 53,79
input wb_ack_i,
input wb_err_i,
input wb_rty_i,
 
input wb_clk_i,
input wb_rst_i
input wb_rst_i
);
 
// --------------------------------------------------------------------
// wires
wire tip_addr_byte;
wire tip_read_byte;
wire tip_write_byte;
wire tip_addr_byte;
wire tip_read_byte;
wire tip_write_byte;
wire tip_wr_ack;
wire tip_rd_ack;
wire tip_addr_ack;
 
// wire i2c_ack_out = 1'b0;
wire i2c_ack_out;
wire i2c_ack_done;
 
wire [7:0] i2c_byte_out;
wire i2c_parallel_load;
 
 
// --------------------------------------------------------------------
// glitch filter
 
wire gf_i2c_data_in;
wire gf_i2c_data_in_rise;
wire gf_i2c_data_in_fall;
 
glitch_filter
i_gf_i2c_data_in(
.in(i2c_data_in),
.out(gf_i2c_data_in),
 
.rise(gf_i2c_data_in_rise),
.fall(gf_i2c_data_in_fall),
 
.clk(wb_clk_i),
.rst(wb_rst_i)
.rst(wb_rst_i)
);
 
wire gf_i2c_clk_in;
wire gf_i2c_clk_in_rise;
wire gf_i2c_clk_in_fall;
 
glitch_filter
i_gf_i2c_clk_in(
.in(i2c_clk_in),
.out(gf_i2c_clk_in),
 
.rise(gf_i2c_clk_in_rise),
.fall(gf_i2c_clk_in_fall),
 
.clk(wb_clk_i),
.rst(wb_rst_i)
.rst(wb_rst_i)
);
 
 
// --------------------------------------------------------------------
// i2c data shift register w/ parallel load
 
reg [8:0] i2c_data_in_r; // add throw away bit for serial_out
wire serial_out = i2c_data_in_r[8];
 
always @(posedge wb_clk_i)
if( i2c_parallel_load )
i2c_data_in_r[7:0] <= i2c_byte_out;
else if( (tip_write_byte & gf_i2c_clk_in_rise) | (tip_read_byte & gf_i2c_clk_in_fall) )
i2c_data_in_r <= {i2c_data_in_r[7:0], gf_i2c_data_in};
 
 
// --------------------------------------------------------------------
// main state machine
// main state machine
i2c_to_wb_fsm
i_i2c_to_wb_fsm
(
132,30 → 132,30
.i2c_data(gf_i2c_data_in),
.i2c_data_rise(gf_i2c_data_in_rise),
.i2c_data_fall(gf_i2c_data_in_fall),
 
.i2c_clk(gf_i2c_clk_in),
.i2c_clk_rise(gf_i2c_clk_in_rise),
.i2c_clk_fall(gf_i2c_clk_in_fall),
 
.i2c_r_w_bit(i2c_data_in_r[0]),
.i2c_ack_out(i2c_ack_out),
.i2c_ack_done(i2c_ack_done),
 
.tip_addr_byte(tip_addr_byte),
.tip_read_byte(tip_read_byte),
.tip_write_byte(tip_write_byte),
.tip_wr_ack(tip_wr_ack),
.tip_rd_ack(tip_rd_ack),
.tip_addr_ack(tip_addr_ack),
.tip_wr_ack(tip_wr_ack),
.tip_rd_ack(tip_rd_ack),
.tip_addr_ack(tip_addr_ack),
 
.state_out(),
.i2c_error(),
 
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i)
.wb_rst_i(wb_rst_i)
);
 
 
// --------------------------------------------------------------------
// i2c_to_wb_config
i2c_to_wb_config
164,25 → 164,25
.i2c_byte_in(i2c_data_in_r[7:0]),
.tip_addr_ack(tip_addr_ack),
.i2c_ack_out(i2c_ack_out),
 
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i)
);
 
 
// --------------------------------------------------------------------
// i2c_to_wb_if
i2c_to_wb_if #( .DW(DW), .AW(AW) )
i2c_to_wb_if #( .DW(DW), .AW(AW) )
i_i2c_to_wb_if(
.i2c_data(gf_i2c_data_in),
.i2c_ack_done(i2c_ack_done),
.i2c_ack_done(i2c_ack_done),
.i2c_byte_in(i2c_data_in_r[7:0]),
.i2c_byte_out(i2c_byte_out),
.i2c_parallel_load(i2c_parallel_load),
.tip_wr_ack(tip_wr_ack),
.tip_rd_ack(tip_rd_ack),
.tip_addr_ack(tip_addr_ack),
.tip_wr_ack(tip_wr_ack),
.tip_rd_ack(tip_rd_ack),
.tip_addr_ack(tip_addr_ack),
 
.wb_data_i(wb_data_i),
.wb_data_o(wb_data_o),
.wb_addr_o(wb_addr_o),
193,15 → 193,15
.wb_ack_i(wb_ack_i),
.wb_err_i(wb_err_i),
.wb_rty_i(wb_rty_i),
 
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i)
);
 
 
// --------------------------------------------------------------------
// i2c_data out sync
 
reg i2c_data_oe_r;
always @(posedge wb_clk_i)
if( wb_rst_i )
208,20 → 208,20
i2c_data_oe_r <= 1'b0;
else if( gf_i2c_clk_in_fall )
i2c_data_oe_r <= tip_read_byte | tip_wr_ack;
 
reg i2c_data_mux_select_r;
always @(posedge wb_clk_i)
if( gf_i2c_clk_in_fall )
i2c_data_mux_select_r <= tip_wr_ack;
 
 
// --------------------------------------------------------------------
// outputs
// outputs
 
assign i2c_data_out = i2c_data_mux_select_r ? i2c_ack_out : serial_out;
assign i2c_data_oe = i2c_data_oe_r;
assign i2c_clk_out = 1'b1;
assign i2c_clk_oe = 1'b0;
 
endmodule
 
/i2c_to_wb/trunk/sim/models/wb_slave_model.v
25,7 → 25,6
//// ////
//////////////////////////////////////////////////////////////////////
 
 
`timescale 1ns/10ps
 
 
159,4 → 158,4
assign rty_o = 1'b0;
 
endmodule
endmodule

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