URL
https://opencores.org/ocsvn/i8255/i8255/trunk
Subversion Repositories i8255
Compare Revisions
- This comparison shows the changes necessary to convert path
/i8255
- from Rev 2 to Rev 3
- ↔ Reverse comparison
Rev 2 → Rev 3
/i8255.v
341,7 → 341,7
//control register |
2'b11: begin //write - control |
if (data[7:7]==0) begin |
gracw=1; |
gracw<=1; |
end |
else begin |
//send mode to the all groups |
398,26 → 398,26
if(ncs==0) begin |
case (addr) |
2'b11: begin//read - control |
intdata=mode; |
iflag=0; |
oflag=0; |
extrai=1; |
intdata<=mode; |
iflag<=0; |
oflag<=0; |
extrai<=1; |
end |
2'b00: begin //read - porta |
iflag=1; |
gracw=3; |
sel=1; |
iflag<=1; |
gracw<=3; |
sel<=1; |
end |
2'b01: begin//read - portb |
iflag=1; |
grbcw=3; |
sel=1; |
iflag<=1; |
grbcw<=3; |
sel<=1; |
end |
2'b10: begin//read - portc |
iflag=1; |
gracw=5; |
grbcw=5; |
sel=3; |
iflag<=1; |
gracw<=5; |
grbcw<=5; |
sel<=3; |
end |
endcase |
end |
/tsti8255.v
70,7 → 70,6
pae<=0; |
pche<=0; |
wrtport<=0; |
pause<=0; |
ncs <= 1; |
nrd <= 1; |
nwr <= 1; |
113,65 → 112,65
writeret<=32; |
end |
3: begin |
newval=8'h0; |
nrd=1; |
nwr=1; |
step=4; |
newval<=8'h0; |
nrd<=1; |
nwr<=1; |
step<=4; |
end |
4: begin |
newval=8'b10100000; |
addr=2; |
nrd=1; |
nwr=0; |
step=5; |
newval<=8'b10100000; |
addr<=2; |
nrd<=1; |
nwr<=0; |
step<=5; |
end |
6: begin |
newval=8'b10010000; //a-output, c -input //#4 |
addr=3; |
oflag=1; |
pae=0; |
step=33; |
resetret=7; |
writeret=32; |
newval<=8'b10010000; //a-output, c -input //#4 |
addr<=3; |
oflag<=1; |
pae<=0; |
step<=33; |
resetret<=7; |
writeret<=32; |
end |
7: begin |
wrtport=8'b11010000; //#10 |
pae=1; |
wrtport<=8'b11010000; //#10 |
pae<=1; |
//pche=1; |
oflag=0; |
addr=0; |
nrd=0; |
nwr=1; |
step=32; |
resetret=8; |
oflag<=0; |
addr<=0; |
nrd<=0; |
nwr<=1; |
step<=32; |
resetret<=8; |
end |
8: begin |
newval=8'b10100000; |
newval<=8'b10100000; |
//pae=0; |
pche=1; |
oflag=1; |
addr=0; |
nrd=1; |
nwr=0; |
step=10; |
pche<=1; |
oflag<=1; |
addr<=0; |
nrd<=1; |
nwr<=0; |
step<=10; |
end |
9: begin |
pae=0; |
addr=0; |
nrd=0; |
nwr=1; |
step=10; |
pae<=0; |
addr<=0; |
nrd<=0; |
nwr<=1; |
step<=10; |
end |
32: begin |
oflag=0; |
nrd=1; |
nwr=1; |
step=resetret; |
32: begin //reset step |
oflag<=0; |
nrd<=1; |
nwr<=1; |
step<=resetret; |
end |
33: begin //write routine |
nwr=0; |
nrd=1; |
step=writeret; |
nwr<=0; |
nrd<=1; |
step<=writeret; |
end |
|
endcase |