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URL https://opencores.org/ocsvn/lwrisc/lwrisc/trunk

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Rev 15 → Rev 16

/trunk/BENCH/test1/seg7_decode.c
0,0 → 1,21
unsigned char byte2seg7(unsigned char my_byte)
{unsigned char seg;
switch (my_byte){
case 0: return 0xc0;//~8'b00111111;//b11111100;
case 1: return 0xf6;//~8'b00000110;//01100000;
case 2: return 0xa4;//~8'b01011011;//11011010;
case 3: return 0xb0;//~8'b01001111;//11010010;
case 4: return 0x99;//~8'b01100110;//1100110;
case 5: return 0x92;//~8'b01101101;//10110110;
case 6: return 0x82;//~8'b01111101;//10111110;
case 7: return 0xf8;//~8'b00000111;//11100000;
case 8: return 0x8f;//~8'b01111111;//11111110;
case 9: return 0x90;//~8'b01101111;//11110110;
case 10: return 0x88;//~8'b01110111;//11101110;
case 11: return 0x83;//~8'b01111100;//00111110;
case 12: return 0xa7;//~8'b01011000;//00011010;
case 13: return 0xa1;//~8'b01011110;//01111010;
case 14: return 0x86;//~8'b01111001;//10011110;
case 15: return 0x8e;//~8'b01110001;//10001110;
default : return 0xff;}
}
/trunk/BENCH/test1/sw_led.c
0,0 → 1,52
#device PIC16F54
 
#define PORT_DATA *(unsigned char*)0
#define IN_PORT_ADDR *(unsigned char*)1
#define OUT_PORT_ADDR *(unsigned char*)2
#define STATUS *(unsigned char*)3
 
#define PORT_ADDR_SEG 0
#define PORT_ADDR_LED 8
#define PORT_ADDR_SW 9
#define PORT_ADDR_KEY 10
#define PORT_ADDR_BEEP 11
 
void outport(unsigned char addr,unsigned char data)
{
OUT_PORT_ADDR = addr;
PORT_DATA = data;
}
 
unsigned char inport(unsigned char addr)
{
IN_PORT_ADDR = addr;
return PORT_DATA;
}
 
#define GetKey() inport(PORT_ADDR_KEY)
#define GetSwich() inport(PORT_ADDR_SW)
#define BeepSet(data) outport(PORT_ADDR_BEEP,data)
#define BeepON() outport(PORT_ADDR_BEEP,1)
#define BeepOFF() outport(PORT_ADDR_BEEP,0)
#define SetLed(data) outport(PORT_ADDR_LED,data)
 
#define Seg7Led(addr,data) outport(addr,data)
#define Seg7Led0(data) outport(0,data)
#define Seg7Led1(data) outport(1,data)
#define Seg7Led2(data) outport(2,data)
#define Seg7Led3(data) outport(3,data)
#define Seg7Led4(data) outport(4,data)
#define Seg7Led5(data) outport(5,data)
#define Seg7Led6(data) outport(6,data)
#define Seg7Led7(data) outport(7,data)
 
void main()
{
unsigned char i;
while(1){
i=GetSwich();
SetLed(i);
}
 
}
/trunk/CTOOL/hexdasm.exe Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/CTOOL/hexdasm.c
55,7 → 55,7
static volatile unsigned char WB_CTL @ 0x06;*/
static char reg_name[30];
char*find_reg(unsigned int t)
{
{/*
//puts(&ins[7]);
if(t==0)
{
75,11 → 75,13
strcpy(reg_name,"PCL");
return reg_name ;
}
else if(t-3==0)
else
*/ if(t-3==0)
{
strcpy(reg_name,"STATUS");
return reg_name ;
}
}/*
else if(t==0+4)
{
strcpy(reg_name,"FSR");
102,6 → 104,7
strcpy(reg_name,"PORTC");
return reg_name ;
}
*/
return NULL ;
}
 
171,7 → 174,7
if(ins[11-5]=='1')t+=32;//1<<5 ;
if(ins[11-6]=='1')t+=64;//1<<6 ;
if(ins[11-7]=='1')t+=128;//1<<7 ;
if(ins[11-8]=='1')t+=256;//1<<8 ;
// if(ins[11-8]=='1')t+=256;//1<<8 ;
return t ;
}
 
862,7 → 865,7
fprintf(fpi,"%4X : %4X;\n",Memory[i].nAddress,Memory[i].byData);
}
fprintf(fpi,"\END;\n");
fprintf(fpi,"\nEND;\n");
printf("\END;\n");
close(fpi);
/*output simulate verilog code */
953,9 → 956,9
// getchar();
strcpy(mif_fn,"rom_set.h");
// strcpy(mif_fn,"rom_set.h");
fpi=fopen(mif_fn,"w");
// fpi=fopen(mif_fn,"w");
for(i=0;i<nMemoryCount;i++)
{
if ((Memory[i].nAddress==2047)&&(Memory[i-1].nAddress!=2046))continue;
971,9 → 974,9
// fprintf(fpi,"`define ALT_MEM_WIDTHAD %d\n",addr_wdt);
// fprintf(fpi,"`define ALT_MEM_NUMWORDS %d\n",1<<addr_wdt);
// `define MIF_NAME %s\n\n","init_file.mif");
fprintf(fpi,"`define ROM_TYPE rom%dx12\n\n",1<<func1(max));
// fprintf(fpi,"`define ROM_TYPE rom%dx12\n\n",1<<func1(max));
close(fpi);
// close(fpi);
// getchar();
}
 
/trunk/RTL/device_box.v
0,0 → 1,472
`define HARD_CLOCK
 
 
`ifndef HARD_CLOCK
`define SEG7_CLOCK_MODEL
`endif
 
 
module led_interface (
input clk, rst, wr, rd,
input [7:0] din,
output reg [7:0] dout,
output [7:0]led
);
reg [7:0] led_data;
assign led = led_data;
 
always @ (posedge clk)
if (rst)
led_data = 0;
else if (wr)
led_data=din;
 
always@ (posedge clk)
if (rd)
dout=led_data;
else dout = 0;
endmodule
 
 
module clock_seg7led_interface(
input clk,rst,
input [7:0]din,
output reg [7:0]dout,
input wr,rd ,
input [2:0]wr_addr,input [2:0]rd_addr,
output reg [7:0] seg7_sel,seg7_data
);
reg [7:0]buff[0:3];
always @ (posedge clk)
if (wr)
buff[wr_addr] = din;
 
always @(posedge clk)
if (rd)
dout = buff[rd_addr] ;
else dout=0;
 
/*the main counter*/
reg [31:0] seg7_cntr;
always @(posedge clk)seg7_cntr=seg7_cntr+1;
wire [2:0] sel =seg7_cntr[17:15] ;
wire flash_bit = seg7_cntr[21];
always @(posedge clk)
case (sel[2:0])
0:seg7_data=(buff[3][0]&flash_bit)?'hff:seg(buff[0][3:0]);
1:seg7_data=(buff[3][1]&flash_bit)?'hff:seg(buff[0][3:0]);
2:seg7_data=(buff[3][2]&flash_bit)?'hff:~8'b01000000;
3:seg7_data=(buff[3][3]&flash_bit)?'hff:seg(buff[1][3:0]);
4:seg7_data=(buff[3][4]&flash_bit)?'hff:seg(buff[1][3:0]);
5:seg7_data=(buff[3][5]&flash_bit)?'hff:~8'b01000000;
6:seg7_data=(buff[3][6]&flash_bit)?'hff:seg(buff[2][3:0]);
7:seg7_data=(buff[3][7]&flash_bit)?'hff:seg(buff[2][3:0]);
endcase
 
always @(posedge clk) seg7_sel=~(1<<sel);
function [7:0] seg;
input [3:0] data;
begin
case(data)
0: seg = ~8'b00111111;//b11111100;
1: seg = ~8'b00000110;//01100000;
2: seg = ~8'b01011011;//11011010;
3: seg = ~8'b01001111;//11010010;
4: seg = ~8'b01100110;//1100110;
5: seg = ~8'b01101101;//10110110;
6: seg = ~8'b01111101;//10111110;
7: seg = ~8'b00000111;//11100000;
8: seg = ~8'b01111111;//11111110;
9: seg = ~8'b01101111;//11110110;
10: seg = ~8'b01110111;//11101110;
11: seg = ~8'b01111100;//00111110;
12: seg = ~8'b01011000;//00011010;
13: seg = ~8'b01011110;//01111010;
14: seg = ~8'b01111001;//10011110;
15: seg = ~8'b01110001;//10001110;
endcase
end
endfunction
endmodule
 
 
module seg7led_interface(
input clk,rst,
input [7:0]din,
output reg [7:0]dout,
input wr,rd ,
input [2:0]wr_addr,
input [2:0]rd_addr,
output reg [7:0] seg7_sel,
output reg [7:0] seg7_data
);
reg [7:0]buff[0:7];
 
always @ (posedge clk)if (wr)buff[wr_addr] = din;
 
always @(posedge clk)if (rd)dout = buff[rd_addr] ;else dout=0;
 
reg [22:0] cntr ;
always @ (posedge clk)
cntr = cntr +1;
reg [2:0]sel ;
always @ (posedge clk)
sel= cntr[22:19];
 
always @(posedge clk)
case (sel)
0:seg7_data=buff[0];
1:seg7_data=buff[1];
2:seg7_data=buff[2];
3:seg7_data=buff[3];
4:seg7_data=buff[4];
5:seg7_data=buff[5];
6:seg7_data=buff[6];
7:seg7_data=buff[7];
endcase
always @(posedge clk)
seg7_sel = 1<<sel;
 
endmodule
 
 
module sw_interface(
input clk,rst,rd,
input [7:0]sw,
output reg[7:0] dout
);
reg [7:0]sw_r;
always @ (posedge clk)sw_r = sw;
always @ (posedge clk)if (rd)dout=sw_r;else dout =0;
endmodule
 
module key_interface(
input clk,rst,rd,
input [3:0]key,
output reg [7:0]dout
);
reg [3:0]key_r;
always @ (posedge clk)
key_r=key;
 
wire [3:0]w_key;
always @(posedge clk)
begin
dout[7:4]=0;
if (rd)dout[3:0] = w_key;else dout[3:0]=0;
end
 
`define KEY_FSM
`ifdef KEY_FSM
key_fsm ukey0(.clk(clk),.rst(rst),.key_i(key_r[0]),.key_o(w_key[0]),.rd(rd));
key_fsm ukey1(.clk(clk),.rst(rst),.key_i(key_r[1]),.key_o(w_key[1]),.rd(rd));
key_fsm ukey2(.clk(clk),.rst(rst),.key_i(key_r[2]),.key_o(w_key[2]),.rd(rd));
key_fsm ukey3(.clk(clk),.rst(rst),.key_i(key_r[3]),.key_o(w_key[3]),.rd(rd));
`else
assign w_key = key_r;
`endif
endmodule
 
module beep_interface(
input clk,rst,rd,wr,
output reg [7:0]dout ,
input [7:0]din,
output beep
);
reg beep_en;
always @ (posedge clk)
if (rst)beep_en=0;
else if (wr)
beep_en=din[0];
always @(posedge clk)
if (rd)
dout ={7'b0, beep_en};
else dout=0;
BELL uu(
.sys_clk(clk),
.beep(beep),
.beep_en(beep_en)
);
endmodule
`define ADDR_LED 8
`define ADDR_SEG 0
`define ADDR_SW 9
`define ADDR_KEY 10
`define ADDR_BEEP 11
`define ADDR_SECGEN 12
module devices_box(
input clk,rst,wr,rd,
input [7:0]din,
input [7:0]sw ,
input [3:0] key,
input [7:0]wr_addr,
input [7:0]rd_addr,
output [7:0]dout ,
output [7:0]seg7_sel,
output [7:0]seg7_data,
output [7:0]led
);
 
wire [7:0]dout_key;
wire sel_key_wr = wr_addr==`ADDR_KEY;
wire sel_key_rd = rd_addr==`ADDR_KEY;
key_interface u1(
.clk(clk),
.rst(rst),
.rd(rd&sel_key_rd),
.key(key),
.dout(dout_key)
);
 
wire [7:0]dout_sw;
wire sel_sw_wr = wr_addr==`ADDR_SW;
wire sel_sw_rd = rd_addr==`ADDR_SW;
sw_interface u2(
.clk(clk),
.rst(rst),
.rd(rd&sel_sw_rd),
.sw(sw),
.dout(dout_sw)
);
 
wire [7:0]dout_seg7led;
wire sel_seg7_wr = (wr_addr&(~7))== 0;
wire sel_seg7_rd = (rd_addr&(~7))== 0;
 
`ifdef HARD_CLOCK
hard_clock
`else
`ifdef SEG7_CLOCK_MODEL
clock_seg7led_interface
`else
seg7led_interface
`endif
`endif
 
clock(
.clk(clk),
.rst(rst),
.din(din ),
.dout(dout_seg7led),
.wr(wr&sel_seg7_wr ),
.rd(rd&sel_seg7_rd ) ,
.rd_addr(rd_addr[2:0]),
.wr_addr(wr_addr[2:0]),
.seg7_sel(seg7_sel),
.seg7_data(seg7_data)
);
 
 
wire [7:0] dout_led;
wire sel_led_wr = rd_addr==`ADDR_LED;
wire sel_led_rd = wr_addr==`ADDR_LED;
led_interface u4(
.clk(clk),
.rst(rst),
.wr(wr&sel_led_wr),
.rd(rd&sel_led_rd),
.din(din),
.dout(dout_led),
.led(led)
);
 
wire [7:0]dout_beep;
 
wire sel_beep_rd = rd_addr==`ADDR_BEEP;
wire sel_beep_wr = wr_addr==`ADDR_BEEP;
 
beep_interface u5(
.clk(clk),
.rst(rst),
.rd(rd&sel_beep_rd),
.wr(wr&sel_beep_wr),
.dout(dout_beep) ,
.din(din),
.beep(beep)
);
 
wire [7:0] dout_secgen ;
wire sel_secgen_rd = rd_addr==`ADDR_SECGEN;
wire sel_secgen_wr = wr_addr==`ADDR_SECGEN;
 
second_gen secgen(
.clk(clk),
.rst(rst),
.rd(rd&sel_secgen_rd),
.din(din),
.wr(wr&sel_secgen_wr),
.dout(dout_secgen)
);
 
assign dout = dout_key | dout_sw |dout_seg7led | dout_led | dout_beep | dout_secgen;
 
endmodule
 
`define CLK_HZ 25000000
 
module second_gen(
input clk,rst,
input rd,
input [7:0]din,
input wr,
output reg [7:0]dout
);
reg [31:0] cntr;
wire time_out = cntr==(`CLK_HZ-1);
 
wire clr = wr&(din[0]==0);
 
always @(posedge clk)
if (rst)cntr=0;
else
if (time_out)
cntr=0;
else
cntr=cntr+1;
reg int_req;
always @ (posedge clk)
if (clr)
int_req=0;
else
int_req = int_req|time_out ;
 
always @ (posedge clk)
if(rd)
dout={7'b0,int_req};
else dout=0;
endmodule
 
module hard_clock(
input clk,
input rst,
input wr,
input rd,
input [2:0]rd_addr,
input [2:0]wr_addr,
output reg [7:0] seg7_data,
output reg [7:0] seg7_sel,
input [7:0]din,
output reg[7:0]dout
);
`define CTL_ADDR 3
`define HOUR_ADDR 2
`define MIN_ADDR 1
`define SEC_ADDR 0
reg [7:0]hour;
reg [7:0]min;
reg [7:0]sec;
reg [7:0]ctl;
always @ (posedge clk)if (rst)hour=0; else if (wr&wr_addr==`HOUR_ADDR)hour=din;
always @ (posedge clk)if (rst)min=0; else if (wr&wr_addr==`MIN_ADDR)min=din;
always @ (posedge clk)if (rst)sec=0; else if (wr&wr_addr==`SEC_ADDR)sec=din;
always @(posedge clk) if (rd)
case (rd_addr[2:0])
`SEC_ADDR:dout = sec;
`MIN_ADDR :dout = min;
`HOUR_ADDR:dout = hour;
`CTL_ADDR:dout = ctl;
endcase else dout=0;
/*the main counter*/
reg [31:0] seg7_cntr;
always @(posedge clk)seg7_cntr=seg7_cntr+1;
wire [2:0] sel =seg7_cntr[17:15] ;
wire flash_bit = seg7_cntr[23];
always @(posedge clk)
case (sel[2:0])
0:seg7_data=(ctl[0]&flash_bit)?'hff:seg(sec[3:0]);
1:seg7_data=(ctl[1]&flash_bit)?'hff:seg(sec[7:4]);
2:seg7_data=(ctl[2]&flash_bit)?'hff:~8'b01000000;
3:seg7_data=(ctl[3]&flash_bit)?'hff:seg(min[3:0]);
4:seg7_data=(ctl[4]&flash_bit)?'hff:seg(min[7:4]);
5:seg7_data=(ctl[5]&flash_bit)?'hff:~8'b01000000;
6:seg7_data=(ctl[6]&flash_bit)?'hff:seg(hour[3:0]);
7:seg7_data=(ctl[7]&flash_bit)?'hff:seg(hour[7:4]);
endcase
 
always @(posedge clk) seg7_sel=~(1<<sel);
function [7:0] seg;
input [3:0] data;
begin
case(data)
0: seg = ~8'b00111111;//b11111100;
1: seg = ~8'b00000110;//01100000;
2: seg = ~8'b01011011;//11011010;
3: seg = ~8'b01001111;//11010010;
4: seg = ~8'b01100110;//1100110;
5: seg = ~8'b01101101;//10110110;
6: seg = ~8'b01111101;//10111110;
7: seg = ~8'b00000111;//11100000;
8: seg = ~8'b01111111;//11111110;
9: seg = ~8'b01101111;//11110110;
10: seg = ~8'b01110111;//11101110;
11: seg = ~8'b01111100;//00111110;
12: seg = ~8'b01011000;//00011010;
13: seg = ~8'b01011110;//01111010;
14: seg = ~8'b01111001;//10011110;
15: seg = ~8'b01110001;//10001110;
endcase
end
endfunction
endmodule
 
 
`define KEY_ACTIVE_LEVEL 1
`define TIME_OUT_VALUE 25000000/2
 
module key_fsm(
input clk,rst,
input key_i,
output reg key_o,
input rd
);
reg [3:0]curr_state,next_state;
reg [31:0] cntr ;
always @ (posedge clk)
if (rst)cntr =0;
else if (curr_state==1)
cntr=cntr+1;
else cntr=0;
always @ (posedge clk)
if (rst)curr_state=0;
else
curr_state = next_state;
always @*
case (curr_state)
0:if (key_i==`KEY_ACTIVE_LEVEL&rd)
//read a active key value ,then we need delay for a period
next_state = 1;else next_state = 0;
1:if(cntr==`TIME_OUT_VALUE)
next_state = 0;else next_state = 1;
endcase
always @*
key_o=key_i&(~curr_state);
endmodule
/trunk/RTL/risc_core.v
1,25 → 1,14
/******************************************************************
* *
* Author: Liwei *
* *
* This file is part of the "ClaiRISC" project, *
* The folder in CVS is named as "lwrisc" *
* Downloaded from: *
* http://www.opencores.org/pdownloads.cgi/list/lwrisc *
* *
* If you encountered any problem, please contact me via *
* Email:mcupro@opencores.org or mcupro@163.com *
* *
******************************************************************/
 
`include "clairisc_def.h"
module ClaiRISC_core (
input clk,
input rst ,
input [7:0] in0,
input [7:0] in1,
output [7:0] out0,
output [7:0] out1
input rst,
output [7:0]dvc_wr_addr,
output [7:0]dvc_rd_addr,
output [7:0]data_mem2dvc,
input [7:0]data_dvc2mem,
output dvc_wr ,
output dvc_rd
);
supply0 GND;
35,8 → 24,8
reg w_reg_muxb_r;
reg w_skip;
reg w_w_wr;
reg w_w_wr_r;
wire w_z;
reg w_w_wr_r;
wire w_z;
reg w_z_wr;
reg w_z_wr_r;
reg [7:0] w_alu_in_a;
43,7 → 32,7
reg [7:0] w_alu_in_b;
reg [4:0] w_alu_op;
reg [4:0] w_alu_op_r;
reg [7:0] w_alu_res;
reg [7:0] w_alu_res;
wire [1:0] w_bank;
reg [7:0] w_bd_r;
reg [1:0] w_brc_ctl;
54,7 → 43,7
reg [10:0] w_pc;
reg [2:0] w_pc_gen_ctl;
reg [10:0] w_pc_nxt;
wire [6:0] w_rd_addr;
wire [4:0] w_rd_addr;
wire [7:0] w_status;
reg [1:0] w_stk_op;
wire [10:0] w_stk_pc;
61,12 → 50,20
reg[4:0] w_wbadd_r;
wire [4:0] w_wd_addr;
reg [7:0] w_wreg;
wire [6:0] w_wr_addr;
wire [4:0] w_wr_addr;
 
always @(posedge clk)
w_pc<=w_pc_nxt;
reg [10:0] stack1, stack2, stack3, stack4;
reg [10:0] stack1, stack2,stack3, stack4;
initial begin
stack1=0;
stack2=0;
stack3=0;
stack4=0;
end
assign w_stk_pc = stack1;
 
always @(posedge clk)
73,27 → 70,26
begin
case (w_stk_op)
`STK_PSH :// PUSH stack
begin
begin
stack4 <= stack3;
stack3 <= stack2;
stack3 <= stack2;
stack2 <= stack1;
stack1 <= w_pc;
stack1 <= w_pc+1;
end
`STK_POP :// POP stack
begin
stack1 <= stack2;
stack2 <= stack3;
stack3 <= stack4;
end
stack1 <= stack2;
stack2 <= stack3;
stack3 <= stack4;
end
// default ://do nothing
endcase
end
assign w_rd_addr ={ w_bank[1:0],w_wd_addr[4:0]};
assign w_rd_addr =w_wd_addr[4:0];
 
wb_mem_man mem_man
(
.bank(w_bank),
mem_man mem_man
(
.c_wr(w_c_wr_r),
.ci(w_c_2mem),
.clk(clk),
100,54 → 96,56
.co(w_c_2alu),
.din(w_alu_res),
.dout(w_file_o),
.rd_addr(w_rd_addr),
.rd_addr(w_rd_addr[4:0]),
.rst(rst),
.status(w_status),
.wr_addr(w_wr_addr),
.wr_addr(w_wr_addr[4:0]),
.wr_en(w_mem_wr_r),
.z_wr(w_z_wr_r),
.zi(w_z),
.in0(in0),
.in1(in1),
.out0(out0),
.out1(out1)
.zi(w_z),
.dvc_wr_addr(dvc_wr_addr),
.dvc_rd_addr(dvc_rd_addr),
.data_mem2dvc(data_mem2dvc),
.data_dvc2mem(data_dvc2mem),
.dvc_wr(dvc_wr),
.dvc_rd(dvc_rd)
);
 
always @(posedge clk)
if (w_skip==1)
always @(posedge clk)
if (w_skip)
w_alu_op_r<=0;
else
w_alu_op_r<=w_alu_op;
 
always@(posedge clk)
if (w_skip==1) w_br_ctl_r<=0;
if (w_skip) w_br_ctl_r<=0;
else w_br_ctl_r<=w_brc_ctl;
 
always@(posedge clk)
if (w_skip==1) w_z_wr_r<=0;
if (w_skip) w_z_wr_r<=0;
else w_z_wr_r<=w_z_wr;
 
always @ (posedge clk)
if (w_skip==1)
if (w_skip)
w_c_wr_r<=0;
else
w_c_wr_r<=w_c_wr;
 
always @(posedge clk)
if(w_skip==1)
if(w_skip)
w_mem_wr_r<=0;
else
else
w_mem_wr_r<=w_mem_wr;
always @(posedge clk)
if (w_w_wr_r==1)
if (w_w_wr_r)
w_wreg<=w_alu_res;
always @ (posedge clk)
w_bd_r<=1<<w_ins[7:5];
 
always @(posedge clk)
w_w_wr_r <=w_w_wr ;
always @(posedge clk)
w_w_wr_r <=w_w_wr ;
 
always @(posedge clk)
w_ek_r<=w_ins[8:0];
156,10 → 154,9
 
always@(posedge clk)
w_wbadd_r<=w_wd_addr;
 
assign w_wr_addr = {w_bank[1:0],w_wbadd_r[4:0]};
 
 
assign w_wr_addr = w_wbadd_r[4:0];
reg addercout;
always @(*) begin
case (w_alu_op_r) // synsys parallel_case
218,14 → 215,13
//then skip the next instruction
default w_skip = 0;
endcase
 
 
pram program_rom
com_prom program_rom
(
.clk(clk),
.dout(w_ins),
.rd_addr(w_pc_nxt)
);
);
 
always @ (*)
if (rst)
239,8 → 235,8
begin
case(w_pc_gen_ctl)
`PC_GOTO,
`PC_CALL: w_pc_nxt= {w_status[7:6],w_ins[8:0]};
`PC_RET: w_pc_nxt= w_stk_pc;
`PC_CALL: w_pc_nxt= w_ins[7:0];//{w_status[7:6],1'b0,w_ins[7:0]};
`PC_RET : w_pc_nxt= w_stk_pc;
default
w_pc_nxt= w_pc+1;
endcase
247,7 → 243,7
end
 
 
always @(*) begin
always @(*) begin
casex (w_ins)
 
12'b0000_001X_XXXX: //Checked 2008_11_22
822,7 → 818,7
//REPLACE ID = RETLW
//REPLACE ID = RETLW
begin
w_pc_gen_ctl = `PC_NEXT;
w_pc_gen_ctl = `PC_RET ;
w_stk_op = `STK_POP;
w_muxa_ctl = `MUXA_IGN;
w_muxb_ctl = `MUXB_EK; //check 2008_11_22
946,6 → 942,5
w_brc_ctl = `BG_NOP;
end //end of NOP ;
endcase
end
 
end
endmodule
/trunk/RTL/mem_man.v
1,74 → 1,70
/******************************************************************
* *
* Author: Liwei *
* *
* This file is part of the "ClaiRISC" project, *
* The folder in CVS is named as "lwrisc" *
* Downloaded from: *
* http://www.opencores.org/pdownloads.cgi/list/lwrisc *
* *
* If you encountered any problem, please contact me via *
* Email:mcupro@opencores.org or mcupro@163.com *
* *
******************************************************************/
 
`include "clairisc_def.h"
`define ADDR_FSR 4
`define ADDR_STATUS 3
`define ADDR_IN0 5
`define ADDR_IN1 1
`define ADDR_OUT0 6
`define ADDR_OUT1 7
`define ADDR_DVC_DATA 0
`define ADDR_DVC_WR_ADDR 2
`define ADDR_DVC_RD_ADDR 1
 
module wb_mem_man(
/*
#define PORT_DATA *(unsigned char*)0
#define IN_PORT_ADDR *(unsigned char*)1
#define OUT_PORT_ADDR *(unsigned char*)2
#define STATUS *(unsigned char*)3
*/
 
module mem_man(
input wr_en,
input clk,
input rst,
input rst,
input ci,
input zi,
input z_wr,
input c_wr,
output reg [7:0] dout,
output reg [7:0] dout,
output co,
output [1:0] bank,
input [7:0] din ,
output reg [7:0]status ,
 
input [7:0] rd_addr, //[6:0]Should be also OK,For there is only 128byte RAM
input [7:0] wr_addr , //[6:0]Should be also OK,For there is only 128byte RAM
input [4:0] rd_addr,
input [4:0] wr_addr ,
output reg [7:0]dvc_wr_addr,
output reg [7:0]dvc_rd_addr,
output reg [7:0]data_mem2dvc,
input [7:0]data_dvc2mem,
output reg dvc_wr ,
output /*reg */dvc_rd
);
 
input [7:0] in0,
input [7:0] in1,
output reg [7:0] out0,
output reg [7:0] out1
);
reg wr_en_r;
reg [7:0] din_r, wr_addr_r;
reg [7:0] rd_addr_r;
reg [7:0] din_r;
reg [4:0] wr_addr_r;
reg [4:0] rd_addr_r;
 
always @(posedge clk)
begin //used to bypass the data
//which wrote anf then be read in the followwing period
begin
wr_addr_r<=wr_addr;
rd_addr_r<=rd_addr;
wr_en_r<=wr_en;
din_r<=din;
end
 
end
wire [7:0] ram_q ;
wire [7:0] alt_ram_q;
 
`ifdef SIM
 
// `ifdef SIM
sim_reg_file i_reg_file(
.data(din),
.wren(wr_en),
.wraddress(wr_addr),
.rdaddress(rd_addr),
.wraddress(wr_addr[4:0]),
.rdaddress(rd_addr[4:0]),
.clock(clk),
.q(alt_ram_q));
`else
/* `else
ram128x8 i_reg_file(
.data(din),
.wren(wr_en),
76,11 → 72,11
.rdaddress(rd_addr),
.clock(clk),
.q(alt_ram_q)
);
);
`endif
*/
assign ram_q =/* ((wr_addr_r==rd_addr_r)&&(wr_en_r))?din_r:*/alt_ram_q;
 
assign ram_q = ((wr_addr_r==rd_addr_r)&&(wr_en_r))?din_r:alt_ram_q;
 
/*status register*/
wire write_status = wr_addr[4:0] ==`ADDR_STATUS && wr_en;
always@(posedge clk)
91,62 → 87,34
else
begin
if (c_wr)status[0]<=ci;
if (z_wr)status[2]<=zi;
if (z_wr)status[2]<=zi;
end
end
 
end
assign co = status[0];
 
`ifdef SIM
wire write_disp = wr_addr == 'h1f && wr_en;
always@(posedge clk)
`ifdef SIM
always@(*)
begin
if (write_disp)
$display("hex=>%x< char=>%c<",din,din);
if (wr_en)
$display("hex=>%x< char=>%x<",wr_addr[4:0],din[7:0]);
end
`endif
 
/*fsr register*/
reg [7:0] fsr;
assign bank = fsr[6:5];
wire write_fsr = wr_addr[4:0] == `ADDR_FSR &&wr_en ;
always@(posedge clk)
begin
if (rst)fsr<=0;
else if(write_fsr) fsr<=din[7:0];
end
 
/*latch the input data*/
reg [7:0] reg_in1,reg_in0;
always@(posedge clk) reg_in0<=in0;
always@(posedge clk) reg_in1<=in1;
 
/*data output latch */
wire write_out0 = wr_addr[4:0] == `ADDR_OUT0 &&wr_en ;
always@(posedge clk)
begin
if (rst)out0<=0;
else if(write_out0)out0<=din[7:0];
end
 
/*data output latch */
wire write_out1 = wr_addr[4:0] == `ADDR_OUT1 &&wr_en ;
always@(posedge clk)
begin
if (rst)out1<=0;
else if(write_out1)out1<=din[7:0];
end
 
/*data bus output select logic*/
always@(*)//select status,fsr,wb_data,ram,wb_din
case(rd_addr_r[4:0])
`ADDR_FSR:dout = fsr;
`ADDR_STATUS:dout = status;
`ADDR_IN0:dout = reg_in0;
`ADDR_IN1:dout = reg_in1;
`endif
always@(*)
case(rd_addr_r[4:0])
`ADDR_STATUS:dout = status;
`ADDR_DVC_DATA :dout = data_dvc2mem ;
default dout = ram_q ;
endcase
endcase
always @ (posedge clk) if ((wr_addr[4:0]==`ADDR_DVC_WR_ADDR)&&(1==wr_en))dvc_wr_addr <=din;
always @ (posedge clk) if ((wr_addr[4:0]==`ADDR_DVC_RD_ADDR)&&(1==wr_en)) dvc_rd_addr <=din;
always @ (posedge clk) if ((wr_addr[4:0]==`ADDR_DVC_DATA )&&(1==wr_en)) data_mem2dvc <=din;
always @ (*) dvc_wr <=wr_en_r&(wr_addr==0);
assign dvc_rd = 1'b1 ;
endmodule
 
 

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