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URL https://opencores.org/ocsvn/lwrisc/lwrisc/trunk

Subversion Repositories lwrisc

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Rev 3 → Rev 4

/trunk/utilities.v
0,0 → 1,107
 
`include "clairisc_def.h"
 
module ins2wb_addr(
input [11:0] ins,
output [4:0] wb_addr //wirte back addr
);
assign wb_addr = ins[4:0];
endmodule
 
module mem_addr(
input [1:0] bank,
input [4:0]addr,
output [6:0] file_addr
);
assign file_addr = {bank[1:0],addr[4:0]};
endmodule
 
 
module ins2bd(
input [11:0] ins,
output reg [7:0] bd
);
always @ (*)
case (ins[8:6])
0:bd=1<<0;
1:bd=1<<1;
2:bd=1<<2;
3:bd=1<<3;
4:bd=1<<4;
5:bd=1<<5;
6:bd=1<<6;
7:bd=1<<7;
endcase
endmodule
 
module alu_muxa(
input ctl,
output reg [7:0]alu_a,
input [7:0]w,
input [7:0]bd
);
always@(*)
if (ctl==`MUXA_W)
alu_a=w;
else
alu_a=bd;
endmodule
 
module alu_muxb(
input ctl,
output reg [7:0] alu_b,
input [8:0] k,
input [7:0] f
);
always@(*)
if (ctl==`MUXB_EK)
alu_b=k[7:0];
else alu_b=f;
endmodule
 
 
module pc_gen(
input [10:0]pc_i,
output reg [10:0] pc_o,
input [11:0] ins,
input [8:0] ek,
input [10:0] stack_pc,
input [2:0]ctl,
input brc,
input rst,
input [7:0]status
);
always @ (*)
if (rst)
pc_o ='h1ff; //THE RST ENTRY
else
if (brc)
begin
pc_o = pc_i+1;
end
else
begin
case(ctl)
// `PC_NOP :pc_o = pc_i+1;
// `PC_BRC : if(brc)pc_o = {status[7:6],ek[8:0]}; //jmp_addr means K
`PC_GOTO,
`PC_CALL: pc_o = {status[7:6],ins[8:0]};
`PC_RET: pc_o = stack_pc;
default
pc_o = pc_i+1;
endcase
end
endmodule
 
 
module bg(
input z ,
input [1:0]ctl,
output reg branch);
always @(*)
case (ctl)
`BG_ZERO :branch = ~z; //if the ALU result is 0 then the next instrction will be discarded
`BG_NZERO :branch = z; //if the ALU result is not zero ,then skip the next instruction
default branch = 0;
endcase
endmodule
/trunk/reg_file.v
0,0 → 1,304
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "12"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "12"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "12"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "12"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "24576"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "init_rom.mif"
// Retrieval info: PRIVATE: UseLCs NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "12"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: INIT_FILE STRING "init_rom.mif"
// Retrieval info: CONSTANT: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: USED_PORT: data 0 0 12 0 INPUT NODEFVAL data[11..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL q[11..0]
// Retrieval info: USED_PORT: wraddress 0 0 11 0 INPUT NODEFVAL wraddress[10..0]
// Retrieval info: USED_PORT: rdaddress 0 0 11 0 INPUT NODEFVAL rdaddress[10..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: CONNECT: @data_a 0 0 12 0 data 0 0 12 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_b 0 0 12 0
// Retrieval info: CONNECT: @address_a 0 0 11 0 wraddress 0 0 11 0
// Retrieval info: CONNECT: @address_b 0 0 11 0 rdaddress 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_wave*.jpg FALSE
 
 
 
 
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
 
// ============================================================
// File Name: reg_file.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 157 12/07/2004 SJ Full Version
// ************************************************************
 
 
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module reg_file (
data,
wren,
wraddress,
rdaddress,
clock,
q);
 
input [7:0] data;
input wren;
input [6:0] wraddress;
input [6:0] rdaddress;
input clock;
output [7:0] q;
 
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
 
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (clock),
.address_a (wraddress),
.address_b (rdaddress),
.data_a (data),
.q_b (sub_wire0)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.data_b (),
.q_a (),
.rden_b (),
.wren_b ()
// synopsys translate_on
);
defparam
altsyncram_component.intended_device_family = "Cyclone",
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.width_a = 8,
altsyncram_component.widthad_a = 7,
altsyncram_component.numwords_a = 128,
altsyncram_component.width_b = 8,
altsyncram_component.widthad_b = 7,
altsyncram_component.numwords_b = 128,
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.width_byteena_a = 1,
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.indata_aclr_a = "NONE",
altsyncram_component.wrcontrol_aclr_a = "NONE",
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE";
 
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "1024"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: UseLCs NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "7"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "128"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: USED_PORT: wraddress 0 0 7 0 INPUT NODEFVAL wraddress[6..0]
// Retrieval info: USED_PORT: rdaddress 0 0 7 0 INPUT NODEFVAL rdaddress[6..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: CONNECT: @address_a 0 0 7 0 wraddress 0 0 7 0
// Retrieval info: CONNECT: @address_b 0 0 7 0 rdaddress 0 0 7 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL reg_file.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL reg_file.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL reg_file.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL reg_file.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL reg_file_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL reg_file_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL reg_file_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL reg_file_wave*.jpg FALSE
/trunk/test.v
0,0 → 1,38
 
`timescale 10ns / 10ns
 
module test;
reg clk;
reg rst;
initial begin
#10 clk = 0;
#10 rst = 0;
#10 rst = 1;
#10 rst = 0;
end
always #5 clk=~clk ;
ClaiRISC_core I_ClaiRISC_core
(
.clk(clk),
.pdata_we(0),
.rst(rst)
 
/*
.exp_din,
.pdata_in,
.pdata_wraddr,
.exp_wren,
.exp_dout,
.exp_rd_addr,
.exp_wr_addr
*/
 
) ;
 
endmodule
/trunk/alt_ram.v
0,0 → 1,107
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
 
// ============================================================
// File Name: alt_ram.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 157 12/07/2004 SJ Full Version
// ************************************************************
 
 
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_ram (
data,
wren,
wraddress,
rdaddress,
clock,
q);
 
input [11:0] data;
input wren;
input [10:0] wraddress;
input [10:0] rdaddress;
input clock;
output [11:0] q;
 
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
 
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (clock),
.address_a (wraddress),
.address_b (rdaddress),
.data_a (data),
.q_b (sub_wire0)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.data_b (),
.q_a (),
.rden_b (),
.wren_b ()
// synopsys translate_on
);
defparam
altsyncram_component.intended_device_family = "Cyclone",
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.width_a = 12,
altsyncram_component.widthad_a = 11,
altsyncram_component.numwords_a = 2048,
altsyncram_component.width_b = 12,
altsyncram_component.widthad_b = 11,
altsyncram_component.numwords_b = 2048,
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.width_byteena_a = 1,
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.indata_aclr_a = "NONE",
altsyncram_component.wrcontrol_aclr_a = "NONE",
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.init_file = "init_rom.mif",
altsyncram_component.init_file_layout = "PORT_B";
 
 
endmodule
/trunk/alu.v
0,0 → 1,41
`include "clairisc_def.h"
 
module alu(op,a,b,y,cin,cout,zout);
input [4:0] op; // ALU Operation
input [7:0] a; // 8-bit Input a
input [7:0] b; // 8-bit Input b
output [7:0] y; // 8-bit Output
input cin;
output cout;
output zout;
// Reg declarations for outputs
reg [7:0] y;
// Internal declarations
reg addercout; // Carry out straight from the adder itself.
always @(*) begin
case (op) // synsys parallel_case
`ALU_ADD: {addercout, y} = a + b;
`ALU_SUB: {addercout, y} = b - a; // Carry out is really "borrow"
`ALU_AND: {addercout, y} = {1'b0, a & b};
`ALU_ROR: {addercout, y} = {b[0], cin, b[7:1]};
`ALU_ROL: {addercout, y} = {b[7], b[6:0], cin};
`ALU_OR: {addercout, y} = {1'b0, a | b};
`ALU_XOR: {addercout, y} = {1'b0, a ^ b};
`ALU_COM: {addercout, y} = {1'b0, ~b};
`ALU_SWAP: {addercout, y} = {1'b0, b[3:0], b[7:4]};
/*below added by liwei*/
`ALU_BTFSC,//: {addercout, y} = {1'b0, a & b };
`ALU_BTFSS: {addercout, y} = {1'b0, a & b }; //if the 'b' bit is 1 ,skip nxt instruction
`ALU_DEC: y = b - 1;
`ALU_INC: y = 1 + b;
`ALU_PA : {addercout, y} = {1'b0, a};
`ALU_PB : {addercout, y} = {1'b0, b};
`ALU_BSF : {addercout, y} = {1'B0,a | b};
`ALU_BCF : {addercout, y} = {1'b0,~a & b};
`ALU_ZERO: {addercout, y} = {1'b0, 8'h00};
default: {addercout, y} = {1'b0, 8'h00};
endcase
end
assign zout = (y == 8'h00);
assign cout = (op == `ALU_SUB) ? ~addercout : addercout;
endmodule
/trunk/pc_stack.v
0,0 → 1,30
`include "clairisc_def.h"
 
// A Basic Synchrounous FIFO (4 entries deep)
module sfifo4x11(clk, ctl,din, dout);
input clk;
input [1:0] ctl;
input [10:0] din;
output [10:0] dout;
reg [10:0] stack1, stack2, stack3, stack4;
assign dout = stack1;
always @(posedge clk)
begin
case (ctl)
`STK_PSH :// PUSH stack
begin
stack4 <= stack3;
stack3 <= stack2;
stack2 <= stack1;
stack1 <= din;
end
`STK_POP :// POP stack
begin
stack1 <= stack2;
stack2 <= stack3;
stack3 <= stack4;
end
// default ://do nothing
endcase
end
endmodule
/trunk/clairisc_def.h
0,0 → 1,69
`define MUXA_W 0
`define MUXA_BD 1
 
`define MUXB_EK 0
`define MUXB_REG 1
 
`define BRC_NOP 0
`define BRC_ZERO 1
`define BRC_NZERO 2
 
`define BG_ZERO 1
`define BG_NZERO 2
`define BG_IGN 0
`define BG_NOP 0
 
`define PC_NOP 0
`define PC_BRC 1
`define PC_GOTO 2
`define PC_CALL 2
`define PC_INS 2
`define PC_RET 3
`define PC_NEXT 4
 
`define MUXB_IGN 1'BX
`define MUXA_IGN 1'BX
 
`define R1_LEN 1
`define R2_LEN 2
`define R3_LEN 3
`define R4_LEN 4
`define R5_LEN 5
`define R8_LEN 8
`define R9_LEN 9
`define R11_LEN 11
`define R12_LEN 12
 
`define ALU_NOP 0
`define ALU_ADD 1
`define ALU_SUB 2
`define ALU_AND 3
`define ALU_OR 4
`define ALU_XOR 5
`define ALU_COM 6
`define ALU_ROR 7
`define ALU_ROL 8
`define ALU_SWAP 9
`define ALU_BSF 10
`define ALU_BCF 11
`define ALU_ZERO 12
`define ALU_DEC 13
`define ALU_INC 14
`define ALU_PB 15
`define ALU_PA 16
`define ALU_BTFSC 17
`define ALU_BTFSS 18
 
`define STK_PSH 1
`define STK_POP 2
`define STK_NOP 0
 
`define EN 1
`define DIS 0
 
`define ADDR_FSR 4
`define ADDR_STATUS 3
 
`define SIM 1
 
 
/trunk/risc_core.bde
0,0 → 1,9095
SCHM0103
 
HEADER
{
FREEID 15592
VARIABLES
{
#BLOCKTABLE_FILE="#table.bde"
#BLOCKTABLE_INCLUDED="1"
#LANGUAGE="VERILOG"
#MODULE="ClaiRISC_core"
 
 
CREATIONDATE="2008-2-25"
TITLE="ClaiRISC"
}
SYMBOL "#default" "alu" "alu"
{
HEADER
{
VARIABLES
{
#DESCRIPTION=""
#LANGUAGE="VERILOG"
#MODIFIED="1140880898"
}
}
PAGE ""
{
PAGEHEADER
{
RECT (0,0,240,200)
FREEID 17
}
BODY
{
RECT 1, -1, 0
{
VARIABLES
{
#OUTLINE_FILLING="1"
}
AREA (20,0,220,200)
}
TEXT 3, 0, 0
{
TEXT "$#NAME"
RECT (25,30,93,54)
ALIGN 4
MARGINS (1,1)
PARENT 2
}
TEXT 5, 0, 0
{
TEXT "$#NAME"
RECT (169,30,215,54)
ALIGN 6
MARGINS (1,1)
PARENT 4
}
TEXT 7, 0, 0
{
TEXT "$#NAME"
RECT (25,70,93,94)
ALIGN 4
MARGINS (1,1)
PARENT 6
}
TEXT 9, 0, 0
{
TEXT "$#NAME"
RECT (147,70,215,94)
ALIGN 6
MARGINS (1,1)
PARENT 8
}
TEXT 11, 0, 0
{
TEXT "$#NAME"
RECT (25,110,60,134)
ALIGN 4
MARGINS (1,1)
PARENT 10
}
TEXT 13, 0, 0
{
TEXT "$#NAME"
RECT (169,110,215,134)
ALIGN 6
MARGINS (1,1)
PARENT 12
}
TEXT 15, 0, 0
{
TEXT "$#NAME"
RECT (20,148,99,172)
ALIGN 4
MARGINS (1,1)
PARENT 14
}
PIN 2, 0, 0
{
COORD (0,40)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="a(7:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 4, 0, 0
{
COORD (240,40)
VARIABLES
{
#DIRECTION="OUT"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="cout"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 6, 0, 0
{
COORD (0,80)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="b(7:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 8, 0, 0
{
COORD (240,80)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="y(7:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 10, 0, 0
{
COORD (0,120)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="cin"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 12, 0, 0
{
COORD (240,120)
VARIABLES
{
#DIRECTION="OUT"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="zout"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 14, 0, 0
{
COORD (0,160)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="op(4:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
}
}
}
SYMBOL "#default" "alu_muxa" "alu_muxa"
{
HEADER
{
VARIABLES
{
#DESCRIPTION=""
#LANGUAGE="VERILOG"
#MODIFIED="1203406438"
}
}
PAGE ""
{
PAGEHEADER
{
RECT (0,0,320,160)
FREEID 11
}
BODY
{
RECT 1, -1, 0
{
VARIABLES
{
#OUTLINE_FILLING="1"
}
AREA (20,0,300,160)
}
TEXT 3, 0, 0
{
TEXT "$#NAME"
RECT (25,30,104,54)
ALIGN 4
MARGINS (1,1)
PARENT 2
}
TEXT 5, 0, 0
{
TEXT "$#NAME"
RECT (183,30,295,54)
ALIGN 6
MARGINS (1,1)
PARENT 4
}
TEXT 7, 0, 0
{
TEXT "$#NAME"
RECT (25,70,60,94)
ALIGN 4
MARGINS (1,1)
PARENT 6
}
TEXT 9, 0, 0
{
TEXT "$#NAME"
RECT (25,110,93,134)
ALIGN 4
MARGINS (1,1)
PARENT 8
}
PIN 2, 0, 0
{
COORD (0,40)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="bd(7:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 4, 0, 0
{
COORD (320,40)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="alu_a(7:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 6, 0, 0
{
COORD (0,80)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="ctl"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 8, 0, 0
{
COORD (0,120)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="w(7:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
}
}
}
SYMBOL "#default" "alu_muxb" "alu_muxb"
{
HEADER
{
VARIABLES
{
#DESCRIPTION=""
#LANGUAGE="VERILOG"
#MODIFIED="1140881510"
}
}
PAGE ""
{
PAGEHEADER
{
RECT (0,0,320,160)
FREEID 11
}
BODY
{
RECT 1, -1, 0
{
VARIABLES
{
#OUTLINE_FILLING="1"
}
AREA (20,0,300,160)
}
TEXT 3, 0, 0
{
TEXT "$#NAME"
RECT (25,30,60,54)
ALIGN 4
MARGINS (1,1)
PARENT 2
}
TEXT 5, 0, 0
{
TEXT "$#NAME"
RECT (183,30,295,54)
ALIGN 6
MARGINS (1,1)
PARENT 4
}
TEXT 7, 0, 0
{
TEXT "$#NAME"
RECT (25,70,93,94)
ALIGN 4
MARGINS (1,1)
PARENT 6
}
TEXT 9, 0, 0
{
TEXT "$#NAME"
RECT (25,110,93,134)
ALIGN 4
MARGINS (1,1)
PARENT 8
}
PIN 2, 0, 0
{
COORD (0,40)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="ctl"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 4, 0, 0
{
COORD (320,40)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="alu_b(7:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 6, 0, 0
{
COORD (0,80)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="f(7:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 8, 0, 0
{
COORD (0,120)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="k(8:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
}
}
}
SYMBOL "#default" "bg" "bg"
{
HEADER
{
VARIABLES
{
#DESCRIPTION=""
#LANGUAGE="VERILOG"
#MODIFIED="1140877883"
}
}
PAGE ""
{
PAGEHEADER
{
RECT (0,0,200,120)
FREEID 8
}
BODY
{
RECT 1, -1, 0
{
VARIABLES
{
#OUTLINE_FILLING="1"
}
AREA (20,0,180,120)
}
TEXT 3, 0, 0
{
TEXT "$#NAME"
RECT (25,30,115,54)
ALIGN 4
MARGINS (1,1)
PARENT 2
}
TEXT 5, 0, 0
{
TEXT "$#NAME"
RECT (107,30,175,54)
ALIGN 6
MARGINS (1,1)
PARENT 4
}
TEXT 7, 0, 0
{
TEXT "$#NAME"
RECT (25,70,38,94)
ALIGN 4
MARGINS (1,1)
PARENT 6
}
PIN 2, 0, 0
{
COORD (0,40)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="ctl(1:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 4, 0, 0
{
COORD (200,40)
VARIABLES
{
#DIRECTION="OUT"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="branch"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 6, 0, 0
{
COORD (0,80)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="z"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
}
}
}
SYMBOL "#default" "mem_man" "mem_man"
{
HEADER
{
VARIABLES
{
#DESCRIPTION=""
#LANGUAGE="VERILOG"
#MODIFIED="1203406652"
}
}
PAGE ""
{
PAGEHEADER
{
RECT (0,0,440,480)
FREEID 39
}
BODY
{
RECT 1, -1, 0
{
VARIABLES
{
#OUTLINE_FILLING="1"
}
AREA (20,0,420,480)
}
TEXT 3, 0, 0
{
TEXT "$#NAME"
RECT (25,30,71,54)
ALIGN 4
MARGINS (1,1)
PARENT 2
}
TEXT 5, 0, 0
{
TEXT "$#NAME"
RECT (314,30,415,54)
ALIGN 6
MARGINS (1,1)
PARENT 4
}
TEXT 7, 0, 0
{
TEXT "$#NAME"
RECT (25,70,49,94)
ALIGN 4
MARGINS (1,1)
PARENT 6
}
TEXT 9, 0, 0
{
TEXT "$#NAME"
RECT (391,70,415,94)
ALIGN 6
MARGINS (1,1)
PARENT 8
}
TEXT 11, 0, 0
{
TEXT "$#NAME"
RECT (25,110,60,134)
ALIGN 4
MARGINS (1,1)
PARENT 10
}
TEXT 13, 0, 0
{
TEXT "$#NAME"
RECT (314,110,415,134)
ALIGN 6
MARGINS (1,1)
PARENT 12
}
TEXT 15, 0, 0
{
TEXT "$#NAME"
RECT (25,150,115,174)
ALIGN 4
MARGINS (1,1)
PARENT 14
}
TEXT 17, 0, 0
{
TEXT "$#NAME"
RECT (270,150,415,174)
ALIGN 6
MARGINS (1,1)
PARENT 16
}
TEXT 19, 0, 0
{
TEXT "$#NAME"
RECT (25,190,159,214)
ALIGN 4
MARGINS (1,1)
PARENT 18
}
TEXT 21, 0, 0
{
TEXT "$#NAME"
RECT (237,190,415,214)
ALIGN 6
MARGINS (1,1)
PARENT 20
}
TEXT 23, 0, 0
{
TEXT "$#NAME"
RECT (25,230,159,254)
ALIGN 4
MARGINS (1,1)
PARENT 22
}
TEXT 25, 0, 0
{
TEXT "$#NAME"
RECT (237,230,415,254)
ALIGN 6
MARGINS (1,1)
PARENT 24
}
TEXT 27, 0, 0
{
TEXT "$#NAME"
RECT (25,270,60,294)
ALIGN 4
MARGINS (1,1)
PARENT 26
}
TEXT 29, 0, 0
{
TEXT "$#NAME"
RECT (292,270,415,294)
ALIGN 6
MARGINS (1,1)
PARENT 28
}
TEXT 31, 0, 0
{
TEXT "$#NAME"
RECT (25,310,159,334)
ALIGN 4
MARGINS (1,1)
PARENT 30
}
TEXT 33, 0, 0
{
TEXT "$#NAME"
RECT (25,350,82,374)
ALIGN 4
MARGINS (1,1)
PARENT 32
}
TEXT 35, 0, 0
{
TEXT "$#NAME"
RECT (25,390,71,414)
ALIGN 4
MARGINS (1,1)
PARENT 34
}
TEXT 37, 0, 0
{
TEXT "$#NAME"
RECT (25,430,49,454)
ALIGN 4
MARGINS (1,1)
PARENT 36
}
PIN 2, 0, 0
{
COORD (0,40)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="c_wr"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 4, 0, 0
{
COORD (440,40)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="bank(1:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 6, 0, 0
{
COORD (0,80)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="ci"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 8, 0, 0
{
COORD (440,80)
VARIABLES
{
#DIRECTION="OUT"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="co"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 10, 0, 0
{
COORD (0,120)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="clk"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 12, 0, 0
{
COORD (440,120)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="dout(7:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 14, 0, 0
{
COORD (0,160)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="din(7:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 16, 0, 0
{
COORD (440,160)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="exp_dout(7:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 18, 0, 0
{
COORD (0,200)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="exp_din(7:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 20, 0, 0
{
COORD (440,200)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="exp_rd_addr(6:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 22, 0, 0
{
COORD (0,240)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="rd_addr(6:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 24, 0, 0
{
COORD (440,240)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="exp_wr_addr(6:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 26, 0, 0
{
COORD (0,280)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="rst"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 28, 0, 0
{
COORD (440,280)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="status(7:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 30, 0, 0
{
COORD (0,320)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="wr_addr(6:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 32, 0, 0
{
COORD (0,360)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="wr_en"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 34, 0, 0
{
COORD (0,400)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="z_wr"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 36, 0, 0
{
COORD (0,440)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="zi"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
}
}
}
SYMBOL "#default" "pc_gen" "pc_gen"
{
HEADER
{
VARIABLES
{
#DESCRIPTION=""
#LANGUAGE="VERILOG"
#MODIFIED="1204259715"
}
}
PAGE ""
{
PAGEHEADER
{
RECT (0,-80,280,280)
FREEID 23
}
BODY
{
RECT 1, -1, 0
{
VARIABLES
{
#OUTLINE_FILLING="1"
}
AREA (20,-80,260,280)
}
TEXT 3, 0, 0
{
TEXT "$#NAME"
RECT (25,30,60,54)
ALIGN 4
MARGINS (1,1)
PARENT 2
}
TEXT 5, 0, 0
{
TEXT "$#NAME"
RECT (143,30,255,54)
ALIGN 6
MARGINS (1,1)
PARENT 4
}
TEXT 7, 0, 0
{
TEXT "$#NAME"
RECT (20,68,110,92)
ALIGN 4
MARGINS (1,1)
PARENT 6
}
TEXT 9, 0, 0
{
TEXT "$#NAME"
RECT (20,108,121,132)
ALIGN 4
MARGINS (1,1)
PARENT 8
}
TEXT 11, 0, 0
{
TEXT "$#NAME"
RECT (25,150,137,174)
ALIGN 4
MARGINS (1,1)
PARENT 10
}
TEXT 13, 0, 0
{
TEXT "$#NAME"
RECT (25,190,181,214)
ALIGN 4
MARGINS (1,1)
PARENT 12
}
TEXT 15, 0, 0
{
TEXT "$#NAME"
RECT (25,230,148,254)
ALIGN 4
MARGINS (1,1)
PARENT 14
}
TEXT 18, 0, 0
{
TEXT "$#NAME"
RECT (25,-10,104,14)
ALIGN 4
MARGINS (1,1)
PARENT 17
}
TEXT 21, 0, 0
{
TEXT "$#NAME"
RECT (25,-50,60,-26)
ALIGN 4
MARGINS (1,1)
PARENT 20
}
PIN 2, 0, 0
{
COORD (0,40)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="brc"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 4, 0, 0
{
COORD (280,40)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="pc_o(10:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 6, 0, 0
{
COORD (0,80)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="ctl(2:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 8, 0, 0
{
COORD (0,120)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="ins(11:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 10, 0, 0
{
COORD (0,160)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="pc_i(10:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 12, 0, 0
{
COORD (0,200)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="stack_pc(10:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 14, 0, 0
{
COORD (0,240)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="status(7:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 17, 0, 0
{
COORD (0,0)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#MODIFIED=""
#NAME="ek(8:0)"
#NUMBER="0"
#SIDE="left"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 20, 0, 0
{
COORD (0,-40)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#MODIFIED=""
#NAME="rst"
#NUMBER="0"
#SIDE="left"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
}
}
}
SYMBOL "#default" "sfifo4x11" "sfifo4x11"
{
HEADER
{
VARIABLES
{
#DESCRIPTION=""
#LANGUAGE="VERILOG"
#MODIFIED="1203406747"
}
}
PAGE ""
{
PAGEHEADER
{
RECT (0,0,260,160)
FREEID 11
}
BODY
{
RECT 1, -1, 0
{
VARIABLES
{
#OUTLINE_FILLING="1"
}
AREA (20,0,240,160)
}
TEXT 3, 0, 0
{
TEXT "$#NAME"
RECT (25,30,60,54)
ALIGN 4
MARGINS (1,1)
PARENT 2
}
TEXT 5, 0, 0
{
TEXT "$#NAME"
RECT (123,30,235,54)
ALIGN 6
MARGINS (1,1)
PARENT 4
}
TEXT 7, 0, 0
{
TEXT "$#NAME"
RECT (25,70,115,94)
ALIGN 4
MARGINS (1,1)
PARENT 6
}
TEXT 9, 0, 0
{
TEXT "$#NAME"
RECT (25,110,126,134)
ALIGN 4
MARGINS (1,1)
PARENT 8
}
PIN 2, 0, 0
{
COORD (0,40)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="clk"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 4, 0, 0
{
COORD (260,40)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="dout(10:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 6, 0, 0
{
COORD (0,80)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="ctl(1:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 8, 0, 0
{
COORD (0,120)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="din(10:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
}
}
}
SYMBOL "#default" "w_reg" "w_reg"
{
HEADER
{
VARIABLES
{
#DESCRIPTION=""
#LANGUAGE="VERILOG"
#MODIFIED="1203406755"
}
}
PAGE ""
{
PAGEHEADER
{
RECT (0,0,240,160)
FREEID 11
}
BODY
{
RECT 1, -1, 0
{
VARIABLES
{
#OUTLINE_FILLING="1"
}
AREA (20,0,220,160)
}
TEXT 3, 0, 0
{
TEXT "$#NAME"
RECT (25,30,60,54)
ALIGN 4
MARGINS (1,1)
PARENT 2
}
TEXT 5, 0, 0
{
TEXT "$#NAME"
RECT (147,30,215,54)
ALIGN 6
MARGINS (1,1)
PARENT 4
}
TEXT 7, 0, 0
{
TEXT "$#NAME"
RECT (25,70,93,94)
ALIGN 4
MARGINS (1,1)
PARENT 6
}
TEXT 9, 0, 0
{
TEXT "$#NAME"
RECT (25,110,104,134)
ALIGN 4
MARGINS (1,1)
PARENT 8
}
PIN 2, 0, 0
{
COORD (0,40)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="clk"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 4, 0, 0
{
COORD (240,40)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="q(7:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 6, 0, 0
{
COORD (0,80)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="d(7:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 8, 0, 0
{
COORD (0,120)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_wr_en"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
}
}
}
SYMBOL "#default" "decoder" "decoder"
{
HEADER
{
VARIABLES
{
#DESCRIPTION=""
#LANGUAGE="VERILOG"
#MODIFIED="1140882181"
}
}
PAGE ""
{
PAGEHEADER
{
RECT (0,0,320,440)
FREEID 25
}
BODY
{
RECT 1, -1, 0
{
VARIABLES
{
#OUTLINE_FILLING="1"
}
AREA (20,0,300,440)
}
TEXT 3, 0, 0
{
TEXT "$#NAME"
RECT (25,30,137,54)
ALIGN 4
MARGINS (1,1)
PARENT 2
}
TEXT 5, 0, 0
{
TEXT "$#NAME"
RECT (205,30,295,54)
ALIGN 6
MARGINS (1,1)
PARENT 4
}
TEXT 7, 0, 0
{
TEXT "$#NAME"
RECT (205,70,295,94)
ALIGN 6
MARGINS (1,1)
PARENT 6
}
TEXT 9, 0, 0
{
TEXT "$#NAME"
RECT (172,110,295,134)
ALIGN 6
MARGINS (1,1)
PARENT 8
}
TEXT 11, 0, 0
{
TEXT "$#NAME"
RECT (183,150,295,174)
ALIGN 6
MARGINS (1,1)
PARENT 10
}
TEXT 13, 0, 0
{
TEXT "$#NAME"
RECT (249,190,295,214)
ALIGN 6
MARGINS (1,1)
PARENT 12
}
TEXT 15, 0, 0
{
TEXT "$#NAME"
RECT (227,230,295,254)
ALIGN 6
MARGINS (1,1)
PARENT 14
}
TEXT 17, 0, 0
{
TEXT "$#NAME"
RECT (172,270,295,294)
ALIGN 6
MARGINS (1,1)
PARENT 16
}
TEXT 19, 0, 0
{
TEXT "$#NAME"
RECT (150,310,295,334)
ALIGN 6
MARGINS (1,1)
PARENT 18
}
TEXT 21, 0, 0
{
TEXT "$#NAME"
RECT (249,350,295,374)
ALIGN 6
MARGINS (1,1)
PARENT 20
}
TEXT 23, 0, 0
{
TEXT "$#NAME"
RECT (249,390,295,414)
ALIGN 6
MARGINS (1,1)
PARENT 22
}
PIN 2, 0, 0
{
COORD (0,40)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="inst(11:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 4, 0, 0
{
COORD (320,40)
VARIABLES
{
#DIRECTION="OUT"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="alu_muxa"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 6, 0, 0
{
COORD (320,80)
VARIABLES
{
#DIRECTION="OUT"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="alu_muxb"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 8, 0, 0
{
COORD (320,120)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="alu_op(4:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 10, 0, 0
{
COORD (320,160)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="bg_op(1:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 12, 0, 0
{
COORD (320,200)
VARIABLES
{
#DIRECTION="OUT"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="c_wr"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 14, 0, 0
{
COORD (320,240)
VARIABLES
{
#DIRECTION="OUT"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="men_wr"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 16, 0, 0
{
COORD (320,280)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="pc_ctl(2:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 18, 0, 0
{
COORD (320,320)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="stack_op(1:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 20, 0, 0
{
COORD (320,360)
VARIABLES
{
#DIRECTION="OUT"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_wr"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 22, 0, 0
{
COORD (320,400)
VARIABLES
{
#DIRECTION="OUT"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="z_wr"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
}
}
}
SYMBOL "#default" "ins2bd" "ins2bd"
{
HEADER
{
VARIABLES
{
#DESCRIPTION=""
#LANGUAGE="VERILOG"
#MODIFIED="1140882215"
}
}
PAGE ""
{
PAGEHEADER
{
RECT (0,0,200,80)
FREEID 6
}
BODY
{
RECT 1, -1, 0
{
VARIABLES
{
#OUTLINE_FILLING="1"
}
AREA (20,0,180,80)
}
TEXT 3, 0, 0
{
TEXT "$#NAME"
RECT (25,30,126,54)
ALIGN 4
MARGINS (1,1)
PARENT 2
}
TEXT 5, 0, 0
{
TEXT "$#NAME"
RECT (96,30,175,54)
ALIGN 6
MARGINS (1,1)
PARENT 4
}
PIN 2, 0, 0
{
COORD (0,40)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="ins(11:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 4, 0, 0
{
COORD (200,40)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="bd(7:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
}
}
}
SYMBOL "#default" "r8_reg_clr_cls" "r8_reg_clr_cls"
{
HEADER
{
VARIABLES
{
#DESCRIPTION=""
#LANGUAGE="VERILOG"
#MODIFIED="1140882281"
}
}
PAGE ""
{
PAGEHEADER
{
RECT (0,0,180,200)
FREEID 12
}
BODY
{
RECT 1, -1, 0
{
VARIABLES
{
#OUTLINE_FILLING="1"
}
AREA (20,0,160,200)
}
TEXT 3, 0, 0
{
TEXT "$#NAME"
RECT (25,30,60,54)
ALIGN 4
MARGINS (1,1)
PARENT 2
}
TEXT 5, 0, 0
{
TEXT "$#NAME"
RECT (54,30,155,54)
ALIGN 6
MARGINS (1,1)
PARENT 4
}
TEXT 7, 0, 0
{
TEXT "$#NAME"
RECT (25,70,60,94)
ALIGN 4
MARGINS (1,1)
PARENT 6
}
TEXT 9, 0, 0
{
TEXT "$#NAME"
RECT (25,110,60,134)
ALIGN 4
MARGINS (1,1)
PARENT 8
}
TEXT 11, 0, 0
{
TEXT "$#NAME"
RECT (25,150,126,174)
ALIGN 4
MARGINS (1,1)
PARENT 10
}
PIN 2, 0, 0
{
COORD (0,40)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="clk"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 4, 0, 0
{
COORD (180,40)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="r8_o(7:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 6, 0, 0
{
COORD (0,80)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="clr"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 8, 0, 0
{
COORD (0,120)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="cls"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 10, 0, 0
{
COORD (0,160)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="r8_i(7:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
}
}
}
SYMBOL "#default" "ek_reg_clr_cls" "ek_reg_clr_cls"
{
HEADER
{
VARIABLES
{
#DESCRIPTION=""
#LANGUAGE="VERILOG"
#MODIFIED="1140882775"
}
}
PAGE ""
{
PAGEHEADER
{
RECT (0,0,180,200)
FREEID 12
}
BODY
{
RECT 1, -1, 0
{
VARIABLES
{
#OUTLINE_FILLING="1"
}
AREA (20,0,160,200)
}
TEXT 3, 0, 0
{
TEXT "$#NAME"
RECT (25,30,60,54)
ALIGN 4
MARGINS (1,1)
PARENT 2
}
TEXT 5, 0, 0
{
TEXT "$#NAME"
RECT (54,30,155,54)
ALIGN 6
MARGINS (1,1)
PARENT 4
}
TEXT 7, 0, 0
{
TEXT "$#NAME"
RECT (25,70,60,94)
ALIGN 4
MARGINS (1,1)
PARENT 6
}
TEXT 9, 0, 0
{
TEXT "$#NAME"
RECT (25,110,60,134)
ALIGN 4
MARGINS (1,1)
PARENT 8
}
TEXT 11, 0, 0
{
TEXT "$#NAME"
RECT (25,150,126,174)
ALIGN 4
MARGINS (1,1)
PARENT 10
}
PIN 2, 0, 0
{
COORD (0,40)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="clk"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 4, 0, 0
{
COORD (180,40)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="r9_o(8:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 6, 0, 0
{
COORD (0,80)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="clr"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 8, 0, 0
{
COORD (0,120)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="cls"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 10, 0, 0
{
COORD (0,160)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="ins(11:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
}
}
}
SYMBOL "#default" "mem_addr" "mem_addr"
{
HEADER
{
VARIABLES
{
#DESCRIPTION=""
#LANGUAGE="VERILOG"
#MODIFIED="1204085384"
}
}
PAGE ""
{
PAGEHEADER
{
RECT (0,0,300,120)
FREEID 9
}
BODY
{
RECT 1, -1, 0
{
VARIABLES
{
#OUTLINE_FILLING="1"
}
AREA (20,0,280,120)
}
TEXT 3, 0, 0
{
TEXT "$#NAME"
RECT (25,30,126,54)
ALIGN 4
MARGINS (1,1)
PARENT 2
}
TEXT 5, 0, 0
{
TEXT "$#NAME"
RECT (119,30,275,54)
ALIGN 6
MARGINS (1,1)
PARENT 4
}
TEXT 7, 0, 0
{
TEXT "$#NAME"
RECT (25,70,126,94)
ALIGN 4
MARGINS (1,1)
PARENT 6
}
PIN 2, 0, 0
{
COORD (0,40)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="addr(4:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 4, 0, 0
{
COORD (300,40)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="file_addr(6:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 6, 0, 0
{
COORD (0,80)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="bank(1:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
}
}
}
SYMBOL "#default" "ins2wb_addr" "ins2wb_addr"
{
HEADER
{
VARIABLES
{
#DESCRIPTION=""
#LANGUAGE="VERILOG"
#MODIFIED="1140886139"
}
}
PAGE ""
{
PAGEHEADER
{
RECT (-120,0,260,80)
FREEID 7
}
BODY
{
RECT 1, -1, 0
{
VARIABLES
{
#OUTLINE_FILLING="1"
}
AREA (-100,0,240,80)
}
TEXT 3, 0, 0
{
TEXT "$#NAME"
RECT (-95,30,6,54)
ALIGN 4
MARGINS (1,1)
PARENT 2
}
TEXT 5, 0, 0
{
TEXT "$#NAME"
RECT (101,30,235,54)
ALIGN 6
MARGINS (1,1)
PARENT 4
}
PIN 2, 0, 0
{
COORD (-120,40)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="ins(11:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 4, 0, 0
{
COORD (260,40)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="wb_addr(4:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
}
}
}
SYMBOL "#default" "r5_reg_clr_cls" "r5_reg_clr_cls"
{
HEADER
{
VARIABLES
{
#DESCRIPTION=""
#LANGUAGE="VERILOG"
#MODIFIED="1140883554"
}
}
PAGE ""
{
PAGEHEADER
{
RECT (0,0,180,200)
FREEID 12
}
BODY
{
RECT 1, -1, 0
{
VARIABLES
{
#OUTLINE_FILLING="1"
}
AREA (20,0,160,200)
}
TEXT 3, 0, 0
{
TEXT "$#NAME"
RECT (25,30,60,54)
ALIGN 4
MARGINS (1,1)
PARENT 2
}
TEXT 5, 0, 0
{
TEXT "$#NAME"
RECT (54,30,155,54)
ALIGN 6
MARGINS (1,1)
PARENT 4
}
TEXT 7, 0, 0
{
TEXT "$#NAME"
RECT (25,70,60,94)
ALIGN 4
MARGINS (1,1)
PARENT 6
}
TEXT 9, 0, 0
{
TEXT "$#NAME"
RECT (25,110,60,134)
ALIGN 4
MARGINS (1,1)
PARENT 8
}
TEXT 11, 0, 0
{
TEXT "$#NAME"
RECT (25,150,126,174)
ALIGN 4
MARGINS (1,1)
PARENT 10
}
PIN 2, 0, 0
{
COORD (0,40)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="clk"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 4, 0, 0
{
COORD (180,40)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="r5_o(4:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 6, 0, 0
{
COORD (0,80)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="clr"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 8, 0, 0
{
COORD (0,120)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="cls"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 10, 0, 0
{
COORD (0,160)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="r5_i(4:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
}
}
}
SYMBOL "#default" "pram" "pram"
{
HEADER
{
VARIABLES
{
#DESCRIPTION=""
#LANGUAGE="VERILOG"
#MODIFIED="1140885812"
}
}
PAGE ""
{
PAGEHEADER
{
RECT (0,0,220,240)
FREEID 15
}
BODY
{
RECT 1, -1, 0
{
VARIABLES
{
#OUTLINE_FILLING="1"
}
AREA (20,0,200,240)
}
TEXT 3, 0, 0
{
TEXT "$#NAME"
RECT (25,30,60,54)
ALIGN 4
MARGINS (1,1)
PARENT 2
}
TEXT 5, 0, 0
{
TEXT "$#NAME"
RECT (83,30,195,54)
ALIGN 6
MARGINS (1,1)
PARENT 4
}
TEXT 7, 0, 0
{
TEXT "$#NAME"
RECT (25,70,126,94)
ALIGN 4
MARGINS (1,1)
PARENT 6
}
TEXT 9, 0, 0
{
TEXT "$#NAME"
RECT (25,110,170,134)
ALIGN 4
MARGINS (1,1)
PARENT 8
}
TEXT 11, 0, 0
{
TEXT "$#NAME"
RECT (25,150,49,174)
ALIGN 4
MARGINS (1,1)
PARENT 10
}
TEXT 13, 0, 0
{
TEXT "$#NAME"
RECT (25,190,170,214)
ALIGN 4
MARGINS (1,1)
PARENT 12
}
PIN 2, 0, 0
{
COORD (0,40)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="clk"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 4, 0, 0
{
COORD (220,40)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="dout(11:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 6, 0, 0
{
COORD (0,80)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="din(11:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 8, 0, 0
{
COORD (0,120)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="rd_addr(10:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 10, 0, 0
{
COORD (0,160)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="we"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 12, 0, 0
{
COORD (0,200)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="wr_addr(10:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
}
}
}
SYMBOL "#default" "r1_reg_clr_cls" "r1_reg_clr_cls"
{
HEADER
{
VARIABLES
{
#DESCRIPTION=""
#LANGUAGE="VERILOG"
#MODIFIED="1203988930"
}
}
PAGE ""
{
PAGEHEADER
{
RECT (0,0,180,200)
FREEID 12
}
BODY
{
RECT 1, -1, 0
{
VARIABLES
{
#OUTLINE_FILLING="1"
}
AREA (20,0,160,200)
}
TEXT 3, 0, 0
{
TEXT "$#NAME"
RECT (25,30,60,54)
ALIGN 4
MARGINS (1,1)
PARENT 2
}
TEXT 5, 0, 0
{
TEXT "$#NAME"
RECT (54,30,155,54)
ALIGN 6
MARGINS (1,1)
PARENT 4
}
TEXT 7, 0, 0
{
TEXT "$#NAME"
RECT (25,70,60,94)
ALIGN 4
MARGINS (1,1)
PARENT 6
}
TEXT 9, 0, 0
{
TEXT "$#NAME"
RECT (25,110,60,134)
ALIGN 4
MARGINS (1,1)
PARENT 8
}
TEXT 11, 0, 0
{
TEXT "$#NAME"
RECT (25,150,126,174)
ALIGN 4
MARGINS (1,1)
PARENT 10
}
PIN 2, 0, 0
{
COORD (0,40)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="clk"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 4, 0, 0
{
COORD (180,40)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="r1_o(0:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 6, 0, 0
{
COORD (0,80)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="clr"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 8, 0, 0
{
COORD (0,120)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="cls"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 10, 0, 0
{
COORD (0,160)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="r1_i(0:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
}
}
}
SYMBOL "#default" "r2_reg_clr_cls" "r2_reg_clr_cls"
{
HEADER
{
VARIABLES
{
#DESCRIPTION=""
#LANGUAGE="VERILOG"
#MODIFIED="1203989499"
}
}
PAGE ""
{
PAGEHEADER
{
RECT (0,0,180,200)
FREEID 12
}
BODY
{
RECT 1, -1, 0
{
VARIABLES
{
#OUTLINE_FILLING="1"
}
AREA (20,0,160,200)
}
TEXT 3, 0, 0
{
TEXT "$#NAME"
RECT (25,30,60,54)
ALIGN 4
MARGINS (1,1)
PARENT 2
}
TEXT 5, 0, 0
{
TEXT "$#NAME"
RECT (54,30,155,54)
ALIGN 6
MARGINS (1,1)
PARENT 4
}
TEXT 7, 0, 0
{
TEXT "$#NAME"
RECT (25,70,60,94)
ALIGN 4
MARGINS (1,1)
PARENT 6
}
TEXT 9, 0, 0
{
TEXT "$#NAME"
RECT (25,110,60,134)
ALIGN 4
MARGINS (1,1)
PARENT 8
}
TEXT 11, 0, 0
{
TEXT "$#NAME"
RECT (25,150,126,174)
ALIGN 4
MARGINS (1,1)
PARENT 10
}
PIN 2, 0, 0
{
COORD (0,40)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="clk"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 4, 0, 0
{
COORD (180,40)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="r2_o(1:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 6, 0, 0
{
COORD (0,80)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="clr"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 8, 0, 0
{
COORD (0,120)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="cls"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 10, 0, 0
{
COORD (0,160)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="r2_i(1:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
}
}
}
SYMBOL "#default" "r11_reg_clr_cls" "r11_reg_clr_cls"
{
HEADER
{
VARIABLES
{
#DESCRIPTION=""
#LANGUAGE="VERILOG"
#MODIFIED="1203992608"
}
}
PAGE ""
{
PAGEHEADER
{
RECT (0,0,200,200)
FREEID 12
}
BODY
{
RECT 1, -1, 0
{
VARIABLES
{
#OUTLINE_FILLING="1"
}
AREA (20,0,180,200)
}
TEXT 3, 0, 0
{
TEXT "$#NAME"
RECT (25,30,60,54)
ALIGN 4
MARGINS (1,1)
PARENT 2
}
TEXT 5, 0, 0
{
TEXT "$#NAME"
RECT (52,30,175,54)
ALIGN 6
MARGINS (1,1)
PARENT 4
}
TEXT 7, 0, 0
{
TEXT "$#NAME"
RECT (25,70,60,94)
ALIGN 4
MARGINS (1,1)
PARENT 6
}
TEXT 9, 0, 0
{
TEXT "$#NAME"
RECT (25,110,60,134)
ALIGN 4
MARGINS (1,1)
PARENT 8
}
TEXT 11, 0, 0
{
TEXT "$#NAME"
RECT (25,150,148,174)
ALIGN 4
MARGINS (1,1)
PARENT 10
}
PIN 2, 0, 0
{
COORD (0,40)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="clk"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 4, 0, 0
{
COORD (200,40)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="r11_o(10:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 6, 0, 0
{
COORD (0,80)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="clr"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 8, 0, 0
{
COORD (0,120)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="cls"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 10, 0, 0
{
COORD (0,160)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#MDA_RECORD_TOKEN="OTHER"
#NAME="r11_i(10:0)"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
}
}
}
}
 
PAGE ""
{
PAGEHEADER
{
PAGESIZE (2400,2400)
MARGINS (0,0,0,0)
RECT (0,0,100,200)
}
BODY
{
INSTANCE 29, 0, 0
{
VARIABLES
{
#COMPONENT="alu"
#LIBRARY="#default"
#REFERENCE="i_alu"
#SYMBOL="alu"
}
COORD (1620,800)
VERTEXES ( (2,9961), (6,9857), (10,9860), (14,9981), (4,9861), (8,9868), (12,9855) )
}
TEXT 30, 0, 0
{
TEXT "$#REFERENCE"
RECT (1620,764,1707,799)
ALIGN 8
MARGINS (1,1)
PARENT 29
}
TEXT 34, 0, 0
{
TEXT "$#COMPONENT"
RECT (1620,1000,1673,1035)
MARGINS (1,1)
PARENT 29
}
INSTANCE 38, 0, 0
{
VARIABLES
{
#COMPONENT="alu_muxa"
#LIBRARY="#default"
#REFERENCE="i_alu_muxa"
#SYMBOL="alu_muxa"
}
COORD (1040,800)
VERTEXES ( (2,9960), (6,9966), (8,9964), (4,9962) )
}
TEXT 39, 0, 0
{
TEXT "$#REFERENCE"
RECT (1040,764,1212,799)
ALIGN 8
MARGINS (1,1)
PARENT 38
}
TEXT 43, 0, 0
{
TEXT "$#COMPONENT"
RECT (1040,960,1178,995)
MARGINS (1,1)
PARENT 38
}
INSTANCE 47, 0, 0
{
VARIABLES
{
#COMPONENT="alu_muxb"
#LIBRARY="#default"
#REFERENCE="i_alu_muxb"
#SYMBOL="alu_muxb"
}
COORD (1020,1060)
VERTEXES ( (2,9956), (6,9864), (4,9856), (8,11332) )
}
TEXT 48, 0, 0
{
TEXT "$#REFERENCE"
RECT (1020,1024,1192,1059)
ALIGN 8
MARGINS (1,1)
PARENT 47
}
TEXT 52, 0, 0
{
TEXT "$#COMPONENT"
RECT (1020,1220,1158,1255)
MARGINS (1,1)
PARENT 47
}
TEXT 73, 0, 0
{
TEXT "$#NAME"
RECT (1334,810,1546,839)
ALIGN 9
MARGINS (1,1)
PARENT 10373
}
TEXT 78, 0, 0
{
TEXT "$#NAME"
RECT (1314,1070,1526,1099)
ALIGN 9
MARGINS (1,1)
PARENT 10042
}
INSTANCE 116, 0, 0
{
VARIABLES
{
#COMPONENT="bg"
#LIBRARY="#default"
#REFERENCE="i_bg"
#SYMBOL="bg"
}
COORD (1900,520)
VERTEXES ( (2,9993), (4,9988), (6,11188) )
}
TEXT 117, 0, 0
{
TEXT "$#REFERENCE"
RECT (1900,484,1970,519)
ALIGN 8
MARGINS (1,1)
PARENT 116
}
TEXT 121, 0, 0
{
TEXT "$#COMPONENT"
RECT (1900,640,1936,675)
MARGINS (1,1)
PARENT 116
}
NET WIRE 133, 0, 0
{
VARIABLES
{
#NAME="w_z"
}
}
TEXT 134, 0, 0
{
TEXT "$#NAME"
RECT (1902,761,1946,790)
ALIGN 4
MARGINS (1,1)
PARENT 11189
}
NET BUS 138, 0, 0
{
VARIABLES
{
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_alu_in_b[7:0]"
#VERILOG_TYPE="wire"
}
}
NET BUS 139, 0, 0
{
VARIABLES
{
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_alu_in_a[7:0]"
#VERILOG_TYPE="wire"
}
}
INSTANCE 201, 0, 0
{
VARIABLES
{
#COMPONENT="mem_man"
#LIBRARY="#default"
#REFERENCE="i_reg_file"
#SYMBOL="mem_man"
}
COORD (1600,1260)
VERTEXES ( (6,9862), (10,9998), (14,9870), (32,10015), (34,9996), (36,9858), (4,9888), (8,9859), (12,9863), (16,10868), (20,10870), (24,10872), (18,11154), (22,11274), (30,11276), (26,11883), (2,12008), (28,13413) )
}
TEXT 202, 0, 0
{
TEXT "$#REFERENCE"
RECT (1820,1345,1992,1380)
ALIGN 8
MARGINS (1,1)
PARENT 201
}
TEXT 206, 0, 0
{
TEXT "$#COMPONENT"
RECT (1860,1680,1981,1715)
MARGINS (1,1)
PARENT 201
}
NET WIRE 230, 0, 0
{
VARIABLES
{
#NAME="w_c_2alu"
}
}
TEXT 231, 0, 0
{
TEXT "$#NAME"
RECT (1763,1070,1877,1099)
ALIGN 9
MARGINS (1,1)
PARENT 10058
}
NET WIRE 247, 0, 0
{
VARIABLES
{
#NAME="w_c_2mem"
}
}
TEXT 248, 0, 0
{
TEXT "$#NAME"
RECT (1882,1026,1996,1055)
ALIGN 4
MARGINS (1,1)
PARENT 10065
}
TEXT 269, 0, 0
{
TEXT "$#NAME"
RECT (1618,1190,1802,1219)
ALIGN 9
MARGINS (1,1)
PARENT 10076
}
INSTANCE 273, 0, 0
{
VARIABLES
{
#COMPONENT="pc_gen"
#LIBRARY="#default"
#REFERENCE="i_pc_gen"
#SYMBOL="pc_gen"
}
COORD (1020,440)
VERTEXES ( (2,13405), (4,13499), (6,13408), (8,13409), (10,13410), (12,13412), (14,13414), (17,13415), (20,13416) )
}
TEXT 274, 0, 0
{
TEXT "$#REFERENCE"
RECT (1100,367,1238,402)
ALIGN 8
MARGINS (1,1)
PARENT 273
}
TEXT 278, 0, 0
{
TEXT "$#COMPONENT"
RECT (1020,720,1124,755)
MARGINS (1,1)
PARENT 273
}
TEXT 304, 0, 0
{
TEXT "$#NAME"
RECT (464,711,662,740)
ALIGN 9
MARGINS (1,1)
PARENT 13502
}
INSTANCE 694, 0, 0
{
VARIABLES
{
#COMPONENT="sfifo4x11"
#LIBRARY="#default"
#REFERENCE="PC_FIFO"
#SYMBOL="sfifo4x11"
}
COORD (480,460)
VERTEXES ( (2,9911), (6,9898), (8,9865), (4,13411) )
}
TEXT 695, 0, 0
{
TEXT "$#REFERENCE"
RECT (480,424,601,459)
ALIGN 8
MARGINS (1,1)
PARENT 694
}
TEXT 699, 0, 0
{
TEXT "$#COMPONENT"
RECT (480,620,635,655)
MARGINS (1,1)
PARENT 694
}
TEXT 750, 0, 0
{
TEXT "$#NAME"
RECT (720,766,862,795)
ALIGN 4
MARGINS (1,1)
PARENT 12689
}
NET BUS 801, 0, 0
{
VARIABLES
{
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_status[7:0]"
#VERILOG_TYPE="wire"
}
}
TEXT 802, 0, 0
{
TEXT "$#NAME"
RECT (1223,750,1407,779)
ALIGN 9
MARGINS (1,1)
PARENT 13480
}
INSTANCE 824, 0, 0
{
VARIABLES
{
#COMPONENT="w_reg"
#LIBRARY="#default"
#REFERENCE="U2"
#SYMBOL="w_reg"
}
COORD (760,820)
VERTEXES ( (2,10006), (6,9873), (8,9875), (4,9963) )
}
TEXT 825, 0, 0
{
TEXT "$#REFERENCE"
RECT (760,784,796,819)
ALIGN 8
MARGINS (1,1)
PARENT 824
}
TEXT 829, 0, 0
{
TEXT "$#COMPONENT"
RECT (760,980,847,1015)
MARGINS (1,1)
PARENT 824
}
TEXT 845, 0, 0
{
TEXT "$#NAME"
RECT (1012,881,1168,910)
ALIGN 4
MARGINS (1,1)
PARENT 10377
}
NET BUS 872, 0, 0
{
VARIABLES
{
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_alu_res[7:0]"
#VERILOG_TYPE="wire"
}
}
TEXT 873, 0, 0
{
TEXT "$#NAME"
RECT (1140,1266,1338,1295)
ALIGN 4
MARGINS (1,1)
PARENT 10100
}
NET WIRE 935, 0, 0
{
VARIABLES
{
#NAME="w_muxa_ctl"
}
}
TEXT 936, 0, 0
{
TEXT "$#NAME"
RECT (1362,611,1504,640)
ALIGN 4
MARGINS (1,1)
PARENT 10354
}
NET WIRE 948, 0, 0
{
VARIABLES
{
#NAME="w_muxb_ctl"
}
}
TEXT 949, 0, 0
{
TEXT "$#NAME"
RECT (982,1312,1124,1341)
ALIGN 4
MARGINS (1,1)
PARENT 10328
}
INSTANCE 953, 0, 0
{
VARIABLES
{
#COMPONENT="decoder"
#LIBRARY="#default"
#REFERENCE="decoder"
#SYMBOL="decoder"
}
COORD (640,1320)
VERTEXES ( (2,9883), (4,9957), (6,9953), (8,9976), (10,9990), (12,10004), (14,10017), (18,9897), (20,9874), (22,10010), (16,13407) )
}
TEXT 954, 0, 0
{
TEXT "$#REFERENCE"
RECT (640,1284,761,1319)
ALIGN 8
MARGINS (1,1)
PARENT 953
}
TEXT 958, 0, 0
{
TEXT "$#COMPONENT"
RECT (640,1760,761,1795)
MARGINS (1,1)
PARENT 953
}
NET BUS 1023, 0, 0
{
VARIABLES
{
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_brc_ctl[1:0]"
#VERILOG_TYPE="wire"
}
}
TEXT 1024, 0, 0
{
TEXT "$#NAME"
RECT (1475,591,1673,620)
ALIGN 9
MARGINS (1,1)
PARENT 10477
}
NET BUS 1040, 0, 0
{
VARIABLES
{
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_pc_gen_ctl[4:0]"
#VERILOG_TYPE="wire"
}
}
TEXT 1041, 0, 0
{
TEXT "$#NAME"
RECT (1142,1528,1382,1557)
ALIGN 4
MARGINS (1,1)
PARENT 13436
}
NET WIRE 1059, 0, 0
{
VARIABLES
{
#NAME="w_mem_wr"
}
}
TEXT 1060, 0, 0
{
TEXT "$#NAME"
RECT (976,1530,1090,1559)
ALIGN 9
MARGINS (1,1)
PARENT 10580
}
NET WIRE 1076, 0, 0
{
VARIABLES
{
#NAME="w_c_wr"
}
}
TEXT 1077, 0, 0
{
TEXT "$#NAME"
RECT (1011,1490,1097,1519)
ALIGN 9
MARGINS (1,1)
PARENT 10528
}
NET WIRE 1089, 0, 0
{
VARIABLES
{
#NAME="w_z_wr"
}
}
TEXT 1090, 0, 0
{
TEXT "$#NAME"
RECT (1018,1690,1104,1719)
ALIGN 9
MARGINS (1,1)
PARENT 10552
}
NET WIRE 1106, 0, 0
{
VARIABLES
{
#NAME="w_w_wr"
}
}
TEXT 1107, 0, 0
{
TEXT "$#NAME"
RECT (960,1406,1046,1435)
ALIGN 4
MARGINS (1,1)
PARENT 10123
}
NET BUS 1123, 0, 0
{
VARIABLES
{
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_alu_op[4:0]"
#VERILOG_TYPE="wire"
}
}
TEXT 1124, 0, 0
{
TEXT "$#NAME"
RECT (1148,1411,1332,1440)
ALIGN 9
MARGINS (1,1)
PARENT 10411
}
NET BUS 1168, 0, 0
{
VARIABLES
{
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_ins[11:0]"
#VERILOG_TYPE="wire"
}
}
TEXT 1169, 0, 0
{
TEXT "$#NAME"
RECT (432,1330,588,1359)
ALIGN 9
MARGINS (1,1)
PARENT 10139
}
NET BUS 1250, 0, 0
{
VARIABLES
{
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_ek_r[8:0]"
#VERILOG_TYPE="wire"
}
}
TEXT 1251, 0, 0
{
TEXT "$#NAME"
RECT (982,1106,1138,1135)
ALIGN 4
MARGINS (1,1)
PARENT 11336
}
INSTANCE 1354, 0, 0
{
VARIABLES
{
#COMPONENT="ins2bd"
#LIBRARY="#default"
#REFERENCE="U3"
#SYMBOL="ins2bd"
}
COORD (420,1200)
VERTEXES ( (2,9882), (4,9907) )
}
TEXT 1355, 0, 0
{
TEXT "$#REFERENCE"
RECT (420,1164,456,1199)
ALIGN 8
MARGINS (1,1)
PARENT 1354
}
TEXT 1359, 0, 0
{
TEXT "$#COMPONENT"
RECT (420,1280,524,1315)
MARGINS (1,1)
PARENT 1354
}
INSTANCE 1386, 0, 0
{
VARIABLES
{
#COMPONENT="r8_reg_clr_cls"
#LIBRARY="#default"
#REFERENCE="i_bd"
#SYMBOL="r8_reg_clr_cls"
}
COORD (360,1420)
VERTEXES ( (2,9913), (6,9940), (8,10039), (10,9908), (4,9959) )
}
TEXT 1387, 0, 0
{
TEXT "$#REFERENCE"
RECT (360,1384,430,1419)
ALIGN 8
MARGINS (1,1)
PARENT 1386
}
TEXT 1391, 0, 0
{
TEXT "$#COMPONENT"
RECT (360,1620,600,1655)
MARGINS (1,1)
PARENT 1386
}
TEXT 1419, 0, 0
{
TEXT "$#NAME"
RECT (418,1270,546,1299)
ALIGN 9
MARGINS (1,1)
PARENT 10217
}
TEXT 1438, 0, 0
{
TEXT "$#NAME"
RECT (462,771,618,800)
ALIGN 9
MARGINS (1,1)
PARENT 10369
}
NET BUS 1442, 0, 0
{
VARIABLES
{
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_bd_r[7:0]"
#VERILOG_TYPE="wire"
}
}
NET BUS 1443, 0, 0
{
VARIABLES
{
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_bd[7:0]"
#VERILOG_TYPE="wire"
}
}
NET BUS 1460, 0, 0
{
VARIABLES
{
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_stk_op[1:0]"
#VERILOG_TYPE="wire"
}
}
TEXT 1461, 0, 0
{
TEXT "$#NAME"
RECT (342,824,526,853)
ALIGN 4
MARGINS (1,1)
PARENT 10172
}
INSTANCE 1633, 0, 0
{
VARIABLES
{
#COMPONENT="ek_reg_clr_cls"
#LIBRARY="#default"
#REFERENCE="U5"
#SYMBOL="ek_reg_clr_cls"
}
COORD (760,1020)
VERTEXES ( (2,9923), (6,9939), (8,9945), (10,9879), (4,9876) )
}
TEXT 1634, 0, 0
{
TEXT "$#REFERENCE"
RECT (760,984,796,1019)
ALIGN 8
MARGINS (1,1)
PARENT 1633
}
TEXT 1638, 0, 0
{
TEXT "$#COMPONENT"
RECT (760,1220,1000,1255)
MARGINS (1,1)
PARENT 1633
}
INSTANCE 1723, 0, 0
{
VARIABLES
{
#COMPONENT="mem_addr"
#LIBRARY="#default"
#REFERENCE="WRITE_CMB"
#SYMBOL="mem_addr"
}
COORD (1660,1840)
VERTEXES ( (2,9886), (6,9947), (4,11277) )
}
TEXT 1724, 0, 0
{
TEXT "$#REFERENCE"
RECT (1660,1804,1815,1839)
ALIGN 8
MARGINS (1,1)
PARENT 1723
}
TEXT 1728, 0, 0
{
TEXT "$#COMPONENT"
RECT (1660,1960,1798,1995)
MARGINS (1,1)
PARENT 1723
}
INSTANCE 1769, 0, 0
{
VARIABLES
{
#COMPONENT="ins2wb_addr"
#LIBRARY="#default"
#REFERENCE="U7"
#SYMBOL="ins2wb_addr"
}
COORD (760,1800)
VERTEXES ( (2,10009), (4,10014) )
}
TEXT 1770, 0, 0
{
TEXT "$#REFERENCE"
RECT (640,1764,676,1799)
ALIGN 8
MARGINS (1,1)
PARENT 1769
}
TEXT 1774, 0, 0
{
TEXT "$#COMPONENT"
RECT (640,1880,829,1915)
MARGINS (1,1)
PARENT 1769
}
INSTANCE 1786, 0, 0
{
VARIABLES
{
#COMPONENT="r5_reg_clr_cls"
#LIBRARY="#default"
#REFERENCE="U8"
#SYMBOL="r5_reg_clr_cls"
}
COORD (1160,1880)
VERTEXES ( (2,10019), (6,9942), (8,9944), (10,9949), (4,9885) )
}
TEXT 1787, 0, 0
{
TEXT "$#REFERENCE"
RECT (1160,1844,1196,1879)
ALIGN 8
MARGINS (1,1)
PARENT 1786
}
TEXT 1791, 0, 0
{
TEXT "$#COMPONENT"
RECT (1160,2080,1400,2115)
MARGINS (1,1)
PARENT 1786
}
TEXT 1810, 0, 0
{
TEXT "$#NAME"
RECT (1011,2010,1209,2039)
ALIGN 9
MARGINS (1,1)
PARENT 10570
}
TEXT 1841, 0, 0
{
TEXT "$#NAME"
RECT (1461,1850,1659,1879)
ALIGN 9
MARGINS (1,1)
PARENT 10149
}
NET BUS 1845, 0, 0
{
VARIABLES
{
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_wbadd_r[4:0]"
#VERILOG_TYPE="wire"
}
}
NET BUS 1858, 0, 0
{
VARIABLES
{
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_bank[1:0]"
#VERILOG_TYPE="wire"
}
}
TEXT 1859, 0, 0
{
TEXT "$#NAME"
RECT (1802,1730,1958,1759)
ALIGN 9
MARGINS (1,1)
PARENT 10153
}
TEXT 1876, 0, 0
{
TEXT "$#NAME"
RECT (1670,1750,1868,1779)
ALIGN 9
MARGINS (1,1)
PARENT 11292
}
NET BUS 1880, 0, 0
{
VARIABLES
{
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_wr_addr[6:0]"
#VERILOG_TYPE="wire"
}
}
NET BUS 1929, 0, 0
{
VARIABLES
{
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_wreg[7:0]"
#VERILOG_TYPE="wire"
}
}
NET BUS 1930, 0, 0
{
VARIABLES
{
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_stk_pc[10:0]"
#VERILOG_TYPE="wire"
}
}
TEXT 1931, 0, 0
{
TEXT "$#NAME"
RECT (811,610,1009,639)
ALIGN 9
MARGINS (1,1)
PARENT 13470
}
NET BUS 1935, 0, 0
{
VARIABLES
{
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_pc_nxt[10:0]"
#VERILOG_TYPE="wire"
}
}
NET BUS 1936, 0, 0
{
VARIABLES
{
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_pc[10:0]"
#VERILOG_TYPE="wire"
}
}
NET BUS 1977, 0, 0
{
VARIABLES
{
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_wd_addr[4:0]"
#VERILOG_TYPE="wire"
}
}
NET BUS 2000, 0, 0
NET BUS 2004, 0, 0
INSTANCE 2020, 0, 0
{
VARIABLES
{
#COMPONENT="BusOutput"
#LIBRARY="#terminals"
#REFERENCE="exp_dout(7:0)"
#SYMBOL="BusOutput"
}
COORD (2180,1420)
VERTEXES ( (2,10869) )
}
TEXT 2021, 0, 0
{
TEXT "$#REFERENCE"
RECT (2232,1403,2455,1438)
ALIGN 4
MARGINS (1,1)
PARENT 2020
}
INSTANCE 2025, 0, 0
{
VARIABLES
{
#COMPONENT="BusOutput"
#LIBRARY="#terminals"
#REFERENCE="exp_rd_addr(6:0)"
#SYMBOL="BusOutput"
}
COORD (2180,1460)
VERTEXES ( (2,10871) )
}
TEXT 2026, 0, 0
{
TEXT "$#REFERENCE"
RECT (2232,1443,2506,1478)
ALIGN 4
MARGINS (1,1)
PARENT 2025
}
INSTANCE 2030, 0, 0
{
VARIABLES
{
#COMPONENT="BusOutput"
#LIBRARY="#terminals"
#REFERENCE="exp_wr_addr(6:0)"
#SYMBOL="BusOutput"
}
COORD (2180,1500)
VERTEXES ( (2,10873) )
}
TEXT 2031, 0, 0
{
TEXT "$#REFERENCE"
RECT (2232,1483,2506,1518)
ALIGN 4
MARGINS (1,1)
PARENT 2030
}
INSTANCE 2035, 0, 0
{
VARIABLES
{
#COMPONENT="BusInput"
#LIBRARY="#terminals"
#REFERENCE="exp_din(7:0)"
#SYMBOL="BusInput"
}
COORD (2180,1580)
ORIENTATION 2
VERTEXES ( (2,11155) )
}
TEXT 2036, 0, 0
{
TEXT "$#REFERENCE"
RECT (2231,1563,2437,1598)
ALIGN 4
MARGINS (1,1)
PARENT 2035
}
NET BUS 2053, 0, 0
TEXT 2084, 0, 0
{
TEXT "$#NAME"
RECT (1830,338,1944,367)
ALIGN 4
MARGINS (1,1)
PARENT 13256
}
INSTANCE 2547, 0, 0
{
VARIABLES
{
#COMPONENT="pram"
#LIBRARY="#default"
#REFERENCE="program_rom"
#SYMBOL="pram"
}
COORD (320,1800)
VERTEXES ( (4,9909), (12,10672), (6,10670), (10,10668), (2,9915), (8,9910) )
}
TEXT 2548, 0, 0
{
TEXT "$#REFERENCE"
RECT (320,1764,509,1799)
ALIGN 8
MARGINS (1,1)
PARENT 2547
}
TEXT 2552, 0, 0
{
TEXT "$#COMPONENT"
RECT (320,2040,390,2075)
MARGINS (1,1)
PARENT 2547
}
INSTANCE 2675, 0, 0
{
VARIABLES
{
#COMPONENT="Input"
#LIBRARY="#terminals"
#REFERENCE="clk"
#SYMBOL="Input"
}
COORD (180,500)
VERTEXES ( (2,9924) )
}
TEXT 2676, 0, 0
{
TEXT "$#REFERENCE"
RECT (76,483,129,518)
ALIGN 6
MARGINS (1,1)
PARENT 2675
}
INSTANCE 2790, 0, 0
{
VARIABLES
{
#COMPONENT="Input"
#LIBRARY="#terminals"
#REFERENCE="rst"
#SYMBOL="Input"
}
COORD (180,400)
VERTEXES ( (2,13703) )
}
TEXT 2791, 0, 0
{
TEXT "$#REFERENCE"
RECT (76,383,129,418)
ALIGN 6
MARGINS (1,1)
PARENT 2790
}
NET WIRE 3107, 0, 0
{
VARIABLES
{
#NAME="w_branch"
}
}
TEXT 3108, 0, 0
{
TEXT "$#NAME"
RECT (1463,291,1577,320)
ALIGN 9
MARGINS (1,1)
PARENT 13255
}
NET BUS 3140, 0, 0
NET BUS 3171, 0, 0
NET BUS 3175, 0, 0
NET WIRE 3179, 0, 0
INSTANCE 3186, 0, 0
{
VARIABLES
{
#COMPONENT="Input"
#LIBRARY="#terminals"
#REFERENCE="pdata_we"
#SYMBOL="Input"
}
COORD (280,1940)
VERTEXES ( (2,10669) )
}
TEXT 3187, 0, 0
{
TEXT "$#REFERENCE"
RECT (91,1923,229,1958)
ALIGN 6
MARGINS (1,1)
PARENT 3186
}
INSTANCE 3196, 0, 0
{
VARIABLES
{
#COMPONENT="BusInput"
#LIBRARY="#terminals"
#REFERENCE="pdata_in(11:0)"
#SYMBOL="BusInput"
}
COORD (280,1880)
VERTEXES ( (2,10671) )
}
TEXT 3197, 0, 0
{
TEXT "$#REFERENCE"
RECT (-11,1863,229,1898)
ALIGN 6
MARGINS (1,1)
PARENT 3196
}
INSTANCE 3201, 0, 0
{
VARIABLES
{
#COMPONENT="BusInput"
#LIBRARY="#terminals"
#REFERENCE="pdata_wraddr(10:0)"
#SYMBOL="BusInput"
}
COORD (280,2000)
VERTEXES ( (2,10673) )
}
TEXT 3202, 0, 0
{
TEXT "$#REFERENCE"
RECT (-79,1983,229,2018)
ALIGN 6
MARGINS (1,1)
PARENT 3201
}
INSTANCE 3206, 0, 0
{
VARIABLES
{
#COMPONENT="Ground"
#LIBRARY="#connectors"
#REFERENCE="GND"
#SYMBOL="Ground"
}
COORD (140,1520)
VERTEXES ( (2,9937) )
}
TEXT 3207, 0, 0
{
TEXT "$#REFERENCE"
RECT (162,1533,215,1568)
ALIGN 4
MARGINS (1,1)
PARENT 3206
}
INSTANCE 3395, 0, 0
{
VARIABLES
{
#COMPONENT="mem_addr"
#LIBRARY="#default"
#REFERENCE="READ_CMB"
#SYMBOL="mem_addr"
}
COORD (1660,2040)
VERTEXES ( (2,9950), (6,9946), (4,11275) )
}
TEXT 3396, 0, 0
{
TEXT "$#REFERENCE"
RECT (1660,2004,1798,2039)
ALIGN 8
MARGINS (1,1)
PARENT 3395
}
TEXT 3397, 0, 0
{
TEXT "$#COMPONENT"
RECT (1660,2160,1798,2195)
MARGINS (1,1)
PARENT 3395
}
NET BUS 3427, 0, 0
{
VARIABLES
{
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_wr_Addr[6:0]"
#VERILOG_TYPE="wire"
}
}
TEXT 3428, 0, 0
{
TEXT "$#NAME"
RECT (1660,1950,1858,1979)
ALIGN 9
MARGINS (1,1)
PARENT 11283
}
INSTANCE 3642, 0, 0
{
VARIABLES
{
#COMPONENT="r1_reg_clr_cls"
#LIBRARY="#default"
#REFERENCE="muxa_ctl_reg"
#SYMBOL="r1_reg_clr_cls"
}
COORD (720,180)
VERTEXES ( (2,9968), (6,9974), (8,9969), (10,9954), (4,9955) )
}
TEXT 3643, 0, 0
{
TEXT "$#REFERENCE"
RECT (720,144,926,179)
ALIGN 8
MARGINS (1,1)
PARENT 3642
}
TEXT 3647, 0, 0
{
TEXT "$#COMPONENT"
RECT (720,380,960,415)
MARGINS (1,1)
PARENT 3642
}
INSTANCE 3651, 0, 0
{
VARIABLES
{
#COMPONENT="r1_reg_clr_cls"
#LIBRARY="#default"
#REFERENCE="muxb_ctl_reg"
#SYMBOL="r1_reg_clr_cls"
}
COORD (1100,40)
VERTEXES ( (2,9982), (6,9973), (8,9971), (10,9958), (4,9965) )
}
TEXT 3652, 0, 0
{
TEXT "$#REFERENCE"
RECT (1100,4,1306,39)
ALIGN 8
MARGINS (1,1)
PARENT 3651
}
TEXT 3653, 0, 0
{
TEXT "$#COMPONENT"
RECT (1100,240,1340,275)
MARGINS (1,1)
PARENT 3651
}
TEXT 3682, 0, 0
{
TEXT "$#NAME"
RECT (840,466,1010,495)
ALIGN 4
MARGINS (1,1)
PARENT 10341
}
TEXT 3792, 0, 0
{
TEXT "$#NAME"
RECT (1402,516,1572,545)
ALIGN 4
MARGINS (1,1)
PARENT 10382
}
NET WIRE 3828, 0, 0
INSTANCE 3871, 0, 0
{
VARIABLES
{
#COMPONENT="Ground"
#LIBRARY="#connectors"
#REFERENCE="GND"
#SYMBOL="Ground"
}
COORD (480,240)
VERTEXES ( (2,9975) )
}
TEXT 3872, 0, 0
{
TEXT "$#REFERENCE"
RECT (502,253,555,288)
ALIGN 4
MARGINS (1,1)
PARENT 3871
}
INSTANCE 3909, 0, 0
{
VARIABLES
{
#COMPONENT="r5_reg_clr_cls"
#LIBRARY="#default"
#REFERENCE="U11"
#SYMBOL="r5_reg_clr_cls"
}
COORD (1980,820)
VERTEXES ( (2,9984), (6,9985), (8,10022), (10,9977), (4,9980) )
}
TEXT 3910, 0, 0
{
TEXT "$#REFERENCE"
RECT (1980,784,2033,819)
ALIGN 8
MARGINS (1,1)
PARENT 3909
}
TEXT 3914, 0, 0
{
TEXT "$#COMPONENT"
RECT (1980,1020,2220,1055)
MARGINS (1,1)
PARENT 3909
}
TEXT 3953, 0, 0
{
TEXT "$#NAME"
RECT (2182,936,2394,965)
ALIGN 4
MARGINS (1,1)
PARENT 10439
}
INSTANCE 3983, 0, 0
{
VARIABLES
{
#COMPONENT="Ground"
#LIBRARY="#connectors"
#REFERENCE="GND"
#SYMBOL="Ground"
}
COORD (1940,1100)
VERTEXES ( (2,10023) )
}
TEXT 3984, 0, 0
{
TEXT "$#REFERENCE"
RECT (1962,1113,2015,1148)
ALIGN 4
MARGINS (1,1)
PARENT 3983
}
NET WIRE 3990, 0, 0
INSTANCE 4035, 0, 0
{
VARIABLES
{
#COMPONENT="r2_reg_clr_cls"
#LIBRARY="#default"
#REFERENCE="U12"
#SYMBOL="r2_reg_clr_cls"
}
COORD (1660,380)
VERTEXES ( (2,9994), (10,9991), (4,9992), (8,11898), (6,13261) )
}
TEXT 4036, 0, 0
{
TEXT "$#REFERENCE"
RECT (1660,344,1713,379)
ALIGN 8
MARGINS (1,1)
PARENT 4035
}
TEXT 4040, 0, 0
{
TEXT "$#COMPONENT"
RECT (1660,580,1900,615)
MARGINS (1,1)
PARENT 4035
}
TEXT 4187, 0, 0
{
TEXT "$#NAME"
RECT (1880,446,2092,475)
ALIGN 4
MARGINS (1,1)
PARENT 10484
}
INSTANCE 4207, 0, 0
{
VARIABLES
{
#COMPONENT="Ground"
#LIBRARY="#connectors"
#REFERENCE="GND"
#SYMBOL="Ground"
}
COORD (1560,520)
VERTEXES ( (2,11899) )
}
TEXT 4208, 0, 0
{
TEXT "$#REFERENCE"
RECT (1582,533,1635,568)
ALIGN 4
MARGINS (1,1)
PARENT 4207
}
NET WIRE 4214, 0, 0
NET WIRE 4306, 0, 0
{
VARIABLES
{
#NAME="w_reg_muxb_r"
}
}
NET WIRE 4307, 0, 0
{
VARIABLES
{
#NAME="w_muxa_ctl_r"
}
}
INSTANCE 4308, 0, 0
{
VARIABLES
{
#COMPONENT="r1_reg_clr_cls"
#LIBRARY="#default"
#REFERENCE="U13"
#SYMBOL="r1_reg_clr_cls"
}
COORD (1160,1640)
VERTEXES ( (2,9999), (8,10038), (10,10011), (4,9997), (6,11903) )
}
TEXT 4309, 0, 0
{
TEXT "$#REFERENCE"
RECT (1160,1604,1213,1639)
ALIGN 8
MARGINS (1,1)
PARENT 4308
}
TEXT 4313, 0, 0
{
TEXT "$#COMPONENT"
RECT (1160,1840,1400,1875)
MARGINS (1,1)
PARENT 4308
}
NET WIRE 4335, 0, 0
{
VARIABLES
{
#NAME="w_z_wr_r"
}
}
TEXT 4336, 0, 0
{
TEXT "$#NAME"
RECT (1423,1630,1537,1659)
ALIGN 9
MARGINS (1,1)
PARENT 10498
}
INSTANCE 4389, 0, 0
{
VARIABLES
{
#COMPONENT="r1_reg_clr_cls"
#LIBRARY="#default"
#REFERENCE="U14"
#SYMBOL="r1_reg_clr_cls"
}
COORD (1400,2140)
VERTEXES ( (2,10008), (10,10005), (6,12479), (4,12009), (8,12587) )
}
TEXT 4390, 0, 0
{
TEXT "$#REFERENCE"
RECT (1400,2104,1453,2139)
ALIGN 8
MARGINS (1,1)
PARENT 4389
}
TEXT 4394, 0, 0
{
TEXT "$#COMPONENT"
RECT (1400,2340,1640,2375)
MARGINS (1,1)
PARENT 4389
}
NET WIRE 4417, 0, 0
{
VARIABLES
{
#NAME="w_c_wr_r"
}
}
TEXT 4418, 0, 0
{
TEXT "$#NAME"
RECT (1592,1696,1706,1725)
ALIGN 4
MARGINS (1,1)
PARENT 12013
}
INSTANCE 4475, 0, 0
{
VARIABLES
{
#COMPONENT="Ground"
#LIBRARY="#connectors"
#REFERENCE="GND"
#SYMBOL="Ground"
}
COORD (1120,2240)
VERTEXES ( (2,10037) )
}
TEXT 4476, 0, 0
{
TEXT "$#REFERENCE"
RECT (1120,2223,1173,2258)
ALIGN 4
MARGINS (1,1)
PARENT 4475
}
NET WIRE 4482, 0, 0
INSTANCE 4527, 0, 0
{
VARIABLES
{
#COMPONENT="r1_reg_clr_cls"
#LIBRARY="#default"
#REFERENCE="U15"
#SYMBOL="r1_reg_clr_cls"
}
COORD (800,1980)
VERTEXES ( (2,10020), (10,10018), (4,10016), (6,10977), (8,11945) )
}
TEXT 4528, 0, 0
{
TEXT "$#REFERENCE"
RECT (800,1944,853,1979)
ALIGN 8
MARGINS (1,1)
PARENT 4527
}
TEXT 4532, 0, 0
{
TEXT "$#COMPONENT"
RECT (800,2180,1040,2215)
MARGINS (1,1)
PARENT 4527
}
NET WIRE 4563, 0, 0
{
VARIABLES
{
#NAME="w_mem_wr_r"
}
}
TEXT 4564, 0, 0
{
TEXT "$#NAME"
RECT (1299,1590,1441,1619)
ALIGN 9
MARGINS (1,1)
PARENT 11768
}
NET WIRE 4576, 0, 0
NET BUS 5229, 0, 0
{
VARIABLES
{
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_br_ctl_r[1:0]"
#VERILOG_TYPE="wire"
}
}
INSTANCE 5230, 0, 0
{
VARIABLES
{
#COMPONENT="r11_reg_clr_cls"
#LIBRARY="#default"
#REFERENCE="I_PC"
#SYMBOL="r11_reg_clr_cls"
}
COORD (440,880)
VERTEXES ( (2,10029), (8,10033), (10,10032), (4,12685), (6,12892) )
}
TEXT 5231, 0, 0
{
TEXT "$#REFERENCE"
RECT (440,844,510,879)
ALIGN 8
MARGINS (1,1)
PARENT 5230
}
TEXT 5235, 0, 0
{
TEXT "$#COMPONENT"
RECT (440,1080,697,1115)
MARGINS (1,1)
PARENT 5230
}
VTX 9854, 0, 0
{
COORD (1900,920)
}
VTX 9855, 0, 0
{
COORD (1860,920)
}
VTX 9856, 0, 0
{
COORD (1340,1100)
}
VTX 9857, 0, 0
{
COORD (1620,880)
}
VTX 9858, 0, 0
{
COORD (1600,1700)
}
VTX 9859, 0, 0
{
COORD (2040,1340)
}
VTX 9860, 0, 0
{
COORD (1620,920)
}
VTX 9861, 0, 0
{
COORD (1860,840)
}
VTX 9862, 0, 0
{
COORD (1600,1340)
}
VTX 9863, 0, 0
{
COORD (2040,1380)
}
VTX 9864, 0, 0
{
COORD (1020,1140)
}
VTX 9865, 0, 0
{
COORD (480,580)
}
VTX 9868, 0, 0
{
COORD (1860,880)
}
VTX 9869, 0, 0
{
COORD (1560,1300)
}
VTX 9870, 0, 0
{
COORD (1600,1420)
}
VTX 9871, 0, 0
{
COORD (380,1180)
}
VTX 9873, 0, 0
{
COORD (760,900)
}
VTX 9874, 0, 0
{
COORD (960,1680)
}
VTX 9875, 0, 0
{
COORD (760,940)
}
VTX 9876, 0, 0
{
COORD (940,1060)
}
VTX 9879, 0, 0
{
COORD (760,1180)
}
VTX 9880, 0, 0
{
COORD (600,1360)
}
VTX 9881, 0, 0
{
COORD (380,1240)
}
VTX 9882, 0, 0
{
COORD (420,1240)
}
VTX 9883, 0, 0
{
COORD (640,1360)
}
VTX 9884, 0, 0
{
COORD (600,1840)
}
VTX 9885, 0, 0
{
COORD (1340,1920)
}
VTX 9886, 0, 0
{
COORD (1660,1880)
}
VTX 9887, 0, 0
{
COORD (1640,1920)
}
VTX 9888, 0, 0
{
COORD (2040,1300)
}
VTX 9897, 0, 0
{
COORD (960,1640)
}
VTX 9898, 0, 0
{
COORD (480,540)
}
VTX 9906, 0, 0
{
COORD (280,1040)
}
VTX 9907, 0, 0
{
COORD (620,1240)
}
VTX 9908, 0, 0
{
COORD (360,1580)
}
VTX 9909, 0, 0
{
COORD (540,1840)
}
VTX 9910, 0, 0
{
COORD (320,1920)
}
VTX 9911, 0, 0
{
COORD (480,500)
}
VTX 9912, 0, 0
{
COORD (200,500)
}
VTX 9913, 0, 0
{
COORD (360,1460)
}
VTX 9914, 0, 0
{
COORD (200,1460)
}
VTX 9915, 0, 0
{
COORD (320,1840)
}
VTX 9916, 0, 0
{
COORD (200,1660)
}
VTX 9917, 0, 0
{
COORD (720,1920)
}
VTX 9918, 0, 0
{
COORD (200,1080)
}
VTX 9919, 0, 0
{
COORD (200,920)
}
VTX 9920, 0, 0
{
COORD (200,860)
}
VTX 9921, 0, 0
{
COORD (200,1340)
}
VTX 9922, 0, 0
{
COORD (1120,1380)
}
VTX 9923, 0, 0
{
COORD (760,1060)
}
VTX 9924, 0, 0
{
COORD (180,500)
}
VTX 9936, 0, 0
{
COORD (260,1500)
}
VTX 9937, 0, 0
{
COORD (140,1520)
}
VTX 9938, 0, 0
{
COORD (260,1140)
}
VTX 9939, 0, 0
{
COORD (760,1100)
}
VTX 9940, 0, 0
{
COORD (360,1500)
}
VTX 9941, 0, 0
{
COORD (320,1500)
}
VTX 9942, 0, 0
{
COORD (1160,1960)
}
VTX 9943, 0, 0
{
COORD (320,1540)
}
VTX 9944, 0, 0
{
COORD (1160,2000)
}
VTX 9945, 0, 0
{
COORD (760,1140)
}
VTX 9946, 0, 0
{
COORD (1660,2120)
}
VTX 9947, 0, 0
{
COORD (1660,1920)
}
VTX 9948, 0, 0
{
COORD (1100,2040)
}
VTX 9949, 0, 0
{
COORD (1160,2040)
}
VTX 9950, 0, 0
{
COORD (1660,2080)
}
VTX 9953, 0, 0
{
COORD (960,1400)
}
VTX 9954, 0, 0
{
COORD (720,340)
}
VTX 9955, 0, 0
{
COORD (900,220)
}
VTX 9956, 0, 0
{
COORD (1020,1100)
}
VTX 9957, 0, 0
{
COORD (960,1360)
}
VTX 9958, 0, 0
{
COORD (1100,200)
}
VTX 9959, 0, 0
{
COORD (540,1460)
}
VTX 9960, 0, 0
{
COORD (1040,840)
}
VTX 9961, 0, 0
{
COORD (1620,840)
}
VTX 9962, 0, 0
{
COORD (1360,840)
}
VTX 9963, 0, 0
{
COORD (1000,860)
}
VTX 9964, 0, 0
{
COORD (1040,920)
}
VTX 9965, 0, 0
{
COORD (1280,80)
}
VTX 9966, 0, 0
{
COORD (1040,880)
}
VTX 9967, 0, 0
{
COORD (660,80)
}
VTX 9968, 0, 0
{
COORD (720,220)
}
VTX 9969, 0, 0
{
COORD (720,300)
}
VTX 9970, 0, 0
{
COORD (640,220)
}
VTX 9971, 0, 0
{
COORD (1100,160)
}
VTX 9972, 0, 0
{
COORD (1060,120)
}
VTX 9973, 0, 0
{
COORD (1100,120)
}
VTX 9974, 0, 0
{
COORD (720,260)
}
VTX 9975, 0, 0
{
COORD (480,240)
}
VTX 9976, 0, 0
{
COORD (960,1440)
}
VTX 9977, 0, 0
{
COORD (1980,980)
}
VTX 9980, 0, 0
{
COORD (2160,860)
}
VTX 9981, 0, 0
{
COORD (1620,960)
}
VTX 9982, 0, 0
{
COORD (1100,80)
}
VTX 9983, 0, 0
{
COORD (1080,80)
}
VTX 9984, 0, 0
{
COORD (1980,860)
}
VTX 9985, 0, 0
{
COORD (1980,900)
}
VTX 9987, 0, 0
{
COORD (1960,700)
}
VTX 9988, 0, 0
{
COORD (2100,560)
}
VTX 9990, 0, 0
{
COORD (960,1480)
}
VTX 9991, 0, 0
{
COORD (1660,540)
}
VTX 9992, 0, 0
{
COORD (1840,420)
}
VTX 9993, 0, 0
{
COORD (1900,560)
}
VTX 9994, 0, 0
{
COORD (1660,420)
}
VTX 9996, 0, 0
{
COORD (1600,1660)
}
VTX 9997, 0, 0
{
COORD (1340,1680)
}
VTX 9998, 0, 0
{
COORD (1600,1380)
}
VTX 9999, 0, 0
{
COORD (1160,1680)
}
VTX 10004, 0, 0
{
COORD (960,1520)
}
VTX 10005, 0, 0
{
COORD (1400,2300)
}
VTX 10006, 0, 0
{
COORD (760,860)
}
VTX 10007, 0, 0
{
COORD (680,860)
}
VTX 10008, 0, 0
{
COORD (1400,2180)
}
VTX 10009, 0, 0
{
COORD (640,1840)
}
VTX 10010, 0, 0
{
COORD (960,1720)
}
VTX 10011, 0, 0
{
COORD (1160,1800)
}
VTX 10014, 0, 0
{
COORD (1020,1840)
}
VTX 10015, 0, 0
{
COORD (1600,1620)
}
VTX 10016, 0, 0
{
COORD (980,2020)
}
VTX 10017, 0, 0
{
COORD (960,1560)
}
VTX 10018, 0, 0
{
COORD (800,2140)
}
VTX 10019, 0, 0
{
COORD (1160,1920)
}
VTX 10020, 0, 0
{
COORD (800,2020)
}
VTX 10022, 0, 0
{
COORD (1980,940)
}
VTX 10023, 0, 0
{
COORD (1940,1100)
}
VTX 10029, 0, 0
{
COORD (440,920)
}
VTX 10032, 0, 0
{
COORD (440,1040)
}
VTX 10033, 0, 0
{
COORD (440,1000)
}
VTX 10036, 0, 0
{
COORD (1120,2220)
}
VTX 10037, 0, 0
{
COORD (1120,2240)
}
VTX 10038, 0, 0
{
COORD (1160,1760)
}
VTX 10039, 0, 0
{
COORD (360,1540)
}
WIRE 10040, 0, 0
{
NET 133
VTX 9854, 9855
}
VTX 10041, 0, 0
{
COORD (1440,1100)
}
BUS 10042, 0, 0
{
NET 138
VTX 9856, 10041
VARIABLES
{
#NAMED="1"
}
}
VTX 10043, 0, 0
{
COORD (1440,880)
}
BUS 10044, 0, 0
{
NET 138
VTX 10041, 10043
}
BUS 10045, 0, 0
{
NET 138
VTX 10043, 9857
}
VTX 10046, 0, 0
{
COORD (1900,1160)
}
WIRE 10047, 0, 0
{
NET 133
VTX 9854, 10046
}
VTX 10048, 0, 0
{
COORD (1480,1160)
}
WIRE 10049, 0, 0
{
NET 133
VTX 10046, 10048
}
VTX 10050, 0, 0
{
COORD (1480,1700)
}
WIRE 10051, 0, 0
{
NET 133
VTX 10048, 10050
}
WIRE 10052, 0, 0
{
NET 133
VTX 10050, 9858
}
VTX 10053, 0, 0
{
COORD (2060,1340)
}
WIRE 10054, 0, 0
{
NET 230
VTX 9859, 10053
}
VTX 10055, 0, 0
{
COORD (2060,1100)
}
WIRE 10056, 0, 0
{
NET 230
VTX 10053, 10055
}
VTX 10057, 0, 0
{
COORD (1580,1100)
}
WIRE 10058, 0, 0
{
NET 230
VTX 10055, 10057
VARIABLES
{
#NAMED="1"
}
}
VTX 10059, 0, 0
{
COORD (1580,920)
}
WIRE 10060, 0, 0
{
NET 230
VTX 10057, 10059
}
WIRE 10061, 0, 0
{
NET 230
VTX 10059, 9860
}
VTX 10062, 0, 0
{
COORD (1880,840)
}
WIRE 10063, 0, 0
{
NET 247
VTX 9861, 10062
}
VTX 10064, 0, 0
{
COORD (1880,1240)
}
WIRE 10065, 0, 0
{
NET 247
VTX 10062, 10064
VARIABLES
{
#NAMED="1"
}
}
VTX 10066, 0, 0
{
COORD (1580,1240)
}
WIRE 10067, 0, 0
{
NET 247
VTX 10064, 10066
}
VTX 10068, 0, 0
{
COORD (1580,1340)
}
WIRE 10069, 0, 0
{
NET 247
VTX 10066, 10068
}
WIRE 10070, 0, 0
{
NET 247
VTX 10068, 9862
}
VTX 10071, 0, 0
{
COORD (2080,1380)
}
BUS 10072, 0, 0
{
NET 12776
VTX 9863, 10071
}
VTX 10073, 0, 0
{
COORD (2080,1220)
}
BUS 10074, 0, 0
{
NET 12776
VTX 10071, 10073
}
VTX 10075, 0, 0
{
COORD (1340,1220)
}
BUS 10076, 0, 0
{
NET 12776
VTX 10073, 10075
VARIABLES
{
#NAMED="1"
}
}
VTX 10077, 0, 0
{
COORD (1340,1240)
}
BUS 10078, 0, 0
{
NET 12776
VTX 10075, 10077
}
VTX 10079, 0, 0
{
COORD (1010,1240)
}
BUS 10080, 0, 0
{
NET 12776
VTX 10077, 10079
}
VTX 10081, 0, 0
{
COORD (1010,1140)
}
BUS 10082, 0, 0
{
NET 12776
VTX 10079, 10081
}
BUS 10083, 0, 0
{
NET 12776
VTX 10081, 9864
}
VTX 10084, 0, 0
{
COORD (470,580)
}
BUS 10085, 0, 0
{
NET 1936
VTX 9865, 10084
}
VTX 10086, 0, 0
{
COORD (470,660)
}
BUS 10087, 0, 0
{
NET 1936
VTX 10084, 10086
}
BUS 10088, 0, 0
{
NET 1936
VTX 10086, 12686
}
VTX 10094, 0, 0
{
COORD (1920,880)
}
BUS 10095, 0, 0
{
NET 872
VTX 9868, 10094
}
VTX 10096, 0, 0
{
COORD (1920,1200)
}
BUS 10097, 0, 0
{
NET 872
VTX 10094, 10096
}
VTX 10098, 0, 0
{
COORD (1560,1200)
}
BUS 10099, 0, 0
{
NET 872
VTX 10096, 10098
}
BUS 10100, 0, 0
{
NET 872
VTX 10098, 9869
VARIABLES
{
#NAMED="1"
}
}
VTX 10101, 0, 0
{
COORD (1560,1420)
}
BUS 10102, 0, 0
{
NET 872
VTX 9869, 10101
VARIABLES
{
#NAMED="1"
}
}
BUS 10103, 0, 0
{
NET 872
VTX 10101, 9870
}
VTX 10111, 0, 0
{
COORD (1400,1300)
}
BUS 10112, 0, 0
{
NET 872
VTX 9869, 10111
}
VTX 10113, 0, 0
{
COORD (1400,1000)
}
BUS 10114, 0, 0
{
NET 872
VTX 10111, 10113
}
VTX 10115, 0, 0
{
COORD (750,1000)
}
BUS 10116, 0, 0
{
NET 872
VTX 10113, 10115
}
VTX 10117, 0, 0
{
COORD (750,900)
}
BUS 10118, 0, 0
{
NET 872
VTX 10115, 10117
}
BUS 10119, 0, 0
{
NET 872
VTX 10117, 9873
}
VTX 10120, 0, 0
{
COORD (1020,1680)
}
WIRE 10121, 0, 0
{
NET 1106
VTX 9874, 10120
}
VTX 10122, 0, 0
{
COORD (1020,1260)
}
WIRE 10123, 0, 0
{
NET 1106
VTX 10120, 10122
VARIABLES
{
#NAMED="1"
}
}
VTX 10124, 0, 0
{
COORD (700,1260)
}
WIRE 10125, 0, 0
{
NET 1106
VTX 10122, 10124
}
VTX 10126, 0, 0
{
COORD (700,1100)
}
WIRE 10127, 0, 0
{
NET 1106
VTX 10124, 10126
}
VTX 10128, 0, 0
{
COORD (740,1100)
}
WIRE 10129, 0, 0
{
NET 1106
VTX 10126, 10128
}
VTX 10130, 0, 0
{
COORD (740,940)
}
WIRE 10131, 0, 0
{
NET 1106
VTX 10128, 10130
}
WIRE 10132, 0, 0
{
NET 1106
VTX 10130, 9875
}
BUS 10137, 0, 0
{
NET 1168
VTX 9879, 9871
}
VTX 10138, 0, 0
{
COORD (380,1360)
}
BUS 10139, 0, 0
{
NET 1168
VTX 9880, 10138
VARIABLES
{
#NAMED="1"
}
}
BUS 10140, 0, 0
{
NET 1168
VTX 10138, 9881
}
BUS 10141, 0, 0
{
NET 1168
VTX 9881, 9871
}
BUS 10142, 0, 0
{
NET 1168
VTX 9882, 9881
}
BUS 10143, 0, 0
{
NET 1168
VTX 9883, 9880
VARIABLES
{
#NAMED="1"
}
}
BUS 10144, 0, 0
{
NET 1168
VTX 9880, 9884
}
VTX 10145, 0, 0
{
COORD (1460,1920)
}
BUS 10146, 0, 0
{
NET 1845
VTX 9885, 10145
}
VTX 10147, 0, 0
{
COORD (1460,1880)
}
BUS 10148, 0, 0
{
NET 1845
VTX 10145, 10147
}
BUS 10149, 0, 0
{
NET 1845
VTX 10147, 9886
VARIABLES
{
#NAMED="1"
}
}
VTX 10150, 0, 0
{
COORD (1640,1760)
}
BUS 10151, 0, 0
{
NET 1858
VTX 9887, 10150
}
VTX 10152, 0, 0
{
COORD (2120,1760)
}
BUS 10153, 0, 0
{
NET 1858
VTX 10150, 10152
VARIABLES
{
#NAMED="1"
}
}
VTX 10154, 0, 0
{
COORD (2120,1300)
}
BUS 10155, 0, 0
{
NET 1858
VTX 10152, 10154
}
BUS 10156, 0, 0
{
NET 1858
VTX 10154, 9888
}
VTX 10169, 0, 0
{
COORD (1040,1640)
}
BUS 10170, 0, 0
{
NET 1460
VTX 9897, 10169
}
VTX 10171, 0, 0
{
COORD (1040,1300)
}
BUS 10172, 0, 0
{
NET 1460
VTX 10169, 10171
VARIABLES
{
#NAMED="1"
}
}
VTX 10173, 0, 0
{
COORD (680,1300)
}
BUS 10174, 0, 0
{
NET 1460
VTX 10171, 10173
}
VTX 10175, 0, 0
{
COORD (680,1160)
}
BUS 10176, 0, 0
{
NET 1460
VTX 10173, 10175
}
VTX 10177, 0, 0
{
COORD (340,1160)
}
BUS 10178, 0, 0
{
NET 1460
VTX 10175, 10177
}
VTX 10179, 0, 0
{
COORD (340,540)
}
BUS 10180, 0, 0
{
NET 1460
VTX 10177, 10179
}
BUS 10181, 0, 0
{
NET 1460
VTX 10179, 9898
}
VTX 10212, 0, 0
{
COORD (640,1240)
}
BUS 10213, 0, 0
{
NET 1443
VTX 9907, 10212
}
VTX 10214, 0, 0
{
COORD (640,1300)
}
BUS 10215, 0, 0
{
NET 1443
VTX 10212, 10214
}
VTX 10216, 0, 0
{
COORD (300,1300)
}
BUS 10217, 0, 0
{
NET 1443
VTX 10214, 10216
VARIABLES
{
#NAMED="1"
}
}
VTX 10218, 0, 0
{
COORD (300,1580)
}
BUS 10219, 0, 0
{
NET 1443
VTX 10216, 10218
}
BUS 10220, 0, 0
{
NET 1443
VTX 10218, 9908
}
BUS 10221, 0, 0
{
NET 1168
VTX 9884, 9909
}
VTX 10222, 0, 0
{
COORD (280,1920)
}
BUS 10223, 0, 0
{
NET 1935
VTX 9906, 10222
}
BUS 10224, 0, 0
{
NET 1935
VTX 10222, 9910
}
WIRE 10225, 0, 0
{
NET 4576
VTX 9911, 9912
}
WIRE 10226, 0, 0
{
NET 4576
VTX 9913, 9914
}
VTX 10227, 0, 0
{
COORD (200,1840)
}
WIRE 10228, 0, 0
{
NET 4576
VTX 10227, 9915
}
WIRE 10229, 0, 0
{
NET 4576
VTX 10227, 9916
}
WIRE 10230, 0, 0
{
NET 4576
VTX 9916, 9914
}
VTX 10231, 0, 0
{
COORD (620,1920)
}
WIRE 10232, 0, 0
{
NET 4576
VTX 9917, 10231
}
VTX 10233, 0, 0
{
COORD (620,1660)
}
WIRE 10234, 0, 0
{
NET 4576
VTX 10231, 10233
}
WIRE 10235, 0, 0
{
NET 4576
VTX 10233, 9916
}
WIRE 10236, 0, 0
{
NET 4576
VTX 9918, 9919
}
WIRE 10237, 0, 0
{
NET 4576
VTX 9919, 9920
}
WIRE 10238, 0, 0
{
NET 4576
VTX 9920, 9912
}
WIRE 10239, 0, 0
{
NET 4576
VTX 9914, 9921
}
WIRE 10240, 0, 0
{
NET 4576
VTX 9921, 9918
}
VTX 10241, 0, 0
{
COORD (1060,1380)
}
WIRE 10242, 0, 0
{
NET 4576
VTX 9922, 10241
}
VTX 10243, 0, 0
{
COORD (1060,1280)
}
WIRE 10244, 0, 0
{
NET 4576
VTX 10241, 10243
}
VTX 10245, 0, 0
{
COORD (620,1280)
}
WIRE 10246, 0, 0
{
NET 4576
VTX 10243, 10245
}
VTX 10247, 0, 0
{
COORD (620,1340)
}
WIRE 10248, 0, 0
{
NET 4576
VTX 10245, 10247
}
WIRE 10249, 0, 0
{
NET 4576
VTX 10247, 9921
}
VTX 10250, 0, 0
{
COORD (750,1060)
}
WIRE 10251, 0, 0
{
NET 4576
VTX 9923, 10250
}
VTX 10252, 0, 0
{
COORD (750,1080)
}
WIRE 10253, 0, 0
{
NET 4576
VTX 10250, 10252
}
WIRE 10254, 0, 0
{
NET 4576
VTX 10252, 9918
}
WIRE 10255, 0, 0
{
NET 4576
VTX 9912, 9924
}
VTX 10288, 0, 0
{
COORD (140,1500)
}
WIRE 10289, 0, 0
{
NET 12889
VTX 9936, 10288
}
WIRE 10290, 0, 0
{
NET 12889
VTX 10288, 9937
}
WIRE 10291, 0, 0
{
NET 12889
VTX 9936, 9938
}
WIRE 10297, 0, 0
{
NET 12889
VTX 9940, 9941
}
WIRE 10298, 0, 0
{
NET 12889
VTX 9941, 9936
}
VTX 10299, 0, 0
{
COORD (560,1960)
}
WIRE 10300, 0, 0
{
NET 12889
VTX 9942, 10299
}
VTX 10301, 0, 0
{
COORD (560,1640)
}
WIRE 10302, 0, 0
{
NET 12889
VTX 10299, 10301
}
VTX 10303, 0, 0
{
COORD (320,1640)
}
WIRE 10304, 0, 0
{
NET 12889
VTX 10301, 10303
}
WIRE 10305, 0, 0
{
NET 12889
VTX 10303, 9943
}
WIRE 10306, 0, 0
{
NET 12889
VTX 9944, 9942
}
WIRE 10307, 0, 0
{
NET 12889
VTX 9945, 11537
}
VTX 10308, 0, 0
{
COORD (1640,2120)
}
BUS 10309, 0, 0
{
NET 1858
VTX 9887, 10308
}
BUS 10310, 0, 0
{
NET 1858
VTX 10308, 9946
}
BUS 10311, 0, 0
{
NET 1858
VTX 9947, 9887
}
BUS 10312, 0, 0
{
NET 1977
VTX 9948, 9949
VARIABLES
{
#NAMED="1"
}
}
VTX 10313, 0, 0
{
COORD (1340,2080)
}
BUS 10314, 0, 0
{
NET 1977
VTX 9950, 10313
}
VTX 10315, 0, 0
{
COORD (1340,2100)
}
BUS 10316, 0, 0
{
NET 1977
VTX 10313, 10315
}
VTX 10317, 0, 0
{
COORD (1100,2100)
}
BUS 10318, 0, 0
{
NET 1977
VTX 10315, 10317
}
BUS 10319, 0, 0
{
NET 1977
VTX 10317, 9948
}
VTX 10325, 0, 0
{
COORD (980,1400)
}
WIRE 10326, 0, 0
{
NET 948
VTX 9953, 10325
}
VTX 10327, 0, 0
{
COORD (980,1240)
}
WIRE 10328, 0, 0
{
NET 948
VTX 10325, 10327
VARIABLES
{
#NAMED="1"
}
}
VTX 10329, 0, 0
{
COORD (720,1240)
}
WIRE 10330, 0, 0
{
NET 948
VTX 10327, 10329
}
VTX 10331, 0, 0
{
COORD (720,1120)
}
WIRE 10332, 0, 0
{
NET 948
VTX 10329, 10331
}
VTX 10333, 0, 0
{
COORD (320,1120)
}
WIRE 10334, 0, 0
{
NET 948
VTX 10331, 10333
}
VTX 10335, 0, 0
{
COORD (320,340)
}
WIRE 10336, 0, 0
{
NET 948
VTX 10333, 10335
}
WIRE 10337, 0, 0
{
NET 948
VTX 10335, 9954
}
VTX 10338, 0, 0
{
COORD (950,220)
}
WIRE 10339, 0, 0
{
NET 4307
VTX 9955, 10338
}
VTX 10340, 0, 0
{
COORD (950,810)
}
WIRE 10341, 0, 0
{
NET 4307
VTX 10338, 10340
VARIABLES
{
#NAMED="1"
}
}
VTX 10342, 0, 0
{
COORD (1015,810)
}
WIRE 10343, 0, 0
{
NET 4307
VTX 10340, 10342
}
VTX 10344, 0, 0
{
COORD (1015,1100)
}
WIRE 10345, 0, 0
{
NET 4307
VTX 10342, 10344
}
WIRE 10346, 0, 0
{
NET 4307
VTX 10344, 9956
}
VTX 10347, 0, 0
{
COORD (1000,1360)
}
WIRE 10348, 0, 0
{
NET 935
VTX 9957, 10347
}
VTX 10349, 0, 0
{
COORD (1000,1040)
}
WIRE 10350, 0, 0
{
NET 935
VTX 10347, 10349
}
VTX 10351, 0, 0
{
COORD (1360,1040)
}
WIRE 10352, 0, 0
{
NET 935
VTX 10349, 10351
}
VTX 10353, 0, 0
{
COORD (1360,260)
}
WIRE 10354, 0, 0
{
NET 935
VTX 10351, 10353
VARIABLES
{
#NAMED="1"
}
}
VTX 10355, 0, 0
{
COORD (1090,260)
}
WIRE 10356, 0, 0
{
NET 935
VTX 10353, 10355
}
VTX 10357, 0, 0
{
COORD (1090,200)
}
WIRE 10358, 0, 0
{
NET 935
VTX 10355, 10357
}
WIRE 10359, 0, 0
{
NET 935
VTX 10357, 9958
}
VTX 10360, 0, 0
{
COORD (560,1460)
}
BUS 10361, 0, 0
{
NET 1442
VTX 9959, 10360
}
VTX 10362, 0, 0
{
COORD (560,1380)
}
BUS 10363, 0, 0
{
NET 1442
VTX 10360, 10362
}
VTX 10364, 0, 0
{
COORD (360,1380)
}
BUS 10365, 0, 0
{
NET 1442
VTX 10362, 10364
}
VTX 10366, 0, 0
{
COORD (360,800)
}
BUS 10367, 0, 0
{
NET 1442
VTX 10364, 10366
}
VTX 10368, 0, 0
{
COORD (1020,800)
}
BUS 10369, 0, 0
{
NET 1442
VTX 10366, 10368
VARIABLES
{
#NAMED="1"
}
}
VTX 10370, 0, 0
{
COORD (1020,840)
}
BUS 10371, 0, 0
{
NET 1442
VTX 10368, 10370
}
BUS 10372, 0, 0
{
NET 1442
VTX 10370, 9960
}
BUS 10373, 0, 0
{
NET 139
VTX 9961, 9962
VARIABLES
{
#NAMED="1"
}
}
VTX 10374, 0, 0
{
COORD (1010,860)
}
BUS 10375, 0, 0
{
NET 1929
VTX 9963, 10374
}
VTX 10376, 0, 0
{
COORD (1010,920)
}
BUS 10377, 0, 0
{
NET 1929
VTX 10374, 10376
VARIABLES
{
#NAMED="1"
}
}
BUS 10378, 0, 0
{
NET 1929
VTX 10376, 9964
}
VTX 10379, 0, 0
{
COORD (1400,80)
}
WIRE 10380, 0, 0
{
NET 4306
VTX 9965, 10379
}
VTX 10381, 0, 0
{
COORD (1400,980)
}
WIRE 10382, 0, 0
{
NET 4306
VTX 10379, 10381
VARIABLES
{
#NAMED="1"
}
}
VTX 10383, 0, 0
{
COORD (1020,980)
}
WIRE 10384, 0, 0
{
NET 4306
VTX 10381, 10383
}
VTX 10385, 0, 0
{
COORD (1020,880)
}
WIRE 10386, 0, 0
{
NET 4306
VTX 10383, 10385
}
WIRE 10387, 0, 0
{
NET 4306
VTX 10385, 9966
}
VTX 10388, 0, 0
{
COORD (200,80)
}
WIRE 10389, 0, 0
{
NET 4576
VTX 9967, 10388
}
WIRE 10390, 0, 0
{
NET 4576
VTX 10388, 9912
}
VTX 10391, 0, 0
{
COORD (660,220)
}
WIRE 10392, 0, 0
{
NET 4576
VTX 9968, 10391
}
WIRE 10393, 0, 0
{
NET 4576
VTX 10391, 9967
}
VTX 10394, 0, 0
{
COORD (640,300)
}
WIRE 10395, 0, 0
{
NET 3828
VTX 9969, 10394
}
WIRE 10396, 0, 0
{
NET 3828
VTX 10394, 9970
}
VTX 10397, 0, 0
{
COORD (640,160)
}
WIRE 10398, 0, 0
{
NET 3828
VTX 9971, 10397
}
WIRE 10399, 0, 0
{
NET 3828
VTX 10397, 9970
}
WIRE 10400, 0, 0
{
NET 3107
VTX 13307, 9972
}
WIRE 10401, 0, 0
{
NET 3107
VTX 9972, 9973
}
VTX 10402, 0, 0
{
COORD (700,260)
}
WIRE 10403, 0, 0
{
NET 3107
VTX 9974, 10402
}
VTX 10404, 0, 0
{
COORD (700,120)
}
WIRE 10405, 0, 0
{
NET 3107
VTX 10402, 10404
}
WIRE 10406, 0, 0
{
NET 3107
VTX 10404, 9972
}
VTX 10407, 0, 0
{
COORD (480,220)
}
WIRE 10408, 0, 0
{
NET 3828
VTX 9970, 10407
}
WIRE 10409, 0, 0
{
NET 3828
VTX 10407, 9975
}
VTX 10410, 0, 0
{
COORD (1360,1440)
}
BUS 10411, 0, 0
{
NET 1123
VTX 9976, 10410
VARIABLES
{
#NAMED="1"
}
}
VTX 10412, 0, 0
{
COORD (1360,1140)
}
BUS 10413, 0, 0
{
NET 1123
VTX 10410, 10412
}
VTX 10414, 0, 0
{
COORD (1480,1140)
}
BUS 10415, 0, 0
{
NET 1123
VTX 10412, 10414
}
VTX 10416, 0, 0
{
COORD (1480,1020)
}
BUS 10417, 0, 0
{
NET 1123
VTX 10414, 10416
}
VTX 10418, 0, 0
{
COORD (1960,1020)
}
BUS 10419, 0, 0
{
NET 1123
VTX 10416, 10418
}
VTX 10420, 0, 0
{
COORD (1960,980)
}
BUS 10421, 0, 0
{
NET 1123
VTX 10418, 10420
}
BUS 10422, 0, 0
{
NET 1123
VTX 10420, 9977
}
VTX 10436, 0, 0
{
COORD (2180,860)
}
BUS 10437, 0, 0
{
NET 12187
VTX 9980, 10436
}
VTX 10438, 0, 0
{
COORD (2180,1040)
}
BUS 10439, 0, 0
{
NET 12187
VTX 10436, 10438
VARIABLES
{
#NAMED="1"
}
}
VTX 10440, 0, 0
{
COORD (1600,1040)
}
BUS 10441, 0, 0
{
NET 12187
VTX 10438, 10440
}
VTX 10442, 0, 0
{
COORD (1600,960)
}
BUS 10443, 0, 0
{
NET 12187
VTX 10440, 10442
}
BUS 10444, 0, 0
{
NET 12187
VTX 10442, 9981
}
WIRE 10445, 0, 0
{
NET 4576
VTX 9982, 9983
}
WIRE 10446, 0, 0
{
NET 4576
VTX 9983, 9967
}
VTX 10447, 0, 0
{
COORD (1920,860)
}
WIRE 10448, 0, 0
{
NET 4576
VTX 9984, 10447
}
VTX 10449, 0, 0
{
COORD (1920,660)
}
WIRE 10450, 0, 0
{
NET 4576
VTX 10447, 10449
}
VTX 10451, 0, 0
{
COORD (1420,660)
}
WIRE 10452, 0, 0
{
NET 4576
VTX 10449, 10451
}
VTX 10453, 0, 0
{
COORD (1420,280)
}
WIRE 10454, 0, 0
{
NET 4576
VTX 10451, 10453
}
VTX 10455, 0, 0
{
COORD (1080,280)
}
WIRE 10456, 0, 0
{
NET 4576
VTX 10453, 10455
}
WIRE 10457, 0, 0
{
NET 4576
VTX 10455, 9983
}
WIRE 10458, 0, 0
{
NET 3107
VTX 9985, 11943
}
WIRE 10464, 0, 0
{
NET 3107
VTX 12356, 9988
}
VTX 10472, 0, 0
{
COORD (1460,1480)
}
BUS 10473, 0, 0
{
NET 1023
VTX 9990, 10472
}
VTX 10474, 0, 0
{
COORD (1460,620)
}
BUS 10475, 0, 0
{
NET 1023
VTX 10472, 10474
}
VTX 10476, 0, 0
{
COORD (1640,620)
}
BUS 10477, 0, 0
{
NET 1023
VTX 10474, 10476
VARIABLES
{
#NAMED="1"
}
}
VTX 10478, 0, 0
{
COORD (1640,540)
}
BUS 10479, 0, 0
{
NET 1023
VTX 10476, 10478
}
BUS 10480, 0, 0
{
NET 1023
VTX 10478, 9991
}
VTX 10481, 0, 0
{
COORD (1880,420)
}
BUS 10482, 0, 0
{
NET 5229
VTX 9992, 10481
}
VTX 10483, 0, 0
{
COORD (1880,560)
}
BUS 10484, 0, 0
{
NET 5229
VTX 10481, 10483
VARIABLES
{
#NAMED="1"
}
}
BUS 10485, 0, 0
{
NET 5229
VTX 10483, 9993
}
VTX 10486, 0, 0
{
COORD (1440,420)
}
WIRE 10487, 0, 0
{
NET 4576
VTX 9994, 10486
}
VTX 10488, 0, 0
{
COORD (1440,20)
}
WIRE 10489, 0, 0
{
NET 4576
VTX 10486, 10488
}
VTX 10490, 0, 0
{
COORD (1080,20)
}
WIRE 10491, 0, 0
{
NET 4576
VTX 10488, 10490
}
WIRE 10492, 0, 0
{
NET 4576
VTX 10490, 9983
}
VTX 10497, 0, 0
{
COORD (1360,1660)
}
WIRE 10498, 0, 0
{
NET 4335
VTX 9996, 10497
VARIABLES
{
#NAMED="1"
}
}
VTX 10499, 0, 0
{
COORD (1360,1680)
}
WIRE 10500, 0, 0
{
NET 4335
VTX 10497, 10499
}
WIRE 10501, 0, 0
{
NET 4335
VTX 10499, 9997
}
WIRE 10502, 0, 0
{
NET 4576
VTX 9998, 9922
}
VTX 10503, 0, 0
{
COORD (1120,1680)
}
WIRE 10504, 0, 0
{
NET 4576
VTX 9999, 10503
}
WIRE 10505, 0, 0
{
NET 4576
VTX 10503, 9922
}
VTX 10527, 0, 0
{
COORD (1080,1520)
}
WIRE 10528, 0, 0
{
NET 1076
VTX 10004, 10527
VARIABLES
{
#NAMED="1"
}
}
VTX 10529, 0, 0
{
COORD (1080,2300)
}
WIRE 10530, 0, 0
{
NET 1076
VTX 10527, 10529
}
WIRE 10531, 0, 0
{
NET 1076
VTX 10529, 10005
}
WIRE 10532, 0, 0
{
NET 4576
VTX 10006, 10007
}
WIRE 10533, 0, 0
{
NET 4576
VTX 10007, 9920
}
VTX 10534, 0, 0
{
COORD (1380,2180)
}
WIRE 10535, 0, 0
{
NET 4576
VTX 10008, 10534
}
VTX 10536, 0, 0
{
COORD (1380,1940)
}
WIRE 10537, 0, 0
{
NET 4576
VTX 10534, 10536
}
VTX 10538, 0, 0
{
COORD (1500,1940)
}
WIRE 10539, 0, 0
{
NET 4576
VTX 10536, 10538
}
VTX 10540, 0, 0
{
COORD (1500,740)
}
WIRE 10541, 0, 0
{
NET 4576
VTX 10538, 10540
}
VTX 10542, 0, 0
{
COORD (1340,740)
}
WIRE 10543, 0, 0
{
NET 4576
VTX 10540, 10542
}
VTX 10544, 0, 0
{
COORD (1340,760)
}
WIRE 10545, 0, 0
{
NET 4576
VTX 10542, 10544
}
VTX 10546, 0, 0
{
COORD (680,760)
}
WIRE 10547, 0, 0
{
NET 4576
VTX 10544, 10546
}
WIRE 10548, 0, 0
{
NET 4576
VTX 10546, 10007
}
WIRE 10549, 0, 0
{
NET 3107
VTX 11912, 9987
}
BUS 10550, 0, 0
{
NET 1168
VTX 9884, 10009
}
VTX 10551, 0, 0
{
COORD (1100,1720)
}
WIRE 10552, 0, 0
{
NET 1089
VTX 10010, 10551
VARIABLES
{
#NAMED="1"
}
}
VTX 10553, 0, 0
{
COORD (1100,1800)
}
WIRE 10554, 0, 0
{
NET 1089
VTX 10551, 10553
}
WIRE 10555, 0, 0
{
NET 1089
VTX 10553, 10011
}
VTX 10569, 0, 0
{
COORD (1040,2040)
}
BUS 10570, 0, 0
{
NET 1977
VTX 9948, 10569
VARIABLES
{
#NAMED="1"
}
}
VTX 10571, 0, 0
{
COORD (1040,1840)
}
BUS 10572, 0, 0
{
NET 1977
VTX 10569, 10571
}
BUS 10573, 0, 0
{
NET 1977
VTX 10571, 10014
}
VTX 10574, 0, 0
{
COORD (1140,1620)
}
VTX 10576, 0, 0
{
COORD (1140,2020)
}
WIRE 10577, 0, 0
{
NET 4563
VTX 10574, 10576
}
WIRE 10578, 0, 0
{
NET 4563
VTX 10576, 10016
}
VTX 10579, 0, 0
{
COORD (1000,1560)
}
WIRE 10580, 0, 0
{
NET 1059
VTX 10017, 10579
VARIABLES
{
#NAMED="1"
}
}
VTX 10581, 0, 0
{
COORD (1000,1760)
}
WIRE 10582, 0, 0
{
NET 1059
VTX 10579, 10581
}
VTX 10583, 0, 0
{
COORD (1040,1760)
}
WIRE 10584, 0, 0
{
NET 1059
VTX 10581, 10583
}
VTX 10585, 0, 0
{
COORD (1040,1820)
}
WIRE 10586, 0, 0
{
NET 1059
VTX 10583, 10585
}
VTX 10587, 0, 0
{
COORD (1100,1820)
}
WIRE 10588, 0, 0
{
NET 1059
VTX 10585, 10587
}
VTX 10589, 0, 0
{
COORD (1100,1940)
}
WIRE 10590, 0, 0
{
NET 1059
VTX 10587, 10589
}
VTX 10591, 0, 0
{
COORD (780,1940)
}
WIRE 10592, 0, 0
{
NET 1059
VTX 10589, 10591
}
VTX 10593, 0, 0
{
COORD (780,2140)
}
WIRE 10594, 0, 0
{
NET 1059
VTX 10591, 10593
}
WIRE 10595, 0, 0
{
NET 1059
VTX 10593, 10018
}
WIRE 10596, 0, 0
{
NET 4576
VTX 10019, 9917
}
VTX 10597, 0, 0
{
COORD (720,2020)
}
WIRE 10598, 0, 0
{
NET 4576
VTX 10020, 10597
}
WIRE 10599, 0, 0
{
NET 4576
VTX 10597, 9917
}
VTX 10617, 0, 0
{
COORD (1940,940)
}
WIRE 10618, 0, 0
{
NET 3990
VTX 10022, 10617
}
WIRE 10619, 0, 0
{
NET 3990
VTX 10617, 10023
}
WIRE 10644, 0, 0
{
NET 4576
VTX 9919, 10029
}
VTX 10648, 0, 0
{
COORD (260,1000)
}
WIRE 10649, 0, 0
{
NET 12889
VTX 9938, 10648
}
BUS 10651, 0, 0
{
NET 1935
VTX 9906, 10032
}
WIRE 10661, 0, 0
{
NET 4482
VTX 10036, 10037
}
VTX 10662, 0, 0
{
COORD (1120,1760)
}
WIRE 10663, 0, 0
{
NET 4482
VTX 10038, 10662
}
WIRE 10664, 0, 0
{
NET 4482
VTX 10662, 10036
}
WIRE 10665, 0, 0
{
NET 12889
VTX 9943, 9941
}
WIRE 10666, 0, 0
{
NET 12889
VTX 10039, 9943
}
VTX 10668, 0, 0
{
COORD (320,1960)
}
VTX 10669, 0, 0
{
COORD (280,1940)
}
VTX 10670, 0, 0
{
COORD (320,1880)
}
VTX 10671, 0, 0
{
COORD (280,1880)
}
VTX 10672, 0, 0
{
COORD (320,2000)
}
VTX 10673, 0, 0
{
COORD (280,2000)
}
VTX 10674, 0, 0
{
COORD (300,1960)
}
WIRE 10675, 0, 0
{
NET 3179
VTX 10674, 10668
}
VTX 10676, 0, 0
{
COORD (300,1940)
}
WIRE 10677, 0, 0
{
NET 3179
VTX 10674, 10676
}
WIRE 10678, 0, 0
{
NET 3179
VTX 10676, 10669
}
BUS 10679, 0, 0
{
NET 3171
VTX 10671, 10670
}
BUS 10680, 0, 0
{
NET 3175
VTX 10673, 10672
}
VTX 10868, 0, 0
{
COORD (2040,1420)
}
VTX 10869, 0, 0
{
COORD (2180,1420)
}
VTX 10870, 0, 0
{
COORD (2040,1460)
}
VTX 10871, 0, 0
{
COORD (2180,1460)
}
VTX 10872, 0, 0
{
COORD (2040,1500)
}
VTX 10873, 0, 0
{
COORD (2180,1500)
}
BUS 10876, 0, 0
{
NET 2053
VTX 10868, 10869
}
BUS 10877, 0, 0
{
NET 2000
VTX 10870, 10871
}
BUS 10878, 0, 0
{
NET 2004
VTX 10872, 10873
}
VTX 10977, 0, 0
{
COORD (800,2060)
}
VTX 10992, 0, 0
{
COORD (760,2060)
}
WIRE 10993, 0, 0
{
NET 3107
VTX 10977, 10992
}
VTX 10994, 0, 0
{
COORD (760,2200)
}
WIRE 10995, 0, 0
{
NET 3107
VTX 10992, 10994
}
VTX 10998, 0, 0
{
COORD (1520,700)
}
WIRE 10999, 0, 0
{
NET 3107
VTX 9987, 10998
}
VTX 11000, 0, 0
{
COORD (1520,1960)
}
VTX 11002, 0, 0
{
COORD (1360,1960)
}
WIRE 11003, 0, 0
{
NET 3107
VTX 11000, 11002
}
WIRE 11004, 0, 0
{
NET 3107
VTX 11002, 12486
}
VTX 11154, 0, 0
{
COORD (1600,1460)
}
VTX 11155, 0, 0
{
COORD (2180,1580)
}
VTX 11156, 0, 0
{
COORD (1530,1460)
}
BUS 11157, 0, 0
{
NET 3140
VTX 11154, 11156
}
VTX 11158, 0, 0
{
COORD (1530,1800)
}
BUS 11159, 0, 0
{
NET 3140
VTX 11156, 11158
}
VTX 11160, 0, 0
{
COORD (2140,1800)
}
BUS 11161, 0, 0
{
NET 3140
VTX 11158, 11160
}
VTX 11162, 0, 0
{
COORD (2140,1580)
}
BUS 11163, 0, 0
{
NET 3140
VTX 11160, 11162
}
BUS 11164, 0, 0
{
NET 3140
VTX 11162, 11155
}
VTX 11188, 0, 0
{
COORD (1900,600)
}
WIRE 11189, 0, 0
{
NET 133
VTX 11188, 9854
VARIABLES
{
#NAMED="1"
}
}
VTX 11274, 0, 0
{
COORD (1600,1500)
}
VTX 11275, 0, 0
{
COORD (1960,2080)
}
VTX 11276, 0, 0
{
COORD (1600,1580)
}
VTX 11277, 0, 0
{
COORD (1960,1880)
}
VTX 11278, 0, 0
{
COORD (1560,1500)
}
BUS 11279, 0, 0
{
NET 3427
VTX 11274, 11278
}
VTX 11280, 0, 0
{
COORD (1560,1980)
}
BUS 11281, 0, 0
{
NET 3427
VTX 11278, 11280
}
VTX 11282, 0, 0
{
COORD (1980,1980)
}
BUS 11283, 0, 0
{
NET 3427
VTX 11280, 11282
VARIABLES
{
#NAMED="1"
}
}
VTX 11284, 0, 0
{
COORD (1980,2080)
}
BUS 11285, 0, 0
{
NET 3427
VTX 11282, 11284
}
BUS 11286, 0, 0
{
NET 3427
VTX 11284, 11275
}
VTX 11287, 0, 0
{
COORD (1580,1580)
}
BUS 11288, 0, 0
{
NET 1880
VTX 11276, 11287
}
VTX 11289, 0, 0
{
COORD (1580,1780)
}
BUS 11290, 0, 0
{
NET 1880
VTX 11287, 11289
}
VTX 11291, 0, 0
{
COORD (1980,1780)
}
BUS 11292, 0, 0
{
NET 1880
VTX 11289, 11291
VARIABLES
{
#NAMED="1"
}
}
VTX 11293, 0, 0
{
COORD (1980,1880)
}
BUS 11294, 0, 0
{
NET 1880
VTX 11291, 11293
}
BUS 11295, 0, 0
{
NET 1880
VTX 11293, 11277
}
VTX 11332, 0, 0
{
COORD (1020,1180)
}
VTX 11335, 0, 0
{
COORD (980,1180)
}
BUS 11336, 0, 0
{
NET 1250
VTX 11339, 11335
VARIABLES
{
#NAMED="1"
}
}
BUS 11337, 0, 0
{
NET 1250
VTX 11335, 11332
}
VTX 11339, 0, 0
{
COORD (980,1060)
}
BUS 11340, 0, 0
{
NET 1250
VTX 9876, 11339
}
VTX 11537, 0, 0
{
COORD (760,1140)
}
WIRE 11538, 0, 0
{
NET 12889
VTX 9939, 11537
}
WIRE 11539, 0, 0
{
NET 12889
VTX 11537, 9938
}
VTX 11765, 0, 0
{
COORD (1540,1620)
}
VTX 11766, 0, 0
{
COORD (2180,1660)
}
WIRE 11767, 0, 0
{
NET 4563
VTX 10015, 11765
VARIABLES
{
#NAMED="1"
}
}
WIRE 11768, 0, 0
{
NET 4563
VTX 11765, 10574
VARIABLES
{
#NAMED="1"
}
}
VTX 11770, 0, 0
{
COORD (1540,1820)
}
WIRE 11771, 0, 0
{
NET 4563
VTX 11765, 11770
}
VTX 11772, 0, 0
{
COORD (2180,1820)
}
WIRE 11773, 0, 0
{
NET 4563
VTX 11770, 11772
}
WIRE 11774, 0, 0
{
NET 4563
VTX 11772, 11766
}
INSTANCE 11775, 0, 0
{
VARIABLES
{
#COMPONENT="Output"
#LIBRARY="#terminals"
#REFERENCE="exp_wren"
#SYMBOL="Output"
}
COORD (2180,1660)
VERTEXES ( (2,11766) )
}
TEXT 11776, 0, 0
{
TEXT "$#REFERENCE"
RECT (2232,1643,2370,1678)
ALIGN 4
MARGINS (1,1)
PARENT 11775
}
VTX 11883, 0, 0
{
COORD (1600,1540)
}
VTX 11885, 0, 0
{
COORD (1380,1540)
}
WIRE 11886, 0, 0
{
NET 12897
VTX 11883, 11885
}
VTX 11887, 0, 0
{
COORD (1380,1860)
}
WIRE 11888, 0, 0
{
NET 12897
VTX 11885, 11887
}
VTX 11889, 0, 0
{
COORD (1060,1860)
}
WIRE 11890, 0, 0
{
NET 12897
VTX 11887, 11889
}
VTX 11891, 0, 0
{
COORD (1060,1780)
}
WIRE 11892, 0, 0
{
NET 12897
VTX 11889, 11891
}
VTX 11893, 0, 0
{
COORD (240,1780)
}
WIRE 11894, 0, 0
{
NET 12897
VTX 11891, 11893
}
VTX 11898, 0, 0
{
COORD (1660,500)
}
VTX 11899, 0, 0
{
COORD (1560,520)
}
VTX 11900, 0, 0
{
COORD (1560,500)
}
WIRE 11901, 0, 0
{
NET 4214
VTX 11898, 11900
}
WIRE 11902, 0, 0
{
NET 4214
VTX 11900, 11899
}
VTX 11903, 0, 0
{
COORD (1160,1720)
}
VTX 11904, 0, 0
{
COORD (1150,1720)
}
WIRE 11905, 0, 0
{
NET 3107
VTX 11903, 11904
}
VTX 11906, 0, 0
{
COORD (1150,1500)
}
WIRE 11907, 0, 0
{
NET 3107
VTX 11904, 11906
}
VTX 11908, 0, 0
{
COORD (1420,1500)
}
WIRE 11909, 0, 0
{
NET 3107
VTX 11906, 11908
}
VTX 11910, 0, 0
{
COORD (1420,760)
}
WIRE 11911, 0, 0
{
NET 3107
VTX 11908, 11910
}
VTX 11912, 0, 0
{
COORD (1960,760)
}
WIRE 11913, 0, 0
{
NET 3107
VTX 11910, 11912
}
WIRE 11915, 0, 0
{
NET 3107
VTX 11912, 11943
}
VTX 11943, 0, 0
{
COORD (1960,900)
}
VTX 11945, 0, 0
{
COORD (800,2100)
}
VTX 11946, 0, 0
{
COORD (1520,1000)
}
WIRE 11947, 0, 0
{
NET 3107
VTX 10998, 11946
}
WIRE 11948, 0, 0
{
NET 3107
VTX 11946, 11000
}
VTX 11949, 0, 0
{
COORD (790,2100)
}
WIRE 11950, 0, 0
{
NET 3107
VTX 11945, 11949
}
VTX 11951, 0, 0
{
COORD (790,1945)
}
WIRE 11952, 0, 0
{
NET 3107
VTX 11949, 11951
}
VTX 11953, 0, 0
{
COORD (1155,1945)
}
WIRE 11954, 0, 0
{
NET 3107
VTX 11951, 11953
}
VTX 11955, 0, 0
{
COORD (1155,1865)
}
WIRE 11956, 0, 0
{
NET 3107
VTX 11953, 11955
}
VTX 11957, 0, 0
{
COORD (1475,1865)
}
WIRE 11958, 0, 0
{
NET 3107
VTX 11955, 11957
}
VTX 11959, 0, 0
{
COORD (1475,1000)
}
WIRE 11960, 0, 0
{
NET 3107
VTX 11957, 11959
}
WIRE 11961, 0, 0
{
NET 3107
VTX 11959, 11946
}
VTX 12008, 0, 0
{
COORD (1600,1300)
}
VTX 12009, 0, 0
{
COORD (1580,2180)
}
VTX 12010, 0, 0
{
COORD (1590,1300)
}
WIRE 12011, 0, 0
{
NET 4417
VTX 12008, 12010
}
VTX 12012, 0, 0
{
COORD (1590,2120)
}
WIRE 12013, 0, 0
{
NET 4417
VTX 12010, 12012
VARIABLES
{
#NAMED="1"
}
}
VTX 12014, 0, 0
{
COORD (1600,2120)
}
WIRE 12015, 0, 0
{
NET 4417
VTX 12012, 12014
}
VTX 12016, 0, 0
{
COORD (1600,2180)
}
WIRE 12017, 0, 0
{
NET 4417
VTX 12014, 12016
}
WIRE 12018, 0, 0
{
NET 4417
VTX 12016, 12009
}
NET BUS 12187, 0, 0
{
VARIABLES
{
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_alu_op_r[4:0]"
#VERILOG_TYPE="wire"
}
}
VTX 12356, 0, 0
{
COORD (2120,560)
}
VTX 12417, 0, 0
{
COORD (1960,660)
}
WIRE 12418, 0, 0
{
NET 3107
VTX 9987, 12417
}
VTX 12419, 0, 0
{
COORD (2120,660)
}
WIRE 12420, 0, 0
{
NET 3107
VTX 12417, 12419
}
WIRE 12422, 0, 0
{
NET 3107
VTX 12356, 12419
}
VTX 12479, 0, 0
{
COORD (1400,2220)
}
VTX 12482, 0, 0
{
COORD (1360,2220)
}
WIRE 12483, 0, 0
{
NET 3107
VTX 12486, 12482
}
WIRE 12484, 0, 0
{
NET 3107
VTX 12482, 12479
}
VTX 12486, 0, 0
{
COORD (1360,2200)
}
WIRE 12487, 0, 0
{
NET 3107
VTX 10994, 12486
}
VTX 12587, 0, 0
{
COORD (1400,2260)
}
VTX 12588, 0, 0
{
COORD (1180,2220)
}
WIRE 12589, 0, 0
{
NET 4482
VTX 10036, 12588
}
VTX 12590, 0, 0
{
COORD (1180,2260)
}
WIRE 12591, 0, 0
{
NET 4482
VTX 12588, 12590
}
WIRE 12592, 0, 0
{
NET 4482
VTX 12590, 12587
}
VTX 12685, 0, 0
{
COORD (640,920)
}
VTX 12686, 0, 0
{
COORD (720,660)
}
VTX 12688, 0, 0
{
COORD (720,920)
}
BUS 12689, 0, 0
{
NET 1936
VTX 12686, 12688
VARIABLES
{
#NAMED="1"
}
}
BUS 12690, 0, 0
{
NET 1936
VTX 12688, 12685
}
NET BUS 12776, 0, 0
{
VARIABLES
{
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_file_o[7:0]"
#VERILOG_TYPE="wire"
}
}
NET WIRE 12889, 0, 0
WIRE 12891, 0, 0
{
NET 12889
VTX 10648, 10033
}
VTX 12892, 0, 0
{
COORD (440,960)
}
VTX 12893, 0, 0
{
COORD (240,960)
}
WIRE 12894, 0, 0
{
NET 12897
VTX 11893, 12893
}
WIRE 12896, 0, 0
{
NET 12897
VTX 12892, 12893
}
NET WIRE 12897, 0, 0
VTX 13254, 0, 0
{
COORD (2120,340)
}
WIRE 13255, 0, 0
{
NET 3107
VTX 13266, 13254
VARIABLES
{
#NAMED="1"
}
}
WIRE 13256, 0, 0
{
NET 3107
VTX 13254, 12356
VARIABLES
{
#NAMED="1"
}
}
VTX 13261, 0, 0
{
COORD (1660,460)
}
VTX 13263, 0, 0
{
COORD (1560,460)
}
WIRE 13264, 0, 0
{
NET 3107
VTX 13261, 13263
}
VTX 13266, 0, 0
{
COORD (1560,340)
}
WIRE 13270, 0, 0
{
NET 3107
VTX 13263, 13266
}
VTX 13307, 0, 0
{
COORD (1060,340)
}
WIRE 13311, 0, 0
{
NET 3107
VTX 13307, 13266
VARIABLES
{
#NAMED="1"
}
}
VTX 13405, 0, 0
{
COORD (1020,480)
}
VTX 13407, 0, 0
{
COORD (960,1600)
}
VTX 13408, 0, 0
{
COORD (1020,520)
}
VTX 13409, 0, 0
{
COORD (1020,560)
}
VTX 13410, 0, 0
{
COORD (1020,600)
}
VTX 13411, 0, 0
{
COORD (740,500)
}
VTX 13412, 0, 0
{
COORD (1020,640)
}
VTX 13413, 0, 0
{
COORD (2040,1540)
}
VTX 13414, 0, 0
{
COORD (1020,680)
}
VTX 13415, 0, 0
{
COORD (1020,440)
}
VTX 13416, 0, 0
{
COORD (1020,400)
}
VTX 13417, 0, 0
{
COORD (1000,340)
}
WIRE 13418, 0, 0
{
NET 3107
VTX 13307, 13417
}
VTX 13419, 0, 0
{
COORD (1000,480)
}
WIRE 13420, 0, 0
{
NET 3107
VTX 13417, 13419
VARIABLES
{
#NAMED="1"
}
}
WIRE 13421, 0, 0
{
NET 3107
VTX 13419, 13405
}
VTX 13433, 0, 0
{
COORD (1140,1600)
}
BUS 13434, 0, 0
{
NET 1040
VTX 13407, 13433
}
VTX 13435, 0, 0
{
COORD (1140,1460)
}
BUS 13436, 0, 0
{
NET 1040
VTX 13433, 13435
VARIABLES
{
#NAMED="1"
}
}
VTX 13437, 0, 0
{
COORD (1440,1460)
}
BUS 13438, 0, 0
{
NET 1040
VTX 13435, 13437
}
VTX 13439, 0, 0
{
COORD (1440,1120)
}
BUS 13440, 0, 0
{
NET 1040
VTX 13437, 13439
}
VTX 13441, 0, 0
{
COORD (1560,1120)
}
BUS 13442, 0, 0
{
NET 1040
VTX 13439, 13441
}
VTX 13443, 0, 0
{
COORD (1560,600)
}
BUS 13444, 0, 0
{
NET 1040
VTX 13441, 13443
}
VTX 13445, 0, 0
{
COORD (1460,600)
}
BUS 13446, 0, 0
{
NET 1040
VTX 13443, 13445
}
VTX 13447, 0, 0
{
COORD (1460,320)
}
BUS 13448, 0, 0
{
NET 1040
VTX 13445, 13447
}
VTX 13449, 0, 0
{
COORD (960,320)
}
BUS 13450, 0, 0
{
NET 1040
VTX 13447, 13449
}
VTX 13451, 0, 0
{
COORD (960,520)
}
BUS 13452, 0, 0
{
NET 1040
VTX 13449, 13451
}
BUS 13453, 0, 0
{
NET 15035
VTX 13451, 13408
VARIABLES
{
#NAMED="1"
}
}
VTX 13454, 0, 0
{
COORD (380,640)
}
BUS 13455, 0, 0
{
NET 1168
VTX 9871, 13454
}
VTX 13456, 0, 0
{
COORD (760,640)
}
BUS 13457, 0, 0
{
NET 1168
VTX 13454, 13456
}
VTX 13458, 0, 0
{
COORD (760,560)
}
BUS 13459, 0, 0
{
NET 1168
VTX 13456, 13458
}
BUS 13460, 0, 0
{
NET 1168
VTX 13458, 13409
}
VTX 13461, 0, 0
{
COORD (1000,660)
}
BUS 13462, 0, 0
{
NET 1936
VTX 12686, 13461
}
VTX 13463, 0, 0
{
COORD (1000,600)
}
BUS 13464, 0, 0
{
NET 1936
VTX 13461, 13463
}
BUS 13465, 0, 0
{
NET 1936
VTX 13463, 13410
}
VTX 13466, 0, 0
{
COORD (800,500)
}
BUS 13467, 0, 0
{
NET 1930
VTX 13411, 13466
}
VTX 13468, 0, 0
{
COORD (800,640)
}
BUS 13469, 0, 0
{
NET 1930
VTX 13466, 13468
}
BUS 13470, 0, 0
{
NET 1930
VTX 13468, 13412
VARIABLES
{
#NAMED="1"
}
}
VTX 13471, 0, 0
{
COORD (2160,1540)
}
BUS 13472, 0, 0
{
NET 801
VTX 13413, 13471
}
VTX 13473, 0, 0
{
COORD (2160,1180)
}
BUS 13474, 0, 0
{
NET 801
VTX 13471, 13473
}
VTX 13475, 0, 0
{
COORD (1540,1180)
}
BUS 13476, 0, 0
{
NET 801
VTX 13473, 13475
}
VTX 13477, 0, 0
{
COORD (1540,780)
}
BUS 13478, 0, 0
{
NET 801
VTX 13475, 13477
}
VTX 13479, 0, 0
{
COORD (1000,780)
}
BUS 13480, 0, 0
{
NET 801
VTX 13477, 13479
VARIABLES
{
#NAMED="1"
}
}
VTX 13481, 0, 0
{
COORD (1000,680)
}
BUS 13482, 0, 0
{
NET 801
VTX 13479, 13481
}
BUS 13483, 0, 0
{
NET 801
VTX 13481, 13414
}
VTX 13484, 0, 0
{
COORD (980,1020)
}
BUS 13485, 0, 0
{
NET 1250
VTX 11339, 13484
}
VTX 13486, 0, 0
{
COORD (1380,1020)
}
BUS 13487, 0, 0
{
NET 1250
VTX 13484, 13486
}
VTX 13488, 0, 0
{
COORD (1380,300)
}
BUS 13489, 0, 0
{
NET 1250
VTX 13486, 13488
}
VTX 13490, 0, 0
{
COORD (980,300)
}
BUS 13491, 0, 0
{
NET 1250
VTX 13488, 13490
}
VTX 13492, 0, 0
{
COORD (980,440)
}
BUS 13493, 0, 0
{
NET 1250
VTX 13490, 13492
}
BUS 13494, 0, 0
{
NET 1250
VTX 13492, 13415
}
VTX 13495, 0, 0
{
COORD (240,400)
}
WIRE 13497, 0, 0
{
NET 12897
VTX 13495, 13416
}
VTX 13498, 0, 0
{
COORD (1340,740)
}
VTX 13499, 0, 0
{
COORD (1300,480)
}
VTX 13500, 0, 0
{
COORD (280,740)
}
BUS 13501, 0, 0
{
NET 1935
VTX 9906, 13500
}
BUS 13502, 0, 0
{
NET 1935
VTX 13500, 13498
VARIABLES
{
#NAMED="1"
}
}
VTX 13503, 0, 0
{
COORD (1340,480)
}
BUS 13504, 0, 0
{
NET 1935
VTX 13499, 13503
}
BUS 13505, 0, 0
{
NET 1935
VTX 13503, 13498
}
WIRE 13702, 0, 0
{
NET 12897
VTX 12893, 13495
}
VTX 13703, 0, 0
{
COORD (180,400)
}
WIRE 13704, 0, 0
{
NET 12897
VTX 13495, 13703
}
NET BUS 15035, 0, 0
{
VARIABLES
{
#MDA_RECORD_TOKEN="OTHER"
#NAME="w_pc_gen_ctl[2:0]"
#VERILOG_TYPE="wire"
}
}
TEXT 15036, 0, 0
{
TEXT "$#NAME"
RECT (870,490,1110,519)
ALIGN 9
MARGINS (1,1)
PARENT 13453
}
}
}
 
PAGE ""
{
PAGEHEADER
{
PAGESIZE (2400,2400)
MARGINS (0,0,0,0)
RECT (0,0,0,0)
VARIABLES
{
#ARCHITECTURE="\\#TABLE\\"
#BLOCKTABLE_PAGE="1"
#BLOCKTABLE_TEMPL="1"
#BLOCKTABLE_VISIBLE="0"
#ENTITY="\\#TABLE\\"
#MODIFIED="1140746926"
}
}
BODY
{
TEXT 15564, 0, 0
{
PAGEALIGN 10
OUTLINE 5,1, (0,0,0)
TEXT "Created:"
RECT (1540,2286,1657,2339)
ALIGN 4
MARGINS (1,10)
COLOR (0,0,0)
FONT (12,0,0,700,0,0,0,"Arial")
}
TEXT 15565, 0, 0
{
PAGEALIGN 10
TEXT "$CREATIONDATE"
RECT (1710,2280,2380,2340)
ALIGN 4
MARGINS (1,1)
COLOR (0,0,0)
FONT (12,0,0,700,0,128,0,"Arial")
UPDATE 0
}
TEXT 15566, 0, 0
{
PAGEALIGN 10
TEXT "Title:"
RECT (1541,2344,1612,2397)
ALIGN 4
MARGINS (1,10)
COLOR (0,0,0)
FONT (12,0,0,700,0,0,0,"Arial")
}
TEXT 15567, 0, 0
{
PAGEALIGN 10
OUTLINE 5,1, (0,0,0)
TEXT "$TITLE"
RECT (1710,2340,2380,2400)
ALIGN 4
MARGINS (1,1)
COLOR (0,0,0)
FONT (12,0,0,700,0,128,0,"Arial")
UPDATE 0
}
LINE 15568, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (128,128,128)
POINTS ( (1530,2280), (2400,2280) )
FILL (1,(0,0,0),0)
}
LINE 15569, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (128,128,128)
POINTS ( (1530,2340), (2400,2340) )
FILL (1,(0,0,0),0)
}
LINE 15570, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (128,128,128)
POINTS ( (1700,2280), (1700,2400) )
}
LINE 15571, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (128,128,128)
POINTS ( (2400,2400), (2400,2140), (1530,2140), (1530,2400), (2400,2400) )
FILL (1,(0,0,0),0)
}
TEXT 15572, 0, 0
{
PAGEALIGN 10
TEXT
"(C)ALDEC. Inc\n"+
"2260 Corporate Circle\n"+
"Henderson, NV 89074"
RECT (1540,2160,1835,2261)
MARGINS (1,1)
COLOR (0,0,0)
FONT (12,0,0,700,0,0,0,"Arial")
MULTILINE
}
LINE 15573, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (128,128,128)
POINTS ( (1840,2140), (1840,2280) )
}
LINE 15574, 0, 0
{
PAGEALIGN 10
OUTLINE 0,4, (0,4,255)
POINTS ( (2016,2204), (2082,2204) )
FILL (0,(0,4,255),0)
}
LINE 15575, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (1985,2200), (1985,2200) )
FILL (0,(0,4,255),0)
}
LINE 15576, 0, 0
{
PAGEALIGN 10
OUTLINE 0,3, (0,4,255)
POINTS ( (2034,2204), (2050,2164) )
FILL (0,(0,4,255),0)
}
TEXT 15577, -4, 0
{
PAGEALIGN 10
OUTLINE 5,0, (49,101,255)
TEXT "ALDEC"
RECT (2063,2146,2361,2248)
MARGINS (1,1)
COLOR (0,4,255)
FONT (36,0,0,700,0,0,0,"Arial")
}
LINE 15578, 0, 0
{
PAGEALIGN 10
OUTLINE 0,3, (0,4,255)
POINTS ( (1976,2164), (1951,2227) )
FILL (0,(0,4,255),0)
}
BEZIER 15579, 0, 0
{
PAGEALIGN 10
OUTLINE 0,3, (0,4,255)
FILL (0,(0,4,255),0)
ORIGINS ( (1983,2190), (2016,2204), (1983,2215), (1983,2190) )
CONTROLS (( (2007,2190), (2015,2189)),( (2013,2215), (2010,2215)),( (1983,2207), (1983,2202)) )
}
LINE 15580, 0, 0
{
PAGEALIGN 10
OUTLINE 0,4, (0,4,255)
POINTS ( (1895,2211), (1983,2211) )
FILL (0,(0,4,255),0)
}
LINE 15581, 0, 0
{
PAGEALIGN 10
OUTLINE 0,4, (0,4,255)
POINTS ( (1902,2194), (1983,2194) )
FILL (0,(0,4,255),0)
}
LINE 15582, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (2088,2171), (1911,2171) )
FILL (0,(0,4,255),0)
}
LINE 15583, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (2086,2178), (1908,2178) )
FILL (0,(0,4,255),0)
}
LINE 15584, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (2100,2186), (1906,2186) )
FILL (0,(0,4,255),0)
}
LINE 15585, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (2102,2194), (1910,2194) )
FILL (0,(0,4,255),0)
}
LINE 15586, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (2015,2202), (1899,2202) )
FILL (0,(0,4,255),0)
}
LINE 15587, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (2080,2211), (1895,2211) )
FILL (0,(0,4,255),0)
}
LINE 15588, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (2073,2219), (1892,2219) )
FILL (0,(0,4,255),0)
}
TEXT 15589, 0, 0
{
PAGEALIGN 10
TEXT "The Design Verification Company"
RECT (1882,2236,2334,2270)
MARGINS (1,1)
COLOR (0,4,255)
FONT (12,0,0,700,1,0,0,"Arial")
}
LINE 15590, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (2067,2227), (1889,2227) )
FILL (0,(0,4,255),0)
}
LINE 15591, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (2090,2164), (1914,2164) )
FILL (0,(0,4,255),0)
}
}
}
 
/trunk/regs.v
0,0 → 1,12
`include "clairisc_def.h"
 
module w_reg(input [7:0]d,input clk,output reg [7:0] q,input w_wr_en);always @(posedge clk)if (w_wr_en) q<=d;endmodule
module r1_reg_clr_cls(input[`R1_LEN-1:0] r1_i,output reg[`R1_LEN-1:0] r1_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r1_o<=0;else if(cls)r1_o<=r1_o;else r1_o<=r1_i;endmodule
module r2_reg_clr_cls(input[`R2_LEN-1:0] r2_i,output reg[`R2_LEN-1:0] r2_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r2_o<=0;else if(cls)r2_o<=r2_o;else r2_o<=r2_i;endmodule
module r3_reg_clr_cls(input[`R3_LEN-1:0] r3_i,output reg[`R3_LEN-1:0] r3_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r3_o<=0;else if(cls)r3_o<=r3_o;else r3_o<=r3_i;endmodule
module r4_reg_clr_cls(input[`R4_LEN-1:0] r4_i,output reg[`R4_LEN-1:0] r4_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r4_o<=0;else if(cls)r4_o<=r4_o;else r4_o<=r4_i;endmodule
module r5_reg_clr_cls(input[`R5_LEN-1:0] r5_i,output reg[`R5_LEN-1:0] r5_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r5_o<=0;else if(cls)r5_o<=r5_o;else r5_o<=r5_i;endmodule
module r8_reg_clr_cls(input[`R8_LEN-1:0] r8_i,output reg[`R8_LEN-1:0] r8_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r8_o<=0;else if(cls)r8_o<=r8_o;else r8_o<=r8_i;endmodule
module r12_reg_clr_cls(input[`R12_LEN-1:0] r12_i,output reg[`R12_LEN-1:0] r12_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r12_o<=0;else if(cls)r12_o<=r12_o;else r12_o<=r12_i;endmodule
module r11_reg_clr_cls(input[`R11_LEN-1:0] r11_i,output reg[`R11_LEN-1:0] r11_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r11_o<=0;else if(cls)r11_o<=r11_o;else r11_o<=r11_i;endmodule
module ek_reg_clr_cls(input[11:0] ins,output reg[`R9_LEN-1:0] r9_o,input clk,input clr,input cls); wire [8:0] r9_i =ins[8:0];always@(posedge clk)if(clr) r9_o<=0;else if(cls)r9_o<=r9_o;else r9_o<=r9_i;endmodule
/trunk/decoder.v
0,0 → 1,732
`include "clairisc_def.h"
 
module decoder(
input [11:0]inst,
output reg [2:0]pc_ctl,
output reg [1:0]stack_op,
output reg alu_muxa,
output reg alu_muxb,
output reg [4:0]alu_op,
output reg men_wr,
output reg w_wr,
output reg c_wr,
output reg z_wr,
output reg [1:0]bg_op
);
always @(inst) begin
casex (inst) //synopsys parallel_case
12'b0000_0000_0000:
//REPLACE ID = NOP
//REPLACE ID = NOP
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_IGN;
alu_muxb = `MUXB_IGN;
alu_op = `ALU_NOP;
men_wr = `DIS;
w_wr = `DIS;
z_wr = `DIS;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of NOP ;
/**/
 
12'b0000_001X_XXXX:
//REPLACE ID = MOVWF
//REPLACE ID = MOVWF
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_W;
alu_muxb = `MUXB_IGN;
alu_op = `ALU_PA;
men_wr = `EN;
w_wr = `DIS;
z_wr = `DIS;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of MOVWF ;
 
12'b0000_0100_0000:
//REPLACE ID = CLRW
//REPLACE ID = CLRW
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_IGN;
alu_muxb = `MUXB_IGN;
alu_op = `ALU_ZERO;
men_wr = `DIS;
w_wr = `EN;
z_wr = `EN;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of CLRW ;
 
12'b0000_011X_XXXX:
//REPLACE ID = CLRF
//REPLACE ID = CLRF
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_IGN;
alu_muxb = `MUXB_IGN;
alu_op = `ALU_ZERO;
men_wr = `EN;
w_wr = `DIS;
z_wr = `EN;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of CLRF ;
 
12'b0000_100X_XXXX:
//REPLACE ID = SUBWF_W
//REPLACE ID = SUBWF_W
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_W;
alu_muxb = `MUXB_REG;
alu_op = `ALU_SUB;
men_wr = `DIS;
w_wr = `EN;
z_wr = `EN;
c_wr = `EN;
bg_op = `BG_NOP;
end //end of SUBWF_W ;
 
12'b0000_101X_XXXX:
//REPLACE ID = SUBWF_F
//REPLACE ID = SUBWF_F
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_W;
alu_muxb = `MUXB_REG;
alu_op = `ALU_SUB;
men_wr = `EN;
w_wr = `DIS;
z_wr = `EN;
c_wr = `EN;
bg_op = `BG_NOP;
end //end of SUBWF_F ;
 
12'b0000_110X_XXXX:
//REPLACE ID = DECF_W
//REPLACE ID = DECF_W
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_IGN;
alu_muxb = `MUXB_REG;
alu_op = `ALU_DEC;
men_wr = `DIS;
w_wr = `EN;
z_wr = `EN;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of DECF_W ;
 
 
12'b0000_111X_XXXX:
//REPLACE ID = DECF_F
//REPLACE ID = DECF_F
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_IGN;
alu_muxb = `MUXB_REG;
alu_op = `ALU_DEC;
men_wr = `EN;
w_wr = `DIS;
z_wr = `EN;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of DECF_F ;
 
12'b0001_000X_XXXX:
//REPLACE ID = IORWF_W
//REPLACE ID = IORWF_W
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_W;
alu_muxb = `MUXB_EK;
alu_op = `ALU_OR;
men_wr = `DIS;
w_wr = `EN;
z_wr = `EN;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of IORWF_W ;
 
 
 
12'b0001_001X_XXXX:
//REPLACE ID = IORWF_F
//REPLACE ID = IORWF_F
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_W;
alu_muxb = `MUXB_EK;
alu_op = `ALU_OR;
men_wr = `EN;
w_wr = `DIS;
z_wr = `EN;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of IORWF_F ;
 
12'b0001_010X_XXXX:
//REPLACE ID = ANDWF_W
//REPLACE ID = ANDWF_W
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_W;
alu_muxb = `MUXB_EK;
alu_op = `ALU_AND;
men_wr = `DIS;
w_wr = `EN;
z_wr = `EN;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of ANDWF_W ;
 
12'b0001_011X_XXXX:
//REPLACE ID = ANDWF_F
//REPLACE ID = ANDWF_F
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_W;
alu_muxb = `MUXB_EK;
alu_op = `ALU_AND;
men_wr = `EN;
w_wr = `DIS;
z_wr = `EN;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of ANDWF_F ;
 
12'b0001_100X_XXXX:
//REPLACE ID = XORWF_W
//REPLACE ID = XORWF_W
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_W;
alu_muxb = `MUXB_REG;
alu_op = `ALU_XOR;
men_wr = `DIS;
w_wr = `EN;
z_wr = `EN;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of XORWF_W ;
 
12'b0001_101X_XXXX:
//REPLACE ID = XORWF_F
//REPLACE ID = XORWF_F
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_W;
alu_muxb = `MUXB_REG;
alu_op = `ALU_XOR;
men_wr = `EN;
w_wr = `DIS;
z_wr = `EN;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of XORWF_F ;
 
12'b0001_110X_XXXX:
//REPLACE ID = ADDWF_W
//REPLACE ID = ADDWF_W
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_W;
alu_muxb = `MUXB_REG;
alu_op = `ALU_ADD;
men_wr = `DIS;
w_wr = `EN;
z_wr = `EN;
c_wr = `EN;
bg_op = `BG_NOP;
end //end of ADDWF_W ;
 
12'b0001_111X_XXXX:
//REPLACE ID = ADDWF_F
//REPLACE ID = ADDWF_F
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_W;
alu_muxb = `MUXB_REG;
alu_op = `ALU_ADD;
men_wr = `EN;
w_wr = `DIS;
z_wr = `EN;
c_wr = `EN;
bg_op = `BG_NOP;
end //end of ADDWF_F ;
 
12'b0010_000X_XXXX:
//REPLACE ID = MOVF_W
//REPLACE ID = MOVF_W
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_W;
alu_muxb = `MUXB_REG;
alu_op = `ALU_PB;
men_wr = `DIS;
w_wr = `EN;
z_wr = `EN;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of MOVF_W ;
 
 
12'b0010_001X_XXXX:
//REPLACE ID = MOVF_F
//REPLACE ID = MOVF_F
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_W;
alu_muxb = `MUXB_REG;
alu_op = `ALU_PB;
men_wr = `DIS;//Also can be set as EN
w_wr = `DIS;
z_wr = `EN;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of MOVF_F ;
 
12'b0010_010X_XXXX:
//REPLACE ID = COMF_W
//REPLACE ID = COMF_W
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_W;
alu_muxb = `MUXB_REG;
alu_op = `ALU_COM;
men_wr = `DIS;
w_wr = `EN;
z_wr = `EN;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of COMF_W ;
 
12'b0010_011X_XXXX:
//REPLACE ID = COMF_F
//REPLACE ID = COMF_F
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_IGN;
alu_muxb = `MUXB_REG;
alu_op = `ALU_COM;
men_wr = `EN;
w_wr = `DIS;
z_wr = `EN;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of COMF_F ;
 
12'b0010_100X_XXXX:
//REPLACE ID = INCF_W
//REPLACE ID = INCF_W
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_IGN;
alu_muxb = `MUXB_REG;
alu_op = `ALU_INC;
men_wr = `DIS;
w_wr = `EN;
z_wr = `EN;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of INCF_W ;
 
12'b0010_101X_XXXX:
//REPLACE ID = INCF_F
//REPLACE ID = INCF_F
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_IGN;
alu_muxb = `MUXB_REG;
alu_op = `ALU_INC;
men_wr = `EN;
w_wr = `DIS;
z_wr = `EN;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of INCF_F ;
 
12'b0010_110X_XXXX:
//REPLACE ID = DECFSZ_W
//REPLACE ID = DECFSZ_W
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_IGN;
alu_muxb = `MUXB_REG;
alu_op = `ALU_DEC;
men_wr = `DIS;
w_wr = `EN;
z_wr = `DIS;
c_wr = `DIS;
bg_op = `BG_ZERO; //if the result is 0 then the next instrction will be discarded
end //end of DECFSZ_W ;
 
12'b0010_111X_XXXX:
//REPLACE ID = DECFSZ_F
//REPLACE ID = DECFSZ_F
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_IGN;
alu_muxb = `MUXB_REG;
alu_op = `ALU_DEC;
men_wr = `EN;
w_wr = `DIS;
z_wr = `DIS;
c_wr = `DIS;
bg_op = `BG_ZERO; //if the result is 0 then the next instrction will be discarded
end //end of DECFSZ_F ;
//checked
 
12'b0011_000X_XXXX:
//REPLACE ID = RRF_W
//REPLACE ID = RRF_W
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_IGN;
alu_muxb = `MUXB_REG;
alu_op = `ALU_ROR;
men_wr = `DIS;
w_wr = `EN;
z_wr = `DIS;
c_wr = `EN;
bg_op = `BG_NOP;
end //end of RRF_W ;
//checked
 
12'b0011_001X_XXXX:
//REPLACE ID = RRF_F
//REPLACE ID = RRF_F
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_IGN;
alu_muxb = `MUXB_REG;
alu_op = `ALU_ROR;
men_wr = `EN;
w_wr = `DIS;
z_wr = `DIS;
c_wr = `EN;
bg_op = `BG_NOP;
end //end of RRF_F ;
 
//
12'b0011_010X_XXXX:
//REPLACE ID = RLF_W
//REPLACE ID = RLF_W
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_IGN;
alu_muxb = `MUXB_REG;
alu_op = `ALU_ROL;
men_wr = `DIS;
w_wr = `EN;
z_wr = `DIS;
c_wr = `EN;
bg_op = `BG_NOP;
end //end of RLF_W ;
 
12'b0011_011X_XXXX:
//REPLACE ID = RLF_F
//REPLACE ID = RLF_F
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_IGN;
alu_muxb = `MUXB_REG;
alu_op = `ALU_ROL;
men_wr = `EN;
w_wr = `DIS;
z_wr = `DIS;
c_wr = `EN;
bg_op = `BG_NOP;
end //end of RLF_F ;
 
12'b0011_100X_XXXX:
//REPLACE ID = SWAPF_W
//REPLACE ID = SWAPF_W
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_W;
alu_muxb = `MUXB_REG;
alu_op = `ALU_SWAP;
men_wr = `DIS;
w_wr = `EN;
z_wr = `DIS;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of SWAPF_F ;
 
12'b0011_101X_XXXX:
//REPLACE ID = SWAPF_F
//REPLACE ID = SWAPF_F
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_W;
alu_muxb = `MUXB_REG;
alu_op = `ALU_SWAP;
men_wr = `EN;
w_wr = `DIS;
z_wr = `DIS;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of SWAPF_F ;
 
12'b0011_110X_XXXX:
//REPLACE ID = INCFSZ_W
//REPLACE ID = INCFSZ_W
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_W;
alu_muxb = `MUXB_REG;
alu_op = `ALU_INC;
men_wr = `DIS;
w_wr = `EN;
z_wr = `DIS;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of INCFSZ_W ;
 
12'b0011_111X_XXXX:
//REPLACE ID = INCFSZ_F
//REPLACE ID = INCFSZ_F
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_W;
alu_muxb = `MUXB_REG;
alu_op = `ALU_INC;
men_wr = `EN;
w_wr = `DIS;
z_wr = `DIS;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of INCFSZ_F ;
 
12'b0100_XXXX_XXXX:
//REPLACE ID = BCF
//REPLACE ID = BCF
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_W;
alu_muxb = `MUXB_REG;
alu_op = `ALU_NOP;
men_wr = `EN;
w_wr = `DIS;
z_wr = `DIS;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of BCF ;
 
12'b0101_XXXX_XXXX:
//REPLACE ID = BSF
//REPLACE ID = BSF
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_W;
alu_muxb = `MUXB_REG;
alu_op = `ALU_NOP;
men_wr = `EN;
w_wr = `DIS;
z_wr = `DIS;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of BSF ;
/**/
 
12'b0110_XXXX_XXXX:
//REPLACE ID = BTFSC
//REPLACE ID = BTFSC
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_W;
alu_muxb = `MUXB_REG;
alu_op = `ALU_NOP;
men_wr = `DIS;
w_wr = `DIS;
z_wr = `DIS;
c_wr = `DIS;
bg_op = `BG_ZERO;
end //end of BTFSC ;
 
12'b0111_XXXX_XXXX:
//REPLACE ID = BTFSS
//REPLACE ID = BTFSS
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_W;
alu_muxb = `MUXB_REG;
alu_op = `ALU_NOP;
men_wr = `DIS;
w_wr = `DIS;
z_wr = `DIS;
c_wr = `DIS;
bg_op = `BG_NZERO;
end //end of BTFSS ;
 
12'b1000_XXXX_XXXX:
//REPLACE ID = RETLW
//REPLACE ID = RETLW
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_POP;
alu_muxa = `MUXA_W;
alu_muxb = `MUXB_REG;
alu_op = `ALU_NOP;
men_wr = `DIS;
w_wr = `DIS;
z_wr = `DIS;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of RETLW ;
 
12'b1001_XXXX_XXXX:
//REPLACE ID = CALL
//REPLACE ID = CALL
begin
pc_ctl = `PC_GOTO;
stack_op = `STK_PSH;
alu_muxa = `MUXA_IGN;
alu_muxb = `MUXB_IGN;
alu_op = `ALU_NOP;
men_wr = `DIS;
w_wr = `DIS;
z_wr = `DIS;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of CALL ;
 
12'b101X_XXXX_XXXX:
//REPLACE ID = GOTO
//REPLACE ID = GOTO
begin
pc_ctl = `PC_GOTO;
stack_op = `STK_NOP;
alu_muxa = `MUXA_IGN;
alu_muxb = `MUXB_IGN;
alu_op = `ALU_NOP;
men_wr = `DIS;
w_wr = `DIS;
z_wr = `DIS;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of GOTO ;
 
12'b1100_XXXX_XXXX:
//REPLACE ID = MOVLW
//REPLACE ID = MOVLW
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_IGN;
alu_muxb = `MUXB_EK;
alu_op = `ALU_PB;
men_wr = `DIS;
w_wr = `EN;
z_wr = `DIS;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of MOVLW ;
 
12'b1101_XXXX_XXXX:
//REPLACE ID = IORLW
//REPLACE ID = IORLW
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_W;
alu_muxb = `MUXB_EK;
alu_op = `ALU_OR;
men_wr = `DIS;
w_wr = `EN;
z_wr = `EN;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of IORLW ;
 
12'b1110_XXXX_XXXX:
//REPLACE ID = ANDLW
//REPLACE ID = ANDLW
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_W;
alu_muxb = `MUXB_EK;
alu_op = `ALU_AND;
men_wr = `DIS;
w_wr = `EN;
z_wr = `EN;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of ANDLW ;
 
12'b1111_XXXX_XXXX:
//REPLACE ID = XORLW
//REPLACE ID = XORLW
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_W;
alu_muxb = `MUXB_EK;
alu_op = `ALU_XOR;
men_wr = `DIS;
w_wr = `EN;
z_wr = `EN;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of XORLW ;
 
 
default:
//REPLACE ID = NOP
begin
pc_ctl = `PC_NEXT;
stack_op = `STK_NOP;
alu_muxa = `MUXA_IGN;
alu_muxb = `MUXB_IGN;
alu_op = `ALU_NOP;
men_wr = `DIS;
w_wr = `DIS;
z_wr = `DIS;
c_wr = `DIS;
bg_op = `BG_NOP;
end //end of NOP ;
endcase
end
endmodule
/trunk/sim_rom.v
0,0 → 1,64
//This file was created by a tool wrietten with C.
module sim_rom (
address,
clock,
q);
input [10:0] address;
input clock;
output [11:0] q;
reg [10:0] address_latched;
// Instantiate the memory array itself.
reg [11:0] mem[0:2048-1];
initial begin
mem[0] = 1219;
mem[1] = 1187;
mem[2] = 3058;
mem[481] = 3075;
mem[482] = 100;
mem[483] = 42;
mem[484] = 107;
mem[485] = 522;
mem[486] = 1603;
mem[487] = 235;
mem[488] = 234;
mem[489] = 650;
mem[490] = 1603;
mem[491] = 651;
mem[492] = 1859;
mem[493] = 3045;
mem[494] = 521;
mem[495] = 1219;
mem[496] = 1443;
mem[497] = 2561;
mem[498] = 100;
mem[499] = 104;
mem[500] = 104;
mem[501] = 3076;
mem[502] = 41;
mem[503] = 3041;
mem[504] = 680;
mem[505] = 3172;
mem[506] = 136;
mem[507] = 1795;
mem[508] = 3061;
mem[509] = 1219;
mem[510] = 1187;
mem[511] = 2560;
mem[512] = 524;
mem[513] = 44;
mem[514] = 684;
mem[515] = 34;
mem[516] = 1219;
mem[517] = 1187;
mem[518] = 3064;
mem[2047] = 2560;
end
// Latch address
always @(posedge clock)
address_latched <= address;
// READ
assign q = mem[address_latched];
 
endmodule
/trunk/memory.v
0,0 → 1,78
`include "clairisc_def.h"
module pram (
clk,
rd_addr,
wr_addr,
we,
din,
dout
);
input clk;
input [10:0] rd_addr;
input [10:0] wr_addr;
input we;
input [11:0] din;
output [11:0] dout;
/*
`ifndef SIM
alt_ram i_alt_ram (
.data(din),
.wren(we),
.wraddress(wr_addr),
.rdaddress(rd_addr),
.clock(clk),
.q(dout)
);
`else
*/
sim_rom i_sim_ram(
.address(rd_addr),
.clock(clk),
.q(dout)
);
//`endif
 
endmodule
 
module sim_reg_file (
data,
wren,
wraddress,
rdaddress,
clock,
q);
 
input [7:0] data;
input wren;
input [6:0] wraddress;
input [6:0] rdaddress;
input clock;
output [7:0] q;
 
reg [7:0] membank[0:127];
 
reg r_we;
reg [6:0] r_rd_addr;
reg [6:0] r_wr_addr;
reg [6:0] r_data;
 
always @ (posedge clock)
begin
 
r_rd_addr<=rdaddress;
r_wr_addr<=wraddress;
r_data<=data;
r_we<=wren;
end
 
always @(posedge clock)
if (r_we)
membank[r_wr_addr]<=r_data;
 
assign q=((r_rd_addr==r_wr_addr)&&(r_we))?r_data:membank[r_rd_addr] ;
 
endmodule
 
/trunk/mem_man.v
0,0 → 1,106
`include "clairisc_def.h"
 
module mem_man(
input wr_en,
input clk,
input rst,
output reg [7:0] dout,
output co,
output [1:0] bank,
input [6:0] rd_addr,
input [6:0] wr_addr,
output [6:0] exp_wr_addr,
output [6:0] exp_rd_addr,
output [7:0] exp_dout,
input ci,
input zi,
input z_wr,
input c_wr,
input [7:0] exp_din ,
input [7:0] din ,
output reg [7:0]status
);
 
reg wr_en_r;
reg [6:0] din_r, wr_addr_r;
reg [6:0] rd_addr_r;
 
always @(posedge clk)
begin
wr_addr_r<=wr_addr;
rd_addr_r<=rd_addr;
wr_en_r<=wr_en;
din_r<=din;
end
 
wire [7:0] ram_q ;
wire [7:0] alt_ram_q;
/*`ifdef SIM
reg_file i_reg_file(
.data(din),
.wren(wr_en),
.wraddress(wr_addr),
.rdaddress(rd_addr),
.clock(clk),
.q(alt_ram_q)
);
`else
*/
sim_reg_file i_reg_file(
.data(din),
.wren(wr_en),
.wraddress(wr_addr),
.rdaddress(rd_addr),
.clock(clk),
.q(alt_ram_q));
//`endif
 
assign ram_q = ((wr_addr_r==rd_addr_r)&&(wr_en_r))?din_r:alt_ram_q;
 
/*status register*/
wire write_status = wr_addr == `ADDR_STATUS && wr_en ;
always@(posedge clk)
begin
if (rst)status<=8'h3f;//default value
else
if (write_status)status<=din;
else
begin
if (c_wr)status[0]<=ci;
if (z_wr)status[2]<=zi;
end
end
 
assign co = status[0];
assign zo = status[2];
 
/*fsr register*/
reg [6:0] fsr;
wire write_fsr = wr_addr == `ADDR_FSR &&wr_en ;
always@(posedge clk)
begin
if (rst)fsr<=0;
else if(write_fsr) fsr<=din[6:0];
end
//reg [7:0] status;
assign bank = fsr[6:5];
 
/*data bus output logic*/
always@(*)//select status,fsr,ram,exp_din
casex(rd_addr_r)
`ADDR_FSR:dout = fsr;
`ADDR_STATUS:dout = status;
7'b00_01XXX,7'b01_01XXX,7'b10_01XXX,7'b11_01XXX,7'b00_10XXX,7'b00_11XXX,
7'b01_10XXX,7'b01_11XXX,7'b10_10XXX,7'b10_11XXX,7'b11_10XXX,7'b11_11XXX:
dout = ram_q ;
default dout = exp_din;
endcase
 
/*exp device bus logic*/
assign exp_rd_addr = rd_addr;
assign exp_wr_addr = wr_addr;
assign exp_dout =din;
 
endmodule

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