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URL https://opencores.org/ocsvn/nand_controller/nand_controller/trunk

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Rev 2 → Rev 3

/nand_controller/trunk/VHDL/nand_interface.vhd
9,7 → 9,8
-- This file implements a simplistic NAND interface driven by 5 control signals:
-- action_cmd, action_address, action_read and action_write which trigger
-- execution of Command Latch Cycle, Address Latch Cycle, Data Output and
-- Data Input cycles respectively.
-- Data Input cycles respectively. This interface controlls all timing stuff
-- as well.
-- This component may be used as a standalone NAND Flash adapter, although,
-- I would recommend using the controller as a whole.
--------------------------------------------------------------------------
29,8 → 30,9
nand_n_we : out std_logic := '1';
nand_n_wp : out std_logic := '1';
nand_n_ce : out std_logic := '1';
nand_n_ce2 : out std_logic := '1';
nand_n_re : out std_logic := '1';
nand_r_nb : in std_logic := '1';
nand_r_nb : in std_logic := '1'; -- We use single RB# input even for 8Gbit NAND chips. In such case, RB# should be ORed with RB2#
nand_io : inout std_logic_vector(15 downto 0);
-- System interface
37,14 → 39,16
clk : in std_logic;
-- NAND controller internal interface
data_rx : in std_logic_vector(15 downto 0);
data_tx : out std_logic_vector(15 downto 0);
ready : out std_logic := '0';
n_nand_enable : in std_logic := '1';
action_cmd : in std_logic := '0';
action_address : in std_logic := '0';
action_read : in std_logic := '0';
action_write : in std_logic := '0'
data_rx : in std_logic_vector(15 downto 0); -- Data input from the 'client'
data_tx : out std_logic_vector(15 downto 0); -- Data output to the 'client'
ready : out std_logic := '0'; -- Indicates whether the component is ready for next operation.
n_nand_enable : in std_logic := '1'; -- Enables the component and the NAND Flash. Signal is active LOW.
action_cmd : in std_logic := '0'; -- When strobed high, initiates Command Latch Cycle
action_address : in std_logic := '0'; -- When strobed high, initiates Address Latch Cycle
action_read : in std_logic := '0'; -- When strobed high, initiates Data Output Cycle
action_write : in std_logic := '0'; -- When strobed high, initiates Data Input Cycle
is_x16 : in std_logic := '0'; -- When '1', the NAND chip is a x16 NAND, so the data line must be remuxed!
die_select : in std_logic := '0' -- For x8 8Gbit devices only. Selects active die
);
end nand_interface;
 
52,8 → 56,8
-- NAND IO
signal nand_io_rx : std_logic_vector(15 downto 0);
signal nand_io_tx : std_logic_vector(15 downto 0);
signal nand_oe : std_logic;
signal nand_io_buffer : std_logic_vector(15 downto 0);
signal nand_oe : std_logic; -- Enables output on nand_io "pin"
signal nand_io_buffer : std_logic_vector(15 downto 0); -- Stores data read from the NAND Flash
-- Main FSM
type c_state_t is (C_IDLE, C_COMMAND, C_ADDRESS, C_READ, C_WRITE, C_DELAY);
65,14 → 69,25
signal l_state : l_state_t := L_BEGIN;
-- Delay counter
signal delay_cnt : integer := 0;
signal delay_cnt : integer := 0; -- Simply a delay counter
begin
-- NAND chip enable
nand_n_ce <= n_nand_enable;
nand_n_ce <= n_nand_enable when is_x16 = '1' else
n_nand_enable when die_select = '0' else
'1';
 
nand_n_ce2 <= '1' when is_x16 = '1' else
n_nand_enable when die_select = '1' else
'1';
-- NAND IO bidirectional "pin"
nand_io <= nand_io_tx when nand_oe = '1' else "ZZZZZZZZZZZZZZZZ";
data_tx <= nand_io_buffer;
nand_io <= nand_io_tx when nand_oe = '1' and is_x16 = '0' else
nand_io_tx(15)&nand_io_tx(14)&nand_io_tx(11)&nand_io_tx(8)&nand_io_tx(7)&nand_io_tx(4)&nand_io_tx(1)&nand_io_tx(0)&
nand_io_tx(6)&nand_io_tx(13)&nand_io_tx(5)&nand_io_tx(12)&nand_io_tx(3)&nand_io_tx(10)&nand_io_tx(2)&nand_io_tx(9) when nand_oe = '1' and is_x16 = '1'
else "ZZZZZZZZZZZZZZZZ";
data_tx <= nand_io_buffer when is_x16 = '0' else
nand_io_buffer(15)&nand_io_buffer(14)&nand_io_buffer(6)&nand_io_buffer(4)&nand_io_buffer(13)&nand_io_buffer(2)&nand_io_buffer(0)&nand_io_buffer(12)&
nand_io_buffer(11)&nand_io_buffer(7)&nand_io_buffer(5)&nand_io_buffer(10)&nand_io_buffer(3)&nand_io_buffer(1)&nand_io_buffer(9)&nand_io_buffer(8) when is_x16 = '1';
-- READY
ready <= '1' when c_state = C_IDLE and nand_r_nb = '1' and n_nand_enable = '0' else '0';

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