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/nfcc/trunk/LICENSE.txt
0,0 → 1,37
Nugroho Free Crypto Cores (NFCC) License:
------------------------------------------------------------------------
Copyright (C) 2010 Arif Endro Nugroho
All rights reserved.
 
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
 
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
 
THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
 
End Of License.
------------------------------------------------------------------------
 
Author Contact:
 
Arif E. Nugroho
Segaran I/27A 50184, Semarang, Central Java, Indonesia
 
mobile: +62 818 220 540
e-mail: arif_endro@yahoo.com
/nfcc/trunk/snow/diva.vhdl
0,0 → 1,127
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity diva is
port (
c : in bit_vector ( 7 downto 0);
w : out bit_vector ( 31 downto 0)
);
end diva;
 
architecture phy of diva is
begin
with c select
w <=
 
X"00000000" when X"00", X"180f40cd" when X"01", X"301e8033" when X"02", X"2811c0fe" when X"03",
X"603ca966" when X"04", X"7833e9ab" when X"05", X"50222955" when X"06", X"482d6998" when X"07",
X"c078fbcc" when X"08", X"d877bb01" when X"09", X"f0667bff" when X"0a", X"e8693b32" when X"0b",
X"a04452aa" when X"0c", X"b84b1267" when X"0d", X"905ad299" when X"0e", X"88559254" when X"0f",
 
X"29f05f31" when X"10", X"31ff1ffc" when X"11", X"19eedf02" when X"12", X"01e19fcf" when X"13",
X"49ccf657" when X"14", X"51c3b69a" when X"15", X"79d27664" when X"16", X"61dd36a9" when X"17",
X"e988a4fd" when X"18", X"f187e430" when X"19", X"d99624ce" when X"1a", X"c1996403" when X"1b",
X"89b40d9b" when X"1c", X"91bb4d56" when X"1d", X"b9aa8da8" when X"1e", X"a1a5cd65" when X"1f",
 
X"5249be62" when X"20", X"4a46feaf" when X"21", X"62573e51" when X"22", X"7a587e9c" when X"23",
X"32751704" when X"24", X"2a7a57c9" when X"25", X"026b9737" when X"26", X"1a64d7fa" when X"27",
X"923145ae" when X"28", X"8a3e0563" when X"29", X"a22fc59d" when X"2a", X"ba208550" when X"2b",
X"f20decc8" when X"2c", X"ea02ac05" when X"2d", X"c2136cfb" when X"2e", X"da1c2c36" when X"2f",
 
X"7bb9e153" when X"30", X"63b6a19e" when X"31", X"4ba76160" when X"32", X"53a821ad" when X"33",
X"1b854835" when X"34", X"038a08f8" when X"35", X"2b9bc806" when X"36", X"339488cb" when X"37",
X"bbc11a9f" when X"38", X"a3ce5a52" when X"39", X"8bdf9aac" when X"3a", X"93d0da61" when X"3b",
X"dbfdb3f9" when X"3c", X"c3f2f334" when X"3d", X"ebe333ca" when X"3e", X"f3ec7307" when X"3f",
 
X"a492d5c4" when X"40", X"bc9d9509" when X"41", X"948c55f7" when X"42", X"8c83153a" when X"43",
X"c4ae7ca2" when X"44", X"dca13c6f" when X"45", X"f4b0fc91" when X"46", X"ecbfbc5c" when X"47",
X"64ea2e08" when X"48", X"7ce56ec5" when X"49", X"54f4ae3b" when X"4a", X"4cfbeef6" when X"4b",
X"04d6876e" when X"4c", X"1cd9c7a3" when X"4d", X"34c8075d" when X"4e", X"2cc74790" when X"4f",
 
X"8d628af5" when X"50", X"956dca38" when X"51", X"bd7c0ac6" when X"52", X"a5734a0b" when X"53",
X"ed5e2393" when X"54", X"f551635e" when X"55", X"dd40a3a0" when X"56", X"c54fe36d" when X"57",
X"4d1a7139" when X"58", X"551531f4" when X"59", X"7d04f10a" when X"5a", X"650bb1c7" when X"5b",
X"2d26d85f" when X"5c", X"35299892" when X"5d", X"1d38586c" when X"5e", X"053718a1" when X"5f",
 
X"f6db6ba6" when X"60", X"eed42b6b" when X"61", X"c6c5eb95" when X"62", X"decaab58" when X"63",
X"96e7c2c0" when X"64", X"8ee8820d" when X"65", X"a6f942f3" when X"66", X"bef6023e" when X"67",
X"36a3906a" when X"68", X"2eacd0a7" when X"69", X"06bd1059" when X"6a", X"1eb25094" when X"6b",
X"569f390c" when X"6c", X"4e9079c1" when X"6d", X"6681b93f" when X"6e", X"7e8ef9f2" when X"6f",
 
X"df2b3497" when X"70", X"c724745a" when X"71", X"ef35b4a4" when X"72", X"f73af469" when X"73",
X"bf179df1" when X"74", X"a718dd3c" when X"75", X"8f091dc2" when X"76", X"97065d0f" when X"77",
X"1f53cf5b" when X"78", X"075c8f96" when X"79", X"2f4d4f68" when X"7a", X"37420fa5" when X"7b",
X"7f6f663d" when X"7c", X"676026f0" when X"7d", X"4f71e60e" when X"7e", X"577ea6c3" when X"7f",
 
X"e18d0321" when X"80", X"f98243ec" when X"81", X"d1938312" when X"82", X"c99cc3df" when X"83",
X"81b1aa47" when X"84", X"99beea8a" when X"85", X"b1af2a74" when X"86", X"a9a06ab9" when X"87",
X"21f5f8ed" when X"88", X"39fab820" when X"89", X"11eb78de" when X"8a", X"09e43813" when X"8b",
X"41c9518b" when X"8c", X"59c61146" when X"8d", X"71d7d1b8" when X"8e", X"69d89175" when X"8f",
 
X"c87d5c10" when X"90", X"d0721cdd" when X"91", X"f863dc23" when X"92", X"e06c9cee" when X"93",
X"a841f576" when X"94", X"b04eb5bb" when X"95", X"985f7545" when X"96", X"80503588" when X"97",
X"0805a7dc" when X"98", X"100ae711" when X"99", X"381b27ef" when X"9a", X"20146722" when X"9b",
X"68390eba" when X"9c", X"70364e77" when X"9d", X"58278e89" when X"9e", X"4028ce44" when X"9f",
 
X"b3c4bd43" when X"a0", X"abcbfd8e" when X"a1", X"83da3d70" when X"a2", X"9bd57dbd" when X"a3",
X"d3f81425" when X"a4", X"cbf754e8" when X"a5", X"e3e69416" when X"a6", X"fbe9d4db" when X"a7",
X"73bc468f" when X"a8", X"6bb30642" when X"a9", X"43a2c6bc" when X"aa", X"5bad8671" when X"ab",
X"1380efe9" when X"ac", X"0b8faf24" when X"ad", X"239e6fda" when X"ae", X"3b912f17" when X"af",
 
X"9a34e272" when X"b0", X"823ba2bf" when X"b1", X"aa2a6241" when X"b2", X"b225228c" when X"b3",
X"fa084b14" when X"b4", X"e2070bd9" when X"b5", X"ca16cb27" when X"b6", X"d2198bea" when X"b7",
X"5a4c19be" when X"b8", X"42435973" when X"b9", X"6a52998d" when X"ba", X"725dd940" when X"bb",
X"3a70b0d8" when X"bc", X"227ff015" when X"bd", X"0a6e30eb" when X"be", X"12617026" when X"bf",
 
X"451fd6e5" when X"c0", X"5d109628" when X"c1", X"750156d6" when X"c2", X"6d0e161b" when X"c3",
X"25237f83" when X"c4", X"3d2c3f4e" when X"c5", X"153dffb0" when X"c6", X"0d32bf7d" when X"c7",
X"85672d29" when X"c8", X"9d686de4" when X"c9", X"b579ad1a" when X"ca", X"ad76edd7" when X"cb",
X"e55b844f" when X"cc", X"fd54c482" when X"cd", X"d545047c" when X"ce", X"cd4a44b1" when X"cf",
 
X"6cef89d4" when X"d0", X"74e0c919" when X"d1", X"5cf109e7" when X"d2", X"44fe492a" when X"d3",
X"0cd320b2" when X"d4", X"14dc607f" when X"d5", X"3ccda081" when X"d6", X"24c2e04c" when X"d7",
X"ac977218" when X"d8", X"b49832d5" when X"d9", X"9c89f22b" when X"da", X"8486b2e6" when X"db",
X"ccabdb7e" when X"dc", X"d4a49bb3" when X"dd", X"fcb55b4d" when X"de", X"e4ba1b80" when X"df",
 
X"17566887" when X"e0", X"0f59284a" when X"e1", X"2748e8b4" when X"e2", X"3f47a879" when X"e3",
X"776ac1e1" when X"e4", X"6f65812c" when X"e5", X"477441d2" when X"e6", X"5f7b011f" when X"e7",
X"d72e934b" when X"e8", X"cf21d386" when X"e9", X"e7301378" when X"ea", X"ff3f53b5" when X"eb",
X"b7123a2d" when X"ec", X"af1d7ae0" when X"ed", X"870cba1e" when X"ee", X"9f03fad3" when X"ef",
 
X"3ea637b6" when X"f0", X"26a9777b" when X"f1", X"0eb8b785" when X"f2", X"16b7f748" when X"f3",
X"5e9a9ed0" when X"f4", X"4695de1d" when X"f5", X"6e841ee3" when X"f6", X"768b5e2e" when X"f7",
X"fedecc7a" when X"f8", X"e6d18cb7" when X"f9", X"cec04c49" when X"fa", X"d6cf0c84" when X"fb",
X"9ee2651c" when X"fc", X"86ed25d1" when X"fd", X"aefce52f" when X"fe", X"b6f3a5e2" when X"ff",
 
X"00000000" when others;
end phy;
/nfcc/trunk/snow/mulx.vhdl
0,0 → 1,47
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity mulx is
port (
V : in bit_vector ( 7 downto 0);
c : in bit_vector ( 7 downto 0);
w : out bit_vector ( 7 downto 0)
);
end mulx;
 
architecture phy of mulx is
begin
--MULx(V,c) == ( V<<1 ) xor c when MSB(V) = 1 else
w <= (V(6 downto 0) & '0' ) xor c when V(7) = '1' else
(V(6 downto 0) & '0' );
end phy;
/nfcc/trunk/snow/snow.vhdl
0,0 → 1,209
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity snow is
port (
key : in bit_vector ( 31 downto 0);
IV : in bit_vector ( 31 downto 0);
n : in bit_vector ( 31 downto 0);
zt : out bit_vector ( 31 downto 0);
ld : in bit;
init : in bit;
shift : in bit;
clk : in bit;
rst : in bit
);
end snow;
 
architecture phy of snow is
 
signal lsfr : bit_vector (511 downto 0);
signal s0 : bit_vector ( 31 downto 0);
signal s1 : bit_vector ( 31 downto 0);
signal s2 : bit_vector ( 31 downto 0);
signal s3 : bit_vector ( 31 downto 0);
signal s4 : bit_vector ( 31 downto 0);
signal s5 : bit_vector ( 31 downto 0);
signal s6 : bit_vector ( 31 downto 0);
signal s7 : bit_vector ( 31 downto 0);
signal s8 : bit_vector ( 31 downto 0);
signal s9 : bit_vector ( 31 downto 0);
signal sa : bit_vector ( 31 downto 0);
signal sb : bit_vector ( 31 downto 0);
signal sc : bit_vector ( 31 downto 0);
signal sd : bit_vector ( 31 downto 0);
signal se : bit_vector ( 31 downto 0);
signal sf : bit_vector ( 31 downto 0);
 
signal v : bit_vector ( 31 downto 0);
 
signal ss1i : bit_vector ( 31 downto 0); -- S1
signal ss1o : bit_vector ( 31 downto 0); -- S1
signal ss2i : bit_vector ( 31 downto 0); -- S2
signal ss2o : bit_vector ( 31 downto 0); -- S2
 
signal F : bit_vector ( 31 downto 0); -- F = (sf +) xor R2
signal r : bit_vector ( 31 downto 0); -- r = R2 + (R3 xor s5)
signal R1 : bit_vector ( 31 downto 0); -- R1 = r
signal R2 : bit_vector ( 31 downto 0); -- R2 = S1(R1)
signal R3 : bit_vector ( 31 downto 0); -- R3 = S2(R2)
 
signal mli : bit_vector ( 7 downto 0);
signal mlo : bit_vector ( 31 downto 0);
signal dvi : bit_vector ( 7 downto 0);
signal dvo : bit_vector ( 31 downto 0);
 
signal ivma : bit_vector (127 downto 0) := X"ffffffffffffffff0000000000000000";
signal ivmb : bit_vector (127 downto 0) := X"0000000000000000ffffffff00000000";
signal ivmc : bit_vector (127 downto 0) := X"000000000000000000000000ffffffff";
 
component sboxs1
port (
w : bit_vector ( 31 downto 0);
r : bit_vector ( 31 downto 0)
);
end component;
 
component sboxs2
port (
w : bit_vector ( 31 downto 0);
r : bit_vector ( 31 downto 0)
);
end component;
 
component mula
port (
c : bit_vector ( 7 downto 0);
w : bit_vector ( 31 downto 0)
);
end component;
 
component diva
port (
c : bit_vector ( 7 downto 0);
w : bit_vector ( 31 downto 0)
);
end component;
 
begin
 
ss1 : sboxs1
port map (
w => ss1i,
r => ss1o
);
ss2 : sboxs2
port map (
w => ss2i,
r => ss2o
);
ml : mula
port map (
c => mli,
w => mlo
);
dv : diva
port map (
c => dvi,
w => dvo
);
--persistent connection
s0 <= lsfr(511 downto 480);
s1 <= lsfr(479 downto 448);
s2 <= lsfr(447 downto 416);
s3 <= lsfr(415 downto 384);
s4 <= lsfr(383 downto 352);
s5 <= lsfr(351 downto 320);
s6 <= lsfr(319 downto 288);
s7 <= lsfr(287 downto 256);
s8 <= lsfr(255 downto 224);
s9 <= lsfr(223 downto 192);
sa <= lsfr(191 downto 160);
sb <= lsfr(159 downto 128);
sc <= lsfr(127 downto 96);
sd <= lsfr( 95 downto 64);
se <= lsfr( 63 downto 32);
sf <= lsfr( 31 downto 0);
--persistent connection
 
--FSM-Network
F <= (sf + R1) xor R2 ; -- CAVEATS: THIS LINE IS NOT PORTABLE CODE
r <= R2 + (R3 xor s5); -- CAVEATS: THIS LINE IS NOT PORTABLE CODE
R1 <= r;
ss1i <= R1;
R2 <= ss1o;
ss2i <= R2;
R3 <= ss2o;
--FSM-Network
mli <= s0(31 downto 24);
dvi <= sb( 7 downto 0);
--v == (S0,1||S0,2||S0,3||0x00) xor MULa(S0,0) xor S2 xor (0x00||S11,0||S11,1||S11,2) xor DIVa(S11,3)
v <= (s0(23 downto 0) & X"00") xor mlo xor s2 xor (X"00" & sb(31 downto 8)) xor dvo xor F when init = '1' else
(s0(23 downto 0) & X"00") xor mlo xor s2 xor (X"00" & sb(31 downto 8)) xor dvo;
 
process (clk)
begin
if((clk = '1') and clk'event) then
if (rst = '1') then
lsfr <= (others => '0');
ivma <= X"ffffffffffffffff0000000000000000";
ivmb <= X"0000000000000000ffffffff00000000";
ivmc <= X"000000000000000000000000ffffffff";
elsif (ld = '1') then
ivma(127 downto 0) <= ivma( 95 downto 0) & ivma(127 downto 96); -- IV mask a
ivmb(127 downto 0) <= ivmb( 95 downto 0) & ivmb(127 downto 96); -- IV mask b
ivmc(127 downto 0) <= ivmc( 95 downto 0) & ivmc(127 downto 96); -- IV mask c
--rotate in each block
lsfr(127 downto 0) <= lsfr( 95 downto 0) & lsfr(127 downto 96); -- sc...sf
lsfr(255 downto 128) <= lsfr(223 downto 128) & lsfr(255 downto 224); -- s8...sb
lsfr(383 downto 256) <= lsfr(351 downto 256) & lsfr(383 downto 352); -- s4...s7
lsfr(511 downto 384) <= lsfr(479 downto 384) & lsfr(511 downto 448); -- s0...s3
--key
lsfr(127 downto 96) <= key; -- sc == key
lsfr(255 downto 224) <= key xor X"ffffffff"; -- s8 == key xor 1
lsfr(383 downto 352) <= key; -- s4 == key
lsfr(511 downto 448) <= key xor X"ffffffff"; -- s0 == key xor 1
--special cases for IV, the sequences is quite peculiar: sf, sc, and sa, s9
lsfr( 31 downto 0) <= IV and ivma(127 downto 96); -- first 2 clock go to sf then sc
lsfr(255 downto 224) <= IV and ivmb(127 downto 96); -- next 1 clock go to sa
lsfr(191 downto 160) <= IV and ivmc(127 downto 96); -- last 1 clock go to s9
elsif (shift = '1') then
lsfr <= lsfr(479 downto 0) & v;
end if;
end if;
end process;
 
zt <= F xor s0;
 
end phy;
/nfcc/trunk/snow/mulx.pat
0,0 → 1,9
in V (7 downto 0) X;;
in c (7 downto 0) X;;
out w (7 downto 0) X;;
 
begin
< 0ns> : 96 1b ?**;
<+50ns>: 61 1b ?**;
<+50ns>: 69 1b ?**;
end;
/nfcc/trunk/snow/sboxq.vhdl
0,0 → 1,129
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity sboxq is
port (
di : in bit_vector (07 downto 00);
do : out bit_vector (07 downto 00)
);
end sboxq;
 
architecture phy of sboxq is
begin
with di(07 downto 00) select
do <=
-- start sboxq
 
X"25" when X"00", X"24" when X"01", X"73" when X"02", X"67" when X"03",
X"d7" when X"04", X"ae" when X"05", X"5c" when X"06", X"30" when X"07",
X"a4" when X"08", X"ee" when X"09", X"6e" when X"0a", X"cb" when X"0b",
X"7d" when X"0c", X"b5" when X"0d", X"82" when X"0e", X"db" when X"0f",
 
X"e4" when X"10", X"8e" when X"11", X"48" when X"12", X"49" when X"13",
X"4f" when X"14", X"5d" when X"15", X"6a" when X"16", X"78" when X"17",
X"70" when X"18", X"88" when X"19", X"e8" when X"1a", X"5f" when X"1b",
X"5e" when X"1c", X"84" when X"1d", X"65" when X"1e", X"e2" when X"1f",
 
X"d8" when X"20", X"e9" when X"21", X"cc" when X"22", X"ed" when X"23",
X"40" when X"24", X"2f" when X"25", X"11" when X"26", X"28" when X"27",
X"57" when X"28", X"d2" when X"29", X"ac" when X"2a", X"e3" when X"2b",
X"4a" when X"2c", X"15" when X"2d", X"1b" when X"2e", X"b9" when X"2f",
 
X"b2" when X"30", X"80" when X"31", X"85" when X"32", X"a6" when X"33",
X"2e" when X"34", X"02" when X"35", X"47" when X"36", X"29" when X"37",
X"07" when X"38", X"4b" when X"39", X"0e" when X"3a", X"c1" when X"3b",
X"51" when X"3c", X"aa" when X"3d", X"89" when X"3e", X"d4" when X"3f",
 
X"ca" when X"40", X"01" when X"41", X"46" when X"42", X"b3" when X"43",
X"ef" when X"44", X"dd" when X"45", X"44" when X"46", X"7b" when X"47",
X"c2" when X"48", X"7f" when X"49", X"be" when X"4a", X"c3" when X"4b",
X"9f" when X"4c", X"20" when X"4d", X"4c" when X"4e", X"64" when X"4f",
 
X"83" when X"50", X"a2" when X"51", X"68" when X"52", X"42" when X"53",
X"13" when X"54", X"b4" when X"55", X"41" when X"56", X"cd" when X"57",
X"ba" when X"58", X"c6" when X"59", X"bb" when X"5a", X"6d" when X"5b",
X"4d" when X"5c", X"71" when X"5d", X"21" when X"5e", X"f4" when X"5f",
 
X"8d" when X"60", X"b0" when X"61", X"e5" when X"62", X"93" when X"63",
X"fe" when X"64", X"8f" when X"65", X"e6" when X"66", X"cf" when X"67",
X"43" when X"68", X"45" when X"69", X"31" when X"6a", X"22" when X"6b",
X"37" when X"6c", X"36" when X"6d", X"96" when X"6e", X"fa" when X"6f",
 
X"bc" when X"70", X"0f" when X"71", X"08" when X"72", X"52" when X"73",
X"1d" when X"74", X"55" when X"75", X"1a" when X"76", X"c5" when X"77",
X"4e" when X"78", X"23" when X"79", X"69" when X"7a", X"7a" when X"7b",
X"92" when X"7c", X"ff" when X"7d", X"5b" when X"7e", X"5a" when X"7f",
 
X"eb" when X"80", X"9a" when X"81", X"1c" when X"82", X"a9" when X"83",
X"d1" when X"84", X"7e" when X"85", X"0d" when X"86", X"fc" when X"87",
X"50" when X"88", X"8a" when X"89", X"b6" when X"8a", X"62" when X"8b",
X"f5" when X"8c", X"0a" when X"8d", X"f8" when X"8e", X"dc" when X"8f",
 
X"03" when X"90", X"3c" when X"91", X"0c" when X"92", X"39" when X"93",
X"f1" when X"94", X"b8" when X"95", X"f3" when X"96", X"3d" when X"97",
X"f2" when X"98", X"d5" when X"99", X"97" when X"9a", X"66" when X"9b",
X"81" when X"9c", X"32" when X"9d", X"a0" when X"9e", X"00" when X"9f",
 
X"06" when X"a0", X"ce" when X"a1", X"f6" when X"a2", X"ea" when X"a3",
X"b7" when X"a4", X"17" when X"a5", X"f7" when X"a6", X"8c" when X"a7",
X"79" when X"a8", X"d6" when X"a9", X"a7" when X"aa", X"bf" when X"ab",
X"8b" when X"ac", X"3f" when X"ad", X"1f" when X"ae", X"53" when X"af",
 
X"63" when X"b0", X"75" when X"b1", X"35" when X"b2", X"2c" when X"b3",
X"60" when X"b4", X"fd" when X"b5", X"27" when X"b6", X"d3" when X"b7",
X"94" when X"b8", X"a5" when X"b9", X"7c" when X"ba", X"a1" when X"bb",
X"05" when X"bc", X"58" when X"bd", X"2d" when X"be", X"bd" when X"bf",
 
X"d9" when X"c0", X"c7" when X"c1", X"af" when X"c2", X"6b" when X"c3",
X"54" when X"c4", X"0b" when X"c5", X"e0" when X"c6", X"38" when X"c7",
X"04" when X"c8", X"c8" when X"c9", X"9d" when X"ca", X"e7" when X"cb",
X"14" when X"cc", X"b1" when X"cd", X"87" when X"ce", X"9c" when X"cf",
 
X"df" when X"d0", X"6f" when X"d1", X"f9" when X"d2", X"da" when X"d3",
X"2a" when X"d4", X"c4" when X"d5", X"59" when X"d6", X"16" when X"d7",
X"74" when X"d8", X"91" when X"d9", X"ab" when X"da", X"26" when X"db",
X"61" when X"dc", X"76" when X"dd", X"34" when X"de", X"2b" when X"df",
 
X"ad" when X"e0", X"99" when X"e1", X"fb" when X"e2", X"72" when X"e3",
X"ec" when X"e4", X"33" when X"e5", X"12" when X"e6", X"de" when X"e7",
X"98" when X"e8", X"3b" when X"e9", X"c0" when X"ea", X"9b" when X"eb",
X"3e" when X"ec", X"18" when X"ed", X"10" when X"ee", X"3a" when X"ef",
 
X"56" when X"f0", X"e1" when X"f1", X"77" when X"f2", X"c9" when X"f3",
X"1e" when X"f4", X"9e" when X"f5", X"95" when X"f6", X"a3" when X"f7",
X"90" when X"f8", X"19" when X"f9", X"a8" when X"fa", X"6c" when X"fb",
X"09" when X"fc", X"d0" when X"fd", X"f0" when X"fe", X"86" when X"ff",
 
-- end sboxq
X"00" when others;
end phy;
/nfcc/trunk/snow/sboxr.vhdl
0,0 → 1,128
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity sboxr is
port (
di : in bit_vector (07 downto 00);
do : out bit_vector (07 downto 00)
);
end sboxr;
 
architecture phy of sboxr is
begin
with di(07 downto 00) select
do <=
-- start sboxr
X"63" when X"00", X"7c" when X"01", X"77" when X"02", X"7b" when X"03",
X"f2" when X"04", X"6b" when X"05", X"6f" when X"06", X"c5" when X"07",
X"30" when X"08", X"01" when X"09", X"67" when X"0a", X"2b" when X"0b",
X"fe" when X"0c", X"d7" when X"0d", X"ab" when X"0e", X"76" when X"0f",
 
X"ca" when X"10", X"82" when X"11", X"c9" when X"12", X"7d" when X"13",
X"fa" when X"14", X"59" when X"15", X"47" when X"16", X"f0" when X"17",
X"ad" when X"18", X"d4" when X"19", X"a2" when X"1a", X"af" when X"1b",
X"9c" when X"1c", X"a4" when X"1d", X"72" when X"1e", X"c0" when X"1f",
 
X"b7" when X"20", X"fd" when X"21", X"93" when X"22", X"26" when X"23",
X"36" when X"24", X"3f" when X"25", X"f7" when X"26", X"cc" when X"27",
X"34" when X"28", X"a5" when X"29", X"e5" when X"2a", X"f1" when X"2b",
X"71" when X"2c", X"d8" when X"2d", X"31" when X"2e", X"15" when X"2f",
 
X"04" when X"30", X"c7" when X"31", X"23" when X"32", X"c3" when X"33",
X"18" when X"34", X"96" when X"35", X"05" when X"36", X"9a" when X"37",
X"07" when X"38", X"12" when X"39", X"80" when X"3a", X"e2" when X"3b",
X"eb" when X"3c", X"27" when X"3d", X"b2" when X"3e", X"75" when X"3f",
 
X"09" when X"40", X"83" when X"41", X"2c" when X"42", X"1a" when X"43",
X"1b" when X"44", X"6e" when X"45", X"5a" when X"46", X"a0" when X"47",
X"52" when X"48", X"3b" when X"49", X"d6" when X"4a", X"b3" when X"4b",
X"29" when X"4c", X"e3" when X"4d", X"2f" when X"4e", X"84" when X"4f",
 
X"53" when X"50", X"d1" when X"51", X"00" when X"52", X"ed" when X"53",
X"20" when X"54", X"fc" when X"55", X"b1" when X"56", X"5b" when X"57",
X"6a" when X"58", X"cb" when X"59", X"be" when X"5a", X"39" when X"5b",
X"4a" when X"5c", X"4c" when X"5d", X"58" when X"5e", X"cf" when X"5f",
 
X"d0" when X"60", X"ef" when X"61", X"aa" when X"62", X"fb" when X"63",
X"43" when X"64", X"4d" when X"65", X"33" when X"66", X"85" when X"67",
X"45" when X"68", X"f9" when X"69", X"02" when X"6a", X"7f" when X"6b",
X"50" when X"6c", X"3c" when X"6d", X"9f" when X"6e", X"a8" when X"6f",
 
X"51" when X"70", X"a3" when X"71", X"40" when X"72", X"8f" when X"73",
X"92" when X"74", X"9d" when X"75", X"38" when X"76", X"f5" when X"77",
X"bc" when X"78", X"b6" when X"79", X"da" when X"7a", X"21" when X"7b",
X"10" when X"7c", X"ff" when X"7d", X"f3" when X"7e", X"d2" when X"7f",
 
X"cd" when X"80", X"0c" when X"81", X"13" when X"82", X"ec" when X"83",
X"5f" when X"84", X"97" when X"85", X"44" when X"86", X"17" when X"87",
X"c4" when X"88", X"a7" when X"89", X"7e" when X"8a", X"3d" when X"8b",
X"64" when X"8c", X"5d" when X"8d", X"19" when X"8e", X"73" when X"8f",
 
X"60" when X"90", X"81" when X"91", X"4f" when X"92", X"dc" when X"93",
X"22" when X"94", X"2a" when X"95", X"90" when X"96", X"88" when X"97",
X"46" when X"98", X"ee" when X"99", X"b8" when X"9a", X"14" when X"9b",
X"de" when X"9c", X"5e" when X"9d", X"0b" when X"9e", X"db" when X"9f",
 
X"e0" when X"a0", X"32" when X"a1", X"3a" when X"a2", X"0a" when X"a3",
X"49" when X"a4", X"06" when X"a5", X"24" when X"a6", X"5c" when X"a7",
X"c2" when X"a8", X"d3" when X"a9", X"ac" when X"aa", X"62" when X"ab",
X"91" when X"ac", X"95" when X"ad", X"e4" when X"ae", X"79" when X"af",
 
X"e7" when X"b0", X"c8" when X"b1", X"37" when X"b2", X"6d" when X"b3",
X"8d" when X"b4", X"d5" when X"b5", X"4e" when X"b6", X"a9" when X"b7",
X"6c" when X"b8", X"56" when X"b9", X"f4" when X"ba", X"ea" when X"bb",
X"65" when X"bc", X"7a" when X"bd", X"ae" when X"be", X"08" when X"bf",
 
X"ba" when X"c0", X"78" when X"c1", X"25" when X"c2", X"2e" when X"c3",
X"1c" when X"c4", X"a6" when X"c5", X"b4" when X"c6", X"c6" when X"c7",
X"e8" when X"c8", X"dd" when X"c9", X"74" when X"ca", X"1f" when X"cb",
X"4b" when X"cc", X"bd" when X"cd", X"8b" when X"ce", X"8a" when X"cf",
 
X"70" when X"d0", X"3e" when X"d1", X"b5" when X"d2", X"66" when X"d3",
X"48" when X"d4", X"03" when X"d5", X"f6" when X"d6", X"0e" when X"d7",
X"61" when X"d8", X"35" when X"d9", X"57" when X"da", X"b9" when X"db",
X"86" when X"dc", X"c1" when X"dd", X"1d" when X"de", X"9e" when X"df",
 
X"e1" when X"e0", X"f8" when X"e1", X"98" when X"e2", X"11" when X"e3",
X"69" when X"e4", X"d9" when X"e5", X"8e" when X"e6", X"94" when X"e7",
X"9b" when X"e8", X"1e" when X"e9", X"87" when X"ea", X"e9" when X"eb",
X"ce" when X"ec", X"55" when X"ed", X"28" when X"ee", X"df" when X"ef",
 
X"8c" when X"f0", X"a1" when X"f1", X"89" when X"f2", X"0d" when X"f3",
X"bf" when X"f4", X"e6" when X"f5", X"42" when X"f6", X"68" when X"f7",
X"41" when X"f8", X"99" when X"f9", X"2d" when X"fa", X"0f" when X"fb",
X"b0" when X"fc", X"54" when X"fd", X"bb" when X"fe", X"16" when X"ff",
 
-- end sboxr
X"00" when others;
end phy;
/nfcc/trunk/snow/mula.vhdl
0,0 → 1,127
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity mula is
port (
c : in bit_vector ( 7 downto 0);
w : out bit_vector ( 31 downto 0)
);
end mula;
 
architecture phy of mula is
begin
with c select
w <=
 
X"00000000" when X"00", X"e19fcf13" when X"01", X"6b973726" when X"02", X"8a08f835" when X"03",
X"d6876e4c" when X"04", X"3718a15f" when X"05", X"bd10596a" when X"06", X"5c8f9679" when X"07",
X"05a7dc98" when X"08", X"e438138b" when X"09", X"6e30ebbe" when X"0a", X"8faf24ad" when X"0b",
X"d320b2d4" when X"0c", X"32bf7dc7" when X"0d", X"b8b785f2" when X"0e", X"59284ae1" when X"0f",
 
X"0ae71199" when X"10", X"eb78de8a" when X"11", X"617026bf" when X"12", X"80efe9ac" when X"13",
X"dc607fd5" when X"14", X"3dffb0c6" when X"15", X"b7f748f3" when X"16", X"566887e0" when X"17",
X"0f40cd01" when X"18", X"eedf0212" when X"19", X"64d7fa27" when X"1a", X"85483534" when X"1b",
X"d9c7a34d" when X"1c", X"38586c5e" when X"1d", X"b250946b" when X"1e", X"53cf5b78" when X"1f",
 
X"1467229b" when X"20", X"f5f8ed88" when X"21", X"7ff015bd" when X"22", X"9e6fdaae" when X"23",
X"c2e04cd7" when X"24", X"237f83c4" when X"25", X"a9777bf1" when X"26", X"48e8b4e2" when X"27",
X"11c0fe03" when X"28", X"f05f3110" when X"29", X"7a57c925" when X"2a", X"9bc80636" when X"2b",
X"c747904f" when X"2c", X"26d85f5c" when X"2d", X"acd0a769" when X"2e", X"4d4f687a" when X"2f",
 
X"1e803302" when X"30", X"ff1ffc11" when X"31", X"75170424" when X"32", X"9488cb37" when X"33",
X"c8075d4e" when X"34", X"2998925d" when X"35", X"a3906a68" when X"36", X"420fa57b" when X"37",
X"1b27ef9a" when X"38", X"fab82089" when X"39", X"70b0d8bc" when X"3a", X"912f17af" when X"3b",
X"cda081d6" when X"3c", X"2c3f4ec5" when X"3d", X"a637b6f0" when X"3e", X"47a879e3" when X"3f",
 
X"28ce449f" when X"40", X"c9518b8c" when X"41", X"435973b9" when X"42", X"a2c6bcaa" when X"43",
X"fe492ad3" when X"44", X"1fd6e5c0" when X"45", X"95de1df5" when X"46", X"7441d2e6" when X"47",
X"2d699807" when X"48", X"ccf65714" when X"49", X"46feaf21" when X"4a", X"a7616032" when X"4b",
X"fbeef64b" when X"4c", X"1a713958" when X"4d", X"9079c16d" when X"4e", X"71e60e7e" when X"4f",
 
X"22295506" when X"50", X"c3b69a15" when X"51", X"49be6220" when X"52", X"a821ad33" when X"53",
X"f4ae3b4a" when X"54", X"1531f459" when X"55", X"9f390c6c" when X"56", X"7ea6c37f" when X"57",
X"278e899e" when X"58", X"c611468d" when X"59", X"4c19beb8" when X"5a", X"ad8671ab" when X"5b",
X"f109e7d2" when X"5c", X"109628c1" when X"5d", X"9a9ed0f4" when X"5e", X"7b011fe7" when X"5f",
 
X"3ca96604" when X"60", X"dd36a917" when X"61", X"573e5122" when X"62", X"b6a19e31" when X"63",
X"ea2e0848" when X"64", X"0bb1c75b" when X"65", X"81b93f6e" when X"66", X"6026f07d" when X"67",
X"390eba9c" when X"68", X"d891758f" when X"69", X"52998dba" when X"6a", X"b30642a9" when X"6b",
X"ef89d4d0" when X"6c", X"0e161bc3" when X"6d", X"841ee3f6" when X"6e", X"65812ce5" when X"6f",
 
X"364e779d" when X"70", X"d7d1b88e" when X"71", X"5dd940bb" when X"72", X"bc468fa8" when X"73",
X"e0c919d1" when X"74", X"0156d6c2" when X"75", X"8b5e2ef7" when X"76", X"6ac1e1e4" when X"77",
X"33e9ab05" when X"78", X"d2766416" when X"79", X"587e9c23" when X"7a", X"b9e15330" when X"7b",
X"e56ec549" when X"7c", X"04f10a5a" when X"7d", X"8ef9f26f" when X"7e", X"6f663d7c" when X"7f",
 
X"50358897" when X"80", X"b1aa4784" when X"81", X"3ba2bfb1" when X"82", X"da3d70a2" when X"83",
X"86b2e6db" when X"84", X"672d29c8" when X"85", X"ed25d1fd" when X"86", X"0cba1eee" when X"87",
X"5592540f" when X"88", X"b40d9b1c" when X"89", X"3e056329" when X"8a", X"df9aac3a" when X"8b",
X"83153a43" when X"8c", X"628af550" when X"8d", X"e8820d65" when X"8e", X"091dc276" when X"8f",
 
X"5ad2990e" when X"90", X"bb4d561d" when X"91", X"3145ae28" when X"92", X"d0da613b" when X"93",
X"8c55f742" when X"94", X"6dca3851" when X"95", X"e7c2c064" when X"96", X"065d0f77" when X"97",
X"5f754596" when X"98", X"beea8a85" when X"99", X"34e272b0" when X"9a", X"d57dbda3" when X"9b",
X"89f22bda" when X"9c", X"686de4c9" when X"9d", X"e2651cfc" when X"9e", X"03fad3ef" when X"9f",
 
X"4452aa0c" when X"a0", X"a5cd651f" when X"a1", X"2fc59d2a" when X"a2", X"ce5a5239" when X"a3",
X"92d5c440" when X"a4", X"734a0b53" when X"a5", X"f942f366" when X"a6", X"18dd3c75" when X"a7",
X"41f57694" when X"a8", X"a06ab987" when X"a9", X"2a6241b2" when X"aa", X"cbfd8ea1" when X"ab",
X"977218d8" when X"ac", X"76edd7cb" when X"ad", X"fce52ffe" when X"ae", X"1d7ae0ed" when X"af",
 
X"4eb5bb95" when X"b0", X"af2a7486" when X"b1", X"25228cb3" when X"b2", X"c4bd43a0" when X"b3",
X"9832d5d9" when X"b4", X"79ad1aca" when X"b5", X"f3a5e2ff" when X"b6", X"123a2dec" when X"b7",
X"4b12670d" when X"b8", X"aa8da81e" when X"b9", X"2085502b" when X"ba", X"c11a9f38" when X"bb",
X"9d950941" when X"bc", X"7c0ac652" when X"bd", X"f6023e67" when X"be", X"179df174" when X"bf",
 
X"78fbcc08" when X"c0", X"9964031b" when X"c1", X"136cfb2e" when X"c2", X"f2f3343d" when X"c3",
X"ae7ca244" when X"c4", X"4fe36d57" when X"c5", X"c5eb9562" when X"c6", X"24745a71" when X"c7",
X"7d5c1090" when X"c8", X"9cc3df83" when X"c9", X"16cb27b6" when X"ca", X"f754e8a5" when X"cb",
X"abdb7edc" when X"cc", X"4a44b1cf" when X"cd", X"c04c49fa" when X"ce", X"21d386e9" when X"cf",
 
X"721cdd91" when X"d0", X"93831282" when X"d1", X"198beab7" when X"d2", X"f81425a4" when X"d3",
X"a49bb3dd" when X"d4", X"45047cce" when X"d5", X"cf0c84fb" when X"d6", X"2e934be8" when X"d7",
X"77bb0109" when X"d8", X"9624ce1a" when X"d9", X"1c2c362f" when X"da", X"fdb3f93c" when X"db",
X"a13c6f45" when X"dc", X"40a3a056" when X"dd", X"caab5863" when X"de", X"2b349770" when X"df",
 
X"6c9cee93" when X"e0", X"8d032180" when X"e1", X"070bd9b5" when X"e2", X"e69416a6" when X"e3",
X"ba1b80df" when X"e4", X"5b844fcc" when X"e5", X"d18cb7f9" when X"e6", X"301378ea" when X"e7",
X"693b320b" when X"e8", X"88a4fd18" when X"e9", X"02ac052d" when X"ea", X"e333ca3e" when X"eb",
X"bfbc5c47" when X"ec", X"5e239354" when X"ed", X"d42b6b61" when X"ee", X"35b4a472" when X"ef",
 
X"667bff0a" when X"f0", X"87e43019" when X"f1", X"0decc82c" when X"f2", X"ec73073f" when X"f3",
X"b0fc9146" when X"f4", X"51635e55" when X"f5", X"db6ba660" when X"f6", X"3af46973" when X"f7",
X"63dc2392" when X"f8", X"8243ec81" when X"f9", X"084b14b4" when X"fa", X"e9d4dba7" when X"fb",
X"b55b4dde" when X"fc", X"54c482cd" when X"fd", X"decc7af8" when X"fe", X"3f53b5eb" when X"ff",
 
X"00000000" when others;
end phy;
/nfcc/trunk/snow/sboxs1.vhdl
0,0 → 1,154
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity sboxs1 is
port (
w : in bit_vector ( 31 downto 0);
r : out bit_vector ( 31 downto 0)
);
end sboxs1;
 
architecture phy of sboxs1 is
signal w0 : bit_vector ( 7 downto 0);
signal w1 : bit_vector ( 7 downto 0);
signal w2 : bit_vector ( 7 downto 0);
signal w3 : bit_vector ( 7 downto 0);
signal r0 : bit_vector ( 7 downto 0);
signal r1 : bit_vector ( 7 downto 0);
signal r2 : bit_vector ( 7 downto 0);
signal r3 : bit_vector ( 7 downto 0);
signal sr0i : bit_vector ( 7 downto 0);
signal sr1i : bit_vector ( 7 downto 0);
signal sr2i : bit_vector ( 7 downto 0);
signal sr3i : bit_vector ( 7 downto 0);
signal sr0o : bit_vector ( 7 downto 0);
signal sr1o : bit_vector ( 7 downto 0);
signal sr2o : bit_vector ( 7 downto 0);
signal sr3o : bit_vector ( 7 downto 0);
signal mlx0vi : bit_vector ( 7 downto 0);
signal mlx0ci : bit_vector ( 7 downto 0);
signal mlx0wo : bit_vector ( 7 downto 0);
signal mlx1vi : bit_vector ( 7 downto 0);
signal mlx1ci : bit_vector ( 7 downto 0);
signal mlx1wo : bit_vector ( 7 downto 0);
signal mlx2vi : bit_vector ( 7 downto 0);
signal mlx2ci : bit_vector ( 7 downto 0);
signal mlx2wo : bit_vector ( 7 downto 0);
signal mlx3vi : bit_vector ( 7 downto 0);
signal mlx3ci : bit_vector ( 7 downto 0);
signal mlx3wo : bit_vector ( 7 downto 0);
component sboxr
port (
di : in bit_vector ( 7 downto 0);
do : out bit_vector ( 7 downto 0)
);
end component;
component mulx
port (
V : in bit_vector ( 7 downto 0);
c : in bit_vector ( 7 downto 0);
w : out bit_Vector ( 7 downto 0)
);
end component;
begin
sr0 : sboxr
port map (
di => sr0i,
do => sr0o
);
sr1 : sboxr
port map (
di => sr1i,
do => sr1o
);
sr2 : sboxr
port map (
di => sr2i,
do => sr2o
);
sr3 : sboxr
port map (
di => sr3i,
do => sr3o
);
mlx0 : mulx
port map (
V => mlx0vi,
c => mlx0ci,
w => mlx0wo
);
mlx1 : mulx
port map (
V => mlx1vi,
c => mlx1ci,
w => mlx1wo
);
mlx2 : mulx
port map (
V => mlx2vi,
c => mlx2ci,
w => mlx2wo
);
mlx3 : mulx
port map (
V => mlx3vi,
c => mlx3ci,
w => mlx3wo
);
--persistent connection
w0 <= w ( 31 downto 24);
w1 <= w ( 23 downto 16);
w2 <= w ( 15 downto 8);
w3 <= w ( 7 downto 0);
sr0i <= w0;
sr1i <= w1;
sr2i <= w2;
sr3i <= w3;
mlx0vi <= sr0o; --SR(w0)
mlx1vi <= sr1o; --SR(w1)
mlx2vi <= sr2o; --SR(w2)
mlx3vi <= sr3o; --SR(w3)
mlx0ci <= X"1b";
mlx1ci <= X"1b";
mlx2ci <= X"1b";
mlx3ci <= X"1b";
r0 <= mlx0wo xor sr1o xor sr2o xor mlx3wo xor sr3o;
r1 <= mlx0wo xor sr0o xor mlx1wo xor sr2o xor sr3o;
r2 <= sr0o xor mlx1wo xor sr1o xor mlx2wo xor sr3o;
r3 <= sr0o xor sr1o xor mlx2wo xor sr2o xor mlx3wo;
r ( 31 downto 24)<= r0;
r ( 23 downto 16)<= r1;
r ( 15 downto 8)<= r2;
r ( 7 downto 0)<= r3;
--persistent connection
end phy;
/nfcc/trunk/snow/sboxs2.vhdl
0,0 → 1,154
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity sboxs2 is
port (
w : in bit_vector ( 31 downto 0);
r : out bit_vector ( 31 downto 0)
);
end sboxs2;
 
architecture phy of sboxs2 is
signal w0 : bit_vector ( 7 downto 0);
signal w1 : bit_vector ( 7 downto 0);
signal w2 : bit_vector ( 7 downto 0);
signal w3 : bit_vector ( 7 downto 0);
signal r0 : bit_vector ( 7 downto 0);
signal r1 : bit_vector ( 7 downto 0);
signal r2 : bit_vector ( 7 downto 0);
signal r3 : bit_vector ( 7 downto 0);
signal sq0i : bit_vector ( 7 downto 0);
signal sq1i : bit_vector ( 7 downto 0);
signal sq2i : bit_vector ( 7 downto 0);
signal sq3i : bit_vector ( 7 downto 0);
signal sq0o : bit_vector ( 7 downto 0);
signal sq1o : bit_vector ( 7 downto 0);
signal sq2o : bit_vector ( 7 downto 0);
signal sq3o : bit_vector ( 7 downto 0);
signal mlx0vi : bit_vector ( 7 downto 0);
signal mlx0ci : bit_vector ( 7 downto 0);
signal mlx0wo : bit_vector ( 7 downto 0);
signal mlx1vi : bit_vector ( 7 downto 0);
signal mlx1ci : bit_vector ( 7 downto 0);
signal mlx1wo : bit_vector ( 7 downto 0);
signal mlx2vi : bit_vector ( 7 downto 0);
signal mlx2ci : bit_vector ( 7 downto 0);
signal mlx2wo : bit_vector ( 7 downto 0);
signal mlx3vi : bit_vector ( 7 downto 0);
signal mlx3ci : bit_vector ( 7 downto 0);
signal mlx3wo : bit_vector ( 7 downto 0);
component sboxq
port (
di : in bit_vector ( 7 downto 0);
do : out bit_vector ( 7 downto 0)
);
end component;
component mulx
port (
V : in bit_vector ( 7 downto 0);
c : in bit_vector ( 7 downto 0);
w : out bit_Vector ( 7 downto 0)
);
end component;
begin
sq0 : sboxq
port map (
di => sq0i,
do => sq0o
);
sq1 : sboxq
port map (
di => sq1i,
do => sq1o
);
sq2 : sboxq
port map (
di => sq2i,
do => sq2o
);
sq3 : sboxq
port map (
di => sq3i,
do => sq3o
);
mlx0 : mulx
port map (
V => mlx0vi,
c => mlx0ci,
w => mlx0wo
);
mlx1 : mulx
port map (
V => mlx1vi,
c => mlx1ci,
w => mlx1wo
);
mlx2 : mulx
port map (
V => mlx2vi,
c => mlx2ci,
w => mlx2wo
);
mlx3 : mulx
port map (
V => mlx3vi,
c => mlx3ci,
w => mlx3wo
);
--persistent connection
w0 <= w ( 31 downto 24);
w1 <= w ( 23 downto 16);
w2 <= w ( 15 downto 8);
w3 <= w ( 7 downto 0);
sq0i <= w0;
sq1i <= w1;
sq2i <= w2;
sq3i <= w3;
mlx0vi <= sq0o; --SQ(w0)
mlx1vi <= sq1o; --SQ(w1)
mlx2vi <= sq2o; --SQ(w2)
mlx3vi <= sq3o; --SQ(w3)
mlx0ci <= X"69";
mlx1ci <= X"69";
mlx2ci <= X"69";
mlx3ci <= X"69";
r0 <= mlx0wo xor sq1o xor sq2o xor mlx3wo xor sq3o;
r1 <= mlx0wo xor sq0o xor mlx1wo xor sq2o xor sq3o;
r2 <= sq0o xor mlx1wo xor sq1o xor mlx2wo xor sq3o;
r3 <= sq0o xor sq1o xor mlx2wo xor sq2o xor mlx3wo;
r ( 31 downto 24)<= r0;
r ( 23 downto 16)<= r1;
r ( 15 downto 8)<= r2;
r ( 7 downto 0)<= r3;
--persistent connection
end phy;
/nfcc/trunk/snow/smap.vhdl
0,0 → 1,74
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
entity smap is
port (
lsfr : in bit_vector (511 downto 0);
s0 : out bit_vector ( 31 downto 0);
s1 : out bit_vector ( 31 downto 0);
s2 : out bit_vector ( 31 downto 0);
s3 : out bit_vector ( 31 downto 0);
s4 : out bit_vector ( 31 downto 0);
s5 : out bit_vector ( 31 downto 0);
s6 : out bit_vector ( 31 downto 0);
s7 : out bit_vector ( 31 downto 0);
s8 : out bit_vector ( 31 downto 0);
s9 : out bit_vector ( 31 downto 0);
sa : out bit_vector ( 31 downto 0);
sb : out bit_vector ( 31 downto 0);
sc : out bit_vector ( 31 downto 0);
sd : out bit_vector ( 31 downto 0);
se : out bit_vector ( 31 downto 0);
sf : out bit_vector ( 31 downto 0)
);
end smap;
 
architecture phy of smap is
begin
 
--persistent connection
s0 <= lsfr(511 downto 480);
s1 <= lsfr(479 downto 448);
s2 <= lsfr(447 downto 416);
s3 <= lsfr(415 downto 384);
s4 <= lsfr(383 downto 352);
s5 <= lsfr(351 downto 320);
s6 <= lsfr(319 downto 288);
s7 <= lsfr(287 downto 256);
s8 <= lsfr(255 downto 224);
s9 <= lsfr(223 downto 192);
sa <= lsfr(191 downto 160);
sb <= lsfr(159 downto 128);
sc <= lsfr(127 downto 96);
sd <= lsfr( 95 downto 64);
se <= lsfr( 63 downto 32);
sf <= lsfr( 31 downto 0);
--persistent connection
 
end phy;
/nfcc/trunk/snow/Makefile
0,0 → 1,119
#- ------------------------------------------------------------------------
#- Copyright (C) 2010 Arif Endro Nugroho
#- All rights reserved.
#-
#- Redistribution and use in source and binary forms, with or without
#- modification, are permitted provided that the following conditions
#- are met:
#-
#- 1. Redistributions of source code must retain the above copyright
#- notice, this list of conditions and the following disclaimer.
#- 2. Redistributions in binary form must reproduce the above copyright
#- notice, this list of conditions and the following disclaimer in the
#- documentation and/or other materials provided with the distribution.
#-
#- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
#- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
#- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
#- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
#- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
#- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
#- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
#- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
#- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
#- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
#- POSSIBILITY OF SUCH DAMAGE.
#-
#- End Of License.
#- ------------------------------------------------------------------------
#
# Need to FLATTENING the design before OCP and NERO
# Use x2y vst vst <source> <result>
# then flatlo -r <source> <result> # source is a result from x2y
# this two sequence will remove most warning/error message when
# performing LOON on the netlist.
#
# BOOM will optimize the logic
# BOOG will optimize/convert the logic into netlist
# LOON will optimize the netlist (this will report area/timing)
#
# VST is a circuit netlist file
# AP is a circuit placement file (OCP/NERO create this file)
# VBE is alliance VHDL Behavioral Description file
 
VASYFLAGS = -V -B -I vhdl -a -p -o
BOOMFLAGS = -VP
BOOGFLAGS =
LOONFLAGS =
OCPFLAGS = -v
NEROFLAGS = -V -G -6 -p
DRUCFLAGS =
S2RFLAGS = -v
OCP = ocp
NERO = nero
DRUC = druc
S2R = s2r
VASY = vasy
BOOM = boom
GENPAT = genpat -v
BOOG = boog
LOON = loon
RM = /bin/rm -vf
X2Y = x2y
FLATLO = flatlo
X2YFLAGS = vst vst
FLATLOFLAGS = -r
TOUCH = touch
 
# Set-up TARGET variable respectively
%.ap: TARGET = $(subst .ap,, $@)
%.pat: TARGET = $(subst .pat,, $@)
%.cif: TARGET = $(subst .cif,, $@)
%.vst: TARGET = $(subst .vst,, $@)
%.flt: TARGET = $(subst .flt,, $@)
%.sflt: TARGET = $(subst .sflt,, $@)
%.flatten: TARGET = $(subst .flatten,, $@)
 
all:
 
%.vbe: %.vhdl
@$(VASY) $(VASYFLAGS) $<
 
%.vst: %.vbe
@$(BOOM) $(BOOMFLAGS) $(TARGET) $(TARGET)_o
@$(BOOG) $(BOOGFLAGS) $(TARGET)_o
@$(LOON) $(LOONFLAGS) $(TARGET)_o $(TARGET)
-$(RM) $(TARGET)_o.*
 
%.sflt: %.vbe
# @$(BOOM) $(BOOMFLAGS) $(TARGET)_model $(TARGET)_model_o
@$(BOOG) $(BOOGFLAGS) $(TARGET)_model
# @$(BOOG) $(BOOGFLAGS) $(TARGET)_model_o
# @$(LOON) $(LOONFLAGS) $(TARGET)_model_o $(TARGET)_model
-$(RM) $(TARGET)_model_o.*
@$(X2Y) $(X2YFLAGS) $(TARGET) $(TARGET)_m
@$(FLATLO) $(FLATLOFLAGS) $(TARGET)_m $(TARGET)
# @$(FLATLO) $(FLATLOFLAGS) $(TARGET)_m $(TARGET)_o
# @$(LOON) $(LOONFLAGS) $(TARGET)_o $(TARGET)
-$(RM) $(TARGET){_o,m}.*
@$(TOUCH) $@
 
%.flt: %.vbe
@$(BOOM) $(BOOMFLAGS) $(TARGET)_model $(TARGET)_model_o
@$(BOOG) $(BOOGFLAGS) $(TARGET)_model_o
@$(LOON) $(LOONFLAGS) $(TARGET)_model_o $(TARGET)_model
-$(RM) $(TARGET)_model_o.*
@$(X2Y) $(X2YFLAGS) $(TARGET) $(TARGET)_m
@$(FLATLO) $(FLATLOFLAGS) $(TARGET)_m $(TARGET)_o
@$(LOON) $(LOONFLAGS) $(TARGET)_o $(TARGET)
-$(RM) $(TARGET){_o,m}.*
@$(TOUCH) $@
 
%.flatten: %.vst
@$(X2Y) $(X2YFLAGS) $(TARGET) $(TARGET)_m
@$(FLATLO) $(FLATLOFLAGS) $(TARGET)_m $(TARGET)_o
@$(LOON) $(LOONFLAGS) $(TARGET)_o $(TARGET)
-$(RM) $(TARGET){_o,m}.*
 
clean:
@rm -vf *.dat *.gpl *.vhd *.vbe *.boom *.vst *.xsc *.ap *.cif *.drc done.* *.flt *.sflt *_syn.pat *_sim.pat
/nfcc/trunk/snow/sboxq.c
0,0 → 1,43
#include <stdio.h>
#include "genpat.h"
 
char *inttostr(entier)
int entier;
{
char *str;
str = (char *) mbkalloc (32 * sizeof (char));
sprintf (str, "%d",entier);
return(str);
}
/*------------------------------*/
/* end of the description */
/*------------------------------*/
 
main ()
{
int i;
int cur_vect = 0;
 
DEF_GENPAT("sboxq");
SETTUNIT("ns");
 
/* interface */
DECLAR ("di" , ":2", "X", IN , "7 downto 0", "" );
DECLAR ("do" , ":2", "X", OUT, "7 downto 0", "" );
DECLAR ("vss", ":1", "B", IN , "" , "" );
DECLAR ("vdd", ":1", "B", IN , "" , "" );
 
AFFECT ("0", "vss", "0b0");
AFFECT ("0", "vdd", "0b1");
AFFECT ("0", "di", "0x00");
 
for (i=1; i<256; i++)
{
AFFECT ("+10", "di", inttostr(i) );
cur_vect++;
}
 
 
SAV_GENPAT ();
}
 
/nfcc/trunk/snow/sbox.pat
0,0 → 1,283
 
-- description generated by Pat driver
 
-- date : Fri Oct 16 18:19:58 2009
-- revision : v109
 
-- sequence : sbox
 
-- input / output list :
in di (7 downto 0) X;;;
out do (7 downto 0) X;;;
in vss B;;
in vdd B;;
 
begin
 
-- Pattern description :
 
-- d d v v
-- i o s d
-- s d
 
 
-- Beware : unprocessed patterns
 
< 0 ns> : 00 ?** 0 1 ;
< 10 ns> : 01 ?** 0 1 ;
< 20 ns> : 02 ?** 0 1 ;
< 30 ns> : 03 ?** 0 1 ;
< 40 ns> : 04 ?** 0 1 ;
< 50 ns> : 05 ?** 0 1 ;
< 60 ns> : 06 ?** 0 1 ;
< 70 ns> : 07 ?** 0 1 ;
< 80 ns> : 08 ?** 0 1 ;
< 90 ns> : 09 ?** 0 1 ;
< 100 ns> : 0a ?** 0 1 ;
< 110 ns> : 0b ?** 0 1 ;
< 120 ns> : 0c ?** 0 1 ;
< 130 ns> : 0d ?** 0 1 ;
< 140 ns> : 0e ?** 0 1 ;
< 150 ns> : 0f ?** 0 1 ;
< 160 ns> : 10 ?** 0 1 ;
< 170 ns> : 11 ?** 0 1 ;
< 180 ns> : 12 ?** 0 1 ;
< 190 ns> : 13 ?** 0 1 ;
< 200 ns> : 14 ?** 0 1 ;
< 210 ns> : 15 ?** 0 1 ;
< 220 ns> : 16 ?** 0 1 ;
< 230 ns> : 17 ?** 0 1 ;
< 240 ns> : 18 ?** 0 1 ;
< 250 ns> : 19 ?** 0 1 ;
< 260 ns> : 1a ?** 0 1 ;
< 270 ns> : 1b ?** 0 1 ;
< 280 ns> : 1c ?** 0 1 ;
< 290 ns> : 1d ?** 0 1 ;
< 300 ns> : 1e ?** 0 1 ;
< 310 ns> : 1f ?** 0 1 ;
< 320 ns> : 20 ?** 0 1 ;
< 330 ns> : 21 ?** 0 1 ;
< 340 ns> : 22 ?** 0 1 ;
< 350 ns> : 23 ?** 0 1 ;
< 360 ns> : 24 ?** 0 1 ;
< 370 ns> : 25 ?** 0 1 ;
< 380 ns> : 26 ?** 0 1 ;
< 390 ns> : 27 ?** 0 1 ;
< 400 ns> : 28 ?** 0 1 ;
< 410 ns> : 29 ?** 0 1 ;
< 420 ns> : 2a ?** 0 1 ;
< 430 ns> : 2b ?** 0 1 ;
< 440 ns> : 2c ?** 0 1 ;
< 450 ns> : 2d ?** 0 1 ;
< 460 ns> : 2e ?** 0 1 ;
< 470 ns> : 2f ?** 0 1 ;
< 480 ns> : 30 ?** 0 1 ;
< 490 ns> : 31 ?** 0 1 ;
< 500 ns> : 32 ?** 0 1 ;
< 510 ns> : 33 ?** 0 1 ;
< 520 ns> : 34 ?** 0 1 ;
< 530 ns> : 35 ?** 0 1 ;
< 540 ns> : 36 ?** 0 1 ;
< 550 ns> : 37 ?** 0 1 ;
< 560 ns> : 38 ?** 0 1 ;
< 570 ns> : 39 ?** 0 1 ;
< 580 ns> : 3a ?** 0 1 ;
< 590 ns> : 3b ?** 0 1 ;
< 600 ns> : 3c ?** 0 1 ;
< 610 ns> : 3d ?** 0 1 ;
< 620 ns> : 3e ?** 0 1 ;
< 630 ns> : 3f ?** 0 1 ;
< 640 ns> : 40 ?** 0 1 ;
< 650 ns> : 41 ?** 0 1 ;
< 660 ns> : 42 ?** 0 1 ;
< 670 ns> : 43 ?** 0 1 ;
< 680 ns> : 44 ?** 0 1 ;
< 690 ns> : 45 ?** 0 1 ;
< 700 ns> : 46 ?** 0 1 ;
< 710 ns> : 47 ?** 0 1 ;
< 720 ns> : 48 ?** 0 1 ;
< 730 ns> : 49 ?** 0 1 ;
< 740 ns> : 4a ?** 0 1 ;
< 750 ns> : 4b ?** 0 1 ;
< 760 ns> : 4c ?** 0 1 ;
< 770 ns> : 4d ?** 0 1 ;
< 780 ns> : 4e ?** 0 1 ;
< 790 ns> : 4f ?** 0 1 ;
< 800 ns> : 50 ?** 0 1 ;
< 810 ns> : 51 ?** 0 1 ;
< 820 ns> : 52 ?** 0 1 ;
< 830 ns> : 53 ?** 0 1 ;
< 840 ns> : 54 ?** 0 1 ;
< 850 ns> : 55 ?** 0 1 ;
< 860 ns> : 56 ?** 0 1 ;
< 870 ns> : 57 ?** 0 1 ;
< 880 ns> : 58 ?** 0 1 ;
< 890 ns> : 59 ?** 0 1 ;
< 900 ns> : 5a ?** 0 1 ;
< 910 ns> : 5b ?** 0 1 ;
< 920 ns> : 5c ?** 0 1 ;
< 930 ns> : 5d ?** 0 1 ;
< 940 ns> : 5e ?** 0 1 ;
< 950 ns> : 5f ?** 0 1 ;
< 960 ns> : 60 ?** 0 1 ;
< 970 ns> : 61 ?** 0 1 ;
< 980 ns> : 62 ?** 0 1 ;
< 990 ns> : 63 ?** 0 1 ;
< 1000 ns> : 64 ?** 0 1 ;
< 1010 ns> : 65 ?** 0 1 ;
< 1020 ns> : 66 ?** 0 1 ;
< 1030 ns> : 67 ?** 0 1 ;
< 1040 ns> : 68 ?** 0 1 ;
< 1050 ns> : 69 ?** 0 1 ;
< 1060 ns> : 6a ?** 0 1 ;
< 1070 ns> : 6b ?** 0 1 ;
< 1080 ns> : 6c ?** 0 1 ;
< 1090 ns> : 6d ?** 0 1 ;
< 1100 ns> : 6e ?** 0 1 ;
< 1110 ns> : 6f ?** 0 1 ;
< 1120 ns> : 70 ?** 0 1 ;
< 1130 ns> : 71 ?** 0 1 ;
< 1140 ns> : 72 ?** 0 1 ;
< 1150 ns> : 73 ?** 0 1 ;
< 1160 ns> : 74 ?** 0 1 ;
< 1170 ns> : 75 ?** 0 1 ;
< 1180 ns> : 76 ?** 0 1 ;
< 1190 ns> : 77 ?** 0 1 ;
< 1200 ns> : 78 ?** 0 1 ;
< 1210 ns> : 79 ?** 0 1 ;
< 1220 ns> : 7a ?** 0 1 ;
< 1230 ns> : 7b ?** 0 1 ;
< 1240 ns> : 7c ?** 0 1 ;
< 1250 ns> : 7d ?** 0 1 ;
< 1260 ns> : 7e ?** 0 1 ;
< 1270 ns> : 7f ?** 0 1 ;
< 1280 ns> : 80 ?** 0 1 ;
< 1290 ns> : 81 ?** 0 1 ;
< 1300 ns> : 82 ?** 0 1 ;
< 1310 ns> : 83 ?** 0 1 ;
< 1320 ns> : 84 ?** 0 1 ;
< 1330 ns> : 85 ?** 0 1 ;
< 1340 ns> : 86 ?** 0 1 ;
< 1350 ns> : 87 ?** 0 1 ;
< 1360 ns> : 88 ?** 0 1 ;
< 1370 ns> : 89 ?** 0 1 ;
< 1380 ns> : 8a ?** 0 1 ;
< 1390 ns> : 8b ?** 0 1 ;
< 1400 ns> : 8c ?** 0 1 ;
< 1410 ns> : 8d ?** 0 1 ;
< 1420 ns> : 8e ?** 0 1 ;
< 1430 ns> : 8f ?** 0 1 ;
< 1440 ns> : 90 ?** 0 1 ;
< 1450 ns> : 91 ?** 0 1 ;
< 1460 ns> : 92 ?** 0 1 ;
< 1470 ns> : 93 ?** 0 1 ;
< 1480 ns> : 94 ?** 0 1 ;
< 1490 ns> : 95 ?** 0 1 ;
< 1500 ns> : 96 ?** 0 1 ;
< 1510 ns> : 97 ?** 0 1 ;
< 1520 ns> : 98 ?** 0 1 ;
< 1530 ns> : 99 ?** 0 1 ;
< 1540 ns> : 9a ?** 0 1 ;
< 1550 ns> : 9b ?** 0 1 ;
< 1560 ns> : 9c ?** 0 1 ;
< 1570 ns> : 9d ?** 0 1 ;
< 1580 ns> : 9e ?** 0 1 ;
< 1590 ns> : 9f ?** 0 1 ;
< 1600 ns> : a0 ?** 0 1 ;
< 1610 ns> : a1 ?** 0 1 ;
< 1620 ns> : a2 ?** 0 1 ;
< 1630 ns> : a3 ?** 0 1 ;
< 1640 ns> : a4 ?** 0 1 ;
< 1650 ns> : a5 ?** 0 1 ;
< 1660 ns> : a6 ?** 0 1 ;
< 1670 ns> : a7 ?** 0 1 ;
< 1680 ns> : a8 ?** 0 1 ;
< 1690 ns> : a9 ?** 0 1 ;
< 1700 ns> : aa ?** 0 1 ;
< 1710 ns> : ab ?** 0 1 ;
< 1720 ns> : ac ?** 0 1 ;
< 1730 ns> : ad ?** 0 1 ;
< 1740 ns> : ae ?** 0 1 ;
< 1750 ns> : af ?** 0 1 ;
< 1760 ns> : b0 ?** 0 1 ;
< 1770 ns> : b1 ?** 0 1 ;
< 1780 ns> : b2 ?** 0 1 ;
< 1790 ns> : b3 ?** 0 1 ;
< 1800 ns> : b4 ?** 0 1 ;
< 1810 ns> : b5 ?** 0 1 ;
< 1820 ns> : b6 ?** 0 1 ;
< 1830 ns> : b7 ?** 0 1 ;
< 1840 ns> : b8 ?** 0 1 ;
< 1850 ns> : b9 ?** 0 1 ;
< 1860 ns> : ba ?** 0 1 ;
< 1870 ns> : bb ?** 0 1 ;
< 1880 ns> : bc ?** 0 1 ;
< 1890 ns> : bd ?** 0 1 ;
< 1900 ns> : be ?** 0 1 ;
< 1910 ns> : bf ?** 0 1 ;
< 1920 ns> : c0 ?** 0 1 ;
< 1930 ns> : c1 ?** 0 1 ;
< 1940 ns> : c2 ?** 0 1 ;
< 1950 ns> : c3 ?** 0 1 ;
< 1960 ns> : c4 ?** 0 1 ;
< 1970 ns> : c5 ?** 0 1 ;
< 1980 ns> : c6 ?** 0 1 ;
< 1990 ns> : c7 ?** 0 1 ;
< 2000 ns> : c8 ?** 0 1 ;
< 2010 ns> : c9 ?** 0 1 ;
< 2020 ns> : ca ?** 0 1 ;
< 2030 ns> : cb ?** 0 1 ;
< 2040 ns> : cc ?** 0 1 ;
< 2050 ns> : cd ?** 0 1 ;
< 2060 ns> : ce ?** 0 1 ;
< 2070 ns> : cf ?** 0 1 ;
< 2080 ns> : d0 ?** 0 1 ;
< 2090 ns> : d1 ?** 0 1 ;
< 2100 ns> : d2 ?** 0 1 ;
< 2110 ns> : d3 ?** 0 1 ;
< 2120 ns> : d4 ?** 0 1 ;
< 2130 ns> : d5 ?** 0 1 ;
< 2140 ns> : d6 ?** 0 1 ;
< 2150 ns> : d7 ?** 0 1 ;
< 2160 ns> : d8 ?** 0 1 ;
< 2170 ns> : d9 ?** 0 1 ;
< 2180 ns> : da ?** 0 1 ;
< 2190 ns> : db ?** 0 1 ;
< 2200 ns> : dc ?** 0 1 ;
< 2210 ns> : dd ?** 0 1 ;
< 2220 ns> : de ?** 0 1 ;
< 2230 ns> : df ?** 0 1 ;
< 2240 ns> : e0 ?** 0 1 ;
< 2250 ns> : e1 ?** 0 1 ;
< 2260 ns> : e2 ?** 0 1 ;
< 2270 ns> : e3 ?** 0 1 ;
< 2280 ns> : e4 ?** 0 1 ;
< 2290 ns> : e5 ?** 0 1 ;
< 2300 ns> : e6 ?** 0 1 ;
< 2310 ns> : e7 ?** 0 1 ;
< 2320 ns> : e8 ?** 0 1 ;
< 2330 ns> : e9 ?** 0 1 ;
< 2340 ns> : ea ?** 0 1 ;
< 2350 ns> : eb ?** 0 1 ;
< 2360 ns> : ec ?** 0 1 ;
< 2370 ns> : ed ?** 0 1 ;
< 2380 ns> : ee ?** 0 1 ;
< 2390 ns> : ef ?** 0 1 ;
< 2400 ns> : f0 ?** 0 1 ;
< 2410 ns> : f1 ?** 0 1 ;
< 2420 ns> : f2 ?** 0 1 ;
< 2430 ns> : f3 ?** 0 1 ;
< 2440 ns> : f4 ?** 0 1 ;
< 2450 ns> : f5 ?** 0 1 ;
< 2460 ns> : f6 ?** 0 1 ;
< 2470 ns> : f7 ?** 0 1 ;
< 2480 ns> : f8 ?** 0 1 ;
< 2490 ns> : f9 ?** 0 1 ;
< 2500 ns> : fa ?** 0 1 ;
< 2510 ns> : fb ?** 0 1 ;
< 2520 ns> : fc ?** 0 1 ;
< 2530 ns> : fd ?** 0 1 ;
< 2540 ns> : fe ?** 0 1 ;
< 2550 ns> : ff ?** 0 1 ;
 
end;
/nfcc/trunk/snow/sboxr.c
0,0 → 1,43
#include <stdio.h>
#include "genpat.h"
 
char *inttostr(entier)
int entier;
{
char *str;
str = (char *) mbkalloc (32 * sizeof (char));
sprintf (str, "%d",entier);
return(str);
}
/*------------------------------*/
/* end of the description */
/*------------------------------*/
 
main ()
{
int i;
int cur_vect = 0;
 
DEF_GENPAT("sboxr");
SETTUNIT("ns");
 
/* interface */
DECLAR ("di" , ":2", "X", IN , "7 downto 0", "" );
DECLAR ("do" , ":2", "X", OUT, "7 downto 0", "" );
DECLAR ("vss", ":1", "B", IN , "" , "" );
DECLAR ("vdd", ":1", "B", IN , "" , "" );
 
AFFECT ("0", "vss", "0b0");
AFFECT ("0", "vdd", "0b1");
AFFECT ("0", "di", "0x00");
 
for (i=1; i<256; i++)
{
AFFECT ("+10", "di", inttostr(i) );
cur_vect++;
}
 
 
SAV_GENPAT ();
}
 
/nfcc/trunk/camellia/c2b.vhdl
0,0 → 1,59
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity c2b is
port (
cnt : out bit_vector ( 1 downto 0);
clk : in bit;
rst : in bit
);
end c2b;
 
architecture phy of c2b is
signal sum : bit_vector ( 1 downto 0); -- sum
signal cr : bit_vector ( 1 downto 0); -- carry
begin
cr(0) <= '0'; -- LSB always zero
cr(1) <= sum(0);
process (clk)
begin
if (clk = '1' and clk'event) then
if (rst = '1') then
sum <= B"00";
else
sum <= ((sum xor B"01") xor cr); -- sum = ((addend xor augend) xor carry)
end if;
end if;
end process;
cnt <= sum;
end phy;
/nfcc/trunk/camellia/camellia.vhdl
0,0 → 1,334
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
-- 128 64 0
-- Ln Rn
--
-- L_{r} = R_{r-1} xor F(L_{r-1}, k_r)
-- R_{r} = L_{r-1}
 
-- because P-function working in 64 bit field, then the minimum block is 64.
entity camellia is
port (
pt : in bit_vector ( 63 downto 0);
key : in bit_vector ( 63 downto 0);
Nk : in bit_vector ( 3 downto 0);
ldpt : in bit;
ct : out bit_vector ( 63 downto 0);
--probe
--r_prb : out bit_vector ( 63 downto 0);
--l_prb : out bit_vector ( 63 downto 0);
--s_prb : out bit_vector ( 63 downto 0);
--z_prb : out bit_vector ( 63 downto 0);
--fla_prb : out bit_vector ( 63 downto 0);
--ir_prb : out bit_vector ( 63 downto 0);
--il_prb : out bit_vector ( 63 downto 0);
--rc_prb : out bit_vector ( 2 downto 0);
--probe
v : out bit;
clk : in bit;
rst : in bit
);
end camellia;
 
architecture phy of camellia is
 
signal ireg1 : bit_vector (127 downto 0);
signal ikey : bit_vector ( 63 downto 0);
signal ipt : bit_vector ( 63 downto 0);
signal iptt : bit_vector ( 63 downto 0);
signal f : bit_vector ( 63 downto 0);
signal l : bit_vector ( 63 downto 0);
signal r : bit_vector ( 63 downto 0);
signal ri : bit_vector ( 63 downto 0);
signal il : bit_vector ( 63 downto 0);
signal ir : bit_vector ( 63 downto 0);
signal fl1 : bit_vector ( 63 downto 0);
signal fl1i : bit_vector ( 63 downto 0);
signal fl2 : bit_vector ( 63 downto 0);
signal flx : bit_vector ( 31 downto 0);
signal fla : bit_vector ( 63 downto 0);
signal flb : bit_vector ( 63 downto 0);
signal s1i : bit_vector ( 7 downto 0);
signal s2i : bit_vector ( 7 downto 0);
signal s2t : bit_vector ( 7 downto 0);
signal s3i : bit_vector ( 7 downto 0);
signal s4i : bit_vector ( 7 downto 0);
signal s5i : bit_vector ( 7 downto 0);
signal s5t : bit_vector ( 7 downto 0);
signal s6i : bit_vector ( 7 downto 0);
signal s7i : bit_vector ( 7 downto 0);
signal s8i : bit_vector ( 7 downto 0);
signal s1o : bit_vector ( 7 downto 0);
signal s2o : bit_vector ( 7 downto 0);
signal s3o : bit_vector ( 7 downto 0);
signal s4o : bit_vector ( 7 downto 0);
signal s5o : bit_vector ( 7 downto 0);
signal s6o : bit_vector ( 7 downto 0);
signal s7o : bit_vector ( 7 downto 0);
signal s8o : bit_vector ( 7 downto 0);
signal z1 : bit_vector ( 7 downto 0);
signal z2 : bit_vector ( 7 downto 0);
signal z3 : bit_vector ( 7 downto 0);
signal z4 : bit_vector ( 7 downto 0);
signal z5 : bit_vector ( 7 downto 0);
signal z6 : bit_vector ( 7 downto 0);
signal z7 : bit_vector ( 7 downto 0);
signal z8 : bit_vector ( 7 downto 0);
signal c2b : bit_vector ( 1 downto 0);
signal c2b_cr : bit_vector ( 1 downto 0);
signal c3b : bit_vector ( 2 downto 0);
signal c3b_cr : bit_vector ( 2 downto 0);
signal c3b_rst : bit;
signal c2b_rst : bit;
signal rc : bit;
signal vld4 : bit;
signal vld8 : bit;
signal ildpt : bit;
signal ildptt : bit;
signal ildpt_rst : bit;
 
component sbox
port (
di : in bit_vector ( 7 downto 0);
do : out bit_vector ( 7 downto 0)
);
end component;
 
begin
 
sb1 : sbox
port map (
di => s1i,
do => s1o
);
sb2 : sbox
port map (
di => s2i,
do => s2o
);
sb3 : sbox
port map (
di => s3i,
do => s3o
);
sb4 : sbox
port map (
di => s4i,
do => s4o
);
sb5 : sbox
port map (
di => s5i,
do => s5o
);
sb6 : sbox
port map (
di => s6i,
do => s6o
);
sb7 : sbox
port map (
di => s7i,
do => s7o
);
sb8 : sbox
port map (
di => s8i,
do => s8o
);
 
--probe
--r_prb <= r;
--l_prb <= l;
--fla_prb <= fla;
--ir_prb <= ir;
--il_prb <= il;
--rc_prb <= c3b;
--s_prb <= s8i & s7i & s6i & s5i & s4i & s3i & s2i & s1i;
--z_prb <= z1 & z2 & z3 & z4 & z5 & z6 & z7 & z8 ;
--probe
 
c3b_cr(0) <= '0'; -- LSB always zero
c3b_cr( 2 downto 1) <= ( ((c3b( 1 downto 0) and B"01") or (c3b( 1 downto 0) and c3b_cr( 1 downto 0))) or (B"01" and c3b_cr( 1 downto 0)) );
 
process (clk)
begin
if (clk = '1' and clk'event) then
if (c3b_rst = '1') then
c3b <= B"000";
else
c3b <= ((c3b xor B"001") xor c3b_cr);
end if;
end if;
end process;
 
c2b_cr(0) <= '0'; -- LSB always zero
c2b_cr(1) <= c2b(0);
 
process (clk)
begin
if (clk = '1' and clk'event) then
if (c2b_rst = '1') then
c2b <= B"00";
elsif (rc = '1') then
c2b <= ((c2b xor B"01") xor c2b_cr);
end if;
end if;
end process;
 
process (clk)
begin
if ((clk = '1') and clk'event) then
if (rst = '1') then
ildpt <= '0';
ildptt <= '0';
ipt <= (others => '0');
ikey <= (others => '0');
fl1i <= (others => '0');
iptt <= (others => '0');
ri <= (others => '0');
else
ildptt <= ldpt;
ildpt <= ildptt;
fl1i <= fl1;
iptt <= pt;
ipt <= iptt;
ikey <= key;
ri <= r;
end if;
end if;
end process;
 
rc <= not(not(c3b(2)) or not(c3b(1)) or not(c3b(0))); -- B"111" -- count until 7 ( 8 clock cycle)
ildpt_rst <= ((ildpt xor ildptt) and ildpt);
c3b_rst <= rst or ildpt_rst or rc ;
c2b_rst <= rst or ildpt_rst;
 
--L_{r} == R_{r-1} xor F(L_{r-1}, kr)
--R_{r} == L_{r-1}
 
l <= ireg1(127 downto 64) ;
r <= ireg1( 63 downto 0) ;
 
s1i <= l ( 7 downto 0) xor ikey( 7 downto 0);
s2t <= l ( 15 downto 8) xor ikey(15 downto 8);
s2i <= s2t(6 downto 0) & s2t(7);
s3i <= l ( 23 downto 16) xor ikey(23 downto 16);
s4i <= l ( 31 downto 24) xor ikey(31 downto 24);-- SBOX4(ROTL1x)
s5t <= l ( 39 downto 32) xor ikey(39 downto 32);
s5i <= s5t(6 downto 0) & s5t(7);
s6i <= l ( 47 downto 40) xor ikey(47 downto 40);
s7i <= l ( 55 downto 48) xor ikey(55 downto 48);-- SBOX4(ROTL1x)
s8i <= l ( 63 downto 56) xor ikey(63 downto 56);
 
--S-function
 
z8 <= s1o; -- SBOX1
z7 <= s2o; -- SBOX4(ROTL1x)
z6 <= s3o(0) & s3o(7 downto 1); -- SBOX3 ROTR1
z5 <= s4o(6 downto 0) & s4o(7); -- SBOX2 ROTL1
z4 <= s5o; -- SBOX4(ROTL1x)
z3 <= s6o(0) & s6o(7 downto 1); -- SBOX3 ROTR1
z2 <= s7o(6 downto 0) & s7o(7); -- SBOX2 ROTL1
z1 <= s8o; -- SBOX1
 
--P-function
--z'1 == z1 xor z3 xor z4 xor z6 xor z7 xor z8
--z'2 == z1 xor z2 xor z4 xor z5 xor z7 xor z8
--z'3 == z1 xor z2 xor z3 xor z5 xor z6 xor z8
--z'4 == z2 xor z3 xor z4 xor z5 xor z6 xor z7
--z'5 == z1 xor z2 xor z6 xor z7 xor z8
--z'6 == z2 xor z3 xor z5 xor z7 xor z8
--z'7 == z3 xor z4 xor z5 xor z6 xor z8
--z'8 == z1 xor z4 xor z5 xor z6 xor z7
 
f (63 downto 56) <= z1 xor z3 xor z4 xor z6 xor z7 xor z8 ;
f (55 downto 48) <= z1 xor z2 xor z4 xor z5 xor z7 xor z8 ;
f (47 downto 40) <= z1 xor z2 xor z3 xor z5 xor z6 xor z8 ;
f (39 downto 32) <= z2 xor z3 xor z4 xor z5 xor z6 xor z7 ;
f (31 downto 24) <= z1 xor z2 xor z6 xor z7 xor z8 ;
f (23 downto 16) <= z2 xor z3 xor z5 xor z7 xor z8 ;
f (15 downto 8) <= z3 xor z4 xor z5 xor z6 xor z8 ;
f ( 7 downto 0) <= z1 xor z4 xor z5 xor z6 xor z7 ;
 
--F-function
 
fla <= r xor f;
 
--FL1-function
--Xi(64) == XL(32) & XR(32)
--Ki(64) == KL(32) & KR(32)
--Yr(32) == ((XL and Kl) <<< 1) xor XR
--Yl(32) == ( Yr or Kr) xor XL
--Yi(64) == Yl(32) & Yr(32)
fl1(31 downto 0)<= ((( l (62 downto 32) and ikey(62 downto 32)) & ( l (63) and ikey(63))) xor l (31 downto 0));
--fl1(31 downto 0)<= ((((fla(62 downto 32) and ikey(62 downto 32)) & (fla(63) and ikey(32))) xor fla(31 downto 0)) or ikey(31 downto 0)) xor fla(63 downto 32);
fl1(63 downto 32)<= (fl1(31 downto 0) or ikey(31 downto 0)) xor l (63 downto 32);
 
il <= fla when rc = '0' else fl1i;
 
--FL2-function
--Yi(64) == YL(32) & YR(32)
--Ki(64) == KL(32) & KR(32)
--Xl(32) == ( Yr or Kr) xor YL
--Xr(32) == ((Xl and Kl) <<< 1) xor YR
--Xi(64) == Xl(32) & Xr(32)
fl2(63 downto 32)<= ((ri(31 downto 0) or ikey(31 downto 0)) xor ri(63 downto 32));
flx(31 downto 0)<= (((ri(31 downto 0) or ikey(31 downto 0)) xor ri(63 downto 32)) and ikey(63 downto 32));
fl2(31 downto 0)<= (( flx(30 downto 0) & flx(31) ) xor ri(31 downto 0));
 
ir <= l when rc = '0' else fl2;
 
process (clk)
begin
if ((clk = '1') and clk'event) then
if (rst = '1') then
ireg1(127 downto 0) <= (others => '0') ;
elsif (ildpt = '1') then
ireg1(127 downto 0) <= ireg1( 63 downto 0) & (ipt xor ikey); -- initial round 2 clock
else
ireg1( 63 downto 0) <= ir ;
ireg1(127 downto 64) <= il ;
end if;
end if;
end process;
 
-- this valid signal for Nk=4 2 round (8 clock) plus the next 6-7 (the last two clock of its round) approx: 24 clock for each block
vld4 <= not(not(c2b(1)) or c2b(0) ) and (not(not(c3b(2)) or not(c3b(1)) or not(c3b(0))) or not(not(c3b(2)) or not(c3b(1)) or c3b(0)));
-- this valid signal for Nk=6/8 3 round (8 clock) plus the next 6-7 (the last two clock of its round) aprrox: 32 clock for each block
vld8 <= not(not(c2b(1)) or not(c2b(0))) and (not(not(c3b(2)) or not(c3b(1)) or not(c3b(0))) or not(not(c3b(2)) or not(c3b(1)) or c3b(0)));
ct <= r xor ikey ;
v <= vld4 when (not(Nk(3) or not(Nk(2)) or Nk(1) or Nk(0)) = '1') else vld8;
 
end phy;
/nfcc/trunk/camellia/keyscheduler.vhdl
0,0 → 1,350
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
-- 128-bit key K:
-- KL = K; KR = 0;
 
-- 192-bit key K:
-- KL = K >> 64;
-- KR = ((K & MASK64) << 64) | (~(K & MASK64));
 
-- 256-bit key K:
-- KL = K >> 128;
-- KR = K & MASK128;
 
-- The 128-bit variables KA and KB are generated from KL and KR as
-- follows. Note that KB is used only if the length of the secret key
-- is 192 or 256 bits. D1 and D2 are 64-bit temporary variables. F-
-- function is described in Section 2.4.
 
-- D1 = (KL ^ KR) >> 64;
-- D2 = (KL ^ KR) & MASK64;
-- D2 = D2 ^ F(D1, Sigma1);
-- D1 = D1 ^ F(D2, Sigma2);
-- D1 = D1 ^ (KL >> 64);
-- D2 = D2 ^ (KL & MASK64);
-- D2 = D2 ^ F(D1, Sigma3);
-- D1 = D1 ^ F(D2, Sigma4);
-- KA = (D1 << 64) | D2;
-- D1 = (KA ^ KR) >> 64;
-- D2 = (KA ^ KR) & MASK64;
-- D2 = D2 ^ F(D1, Sigma5);
-- D1 = D1 ^ F(D2, Sigma6);
-- KB = (D1 << 64) | D2;
 
-- The 64-bit constants Sigma1, Sigma2, ..., Sigma6 are used as "keys"
-- in the F-function. These constant values are, in hexadecimal
-- notation, as follows.
 
-- Sigma1 = 0xA09E667F3BCC908B;
-- Sigma2 = 0xB67AE8584CAA73B2;
-- Sigma3 = 0xC6EF372FE94F82BE;
-- Sigma4 = 0x54FF53A5F1D36F1C;
-- Sigma5 = 0x10E527FADE682D1D;
-- Sigma6 = 0xB05688C2B3E6C1FD;
 
-- 64-bit subkeys are generated by rotating KL, KR, KA, and KB and
-- taking the left- or right-half of them.
 
-- For 128-bit keys, 64-bit subkeys kw1, ..., kw4, k1, ..., k18,
-- ke1, ..., ke4 are generated as follows.
 
-- kw1 = (KL <<< 0) >> 64;
-- kw2 = (KL <<< 0) & MASK64;
-- k1 = (KA <<< 0) >> 64;
-- k2 = (KA <<< 0) & MASK64;
-- k3 = (KL <<< 15) >> 64;
-- k4 = (KL <<< 15) & MASK64;
-- k5 = (KA <<< 15) >> 64;
-- k6 = (KA <<< 15) & MASK64;
-- ke1 = (KA <<< 30) >> 64;
-- ke2 = (KA <<< 30) & MASK64;
-- k7 = (KL <<< 45) >> 64;
-- k8 = (KL <<< 45) & MASK64;
-- k9 = (KA <<< 45) >> 64;
-- k10 = (KL <<< 60) & MASK64;
-- k11 = (KA <<< 60) >> 64;
-- k12 = (KA <<< 60) & MASK64;
-- ke3 = (KL <<< 77) >> 64;
-- ke4 = (KL <<< 77) & MASK64;
-- k13 = (KL <<< 94) >> 64;
-- k14 = (KL <<< 94) & MASK64;
-- k15 = (KA <<< 94) >> 64;
-- k16 = (KA <<< 94) & MASK64;
-- k17 = (KL <<< 111) >> 64;
-- k18 = (KL <<< 111) & MASK64;
-- kw3 = (KA <<< 111) >> 64;
-- kw4 = (KA <<< 111) & MASK64;
 
-- For 192- and 256-bit keys, 64-bit subkeys kw1, ..., kw4, k1, ...,
-- k24, ke1, ..., ke6 are generated as follows.
 
-- kw1 = (KL <<< 0) >> 64;
-- kw2 = (KL <<< 0) & MASK64;
-- k1 = (KB <<< 0) >> 64;
-- k2 = (KB <<< 0) & MASK64;
-- k3 = (KR <<< 15) >> 64;
-- k4 = (KR <<< 15) & MASK64;
-- k5 = (KA <<< 15) >> 64;
-- k6 = (KA <<< 15) & MASK64;
-- ke1 = (KR <<< 30) >> 64;
-- ke2 = (KR <<< 30) & MASK64;
-- k7 = (KB <<< 30) >> 64;
-- k8 = (KB <<< 30) & MASK64;
-- k9 = (KL <<< 45) >> 64;
-- k10 = (KL <<< 45) & MASK64;
-- k11 = (KA <<< 45) >> 64;
-- k12 = (KA <<< 45) & MASK64;
-- ke3 = (KL <<< 60) >> 64;
-- ke4 = (KL <<< 60) & MASK64;
-- k13 = (KR <<< 60) >> 64;
-- k14 = (KR <<< 60) & MASK64;
-- k15 = (KB <<< 60) >> 64;
-- k16 = (KB <<< 60) & MASK64;
-- k17 = (KL <<< 77) >> 64;
-- k18 = (KL <<< 77) & MASK64;
-- ke5 = (KA <<< 77) >> 64;
-- ke6 = (KA <<< 77) & MASK64;
-- k19 = (KR <<< 94) >> 64;
-- k20 = (KR <<< 94) & MASK64;
-- k21 = (KA <<< 94) >> 64;
-- k22 = (KA <<< 94) & MASK64;
-- k23 = (KL <<< 111) >> 64;
-- k24 = (KL <<< 111) & MASK64;
-- kw3 = (KB <<< 111) >> 64;
-- kw4 = (KB <<< 111) & MASK64;
 
entity keyscheduler is
port (
key : in bit_vector ( 63 downto 0);
Nk : in bit_vector ( 3 downto 0);
ldk : in bit;
w : out bit_vector ( 63 downto 0);
v : out bit;
clk : in bit;
rst : in bit
);
end keyscheduler;
 
architecture phy of keyscheduler is
 
constant sigma1 : bit_vector ( 63 downto 0) := X"a09e667f3bcc908b";
constant sigma2 : bit_vector ( 63 downto 0) := X"b67ae8584caa73b2";
constant sigma3 : bit_vector ( 63 downto 0) := X"c6ef372fe94f82be";
constant sigma4 : bit_vector ( 63 downto 0) := X"54ff53a5f1d36f1c";
constant sigma5 : bit_vector ( 63 downto 0) := X"10e527fade682d1d";
constant sigma6 : bit_vector ( 63 downto 0) := X"b05688c2b3e6c1fd";
signal lsfr : bit_vector (383 downto 0); -- constant sigma 1-6
signal sigma : bit_vector ( 63 downto 0);
signal ireg1 : bit_vector (127 downto 0);
signal ikey : bit_vector ( 63 downto 0);
signal f : bit_vector ( 63 downto 0);
signal l : bit_vector ( 63 downto 0);
signal r : bit_vector ( 63 downto 0);
signal fla : bit_vector ( 63 downto 0);
signal s1i : bit_vector ( 7 downto 0);
signal s2i : bit_vector ( 7 downto 0);
signal s2t : bit_vector ( 7 downto 0);
signal s3i : bit_vector ( 7 downto 0);
signal s4i : bit_vector ( 7 downto 0);
signal s5i : bit_vector ( 7 downto 0);
signal s5t : bit_vector ( 7 downto 0);
signal s6i : bit_vector ( 7 downto 0);
signal s7i : bit_vector ( 7 downto 0);
signal s8i : bit_vector ( 7 downto 0);
signal s1o : bit_vector ( 7 downto 0);
signal s2o : bit_vector ( 7 downto 0);
signal s3o : bit_vector ( 7 downto 0);
signal s4o : bit_vector ( 7 downto 0);
signal s5o : bit_vector ( 7 downto 0);
signal s6o : bit_vector ( 7 downto 0);
signal s7o : bit_vector ( 7 downto 0);
signal s8o : bit_vector ( 7 downto 0);
signal z1 : bit_vector ( 7 downto 0);
signal z2 : bit_vector ( 7 downto 0);
signal z3 : bit_vector ( 7 downto 0);
signal z4 : bit_vector ( 7 downto 0);
signal z5 : bit_vector ( 7 downto 0);
signal z6 : bit_vector ( 7 downto 0);
signal z7 : bit_vector ( 7 downto 0);
signal z8 : bit_vector ( 7 downto 0);
signal ildk : bit;
signal shift : bit;
 
component sbox
port (
di : in bit_vector ( 7 downto 0);
do : out bit_vector ( 7 downto 0)
);
end component;
 
begin
 
sb1 : sbox
port map (
di => s1i,
do => s1o
);
sb2 : sbox
port map (
di => s2i,
do => s2o
);
sb3 : sbox
port map (
di => s3i,
do => s3o
);
sb4 : sbox
port map (
di => s4i,
do => s4o
);
sb5 : sbox
port map (
di => s5i,
do => s5o
);
sb6 : sbox
port map (
di => s6i,
do => s6o
);
sb7 : sbox
port map (
di => s7i,
do => s7o
);
sb8 : sbox
port map (
di => s8i,
do => s8o
);
 
--L_{r} == R_{r-1} xor F(L_{r-1}, kr)
--R_{r} == L_{r-1}
 
l <= ireg1(127 downto 64);
r <= ireg1( 63 downto 0);
sigma <= lsfr (383 downto 320);
 
s1i <= l ( 7 downto 0) xor sigma( 7 downto 0);
s2t <= l ( 15 downto 8) xor sigma(15 downto 8);
s2i <= s2t(6 downto 0) & s2t(7);
s3i <= l ( 23 downto 16) xor sigma(23 downto 16);
s4i <= l ( 31 downto 24) xor sigma(31 downto 24);-- SBOX4(ROTL1x)
s5t <= l ( 39 downto 32) xor sigma(39 downto 32);
s5i <= s5t(6 downto 0) & s5t(7);
s6i <= l ( 47 downto 40) xor sigma(47 downto 40);
s7i <= l ( 55 downto 48) xor sigma(55 downto 48);-- SBOX4(ROTL1x)
s8i <= l ( 63 downto 56) xor sigma(63 downto 56);
 
--S-function
 
z8 <= s1o; -- SBOX1
z7 <= s2o; -- SBOX4(ROTL1x)
z6 <= s3o(0) & s3o(7 downto 1); -- SBOX3 ROTR1
z5 <= s4o(6 downto 0) & s4o(7); -- SBOX2 ROTL1
z4 <= s5o; -- SBOX4(ROTL1x)
z3 <= s6o(0) & s6o(7 downto 1); -- SBOX3 ROTR1
z2 <= s7o(6 downto 0) & s7o(7); -- SBOX2 ROTL1
z1 <= s8o; -- SBOX1
 
--P-function
--z'1 == z1 xor z3 xor z4 xor z6 xor z7 xor z8
--z'2 == z1 xor z2 xor z4 xor z5 xor z7 xor z8
--z'3 == z1 xor z2 xor z3 xor z5 xor z6 xor z8
--z'4 == z2 xor z3 xor z4 xor z5 xor z6 xor z7
--z'5 == z1 xor z2 xor z6 xor z7 xor z8
--z'6 == z2 xor z3 xor z5 xor z7 xor z8
--z'7 == z3 xor z4 xor z5 xor z6 xor z8
--z'8 == z1 xor z4 xor z5 xor z6 xor z7
 
f (63 downto 56) <= z1 xor z3 xor z4 xor z6 xor z7 xor z8 ;
f (55 downto 48) <= z1 xor z2 xor z4 xor z5 xor z7 xor z8 ;
f (47 downto 40) <= z1 xor z2 xor z3 xor z5 xor z6 xor z8 ;
f (39 downto 32) <= z2 xor z3 xor z4 xor z5 xor z6 xor z7 ;
f (31 downto 24) <= z1 xor z2 xor z6 xor z7 xor z8 ;
f (23 downto 16) <= z2 xor z3 xor z5 xor z7 xor z8 ;
f (15 downto 8) <= z3 xor z4 xor z5 xor z6 xor z8 ;
f ( 7 downto 0) <= z1 xor z4 xor z5 xor z6 xor z7 ;
 
--F-function
 
fla <= r xor f;
 
process (clk)
begin
if ((clk = '1') and clk'event) then
if (rst = '1') then
ikey <= (others => '0');
ildk <= '0';
shift <= '0';
else
ikey <= key;
ildk <= ldk;
shift <= '1';
end if;
end if;
end process;
 
process (clk)
begin
if ((clk = '1') and clk'event) then
if (rst = '1') then
lsfr(383 downto 320) <= sigma1;
lsfr(319 downto 256) <= sigma2;
lsfr(255 downto 192) <= sigma3;
lsfr(191 downto 128) <= sigma4;
lsfr(127 downto 64) <= sigma5;
lsfr( 63 downto 0) <= sigma6;
elsif (shift = '1') then
lsfr <= lsfr (319 downto 0) & lsfr ( 383 downto 320);
end if;
end if;
end process;
 
process (clk)
begin
if ((clk = '1') and clk'event) then
if (rst = '1') then
ireg1(127 downto 0) <= (others => '0') ;
elsif (ildk = '1') then
ireg1(127 downto 0) <= ireg1( 63 downto 0) & ikey; -- initial round 2-4 clock
else
ireg1( 63 downto 0) <= r ;
ireg1(127 downto 64) <= l ;
end if;
end if;
end process;
 
v <= '0';
w <= fla when v = '0' else (others => '0');
 
end phy;
/nfcc/trunk/camellia/pt.lst
0,0 → 1,2
0x0123456789abcdef
0xfedcba9876543210
/nfcc/trunk/camellia/sbox.vhdl
0,0 → 1,82
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity sbox is
port (
di : in bit_vector ( 7 downto 0);
do : out bit_vector ( 7 downto 0)
);
end sbox;
 
architecture phy of sbox is
begin
with di( 7 downto 0) select
do <=
-- start sbox
 
X"70" when X"00", X"82" when X"01", X"2c" when X"02", X"ec" when X"03", X"b3" when X"04", X"27" when X"05", X"c0" when X"06", X"e5" when X"07",
X"e4" when X"08", X"85" when X"09", X"57" when X"0a", X"35" when X"0b", X"ea" when X"0c", X"0c" when X"0d", X"ae" when X"0e", X"41" when X"0f",
X"23" when X"10", X"ef" when X"11", X"6b" when X"12", X"93" when X"13", X"45" when X"14", X"19" when X"15", X"a5" when X"16", X"21" when X"17",
X"ed" when X"18", X"0e" when X"19", X"4f" when X"1a", X"4e" when X"1b", X"1d" when X"1c", X"65" when X"1d", X"92" when X"1e", X"bd" when X"1f",
X"86" when X"20", X"b8" when X"21", X"af" when X"22", X"8f" when X"23", X"7c" when X"24", X"eb" when X"25", X"1f" when X"26", X"ce" when X"27",
X"3e" when X"28", X"30" when X"29", X"dc" when X"2a", X"5f" when X"2b", X"5e" when X"2c", X"c5" when X"2d", X"0b" when X"2e", X"1a" when X"2f",
X"a6" when X"30", X"e1" when X"31", X"39" when X"32", X"ca" when X"33", X"d5" when X"34", X"47" when X"35", X"5d" when X"36", X"3d" when X"37",
X"d9" when X"38", X"01" when X"39", X"5a" when X"3a", X"d6" when X"3b", X"51" when X"3c", X"56" when X"3d", X"6c" when X"3e", X"4d" when X"3f",
X"8b" when X"40", X"0d" when X"41", X"9a" when X"42", X"66" when X"43", X"fb" when X"44", X"cc" when X"45", X"b0" when X"46", X"2d" when X"47",
X"74" when X"48", X"12" when X"49", X"2b" when X"4a", X"20" when X"4b", X"f0" when X"4c", X"b1" when X"4d", X"84" when X"4e", X"99" when X"4f",
X"df" when X"50", X"4c" when X"51", X"cb" when X"52", X"c2" when X"53", X"34" when X"54", X"7e" when X"55", X"76" when X"56", X"05" when X"57",
X"6d" when X"58", X"b7" when X"59", X"a9" when X"5a", X"31" when X"5b", X"d1" when X"5c", X"17" when X"5d", X"04" when X"5e", X"d7" when X"5f",
X"14" when X"60", X"58" when X"61", X"3a" when X"62", X"61" when X"63", X"de" when X"64", X"1b" when X"65", X"11" when X"66", X"1c" when X"67",
X"32" when X"68", X"0f" when X"69", X"9c" when X"6a", X"16" when X"6b", X"53" when X"6c", X"18" when X"6d", X"f2" when X"6e", X"22" when X"6f",
X"fe" when X"70", X"44" when X"71", X"cf" when X"72", X"b2" when X"73", X"c3" when X"74", X"b5" when X"75", X"7a" when X"76", X"91" when X"77",
X"24" when X"78", X"08" when X"79", X"e8" when X"7a", X"a8" when X"7b", X"60" when X"7c", X"fc" when X"7d", X"69" when X"7e", X"50" when X"7f",
X"aa" when X"80", X"d0" when X"81", X"a0" when X"82", X"7d" when X"83", X"a1" when X"84", X"89" when X"85", X"62" when X"86", X"97" when X"87",
X"54" when X"88", X"5b" when X"89", X"1e" when X"8a", X"95" when X"8b", X"e0" when X"8c", X"ff" when X"8d", X"64" when X"8e", X"d2" when X"8f",
X"10" when X"90", X"c4" when X"91", X"00" when X"92", X"48" when X"93", X"a3" when X"94", X"f7" when X"95", X"75" when X"96", X"db" when X"97",
X"8a" when X"98", X"03" when X"99", X"e6" when X"9a", X"da" when X"9b", X"09" when X"9c", X"3f" when X"9d", X"dd" when X"9e", X"94" when X"9f",
X"87" when X"a0", X"5c" when X"a1", X"83" when X"a2", X"02" when X"a3", X"cd" when X"a4", X"4a" when X"a5", X"90" when X"a6", X"33" when X"a7",
X"73" when X"a8", X"67" when X"a9", X"f6" when X"aa", X"f3" when X"ab", X"9d" when X"ac", X"7f" when X"ad", X"bf" when X"ae", X"e2" when X"af",
X"52" when X"b0", X"9b" when X"b1", X"d8" when X"b2", X"26" when X"b3", X"c8" when X"b4", X"37" when X"b5", X"c6" when X"b6", X"3b" when X"b7",
X"81" when X"b8", X"96" when X"b9", X"6f" when X"ba", X"4b" when X"bb", X"13" when X"bc", X"be" when X"bd", X"63" when X"be", X"2e" when X"bf",
X"e9" when X"c0", X"79" when X"c1", X"a7" when X"c2", X"8c" when X"c3", X"9f" when X"c4", X"6e" when X"c5", X"bc" when X"c6", X"8e" when X"c7",
X"29" when X"c8", X"f5" when X"c9", X"f9" when X"ca", X"b6" when X"cb", X"2f" when X"cc", X"fd" when X"cd", X"b4" when X"ce", X"59" when X"cf",
X"78" when X"d0", X"98" when X"d1", X"06" when X"d2", X"6a" when X"d3", X"e7" when X"d4", X"46" when X"d5", X"71" when X"d6", X"ba" when X"d7",
X"d4" when X"d8", X"25" when X"d9", X"ab" when X"da", X"42" when X"db", X"88" when X"dc", X"a2" when X"dd", X"8d" when X"de", X"fa" when X"df",
X"72" when X"e0", X"07" when X"e1", X"b9" when X"e2", X"55" when X"e3", X"f8" when X"e4", X"ee" when X"e5", X"ac" when X"e6", X"0a" when X"e7",
X"36" when X"e8", X"49" when X"e9", X"2a" when X"ea", X"68" when X"eb", X"3c" when X"ec", X"38" when X"ed", X"f1" when X"ee", X"a4" when X"ef",
X"40" when X"f0", X"28" when X"f1", X"d3" when X"f2", X"7b" when X"f3", X"bb" when X"f4", X"c9" when X"f5", X"43" when X"f6", X"c1" when X"f7",
X"15" when X"f8", X"e3" when X"f9", X"ad" when X"fa", X"f4" when X"fb", X"77" when X"fc", X"c7" when X"fd", X"80" when X"fe", X"9e" when X"ff";
 
-- end sbox
 
end phy;
/nfcc/trunk/camellia/camellia.c
0,0 → 1,162
#include <stdio.h>
#include <string.h>
#include "genpat.h"
 
char *inttostr(entier)
int entier;
{
char *str;
str = (char *) mbkalloc (32 * sizeof (char));
sprintf (str, "%d",entier);
return(str);
}
/*------------------------------*/
/* end of the description */
/*------------------------------*/
 
main (int argc, char *argv[])
{
int i,c;
int Nk,ks,ps;
char sNk[4];
FILE *f1, *f2;
char *fname1 = "key.lst";
char *fname2 = "pt.lst";
char key[0xff][0x4f];
char fpt[0xff][0x4f];
 
Nk = 4;
/* remember argc start from 1 not zero and command line is the first array */
if (argc > 1 ) {
if (argc == 4) {
fname1 = argv[3]; /* key */
fname2 = argv[2]; /* plain text*/
sscanf(argv[1], "%d", &Nk);
printf("Using Nk(0x%x) plain-text (%s) key (%s)\n", Nk, fname2, fname1);
} else {
printf("Usage %s: Nk plain-text key\n", argv[0]);
return 0;
}
}
 
sprintf(sNk, "0x%x", Nk);
 
if(fname1 && (f1 = fopen(fname1, "rt"))) {
i = 0;
while(fgets(key[i],sizeof(key[i]),f1) != NULL) {
c = strlen(key[i]);
if(key[i][c-1] == '\n') key[i][c-1] = '\0';
i++;
}
fclose (f1);
} else {
fclose (f1);
}
 
ks = i;
 
if(fname2 && (f2 = fopen(fname2, "rt"))) {
i = 0;
while(fgets(fpt[i],sizeof(fpt[i]),f2) != NULL) {
c = strlen(fpt[i]);
if(fpt[i][c-1] == '\n') fpt[i][c-1] = '\0';
i++;
}
fclose (f2);
} else {
fclose (f2);
}
 
ps = i;
//printf("ps: %d\n",ps);
 
DEF_GENPAT("camellia");
SETTUNIT("ns");
 
/* interface */
DECLAR ("clk", ":1", "B", IN , "" , "" );
DECLAR ("rst", ":1", "B", IN , "" , "" );
DECLAR ("ldpt",":1", "B", IN , "" , "" );
DECLAR ( "pt", ":2", "X", IN , "63 downto 0", "" );
//DECLAR ("cipher_inst_ildpt", ":1", "B", SIGNAL , "" , "" );
//DECLAR ("cipher_inst_ipt" , ":1", "X", SIGNAL , "31 downto 0", "" );
DECLAR ( "Nk", ":2", "X", IN , " 3 downto 0", "" );
//DECLAR ( "st", ":2", "X", OUT, " 7 downto 0", "" );
DECLAR ("key", ":2", "X", IN , "63 downto 0", "" );
DECLAR ( "ct", ":2", "X", OUT, "63 downto 0", "" );
//DECLAR ( "rc_prb", ":2", "X", OUT, " 2 downto 0", "" );
//DECLAR ( "l_prb", ":2", "X", OUT, "63 downto 0", "" );
//DECLAR ( "r_prb", ":2", "X", OUT, "63 downto 0", "" );
//DECLAR ( "fla_prb", ":2", "X", OUT, "63 downto 0", "" );
//DECLAR ( "z_prb", ":2", "X", OUT, "63 downto 0", "" );
//DECLAR ( "il_prb", ":2", "X", OUT, "63 downto 0", "" );
//DECLAR ( "ir_prb", ":2", "X", OUT, "63 downto 0", "" );
DECLAR ( "v", ":1", "B", OUT, "" , "" );
//DECLAR ("cipher_inst_rnd", ":1", "X", SIGNAL , " 3 downto 0" , "" );
//DECLAR ("cipher_inst_swp", ":1", "B", SIGNAL , "" , "" );
//DECLAR ("ct2b_1", ":1", "B", SIGNAL , "" , "" );
//DECLAR ("ct2b_0", ":1", "B", SIGNAL , "" , "" );
//DECLAR ("cipher_inst_ireg1", ":1", "X", SIGNAL , "127 downto 0" , "" );
//DECLAR ("cipher_inst_ireg2", ":1", "X", SIGNAL , "127 downto 0" , "" );
//DECLAR ("cipher_inst_swp1", ":1", "B", SIGNAL , "" , "" );
DECLAR ("vss", ":1", "B", IN , "" , "" );
DECLAR ("vdd", ":1", "B", IN , "" , "" );
 
AFFECT ("0", "vss", "0b0");
AFFECT ("0", "vdd", "0b1");
 
AFFECT ( "0", "pt", "0x0000000000000000");
AFFECT ( "0", "key", "0x0000000000000000");
AFFECT ( "0", "rst", "0b1");
AFFECT ( "0","ldpt", "0b0");
AFFECT ( "0", "Nk", sNk );
AFFECT ( "0", "clk", "0b0");
AFFECT ("+50", "clk", "0b1");
AFFECT ("+50", "clk", "0b0");
AFFECT ( "+0", "rst", "0b0");
AFFECT ( "+0","ldpt", "0b1");
 
//if(Nk==0x4)
//AFFECT ( "+0", "pt", "0x3243f6a8");
 
for (i=0; i < ps; i++)
{
AFFECT ( "+0", "pt", fpt[i]);
AFFECT ("+50", "clk", "0b1" );
AFFECT ("+50", "clk", "0b0" );
AFFECT ( "+0", "key", key[i]);
 
//if ((i==1) && (Nk==0x4))
//AFFECT ( "+0", "pt", "0x885a308d");
//if ((i==2) && (Nk==0x4))
//AFFECT ( "+0", "pt", "0x313198a2");
//if ((i==3) && (Nk==0x4))
//AFFECT ( "+0", "pt", "0xe0370734");
 
}
 
AFFECT ( "+0","ldpt", "0b0");
AFFECT ( "+0", "pt", "0x0000000000000000");
 
for (; i < ks; i++)
{
AFFECT ("+50", "clk", "0b1" );
AFFECT ("+50", "clk", "0b0" );
AFFECT ( "+0", "key", key[i]);
}
 
AFFECT ("+50", "clk", "0b1" );
AFFECT ("+50", "clk", "0b0" );
AFFECT ( "+0", "key", "0x0000000000000000");
 
for (; i < 0x2f; i++)
{
AFFECT ("+50", "clk", "0b1" );
AFFECT ("+50", "clk", "0b0" );
}
 
AFFECT ("+50", "clk", "0b1");
 
SAV_GENPAT ();
}
 
/nfcc/trunk/camellia/keyscheduler.c
0,0 → 1,101
#include <stdio.h>
#include <string.h>
#include "genpat.h"
 
char *inttostr(entier)
int entier;
{
char *str;
str = (char *) mbkalloc (32 * sizeof (char));
sprintf (str, "%d",entier);
return(str);
}
 
main (int argc, char *argv[])
{
int i,c;
int Nk,ks,ps;
char sNk[4];
FILE *f1, *f2;
//char *fname1 = "key.lst";
char *fname2 = "ckey.lst";
//char key[0xff][0x4f];
char fpt[0xff][0x4f];
 
Nk = 4;
/* remember argc start from 1 not zero and command line is the first array */
if (argc > 1 ) {
if (argc == 3) {
fname2 = argv[2];
sscanf(argv[1], "%d", &Nk);
printf("Using Nk(0x%x) key (%s)\n", Nk, fname2);
} else {
printf("Usage %s: Nk key\n", argv[0]);
return 0;
}
}
 
sprintf(sNk, "0x%x", Nk);
 
if(fname2 && (f2 = fopen(fname2, "rt"))) {
i = 0;
while(fgets(fpt[i],sizeof(fpt[i]),f2) != NULL) {
c = strlen(fpt[i]);
if(fpt[i][c-1] == '\n') fpt[i][c-1] = '\0';
i++;
}
fclose (f2);
} else {
fclose (f2);
}
 
ps = i;
 
DEF_GENPAT("keyscheduler");
SETTUNIT("ns");
 
DECLAR ("clk", ":1", "B", IN , "" , "" );
DECLAR ("rst", ":1", "B", IN , "" , "" );
DECLAR ("ldk", ":1", "B", IN , "" , "" );
DECLAR ("key", ":2", "X", IN , "63 downto 0", "" );
DECLAR ( "Nk", ":2", "X", IN , " 3 downto 0", "" );
DECLAR ( "w", ":2", "X", OUT, "63 downto 0", "" );
DECLAR ( "v", ":1", "B", OUT, "" , "" );
DECLAR ("vss", ":1", "B", IN , "" , "" );
DECLAR ("vdd", ":1", "B", IN , "" , "" );
 
AFFECT ("0", "vss", "0b0");
AFFECT ("0", "vdd", "0b1");
 
AFFECT ( "0", "key", "0x0000000000000000");
AFFECT ( "0", "rst", "0b1");
AFFECT ( "0","ldk", "0b0");
AFFECT ( "0", "Nk", sNk );
AFFECT ( "0", "clk", "0b0");
AFFECT ("+50", "clk", "0b1");
AFFECT ("+50", "clk", "0b0");
AFFECT ( "+0", "rst", "0b0");
AFFECT ( "+0","ldk", "0b1");
 
for (i=0; i < ps; i++)
{
AFFECT ( "+0", "key", fpt[i]);
AFFECT ("+50", "clk", "0b1" );
AFFECT ("+50", "clk", "0b0" );
 
}
 
AFFECT ( "+0","ldk", "0b0");
AFFECT ( "+0", "key", "0x0000000000000000");
 
for (; i < 0x2f; i++)
{
AFFECT ("+50", "clk", "0b1" );
AFFECT ("+50", "clk", "0b0" );
}
 
AFFECT ("+50", "clk", "0b1");
 
SAV_GENPAT ();
}
 
/nfcc/trunk/camellia/key.lst
0,0 → 1,26
0x0123456789abcdef
0xfedcba9876543210
0xae71c3d55ba6bf1d
0x169240a795f89256
0xa2b3c4d5e6f7ff6e
0x5d4c3b2a19080091
0xe1eaadd35f8e8b49
0x2053cafc492b5738
0x56e9afc745a49029
0xe57e2495ab9c70f5
0x79bdffdb97530eca
0x8642002468acf135
0xd7e3a2d24814f2bf
0x00123456789abcde
0xd169240a795f8925
0x6ae71c3d55ba6bf1
0x97530eca86420024
0x68acf13579bdffdb
0x1d950c840048d159
0xe26af37bffb72ea6
0xe57e2495ab9c70f5
0x56e9afc745a49029
0x19080091a2b3c4d5
0xe6f7ff6e5d4c3b2a
0x492b5738e1eaadd3
0x5f8e8b492053cafc
/nfcc/trunk/camellia/sbox.c
0,0 → 1,43
#include <stdio.h>
#include "genpat.h"
 
char *inttostr(entier)
int entier;
{
char *str;
str = (char *) mbkalloc (32 * sizeof (char));
sprintf (str, "%d",entier);
return(str);
}
/*------------------------------*/
/* end of the description */
/*------------------------------*/
 
main ()
{
int i;
int cur_vect = 0;
 
DEF_GENPAT("sbox");
SETTUNIT("ns");
 
/* interface */
DECLAR ("di" , ":2", "X", IN , "7 downto 0", "" );
DECLAR ("do" , ":2", "X", OUT, "7 downto 0", "" );
DECLAR ("vss", ":1", "B", IN , "" , "" );
DECLAR ("vdd", ":1", "B", IN , "" , "" );
 
AFFECT ("0", "vss", "0b0");
AFFECT ("0", "vdd", "0b1");
AFFECT ("0", "di", "0x00");
 
for (i=1; i<256; i++)
{
AFFECT ("+10", "di", inttostr(i) );
cur_vect++;
}
 
 
SAV_GENPAT ();
}
 
/nfcc/trunk/camellia/Makefile
0,0 → 1,119
#- ------------------------------------------------------------------------
#- Copyright (C) 2010 Arif Endro Nugroho
#- All rights reserved.
#-
#- Redistribution and use in source and binary forms, with or without
#- modification, are permitted provided that the following conditions
#- are met:
#-
#- 1. Redistributions of source code must retain the above copyright
#- notice, this list of conditions and the following disclaimer.
#- 2. Redistributions in binary form must reproduce the above copyright
#- notice, this list of conditions and the following disclaimer in the
#- documentation and/or other materials provided with the distribution.
#-
#- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
#- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
#- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
#- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
#- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
#- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
#- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
#- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
#- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
#- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
#- POSSIBILITY OF SUCH DAMAGE.
#-
#- End Of License.
#- ------------------------------------------------------------------------
#
# Need to FLATTENING the design before OCP and NERO
# Use x2y vst vst <source> <result>
# then flatlo -r <source> <result> # source is a result from x2y
# this two sequence will remove most warning/error message when
# performing LOON on the netlist.
#
# BOOM will optimize the logic
# BOOG will optimize/convert the logic into netlist
# LOON will optimize the netlist (this will report area/timing)
#
# VST is a circuit netlist file
# AP is a circuit placement file (OCP/NERO create this file)
# VBE is alliance VHDL Behavioral Description file
 
VASYFLAGS = -V -B -I vhdl -a -p -o
BOOMFLAGS = -VP
BOOGFLAGS =
LOONFLAGS =
OCPFLAGS = -v
NEROFLAGS = -V -G -6 -p
DRUCFLAGS =
S2RFLAGS = -v
OCP = ocp
NERO = nero
DRUC = druc
S2R = s2r
VASY = vasy
BOOM = boom
GENPAT = genpat -v
BOOG = boog
LOON = loon
RM = /bin/rm -vf
X2Y = x2y
FLATLO = flatlo
X2YFLAGS = vst vst
FLATLOFLAGS = -r
TOUCH = touch
 
# Set-up TARGET variable respectively
%.ap: TARGET = $(subst .ap,, $@)
%.pat: TARGET = $(subst .pat,, $@)
%.cif: TARGET = $(subst .cif,, $@)
%.vst: TARGET = $(subst .vst,, $@)
%.flt: TARGET = $(subst .flt,, $@)
%.sflt: TARGET = $(subst .sflt,, $@)
%.flatten: TARGET = $(subst .flatten,, $@)
 
all:
 
%.vbe: %.vhdl
@$(VASY) $(VASYFLAGS) $<
 
%.vst: %.vbe
@$(BOOM) $(BOOMFLAGS) $(TARGET) $(TARGET)_o
@$(BOOG) $(BOOGFLAGS) $(TARGET)_o
@$(LOON) $(LOONFLAGS) $(TARGET)_o $(TARGET)
-$(RM) $(TARGET)_o.*
 
%.sflt: %.vbe
# @$(BOOM) $(BOOMFLAGS) $(TARGET)_model $(TARGET)_model_o
@$(BOOG) $(BOOGFLAGS) $(TARGET)_model
# @$(BOOG) $(BOOGFLAGS) $(TARGET)_model_o
# @$(LOON) $(LOONFLAGS) $(TARGET)_model_o $(TARGET)_model
-$(RM) $(TARGET)_model_o.*
@$(X2Y) $(X2YFLAGS) $(TARGET) $(TARGET)_m
@$(FLATLO) $(FLATLOFLAGS) $(TARGET)_m $(TARGET)
# @$(FLATLO) $(FLATLOFLAGS) $(TARGET)_m $(TARGET)_o
# @$(LOON) $(LOONFLAGS) $(TARGET)_o $(TARGET)
-$(RM) $(TARGET){_o,m}.*
@$(TOUCH) $@
 
%.flt: %.vbe
@$(BOOM) $(BOOMFLAGS) $(TARGET)_model $(TARGET)_model_o
@$(BOOG) $(BOOGFLAGS) $(TARGET)_model_o
@$(LOON) $(LOONFLAGS) $(TARGET)_model_o $(TARGET)_model
-$(RM) $(TARGET)_model_o.*
@$(X2Y) $(X2YFLAGS) $(TARGET) $(TARGET)_m
@$(FLATLO) $(FLATLOFLAGS) $(TARGET)_m $(TARGET)_o
@$(LOON) $(LOONFLAGS) $(TARGET)_o $(TARGET)
-$(RM) $(TARGET){_o,m}.*
@$(TOUCH) $@
 
%.flatten: %.vst
@$(X2Y) $(X2YFLAGS) $(TARGET) $(TARGET)_m
@$(FLATLO) $(FLATLOFLAGS) $(TARGET)_m $(TARGET)_o
@$(LOON) $(LOONFLAGS) $(TARGET)_o $(TARGET)
-$(RM) $(TARGET){_o,m}.*
 
clean:
@rm -vf *.dat *.gpl *.vhd *.vbe *.boom *.vst *.xsc *.ap *.cif *.drc done.* *.flt *.sflt *_syn.pat *_sim.pat
/nfcc/trunk/rijndael/invcipher/invsbox.vhdl
0,0 → 1,128
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity invsbox is
port (
di : in bit_vector (07 downto 00);
do : out bit_vector (07 downto 00)
);
end invsbox;
 
architecture phy of invsbox is
begin
with di(07 downto 00) select
do <=
-- start invsbox
X"52" when X"00", X"09" when X"01", X"6a" when X"02", X"d5" when X"03",
X"30" when X"04", X"36" when X"05", X"a5" when X"06", X"38" when X"07",
X"bf" when X"08", X"40" when X"09", X"a3" when X"0a", X"9e" when X"0b",
X"81" when X"0c", X"f3" when X"0d", X"d7" when X"0e", X"fb" when X"0f",
 
X"7c" when X"10", X"e3" when X"11", X"39" when X"12", X"82" when X"13",
X"9b" when X"14", X"2f" when X"15", X"ff" when X"16", X"87" when X"17",
X"34" when X"18", X"8e" when X"19", X"43" when X"1a", X"44" when X"1b",
X"c4" when X"1c", X"de" when X"1d", X"e9" when X"1e", X"cb" when X"1f",
 
X"54" when X"20", X"7b" when X"21", X"94" when X"22", X"32" when X"23",
X"a6" when X"24", X"c2" when X"25", X"23" when X"26", X"3d" when X"27",
X"ee" when X"28", X"4c" when X"29", X"95" when X"2a", X"0b" when X"2b",
X"42" when X"2c", X"fa" when X"2d", X"c3" when X"2e", X"4e" when X"2f",
 
X"08" when X"30", X"2e" when X"31", X"a1" when X"32", X"66" when X"33",
X"28" when X"34", X"d9" when X"35", X"24" when X"36", X"b2" when X"37",
X"76" when X"38", X"5b" when X"39", X"a2" when X"3a", X"49" when X"3b",
X"6d" when X"3c", X"8b" when X"3d", X"d1" when X"3e", X"25" when X"3f",
 
X"72" when X"40", X"f8" when X"41", X"f6" when X"42", X"64" when X"43",
X"86" when X"44", X"68" when X"45", X"98" when X"46", X"16" when X"47",
X"d4" when X"48", X"a4" when X"49", X"5c" when X"4a", X"cc" when X"4b",
X"5d" when X"4c", X"65" when X"4d", X"b6" when X"4e", X"92" when X"4f",
 
X"6c" when X"50", X"70" when X"51", X"48" when X"52", X"50" when X"53",
X"fd" when X"54", X"ed" when X"55", X"b9" when X"56", X"da" when X"57",
X"5e" when X"58", X"15" when X"59", X"46" when X"5a", X"57" when X"5b",
X"a7" when X"5c", X"8d" when X"5d", X"9d" when X"5e", X"84" when X"5f",
 
X"90" when X"60", X"d8" when X"61", X"ab" when X"62", X"00" when X"63",
X"8c" when X"64", X"bc" when X"65", X"d3" when X"66", X"0a" when X"67",
X"f7" when X"68", X"e4" when X"69", X"58" when X"6a", X"05" when X"6b",
X"b8" when X"6c", X"b3" when X"6d", X"45" when X"6e", X"06" when X"6f",
 
X"d0" when X"70", X"2c" when X"71", X"1e" when X"72", X"8f" when X"73",
X"ca" when X"74", X"3f" when X"75", X"0f" when X"76", X"02" when X"77",
X"c1" when X"78", X"af" when X"79", X"bd" when X"7a", X"03" when X"7b",
X"01" when X"7c", X"13" when X"7d", X"8a" when X"7e", X"6b" when X"7f",
 
X"3a" when X"80", X"91" when X"81", X"11" when X"82", X"41" when X"83",
X"4f" when X"84", X"67" when X"85", X"dc" when X"86", X"ea" when X"87",
X"97" when X"88", X"f2" when X"89", X"cf" when X"8a", X"ce" when X"8b",
X"f0" when X"8c", X"b4" when X"8d", X"e6" when X"8e", X"73" when X"8f",
 
X"96" when X"90", X"ac" when X"91", X"74" when X"92", X"22" when X"93",
X"e7" when X"94", X"ad" when X"95", X"35" when X"96", X"85" when X"97",
X"e2" when X"98", X"f9" when X"99", X"37" when X"9a", X"e8" when X"9b",
X"1c" when X"9c", X"75" when X"9d", X"df" when X"9e", X"6e" when X"9f",
 
X"47" when X"a0", X"f1" when X"a1", X"1a" when X"a2", X"71" when X"a3",
X"1d" when X"a4", X"29" when X"a5", X"c5" when X"a6", X"89" when X"a7",
X"6f" when X"a8", X"b7" when X"a9", X"62" when X"aa", X"0e" when X"ab",
X"aa" when X"ac", X"18" when X"ad", X"be" when X"ae", X"1b" when X"af",
 
X"fc" when X"b0", X"56" when X"b1", X"3e" when X"b2", X"4b" when X"b3",
X"c6" when X"b4", X"d2" when X"b5", X"79" when X"b6", X"20" when X"b7",
X"9a" when X"b8", X"db" when X"b9", X"c0" when X"ba", X"fe" when X"bb",
X"78" when X"bc", X"cd" when X"bd", X"5a" when X"be", X"f4" when X"bf",
 
X"1f" when X"c0", X"dd" when X"c1", X"a8" when X"c2", X"33" when X"c3",
X"88" when X"c4", X"07" when X"c5", X"c7" when X"c6", X"31" when X"c7",
X"b1" when X"c8", X"12" when X"c9", X"10" when X"ca", X"59" when X"cb",
X"27" when X"cc", X"80" when X"cd", X"ec" when X"ce", X"5f" when X"cf",
 
X"60" when X"d0", X"51" when X"d1", X"7f" when X"d2", X"a9" when X"d3",
X"19" when X"d4", X"b5" when X"d5", X"4a" when X"d6", X"0d" when X"d7",
X"2d" when X"d8", X"e5" when X"d9", X"7a" when X"da", X"9f" when X"db",
X"93" when X"dc", X"c9" when X"dd", X"9c" when X"de", X"ef" when X"df",
 
X"a0" when X"e0", X"e0" when X"e1", X"3b" when X"e2", X"4d" when X"e3",
X"ae" when X"e4", X"2a" when X"e5", X"f5" when X"e6", X"b0" when X"e7",
X"c8" when X"e8", X"eb" when X"e9", X"bb" when X"ea", X"3c" when X"eb",
X"83" when X"ec", X"53" when X"ed", X"99" when X"ee", X"61" when X"ef",
 
X"17" when X"f0", X"2b" when X"f1", X"04" when X"f2", X"7e" when X"f3",
X"ba" when X"f4", X"77" when X"f5", X"d6" when X"f6", X"26" when X"f7",
X"e1" when X"f8", X"69" when X"f9", X"14" when X"fa", X"63" when X"fb",
X"55" when X"fc", X"21" when X"fd", X"0c" when X"fe", X"7d" when X"ff",
 
-- end invsbox
X"00" when others;
end phy;
/nfcc/trunk/rijndael/invcipher/key.lst
0,0 → 1,44
0x2b7e1516
0x28aed2a6
0xabf71588
0x09cf4f3c
0xa0fafe17
0x88542cb1
0x23a33939
0x2a6c7605
0xf2c295f2
0x7a96b943
0x5935807a
0x7359f67f
0x3d80477d
0x4716fe3e
0x1e237e44
0x6d7a883b
0xef44a541
0xa8525b7f
0xb671253b
0xdb0bad00
0xd4d1c6f8
0x7c839d87
0xcaf2b8bc
0x11f915bc
0x6d88a37a
0x110b3efd
0xdbf98641
0xca0093fd
0x4e54f70e
0x5f5fc9f3
0x84a64fb2
0x4ea6dc4f
0xead27321
0xb58dbad2
0x312bf560
0x7f8d292f
0xac7766f3
0x19fadc21
0x28d12941
0x575c006e
0xd014f9a8
0xc9ee2589
0xe13f0cc8
0xb6630ca6
/nfcc/trunk/rijndael/invcipher/c2b.pat
0,0 → 1,38
 
in clk B;;
in rst B;;
out cnt(1 downto 0) X;;
out cnt(1 downto 0) B;;
in vss B;;
in vdd B;;
 
begin
 
< 0ns>: 0 1 ?* ?** 0 1;
< +10ns>: 1 1 ?* ?** 0 1;
< +10ns>: 0 0 ?* ?** 0 1;
< +10ns>: 1 0 ?* ?** 0 1;
< +10ns>: 0 0 ?* ?** 0 1;
< +10ns>: 1 0 ?* ?** 0 1;
< +10ns>: 0 0 ?* ?** 0 1;
< +10ns>: 1 0 ?* ?** 0 1;
< +10ns>: 0 0 ?* ?** 0 1;
< +10ns>: 1 0 ?* ?** 0 1;
< +10ns>: 0 0 ?* ?** 0 1;
< +10ns>: 1 0 ?* ?** 0 1;
< +10ns>: 0 0 ?* ?** 0 1;
< +10ns>: 1 0 ?* ?** 0 1;
< +10ns>: 0 0 ?* ?** 0 1;
< +10ns>: 1 0 ?* ?** 0 1;
< +10ns>: 0 0 ?* ?** 0 1;
< +10ns>: 1 0 ?* ?** 0 1;
< +10ns>: 0 0 ?* ?** 0 1;
< +10ns>: 1 0 ?* ?** 0 1;
< +10ns>: 0 0 ?* ?** 0 1;
< +10ns>: 1 0 ?* ?** 0 1;
< +10ns>: 0 0 ?* ?** 0 1;
< +10ns>: 1 0 ?* ?** 0 1;
< +10ns>: 0 0 ?* ?** 0 1;
< +10ns>: 1 0 ?* ?** 0 1;
 
end;
/nfcc/trunk/rijndael/invcipher/c4b.pat
0,0 → 1,80
 
in clk B;;
in rst B;;
out cnt(3 downto 0) X;;
out cnt(3 downto 0) B;;
in vss B;;
in vdd B;;
 
begin
 
< 0ns>: 0 1 ?* ?**** 0 1;
< +10ns>: 1 1 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
 
end;
/nfcc/trunk/rijndael/invcipher/c6b.pat
0,0 → 1,168
 
in clk B;;
in rst B;;
out cnt(5 downto 0) X;;
out cnt(5 downto 0) B;;
in vss B;;
in vdd B;;
 
begin
 
< 0ns>: 0 1 ?** ?****** 0 1;
< +10ns>: 1 1 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
< +10ns>: 0 0 ?** ?****** 0 1;
< +10ns>: 1 0 ?** ?****** 0 1;
 
end;
/nfcc/trunk/rijndael/invcipher/xtime_2.vhdl
0,0 → 1,44
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity xtime_2 is
port (
x2i : in bit_vector (07 downto 00);
x2o : out bit_vector (07 downto 00)
);
end xtime_2;
 
architecture phy of xtime_2 is
begin
x2o <= ( x2i(06 downto 04) & ( x2i(03 downto 02) xor ( x2i(07) & x2i(07) ) ) & x2i(01) & ( x2i(00) xor x2i(07) ) & x2i(07) );
end phy;
/nfcc/trunk/rijndael/invcipher/xtime_4.vhdl
0,0 → 1,44
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity xtime_4 is
port (
x4i : in bit_vector (07 downto 00);
x4o : out bit_vector (07 downto 00)
);
end xtime_4;
 
architecture phy of xtime_4 is
begin
x4o <= ( x4i(05) & x4i(04) & ( x4i(03) xor x4i(07) ) & ( x4i(02) xor x4i(07) xor x4i(06) ) & ( x4i(01) xor x4i(06) ) & ( x4i(00) xor x4i(07) ) & ( x4i(07) xor x4i(06) ) & x4i(06) );
end phy;
/nfcc/trunk/rijndael/invcipher/invct1.lst
0,0 → 1,4
0x70b4c55a
0xd8cdb780
0x6a7b0430
0x69c4e0d8
/nfcc/trunk/rijndael/invcipher/invct2.lst
0,0 → 1,4
0xec0d7191
0x6eaf70a0
0x864cdfe0
0xdda97ca4
/nfcc/trunk/rijndael/invcipher/invct3.lst
0,0 → 1,4
0x4b496089
0xeafc4990
0x516745bf
0x8ea2b7ca
/nfcc/trunk/rijndael/invcipher/ct.lst
0,0 → 1,4
0x3925841d
0x02dc09fb
0xdc118597
0x196a0b32
/nfcc/trunk/rijndael/invcipher/invcipher.c
0,0 → 1,148
#include <stdio.h>
#include <string.h>
#include "genpat.h"
 
char *inttostr(entier)
int entier;
{
char *str;
str = (char *) mbkalloc (32 * sizeof (char));
sprintf (str, "%d",entier);
return(str);
}
/*------------------------------*/
/* end of the description */
/*------------------------------*/
 
main (int argc, char *argv[])
{
int i,c;
int Nk,ks,ps;
char sNk[4];
FILE *f1, *f2;
char *fname1 = "invkey.lst";
char *fname2 = "ct.lst";
char key[80][20];
char fpt[10][20];
 
Nk = 4;
/* remember argc start from 1 not zero and command line is the first array */
if (argc > 1 ) {
if (argc == 4) {
fname1 = argv[3]; /* key */
fname2 = argv[2]; /* plain text*/
sscanf(argv[1], "%d", &Nk);
printf("Using Nk(0x%x) cipher-text (%s) key (%s)\n", Nk, fname2, fname1);
} else {
printf("Usage %s: Nk cipher-text key\n", argv[0]);
return 0;
}
}
 
sprintf(sNk, "0x%x", Nk);
 
if(fname1 && (f1 = fopen(fname1, "rt"))) {
i = 0;
while(fgets(key[i],sizeof(key[i]),f1) != NULL) {
c = strlen(key[i]);
if(key[i][c-1] == '\n') key[i][c-1] = '\0';
i++;
}
fclose (f1);
} else {
fclose (f1);
}
 
ks = i;
 
if(fname2 && (f2 = fopen(fname2, "rt"))) {
i = 0;
while(fgets(fpt[i],sizeof(fpt[i]),f2) != NULL) {
c = strlen(fpt[i]);
if(fpt[i][c-1] == '\n') fpt[i][c-1] = '\0';
i++;
}
fclose (f2);
} else {
fclose (f2);
}
 
ps = i;
 
DEF_GENPAT("invcipher");
SETTUNIT("ns");
 
/* interface */
DECLAR ("clk", ":1", "B", IN , "" , "" );
DECLAR ("rst", ":1", "B", IN , "" , "" );
DECLAR ("ldct",":1", "B", IN , "" , "" );
DECLAR ( "ct", ":2", "X", IN , "31 downto 0", "" );
//DECLAR ("cipher_inst_ildpt", ":1", "B", SIGNAL , "" , "" );
//DECLAR ("cipher_inst_ipt" , ":1", "X", SIGNAL , "31 downto 0", "" );
DECLAR ( "Nk", ":2", "X", IN , " 3 downto 0", "" );
//DECLAR ( "st", ":2", "X", OUT, " 7 downto 0", "" );
DECLAR ("key", ":2", "X", IN , "31 downto 0", "" );
DECLAR ( "pt", ":2", "X", OUT, "31 downto 0", "" );
//DECLAR ("cipher_inst_swp", ":1", "B", SIGNAL , "" , "" );
DECLAR ( "v", ":1", "B", OUT, "" , "" );
DECLAR ("invcipher_inst_rnd", ":1", "X", SIGNAL , " 3 downto 0" , "" );
//DECLAR ( "sr_prb", ":2", "X", OUT, "31 downto 0", "" );
//DECLAR ( "sb_prb", ":2", "X", OUT, "31 downto 0", "" );
//DECLAR ( "mc_prb", ":2", "X", OUT, "31 downto 0", "" );
//DECLAR ("ct2b_1", ":1", "B", SIGNAL , "" , "" );
//DECLAR ("ct2b_0", ":1", "B", SIGNAL , "" , "" );
//DECLAR ("invcipher_inst_wsb", ":1", "X", SIGNAL , "31 downto 0" , "" );
//DECLAR ("invcipher_inst_ireg1", ":1", "X", SIGNAL , "127 downto 0" , "" );
//DECLAR ("invcipher_inst_ireg2", ":1", "X", SIGNAL , "127 downto 0" , "" );
//DECLAR ("cipher_inst_swp1", ":1", "B", SIGNAL , "" , "" );
DECLAR ("vss", ":1", "B", IN , "" , "" );
DECLAR ("vdd", ":1", "B", IN , "" , "" );
 
AFFECT ("0", "vss", "0b0");
AFFECT ("0", "vdd", "0b1");
 
AFFECT ( "0", "ct", "0x00000000");
AFFECT ( "0", "key", "0x00000000");
AFFECT ( "0", "rst", "0b1");
AFFECT ( "0","ldct", "0b0");
AFFECT ( "0", "Nk", sNk );
AFFECT ( "0", "clk", "0b0");
AFFECT ("+50", "clk", "0b1");
AFFECT ("+50", "clk", "0b0");
AFFECT ( "+0", "rst", "0b0");
AFFECT ( "+0","ldct", "0b1");
 
for (i=0; i < ps; i++)
{
AFFECT ( "+0", "ct", fpt[i]);
AFFECT ("+50", "clk", "0b1" );
AFFECT ("+50", "clk", "0b0" );
AFFECT ( "+0", "key", key[i]);
 
}
 
AFFECT ( "+0","ldct", "0b0");
AFFECT ( "+0", "ct", "0x00000000");
 
for (; i < ks; i++)
{
AFFECT ("+50", "clk", "0b1" );
AFFECT ("+50", "clk", "0b0" );
AFFECT ( "+0", "key", key[i]);
}
 
AFFECT ("+50", "clk", "0b1" );
AFFECT ("+50", "clk", "0b0" );
AFFECT ( "+0", "key", "0x00000000");
 
for (; i < 64; i++)
{
AFFECT ("+50", "clk", "0b1" );
AFFECT ("+50", "clk", "0b0" );
}
 
AFFECT ("+50", "clk", "0b1");
 
SAV_GENPAT ();
}
 
/nfcc/trunk/rijndael/invcipher/invsbox.c
0,0 → 1,44
#include <stdio.h>
#include "genpat.h"
 
char *inttostr(entier)
int entier;
{
char *str;
str = (char *) mbkalloc (32 * sizeof (char));
sprintf (str, "%d",entier);
return(str);
}
/*------------------------------*/
/* end of the description */
/*------------------------------*/
 
main ()
{
int i;
int cur_vect = 0;
 
DEF_GENPAT("invsbox");
SETTUNIT("ns");
 
/* interface */
DECLAR ("di" , ":2", "X", IN , "7 downto 0", "" );
DECLAR ("do" , ":2", "X", OUT, "7 downto 0", "" );
DECLAR ("vss", ":1", "B", IN , "" , "" );
DECLAR ("vdd", ":1", "B", IN , "" , "" );
 
AFFECT ("0", "vss", "0b0");
AFFECT ("0", "vdd", "0b1");
AFFECT ("0", "di", "0x00");
 
for (i=1; i<256; i++)
{
/* AFFECT (inttostr(cur_vect), "di", inttostr(i) ); */
AFFECT ("+10", "di", inttostr(i) );
cur_vect++;
}
 
 
SAV_GENPAT ();
}
 
/nfcc/trunk/rijndael/invcipher/xtime_8.vhdl
0,0 → 1,44
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity xtime_8 is
port (
x8i : in bit_vector (07 downto 00);
x8o : out bit_vector (07 downto 00)
);
end xtime_8;
 
architecture phy of xtime_8 is
begin
x8o <= ( x8i(04) & ( x8i(03) xor x8i(07) ) & ( x8i(02) xor x8i(07) xor x8i(06) ) & ( x8i(01) xor x8i(06) xor x8i(05) ) & ( x8i(00) xor x8i(07) xor x8i(05) ) & ( x8i(07) xor x8i(06) ) & ( x8i(06) xor x8i(05) ) & x8i(05) );
end phy;
/nfcc/trunk/rijndael/invcipher/key1.lst
0,0 → 1,44
0x00010203
0x04050607
0x08090a0b
0x0c0d0e0f
0xd6aa74fd
0xd2af72fa
0xdaa678f1
0xd6ab76fe
0xb692cf0b
0x643dbdf1
0xbe9bc500
0x6830b3fe
0xb6ff744e
0xd2c2c9bf
0x6c590cbf
0x0469bf41
0x47f7f7bc
0x95353e03
0xf96c32bc
0xfd058dfd
0x3caaa3e8
0xa99f9deb
0x50f3af57
0xadf622aa
0x5e390f7d
0xf7a69296
0xa7553dc1
0x0aa31f6b
0x14f9701a
0xe35fe28c
0x440adf4d
0x4ea9c026
0x47438735
0xa41c65b9
0xe016baf4
0xaebf7ad2
0x549932d1
0xf0855768
0x1093ed9c
0xbe2c974e
0x13111d7f
0xe3944a17
0xf307a78b
0x4d2b30c5
/nfcc/trunk/rijndael/invcipher/invcipher.pat
0,0 → 1,183
 
-- description generated by Pat driver
 
-- date : Thu Oct 1 18:51:30 2009
-- revision : v109
 
-- sequence : invcipher
 
-- input / output list :
in clk B;;
in rst B;;
in ldct B;;
in ct (31 downto 0) X;;;
in nk (3 downto 0) X;;;
in key (31 downto 0) X;;;
out pt (31 downto 0) X;;;
out v B;;
signal invcipher_inst_rnd (3 downto 0) X;;
in vss B;;
in vdd B;;
 
begin
 
-- Pattern description :
 
-- c r l c n k p v i v v
-- l s d t k e t n s d
-- k t c y v s d
-- t c
-- i
-- p
-- h
-- e
-- r
-- _
-- i
-- n
-- s
-- t
-- _
-- r
-- n
-- d
 
 
-- Beware : unprocessed patterns
 
< 0 ns> : 0 1 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 50 ns> : 1 1 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 100 ns> : 0 0 1 3925841d 4 00000000 ?******** ?* ?* 0 1 ;
< 150 ns> : 1 0 1 3925841d 4 00000000 ?******** ?* ?* 0 1 ;
< 200 ns> : 0 0 1 02dc09fb 4 d014f9a8 ?******** ?* ?* 0 1 ;
< 250 ns> : 1 0 1 02dc09fb 4 d014f9a8 ?******** ?* ?* 0 1 ;
< 300 ns> : 0 0 1 dc118597 4 c9ee2589 ?******** ?* ?* 0 1 ;
< 350 ns> : 1 0 1 dc118597 4 c9ee2589 ?******** ?* ?* 0 1 ;
< 400 ns> : 0 0 1 196a0b32 4 e13f0cc8 ?******** ?* ?* 0 1 ;
< 450 ns> : 1 0 1 196a0b32 4 e13f0cc8 ?******** ?* ?* 0 1 ;
< 500 ns> : 0 0 0 00000000 4 b6630ca6 ?******** ?* ?* 0 1 ;
< 550 ns> : 1 0 0 00000000 4 b6630ca6 ?******** ?* ?* 0 1 ;
< 600 ns> : 0 0 0 00000000 4 ac7766f3 ?******** ?* ?* 0 1 ;
< 650 ns> : 1 0 0 00000000 4 ac7766f3 ?******** ?* ?* 0 1 ;
< 700 ns> : 0 0 0 00000000 4 19fadc21 ?******** ?* ?* 0 1 ;
< 750 ns> : 1 0 0 00000000 4 19fadc21 ?******** ?* ?* 0 1 ;
< 800 ns> : 0 0 0 00000000 4 28d12941 ?******** ?* ?* 0 1 ;
< 850 ns> : 1 0 0 00000000 4 28d12941 ?******** ?* ?* 0 1 ;
< 900 ns> : 0 0 0 00000000 4 575c006e ?******** ?* ?* 0 1 ;
< 950 ns> : 1 0 0 00000000 4 575c006e ?******** ?* ?* 0 1 ;
< 1000 ns> : 0 0 0 00000000 4 ead27321 ?******** ?* ?* 0 1 ;
< 1050 ns> : 1 0 0 00000000 4 ead27321 ?******** ?* ?* 0 1 ;
< 1100 ns> : 0 0 0 00000000 4 b58dbad2 ?******** ?* ?* 0 1 ;
< 1150 ns> : 1 0 0 00000000 4 b58dbad2 ?******** ?* ?* 0 1 ;
< 1200 ns> : 0 0 0 00000000 4 312bf560 ?******** ?* ?* 0 1 ;
< 1250 ns> : 1 0 0 00000000 4 312bf560 ?******** ?* ?* 0 1 ;
< 1300 ns> : 0 0 0 00000000 4 7f8d292f ?******** ?* ?* 0 1 ;
< 1350 ns> : 1 0 0 00000000 4 7f8d292f ?******** ?* ?* 0 1 ;
< 1400 ns> : 0 0 0 00000000 4 4e54f70e ?******** ?* ?* 0 1 ;
< 1450 ns> : 1 0 0 00000000 4 4e54f70e ?******** ?* ?* 0 1 ;
< 1500 ns> : 0 0 0 00000000 4 5f5fc9f3 ?******** ?* ?* 0 1 ;
< 1550 ns> : 1 0 0 00000000 4 5f5fc9f3 ?******** ?* ?* 0 1 ;
< 1600 ns> : 0 0 0 00000000 4 84a64fb2 ?******** ?* ?* 0 1 ;
< 1650 ns> : 1 0 0 00000000 4 84a64fb2 ?******** ?* ?* 0 1 ;
< 1700 ns> : 0 0 0 00000000 4 4ea6dc4f ?******** ?* ?* 0 1 ;
< 1750 ns> : 1 0 0 00000000 4 4ea6dc4f ?******** ?* ?* 0 1 ;
< 1800 ns> : 0 0 0 00000000 4 6d88a37a ?******** ?* ?* 0 1 ;
< 1850 ns> : 1 0 0 00000000 4 6d88a37a ?******** ?* ?* 0 1 ;
< 1900 ns> : 0 0 0 00000000 4 110b3efd ?******** ?* ?* 0 1 ;
< 1950 ns> : 1 0 0 00000000 4 110b3efd ?******** ?* ?* 0 1 ;
< 2000 ns> : 0 0 0 00000000 4 dbf98641 ?******** ?* ?* 0 1 ;
< 2050 ns> : 1 0 0 00000000 4 dbf98641 ?******** ?* ?* 0 1 ;
< 2100 ns> : 0 0 0 00000000 4 ca0093fd ?******** ?* ?* 0 1 ;
< 2150 ns> : 1 0 0 00000000 4 ca0093fd ?******** ?* ?* 0 1 ;
< 2200 ns> : 0 0 0 00000000 4 d4d1c6f8 ?******** ?* ?* 0 1 ;
< 2250 ns> : 1 0 0 00000000 4 d4d1c6f8 ?******** ?* ?* 0 1 ;
< 2300 ns> : 0 0 0 00000000 4 7c839d87 ?******** ?* ?* 0 1 ;
< 2350 ns> : 1 0 0 00000000 4 7c839d87 ?******** ?* ?* 0 1 ;
< 2400 ns> : 0 0 0 00000000 4 caf2b8bc ?******** ?* ?* 0 1 ;
< 2450 ns> : 1 0 0 00000000 4 caf2b8bc ?******** ?* ?* 0 1 ;
< 2500 ns> : 0 0 0 00000000 4 11f915bc ?******** ?* ?* 0 1 ;
< 2550 ns> : 1 0 0 00000000 4 11f915bc ?******** ?* ?* 0 1 ;
< 2600 ns> : 0 0 0 00000000 4 ef44a541 ?******** ?* ?* 0 1 ;
< 2650 ns> : 1 0 0 00000000 4 ef44a541 ?******** ?* ?* 0 1 ;
< 2700 ns> : 0 0 0 00000000 4 a8525b7f ?******** ?* ?* 0 1 ;
< 2750 ns> : 1 0 0 00000000 4 a8525b7f ?******** ?* ?* 0 1 ;
< 2800 ns> : 0 0 0 00000000 4 b671253b ?******** ?* ?* 0 1 ;
< 2850 ns> : 1 0 0 00000000 4 b671253b ?******** ?* ?* 0 1 ;
< 2900 ns> : 0 0 0 00000000 4 db0bad00 ?******** ?* ?* 0 1 ;
< 2950 ns> : 1 0 0 00000000 4 db0bad00 ?******** ?* ?* 0 1 ;
< 3000 ns> : 0 0 0 00000000 4 3d80477d ?******** ?* ?* 0 1 ;
< 3050 ns> : 1 0 0 00000000 4 3d80477d ?******** ?* ?* 0 1 ;
< 3100 ns> : 0 0 0 00000000 4 4716fe3e ?******** ?* ?* 0 1 ;
< 3150 ns> : 1 0 0 00000000 4 4716fe3e ?******** ?* ?* 0 1 ;
< 3200 ns> : 0 0 0 00000000 4 1e237e44 ?******** ?* ?* 0 1 ;
< 3250 ns> : 1 0 0 00000000 4 1e237e44 ?******** ?* ?* 0 1 ;
< 3300 ns> : 0 0 0 00000000 4 6d7a883b ?******** ?* ?* 0 1 ;
< 3350 ns> : 1 0 0 00000000 4 6d7a883b ?******** ?* ?* 0 1 ;
< 3400 ns> : 0 0 0 00000000 4 f2c295f2 ?******** ?* ?* 0 1 ;
< 3450 ns> : 1 0 0 00000000 4 f2c295f2 ?******** ?* ?* 0 1 ;
< 3500 ns> : 0 0 0 00000000 4 7a96b943 ?******** ?* ?* 0 1 ;
< 3550 ns> : 1 0 0 00000000 4 7a96b943 ?******** ?* ?* 0 1 ;
< 3600 ns> : 0 0 0 00000000 4 5935807a ?******** ?* ?* 0 1 ;
< 3650 ns> : 1 0 0 00000000 4 5935807a ?******** ?* ?* 0 1 ;
< 3700 ns> : 0 0 0 00000000 4 7359f67f ?******** ?* ?* 0 1 ;
< 3750 ns> : 1 0 0 00000000 4 7359f67f ?******** ?* ?* 0 1 ;
< 3800 ns> : 0 0 0 00000000 4 a0fafe17 ?******** ?* ?* 0 1 ;
< 3850 ns> : 1 0 0 00000000 4 a0fafe17 ?******** ?* ?* 0 1 ;
< 3900 ns> : 0 0 0 00000000 4 88542cb1 ?******** ?* ?* 0 1 ;
< 3950 ns> : 1 0 0 00000000 4 88542cb1 ?******** ?* ?* 0 1 ;
< 4000 ns> : 0 0 0 00000000 4 23a33939 ?******** ?* ?* 0 1 ;
< 4050 ns> : 1 0 0 00000000 4 23a33939 ?******** ?* ?* 0 1 ;
< 4100 ns> : 0 0 0 00000000 4 2a6c7605 ?******** ?* ?* 0 1 ;
< 4150 ns> : 1 0 0 00000000 4 2a6c7605 ?******** ?* ?* 0 1 ;
< 4200 ns> : 0 0 0 00000000 4 2b7e1516 ?******** ?* ?* 0 1 ;
< 4250 ns> : 1 0 0 00000000 4 2b7e1516 ?******** ?* ?* 0 1 ;
< 4300 ns> : 0 0 0 00000000 4 28aed2a6 ?******** ?* ?* 0 1 ;
< 4350 ns> : 1 0 0 00000000 4 28aed2a6 ?******** ?* ?* 0 1 ;
< 4400 ns> : 0 0 0 00000000 4 abf71588 ?******** ?* ?* 0 1 ;
< 4450 ns> : 1 0 0 00000000 4 abf71588 ?******** ?* ?* 0 1 ;
< 4500 ns> : 0 0 0 00000000 4 09cf4f3c ?******** ?* ?* 0 1 ;
< 4550 ns> : 1 0 0 00000000 4 09cf4f3c ?******** ?* ?* 0 1 ;
< 4600 ns> : 0 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 4650 ns> : 1 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 4700 ns> : 0 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 4750 ns> : 1 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 4800 ns> : 0 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 4850 ns> : 1 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 4900 ns> : 0 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 4950 ns> : 1 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 5000 ns> : 0 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 5050 ns> : 1 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 5100 ns> : 0 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 5150 ns> : 1 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 5200 ns> : 0 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 5250 ns> : 1 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 5300 ns> : 0 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 5350 ns> : 1 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 5400 ns> : 0 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 5450 ns> : 1 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 5500 ns> : 0 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 5550 ns> : 1 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 5600 ns> : 0 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 5650 ns> : 1 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 5700 ns> : 0 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 5750 ns> : 1 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 5800 ns> : 0 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 5850 ns> : 1 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 5900 ns> : 0 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 5950 ns> : 1 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 6000 ns> : 0 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 6050 ns> : 1 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 6100 ns> : 0 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 6150 ns> : 1 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 6200 ns> : 0 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 6250 ns> : 1 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 6300 ns> : 0 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 6350 ns> : 1 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 6400 ns> : 0 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 6450 ns> : 1 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 6500 ns> : 0 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 6550 ns> : 1 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 6600 ns> : 0 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
< 6650 ns> : 1 0 0 00000000 4 00000000 ?******** ?* ?* 0 1 ;
 
end;
/nfcc/trunk/rijndael/invcipher/key2.lst
0,0 → 1,52
0x00010203
0x04050607
0x08090a0b
0x0c0d0e0f
0x10111213
0x14151617
0x5846f2f9
0x5c43f4fe
0x544afef5
0x5847f0fa
0x4856e2e9
0x5c43f4fe
0x40f949b3
0x1cbabd4d
0x48f043b8
0x10b7b342
0x58e151ab
0x04a2a555
0x7effb541
0x6245080c
0x2ab54bb4
0x3a02f8f6
0x62e3a95d
0x66410c08
0xf5018572
0x97448d7e
0xbdf1c6ca
0x87f33e3c
0xe5109761
0x83519b69
0x34157c9e
0xa351f1e0
0x1ea0372a
0x99530916
0x7c439e77
0xff12051e
0xdd7e0e88
0x7e2fff68
0x608fc842
0xf9dcc154
0x859f5f23
0x7a8d5a3d
0xc0c02952
0xbeefd63a
0xde601e78
0x27bcdf2c
0xa223800f
0xd8aeda32
0xa4970a33
0x1a78dc09
0xc418c271
0xe3a41d5d
/nfcc/trunk/rijndael/invcipher/key3.lst
0,0 → 1,60
0x00010203
0x04050607
0x08090a0b
0x0c0d0e0f
0x10111213
0x14151617
0x18191a1b
0x1c1d1e1f
0xa573c29f
0xa176c498
0xa97fce93
0xa572c09c
0x1651a8cd
0x0244beda
0x1a5da4c1
0x0640bade
0xae87dff0
0x0ff11b68
0xa68ed5fb
0x03fc1567
0x6de1f148
0x6fa54f92
0x75f8eb53
0x73b8518d
0xc656827f
0xc9a79917
0x6f294cec
0x6cd5598b
0x3de23a75
0x524775e7
0x27bf9eb4
0x5407cf39
0x0bdc905f
0xc27b0948
0xad5245a4
0xc1871c2f
0x45f5a660
0x17b2d387
0x300d4d33
0x640a820a
0x7ccff71c
0xbeb4fe54
0x13e6bbf0
0xd261a7df
0xf01afafe
0xe7a82979
0xd7a5644a
0xb3afe640
0x2541fe71
0x9bf50025
0x8813bbd5
0x5a721c0a
0x4e5a6699
0xa9f24fe0
0x7e572baa
0xcdf8cdea
0x24fc79cc
0xbf0979e9
0x371ac23c
0x6d68de36
/nfcc/trunk/rijndael/invcipher/invcipher.vhdl
0,0 → 1,351
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
--
-- InvCipher (byte in[4*Nb], byte out[4*Nb], word w[Nb*(Nr+1)])
-- begin
-- byte state[4,Nb]
-- state = in
--
-- AddRoundKey(state, w[Nr*Nb, (Nr+1)*Nb-1])
--
-- for round = Nr-1 step -1 downto 1
-- InvShiftRows(state)
-- InvSubBytes(state)
-- AddRoundKey(state, w[round*Nb, (round+1)*Nb-1])
-- InvMixColumns(state)
-- end for
--
-- InvShiftRows(state)
-- InvSubBytes(state)
-- AddRoundKey(state, w[0, Nb-1])
--
-- out = state
-- end
--
--
-- EqInvCipher (byte in[4*Nb], byte out[4*Nb], word dw[Nb*(Nr+1)])
-- begin
-- byte state[4,Nb]
-- state = in
--
-- AddRoundKey(state, dw[Nr*Nb, (Nr+1)*Nb-1])
--
-- for round = Nr-1 step -1 downto 1
-- InvSubBytes(state)
-- InvShiftRows(state)
-- InvMixColumns(state)
-- AddRoundKey(state, dw[round*Nb, (round+1)*Nb-1])
-- end for
--
-- InvSubBytes(state)
-- InvShiftRows(state)
-- AddRoundKey(state, dw[0, Nb-1])
--
-- out = state
-- end
--
-- for i = 0 step 1 to (Nr+1)*Nb-1
-- dw[i] = w[i]
-- end for
--
-- for round = 1 step 1 to Nr-1
-- InvMixColumns(dw[round*Nb, (round+1)*Nb-1]);
-- end for
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity invcipher is
port (
ct : in bit_vector ( 31 downto 0); -- cipher text
key : in bit_vector ( 31 downto 0); -- source key
Nk : in bit_vector ( 3 downto 0); --
ldct : in bit; -- load cipher text
pt : out bit_vector ( 31 downto 0); -- plain text
v : out bit; -- valid plain text output
clk : in bit; -- master clock
rst : in bit -- master reset
);
end invcipher;
 
architecture phy of invcipher is
 
component invsbox
port (
di : in bit_vector ( 7 downto 0);
do : out bit_vector ( 7 downto 0)
);
end component;
 
component c2b
port (
cnt : out bit_vector ( 1 downto 0);
clk : in bit;
rst : in bit
);
end component;
 
component xtime_2
port (
x2i : in bit_vector ( 7 downto 0);
x2o : out bit_vector ( 7 downto 0)
);
end component;
 
component xtime_4
port (
x4i : in bit_vector ( 7 downto 0);
x4o : out bit_vector ( 7 downto 0)
);
end component;
 
signal ireg1 : bit_vector (127 downto 0); -- 128 bit internal register 1
signal ireg2 : bit_vector (127 downto 0); -- 128 bit internal register 2
signal ct2b : bit_vector ( 1 downto 0); -- 2 bit counter
signal wsb1 : bit_vector ( 31 downto 0); -- SubBytes
signal wsb2 : bit_vector ( 31 downto 0); -- SubBytes
signal wsr : bit_vector ( 31 downto 0); -- ShiftRows
signal wmc : bit_vector ( 31 downto 0); -- MixColumns
signal iwmc : bit_vector ( 31 downto 0); -- InvMixColumns
signal ssm : bit_vector ( 31 downto 0); -- SubBytes, ShiftRows, MixColumns
signal ikey : bit_vector ( 31 downto 0); -- internal round key
signal rnd : bit_vector ( 3 downto 0); -- current round number
signal rnd_cr : bit_vector ( 3 downto 0); -- currend round number carry
signal ict : bit_vector ( 31 downto 0); -- internal cipher text
signal s1i : bit_vector ( 7 downto 0); -- Input SubBytes 1
signal s2i : bit_vector ( 7 downto 0); -- Input SubBytes 2
signal s3i : bit_vector ( 7 downto 0); -- Input SubBytes 3
signal s4i : bit_vector ( 7 downto 0); -- Input SubBytes 4
signal s1o : bit_vector ( 7 downto 0); -- Output SubBytes 1
signal s2o : bit_vector ( 7 downto 0); -- Output SubBytes 2
signal s3o : bit_vector ( 7 downto 0); -- Output SubBytes 3
signal s4o : bit_vector ( 7 downto 0); -- Output SubBytes 4
signal x2ai : bit_vector ( 7 downto 0); -- Input xtime 2 a
signal x2bi : bit_vector ( 7 downto 0); -- Input xtime 2 b
signal x2ci : bit_vector ( 7 downto 0); -- Input xtime 2 c
signal x2di : bit_vector ( 7 downto 0); -- Input xtime 2 d
signal x2ao : bit_vector ( 7 downto 0); -- Output xtime 2 a
signal x2bo : bit_vector ( 7 downto 0); -- Output xtime 2 b
signal x2co : bit_vector ( 7 downto 0); -- Output xtime 2 c
signal x2do : bit_vector ( 7 downto 0); -- Output xtime 2 d
signal x4ai : bit_vector ( 7 downto 0); -- Input xtime 4 a
signal x4bi : bit_vector ( 7 downto 0); -- Input xtime 4 b
signal x4ci : bit_vector ( 7 downto 0); -- Input xtime 4 c
signal x4di : bit_vector ( 7 downto 0); -- Input xtime 4 d
signal x4ao : bit_vector ( 7 downto 0); -- Output xtime 4 a
signal x4bo : bit_vector ( 7 downto 0); -- Output xtime 4 b
signal x4co : bit_vector ( 7 downto 0); -- Output xtime 4 c
signal x4do : bit_vector ( 7 downto 0); -- Output xtime 4 d
signal ct2b_rst : bit; -- reset for internal block operation
signal swp : bit; -- swap internal register
signal swp1 : bit; -- swap internal register
signal vld : bit; -- final round
signal vld1 : bit; -- final round
signal ildct : bit; -- internal load cipher text
signal ildct_rst : bit; -- internal load cipher text reset
 
begin
 
sb1 : invsbox
port map (
di => s1i,
do => s1o
);
sb2 : invsbox
port map (
di => s2i,
do => s2o
);
sb3 : invsbox
port map (
di => s3i,
do => s3o
);
sb4 : invsbox
port map (
di => s4i,
do => s4o
);
ctr1 : c2b
port map (
cnt => ct2b,
clk => clk,
rst => ct2b_rst
);
x2a : xtime_2
port map (
x2i => x2ai,
x2o => x2ao
);
x2b : xtime_2
port map (
x2i => x2bi,
x2o => x2bo
);
x2c : xtime_2
port map (
x2i => x2ci,
x2o => x2co
);
x2d : xtime_2
port map (
x2i => x2di,
x2o => x2do
);
x4a : xtime_4
port map (
x4i => x4ai,
x4o => x4ao
);
x4b : xtime_4
port map (
x4i => x4bi,
x4o => x4bo
);
x4c : xtime_4
port map (
x4i => x4ci,
x4o => x4co
);
x4d : xtime_4
port map (
x4i => x4di,
x4o => x4do
);
 
-- 7 39 71 103 | 7 39 71 103 | 7 39 71 103
-- 15 47 79 111 | 47 79 111 15 | 111 15 47 79
-- 23 55 87 119 | 87 119 23 55 | 87 119 23 55
-- 31 63 95 127 | 127 31 63 95 | 63 95 127 31
with ct2b( 1 downto 0) select
wsb1 <= ireg1( 63 downto 56) & ireg1( 87 downto 80) & ireg1(111 downto 104) & ireg1( 7 downto 0) when B"10", -- 1st column
ireg1( 95 downto 88) & ireg1(119 downto 112) & ireg1( 15 downto 8) & ireg1( 39 downto 32) when B"01", -- 4th column
ireg1(127 downto 120) & ireg1( 23 downto 16) & ireg1( 47 downto 40) & ireg1( 71 downto 64) when B"00", -- 3rd column
ireg1( 31 downto 24) & ireg1( 55 downto 48) & ireg1( 79 downto 72) & ireg1(103 downto 96) when B"11"; -- 2nd column
with ct2b( 1 downto 0) select
wsb2 <= ireg2( 63 downto 56) & ireg2( 87 downto 80) & ireg2(111 downto 104) & ireg2( 7 downto 0) when B"10", -- 1st column
ireg2( 95 downto 88) & ireg2(119 downto 112) & ireg2( 15 downto 8) & ireg2( 39 downto 32) when B"01", -- 4th column
ireg2(127 downto 120) & ireg2( 23 downto 16) & ireg2( 47 downto 40) & ireg2( 71 downto 64) when B"00", -- 3rd column
ireg2( 31 downto 24) & ireg2( 55 downto 48) & ireg2( 79 downto 72) & ireg2(103 downto 96) when B"11"; -- 2nd column
--SubBytes
s1i( 7 downto 0) <= wsb1( 31 downto 24) when swp = '1' else wsb2( 31 downto 24);
s2i( 7 downto 0) <= wsb1( 23 downto 16) when swp = '1' else wsb2( 23 downto 16);
s3i( 7 downto 0) <= wsb1( 15 downto 8) when swp = '1' else wsb2( 15 downto 8);
s4i( 7 downto 0) <= wsb1( 7 downto 0) when swp = '1' else wsb2( 7 downto 0);
 
--ShiftRows
wsr <= s1o & s2o & s3o & s4o;
 
--MixColumns -- addroundkey first
x2ai <= wsr( 31 downto 24) xor ikey( 31 downto 24);
x2bi <= wsr( 23 downto 16) xor ikey( 23 downto 16);
x2ci <= wsr( 15 downto 8) xor ikey( 15 downto 8);
x2di <= wsr( 7 downto 0) xor ikey( 7 downto 0);
 
wmc( 31 downto 24) <= x2ao xor x2bo xor x2bi xor x2ci xor x2di;
wmc( 23 downto 16) <= x2ai xor x2bo xor x2co xor x2ci xor x2di;
wmc( 15 downto 8) <= x2ai xor x2bi xor x2co xor x2do xor x2di;
wmc( 7 downto 0) <= x2ao xor x2ai xor x2bi xor x2ci xor x2do;
 
--InvMixColumns
x4ai <= wmc( 31 downto 24);
x4bi <= wmc( 23 downto 16);
x4ci <= wmc( 15 downto 8);
x4di <= wmc( 7 downto 0);
 
iwmc( 31 downto 24) <= x4ao xor x4ai xor x4co ;
iwmc( 23 downto 16) <= x4bo xor x4bi xor x4do ;
iwmc( 15 downto 8) <= x4co xor x4ci xor x4ao ;
iwmc( 7 downto 0) <= x4do xor x4di xor x4bo ;
 
process (clk)
begin
if ((clk = '1') and clk'event) then
ildct <= ldct;
end if;
end process;
ildct_rst <= ((ildct xor ldct) and ldct);
ct2b_rst <= rst or ildct_rst;
 
rnd_cr(0) <= '0'; -- LSB always zero
rnd_cr(3 downto 1) <= ( ((rnd(2 downto 0) and B"001") or (rnd(2 downto 0) and rnd_cr(2 downto 0))) or (B"001" and rnd_cr(2 downto 0)) );
 
process (clk)
begin
if ((clk = '1') and clk'event) then
if ((ildct_rst or rst) = '1') then
swp <= '0';
rnd <= B"0000";
elsif (not(not(ct2b(1)) or not(ct2b(0))) = '1') then
swp <= not(swp);
rnd <= ((rnd xor B"0001") xor rnd_cr);
end if;
end if;
end process;
 
vld <= (not(Nk(3) or not(Nk(2)) or Nk(1) or Nk(0)) and not(not(rnd(3)) or rnd(2) or not(rnd(1)) or rnd(0))) or -- Nk 0100 (10 round)
(not(Nk(3) or not(Nk(2)) or not(Nk(1)) or Nk(0)) and not(not(rnd(3)) or not(rnd(2)) or rnd(1) or rnd(0))) or -- Nk 0110 (12 round)
(not(not(Nk(3)) or Nk(2) or Nk(1) or Nk(0)) and not(not(rnd(3)) or not(rnd(2)) or not(rnd(1)) or rnd(0))); -- Nk 1000 (14 round)
 
ikey <= key;
ssm <= iwmc when vld = '0' else wsr xor ikey;
 
process (clk)
begin
if ((clk = '1') and clk'event) then
if (rst = '1') then
ireg1(127 downto 0) <= (others => '0');
ireg2(127 downto 0) <= (others => '0');
elsif (ildct = '1') then
ireg1(127 downto 0) <= ireg1( 95 downto 0) & (ict xor ikey); -- initial round
elsif ( swp = '0') then
ireg1(127 downto 0) <= ireg1( 95 downto 0) & (ssm);
else
ireg2(127 downto 0) <= ireg2( 95 downto 0) & (ssm);
end if;
end if;
end process;
 
process (clk)
begin
if ((clk = '1') and clk'event) then
swp1 <= swp;
vld1 <= vld;
ict <= ct;
end if;
end process;
 
pt <= ireg1( 31 downto 0) when swp1 = '0' else ireg2( 31 downto 0);
v <= vld1;
 
end phy;
/nfcc/trunk/rijndael/invcipher/visual.c
0,0 → 1,29
#include <stdio.h>
 
#define st 4
#define nb 4
#define nR 10
main(int argc, char *argv[])
{
int r,i,j,v,nr;
// char state[st][4]= {"ad", "sb", "sr", "mx"};
char state[st][20]= {"AddRoundKey", "SubBytes", "ShiftRows", "MixColumns"};
 
nr = nR;
if (argc > 1 ) sscanf(argv[1], "%d", &nr);
 
// printf("%3s -- %3s -- %3s \n", "Seq", "Fwd", "Inv");
 
r = 0; // initial round equal 0
v = nr+1; // total there is nr+1 operation
for ( j = 0; j < nr + 1; j ++) {
for (i = 0; i < st; i++) {
if (i == 1) r++;
if (i == 3) v--;
if ( !((j == nr) && (i == 3)))
printf("%3d -- %3d(0x%x) -- %3d -- %11s -- %3d -- %3d(0x%x) -- %3d\n", j, r, r, i, state[i], 3-i, v, v, nr-j);
else
printf("%3d -- %3d(0x%x) -- %3d -- %11s -- %3d -- %3d(0x%x) -- %3d\n", j, r, r, i, state[i-3], 3-i, v, v, nr-j);
}
}
}
/nfcc/trunk/rijndael/invcipher/invct.lst
0,0 → 1,4
0x196a0b32
0xdc118597
0x02dc09fb
0x3925841d
/nfcc/trunk/rijndael/invcipher/invkey1.lst
0,0 → 1,44
0x13111d7f
0xe3944a17
0xf307a78b
0x4d2b30c5
0x549932d1
0xf0855768
0x1093ed9c
0xbe2c974e
0x47438735
0xa41c65b9
0xe016baf4
0xaebf7ad2
0x14f9701a
0xe35fe28c
0x440adf4d
0x4ea9c026
0x5e390f7d
0xf7a69296
0xa7553dc1
0x0aa31f6b
0x3caaa3e8
0xa99f9deb
0x50f3af57
0xadf622aa
0x47f7f7bc
0x95353e03
0xf96c32bc
0xfd058dfd
0xb6ff744e
0xd2c2c9bf
0x6c590cbf
0x0469bf41
0xb692cf0b
0x643dbdf1
0xbe9bc500
0x6830b3fe
0xd6aa74fd
0xd2af72fa
0xdaa678f1
0xd6ab76fe
0x00010203
0x04050607
0x08090a0b
0x0c0d0e0f
/nfcc/trunk/rijndael/invcipher/invkey2.lst
0,0 → 1,52
0xa4970a33
0x1a78dc09
0xc418c271
0xe3a41d5d
0xde601e78
0x27bcdf2c
0xa223800f
0xd8aeda32
0x859f5f23
0x7a8d5a3d
0xc0c02952
0xbeefd63a
0xdd7e0e88
0x7e2fff68
0x608fc842
0xf9dcc154
0x1ea0372a
0x99530916
0x7c439e77
0xff12051e
0xe5109761
0x83519b69
0x34157c9e
0xa351f1e0
0xf5018572
0x97448d7e
0xbdf1c6ca
0x87f33e3c
0x2ab54bb4
0x3a02f8f6
0x62e3a95d
0x66410c08
0x58e151ab
0x04a2a555
0x7effb541
0x6245080c
0x40f949b3
0x1cbabd4d
0x48f043b8
0x10b7b342
0x544afef5
0x5847f0fa
0x4856e2e9
0x5c43f4fe
0x10111213
0x14151617
0x5846f2f9
0x5c43f4fe
0x00010203
0x04050607
0x08090a0b
0x0c0d0e0f
/nfcc/trunk/rijndael/invcipher/ct1.lst
0,0 → 1,4
0x69c4e0d8
0x6a7b0430
0xd8cdb780
0x70b4c55a
/nfcc/trunk/rijndael/invcipher/invkey3.lst
0,0 → 1,60
0x24fc79cc
0xbf0979e9
0x371ac23c
0x6d68de36
0x4e5a6699
0xa9f24fe0
0x7e572baa
0xcdf8cdea
0x2541fe71
0x9bf50025
0x8813bbd5
0x5a721c0a
0xf01afafe
0xe7a82979
0xd7a5644a
0xb3afe640
0x7ccff71c
0xbeb4fe54
0x13e6bbf0
0xd261a7df
0x45f5a660
0x17b2d387
0x300d4d33
0x640a820a
0x0bdc905f
0xc27b0948
0xad5245a4
0xc1871c2f
0x3de23a75
0x524775e7
0x27bf9eb4
0x5407cf39
0xc656827f
0xc9a79917
0x6f294cec
0x6cd5598b
0x6de1f148
0x6fa54f92
0x75f8eb53
0x73b8518d
0xae87dff0
0x0ff11b68
0xa68ed5fb
0x03fc1567
0x1651a8cd
0x0244beda
0x1a5da4c1
0x0640bade
0xa573c29f
0xa176c498
0xa97fce93
0xa572c09c
0x10111213
0x14151617
0x18191a1b
0x1c1d1e1f
0x00010203
0x04050607
0x08090a0b
0x0c0d0e0f
/nfcc/trunk/rijndael/invcipher/ct2.lst
0,0 → 1,4
0xdda97ca4
0x864cdfe0
0x6eaf70a0
0xec0d7191
/nfcc/trunk/rijndael/invcipher/ct3.lst
0,0 → 1,4
0x8ea2b7ca
0x516745bf
0xeafc4990
0x4b496089
/nfcc/trunk/rijndael/invcipher/c2b.vhdl
0,0 → 1,59
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity c2b is
port (
cnt : out bit_vector ( 1 downto 0);
clk : in bit;
rst : in bit
);
end c2b;
 
architecture phy of c2b is
signal sum : bit_vector ( 1 downto 0); -- sum
signal cr : bit_vector ( 1 downto 0); -- carry
begin
cr(0) <= '0'; -- LSB always zero
cr(1) <= sum(0);
process (clk)
begin
if (clk = '1' and clk'event) then
if (rst = '1') then
sum <= B"00";
else
sum <= ((sum xor B"01") xor cr); -- sum = ((addend xor augend) xor carry)
end if;
end if;
end process;
cnt <= sum;
end phy;
/nfcc/trunk/rijndael/invcipher/fread.c
0,0 → 1,53
#include <stdio.h>
#include <string.h>
 
main(int argc, char *argv[])
{
FILE *f;
char *fname = "key.lst";
int c,i;
const int rot[4] = { -3, -1, 1, 3 };
char key[60][20];
 
if (argc > 1) {
fname = argv[1]; /*
i = 1;
printf("%3d ", argc);
while (i < argc) {
printf ("-- %s ", argv[i]);
i++;
}
printf("\n"); */
}
 
if(fname && (f = fopen(fname, "rt"))) {
i = 0;
while(fgets(key[i],sizeof(key[i]),f) != NULL) {
c = strlen(key[i]);
if(key[i][c-1] == '\n') key[i][c-1] = '\0';
i++;
}
fclose (f);
} else {
fclose (f);
}
/*
if (fname && (f = fopen ( fname, "rt"))) {
printf ("Success opening %s, ", fname);
} else {
fclose (f);
}
 
i = 0;
while(fgets(key[i],sizeof(key[i]),f) != NULL){
c = strlen(key[i]);
if(key[i][c-1] == '\n') key[i][c-1] = '\0';
i++;
}
printf("got %3d lines\n", i);
*/
for (c = i-1 ; c >= 0; c--) printf("%s\n", key[(c-rot[c%4])]);
// for (c = i-1 ; c >= 0; c--) printf("%3d -- %3d -- %s\t%s\n", c, c%4, key[c], key[(c-rot[c%4])]);
 
fclose (f);
}
/nfcc/trunk/rijndael/invcipher/c3b.vhdl
0,0 → 1,59
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity c3b is
port (
cnt : out bit_vector (02 downto 00);
clk : in bit;
rst : in bit
);
end c3b;
 
architecture phy of c3b is
signal sum : bit_vector (02 downto 00) := B"111"; -- sum
signal cr : bit_vector (02 downto 00) := B"000"; -- carry
begin
cr(0) <= '0'; -- LSB always zero
cr(02 downto 01) <= ( ((sum(01 downto 00) and B"01") or (sum(01 downto 00) and cr(01 downto 00))) or (B"01" and cr(01 downto 00)) );
process (clk)
begin
if (clk = '1' and clk'event) then
if (rst = '1') then
sum <= B"000"; -- we start counting from 0
else
sum <= ((sum xor B"001") xor cr); -- sum = ((addend xor augend) xor carry)
end if;
end if;
end process;
cnt <= sum;
end phy;
/nfcc/trunk/rijndael/invcipher/c4b.vhdl
0,0 → 1,59
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity c4b is
port (
cnt : out bit_vector ( 3 downto 0);
clk : in bit;
rst : in bit
);
end c4b;
 
architecture phy of c4b is
signal sum : bit_vector ( 3 downto 0); -- sum
signal cr : bit_vector ( 3 downto 0); -- carry
begin
cr(0) <= '0'; -- LSB always zero
cr(3 downto 1) <= ( ((sum(2 downto 0) and B"001") or (sum(2 downto 0) and cr(2 downto 0))) or (B"001" and cr(2 downto 0)) );
process (clk)
begin
if (clk = '1' and clk'event) then
if (rst = '1') then
sum <= B"0000";
else
sum <= ((sum xor B"0001") xor cr); -- sum = ((addend xor augend) xor carry)
end if;
end if;
end process;
cnt <= sum;
end phy;
/nfcc/trunk/rijndael/invcipher/invkey.lst
0,0 → 1,44
0xd014f9a8
0xc9ee2589
0xe13f0cc8
0xb6630ca6
0xac7766f3
0x19fadc21
0x28d12941
0x575c006e
0xead27321
0xb58dbad2
0x312bf560
0x7f8d292f
0x4e54f70e
0x5f5fc9f3
0x84a64fb2
0x4ea6dc4f
0x6d88a37a
0x110b3efd
0xdbf98641
0xca0093fd
0xd4d1c6f8
0x7c839d87
0xcaf2b8bc
0x11f915bc
0xef44a541
0xa8525b7f
0xb671253b
0xdb0bad00
0x3d80477d
0x4716fe3e
0x1e237e44
0x6d7a883b
0xf2c295f2
0x7a96b943
0x5935807a
0x7359f67f
0xa0fafe17
0x88542cb1
0x23a33939
0x2a6c7605
0x2b7e1516
0x28aed2a6
0xabf71588
0x09cf4f3c
/nfcc/trunk/rijndael/invcipher/c6b.vhdl
0,0 → 1,59
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity c6b is
port (
cnt : out bit_vector ( 5 downto 0);
clk : in bit;
rst : in bit
);
end c6b;
 
architecture phy of c6b is
signal sum : bit_vector ( 5 downto 0); -- sum
signal cr : bit_vector ( 5 downto 0); -- carry
begin
cr(0) <= '0'; -- LSB always zero
cr(5 downto 1) <= ( ((sum(4 downto 0) and B"00001") or (sum(4 downto 0) and cr(4 downto 0))) or (B"00001" and cr(4 downto 0)) );
process (clk)
begin
if (clk = '1' and clk'event) then
if (rst = '1') then
sum <= B"000000";
else
sum <= ((sum xor B"000001") xor cr); -- sum = ((addend xor augend) xor carry)
end if;
end if;
end process;
cnt <= sum;
end phy;
/nfcc/trunk/rijndael/cipher/extract.sh
0,0 → 1,5
if [ ! -z $1 ]; then
awk -F? '{print $2}' $1 | sed -e 's/ //g' | uniq.exe | sed -e 's/^/0x/'
else
echo "Usage $0: asimut-keyexpansion-output-file"
fi
/nfcc/trunk/rijndael/cipher/key.vhdl
0,0 → 1,223
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity key is
port (
st : in bit_vector ( 7 downto 0);
Nk : in bit_vector ( 3 downto 0);
key: out bit_vector (31 downto 0) -- 32 bit key output
);
end key;
 
architecture phy of key is
signal keya : bit_vector (31 downto 0);
signal keyb : bit_vector (31 downto 0);
signal keyc : bit_vector (31 downto 0);
begin
 
with Nk(3 downto 0) select
key <=
keya when X"4",
keyb when X"6",
keyc when X"8",
X"00000000" when others;
 
with st(7 downto 0) select
keya <=
X"2b7e1516" when X"00", -- 0
X"28aed2a6" when X"01", -- 1
X"abf71588" when X"02", -- 2
X"09cf4f3c" when X"03", -- 3
X"a0fafe17" when X"04", -- 4
X"88542cb1" when X"05", -- 5
X"23a33939" when X"06", -- 6
X"2a6c7605" when X"07", -- 7
X"f2c295f2" when X"08", -- 8
X"7a96b943" when X"09", -- 9
X"5935807a" when X"0a", -- 0
X"7359f67f" when X"0b", -- 1
X"3d80477d" when X"0c", -- 2
X"4716fe3e" when X"0d", -- 3
X"1e237e44" when X"0e", -- 4
X"6d7a883b" when X"0f", -- 5
X"ef44a541" when X"10", -- 6
X"a8525b7f" when X"11", -- 7
X"b671253b" when X"12", -- 8
X"db0bad00" when X"13", -- 9
X"d4d1c6f8" when X"14", -- 0
X"7c839d87" when X"15", -- 1
X"caf2b8bc" when X"16", -- 2
X"11f915bc" when X"17", -- 3
X"6d88a37a" when X"18", -- 4
X"110b3efd" when X"19", -- 5
X"dbf98641" when X"1a", -- 6
X"ca0093fd" when X"1b", -- 7
X"4e54f70e" when X"1c", -- 8
X"5f5fc9f3" when X"1d", -- 9
X"84a64fb2" when X"1e", -- 0
X"4ea6dc4f" when X"1f", -- 1
X"ead27321" when X"20", -- 2
X"b58dbad2" when X"21", -- 3
X"312bf560" when X"22", -- 4
X"7f8d292f" when X"23", -- 5
X"ac7766f3" when X"24", -- 6
X"19fadc21" when X"25", -- 7
X"28d12941" when X"26", -- 8
X"575c006e" when X"27", -- 9
X"d014f9a8" when X"28", -- 0
X"c9ee2589" when X"29", -- 1
X"e13f0cc8" when X"2a", -- 2
X"b6630ca6" when X"2b", -- 3
X"00000000" when others;
 
with st(7 downto 0) select
keyb <=
X"8e73b0f7" when X"00",
X"da0e6452" when X"01",
X"c810f32b" when X"02",
X"809079e5" when X"03",
X"62f8ead2" when X"04",
X"522c6b7b" when X"05",
X"fe0c91f7" when X"06",
X"2402f5a5" when X"07",
X"ec12068e" when X"08",
X"6c827f6b" when X"09",
X"0e7a95b9" when X"0a",
X"5c56fec2" when X"0b",
X"4db7b4bd" when X"0c",
X"69b54118" when X"0d",
X"85a74796" when X"0e",
X"e92538fd" when X"0f",
X"e75fad44" when X"10",
X"bb095386" when X"11",
X"485af057" when X"12",
X"21efb14f" when X"13",
X"a448f6d9" when X"14",
X"4d6dce24" when X"15",
X"aa326360" when X"16",
X"113b30e6" when X"17",
X"a25e7ed5" when X"18",
X"83b1cf9a" when X"19",
X"27f93943" when X"1a",
X"6a94f767" when X"1b",
X"c0a69407" when X"1c",
X"d19da4e1" when X"1d",
X"ec1786eb" when X"1e",
X"6fa64971" when X"1f",
X"485f7032" when X"20",
X"22cb8755" when X"21",
X"e26d1352" when X"22",
X"33f0b7b3" when X"23",
X"40beeb28" when X"24",
X"2f18a259" when X"25",
X"6747d26b" when X"26",
X"458c553e" when X"27",
X"a7e1466c" when X"28",
X"9411f1df" when X"29",
X"821f750a" when X"2a",
X"ad07d753" when X"2b",
X"ca400538" when X"2c",
X"8fcc5006" when X"2d",
X"282d166a" when X"2e",
X"bc3ce7b5" when X"2f",
X"e98ba06f" when X"30",
X"448c773c" when X"31",
X"8ecc7204" when X"32",
X"01002202" when X"33",
X"00000000" when others;
 
with st(7 downto 0) select
keyc <=
X"603deb10" when X"00",
X"15ca71be" when X"01",
X"2b73aef0" when X"02",
X"857d7781" when X"03",
X"1f352c07" when X"04",
X"3b6108d7" when X"05",
X"2d9810a3" when X"06",
X"0914dff4" when X"07",
X"9ba35411" when X"08",
X"8e6925af" when X"09",
X"a51a8b5f" when X"0a",
X"2067fcde" when X"0b",
X"a8b09c1a" when X"0c",
X"93d194cd" when X"0d",
X"be49846e" when X"0e",
X"b75d5b9a" when X"0f",
X"d59aecb8" when X"10",
X"5bf3c917" when X"11",
X"fee94248" when X"12",
X"de8ebe96" when X"13",
X"b5a9328a" when X"14",
X"2678a647" when X"15",
X"98312229" when X"16",
X"2f6c79b3" when X"17",
X"812c81ad" when X"18",
X"dadf48ba" when X"19",
X"24360af2" when X"1a",
X"fab8b464" when X"1b",
X"98c5bfc9" when X"1c",
X"bebd198e" when X"1d",
X"268c3ba7" when X"1e",
X"09e04214" when X"1f",
X"68007bac" when X"20",
X"b2df3316" when X"21",
X"96e939e4" when X"22",
X"6c518d80" when X"23",
X"c814e204" when X"24",
X"76a9fb8a" when X"25",
X"5025c02d" when X"26",
X"59c58239" when X"27",
X"de136967" when X"28",
X"6ccc5a71" when X"29",
X"fa256395" when X"2a",
X"9674ee15" when X"2b",
X"5886ca5d" when X"2c",
X"2e2f31d7" when X"2d",
X"7e0af1fa" when X"2e",
X"27cf73c3" when X"2f",
X"749c47ab" when X"30",
X"18501dda" when X"31",
X"e2757e4f" when X"32",
X"7401905a" when X"33",
X"cafaaae3" when X"34",
X"e4d59b34" when X"35",
X"9adf6ace" when X"36",
X"bd10190d" when X"37",
X"fe4890d1" when X"38",
X"e6188d0b" when X"39",
X"046df344" when X"3a",
X"706c631e" when X"3b",
X"00000000" when others;
 
end phy;
/nfcc/trunk/rijndael/cipher/pt.lst
0,0 → 1,4
0x3243f6a8
0x885a308d
0x313198a2
0xe0370734
/nfcc/trunk/rijndael/cipher/xtime_2.c
0,0 → 1,43
#include <stdio.h>
#include "genpat.h"
 
char *inttostr(entier)
int entier;
{
char *str;
str = (char *) mbkalloc (32 * sizeof (char));
sprintf (str, "%d",entier);
return(str);
}
/*------------------------------*/
/* end of the description */
/*------------------------------*/
 
main ()
{
int i;
int cur_vect = 0;
 
DEF_GENPAT("xtime_2");
SETTUNIT("ns");
 
/* interface */
DECLAR ("x2i", ":2", "X", IN , "7 downto 0", "" );
DECLAR ("x2o", ":2", "X", OUT, "7 downto 0", "" );
DECLAR ("vss", ":1", "B", IN , "" , "" );
DECLAR ("vdd", ":1", "B", IN , "" , "" );
 
AFFECT ("0", "vss", "0b0");
AFFECT ("0", "vdd", "0b1");
AFFECT ("0", "x2i","0x00");
 
for (i=1; i<256; i++)
{
AFFECT ("+10", "x2i", inttostr(i) );
cur_vect++;
}
 
 
SAV_GENPAT ();
}
 
/nfcc/trunk/rijndael/cipher/c2b.pat
0,0 → 1,38
 
in clk B;;
in rst B;;
out cnt(1 downto 0) X;;
out cnt(1 downto 0) B;;
in vss B;;
in vdd B;;
 
begin
 
< 0ns>: 0 1 ?* ?** 0 1;
< +10ns>: 1 1 ?* ?** 0 1;
< +10ns>: 0 0 ?* ?** 0 1;
< +10ns>: 1 0 ?* ?** 0 1;
< +10ns>: 0 0 ?* ?** 0 1;
< +10ns>: 1 0 ?* ?** 0 1;
< +10ns>: 0 0 ?* ?** 0 1;
< +10ns>: 1 0 ?* ?** 0 1;
< +10ns>: 0 0 ?* ?** 0 1;
< +10ns>: 1 0 ?* ?** 0 1;
< +10ns>: 0 0 ?* ?** 0 1;
< +10ns>: 1 0 ?* ?** 0 1;
< +10ns>: 0 1 ?* ?** 0 1;
< +10ns>: 1 1 ?* ?** 0 1;
< +10ns>: 0 0 ?* ?** 0 1;
< +10ns>: 1 0 ?* ?** 0 1;
< +10ns>: 0 0 ?* ?** 0 1;
< +10ns>: 1 0 ?* ?** 0 1;
< +10ns>: 0 0 ?* ?** 0 1;
< +10ns>: 1 0 ?* ?** 0 1;
< +10ns>: 0 0 ?* ?** 0 1;
< +10ns>: 1 0 ?* ?** 0 1;
< +10ns>: 0 0 ?* ?** 0 1;
< +10ns>: 1 0 ?* ?** 0 1;
< +10ns>: 0 0 ?* ?** 0 1;
< +10ns>: 1 0 ?* ?** 0 1;
 
end;
/nfcc/trunk/rijndael/cipher/key.lst
0,0 → 1,44
0x2b7e1516
0x28aed2a6
0xabf71588
0x09cf4f3c
0xa0fafe17
0x88542cb1
0x23a33939
0x2a6c7605
0xf2c295f2
0x7a96b943
0x5935807a
0x7359f67f
0x3d80477d
0x4716fe3e
0x1e237e44
0x6d7a883b
0xef44a541
0xa8525b7f
0xb671253b
0xdb0bad00
0xd4d1c6f8
0x7c839d87
0xcaf2b8bc
0x11f915bc
0x6d88a37a
0x110b3efd
0xdbf98641
0xca0093fd
0x4e54f70e
0x5f5fc9f3
0x84a64fb2
0x4ea6dc4f
0xead27321
0xb58dbad2
0x312bf560
0x7f8d292f
0xac7766f3
0x19fadc21
0x28d12941
0x575c006e
0xd014f9a8
0xc9ee2589
0xe13f0cc8
0xb6630ca6
/nfcc/trunk/rijndael/cipher/cipher.c
0,0 → 1,154
#include <stdio.h>
#include <string.h>
#include "genpat.h"
 
char *inttostr(entier)
int entier;
{
char *str;
str = (char *) mbkalloc (32 * sizeof (char));
sprintf (str, "%d",entier);
return(str);
}
/*------------------------------*/
/* end of the description */
/*------------------------------*/
 
main (int argc, char *argv[])
{
int i,c;
int Nk,ks,ps;
char sNk[4];
FILE *f1, *f2;
char *fname1 = "key.lst";
char *fname2 = "pt.lst";
char key[80][20];
char fpt[10][20];
 
Nk = 4;
/* remember argc start from 1 not zero and command line is the first array */
if (argc > 1 ) {
if (argc == 4) {
fname1 = argv[3]; /* key */
fname2 = argv[2]; /* plain text*/
sscanf(argv[1], "%d", &Nk);
printf("Using Nk(0x%x) plain-text (%s) key (%s)\n", Nk, fname2, fname1);
} else {
printf("Usage %s: Nk plain-text key\n", argv[0]);
return 0;
}
}
 
sprintf(sNk, "0x%x", Nk);
 
if(fname1 && (f1 = fopen(fname1, "rt"))) {
i = 0;
while(fgets(key[i],sizeof(key[i]),f1) != NULL) {
c = strlen(key[i]);
if(key[i][c-1] == '\n') key[i][c-1] = '\0';
i++;
}
fclose (f1);
} else {
fclose (f1);
}
 
ks = i;
 
if(fname2 && (f2 = fopen(fname2, "rt"))) {
i = 0;
while(fgets(fpt[i],sizeof(fpt[i]),f2) != NULL) {
c = strlen(fpt[i]);
if(fpt[i][c-1] == '\n') fpt[i][c-1] = '\0';
i++;
}
fclose (f2);
} else {
fclose (f2);
}
 
ps = i;
 
DEF_GENPAT("cipher");
SETTUNIT("ns");
 
/* interface */
DECLAR ("clk", ":1", "B", IN , "" , "" );
DECLAR ("rst", ":1", "B", IN , "" , "" );
DECLAR ("ldpt",":1", "B", IN , "" , "" );
DECLAR ( "pt", ":2", "X", IN , "31 downto 0", "" );
//DECLAR ("cipher_inst_ildpt", ":1", "B", SIGNAL , "" , "" );
//DECLAR ("cipher_inst_ipt" , ":1", "X", SIGNAL , "31 downto 0", "" );
DECLAR ( "Nk", ":2", "X", IN , " 3 downto 0", "" );
//DECLAR ( "st", ":2", "X", OUT, " 7 downto 0", "" );
DECLAR ("key", ":2", "X", IN , "31 downto 0", "" );
DECLAR ( "ct", ":2", "X", OUT, "31 downto 0", "" );
DECLAR ( "v", ":1", "B", OUT, "" , "" );
DECLAR ("cipher_inst_rnd", ":1", "X", SIGNAL , " 3 downto 0" , "" );
//DECLAR ("cipher_inst_swp", ":1", "B", SIGNAL , "" , "" );
//DECLAR ("ct2b_1", ":1", "B", SIGNAL , "" , "" );
//DECLAR ("ct2b_0", ":1", "B", SIGNAL , "" , "" );
//DECLAR ("cipher_inst_ireg1", ":1", "X", SIGNAL , "127 downto 0" , "" );
//DECLAR ("cipher_inst_ireg2", ":1", "X", SIGNAL , "127 downto 0" , "" );
//DECLAR ("cipher_inst_swp1", ":1", "B", SIGNAL , "" , "" );
DECLAR ("vss", ":1", "B", IN , "" , "" );
DECLAR ("vdd", ":1", "B", IN , "" , "" );
 
AFFECT ("0", "vss", "0b0");
AFFECT ("0", "vdd", "0b1");
 
AFFECT ( "0", "pt", "0x00000000");
AFFECT ( "0", "key", "0x00000000");
AFFECT ( "0", "rst", "0b1");
AFFECT ( "0","ldpt", "0b0");
AFFECT ( "0", "Nk", sNk );
AFFECT ( "0", "clk", "0b0");
AFFECT ("+50", "clk", "0b1");
AFFECT ("+50", "clk", "0b0");
AFFECT ( "+0", "rst", "0b0");
AFFECT ( "+0","ldpt", "0b1");
 
//if(Nk==0x4)
//AFFECT ( "+0", "pt", "0x3243f6a8");
 
for (i=0; i < ps; i++)
{
AFFECT ( "+0", "pt", fpt[i]);
AFFECT ("+50", "clk", "0b1" );
AFFECT ("+50", "clk", "0b0" );
AFFECT ( "+0", "key", key[i]);
 
//if ((i==1) && (Nk==0x4))
//AFFECT ( "+0", "pt", "0x885a308d");
//if ((i==2) && (Nk==0x4))
//AFFECT ( "+0", "pt", "0x313198a2");
//if ((i==3) && (Nk==0x4))
//AFFECT ( "+0", "pt", "0xe0370734");
 
}
 
AFFECT ( "+0","ldpt", "0b0");
AFFECT ( "+0", "pt", "0x00000000");
 
for (; i < ks; i++)
{
AFFECT ("+50", "clk", "0b1" );
AFFECT ("+50", "clk", "0b0" );
AFFECT ( "+0", "key", key[i]);
}
 
AFFECT ("+50", "clk", "0b1" );
AFFECT ("+50", "clk", "0b0" );
AFFECT ( "+0", "key", "0x00000000");
 
for (; i < 64; i++)
{
AFFECT ("+50", "clk", "0b1" );
AFFECT ("+50", "clk", "0b0" );
}
 
AFFECT ("+50", "clk", "0b1");
 
SAV_GENPAT ();
}
 
/nfcc/trunk/rijndael/cipher/c6b.c
0,0 → 1,50
#include <stdio.h>
#include "genpat.h"
 
char *inttostr(entier)
int entier;
{
char *str;
str = (char *) mbkalloc (32 * sizeof (char));
sprintf (str, "%d",entier);
return(str);
}
/*------------------------------*/
/* end of the description */
/*------------------------------*/
 
main ()
{
int i;
 
DEF_GENPAT("c6b");
SETTUNIT("ns");
 
/* interface */
DECLAR ("clk", ":1", "B", IN , "" , "" );
DECLAR ("rst", ":1", "B", IN , "" , "" );
DECLAR ("cnt", ":2", "X", OUT, "5 downto 0", "" );
DECLAR ("c6b.sum",":2","X",REGISTER,"5 downto 0","");
DECLAR ("c6b.cr" ,":2","X",SIGNAL ,"5 downto 0","");
DECLAR ("vss", ":1", "B", IN , "" , "" );
DECLAR ("vdd", ":1", "B", IN , "" , "" );
 
AFFECT ("0", "vss", "0b0");
AFFECT ("0", "vdd", "0b1");
 
AFFECT ( "0", "rst", "0b1");
AFFECT ( "0", "clk", "0b0");
AFFECT ("+10", "clk", "0b1");
AFFECT ("+10", "clk", "0b0");
AFFECT ( "+0", "rst", "0b0");
 
for (i=1; i<256; i++)
{
AFFECT ("+10", "clk", "0b1" );
AFFECT ("+10", "clk", "0b0" );
}
 
 
SAV_GENPAT ();
}
 
/nfcc/trunk/rijndael/cipher/c4b.pat
0,0 → 1,80
 
in clk B;;
in rst B;;
out cnt(3 downto 0) X;;
out cnt(3 downto 0) B;;
in vss B;;
in vdd B;;
 
begin
 
< 0ns>: 0 1 ?* ?**** 0 1;
< +10ns>: 1 1 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
< +10ns>: 0 0 ?* ?**** 0 1;
< +10ns>: 1 0 ?* ?**** 0 1;
 
end;
/nfcc/trunk/rijndael/cipher/sbox.c
0,0 → 1,43
#include <stdio.h>
#include "genpat.h"
 
char *inttostr(entier)
int entier;
{
char *str;
str = (char *) mbkalloc (32 * sizeof (char));
sprintf (str, "%d",entier);
return(str);
}
/*------------------------------*/
/* end of the description */
/*------------------------------*/
 
main ()
{
int i;
int cur_vect = 0;
 
DEF_GENPAT("sbox");
SETTUNIT("ns");
 
/* interface */
DECLAR ("di" , ":2", "X", IN , "7 downto 0", "" );
DECLAR ("do" , ":2", "X", OUT, "7 downto 0", "" );
DECLAR ("vss", ":1", "B", IN , "" , "" );
DECLAR ("vdd", ":1", "B", IN , "" , "" );
 
AFFECT ("0", "vss", "0b0");
AFFECT ("0", "vdd", "0b1");
AFFECT ("0", "di", "0x00");
 
for (i=1; i<256; i++)
{
AFFECT ("+10", "di", inttostr(i) );
cur_vect++;
}
 
 
SAV_GENPAT ();
}
 
/nfcc/trunk/rijndael/cipher/c8b.c
0,0 → 1,50
#include <stdio.h>
#include "genpat.h"
 
char *inttostr(entier)
int entier;
{
char *str;
str = (char *) mbkalloc (32 * sizeof (char));
sprintf (str, "%d",entier);
return(str);
}
/*------------------------------*/
/* end of the description */
/*------------------------------*/
 
main ()
{
int i;
 
DEF_GENPAT("c8b");
SETTUNIT("ns");
 
/* interface */
DECLAR ("clk", ":1", "B", IN , "" , "" );
DECLAR ("rst", ":1", "B", IN , "" , "" );
DECLAR ("cnt", ":2", "X", OUT, "7 downto 0", "" );
DECLAR ("c8b.sum",":2","X",REGISTER,"7 downto 0","");
DECLAR ("c8b.cr" ,":2","X",SIGNAL ,"7 downto 0","");
DECLAR ("vss", ":1", "B", IN , "" , "" );
DECLAR ("vdd", ":1", "B", IN , "" , "" );
 
AFFECT ("0", "vss", "0b0");
AFFECT ("0", "vdd", "0b1");
 
AFFECT ( "0", "rst", "0b1");
AFFECT ( "0", "clk", "0b0");
AFFECT ("+10", "clk", "0b1");
AFFECT ("+10", "clk", "0b0");
AFFECT ( "+0", "rst", "0b0");
 
for (i=1; i<256; i++)
{
AFFECT ("+10", "clk", "0b1" );
AFFECT ("+10", "clk", "0b0" );
}
 
 
SAV_GENPAT ();
}
 
/nfcc/trunk/rijndael/cipher/fread.c
0,0 → 1,51
#include <stdio.h>
#include <string.h>
 
main(int argc, char *argv[])
{
FILE *f;
char *fname = "key.lst";
int c,i;
char key[60][20];
 
if (argc > 1) {
fname = argv[1]; /*
i = 1;
printf("%3d ", argc);
while (i < argc) {
printf ("-- %s ", argv[i]);
i++;
}
printf("\n"); */
}
 
if(fname && (f = fopen(fname, "rt"))) {
i = 0;
while(fgets(key[i],sizeof(key[i]),f) != NULL) {
c = strlen(key[i]);
if(key[i][c-1] == '\n') key[i][c-1] = '\0';
i++;
}
fclose (f);
} else {
fclose (f);
}
/*
if (fname && (f = fopen ( fname, "rt"))) {
printf ("Success opening %s, ", fname);
} else {
fclose (f);
}
 
i = 0;
while(fgets(key[i],sizeof(key[i]),f) != NULL){
c = strlen(key[i]);
if(key[i][c-1] == '\n') key[i][c-1] = '\0';
i++;
}
printf("got %3d lines\n", i);
*/
for (c = 0; c<i; c++) printf("%3d -- %s\n", c, key[c]);
 
fclose (f);
}
/nfcc/trunk/rijndael/cipher/c2b.vhdl
0,0 → 1,59
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity c2b is
port (
cnt : out bit_vector ( 1 downto 0);
clk : in bit;
rst : in bit
);
end c2b;
 
architecture phy of c2b is
signal sum : bit_vector ( 1 downto 0); -- sum
signal cr : bit_vector ( 1 downto 0); -- carry
begin
cr(0) <= '0'; -- LSB always zero
cr(1) <= sum(0);
process (clk)
begin
if (clk = '1' and clk'event) then
if (rst = '1') then
sum <= B"00";
else
sum <= ((sum xor B"01") xor cr); -- sum = ((addend xor augend) xor carry)
end if;
end if;
end process;
cnt <= sum;
end phy;
/nfcc/trunk/rijndael/cipher/xtime_2.vhdl
0,0 → 1,44
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity xtime_2 is
port (
x2i : in bit_vector (07 downto 00);
x2o : out bit_vector (07 downto 00)
);
end xtime_2;
 
architecture phy of xtime_2 is
begin
x2o <= ( x2i(06 downto 04) & ( x2i(03 downto 02) xor ( x2i(07) & x2i(07) ) ) & x2i(01) & ( x2i(00) xor x2i(07) ) & x2i(07) );
end phy;
/nfcc/trunk/rijndael/cipher/c4b.vhdl
0,0 → 1,59
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity c4b is
port (
cnt : out bit_vector ( 3 downto 0);
clk : in bit;
rst : in bit
);
end c4b;
 
architecture phy of c4b is
signal sum : bit_vector ( 3 downto 0); -- sum
signal cr : bit_vector ( 3 downto 0); -- carry
begin
cr(0) <= '0'; -- LSB always zero
cr(3 downto 1) <= ( ((sum(2 downto 0) and B"001") or (sum(2 downto 0) and cr(2 downto 0))) or (B"001" and cr(2 downto 0)) );
process (clk)
begin
if (clk = '1' and clk'event) then
if (rst = '1') then
sum <= B"0000";
else
sum <= ((sum xor B"0001") xor cr); -- sum = ((addend xor augend) xor carry)
end if;
end if;
end process;
cnt <= sum;
end phy;
/nfcc/trunk/rijndael/cipher/pt1.lst
0,0 → 1,4
0x00112233
0x44556677
0x8899aabb
0xccddeeff
/nfcc/trunk/rijndael/cipher/cipher128.do
0,0 → 1,54
#
 
add wave sim:/cipher/pt
add wave sim:/cipher/key
add wave sim:/cipher/ct
add wave sim:/cipher/cti
add wave sim:/cipher/v
add wave sim:/cipher/nk
add wave sim:/cipher/ldpt
add wave sim:/cipher/ldk
add wave sim:/cipher/ld
add wave sim:/cipher/ldi1
add wave sim:/cipher/ldrs
add wave sim:/cipher/clk
add wave sim:/cipher/cnt
add wave sim:/cipher/ct2b
add wave sim:/cipher/cnts
add wave sim:/cipher/rst
add wave sim:/cipher/crst
add wave sim:/cipher/rsts
add wave sim:/cipher/swp
add wave sim:/cipher/swp1
add wave sim:/cipher/wsb1
add wave sim:/cipher/wsb2
add wave sim:/cipher/wsr
add wave sim:/cipher/wmc
add wave sim:/cipher/ssm
add wave sim:/cipher/last
add wave sim:/cipher/rk
add wave sim:/cipher/int
add wave sim:/cipher/int1
add wave sim:/cipher/int2
 
force -freeze sim:/cipher/clk 1 0, 0 {50 ns} -r 100
force -freeze sim:/cipher/rst 1 0
run 100ns
force -freeze sim:/cipher/rst 0 0
force -freeze sim:/cipher/ldpt 1 0
force -freeze sim:/cipher/ldk 1 0
force -freeze sim:/cipher/nk 0100 0
force -freeze sim:/cipher/pt x"00112233" 0
force -freeze sim:/cipher/key x"00010203" 0
run 100ns
force -freeze sim:/cipher/pt x"44556677" 0
force -freeze sim:/cipher/key x"04050607" 0
run 100ns
force -freeze sim:/cipher/pt x"8899aabb" 0
force -freeze sim:/cipher/key x"08090a0b" 0
run 100ns
force -freeze sim:/cipher/pt x"ccddeeff" 0
force -freeze sim:/cipher/key x"0c0d0e0f" 0
run 100ns
force -freeze sim:/cipher/ldpt 0 0
force -freeze sim:/cipher/ldk 0 0
/nfcc/trunk/rijndael/cipher/cipher.vhdl
0,0 → 1,280
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
--
-- Cipher(byte in[4*Nb], byte out[4*Nb], word w[Nb*(Nr+1)])
-- begin
-- byte state[4,Nb]
-- state = in
--
-- AddRoundKey(state, w[0, Nb-1])
--
-- for round = 1 step 1 to Nr-1
-- SubBytes(state)
-- ShiftRows(state)
-- MixColumns(state)
-- AddRoundKey(state, w[round*Nb, (round+1)*Nb-1])
-- end for
--
-- SubBytes(state)
-- ShiftRows(state)
-- AddRoundKey(state, w[Nr*Nb, (Nr+1)*Nb-1])
--
-- out = state
-- end
--
-- Nb = Number of Block, Nr = Number of Round
-- AES-128 => Nk(4), Nb(4), Nr(10)
-- AES-192 => Nk(6), Nb(4), Nr(12)
-- AES-256 => Nk(8), Nb(4), Nr(14)
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity cipher is
port (
pt : in bit_vector ( 31 downto 0); -- plain text
key : in bit_vector ( 31 downto 0); -- source key
Nk : in bit_vector ( 3 downto 0); -- 128,192,256 => 4,6,8 (0100,0110,1000)
ldpt : in bit; -- load signal for the first 128 bit block
ct : out bit_vector ( 31 downto 0); -- cipher text
v : out bit; -- valid cipher text output
clk : in bit; -- master clock
rst : in bit -- master reset
);
end cipher;
 
architecture phy of cipher is
 
signal ireg1 : bit_vector (127 downto 0); -- 128 bit internal register 1
signal ireg2 : bit_vector (127 downto 0); -- 128 bit internal register 2
signal ct2b : bit_vector ( 1 downto 0); -- 2 bit counter
signal wsb1 : bit_vector ( 31 downto 0); -- SubBytes
signal wsb2 : bit_vector ( 31 downto 0); -- SubBytes
signal wsr : bit_vector ( 31 downto 0); -- ShiftRows
signal wmc : bit_vector ( 31 downto 0); -- MixColumns
signal ssm : bit_vector ( 31 downto 0); -- SubBytes, ShiftRows, MixColumns
signal ikey : bit_vector ( 31 downto 0); -- internal round key
signal rnd : bit_vector ( 3 downto 0); -- current round number
signal rnd_cr : bit_vector ( 3 downto 0); -- currend round number carry
signal ipt : bit_vector ( 31 downto 0); -- internal plain text
signal s1i : bit_vector ( 7 downto 0); -- Input SubBytes 1
signal s2i : bit_vector ( 7 downto 0); -- Input SubBytes 2
signal s3i : bit_vector ( 7 downto 0); -- Input SubBytes 3
signal s4i : bit_vector ( 7 downto 0); -- Input SubBytes 4
signal s1o : bit_vector ( 7 downto 0); -- Output SubBytes 1
signal s2o : bit_vector ( 7 downto 0); -- Output SubBytes 2
signal s3o : bit_vector ( 7 downto 0); -- Output SubBytes 3
signal s4o : bit_vector ( 7 downto 0); -- Output SubBytes 4
signal x2ai : bit_vector ( 7 downto 0); -- Input xtime 2 a
signal x2bi : bit_vector ( 7 downto 0); -- Input xtime 2 b
signal x2ci : bit_vector ( 7 downto 0); -- Input xtime 2 c
signal x2di : bit_vector ( 7 downto 0); -- Input xtime 2 d
signal x2ao : bit_vector ( 7 downto 0); -- Output xtime 2 a
signal x2bo : bit_vector ( 7 downto 0); -- Output xtime 2 b
signal x2co : bit_vector ( 7 downto 0); -- Output xtime 2 c
signal x2do : bit_vector ( 7 downto 0); -- Output xtime 2 d
signal ct2b_rst : bit; -- reset for internal block operation
signal swp : bit; -- swap internal register
signal swp1 : bit; -- swap internal register
signal vld : bit; -- final round
signal vld1 : bit; -- final round
signal ildpt : bit; -- internal load plain text
signal ildpt_rst : bit; -- internal load plain text reset
 
component sbox
port (
di : in bit_vector ( 7 downto 0);
do : out bit_vector ( 7 downto 0)
);
end component;
 
component c2b
port (
cnt : out bit_vector ( 1 downto 0);
clk : in bit;
rst : in bit
);
end component;
 
component xtime_2
port (
x2i : in bit_vector ( 7 downto 0);
x2o : out bit_vector ( 7 downto 0)
);
end component;
 
begin
 
sb1 : sbox
port map (
di => s1i,
do => s1o
);
sb2 : sbox
port map (
di => s2i,
do => s2o
);
sb3 : sbox
port map (
di => s3i,
do => s3o
);
sb4 : sbox
port map (
di => s4i,
do => s4o
);
ctr1 : c2b
port map (
cnt => ct2b,
clk => clk,
rst => ct2b_rst
);
x2a : xtime_2
port map (
x2i => x2ai,
x2o => x2ao
);
x2b : xtime_2
port map (
x2i => x2bi,
x2o => x2bo
);
x2c : xtime_2
port map (
x2i => x2ci,
x2o => x2co
);
x2d : xtime_2
port map (
x2i => x2di,
x2o => x2do
);
 
-- 007 039 071 103 | 007 039 071 103
-- 015 047 079 111 | 047 079 111 015
-- 023 055 087 119 | 087 119 023 055
-- 031 063 095 127 | 127 031 063 095
 
with ct2b(01 downto 00) select
wsb1 <= ireg1(127 downto 120) & ireg1( 87 downto 80) & ireg1( 47 downto 40) & ireg1( 7 downto 0) when B"00", -- 1st column
ireg1( 31 downto 24) & ireg1(119 downto 112) & ireg1( 79 downto 72) & ireg1( 39 downto 32) when B"11", -- 4th column
ireg1( 63 downto 56) & ireg1( 23 downto 16) & ireg1(111 downto 104) & ireg1( 71 downto 64) when B"10", -- 3rd column
ireg1( 95 downto 88) & ireg1( 55 downto 48) & ireg1( 15 downto 8) & ireg1(103 downto 96) when B"01"; -- 2nd column
with ct2b(01 downto 00) select
wsb2 <= ireg2(127 downto 120) & ireg2( 87 downto 80) & ireg2( 47 downto 40) & ireg2( 7 downto 0) when B"00", -- 1st column
ireg2( 31 downto 24) & ireg2(119 downto 112) & ireg2( 79 downto 72) & ireg2( 39 downto 32) when B"11", -- 4th column
ireg2( 63 downto 56) & ireg2( 23 downto 16) & ireg2(111 downto 104) & ireg2( 71 downto 64) when B"10", -- 3rd column
ireg2( 95 downto 88) & ireg2( 55 downto 48) & ireg2( 15 downto 8) & ireg2(103 downto 96) when B"01"; -- 2nd column
--SubBytes
s1i(07 downto 00)<= wsb1(31 downto 24) when swp = '1' else wsb2(31 downto 24);
s2i(07 downto 00)<= wsb1(23 downto 16) when swp = '1' else wsb2(23 downto 16);
s3i(07 downto 00)<= wsb1(15 downto 08) when swp = '1' else wsb2(15 downto 08);
s4i(07 downto 00)<= wsb1(07 downto 00) when swp = '1' else wsb2(07 downto 00);
 
--ShiftRows
wsr <= s1o & s2o & s3o & s4o;
 
--MixColumns
x2ai <= wsr(31 downto 24);
x2bi <= wsr(23 downto 16);
x2ci <= wsr(15 downto 08);
x2di <= wsr(07 downto 00);
 
wmc(31 downto 24)<= x2ao xor x2bo xor x2bi xor x2ci xor x2di;
wmc(23 downto 16)<= x2ai xor x2bo xor x2co xor x2ci xor x2di;
wmc(15 downto 08)<= x2ai xor x2bi xor x2co xor x2do xor x2di;
wmc(07 downto 00)<= x2ao xor x2ai xor x2bi xor x2ci xor x2do;
 
process (clk)
begin
if ((clk = '1') and clk'event) then
ildpt <= ldpt;
end if;
end process;
ildpt_rst <= ((ildpt xor ldpt) and ldpt);
ct2b_rst <= rst or ildpt_rst;
 
rnd_cr(0) <= '0'; -- LSB always zero
rnd_cr(3 downto 1) <= ( ((rnd(2 downto 0) and B"001") or (rnd(2 downto 0) and rnd_cr(2 downto 0))) or (B"001" and rnd_cr(2 downto 0)) );
 
process (clk)
begin
if ((clk = '1') and clk'event) then
if ((ildpt_rst or rst) = '1') then
swp <= '0';
rnd <= B"0000";
elsif (not(not(ct2b(1)) or not(ct2b(0))) = '1') then
swp <= not(swp);
rnd <= ((rnd xor B"0001") xor rnd_cr);
end if;
end if;
end process;
 
vld <= (not(Nk(3) or not(Nk(2)) or Nk(1) or Nk(0)) and not(not(rnd(3)) or rnd(2) or not(rnd(1)) or rnd(0))) or -- Nk 0100 (10 round)
(not(Nk(3) or not(Nk(2)) or not(Nk(1)) or Nk(0)) and not(not(rnd(3)) or not(rnd(2)) or rnd(1) or rnd(0))) or -- Nk 0110 (12 round)
(not(not(Nk(3)) or Nk(2) or Nk(1) or Nk(0)) and not(not(rnd(3)) or not(rnd(2)) or not(rnd(1)) or rnd(0))); -- Nk 1000 (14 round)
 
ssm <= wmc when vld = '0' else wsr;
ikey <= key;
 
process (clk)
begin
if ((clk = '1') and clk'event) then
if (rst = '1') then
ireg1(127 downto 00) <= (others => '0');
ireg2(127 downto 00) <= (others => '0');
elsif (ildpt = '1') then
ireg1(127 downto 00) <= ireg1(095 downto 00) & (ipt xor ikey); -- initial round
elsif ( swp = '0') then
ireg1(127 downto 00) <= ireg1(095 downto 00) & (ssm xor ikey);
else
ireg2(127 downto 00) <= ireg2(095 downto 00) & (ssm xor ikey);
end if;
end if;
end process;
 
process (clk)
begin
if ((clk = '1') and clk'event) then
swp1 <= swp;
vld1 <= vld;
ipt <= pt;
end if;
end process;
 
ct <= ireg1(31 downto 00) when swp1 = '0' else ireg2(31 downto 00);
v <= vld1;
 
end phy;
/nfcc/trunk/rijndael/cipher/c6b.vhdl
0,0 → 1,59
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity c6b is
port (
cnt : out bit_vector ( 5 downto 0);
clk : in bit;
rst : in bit
);
end c6b;
 
architecture phy of c6b is
signal sum : bit_vector ( 5 downto 0); -- sum
signal cr : bit_vector ( 5 downto 0); -- carry
begin
cr(0) <= '0'; -- LSB always zero
cr(5 downto 1) <= ( ((sum(4 downto 0) and B"00001") or (sum(4 downto 0) and cr(4 downto 0))) or (B"00001" and cr(4 downto 0)) );
process (clk)
begin
if (clk = '1' and clk'event) then
if (rst = '1') then
sum <= B"000000";
else
sum <= ((sum xor B"000001") xor cr); -- sum = ((addend xor augend) xor carry)
end if;
end if;
end process;
cnt <= sum;
end phy;
/nfcc/trunk/rijndael/cipher/pt2.lst
0,0 → 1,4
0x00112233
0x44556677
0x8899aabb
0xccddeeff
/nfcc/trunk/rijndael/cipher/cipher192.do
0,0 → 1,58
#
 
add wave sim:/cipher/pt
add wave sim:/cipher/key
add wave sim:/cipher/ct
add wave sim:/cipher/cti
add wave sim:/cipher/v
add wave sim:/cipher/nk
add wave sim:/cipher/ldpt
add wave sim:/cipher/ldk
add wave sim:/cipher/ld
add wave sim:/cipher/ldi1
add wave sim:/cipher/ldrs
add wave sim:/cipher/clk
add wave sim:/cipher/cnt
add wave sim:/cipher/ct2b
add wave sim:/cipher/cnts
add wave sim:/cipher/rst
add wave sim:/cipher/crst
add wave sim:/cipher/rsts
add wave sim:/cipher/swp
add wave sim:/cipher/swp1
add wave sim:/cipher/wsb1
add wave sim:/cipher/wsb2
add wave sim:/cipher/wsr
add wave sim:/cipher/wmc
add wave sim:/cipher/ssm
add wave sim:/cipher/last
add wave sim:/cipher/rk
add wave sim:/cipher/int
add wave sim:/cipher/int1
add wave sim:/cipher/int2
 
force -freeze sim:/cipher/clk 1 0, 0 {50 ns} -r 100
force -freeze sim:/cipher/rst 1 0
run 100ns
force -freeze sim:/cipher/rst 0 0
force -freeze sim:/cipher/ldpt 1 0
force -freeze sim:/cipher/ldk 1 0
force -freeze sim:/cipher/nk 0110 0
force -freeze sim:/cipher/pt x"00112233" 0
force -freeze sim:/cipher/key x"00010203" 0
run 100ns
force -freeze sim:/cipher/pt x"44556677" 0
force -freeze sim:/cipher/key x"04050607" 0
run 100ns
force -freeze sim:/cipher/pt x"8899aabb" 0
force -freeze sim:/cipher/key x"08090a0b" 0
run 100ns
force -freeze sim:/cipher/pt x"ccddeeff" 0
force -freeze sim:/cipher/key x"0c0d0e0f" 0
run 100ns
force -freeze sim:/cipher/ldpt 0 0
force -freeze sim:/cipher/key x"10111213" 0
run 100ns
force -freeze sim:/cipher/key x"14151617" 0
run 100ns
force -freeze sim:/cipher/ldk 0 0
/nfcc/trunk/rijndael/cipher/pt3.lst
0,0 → 1,4
0x00112233
0x44556677
0x8899aabb
0xccddeeff
/nfcc/trunk/rijndael/cipher/sbox.vhdl
0,0 → 1,128
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity sbox is
port (
di : in bit_vector (07 downto 00);
do : out bit_vector (07 downto 00)
);
end sbox;
 
architecture phy of sbox is
begin
with di(07 downto 00) select
do <=
-- start sbox
X"63" when X"00", X"7c" when X"01", X"77" when X"02", X"7b" when X"03",
X"f2" when X"04", X"6b" when X"05", X"6f" when X"06", X"c5" when X"07",
X"30" when X"08", X"01" when X"09", X"67" when X"0a", X"2b" when X"0b",
X"fe" when X"0c", X"d7" when X"0d", X"ab" when X"0e", X"76" when X"0f",
 
X"ca" when X"10", X"82" when X"11", X"c9" when X"12", X"7d" when X"13",
X"fa" when X"14", X"59" when X"15", X"47" when X"16", X"f0" when X"17",
X"ad" when X"18", X"d4" when X"19", X"a2" when X"1a", X"af" when X"1b",
X"9c" when X"1c", X"a4" when X"1d", X"72" when X"1e", X"c0" when X"1f",
 
X"b7" when X"20", X"fd" when X"21", X"93" when X"22", X"26" when X"23",
X"36" when X"24", X"3f" when X"25", X"f7" when X"26", X"cc" when X"27",
X"34" when X"28", X"a5" when X"29", X"e5" when X"2a", X"f1" when X"2b",
X"71" when X"2c", X"d8" when X"2d", X"31" when X"2e", X"15" when X"2f",
 
X"04" when X"30", X"c7" when X"31", X"23" when X"32", X"c3" when X"33",
X"18" when X"34", X"96" when X"35", X"05" when X"36", X"9a" when X"37",
X"07" when X"38", X"12" when X"39", X"80" when X"3a", X"e2" when X"3b",
X"eb" when X"3c", X"27" when X"3d", X"b2" when X"3e", X"75" when X"3f",
 
X"09" when X"40", X"83" when X"41", X"2c" when X"42", X"1a" when X"43",
X"1b" when X"44", X"6e" when X"45", X"5a" when X"46", X"a0" when X"47",
X"52" when X"48", X"3b" when X"49", X"d6" when X"4a", X"b3" when X"4b",
X"29" when X"4c", X"e3" when X"4d", X"2f" when X"4e", X"84" when X"4f",
 
X"53" when X"50", X"d1" when X"51", X"00" when X"52", X"ed" when X"53",
X"20" when X"54", X"fc" when X"55", X"b1" when X"56", X"5b" when X"57",
X"6a" when X"58", X"cb" when X"59", X"be" when X"5a", X"39" when X"5b",
X"4a" when X"5c", X"4c" when X"5d", X"58" when X"5e", X"cf" when X"5f",
 
X"d0" when X"60", X"ef" when X"61", X"aa" when X"62", X"fb" when X"63",
X"43" when X"64", X"4d" when X"65", X"33" when X"66", X"85" when X"67",
X"45" when X"68", X"f9" when X"69", X"02" when X"6a", X"7f" when X"6b",
X"50" when X"6c", X"3c" when X"6d", X"9f" when X"6e", X"a8" when X"6f",
 
X"51" when X"70", X"a3" when X"71", X"40" when X"72", X"8f" when X"73",
X"92" when X"74", X"9d" when X"75", X"38" when X"76", X"f5" when X"77",
X"bc" when X"78", X"b6" when X"79", X"da" when X"7a", X"21" when X"7b",
X"10" when X"7c", X"ff" when X"7d", X"f3" when X"7e", X"d2" when X"7f",
 
X"cd" when X"80", X"0c" when X"81", X"13" when X"82", X"ec" when X"83",
X"5f" when X"84", X"97" when X"85", X"44" when X"86", X"17" when X"87",
X"c4" when X"88", X"a7" when X"89", X"7e" when X"8a", X"3d" when X"8b",
X"64" when X"8c", X"5d" when X"8d", X"19" when X"8e", X"73" when X"8f",
 
X"60" when X"90", X"81" when X"91", X"4f" when X"92", X"dc" when X"93",
X"22" when X"94", X"2a" when X"95", X"90" when X"96", X"88" when X"97",
X"46" when X"98", X"ee" when X"99", X"b8" when X"9a", X"14" when X"9b",
X"de" when X"9c", X"5e" when X"9d", X"0b" when X"9e", X"db" when X"9f",
 
X"e0" when X"a0", X"32" when X"a1", X"3a" when X"a2", X"0a" when X"a3",
X"49" when X"a4", X"06" when X"a5", X"24" when X"a6", X"5c" when X"a7",
X"c2" when X"a8", X"d3" when X"a9", X"ac" when X"aa", X"62" when X"ab",
X"91" when X"ac", X"95" when X"ad", X"e4" when X"ae", X"79" when X"af",
 
X"e7" when X"b0", X"c8" when X"b1", X"37" when X"b2", X"6d" when X"b3",
X"8d" when X"b4", X"d5" when X"b5", X"4e" when X"b6", X"a9" when X"b7",
X"6c" when X"b8", X"56" when X"b9", X"f4" when X"ba", X"ea" when X"bb",
X"65" when X"bc", X"7a" when X"bd", X"ae" when X"be", X"08" when X"bf",
 
X"ba" when X"c0", X"78" when X"c1", X"25" when X"c2", X"2e" when X"c3",
X"1c" when X"c4", X"a6" when X"c5", X"b4" when X"c6", X"c6" when X"c7",
X"e8" when X"c8", X"dd" when X"c9", X"74" when X"ca", X"1f" when X"cb",
X"4b" when X"cc", X"bd" when X"cd", X"8b" when X"ce", X"8a" when X"cf",
 
X"70" when X"d0", X"3e" when X"d1", X"b5" when X"d2", X"66" when X"d3",
X"48" when X"d4", X"03" when X"d5", X"f6" when X"d6", X"0e" when X"d7",
X"61" when X"d8", X"35" when X"d9", X"57" when X"da", X"b9" when X"db",
X"86" when X"dc", X"c1" when X"dd", X"1d" when X"de", X"9e" when X"df",
 
X"e1" when X"e0", X"f8" when X"e1", X"98" when X"e2", X"11" when X"e3",
X"69" when X"e4", X"d9" when X"e5", X"8e" when X"e6", X"94" when X"e7",
X"9b" when X"e8", X"1e" when X"e9", X"87" when X"ea", X"e9" when X"eb",
X"ce" when X"ec", X"55" when X"ed", X"28" when X"ee", X"df" when X"ef",
 
X"8c" when X"f0", X"a1" when X"f1", X"89" when X"f2", X"0d" when X"f3",
X"bf" when X"f4", X"e6" when X"f5", X"42" when X"f6", X"68" when X"f7",
X"41" when X"f8", X"99" when X"f9", X"2d" when X"fa", X"0f" when X"fb",
X"b0" when X"fc", X"54" when X"fd", X"bb" when X"fe", X"16" when X"ff",
 
-- end sbox
X"00" when others;
end phy;
/nfcc/trunk/rijndael/cipher/cipher256.do
0,0 → 1,62
#
 
add wave sim:/cipher/pt
add wave sim:/cipher/key
add wave sim:/cipher/ct
add wave sim:/cipher/cti
add wave sim:/cipher/v
add wave sim:/cipher/nk
add wave sim:/cipher/ldpt
add wave sim:/cipher/ldk
add wave sim:/cipher/ld
add wave sim:/cipher/ldi1
add wave sim:/cipher/ldrs
add wave sim:/cipher/clk
add wave sim:/cipher/cnt
add wave sim:/cipher/ct2b
add wave sim:/cipher/cnts
add wave sim:/cipher/rst
add wave sim:/cipher/crst
add wave sim:/cipher/rsts
add wave sim:/cipher/swp
add wave sim:/cipher/swp1
add wave sim:/cipher/wsb1
add wave sim:/cipher/wsb2
add wave sim:/cipher/wsr
add wave sim:/cipher/wmc
add wave sim:/cipher/ssm
add wave sim:/cipher/last
add wave sim:/cipher/rk
add wave sim:/cipher/int
add wave sim:/cipher/int1
add wave sim:/cipher/int2
 
force -freeze sim:/cipher/clk 1 0, 0 {50 ns} -r 100
force -freeze sim:/cipher/rst 1 0
run 100ns
force -freeze sim:/cipher/rst 0 0
force -freeze sim:/cipher/ldpt 1 0
force -freeze sim:/cipher/ldk 1 0
force -freeze sim:/cipher/nk 1000 0
force -freeze sim:/cipher/pt x"00112233" 0
force -freeze sim:/cipher/key x"00010203" 0
run 100ns
force -freeze sim:/cipher/pt x"44556677" 0
force -freeze sim:/cipher/key x"04050607" 0
run 100ns
force -freeze sim:/cipher/pt x"8899aabb" 0
force -freeze sim:/cipher/key x"08090a0b" 0
run 100ns
force -freeze sim:/cipher/pt x"ccddeeff" 0
force -freeze sim:/cipher/key x"0c0d0e0f" 0
run 100ns
force -freeze sim:/cipher/ldpt 0 0
force -freeze sim:/cipher/key x"10111213" 0
run 100ns
force -freeze sim:/cipher/key x"14151617" 0
run 100ns
force -freeze sim:/cipher/key x"18191a1b" 0
run 100ns
force -freeze sim:/cipher/key x"1c1d1e1f" 0
run 100ns
force -freeze sim:/cipher/ldk 0 0
/nfcc/trunk/rijndael/cipher/c8b.vhdl
0,0 → 1,59
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity c6b is
port (
cnt : out bit_vector ( 7 downto 0);
clk : in bit;
rst : in bit
);
end c6b;
 
architecture phy of c6b is
signal sum : bit_vector ( 7 downto 0); -- sum
signal cr : bit_vector ( 7 downto 0); -- carry
begin
cr(0) <= '0'; -- LSB always zero
cr(7 downto 1) <= ( ((sum(6 downto 0) and B"0000001") or (sum(6 downto 0) and cr(6 downto 0))) or (B"0000001" and cr(6 downto 0)) );
process (clk)
begin
if (clk = '1' and clk'event) then
if (rst = '1') then
sum <= B"00000000";
else
sum <= ((sum xor B"00000001") xor cr); -- sum = ((addend xor augend) xor carry)
end if;
end if;
end process;
cnt <= sum;
end phy;
/nfcc/trunk/rijndael/cipher/key.c
0,0 → 1,69
#include <stdio.h>
#include "genpat.h"
 
char *inttostr(entier)
int entier;
{
char *str;
str = (char *) mbkalloc (32 * sizeof (char));
sprintf (str, "%d",entier);
return(str);
}
/*------------------------------*/
/* end of the description */
/*------------------------------*/
 
main ()
{
int i;
int cur_vect = 0;
 
DEF_GENPAT("key");
SETTUNIT("ns");
 
/* interface */
DECLAR ("st" , ":2", "X", IN , " 7 downto 0", "" );
DECLAR ("Nk" , ":2", "X", IN , " 3 downto 0", "" );
DECLAR ("key", ":2", "X", OUT, "31 downto 0", "" );
DECLAR ("vss", ":1", "B", IN , "" , "" );
DECLAR ("vdd", ":1", "B", IN , "" , "" );
 
AFFECT ("0", "vss", "0b0");
AFFECT ("0", "vdd", "0b1");
 
AFFECT ( "0", "Nk", "0x4");
AFFECT ( "0", "st", "0x0");
AFFECT ("+10", "st", "0x0");
 
for (i=1; i<60; i++)
{
AFFECT ("+10", "st", inttostr(i) );
AFFECT ("+10", "st", inttostr(i) );
cur_vect++;
}
 
AFFECT ("+10", "Nk", "0x6");
AFFECT ("+10", "st", "0x0");
AFFECT ("+20", "st", "0x0");
 
for (i=1; i<60; i++)
{
AFFECT ("+10", "st", inttostr(i) );
AFFECT ("+10", "st", inttostr(i) );
cur_vect++;
}
 
AFFECT ("+10", "Nk", "0x8");
AFFECT ("+10", "st", "0x0");
AFFECT ("+20", "st", "0x0");
 
for (i=1; i<60; i++)
{
AFFECT ("+10", "st", inttostr(i) );
AFFECT ("+10", "st", inttostr(i) );
cur_vect++;
}
 
SAV_GENPAT ();
}
 
/nfcc/trunk/rijndael/cipher/key1.lst
0,0 → 1,44
0x00010203
0x04050607
0x08090a0b
0x0c0d0e0f
0xd6aa74fd
0xd2af72fa
0xdaa678f1
0xd6ab76fe
0xb692cf0b
0x643dbdf1
0xbe9bc500
0x6830b3fe
0xb6ff744e
0xd2c2c9bf
0x6c590cbf
0x0469bf41
0x47f7f7bc
0x95353e03
0xf96c32bc
0xfd058dfd
0x3caaa3e8
0xa99f9deb
0x50f3af57
0xadf622aa
0x5e390f7d
0xf7a69296
0xa7553dc1
0x0aa31f6b
0x14f9701a
0xe35fe28c
0x440adf4d
0x4ea9c026
0x47438735
0xa41c65b9
0xe016baf4
0xaebf7ad2
0x549932d1
0xf0855768
0x1093ed9c
0xbe2c974e
0x13111d7f
0xe3944a17
0xf307a78b
0x4d2b30c5
/nfcc/trunk/rijndael/cipher/cipher.do
0,0 → 1,54
#
 
add wave sim:/cipher/pt
add wave sim:/cipher/key
add wave sim:/cipher/ct
add wave sim:/cipher/cti
add wave sim:/cipher/v
add wave sim:/cipher/nk
add wave sim:/cipher/ldpt
add wave sim:/cipher/ldk
add wave sim:/cipher/ld
add wave sim:/cipher/ldi1
add wave sim:/cipher/ldrs
add wave sim:/cipher/clk
add wave sim:/cipher/cnt
add wave sim:/cipher/ct2b
add wave sim:/cipher/cnts
add wave sim:/cipher/rst
add wave sim:/cipher/crst
add wave sim:/cipher/rsts
add wave sim:/cipher/swp
add wave sim:/cipher/swp1
add wave sim:/cipher/wsb1
add wave sim:/cipher/wsb2
add wave sim:/cipher/wsr
add wave sim:/cipher/wmc
add wave sim:/cipher/ssm
add wave sim:/cipher/last
add wave sim:/cipher/rk
add wave sim:/cipher/int
add wave sim:/cipher/int1
add wave sim:/cipher/int2
 
force -freeze sim:/cipher/clk 1 0, 0 {50 ns} -r 100
force -freeze sim:/cipher/rst 1 0
run 100ns
force -freeze sim:/cipher/rst 0 0
force -freeze sim:/cipher/ldpt 1 0
force -freeze sim:/cipher/ldk 1 0
force -freeze sim:/cipher/nk 0100 0
force -freeze sim:/cipher/pt x"3243f6a8" 0
force -freeze sim:/cipher/key x"2b7e1516" 0
run 100ns
force -freeze sim:/cipher/pt x"885a308d" 0
force -freeze sim:/cipher/key x"28aed2a6" 0
run 100ns
force -freeze sim:/cipher/pt x"313198a2" 0
force -freeze sim:/cipher/key x"abf71588" 0
run 100ns
force -freeze sim:/cipher/pt x"e0370734" 0
force -freeze sim:/cipher/key x"09cf4f3c" 0
run 100ns
force -freeze sim:/cipher/ldpt 0 0
force -freeze sim:/cipher/ldk 0 0
/nfcc/trunk/rijndael/cipher/key2.lst
0,0 → 1,52
0x00010203
0x04050607
0x08090a0b
0x0c0d0e0f
0x10111213
0x14151617
0x5846f2f9
0x5c43f4fe
0x544afef5
0x5847f0fa
0x4856e2e9
0x5c43f4fe
0x40f949b3
0x1cbabd4d
0x48f043b8
0x10b7b342
0x58e151ab
0x04a2a555
0x7effb541
0x6245080c
0x2ab54bb4
0x3a02f8f6
0x62e3a95d
0x66410c08
0xf5018572
0x97448d7e
0xbdf1c6ca
0x87f33e3c
0xe5109761
0x83519b69
0x34157c9e
0xa351f1e0
0x1ea0372a
0x99530916
0x7c439e77
0xff12051e
0xdd7e0e88
0x7e2fff68
0x608fc842
0xf9dcc154
0x859f5f23
0x7a8d5a3d
0xc0c02952
0xbeefd63a
0xde601e78
0x27bcdf2c
0xa223800f
0xd8aeda32
0xa4970a33
0x1a78dc09
0xc418c271
0xe3a41d5d
/nfcc/trunk/rijndael/cipher/key3.lst
0,0 → 1,60
0x00010203
0x04050607
0x08090a0b
0x0c0d0e0f
0x10111213
0x14151617
0x18191a1b
0x1c1d1e1f
0xa573c29f
0xa176c498
0xa97fce93
0xa572c09c
0x1651a8cd
0x0244beda
0x1a5da4c1
0x0640bade
0xae87dff0
0x0ff11b68
0xa68ed5fb
0x03fc1567
0x6de1f148
0x6fa54f92
0x75f8eb53
0x73b8518d
0xc656827f
0xc9a79917
0x6f294cec
0x6cd5598b
0x3de23a75
0x524775e7
0x27bf9eb4
0x5407cf39
0x0bdc905f
0xc27b0948
0xad5245a4
0xc1871c2f
0x45f5a660
0x17b2d387
0x300d4d33
0x640a820a
0x7ccff71c
0xbeb4fe54
0x13e6bbf0
0xd261a7df
0xf01afafe
0xe7a82979
0xd7a5644a
0xb3afe640
0x2541fe71
0x9bf50025
0x8813bbd5
0x5a721c0a
0x4e5a6699
0xa9f24fe0
0x7e572baa
0xcdf8cdea
0x24fc79cc
0xbf0979e9
0x371ac23c
0x6d68de36
/nfcc/trunk/rijndael/cipher/Makefile
0,0 → 1,119
#- ------------------------------------------------------------------------
#- Copyright (C) 2010 Arif Endro Nugroho
#- All rights reserved.
#-
#- Redistribution and use in source and binary forms, with or without
#- modification, are permitted provided that the following conditions
#- are met:
#-
#- 1. Redistributions of source code must retain the above copyright
#- notice, this list of conditions and the following disclaimer.
#- 2. Redistributions in binary form must reproduce the above copyright
#- notice, this list of conditions and the following disclaimer in the
#- documentation and/or other materials provided with the distribution.
#-
#- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
#- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
#- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
#- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
#- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
#- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
#- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
#- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
#- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
#- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
#- POSSIBILITY OF SUCH DAMAGE.
#-
#- End Of License.
#- ------------------------------------------------------------------------
#
# Need to FLATTENING the design before OCP and NERO
# Use x2y vst vst <source> <result>
# then flatlo -r <source> <result> # source is a result from x2y
# this two sequence will remove most warning/error message when
# performing LOON on the netlist.
#
# BOOM will optimize the logic
# BOOG will optimize/convert the logic into netlist
# LOON will optimize the netlist (this will report area/timing)
#
# VST is a circuit netlist file
# AP is a circuit placement file (OCP/NERO create this file)
# VBE is alliance VHDL Behavioral Description file
 
VASYFLAGS = -V -B -I vhdl -a -p -o
BOOMFLAGS = -VP
BOOGFLAGS =
LOONFLAGS =
OCPFLAGS = -v
NEROFLAGS = -V -G -6 -p
DRUCFLAGS =
S2RFLAGS = -v
OCP = ocp
NERO = nero
DRUC = druc
S2R = s2r
VASY = vasy
BOOM = boom
GENPAT = genpat -v
BOOG = boog
LOON = loon
RM = /bin/rm -vf
X2Y = x2y
FLATLO = flatlo
X2YFLAGS = vst vst
FLATLOFLAGS = -r
TOUCH = touch
 
# Set-up TARGET variable respectively
%.ap: TARGET = $(subst .ap,, $@)
%.pat: TARGET = $(subst .pat,, $@)
%.cif: TARGET = $(subst .cif,, $@)
%.vst: TARGET = $(subst .vst,, $@)
%.flt: TARGET = $(subst .flt,, $@)
%.sflt: TARGET = $(subst .sflt,, $@)
%.flatten: TARGET = $(subst .flatten,, $@)
 
all:
 
%.vbe: %.vhdl
@$(VASY) $(VASYFLAGS) $<
 
%.vst: %.vbe
@$(BOOM) $(BOOMFLAGS) $(TARGET) $(TARGET)_o
@$(BOOG) $(BOOGFLAGS) $(TARGET)_o
@$(LOON) $(LOONFLAGS) $(TARGET)_o $(TARGET)
-$(RM) $(TARGET)_o.*
 
%.sflt: %.vbe
# @$(BOOM) $(BOOMFLAGS) $(TARGET)_model $(TARGET)_model_o
@$(BOOG) $(BOOGFLAGS) $(TARGET)_model
# @$(BOOG) $(BOOGFLAGS) $(TARGET)_model_o
# @$(LOON) $(LOONFLAGS) $(TARGET)_model_o $(TARGET)_model
-$(RM) $(TARGET)_model_o.*
@$(X2Y) $(X2YFLAGS) $(TARGET) $(TARGET)_m
@$(FLATLO) $(FLATLOFLAGS) $(TARGET)_m $(TARGET)
# @$(FLATLO) $(FLATLOFLAGS) $(TARGET)_m $(TARGET)_o
# @$(LOON) $(LOONFLAGS) $(TARGET)_o $(TARGET)
-$(RM) $(TARGET){_o,m}.*
@$(TOUCH) $@
 
%.flt: %.vbe
@$(BOOM) $(BOOMFLAGS) $(TARGET)_model $(TARGET)_model_o
@$(BOOG) $(BOOGFLAGS) $(TARGET)_model_o
@$(LOON) $(LOONFLAGS) $(TARGET)_model_o $(TARGET)_model
-$(RM) $(TARGET)_model_o.*
@$(X2Y) $(X2YFLAGS) $(TARGET) $(TARGET)_m
@$(FLATLO) $(FLATLOFLAGS) $(TARGET)_m $(TARGET)_o
@$(LOON) $(LOONFLAGS) $(TARGET)_o $(TARGET)
-$(RM) $(TARGET){_o,m}.*
@$(TOUCH) $@
 
%.flatten: %.vst
@$(X2Y) $(X2YFLAGS) $(TARGET) $(TARGET)_m
@$(FLATLO) $(FLATLOFLAGS) $(TARGET)_m $(TARGET)_o
@$(LOON) $(LOONFLAGS) $(TARGET)_o $(TARGET)
-$(RM) $(TARGET){_o,m}.*
 
clean:
@rm -vf *.dat *.gpl *.vhd *.vbe *.boom *.vst *.xsc *.ap *.cif *.drc done.* *.flt
/nfcc/trunk/rijndael/keyexpansion/keyexpansion.pat
0,0 → 1,139
 
in clk B;;
in rst B;;
in ld B;;
in key(31 downto 0) X;;
in Nk(3 downto 0) X;;
out w(31 downto 0) X;;
out v B;;
in vss B;;
in vdd B;;
 
begin
 
< 0ns>: 0 1 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 1 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 1 2b7e1516 4 ?******** ?* 0 1;
<+100ns>: 1 0 1 2b7e1516 4 ?******** ?* 0 1;
<+100ns>: 0 0 1 28aed2a6 4 ?******** ?* 0 1;
<+100ns>: 1 0 1 28aed2a6 4 ?******** ?* 0 1;
<+100ns>: 0 0 1 abf71588 4 ?******** ?* 0 1;
<+100ns>: 1 0 1 abf71588 4 ?******** ?* 0 1;
<+100ns>: 0 0 1 09cf4f3c 4 ?******** ?* 0 1;
<+100ns>: 1 0 1 09cf4f3c 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 0 0 0 00000000 4 ?******** ?* 0 1;
<+100ns>: 1 0 0 00000000 4 ?******** ?* 0 1;
 
end;
/nfcc/trunk/rijndael/keyexpansion/c4b.vhdl
0,0 → 1,59
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity c4b is
port (
cnt : out bit_vector (03 downto 00);
clk : in bit;
rst : in bit
);
end c4b;
 
architecture phy of c4b is
signal sum : bit_vector (03 downto 00) := B"1111"; -- sum
signal cr : bit_vector (03 downto 00) := B"0000"; -- carry
begin
cr(0) <= '0'; -- LSB always zero
cr(03 downto 01) <= ( ((sum(02 downto 00) and B"001") or (sum(02 downto 00) and cr(02 downto 00))) or (B"001" and cr(02 downto 00)) );
process (clk)
begin
if (clk = '1' and clk'event) then
if (rst = '1') then
sum <= B"0001"; -- we start counting from 1
else
sum <= ((sum xor B"0001") xor cr); -- sum = ((addend xor augend) xor carry)
end if;
end if;
end process;
cnt <= sum;
end phy;
/nfcc/trunk/rijndael/keyexpansion/c6b.vhdl
0,0 → 1,59
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity c6b is
port (
cnt : out bit_vector (05 downto 00);
clk : in bit;
rst : in bit
);
end c6b;
 
architecture phy of c6b is
signal sum : bit_vector (05 downto 00) := B"111111"; -- sum
signal cr : bit_vector (05 downto 00) := B"000000"; -- carry
begin
cr(0) <= '0'; -- LSB always zero
cr(05 downto 01) <= ( ((sum(04 downto 00) and B"00001") or (sum(04 downto 00) and cr(04 downto 00))) or (B"00001" and cr(04 downto 00)) );
process (clk)
begin
if (clk = '1' and clk'event) then
if (rst = '1') then
sum <= B"000001"; -- we start counting from 1
else
sum <= ((sum xor B"000001") xor cr); -- sum = ((addend xor augend) xor carry)
end if;
end if;
end process;
cnt <= sum;
end phy;
/nfcc/trunk/rijndael/keyexpansion/sbox.vhdl
0,0 → 1,128
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity sbox is
port (
di : in bit_vector (07 downto 00);
do : out bit_vector (07 downto 00)
);
end sbox;
 
architecture phy of sbox is
begin
with di(07 downto 00) select
do <=
-- start sbox
X"63" when X"00", X"7c" when X"01", X"77" when X"02", X"7b" when X"03",
X"f2" when X"04", X"6b" when X"05", X"6f" when X"06", X"c5" when X"07",
X"30" when X"08", X"01" when X"09", X"67" when X"0a", X"2b" when X"0b",
X"fe" when X"0c", X"d7" when X"0d", X"ab" when X"0e", X"76" when X"0f",
 
X"ca" when X"10", X"82" when X"11", X"c9" when X"12", X"7d" when X"13",
X"fa" when X"14", X"59" when X"15", X"47" when X"16", X"f0" when X"17",
X"ad" when X"18", X"d4" when X"19", X"a2" when X"1a", X"af" when X"1b",
X"9c" when X"1c", X"a4" when X"1d", X"72" when X"1e", X"c0" when X"1f",
 
X"b7" when X"20", X"fd" when X"21", X"93" when X"22", X"26" when X"23",
X"36" when X"24", X"3f" when X"25", X"f7" when X"26", X"cc" when X"27",
X"34" when X"28", X"a5" when X"29", X"e5" when X"2a", X"f1" when X"2b",
X"71" when X"2c", X"d8" when X"2d", X"31" when X"2e", X"15" when X"2f",
 
X"04" when X"30", X"c7" when X"31", X"23" when X"32", X"c3" when X"33",
X"18" when X"34", X"96" when X"35", X"05" when X"36", X"9a" when X"37",
X"07" when X"38", X"12" when X"39", X"80" when X"3a", X"e2" when X"3b",
X"eb" when X"3c", X"27" when X"3d", X"b2" when X"3e", X"75" when X"3f",
 
X"09" when X"40", X"83" when X"41", X"2c" when X"42", X"1a" when X"43",
X"1b" when X"44", X"6e" when X"45", X"5a" when X"46", X"a0" when X"47",
X"52" when X"48", X"3b" when X"49", X"d6" when X"4a", X"b3" when X"4b",
X"29" when X"4c", X"e3" when X"4d", X"2f" when X"4e", X"84" when X"4f",
 
X"53" when X"50", X"d1" when X"51", X"00" when X"52", X"ed" when X"53",
X"20" when X"54", X"fc" when X"55", X"b1" when X"56", X"5b" when X"57",
X"6a" when X"58", X"cb" when X"59", X"be" when X"5a", X"39" when X"5b",
X"4a" when X"5c", X"4c" when X"5d", X"58" when X"5e", X"cf" when X"5f",
 
X"d0" when X"60", X"ef" when X"61", X"aa" when X"62", X"fb" when X"63",
X"43" when X"64", X"4d" when X"65", X"33" when X"66", X"85" when X"67",
X"45" when X"68", X"f9" when X"69", X"02" when X"6a", X"7f" when X"6b",
X"50" when X"6c", X"3c" when X"6d", X"9f" when X"6e", X"a8" when X"6f",
 
X"51" when X"70", X"a3" when X"71", X"40" when X"72", X"8f" when X"73",
X"92" when X"74", X"9d" when X"75", X"38" when X"76", X"f5" when X"77",
X"bc" when X"78", X"b6" when X"79", X"da" when X"7a", X"21" when X"7b",
X"10" when X"7c", X"ff" when X"7d", X"f3" when X"7e", X"d2" when X"7f",
 
X"cd" when X"80", X"0c" when X"81", X"13" when X"82", X"ec" when X"83",
X"5f" when X"84", X"97" when X"85", X"44" when X"86", X"17" when X"87",
X"c4" when X"88", X"a7" when X"89", X"7e" when X"8a", X"3d" when X"8b",
X"64" when X"8c", X"5d" when X"8d", X"19" when X"8e", X"73" when X"8f",
 
X"60" when X"90", X"81" when X"91", X"4f" when X"92", X"dc" when X"93",
X"22" when X"94", X"2a" when X"95", X"90" when X"96", X"88" when X"97",
X"46" when X"98", X"ee" when X"99", X"b8" when X"9a", X"14" when X"9b",
X"de" when X"9c", X"5e" when X"9d", X"0b" when X"9e", X"db" when X"9f",
 
X"e0" when X"a0", X"32" when X"a1", X"3a" when X"a2", X"0a" when X"a3",
X"49" when X"a4", X"06" when X"a5", X"24" when X"a6", X"5c" when X"a7",
X"c2" when X"a8", X"d3" when X"a9", X"ac" when X"aa", X"62" when X"ab",
X"91" when X"ac", X"95" when X"ad", X"e4" when X"ae", X"79" when X"af",
 
X"e7" when X"b0", X"c8" when X"b1", X"37" when X"b2", X"6d" when X"b3",
X"8d" when X"b4", X"d5" when X"b5", X"4e" when X"b6", X"a9" when X"b7",
X"6c" when X"b8", X"56" when X"b9", X"f4" when X"ba", X"ea" when X"bb",
X"65" when X"bc", X"7a" when X"bd", X"ae" when X"be", X"08" when X"bf",
 
X"ba" when X"c0", X"78" when X"c1", X"25" when X"c2", X"2e" when X"c3",
X"1c" when X"c4", X"a6" when X"c5", X"b4" when X"c6", X"c6" when X"c7",
X"e8" when X"c8", X"dd" when X"c9", X"74" when X"ca", X"1f" when X"cb",
X"4b" when X"cc", X"bd" when X"cd", X"8b" when X"ce", X"8a" when X"cf",
 
X"70" when X"d0", X"3e" when X"d1", X"b5" when X"d2", X"66" when X"d3",
X"48" when X"d4", X"03" when X"d5", X"f6" when X"d6", X"0e" when X"d7",
X"61" when X"d8", X"35" when X"d9", X"57" when X"da", X"b9" when X"db",
X"86" when X"dc", X"c1" when X"dd", X"1d" when X"de", X"9e" when X"df",
 
X"e1" when X"e0", X"f8" when X"e1", X"98" when X"e2", X"11" when X"e3",
X"69" when X"e4", X"d9" when X"e5", X"8e" when X"e6", X"94" when X"e7",
X"9b" when X"e8", X"1e" when X"e9", X"87" when X"ea", X"e9" when X"eb",
X"ce" when X"ec", X"55" when X"ed", X"28" when X"ee", X"df" when X"ef",
 
X"8c" when X"f0", X"a1" when X"f1", X"89" when X"f2", X"0d" when X"f3",
X"bf" when X"f4", X"e6" when X"f5", X"42" when X"f6", X"68" when X"f7",
X"41" when X"f8", X"99" when X"f9", X"2d" when X"fa", X"0f" when X"fb",
X"b0" when X"fc", X"54" when X"fd", X"bb" when X"fe", X"16" when X"ff",
 
-- end sbox
X"00" when others;
end phy;
/nfcc/trunk/rijndael/keyexpansion/keyexpansion.vhdl
0,0 → 1,258
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
--
-- KeyExpansion(byte key[4*Nk], word w[Nb*(Nr+1)], Nk)
-- begin
-- word temp
-- i = 0
-- while (i < Nk)
-- w[i] = word(key[4*i], key[4*i+1], key[4*i+2], key[4*i+3])
-- i = i + 1
-- end while
-- i = Nk
-- while (i < Nb * (Nr+1))
-- temp = w[i-1]
-- if (i mod Nk = 0)
-- temp = SubWord(RotWord(temp)) xor Rcon[i/Nk]
-- else if (Nk > 6 and i mod Nk = 4)
-- temp = SubWord(temp)
-- end if
-- w[i] = w[i-Nk] xor temp
-- i = i + 1
-- end while
-- end
-- Nk (Number of Key), Nb (Number of Block), Nr (Number of Round)
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity keyexpansion is
port (
key : in bit_vector (31 downto 00); -- source key
w : out bit_vector (31 downto 00); -- expanded keys
Nk : in bit_vector (03 downto 00); -- 128,192,256 => 4,6,8 (0100,0110,1000)
ld : in bit; -- 'ld' must active for Nk clock to load keys.
v : out bit; -- output valid signal
clk : in bit; -- clock signal
rst : in bit -- reset signal, its wise to reset before any action.
);
end keyexpansion;
 
architecture phy of keyexpansion is
 
constant Rc : bit_vector (79 downto 00) := ( X"01020408_10204080_1B36");
signal Rcs : bit_vector (79 downto 00) := ( X"01020408_10204080_1B36");
signal int : bit_vector (255 downto 0); -- 256 bit internal register
signal cnt : bit_vector (03 downto 00); -- 4 bit counter start from 1 not 0
signal cnts : bit_vector (05 downto 00); -- 6 bit counter start from 1 not 0
signal Rcon : bit_vector (07 downto 00); -- round constant
signal rot : bit; -- RotWord signal
signal crst : bit; -- reset counter
signal rsts : bit; -- reset state counter
signal mod4 : bit; -- modulo 4 (used in case of 256bit key)
signal Nk8s : bit; -- Nk 8 signal
signal ldi1 : bit; -- delayed load signal
signal ldrs : bit; -- reset signal from load
signal vld : bit; -- valid signal
signal vrst1 : bit; -- reset valid signal for 128bit key
signal vrst2 : bit; -- reset valid signal for 192bit key
signal vrst3 : bit; -- reset valid signal for 256bit key
signal rstsc : bit; -- reset state counter from reset valid signal
signal sai : bit_vector (07 downto 00); -- SubWord input signal
signal sbi : bit_vector (07 downto 00); -- SubWord input signal
signal sci : bit_vector (07 downto 00); -- SubWord input signal
signal sdi : bit_vector (07 downto 00); -- SubWord input signal
signal sao : bit_vector (07 downto 00); -- SubWord output signal
signal sbo : bit_vector (07 downto 00); -- SubWord output signal
signal sco : bit_vector (07 downto 00); -- SubWord output signal
signal sdo : bit_vector (07 downto 00); -- SubWord output signal
signal wi1 : bit_vector (31 downto 00); -- w[i] state signal
signal wiNk : bit_vector (31 downto 00); -- w[i-Nk] state signal
signal temp : bit_vector (31 downto 00); -- SubWord,RotWord,Rcon signal
signal tmp : bit_vector (31 downto 00); -- SubWord,RotWord,Rcon signal
 
--For SubWord
component sbox
port (
di : in bit_vector (07 downto 00);
do : out bit_vector (07 downto 00)
);
end component;
--For each round counter
component c4b
port (
cnt : out bit_vector (03 downto 00);
clk : in bit;
rst : in bit
);
end component;
--For all iteration in keyexpansion
component c6b
port (
cnt : out bit_vector (05 downto 00);
clk : in bit;
rst : in bit
);
end component;
 
begin
 
sboxa : sbox
port map (
di => sai,
do => sao
);
sboxb : sbox
port map (
di => sbi,
do => sbo
);
sboxc : sbox
port map (
di => sci,
do => sco
);
sboxd : sbox
port map (
di => sdi,
do => sdo
);
ctr1 : c4b
port map (
cnt => cnt,
clk => clk,
rst => crst
);
ctr2 : c6b
port map (
cnt => cnts,
clk => clk,
rst => rsts
);
 
--Special cases for Nk=8
mod4 <= not(cnt(3) or not(cnt(2)) or cnt(1) or cnt(0));
Nk8s <= mod4 and not(not(Nk(3)) or Nk(2) or Nk(1) or Nk(0));
 
--RotWord detection
rot <= not( (Nk(3) xor cnt(3)) or (Nk(2) xor cnt(2)) or
(Nk(1) xor cnt(1)) or (Nk(0) xor cnt(0)) );
 
process (clk)
begin
if ((clk = '1') and clk'event) then
ldi1 <= ld;
end if;
end process;
ldrs <= ld xor ldi1; -- reset signal from load
 
--Keyexpansion need 4*(Nr+1) clock to do all calculation with
--Nr = 10 when Nk = 4 (128 bit) this would generate 44(101100) 32bit keys
--Nr = 12 when Nk = 6 (192 bit) this would generate 52(110100) 32bit keys
--Nr = 14 when Nk = 8 (256 bit) this would generate 60(111100) 32bit keys
 
vrst1 <= not( not(cnts(5)) or cnts(4) or not(cnts(3)) or not(cnts(2)) or cnts(1) or cnts(0)); -- 44(101100)
vrst2 <= not( not(cnts(5)) or not(cnts(4)) or cnts(3) or not(cnts(2)) or cnts(1) or cnts(0)); -- 52(110100)
vrst3 <= not( not(cnts(5)) or not(cnts(4)) or not(cnts(3)) or not(cnts(2)) or cnts(1) or cnts(0));-- 60(111100)
 
with Nk(03 downto 00) select
rstsc <= vrst1 when B"0100", -- Nk 4(0100)
vrst2 when B"0110", -- Nk 6(0110)
vrst3 when B"1000", -- Nk 8(1000)
vrst1 when others; -- default
 
--Setting up counter inline with Nk periode.
--For each round
crst <= rst or rot or ldrs;
--For the state
rsts <= rst or (ldrs and ld) or rstsc;
 
process (clk)
begin
if ((clk = '1') and clk'event) then
if (rst = '1') then
vld <= '0';
elsif (((ldrs and ld) or (rstsc and vld)) = '1') then -- (ldrs and ld) is start signal (rstsc and vld) is end signal
vld <= not(vld);
end if;
end if;
end process;
 
v <= vld; -- valid key expansion output signal
 
--Round constant calculation
--Rcon sequence: 01 02 04 08 10 20 40 80 1b 36
Rcon(07 downto 00)<= Rcs (79 downto 72);
process (clk)
begin
if ((clk = '1') and clk'event) then
if (rst = '1') then -- default reset
Rcs <= Rc;
elsif (rot = '1') then -- shift one byte
Rcs (79 downto 08)<= Rcs (71 downto 00);
Rcs (07 downto 00)<= (others => '0');
end if;
end if;
end process;
 
with Nk(03 downto 00) select
wiNk <= int(127 downto 96) when B"0100", -- Nk 4(0100)
int(191 downto 160) when B"0110", -- Nk 6(0110)
int(255 downto 224) when B"1000", -- Nk 8(1000)
int(127 downto 96) when others; -- default
 
process (clk)
begin
if ((clk = '1') and clk'event) then
if (rst = '1') then
int(255 downto 00) <= (others => '0');
elsif (ld = '1') then
int(255 downto 00) <= int(223 downto 00) & key(31 downto 00);
else
int(255 downto 00) <= int(223 downto 00) & (wiNk xor temp);
end if;
end if;
end process;
 
wi1( 31 downto 00) <= int( 31 downto 00); -- first fifo
 
sai(07 downto 00)<= wi1(31 downto 24); -- SubWord
sbi(07 downto 00)<= wi1(23 downto 16); -- SubWord
sci(07 downto 00)<= wi1(15 downto 08); -- SubWord
sdi(07 downto 00)<= wi1(07 downto 00); -- SubWord
 
tmp <= sao & sbo & sco & sdo when Nk8s='1' else -- special cases for Nk 8
(sbo xor Rcon ) & sco & sdo & sao; -- others do: RotWord xor Rcon
 
temp <= tmp when (rot='1' or Nk8s='1') else wi1;
 
w ( 31 downto 00) <= int( 31 downto 00) when vld = '1' else (others => '0'); -- key expansion result
 
end phy;
/nfcc/trunk/rijndael/keyexpansion/keyexpansion_syn.pat
0,0 → 1,153
 
-- description generated by Pat driver
 
-- date : Thu Sep 17 14:13:41 2009
-- revision : v109
 
-- sequence : keyexpansion
 
-- input / output list :
in clk B;;
in rst B;;
in ld B;;
in key (31 downto 0) X;;
in nk (3 downto 0) X;;
out w (31 downto 0) X;;
out v B;;
in vss B;;
in vdd B;;
 
begin
 
-- Pattern description :
 
-- c r l k n w v v v
-- l s d e k s d
-- k t y s d
 
< 0 ps> : 0 1 0 00000000 4 ?uuuuuuuu ?u 0 1 ;
< 100000 ps> : 1 1 0 00000000 4 ?uuuuuuuu ?u 0 1 ;
< 200000 ps> : 0 0 1 2b7e1516 4 ?00000000 ?0 0 1 ;
< 300000 ps> : 1 0 1 2b7e1516 4 ?00000000 ?0 0 1 ;
< 400000 ps> : 0 0 1 28aed2a6 4 ?2b7e1516 ?1 0 1 ;
< 500000 ps> : 1 0 1 28aed2a6 4 ?2b7e1516 ?1 0 1 ;
< 600000 ps> : 0 0 1 abf71588 4 ?28aed2a6 ?1 0 1 ;
< 700000 ps> : 1 0 1 abf71588 4 ?28aed2a6 ?1 0 1 ;
< 800000 ps> : 0 0 1 09cf4f3c 4 ?abf71588 ?1 0 1 ;
< 900000 ps> : 1 0 1 09cf4f3c 4 ?abf71588 ?1 0 1 ;
< 1000000 ps> : 0 0 0 00000000 4 ?09cf4f3c ?1 0 1 ;
< 1100000 ps> : 1 0 0 00000000 4 ?09cf4f3c ?1 0 1 ;
< 1200000 ps> : 0 0 0 00000000 4 ?a0fafe17 ?1 0 1 ;
< 1300000 ps> : 1 0 0 00000000 4 ?a0fafe17 ?1 0 1 ;
< 1400000 ps> : 0 0 0 00000000 4 ?88542cb1 ?1 0 1 ;
< 1500000 ps> : 1 0 0 00000000 4 ?88542cb1 ?1 0 1 ;
< 1600000 ps> : 0 0 0 00000000 4 ?23a33939 ?1 0 1 ;
< 1700000 ps> : 1 0 0 00000000 4 ?23a33939 ?1 0 1 ;
< 1800000 ps> : 0 0 0 00000000 4 ?2a6c7605 ?1 0 1 ;
< 1900000 ps> : 1 0 0 00000000 4 ?2a6c7605 ?1 0 1 ;
< 2000000 ps> : 0 0 0 00000000 4 ?f2c295f2 ?1 0 1 ;
< 2100000 ps> : 1 0 0 00000000 4 ?f2c295f2 ?1 0 1 ;
< 2200000 ps> : 0 0 0 00000000 4 ?7a96b943 ?1 0 1 ;
< 2300000 ps> : 1 0 0 00000000 4 ?7a96b943 ?1 0 1 ;
< 2400000 ps> : 0 0 0 00000000 4 ?5935807a ?1 0 1 ;
< 2500000 ps> : 1 0 0 00000000 4 ?5935807a ?1 0 1 ;
< 2600000 ps> : 0 0 0 00000000 4 ?7359f67f ?1 0 1 ;
< 2700000 ps> : 1 0 0 00000000 4 ?7359f67f ?1 0 1 ;
< 2800000 ps> : 0 0 0 00000000 4 ?3d80477d ?1 0 1 ;
< 2900000 ps> : 1 0 0 00000000 4 ?3d80477d ?1 0 1 ;
< 3000000 ps> : 0 0 0 00000000 4 ?4716fe3e ?1 0 1 ;
< 3100000 ps> : 1 0 0 00000000 4 ?4716fe3e ?1 0 1 ;
< 3200000 ps> : 0 0 0 00000000 4 ?1e237e44 ?1 0 1 ;
< 3300000 ps> : 1 0 0 00000000 4 ?1e237e44 ?1 0 1 ;
< 3400000 ps> : 0 0 0 00000000 4 ?6d7a883b ?1 0 1 ;
< 3500000 ps> : 1 0 0 00000000 4 ?6d7a883b ?1 0 1 ;
< 3600000 ps> : 0 0 0 00000000 4 ?ef44a541 ?1 0 1 ;
< 3700000 ps> : 1 0 0 00000000 4 ?ef44a541 ?1 0 1 ;
< 3800000 ps> : 0 0 0 00000000 4 ?a8525b7f ?1 0 1 ;
< 3900000 ps> : 1 0 0 00000000 4 ?a8525b7f ?1 0 1 ;
< 4000000 ps> : 0 0 0 00000000 4 ?b671253b ?1 0 1 ;
< 4100000 ps> : 1 0 0 00000000 4 ?b671253b ?1 0 1 ;
< 4200000 ps> : 0 0 0 00000000 4 ?db0bad00 ?1 0 1 ;
< 4300000 ps> : 1 0 0 00000000 4 ?db0bad00 ?1 0 1 ;
< 4400000 ps> : 0 0 0 00000000 4 ?d4d1c6f8 ?1 0 1 ;
< 4500000 ps> : 1 0 0 00000000 4 ?d4d1c6f8 ?1 0 1 ;
< 4600000 ps> : 0 0 0 00000000 4 ?7c839d87 ?1 0 1 ;
< 4700000 ps> : 1 0 0 00000000 4 ?7c839d87 ?1 0 1 ;
< 4800000 ps> : 0 0 0 00000000 4 ?caf2b8bc ?1 0 1 ;
< 4900000 ps> : 1 0 0 00000000 4 ?caf2b8bc ?1 0 1 ;
< 5000000 ps> : 0 0 0 00000000 4 ?11f915bc ?1 0 1 ;
< 5100000 ps> : 1 0 0 00000000 4 ?11f915bc ?1 0 1 ;
< 5200000 ps> : 0 0 0 00000000 4 ?6d88a37a ?1 0 1 ;
< 5300000 ps> : 1 0 0 00000000 4 ?6d88a37a ?1 0 1 ;
< 5400000 ps> : 0 0 0 00000000 4 ?110b3efd ?1 0 1 ;
< 5500000 ps> : 1 0 0 00000000 4 ?110b3efd ?1 0 1 ;
< 5600000 ps> : 0 0 0 00000000 4 ?dbf98641 ?1 0 1 ;
< 5700000 ps> : 1 0 0 00000000 4 ?dbf98641 ?1 0 1 ;
< 5800000 ps> : 0 0 0 00000000 4 ?ca0093fd ?1 0 1 ;
< 5900000 ps> : 1 0 0 00000000 4 ?ca0093fd ?1 0 1 ;
< 6000000 ps> : 0 0 0 00000000 4 ?4e54f70e ?1 0 1 ;
< 6100000 ps> : 1 0 0 00000000 4 ?4e54f70e ?1 0 1 ;
< 6200000 ps> : 0 0 0 00000000 4 ?5f5fc9f3 ?1 0 1 ;
< 6300000 ps> : 1 0 0 00000000 4 ?5f5fc9f3 ?1 0 1 ;
< 6400000 ps> : 0 0 0 00000000 4 ?84a64fb2 ?1 0 1 ;
< 6500000 ps> : 1 0 0 00000000 4 ?84a64fb2 ?1 0 1 ;
< 6600000 ps> : 0 0 0 00000000 4 ?4ea6dc4f ?1 0 1 ;
< 6700000 ps> : 1 0 0 00000000 4 ?4ea6dc4f ?1 0 1 ;
< 6800000 ps> : 0 0 0 00000000 4 ?ead27321 ?1 0 1 ;
< 6900000 ps> : 1 0 0 00000000 4 ?ead27321 ?1 0 1 ;
< 7000000 ps> : 0 0 0 00000000 4 ?b58dbad2 ?1 0 1 ;
< 7100000 ps> : 1 0 0 00000000 4 ?b58dbad2 ?1 0 1 ;
< 7200000 ps> : 0 0 0 00000000 4 ?312bf560 ?1 0 1 ;
< 7300000 ps> : 1 0 0 00000000 4 ?312bf560 ?1 0 1 ;
< 7400000 ps> : 0 0 0 00000000 4 ?7f8d292f ?1 0 1 ;
< 7500000 ps> : 1 0 0 00000000 4 ?7f8d292f ?1 0 1 ;
< 7600000 ps> : 0 0 0 00000000 4 ?ac7766f3 ?1 0 1 ;
< 7700000 ps> : 1 0 0 00000000 4 ?ac7766f3 ?1 0 1 ;
< 7800000 ps> : 0 0 0 00000000 4 ?19fadc21 ?1 0 1 ;
< 7900000 ps> : 1 0 0 00000000 4 ?19fadc21 ?1 0 1 ;
< 8000000 ps> : 0 0 0 00000000 4 ?28d12941 ?1 0 1 ;
< 8100000 ps> : 1 0 0 00000000 4 ?28d12941 ?1 0 1 ;
< 8200000 ps> : 0 0 0 00000000 4 ?575c006e ?1 0 1 ;
< 8300000 ps> : 1 0 0 00000000 4 ?575c006e ?1 0 1 ;
< 8400000 ps> : 0 0 0 00000000 4 ?d014f9a8 ?1 0 1 ;
< 8500000 ps> : 1 0 0 00000000 4 ?d014f9a8 ?1 0 1 ;
< 8600000 ps> : 0 0 0 00000000 4 ?c9ee2589 ?1 0 1 ;
< 8700000 ps> : 1 0 0 00000000 4 ?c9ee2589 ?1 0 1 ;
< 8800000 ps> : 0 0 0 00000000 4 ?e13f0cc8 ?1 0 1 ;
< 8900000 ps> : 1 0 0 00000000 4 ?e13f0cc8 ?1 0 1 ;
< 9000000 ps> : 0 0 0 00000000 4 ?b6630ca6 ?1 0 1 ;
< 9100000 ps> : 1 0 0 00000000 4 ?b6630ca6 ?1 0 1 ;
< 9200000 ps> : 0 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 9300000 ps> : 1 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 9400000 ps> : 0 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 9500000 ps> : 1 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 9600000 ps> : 0 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 9700000 ps> : 1 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 9800000 ps> : 0 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 9900000 ps> : 1 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 10000000 ps> : 0 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 10100000 ps> : 1 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 10200000 ps> : 0 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 10300000 ps> : 1 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 10400000 ps> : 0 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 10500000 ps> : 1 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 10600000 ps> : 0 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 10700000 ps> : 1 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 10800000 ps> : 0 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 10900000 ps> : 1 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 11000000 ps> : 0 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 11100000 ps> : 1 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 11200000 ps> : 0 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 11300000 ps> : 1 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 11400000 ps> : 0 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 11500000 ps> : 1 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 11600000 ps> : 0 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 11700000 ps> : 1 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 11800000 ps> : 0 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 11900000 ps> : 1 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 12000000 ps> : 0 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 12100000 ps> : 1 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 12200000 ps> : 0 0 0 00000000 4 ?00000000 ?0 0 1 ;
< 12300000 ps> : 1 0 0 00000000 4 ?00000000 ?0 0 1 ;
 
end;
/nfcc/trunk/rijndael/keyexpansion/Makefile
0,0 → 1,103
#- ------------------------------------------------------------------------
#- Copyright (C) 2010 Arif Endro Nugroho
#- All rights reserved.
#-
#- Redistribution and use in source and binary forms, with or without
#- modification, are permitted provided that the following conditions
#- are met:
#-
#- 1. Redistributions of source code must retain the above copyright
#- notice, this list of conditions and the following disclaimer.
#- 2. Redistributions in binary form must reproduce the above copyright
#- notice, this list of conditions and the following disclaimer in the
#- documentation and/or other materials provided with the distribution.
#-
#- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
#- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
#- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
#- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
#- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
#- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
#- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
#- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
#- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
#- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
#- POSSIBILITY OF SUCH DAMAGE.
#-
#- End Of License.
#- ------------------------------------------------------------------------
#
# Need to FLATTENING the design before OCP and NERO
# Use x2y vst vst <source> <result>
# then flatlo -r <source> <result> # source is a result from x2y
# this two sequence will remove most warning/error message when
# performing LOON on the netlist.
#
# BOOM will optimize the logic
# BOOG will optimize/convert the logic into netlist
# LOON will optimize the netlist (this will report area/timing)
#
# VST is a circuit netlist file
# AP is a circuit placement file (OCP/NERO create this file)
# VBE is alliance VHDL Behavioral Description file
 
VASYFLAGS = -V -B -I vhdl -a -p -o
BOOMFLAGS = -VP
BOOGFLAGS =
LOONFLAGS =
OCPFLAGS = -v
NEROFLAGS = -V -G -6 -p
DRUCFLAGS =
S2RFLAGS = -v
OCP = ocp
NERO = nero
DRUC = druc
S2R = s2r
VASY = vasy
BOOM = boom
BOOG = boog
LOON = loon
RM = /bin/rm -vf
X2Y = x2y
FLATLO = flatlo
X2YFLAGS = vst vst
FLATLOFLAGS = -r
TOUCH = touch
 
# Set-up TARGET variable respectively
%.ap: TARGET = $(subst .ap,, $@)
%.cif: TARGET = $(subst .cif,, $@)
%.vst: TARGET = $(subst .vst,, $@)
%.flt: TARGET = $(subst .flt,, $@)
%.flatten: TARGET = $(subst .flatten,, $@)
 
all: sbox.vbe counter.vbe keyexpansion.vbe
 
%.vbe: %.vhdl
@$(VASY) $(VASYFLAGS) $<
 
%.vst: %.vbe
@$(BOOM) $(BOOMFLAGS) $(TARGET) $(TARGET)_o
@$(BOOG) $(BOOGFLAGS) $(TARGET)_o
@$(LOON) $(LOONFLAGS) $(TARGET)_o $(TARGET)
-$(RM) $(TARGET)_o.*
 
%.flt: %.vbe
@$(BOOM) $(BOOMFLAGS) $(TARGET)_model $(TARGET)_model_o
@$(BOOG) $(BOOGFLAGS) $(TARGET)_model_o
@$(LOON) $(LOONFLAGS) $(TARGET)_model_o $(TARGET)_model
-$(RM) $(TARGET)_model_o.*
@$(X2Y) $(X2YFLAGS) $(TARGET) $(TARGET)_m
@$(FLATLO) $(FLATLOFLAGS) $(TARGET)_m $(TARGET)_o
@$(LOON) $(LOONFLAGS) $(TARGET)_o $(TARGET)
-$(RM) $(TARGET){_o,m}.*
@$(TOUCH) $@
 
%.flatten: %.vst
@$(X2Y) $(X2YFLAGS) $(TARGET) $(TARGET)_m
@$(FLATLO) $(FLATLOFLAGS) $(TARGET)_m $(TARGET)_o
@$(LOON) $(LOONFLAGS) $(TARGET)_o $(TARGET)
-$(RM) $(TARGET){_o,m}.*
 
clean:
@rm -vf *.dat *.gpl *.vhd *.vbe *.boom *.pat *.vst *.xsc *.ap *.cif *.drc done.* *.flt
/nfcc/trunk/rijndael/keyexpansion/keyexpansion.c
0,0 → 1,176
#include <stdio.h>
#include "genpat.h"
 
char *inttostr(entier)
int entier;
{
char *str;
str = (char *) mbkalloc (32 * sizeof (char));
sprintf (str, "%d",entier);
return(str);
}
/*------------------------------*/
/* end of the description */
/*------------------------------*/
 
main ()
{
int i;
 
DEF_GENPAT("keyexpansion-tst");
SETTUNIT("ns");
 
/* interface */
DECLAR ("clk", ":1", "B", IN , "" , "" );
DECLAR ("rst", ":1", "B", IN , "" , "" );
DECLAR ("ld" , ":1", "B", IN , "" , "" );
DECLAR ("key", ":1", "X", IN ,"31 downto 0", "" );
DECLAR ("Nk" , ":1", "X", IN , "3 downto 0", "" );
DECLAR ("w" , ":1", "X", OUT,"31 downto 0", "" );
DECLAR ("v" , ":1", "B", OUT, "" , "" );
DECLAR ("vss", ":1", "B", IN , "" , "" );
DECLAR ("vdd", ":1", "B", IN , "" , "" );
 
AFFECT ("0", "vss", "0b0");
AFFECT ("0", "vdd", "0b1");
 
AFFECT ( "0", "clk", "0b0");
AFFECT ( "0", "rst", "0b1");
AFFECT ( "0", "ld" , "0b0");
AFFECT ( "0", "key", "0x00000000");
AFFECT ( "0", "Nk" , "0x0");
AFFECT ("+100", "clk", "0b1");
 
AFFECT ("+100", "clk", "0b0");
AFFECT (" +0", "rst", "0b0");
AFFECT (" +0", "ld" , "0b1");
AFFECT (" +0", "key", "0x2b7e1516");
AFFECT (" +0", "Nk" , "0x4");
AFFECT ("+100", "clk", "0b1");
 
AFFECT ("+100", "clk", "0b0");
AFFECT (" +0", "key", "0x28aed2a6");
AFFECT ("+100", "clk", "0b1");
 
AFFECT ("+100", "clk", "0b0");
AFFECT (" +0", "key", "0xabf71588");
AFFECT ("+100", "clk", "0b1");
 
AFFECT ("+100", "clk", "0b0");
AFFECT (" +0", "key", "0x09cf4f3c");
AFFECT ("+100", "clk", "0b1");
 
AFFECT ("+100", "clk", "0b0");
AFFECT (" +0", "ld" , "0b0");
AFFECT (" +0", "key", "0x00000000");
AFFECT ("+100", "clk", "0b1");
 
for (i=0; i<56; i++)
{
AFFECT ("+100", "clk", "0b0" );
AFFECT ("+100", "clk", "0b1" );
}
 
AFFECT ("+100", "clk", "0b0" );
AFFECT ( "+0", "rst", "0b1");
AFFECT ( "+0", "ld" , "0b0");
AFFECT ( "+0", "key", "0x00000000");
AFFECT ( "+0", "Nk" , "0x0");
AFFECT ("+100", "clk", "0b1");
 
AFFECT ("+100", "clk", "0b0");
AFFECT (" +0", "rst", "0b0");
AFFECT (" +0", "ld" , "0b1");
AFFECT (" +0", "key", "0x8e73b0f7");
AFFECT (" +0", "Nk" , "0x6");
AFFECT ("+100", "clk", "0b1");
 
AFFECT ("+100", "clk", "0b0");
AFFECT (" +0", "key", "0xda0e6452");
AFFECT ("+100", "clk", "0b1");
 
AFFECT ("+100", "clk", "0b0");
AFFECT (" +0", "key", "0xc810f32b");
AFFECT ("+100", "clk", "0b1");
 
AFFECT ("+100", "clk", "0b0");
AFFECT (" +0", "key", "0x809079e5");
AFFECT ("+100", "clk", "0b1");
 
AFFECT ("+100", "clk", "0b0");
AFFECT (" +0", "key", "0x62f8ead2");
AFFECT ("+100", "clk", "0b1");
 
AFFECT ("+100", "clk", "0b0");
AFFECT (" +0", "key", "0x522c6b7b");
AFFECT ("+100", "clk", "0b1");
 
AFFECT ("+100", "clk", "0b0");
AFFECT (" +0", "ld" , "0b0");
AFFECT (" +0", "key", "0x00000000");
AFFECT ("+100", "clk", "0b1");
 
for (i=0; i<56; i++)
{
AFFECT ("+100", "clk", "0b0" );
AFFECT ("+100", "clk", "0b1" );
}
 
AFFECT ("+100", "clk", "0b0" );
AFFECT ( "+0", "rst", "0b1");
AFFECT ( "+0", "ld" , "0b0");
AFFECT ( "+0", "key", "0x00000000");
AFFECT ( "+0", "Nk" , "0x0");
AFFECT ("+100", "clk", "0b1");
 
AFFECT ("+100", "clk", "0b0");
AFFECT (" +0", "rst", "0b0");
AFFECT (" +0", "ld" , "0b1");
AFFECT (" +0", "key", "0x603deb10");
AFFECT (" +0", "Nk" , "0x8");
AFFECT ("+100", "clk", "0b1");
 
AFFECT ("+100", "clk", "0b0");
AFFECT (" +0", "key", "0x15ca71be");
AFFECT ("+100", "clk", "0b1");
 
AFFECT ("+100", "clk", "0b0");
AFFECT (" +0", "key", "0x2b73aef0");
AFFECT ("+100", "clk", "0b1");
 
AFFECT ("+100", "clk", "0b0");
AFFECT (" +0", "key", "0x857d7781");
AFFECT ("+100", "clk", "0b1");
 
AFFECT ("+100", "clk", "0b0");
AFFECT (" +0", "key", "0x1f352c07");
AFFECT ("+100", "clk", "0b1");
 
AFFECT ("+100", "clk", "0b0");
AFFECT (" +0", "key", "0x3b6108d7");
AFFECT ("+100", "clk", "0b1");
 
AFFECT ("+100", "clk", "0b0");
AFFECT (" +0", "key", "0x2d9810a3");
AFFECT ("+100", "clk", "0b1");
 
AFFECT ("+100", "clk", "0b0");
AFFECT (" +0", "key", "0x0914dff4");
AFFECT ("+100", "clk", "0b1");
 
AFFECT ("+100", "clk", "0b0");
AFFECT (" +0", "ld" , "0b0");
AFFECT (" +0", "key", "0x00000000");
AFFECT ("+100", "clk", "0b1");
 
for (i=0; i<56; i++)
{
AFFECT ("+100", "clk", "0b0" );
AFFECT ("+100", "clk", "0b1" );
}
 
AFFECT ("+100", "clk", "0b0");
SAV_GENPAT ();
 
}
 
/nfcc/trunk/kasumi/keyschedule.vhdl
0,0 → 1,175
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity keyschedule is
port (
key : in bit_vector ( 63 downto 0);
st : in bit_vector ( 3 downto 0);
ldk : in bit;
--probe
--keyreg1_prb : out bit_vector (127 downto 0);
--keyreg2_prb : out bit_vector (127 downto 0);
--probe
rk : out bit_vector ( 15 downto 0);
clk : in bit;
rst : in bit
);
end keyschedule;
 
architecture phy of keyschedule is
signal keyreg1 : bit_vector (127 downto 0);
signal keyreg2 : bit_vector (127 downto 0);
signal k1 : bit_vector ( 15 downto 0);
signal k2 : bit_vector ( 15 downto 0);
signal k3 : bit_vector ( 15 downto 0);
signal k4 : bit_vector ( 15 downto 0);
signal k5 : bit_vector ( 15 downto 0);
signal k6 : bit_vector ( 15 downto 0);
signal k7 : bit_vector ( 15 downto 0);
signal k8 : bit_vector ( 15 downto 0);
signal c1 : bit_vector ( 15 downto 0);
signal c2 : bit_vector ( 15 downto 0);
signal c3 : bit_vector ( 15 downto 0);
signal c4 : bit_vector ( 15 downto 0);
signal c5 : bit_vector ( 15 downto 0);
signal c6 : bit_vector ( 15 downto 0);
signal c7 : bit_vector ( 15 downto 0);
signal c8 : bit_vector ( 15 downto 0);
--constant c1 : bit_vector ( 15 downto 0) := X"0123";
--constant c2 : bit_vector ( 15 downto 0) := X"4567";
--constant c3 : bit_vector ( 15 downto 0) := X"89ab";
--constant c4 : bit_vector ( 15 downto 0) := X"cdef";
--constant c5 : bit_vector ( 15 downto 0) := X"fedc";
--constant c6 : bit_vector ( 15 downto 0) := X"ba98";
--constant c7 : bit_vector ( 15 downto 0) := X"7654";
--constant c8 : bit_vector ( 15 downto 0) := X"3210";
signal ikey : bit_vector ( 15 downto 0);
--signal st : bit_vector ( 2 downto 0);
--signal ldk : bit;
 
begin
 
--probe
--keyreg1_prb <= keyreg1;
--keyreg2_prb <= keyreg2;
--probe
 
--process (clk)
--begin
--if ((clk = '1') and clk'event) then
-- if (rst = '1') then
-- rk <= (others => '0');
-- else
rk <= ikey;
-- end if;
--end if;
--end process;
 
process (clk)
begin
if ((clk = '1') and clk'event) then
if (rst = '1') then
keyreg1 <= (others => '0');
keyreg2 <= X"0123456789abcdeffedcba9876543210";
elsif (ldk = '1') then
keyreg1 <= keyreg1( 63 downto 0) & key;
keyreg2 <= X"0123456789abcdeffedcba9876543210";
elsif (st = X"f") then
keyreg1 <= keyreg1( 95 downto 0) & keyreg1(127 downto 96);
keyreg2 <= keyreg2( 95 downto 0) & keyreg2(127 downto 96);
end if;
end if;
end process;
 
k1 <= keyreg1(127 downto 112);
k2 <= keyreg1(111 downto 96);
k3 <= keyreg1( 95 downto 80);
k4 <= keyreg1( 79 downto 64);
k5 <= keyreg1( 63 downto 48);
k6 <= keyreg1( 47 downto 32);
k7 <= keyreg1( 31 downto 16);
k8 <= keyreg1( 15 downto 0);
 
c1 <= keyreg2(127 downto 112);
c2 <= keyreg2(111 downto 96);
c3 <= keyreg2( 95 downto 80);
c4 <= keyreg2( 79 downto 64);
c5 <= keyreg2( 63 downto 48);
c6 <= keyreg2( 47 downto 32);
c7 <= keyreg2( 31 downto 16);
c8 <= keyreg2( 15 downto 0);
 
process (st,rst,k1,k2,k3,k4,k5,k6,k7,k8,c1,c3,c4,c5,c6,c8)
begin
if (rst = '1') then
ikey <= (others => '0');
else
case st is
when X"0" => --KLi,1
ikey <= k1(14 downto 0) & k1(15);
when X"1" => --KLi,2
ikey <= k3 xor c3;
when X"2" => --KOi,1
ikey <= k2(10 downto 0) & k2(15 downto 11);
when X"3" => --KIi,1
ikey <= k5 xor c5;
when X"4" => --KOi,2
ikey <= k6( 7 downto 0) & k6(15 downto 8);
when X"5" => --KIi,2
ikey <= k4 xor c4;
when X"6" => --KOi,3
ikey <= k7( 2 downto 0) & k7(15 downto 3);
when X"7" => --KIi,3
ikey <= k8 xor c8;
when X"8" => --KOi,1
ikey <= k3(10 downto 0) & k3(15 downto 11);
when X"9" => --KIi,1
ikey <= k6 xor c6;
when X"a" => --KOi,2
ikey <= k7( 7 downto 0) & k7(15 downto 8);
when X"b" => --KIi,2
ikey <= k5 xor c5;
when X"c" => --KOi,3
ikey <= k8( 2 downto 0) & k8(15 downto 3);
when X"d" => --KIi,3
ikey <= k1 xor c1;
when X"e" => --KLi,1
ikey <= k2(14 downto 0) & k2(15);
when X"f" => --KLi,2
ikey <= k4 xor c4;
end case;
end if;
end process;
 
end phy;
 
/nfcc/trunk/kasumi/pt.lst
0,0 → 1,2
0x01234567
0x89abcdef
/nfcc/trunk/kasumi/kasumi.vhdl
0,0 → 1,360
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity kasumi is
port (
pt : in bit_vector ( 31 downto 0);
ldpt : in bit;
key : in bit_vector ( 63 downto 0);
ldk : in bit;
--probe
--L_prb : out bit_vector ( 31 downto 0);
--R_prb : out bit_vector ( 31 downto 0);
--FL_prb : out bit_vector ( 31 downto 0);
--ikey_prb : out bit_vector ( 15 downto 0);
--FO_prb : out bit_vector ( 15 downto 0);
--FI_prb : out bit_vector ( 15 downto 0);
--st_prb : out bit_vector ( 3 downto 0);
--rnd_prb : out bit_vector ( 1 downto 0);
--even_prb : out bit;
--probe
ct : out bit_vector ( 63 downto 0);
v : out bit;
clk : in bit;
rst : in bit
);
end kasumi;
 
architecture phy of kasumi is
 
signal ireg1 : bit_vector ( 63 downto 0);
signal ikey : bit_vector ( 15 downto 0);
signal ipt : bit_vector ( 31 downto 0);
signal iptt : bit_vector ( 31 downto 0);
signal r : bit_vector ( 31 downto 0);
signal l : bit_vector ( 31 downto 0);
signal ir : bit_vector ( 31 downto 0);
signal il : bit_vector ( 31 downto 0);
signal F : bit_vector ( 31 downto 0);
signal FL : bit_vector ( 31 downto 0);
signal FLl : bit_vector ( 15 downto 0);
signal FLr : bit_vector ( 15 downto 0);
signal FL0 : bit_vector ( 15 downto 0);
signal FL1 : bit_vector ( 15 downto 0);
signal LFL : bit_vector ( 15 downto 0);
signal RFL : bit_vector ( 15 downto 0);
signal FO : bit_vector ( 15 downto 0);
signal FI : bit_vector ( 15 downto 0);
signal x7a : bit_vector ( 6 downto 0);
signal x9a : bit_vector ( 8 downto 0);
signal x7b : bit_vector ( 6 downto 0);
signal x9b : bit_vector ( 8 downto 0);
signal y7a : bit_vector ( 6 downto 0);
signal y9a : bit_vector ( 8 downto 0);
signal y7b : bit_vector ( 6 downto 0);
signal y9b : bit_vector ( 8 downto 0);
signal st : bit_vector ( 3 downto 0); -- 16 states
signal c3b : bit_vector ( 2 downto 0);
signal c3b_cr : bit_vector ( 2 downto 0);
signal c3b_rst : bit;
signal rnd : bit_vector ( 1 downto 0);
signal rnd_cr : bit_vector ( 1 downto 0);
signal rnd_rst : bit;
signal even : bit;
signal vld : bit;
signal ildpt : bit;
signal ildpt_rst : bit;
signal ildptt : bit;
 
component sbox
port (
x7 : in bit_vector ( 6 downto 0);
x9 : in bit_vector ( 8 downto 0);
y7 : out bit_vector ( 6 downto 0);
y9 : out bit_vector ( 8 downto 0)
);
end component;
 
component keyschedule
port (
key : in bit_vector ( 63 downto 0);
st : in bit_vector ( 3 downto 0);
ldk : in bit;
rk : out bit_vector ( 15 downto 0);
clk : in bit;
rst : in bit
);
end component;
 
begin
 
s1 : sbox
port map (
x7 => x7a,
x9 => x9a,
y7 => y7a,
y9 => y9a
);
s2 : sbox
port map (
x7 => x7b,
x9 => x9b,
y7 => y7b,
y9 => y9b
);
roundkey : keyschedule
port map (
key => key,
st => st,
ldk => ldk,
rk => ikey,
clk => clk,
rst => rst
);
 
--probe
--L_prb <= l;
--R_prb <= r;
--ikey_prb <= ikey;
--FL_prb <= FL;
--FI_prb <= FI;
--FO_prb <= FO;
--st_prb <= st;
--rnd_prb <= rnd;
--even_prb <= even;
--probe
 
process (clk)
begin
if ((clk = '1') and clk'event) then
if (rst = '1') then
ildpt <= '0';
ildptt <= '0';
ipt <= (others => '0');
-- ikey <= (others => '0');
iptt <= (others => '0');
else
ildptt <= ldpt;
ildpt <= ildptt;
iptt <= pt;
ipt <= iptt;
-- ikey <= key;
end if;
end if;
end process;
 
process (clk)
begin
if ((clk = '1') and clk'event) then
if (rst = '1') then
even <= '0';
elsif (c3b = O"7") then
even <= not(even);
end if;
end if;
end process;
 
c3b_cr(0) <= '0'; -- LSB always zero
c3b_cr( 2 downto 1) <= ( ((c3b( 1 downto 0) and B"01") or (c3b( 1 downto 0) and c3b_cr( 1 downto 0))) or (B"01" and c3b_cr( 1 downto 0)) );
 
process (clk)
begin
if (clk = '1' and clk'event) then
if (c3b_rst = '1') then
c3b <= B"000";
else
c3b <= ((c3b xor B"001") xor c3b_cr);
end if;
end if;
end process;
 
ildpt_rst <= ((ildpt xor ildptt) and ildpt);
c3b_rst <= rst or ildpt_rst;
 
l <= ireg1( 63 downto 32);
r <= ireg1( 31 downto 0);
 
--0-FL-FL-FO-FI-FO-FI-FO-FI+FO-FI-FO-FI-FO-FI-FL-FL+
--1-FL-FL-FO-FI-FO-FI-FO-FI+FO-FI-FO-FI-FO-FI-FL-FL+
--2-FL-FL-FO-FI-FO-FI-FO-FI+FO-FI-FO-FI-FO-FI-FL-FL+
--3-FL-FL-FO-FI-FO-FI-FO-FI+FO-FI-FO-FI-FO-FI-FL-FL+
 
st <= even & c3b;
process (st,rst,FL,FO,FI,FL0,FL1,r)
begin
if (rst = '1') then
LFL <= (others => '0');
RFL <= (others => '0');
else
case st is
when X"0" =>
LFL <= FL(31 downto 16);
RFL <= FL0;
when X"1" =>
LFL <= FL1;
RFL <= FL(15 downto 0);
when X"2" =>
LFL <= FO;
RFL <= FL(15 downto 0);
when X"3" =>
LFL <= FL(15 downto 0);
RFL <= FI xor FL(15 downto 0);
when X"4" =>
LFL <= FO;
RFL <= FL(15 downto 0);
when X"5" =>
LFL <= FL(15 downto 0);
RFL <= FI xor FL(15 downto 0);
when X"6" =>
LFL <= FO;
RFL <= FL(15 downto 0);
when X"7" =>
LFL <= FL(15 downto 0) xor r(31 downto 16); -- xor R
RFL <= FI xor FL(15 downto 0) xor r(15 downto 0); -- xor R
when X"8" =>
LFL <= FO;
RFL <= FL(15 downto 0);
when X"9" =>
LFL <= FL(15 downto 0);
RFL <= FI xor FL(15 downto 0);
when X"a" =>
LFL <= FO;
RFL <= FL(15 downto 0);
when X"b" =>
LFL <= FL(15 downto 0);
RFL <= FI xor FL(15 downto 0);
when X"c" =>
LFL <= FO;
RFL <= FL(15 downto 0);
when X"d" =>
LFL <= FL(15 downto 0);
RFL <= FI xor FL(15 downto 0);
when X"e" =>
LFL <= FL(31 downto 16);
RFL <= FL0;
when X"f" =>
LFL <= FL1 xor r(31 downto 16); -- xor R
RFL <= FL(15 downto 0) xor r(15 downto 0); -- xor R
end case;
end if;
end process;
 
FLl <= l(31 downto 16) when even = '0' else FL(31 downto 16);
FLr <= l(15 downto 0) when even = '0' else FL(15 downto 0);
--FL(R') == FL(R) xor ROTL1{FL(L) and KLi1}
FL0 <= FLr xor ((FLl(14 downto 0) and ikey(14 downto 0)) & (FLl(15) and ikey(15)));
--FL(L') == FL(L) xor ROTL1{FL(R') or KLi2}
FL1 <= FLl xor ((FL (14 downto 0) or ikey(14 downto 0)) & (FL (15) or ikey(15)));
 
process (clk)
begin
if ((clk = '1') and clk'event) then
if (rst = '1') then
FL <= (others => '0');
else
FL <= LFL & RFL;
end if;
end if;
end process;
 
--FO == Lj-1 xor KOij
FO <= FL(31 downto 16) xor ikey(15 downto 0);
 
--FI-function
-- L1 == R0 R1 == S9[L0] xor ZE(R0)
-- L2 == R1 xor KIij2 R2 == S7[L1] xor TR(R1) xor KIij1
-- L3 == R2 R3 == S9[L2] xor ZE(R2)
-- L4 == S7[L3] xor TR(R3) R4 == R3
-- Return L4 || R4
 
--L0
x9a <= FL(31 downto 23);
--R0
x7a <= FL(22 downto 16);
--L2 == S9[L0] xor ZE (R0) xor KIi,j,2 (9 bit)
x9b <= y9a(8 downto 0) xor (B"00" & x7a) xor ikey( 8 downto 0);
--R2 == S7[L1] xor TR(R1) xor KIi,j,1 (7 bit)
x7b <= y7a xor y9a(6 downto 0) xor x7a xor ikey(15 downto 9);
--R3 == S9[L2] xor ZE (R2)
FI( 8 downto 0) <= y9b(8 downto 0) xor (B"00" & x7b);
--L4 == S7[L3] xor TR(R3)
FI(15 downto 9) <= y7b xor FI(6 downto 0);
--Rj == FI(Lj-1 xor KOij, KIij) xor Rj-1
 
il <= LFL & RFL;
--R' == Li-1
ir <= l;
 
process (clk)
begin
if ((clk = '1') and clk'event) then
if (rst = '1') then
ireg1 <= (others => '0');
elsif (ildpt = '1') then
ireg1 <= ireg1( 31 downto 0) & ipt;
elsif (c3b = O"7") then
ireg1(31 downto 0)<= ir;
ireg1(63 downto 32)<= il;
end if;
end if;
end process;
 
rnd_cr <= rnd(0) & '0';
process (clk)
begin
if ((clk = '1') and clk'event) then
if (rst = '1') then
rnd <= B"00";
elsif (st = X"f") then
rnd <= ((rnd xor B"01") xor rnd_cr);
end if;
end if;
end process;
 
process (clk)
begin
if ((clk = '1') and clk'event) then
if (rst = '1') then
vld <= '0';
elsif ((rnd & st) = B"111111") then
vld <= '1';
else
vld <= '0';
end if;
end if;
end process;
 
v <= vld;
ct <= l & r;
 
end phy;
/nfcc/trunk/kasumi/keyschedule.c
0,0 → 1,67
#include <stdio.h>
#include "genpat.h"
 
char *inttostr(entier)
int entier;
{
char *str;
str = (char *) mbkalloc (32 * sizeof (char));
sprintf (str, "%d",entier);
return(str);
}
/*------------------------------*/
/* end of the description */
/*------------------------------*/
 
main ()
{
int i,j;
int cur_vect = 0;
 
DEF_GENPAT("keyschedule");
SETTUNIT("ns");
 
/* interface */
DECLAR ("clk", ":1", "B", IN , "" , "" );
DECLAR ("rst", ":1", "B", IN , "" , "" );
DECLAR ("key", ":2", "X", IN ,"63 downto 0", "" );
DECLAR ( "st", ":2", "X", IN , "3 downto 0", "" );
DECLAR ("ildk",":1", "B", IN , "" , "" );
//DECLAR ("keyreg1_prb", ":2", "X", OUT,"127 downto 0", "" );
//DECLAR ("keyreg2_prb", ":2", "X", OUT,"127 downto 0", "" );
DECLAR ("rk" , ":2", "X", OUT, "15 downto 0", "" );
//DECLAR ("y9" , ":2", "X", OUT, "8 downto 0", "" );
DECLAR ("vss", ":1", "B", IN , "" , "" );
DECLAR ("vdd", ":1", "B", IN , "" , "" );
 
AFFECT ("0", "vss", "0b0");
AFFECT ("0", "vdd", "0b1");
AFFECT ("0", "rst", "0b1");
AFFECT ("0", "key", "0x0000000000000000");
AFFECT ("0", "st", "0x0");
AFFECT ( "0","ildk","0b0");
AFFECT ( "0", "clk", "0b0");
AFFECT ("+10", "clk", "0b1");
AFFECT ("+10", "clk", "0b0");
AFFECT ( "+0", "rst", "0b0");
AFFECT ( "+0","ildk", "0b1");
AFFECT ("+0", "key", "0x0011223344556677");
AFFECT ("+10", "clk", "0b1");
AFFECT ("+10", "clk", "0b0");
AFFECT ("+0", "key", "0x8899aabbccddeeff");
AFFECT ("+10", "clk", "0b1");
AFFECT ("+10", "clk", "0b0");
AFFECT ( "+0","ildk", "0b0");
AFFECT ("+0", "key", "0x0000000000000000");
for (j=0; j<0x004; j++)
for (i=0; i<0x010; i++)
{
AFFECT ( "+0", "st", inttostr(i) );
AFFECT ("+10", "clk", "0b1");
AFFECT ("+10", "clk", "0b0");
cur_vect++;
}
 
SAV_GENPAT ();
}
 
/nfcc/trunk/kasumi/sbox.vhdl
0,0 → 1,103
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity sbox is
port (
x7 : in bit_vector ( 6 downto 0);
x9 : in bit_vector ( 8 downto 0);
y7 : out bit_vector ( 6 downto 0);
y9 : out bit_vector ( 8 downto 0)
);
end sbox;
 
architecture phy of sbox is
begin
--S7
y7(0) <= (x7(1) and x7(3)) xor x7(4) xor (x7(0) and x7(1) and x7(4)) xor x7(5) xor
(x7(2) and x7(5)) xor
(x7(3) and x7(4) and x7(5)) xor x7(6) xor (x7(0) and x7(6)) xor (x7(1) and x7(6)) xor
(x7(3) and x7(6)) xor (x7(2) and x7(4) and x7(6)) xor (x7(1) and x7(5) and x7(6)) xor (x7(4) and x7(5) and x7(6));
y7(1) <= (x7(0) and x7(1)) xor (x7(0) and x7(4)) xor (x7(2) and x7(4)) xor x7(5) xor
(x7(1) and x7(2) and x7(5)) xor (x7(0) and x7(3) and x7(5)) xor x7(6) xor (x7(0) and x7(2) and x7(6)) xor
(x7(3) and x7(6)) xor (x7(4) and x7(5) and x7(6)) xor '1';
y7(2) <= x7(0) xor (x7(0) and x7(3)) xor (x7(2) and x7(3)) xor (x7(1) and x7(2) and x7(4)) xor
(x7(0) and x7(3) and x7(4)) xor (x7(1) and x7(5)) xor (x7(0) and x7(2) and x7(5)) xor (x7(0) and x7(6)) xor
(x7(0) and x7(1) and x7(6)) xor (x7(2) and x7(6)) xor (x7(4) and x7(6)) xor '1';
y7(3) <= x7(1) xor (x7(0) and x7(1) and x7(2)) xor (x7(1) and x7(4)) xor
(x7(3) and x7(4)) xor (x7(0) and x7(5)) xor (x7(0) and x7(1) and x7(5)) xor (x7(2) and x7(3) and x7(5)) xor
(x7(1) and x7(4) and x7(5)) xor (x7(2) and x7(6)) xor (x7(1) and x7(3) and x7(6));
y7(4) <= (x7(0) and x7(2)) xor x7(3) xor (x7(1) and x7(3)) xor (x7(1) and x7(4)) xor
(x7(0) and x7(1) and x7(4)) xor (x7(2) and x7(3) and x7(4)) xor (x7(0) and x7(5)) xor (x7(1) and x7(3) and x7(5)) xor
(x7(0) and x7(4) and x7(5)) xor (x7(1) and x7(6)) xor (x7(3) and x7(6)) xor (x7(0) and x7(3) and x7(6)) xor
(x7(5) and x7(6)) xor '1';
y7(5) <= x7(2) xor (x7(0) and x7(2)) xor (x7(0) and x7(3)) xor (x7(1) and x7(2) and x7(3)) xor
(x7(0) and x7(2) and x7(4)) xor (x7(0) and x7(5)) xor (x7(2) and x7(5)) xor (x7(4) and x7(5)) xor
(x7(1) and x7(6)) xor (x7(1) and x7(2) and x7(6)) xor (x7(0) and x7(3) and x7(6)) xor (x7(3) and x7(4) and x7(6)) xor
(x7(2) and x7(5) and x7(6)) xor '1';
y7(6) <= (x7(1) and x7(2)) xor (x7(0) and x7(1) and x7(3)) xor (x7(0) and x7(4)) xor (x7(1) and x7(5)) xor
(x7(3) and x7(5)) xor x7(6) xor (x7(0) and x7(1) and x7(6)) xor (x7(2) and x7(3) and x7(6)) xor
(x7(1) and x7(4) and x7(6)) xor (x7(0) and x7(5) and x7(6));
--S7
--S9
y9(0) <= (x9(0) and x9(2)) xor x9(3) xor (x9(2) and x9(5)) xor (x9(5) and x9(6)) xor
(x9(0) and x9(7)) xor (x9(1) and x9(7)) xor (x9(2) and x9(7)) xor (x9(4) and x9(8)) xor
(x9(5) and x9(8)) xor (x9(7) and x9(8)) xor '1';
y9(1) <= x9(1) xor (x9(0) and x9(1)) xor (x9(2) and x9(3)) xor (x9(0) and x9(4)) xor
(x9(1) and x9(4)) xor (x9(0) and x9(5)) xor (x9(3) and x9(5)) xor x9(6) xor
(x9(1) and x9(7)) xor (x9(2) and x9(7)) xor (x9(5) and x9(8)) xor '1';
y9(2) <= x9(1) xor (x9(0) and x9(3)) xor (x9(3) and x9(4)) xor (x9(0) and x9(5)) xor
(x9(2) and x9(6)) xor (x9(3) and x9(6)) xor (x9(5) and x9(6)) xor (x9(4) and x9(7)) xor
(x9(5) and x9(7)) xor (x9(6) and x9(7)) xor x9(8) xor (x9(0) and x9(8)) xor
'1';
y9(3) <= x9(0) xor (x9(1) and x9(2)) xor (x9(0) and x9(3)) xor (x9(2) and x9(4)) xor
x9(5) xor (x9(0) and x9(6)) xor (x9(1) and x9(6)) xor (x9(4) and x9(7)) xor
(x9(0) and x9(8)) xor (x9(1) and x9(8)) xor (x9(7) and x9(8));
y9(4) <= (x9(0) and x9(1)) xor (x9(1) and x9(3)) xor x9(4) xor (x9(0) and x9(5)) xor
(x9(3) and x9(6)) xor (x9(0) and x9(7)) xor (x9(6) and x9(7)) xor (x9(1) and x9(8)) xor
(x9(2) and x9(8)) xor (x9(3) and x9(8));
y9(5) <= x9(2) xor (x9(1) and x9(4)) xor (x9(4) and x9(5)) xor (x9(0) and x9(6)) xor
(x9(1) and x9(6)) xor (x9(3) and x9(7)) xor (x9(4) and x9(7)) xor (x9(6) and x9(7)) xor
(x9(5) and x9(8)) xor (x9(6) and x9(8)) xor (x9(7) and x9(8)) xor '1';
y9(6) <= x9(0) xor (x9(2) and x9(3)) xor (x9(1) and x9(5)) xor (x9(2) and x9(5)) xor
(x9(4) and x9(5)) xor (x9(3) and x9(6)) xor (x9(4) and x9(6)) xor (x9(5) and x9(6)) xor
x9(7) xor (x9(1) and x9(8)) xor (x9(3) and x9(8)) xor (x9(5) and x9(8)) xor
(x9(7) and x9(8));
y9(7) <= (x9(0) and x9(1)) xor (x9(0) and x9(2)) xor (x9(1) and x9(2)) xor x9(3) xor
(x9(0) and x9(3)) xor (x9(2) and x9(3)) xor (x9(4) and x9(5)) xor (x9(2) and x9(6)) xor
(x9(3) and x9(6)) xor (x9(2) and x9(7)) xor (x9(5) and x9(7)) xor x9(8) xor
'1';
y9(8) <= (x9(0) and x9(1)) xor x9(2) xor (x9(1) and x9(2)) xor (x9(3) and x9(4)) xor
(x9(1) and x9(5)) xor (x9(2) and x9(5)) xor (x9(1) and x9(6)) xor (x9(4) and x9(6)) xor
x9(7) xor (x9(2) and x9(8)) xor (x9(3) and x9(8));
--S9
end phy;
/nfcc/trunk/kasumi/key.lst
0,0 → 1,2
0x0011223344556677
0x8899aabbccddeeff
/nfcc/trunk/kasumi/kasumi.c
0,0 → 1,143
#include <stdio.h>
#include <string.h>
#include "genpat.h"
 
char *inttostr(entier)
int entier;
{
char *str;
str = (char *) mbkalloc (32 * sizeof (char));
sprintf (str, "%d",entier);
return(str);
}
/*------------------------------*/
/* end of the description */
/*------------------------------*/
 
main (int argc, char *argv[])
{
int i,c;
int ks,ps;
FILE *f1, *f2;
char *fname1 = "key.lst";
char *fname2 = "pt.lst";
char key[0xff][0x4f];
char fpt[0xff][0x4f];
 
/* remember argc start from 1 not zero and command line is the first array */
if (argc > 1 ) {
if (argc == 3) {
fname1 = argv[2]; /* key */
fname2 = argv[1]; /* plain text*/
printf("Using plain-text (%s) key (%s)\n", fname2, fname1);
} else {
printf("Usage %s: plain-text key\n", argv[0]);
return 0;
}
}
 
if(fname1 && (f1 = fopen(fname1, "rt"))) {
i = 0;
while(fgets(key[i],sizeof(key[i]),f1) != NULL) {
c = strlen(key[i]);
if(key[i][c-1] == '\n') key[i][c-1] = '\0';
i++;
}
fclose (f1);
} else {
fclose (f1);
}
 
ks = i;
 
if(fname2 && (f2 = fopen(fname2, "rt"))) {
i = 0;
while(fgets(fpt[i],sizeof(fpt[i]),f2) != NULL) {
c = strlen(fpt[i]);
if(fpt[i][c-1] == '\n') fpt[i][c-1] = '\0';
i++;
}
fclose (f2);
} else {
fclose (f2);
}
 
ps = i;
 
DEF_GENPAT("kasumi");
SETTUNIT("ns");
 
/* interface */
DECLAR ("clk", ":1", "B", IN , "" , "" );
DECLAR ("rst", ":1", "B", IN , "" , "" );
DECLAR ("ldpt",":1", "B", IN , "" , "" );
DECLAR ( "pt", ":1", "X", IN , "31 downto 0", "" );
DECLAR ("ldk", ":1", "B", IN , "" , "" );
DECLAR ("key", ":1", "X", IN , "63 downto 0", "" );
DECLAR ( "v", ":1", "B", OUT, "" , "" );
DECLAR ( "ct", ":1", "X", OUT, "63 downto 0", "" );
//DECLAR ( "rnd_prb", ":2", "X", OUT, " 1 downto 0", "" );
//DECLAR ( "c3b_rst_prb", ":1", "B", OUT, "" , "" );
//DECLAR ( "L_prb", ":2", "X", OUT, "31 downto 0", "" );
//DECLAR ( "R_prb", ":2", "X", OUT, "31 downto 0", "" );
//DECLAR ( "ikey_prb", ":2", "X", OUT, "15 downto 0", "" );
//DECLAR ( "FL_prb", ":2", "X", OUT, "31 downto 0", "" );
//DECLAR ( "FO_prb", ":2", "X", OUT, "15 downto 0", "" );
//DECLAR ( "FI_prb", ":2", "X", OUT, "15 downto 0", "" );
//DECLAR ("even_prb",":1", "B", OUT, "" , "" );
//DECLAR ( "st_prb", ":2", "X", OUT, " 3 downto 0", "" );
DECLAR ("vss", ":1", "B", IN , "" , "" );
DECLAR ("vdd", ":1", "B", IN , "" , "" );
 
AFFECT ("0", "vss", "0b0");
AFFECT ("0", "vdd", "0b1");
 
AFFECT ( "0", "pt", "0x0000");
AFFECT ( "0", "key", "0x0000000000000000");
AFFECT ( "0", "rst", "0b1");
AFFECT ( "0","ldpt", "0b0");
AFFECT ( "0", "ldk", "0b0");
AFFECT ( "0", "clk", "0b0");
AFFECT ("+50", "clk", "0b1");
AFFECT ("+50", "clk", "0b0");
AFFECT ( "+0", "rst", "0b0");
AFFECT ( "+0","ldpt", "0b1");
AFFECT ( "+0", "ldk", "0b1");
 
for (i=0; i < ps; i++)
{
AFFECT ( "+0", "pt", fpt[i]);
AFFECT ( "+0", "key", key[i]);
AFFECT ("+50", "clk", "0b1" );
AFFECT ("+50", "clk", "0b0" );
}
 
AFFECT ( "+0","ldpt", "0b0");
AFFECT ( "+0", "ldk", "0b0");
AFFECT ( "+0", "pt", "0x0000");
AFFECT ( "+0", "key", "0x0000000000000000");
AFFECT ("+50", "clk", "0b1" );
AFFECT ("+50", "clk", "0b0" );
/*
for (i=0; i < ks; i++)
{
AFFECT ( "+0", "key", key[i]);
AFFECT ("+50", "clk", "0b1" );
AFFECT ("+50", "clk", "0b0" );
}
 
AFFECT ("+50", "clk", "0b1" );
AFFECT ("+50", "clk", "0b0" );
AFFECT ( "+0", "key", "0x0000");
*/
for (i=0; i < 0x50; i++)
{
AFFECT ("+50", "clk", "0b1" );
AFFECT ("+50", "clk", "0b0" );
}
 
AFFECT ("+50", "clk", "0b1");
 
SAV_GENPAT ();
}
 
/nfcc/trunk/kasumi/sbox.c
0,0 → 1,43
#include <stdio.h>
#include "genpat.h"
 
char *inttostr(entier)
int entier;
{
char *str;
str = (char *) mbkalloc (32 * sizeof (char));
sprintf (str, "%d",entier);
return(str);
}
/*------------------------------*/
/* end of the description */
/*------------------------------*/
 
main ()
{
int i;
int cur_vect = 0;
 
DEF_GENPAT("sbox");
SETTUNIT("ns");
 
/* interface */
DECLAR ( "x" , ":2", "X", IN , "8 downto 0", "" );
DECLAR ("y7" , ":2", "X", OUT, "6 downto 0", "" );
DECLAR ("y9" , ":2", "X", OUT, "8 downto 0", "" );
DECLAR ("vss", ":1", "B", IN , "" , "" );
DECLAR ("vdd", ":1", "B", IN , "" , "" );
 
AFFECT ("0", "vss", "0b0");
AFFECT ("0", "vdd", "0b1");
AFFECT ("0", "x", "0b00000000");
 
for (i=1; i<0x200; i++)
{
AFFECT ("+10", "x", inttostr(i) );
cur_vect++;
}
 
SAV_GENPAT ();
}
 
/nfcc/trunk/kasumi/Makefile
0,0 → 1,119
#- ------------------------------------------------------------------------
#- Copyright (C) 2010 Arif Endro Nugroho
#- All rights reserved.
#-
#- Redistribution and use in source and binary forms, with or without
#- modification, are permitted provided that the following conditions
#- are met:
#-
#- 1. Redistributions of source code must retain the above copyright
#- notice, this list of conditions and the following disclaimer.
#- 2. Redistributions in binary form must reproduce the above copyright
#- notice, this list of conditions and the following disclaimer in the
#- documentation and/or other materials provided with the distribution.
#-
#- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
#- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
#- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
#- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
#- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
#- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
#- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
#- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
#- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
#- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
#- POSSIBILITY OF SUCH DAMAGE.
#-
#- End Of License.
#- ------------------------------------------------------------------------
#
# Need to FLATTENING the design before OCP and NERO
# Use x2y vst vst <source> <result>
# then flatlo -r <source> <result> # source is a result from x2y
# this two sequence will remove most warning/error message when
# performing LOON on the netlist.
#
# BOOM will optimize the logic
# BOOG will optimize/convert the logic into netlist
# LOON will optimize the netlist (this will report area/timing)
#
# VST is a circuit netlist file
# AP is a circuit placement file (OCP/NERO create this file)
# VBE is alliance VHDL Behavioral Description file
 
VASYFLAGS = -V -B -I vhdl -a -p -o
BOOMFLAGS = -VP
BOOGFLAGS =
LOONFLAGS =
OCPFLAGS = -v
NEROFLAGS = -V -G -6 -p
DRUCFLAGS =
S2RFLAGS = -v
OCP = ocp
NERO = nero
DRUC = druc
S2R = s2r
VASY = vasy
BOOM = boom
GENPAT = genpat -v
BOOG = boog
LOON = loon
RM = /bin/rm -vf
X2Y = x2y
FLATLO = flatlo
X2YFLAGS = vst vst
FLATLOFLAGS = -r
TOUCH = touch
 
# Set-up TARGET variable respectively
%.ap: TARGET = $(subst .ap,, $@)
%.pat: TARGET = $(subst .pat,, $@)
%.cif: TARGET = $(subst .cif,, $@)
%.vst: TARGET = $(subst .vst,, $@)
%.flt: TARGET = $(subst .flt,, $@)
%.sflt: TARGET = $(subst .sflt,, $@)
%.flatten: TARGET = $(subst .flatten,, $@)
 
all:
 
%.vbe: %.vhdl
@$(VASY) $(VASYFLAGS) $<
 
%.vst: %.vbe
@$(BOOM) $(BOOMFLAGS) $(TARGET) $(TARGET)_o
@$(BOOG) $(BOOGFLAGS) $(TARGET)_o
@$(LOON) $(LOONFLAGS) $(TARGET)_o $(TARGET)
-$(RM) $(TARGET)_o.*
 
%.sflt: %.vbe
# @$(BOOM) $(BOOMFLAGS) $(TARGET)_model $(TARGET)_model_o
@$(BOOG) $(BOOGFLAGS) $(TARGET)_model
# @$(BOOG) $(BOOGFLAGS) $(TARGET)_model_o
# @$(LOON) $(LOONFLAGS) $(TARGET)_model_o $(TARGET)_model
-$(RM) $(TARGET)_model_o.*
@$(X2Y) $(X2YFLAGS) $(TARGET) $(TARGET)_m
@$(FLATLO) $(FLATLOFLAGS) $(TARGET)_m $(TARGET)
# @$(FLATLO) $(FLATLOFLAGS) $(TARGET)_m $(TARGET)_o
# @$(LOON) $(LOONFLAGS) $(TARGET)_o $(TARGET)
-$(RM) $(TARGET){_o,m}.*
@$(TOUCH) $@
 
%.flt: %.vbe
@$(BOOM) $(BOOMFLAGS) $(TARGET)_model $(TARGET)_model_o
@$(BOOG) $(BOOGFLAGS) $(TARGET)_model_o
@$(LOON) $(LOONFLAGS) $(TARGET)_model_o $(TARGET)_model
-$(RM) $(TARGET)_model_o.*
@$(X2Y) $(X2YFLAGS) $(TARGET) $(TARGET)_m
@$(FLATLO) $(FLATLOFLAGS) $(TARGET)_m $(TARGET)_o
@$(LOON) $(LOONFLAGS) $(TARGET)_o $(TARGET)
-$(RM) $(TARGET){_o,m}.*
@$(TOUCH) $@
 
%.flatten: %.vst
@$(X2Y) $(X2YFLAGS) $(TARGET) $(TARGET)_m
@$(FLATLO) $(FLATLOFLAGS) $(TARGET)_m $(TARGET)_o
@$(LOON) $(LOONFLAGS) $(TARGET)_o $(TARGET)
-$(RM) $(TARGET){_o,m}.*
 
clean:
@rm -vf *.dat *.gpl *.vhd *.vbe *.boom *.vst *.xsc *.ap *.cif *.drc done.* *.flt *.sflt *_syn.pat *_sim.pat
/nfcc/trunk/README
0,0 → 1,5
Nugroho Free Crypto Cores (NFCC)
 
* support rijndael, camellia, and kasumi algorithm.
 
 

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