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URL https://opencores.org/ocsvn/noekeoncore/noekeoncore/trunk

Subversion Repositories noekeoncore

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Rev 3 → Rev 2

/noekeoncore/trunk/rtl/tb_gamma.vhd
0,0 → 1,105
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_gamma IS
END tb_gamma;
ARCHITECTURE behavior OF tb_gamma IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT gamma
PORT(
clk : IN std_logic;
a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
 
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: gamma PORT MAP (
clk => clk,
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + clk_period;
 
a_0_in <= X"C5B032AD";
a_1_in <= X"3E48160D";
a_2_in <= X"8C9A3EF5";
a_3_in <= X"AF2DFC9F";
 
wait for clk_period;
 
a_0_in <= X"AB2DED92";
a_1_in <= X"5C481D1D";
a_2_in <= X"8407F1CF";
a_3_in <= X"C9B824A8";
 
-- insert stimulus here
 
wait;
end process;
 
END;
/noekeoncore/trunk/rtl/tb_pi_1.vhd
0,0 → 1,75
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_pi_1 IS
END tb_pi_1;
ARCHITECTURE behavior OF tb_pi_1 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT pi_1
PORT(
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
 
--Inputs
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
 
--Outputs
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: pi_1 PORT MAP (
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
 
 
 
-- Stimulus process
stim_proc: process
begin
a_1_in <= X"a1abab3c";
a_2_in <= X"0232b23f";
a_3_in <= X"f000abbb";
wait;
end process;
 
END;
/noekeoncore/trunk/rtl/tb_pi_2.vhd
0,0 → 1,73
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_pi_2 IS
END tb_pi_2;
ARCHITECTURE behavior OF tb_pi_2 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT pi_2
PORT(
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
 
--Inputs
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
 
--Outputs
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: pi_2 PORT MAP (
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
 
-- Stimulus process
stim_proc: process
begin
a_1_in <= X"43575679";
a_2_in <= X"465647e0";
a_3_in <= X"c002aeef";
wait;
end process;
 
END;
/noekeoncore/trunk/rtl/tb_round_f.vhd
0,0 → 1,121
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_round_f IS
END tb_round_f;
ARCHITECTURE behavior OF tb_round_f IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT round_f
PORT(
clk : IN std_logic;
rc_in : IN std_logic_vector(31 downto 0);
a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
k_0_in : IN std_logic_vector(31 downto 0);
k_1_in : IN std_logic_vector(31 downto 0);
k_2_in : IN std_logic_vector(31 downto 0);
k_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal rc_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_3_in : std_logic_vector(31 downto 0) := (others => '0');
 
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: round_f PORT MAP (
clk => clk,
rc_in => rc_in,
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
k_0_in => k_0_in,
k_1_in => k_1_in,
k_2_in => k_2_in,
k_3_in => k_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
 
wait for clk_period*10;
rc_in <= X"00000080";
a_0_in <= X"61396c93";
a_1_in <= X"637434b8";
a_2_in <= X"fc6559a9";
a_3_in <= X"5b643f2c";
 
k_0_in <= X"1c1c1c1c";
k_1_in <= X"1c1c1c1c";
k_2_in <= X"1c1c1c1c";
k_3_in <= X"1c1c1c1c";
 
wait;
end process;
 
END;
/noekeoncore/trunk/rtl/tb_rc_gen.vhd
0,0 → 1,88
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_rc_gen IS
END tb_rc_gen;
ARCHITECTURE behavior OF tb_rc_gen IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT rc_gen
PORT(
clk : IN std_logic;
rst : IN std_logic;
enc : IN std_logic;
rc_out : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal enc : std_logic := '0';
 
--Outputs
signal rc_out : std_logic_vector(7 downto 0);
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: rc_gen PORT MAP (
clk => clk,
rst => rst,
enc => enc,
rc_out => rc_out
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + clk_period;
rst <= '1';
enc <= '0';
wait for clk_period;
rst <= '0';
wait for clk_period*15;
rst <= '1';
enc <= '1';
wait for clk_period;
rst <= '0';
 
-- insert stimulus here
 
wait;
end process;
 
END;
/noekeoncore/trunk/rtl/tb_noekeon.vhd
0,0 → 1,169
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_noekeon IS
END tb_noekeon;
ARCHITECTURE behavior OF tb_noekeon IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT noekeon
PORT(
clk : IN std_logic;
rst : IN std_logic;
enc : IN std_logic;
a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
k_0_in : IN std_logic_vector(31 downto 0);
k_1_in : IN std_logic_vector(31 downto 0);
k_2_in : IN std_logic_vector(31 downto 0);
k_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal enc : std_logic := '0';
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_3_in : std_logic_vector(31 downto 0) := (others => '0');
 
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: noekeon PORT MAP (
clk => clk,
rst => rst,
enc => enc,
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
k_0_in => k_0_in,
k_1_in => k_1_in,
k_2_in => k_2_in,
k_3_in => k_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + clk_period;
rst <= '1';
enc <= '0';
a_0_in <= X"2a78421b";
a_1_in <= X"87c7d092";
a_2_in <= X"4f26113f";
a_3_in <= X"1d1349b2";
 
k_0_in <= X"b1656851";
k_1_in <= X"699e29fa";
k_2_in <= X"24b70148";
k_3_in <= X"503d2dfc";
wait for clk_period;
rst <= '0';
 
wait for clk_period*15 + clk_period/2;
 
assert a_0_out = X"e2f687e0"
report "ENCRYPT ERROR (a_0)" severity FAILURE;
 
assert a_1_out = X"7b75660f"
report "ENCRYPT ERROR (a_1)" severity FAILURE;
 
assert a_2_out = X"fc372233"
report "ENCRYPT ERROR (a_2)" severity FAILURE;
 
assert a_3_out = X"bc47532c"
report "ENCRYPT ERROR (a_3)" severity FAILURE;
 
wait for clk_period + clk_period/2;
rst <= '1';
enc <= '1';
a_0_in <= X"e2f687e0";
a_1_in <= X"7b75660f";
a_2_in <= X"fc372233";
a_3_in <= X"bc47532c";
 
k_0_in <= X"b1656851";
k_1_in <= X"699e29fa";
k_2_in <= X"24b70148";
k_3_in <= X"503d2dfc";
wait for clk_period;
rst <= '0';
 
wait for clk_period*15 + clk_period/2;
 
assert a_0_out = X"2a78421b"
report "DECRYPT ERROR (a_0)" severity FAILURE;
 
assert a_1_out = X"87c7d092"
report "DECRYPT ERROR (a_1)" severity FAILURE;
 
assert a_2_out = X"4f26113f"
report "DECRYPT ERROR (a_2)" severity FAILURE;
 
assert a_3_out = X"1d1349b2"
report "DECRYPT ERROR (a_3)" severity FAILURE;
 
wait;
end process;
 
END;
/noekeoncore/trunk/rtl/tb_theta.vhd
0,0 → 1,137
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY tb_theta IS
END tb_theta;
ARCHITECTURE behavior OF tb_theta IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT theta
PORT(
clk : IN std_logic;
a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
k_0_in : IN std_logic_vector(31 downto 0);
k_1_in : IN std_logic_vector(31 downto 0);
k_2_in : IN std_logic_vector(31 downto 0);
k_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_3_in : std_logic_vector(31 downto 0) := (others => '0');
 
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: theta PORT MAP (
clk => clk,
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
k_0_in => k_0_in,
k_1_in => k_1_in,
k_2_in => k_2_in,
k_3_in => k_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + clk_period;
 
a_0_in <= X"61396c13";
a_1_in <= X"637434b8";
a_2_in <= X"fc6559a9";
a_3_in <= X"5b643f2c";
k_0_in <= X"4ED2552D";
k_1_in <= X"1AE69D5D";
k_2_in <= X"C9B75C29";
k_3_in <= X"0C49E157";
 
wait for clk_period;
 
k_0_in <= (others => '0');
k_1_in <= (others => '0');
k_2_in <= (others => '0');
k_3_in <= (others => '0');
 
a_0_in <= X"4ED2552D";
a_1_in <= X"1AE69D5D";
a_2_in <= X"C9B75C29";
a_3_in <= X"0C49E157";
wait for clk_period;
 
a_0_in <= X"200d6ff9";
a_1_in <= X"02667af7";
a_2_in <= X"3a345347";
a_3_in <= X"2cd90d69";
 
k_0_in <= X"fd178c4d";
k_1_in <= X"fc0df5d7";
k_2_in <= X"7a728549";
k_3_in <= X"eaa289dd";
wait;
end process;
 
END;

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