OpenCores
URL https://opencores.org/ocsvn/noekeoncore/noekeoncore/trunk

Subversion Repositories noekeoncore

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/noekeoncore/trunk/rtl/t_m_1.vhd
0,0 → 1,57
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity t_m_1 is
port(clk : in std_logic;
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end t_m_1;
 
architecture Behavioral of t_m_1 is
 
signal tmp_0_s : std_logic_vector(31 downto 0);
signal tmp_1_s : std_logic_vector(31 downto 0);
signal tmp_2_s : std_logic_vector(31 downto 0);
signal tmp_3_s : std_logic_vector(31 downto 0);
 
begin
 
-- temp = a[0]^a[2];
-- temp ^= temp>>>8 ^ temp<<<8;
-- a[1] ^= temp;
-- a[3] ^= temp;
 
--t: 9d5c35ba
--t_rol: 5c35ba9d
--t_ror: ba9d5c35
 
tmp_0_s <= a_0_in xor a_2_in;
tmp_1_s <= tmp_0_s(23 downto 0) & tmp_0_s(31 downto 24);
tmp_2_s <= tmp_0_s(7 downto 0) & tmp_0_s(31 downto 8);
tmp_3_s <= tmp_0_s xor tmp_1_s xor tmp_2_s;
 
a_1_out <= a_1_in xor tmp_3_s;
a_3_out <= a_3_in xor tmp_3_s;
end Behavioral;
 
/noekeoncore/trunk/rtl/t_m_2.vhd
0,0 → 1,51
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity t_m_2 is
port(clk : in std_logic;
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end t_m_2;
 
architecture Behavioral of t_m_2 is
 
begin
 
a_0_out <= a_0_in xor k_0_in;
a_1_out <= a_1_in xor k_1_in;
a_2_out <= a_2_in xor k_2_in;
a_3_out <= a_3_in xor k_3_in;
-- a[0] ^= k[0]; tmp_4_s
-- a[1] ^= k[1]; tmp_5_s
-- a[2] ^= k[2]; tmp_6_s
-- a[3] ^= k[3]; tmp_7_s
 
end Behavioral;
 
/noekeoncore/trunk/rtl/t_m_3.vhd
0,0 → 1,55
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity t_m_3 is
port(clk : in std_logic;
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0));
end t_m_3;
 
architecture Behavioral of t_m_3 is
 
signal tmp_0_s : std_logic_vector(31 downto 0);
signal tmp_1_s : std_logic_vector(31 downto 0);
signal tmp_2_s : std_logic_vector(31 downto 0);
signal tmp_3_s : std_logic_vector(31 downto 0);
 
begin
 
-- temp = a[1]^a[3];
-- temp ^= temp>>>8 ^ temp<<<8;
 
-- a[0] ^= temp;
-- a[2] ^= temp;
 
tmp_0_s <= a_1_in xor a_3_in;
tmp_1_s <= tmp_0_s(23 downto 0) & tmp_0_s(31 downto 24);
tmp_2_s <= tmp_0_s(7 downto 0) & tmp_0_s(31 downto 8);
tmp_3_s <= tmp_0_s xor tmp_1_s xor tmp_2_s;
 
a_0_out <= a_0_in xor tmp_3_s;
a_2_out <= a_2_in xor tmp_3_s;
end Behavioral;
 
 
/noekeoncore/trunk/rtl/theta.vhd
0,0 → 1,113
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity theta is
port(clk : in std_logic;
 
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
 
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end theta;
 
architecture Behavioral of theta is
 
component t_m_1 is
port(clk : in std_logic;
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
 
component t_m_2 is
port(clk : in std_logic;
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
 
component t_m_3 is
port(clk : in std_logic;
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0));
end component;
 
signal a_1_0_s : std_logic_vector(31 downto 0);
signal a_3_0_s : std_logic_vector(31 downto 0);
 
signal tmp_0_s : std_logic_vector(31 downto 0);
signal tmp_1_s : std_logic_vector(31 downto 0);
signal tmp_2_s : std_logic_vector(31 downto 0);
signal tmp_3_s : std_logic_vector(31 downto 0);
begin
 
T_M_1_0 : t_m_1 port map (clk, a_0_in, a_1_in, a_2_in, a_3_in, a_1_0_s, a_3_0_s);
T_M_2_0 : t_m_2 port map (clk, a_0_in, a_1_0_s, a_2_in, a_3_0_s, k_0_in, k_1_in, k_2_in, k_3_in, tmp_0_s, tmp_1_s, tmp_2_s, tmp_3_s);
T_M_1_1 : t_m_3 port map (clk, tmp_0_s, tmp_1_s, tmp_2_s, tmp_3_s, a_0_out, a_2_out);
 
a_1_out <= tmp_1_s;
a_3_out <= tmp_3_s;
 
--Theta(k,a){
-- temp = a[0]^a[2]; tmp_0_s
-- temp ^= temp>>>8 ^ temp<<<8; tmp_1_s
-- a[1] ^= temp; tmp_2_s
-- a[3] ^= temp; tmp_3_s
 
-- a[0] ^= k[0]; tmp_4_s
-- a[1] ^= k[1]; tmp_5_s
-- a[2] ^= k[2]; tmp_6_s
-- a[3] ^= k[3]; tmp_7_s
 
-- temp = a[1]^a[3];
-- temp ^= temp>>>8 ^ temp<<<8;
 
-- a[0] ^= temp;
-- a[2] ^= temp;
--}
 
end Behavioral;
 
/noekeoncore/trunk/rtl/output_trans.vhd
0,0 → 1,85
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity output_trans is
port(clk : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end output_trans;
 
architecture Behavioral of output_trans is
 
component theta is
port(clk : in std_logic;
 
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
 
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
 
signal a_0_s : std_logic_vector(31 downto 0);
signal a_0_in_s : std_logic_vector(31 downto 0);
signal a_0_out_s : std_logic_vector(31 downto 0);
begin
 
a_0_s <= a_0_in xor rc_in;
a_0_in_s <= a_0_s when enc = '0' else a_0_in;
THETA_0 : theta port map (clk,
a_0_in_s,
a_1_in,
a_2_in,
a_3_in,
k_0_in,
k_1_in,
k_2_in,
k_3_in,
a_0_out_s,
a_1_out,
a_2_out,
a_3_out);
 
a_0_out <= (a_0_out_s xor rc_in) when enc = '1' else a_0_out_s;
 
end Behavioral;
 
/noekeoncore/trunk/rtl/tb_gamma.vhd
0,0 → 1,105
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_gamma IS
END tb_gamma;
ARCHITECTURE behavior OF tb_gamma IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT gamma
PORT(
clk : IN std_logic;
a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
 
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: gamma PORT MAP (
clk => clk,
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + clk_period;
 
a_0_in <= X"C5B032AD";
a_1_in <= X"3E48160D";
a_2_in <= X"8C9A3EF5";
a_3_in <= X"AF2DFC9F";
 
wait for clk_period;
 
a_0_in <= X"AB2DED92";
a_1_in <= X"5C481D1D";
a_2_in <= X"8407F1CF";
a_3_in <= X"C9B824A8";
 
-- insert stimulus here
 
wait;
end process;
 
END;
/noekeoncore/trunk/rtl/tb_pi_1.vhd
0,0 → 1,75
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_pi_1 IS
END tb_pi_1;
ARCHITECTURE behavior OF tb_pi_1 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT pi_1
PORT(
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
 
--Inputs
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
 
--Outputs
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: pi_1 PORT MAP (
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
 
 
 
-- Stimulus process
stim_proc: process
begin
a_1_in <= X"a1abab3c";
a_2_in <= X"0232b23f";
a_3_in <= X"f000abbb";
wait;
end process;
 
END;
/noekeoncore/trunk/rtl/tb_pi_2.vhd
0,0 → 1,73
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_pi_2 IS
END tb_pi_2;
ARCHITECTURE behavior OF tb_pi_2 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT pi_2
PORT(
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
 
--Inputs
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
 
--Outputs
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: pi_2 PORT MAP (
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
 
-- Stimulus process
stim_proc: process
begin
a_1_in <= X"43575679";
a_2_in <= X"465647e0";
a_3_in <= X"c002aeef";
wait;
end process;
 
END;
/noekeoncore/trunk/rtl/tb_round_f.vhd
0,0 → 1,121
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_round_f IS
END tb_round_f;
ARCHITECTURE behavior OF tb_round_f IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT round_f
PORT(
clk : IN std_logic;
rc_in : IN std_logic_vector(31 downto 0);
a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
k_0_in : IN std_logic_vector(31 downto 0);
k_1_in : IN std_logic_vector(31 downto 0);
k_2_in : IN std_logic_vector(31 downto 0);
k_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal rc_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_3_in : std_logic_vector(31 downto 0) := (others => '0');
 
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: round_f PORT MAP (
clk => clk,
rc_in => rc_in,
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
k_0_in => k_0_in,
k_1_in => k_1_in,
k_2_in => k_2_in,
k_3_in => k_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
 
wait for clk_period*10;
rc_in <= X"00000080";
a_0_in <= X"61396c93";
a_1_in <= X"637434b8";
a_2_in <= X"fc6559a9";
a_3_in <= X"5b643f2c";
 
k_0_in <= X"1c1c1c1c";
k_1_in <= X"1c1c1c1c";
k_2_in <= X"1c1c1c1c";
k_3_in <= X"1c1c1c1c";
 
wait;
end process;
 
END;
/noekeoncore/trunk/rtl/gamma.vhd
0,0 → 1,120
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity gamma is
port(clk : in std_logic;
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end gamma;
 
architecture Behavioral of gamma is
 
signal a_0_tmp_s : std_logic_vector(31 downto 0);
signal a_1_tmp_s : std_logic_vector(31 downto 0);
signal a_2_tmp_s : std_logic_vector(31 downto 0);
signal a_3_tmp_s : std_logic_vector(31 downto 0);
signal a_1_1_tmp_s : std_logic_vector(31 downto 0);
signal a_0_1_tmp_s : std_logic_vector(31 downto 0);
signal a_0_2_tmp_s : std_logic_vector(31 downto 0);
 
component g_m_1 is
port(clk : in std_logic;
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0));
end component;
 
component g_m_2 is
port(clk : in std_logic;
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0));
end component;
 
component g_m_3 is
port(clk : in std_logic;
a_0_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
 
component g_m_4 is
port(clk : in std_logic;
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0));
end component;
 
component g_m_5 is
port(clk : in std_logic;
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0));
end component;
 
component g_m_6 is
port(clk : in std_logic;
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0));
end component;
 
begin
 
G_M_1_0 : g_m_1 port map (clk, a_1_in, a_2_in, a_3_in, a_1_tmp_s);
G_M_2_0 : g_m_2 port map (clk, a_0_in, a_1_tmp_s, a_2_in, a_0_tmp_s);
G_M_3_0 : g_m_3 port map (clk, a_0_tmp_s, a_3_in, a_0_1_tmp_s, a_3_tmp_s);
G_M_4_0 : g_m_4 port map (clk, a_0_1_tmp_s, a_1_tmp_s, a_2_in, a_3_tmp_s, a_2_tmp_s);
G_M_5_0 : g_m_5 port map (clk, a_1_tmp_s, a_2_tmp_s, a_3_tmp_s, a_1_1_tmp_s);
G_M_6_0 : g_m_6 port map (clk, a_0_1_tmp_s, a_1_1_tmp_s, a_2_tmp_s, a_0_2_tmp_s);
 
a_3_out <= a_3_tmp_s;
a_2_out <= a_2_tmp_s;
a_1_out <= a_1_1_tmp_s;
a_0_out <= a_0_2_tmp_s;
--Gamma(a){
--a[1] ^= ~a[3]&~a[2];
--a[0] ^= a[2]& a[1];
--tmp = a[3];
--a[3] = a[0];
--a[0] = tmp;
--a[2] ^= a[0]^a[1]^a[3];
--a[1] ^= ~a[3]&~a[2];
--a[0] ^= a[2]& a[1];
--}
 
 
end Behavioral;
 
/noekeoncore/trunk/rtl/g_m_1.vhd
0,0 → 1,35
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity g_m_1 is
port(clk : in std_logic;
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0));
end g_m_1;
 
architecture Behavioral of g_m_1 is
 
begin
 
a_1_out <= a_1_in xor (not(a_3_in) and not(a_2_in));
 
end Behavioral;
 
/noekeoncore/trunk/rtl/tb_rc_gen.vhd
0,0 → 1,88
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_rc_gen IS
END tb_rc_gen;
ARCHITECTURE behavior OF tb_rc_gen IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT rc_gen
PORT(
clk : IN std_logic;
rst : IN std_logic;
enc : IN std_logic;
rc_out : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal enc : std_logic := '0';
 
--Outputs
signal rc_out : std_logic_vector(7 downto 0);
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: rc_gen PORT MAP (
clk => clk,
rst => rst,
enc => enc,
rc_out => rc_out
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + clk_period;
rst <= '1';
enc <= '0';
wait for clk_period;
rst <= '0';
wait for clk_period*15;
rst <= '1';
enc <= '1';
wait for clk_period;
rst <= '0';
 
-- insert stimulus here
 
wait;
end process;
 
END;
/noekeoncore/trunk/rtl/g_m_2.vhd
0,0 → 1,35
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity g_m_2 is
port(clk : in std_logic;
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0));
end g_m_2;
 
architecture Behavioral of g_m_2 is
 
begin
 
a_0_out <= a_0_in xor (a_2_in and a_1_in);
 
end Behavioral;
 
/noekeoncore/trunk/rtl/tb_noekeon.vhd
0,0 → 1,169
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_noekeon IS
END tb_noekeon;
ARCHITECTURE behavior OF tb_noekeon IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT noekeon
PORT(
clk : IN std_logic;
rst : IN std_logic;
enc : IN std_logic;
a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
k_0_in : IN std_logic_vector(31 downto 0);
k_1_in : IN std_logic_vector(31 downto 0);
k_2_in : IN std_logic_vector(31 downto 0);
k_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal enc : std_logic := '0';
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_3_in : std_logic_vector(31 downto 0) := (others => '0');
 
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: noekeon PORT MAP (
clk => clk,
rst => rst,
enc => enc,
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
k_0_in => k_0_in,
k_1_in => k_1_in,
k_2_in => k_2_in,
k_3_in => k_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + clk_period;
rst <= '1';
enc <= '0';
a_0_in <= X"2a78421b";
a_1_in <= X"87c7d092";
a_2_in <= X"4f26113f";
a_3_in <= X"1d1349b2";
 
k_0_in <= X"b1656851";
k_1_in <= X"699e29fa";
k_2_in <= X"24b70148";
k_3_in <= X"503d2dfc";
wait for clk_period;
rst <= '0';
 
wait for clk_period*15 + clk_period/2;
 
assert a_0_out = X"e2f687e0"
report "ENCRYPT ERROR (a_0)" severity FAILURE;
 
assert a_1_out = X"7b75660f"
report "ENCRYPT ERROR (a_1)" severity FAILURE;
 
assert a_2_out = X"fc372233"
report "ENCRYPT ERROR (a_2)" severity FAILURE;
 
assert a_3_out = X"bc47532c"
report "ENCRYPT ERROR (a_3)" severity FAILURE;
 
wait for clk_period + clk_period/2;
rst <= '1';
enc <= '1';
a_0_in <= X"e2f687e0";
a_1_in <= X"7b75660f";
a_2_in <= X"fc372233";
a_3_in <= X"bc47532c";
 
k_0_in <= X"b1656851";
k_1_in <= X"699e29fa";
k_2_in <= X"24b70148";
k_3_in <= X"503d2dfc";
wait for clk_period;
rst <= '0';
 
wait for clk_period*15 + clk_period/2;
 
assert a_0_out = X"2a78421b"
report "DECRYPT ERROR (a_0)" severity FAILURE;
 
assert a_1_out = X"87c7d092"
report "DECRYPT ERROR (a_1)" severity FAILURE;
 
assert a_2_out = X"4f26113f"
report "DECRYPT ERROR (a_2)" severity FAILURE;
 
assert a_3_out = X"1d1349b2"
report "DECRYPT ERROR (a_3)" severity FAILURE;
 
wait;
end process;
 
END;
/noekeoncore/trunk/rtl/g_m_3.vhd
0,0 → 1,36
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity g_m_3 is
port(clk : in std_logic;
a_0_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end g_m_3;
 
architecture Behavioral of g_m_3 is
 
begin
 
a_0_out <= a_3_in;
a_3_out <= a_0_in;
 
end Behavioral;
 
/noekeoncore/trunk/rtl/g_m_4.vhd
0,0 → 1,36
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity g_m_4 is
port(clk : in std_logic;
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0));
end g_m_4;
 
architecture Behavioral of g_m_4 is
 
begin
 
a_2_out <= a_0_in xor a_1_in xor a_2_in xor a_3_in;
 
end Behavioral;
 
/noekeoncore/trunk/rtl/g_m_5.vhd
0,0 → 1,44
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity g_m_5 is
port(clk : in std_logic;
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0));
end g_m_5;
 
architecture Behavioral of g_m_5 is
 
begin
 
a_1_out <= a_1_in xor (not(a_3_in) and not(a_2_in));
 
end Behavioral;
 
/noekeoncore/trunk/rtl/g_m_6.vhd
0,0 → 1,35
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity g_m_6 is
port(clk : in std_logic;
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0));
end g_m_6;
 
architecture Behavioral of g_m_6 is
 
begin
 
a_0_out <= a_0_in xor (a_2_in and a_1_in);
 
end Behavioral;
 
/noekeoncore/trunk/rtl/pi_1.vhd
0,0 → 1,38
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity pi_1 is
port(a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end pi_1;
 
architecture Behavioral of pi_1 is
 
begin
 
a_1_out <= a_1_in(30 downto 0) & a_1_in(31);
a_2_out <= a_2_in(26 downto 0) & a_2_in(31 downto 27);
a_3_out <= a_3_in(29 downto 0) & a_3_in(31 downto 30);
 
end Behavioral;
 
/noekeoncore/trunk/rtl/pi_2.vhd
0,0 → 1,53
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
entity pi_2 is
port(a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end pi_2;
 
architecture Behavioral of pi_2 is
 
begin
 
a_1_out <= a_1_in(0) & a_1_in(31 downto 1);
a_2_out <= a_2_in(4 downto 0) & a_2_in(31 downto 5);
a_3_out <= a_3_in(1 downto 0) & a_3_in(31 downto 2);
 
end Behavioral;
 
/noekeoncore/trunk/rtl/tb_theta.vhd
0,0 → 1,137
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY tb_theta IS
END tb_theta;
ARCHITECTURE behavior OF tb_theta IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT theta
PORT(
clk : IN std_logic;
a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
k_0_in : IN std_logic_vector(31 downto 0);
k_1_in : IN std_logic_vector(31 downto 0);
k_2_in : IN std_logic_vector(31 downto 0);
k_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_3_in : std_logic_vector(31 downto 0) := (others => '0');
 
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: theta PORT MAP (
clk => clk,
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
k_0_in => k_0_in,
k_1_in => k_1_in,
k_2_in => k_2_in,
k_3_in => k_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + clk_period;
 
a_0_in <= X"61396c13";
a_1_in <= X"637434b8";
a_2_in <= X"fc6559a9";
a_3_in <= X"5b643f2c";
k_0_in <= X"4ED2552D";
k_1_in <= X"1AE69D5D";
k_2_in <= X"C9B75C29";
k_3_in <= X"0C49E157";
 
wait for clk_period;
 
k_0_in <= (others => '0');
k_1_in <= (others => '0');
k_2_in <= (others => '0');
k_3_in <= (others => '0');
 
a_0_in <= X"4ED2552D";
a_1_in <= X"1AE69D5D";
a_2_in <= X"C9B75C29";
a_3_in <= X"0C49E157";
wait for clk_period;
 
a_0_in <= X"200d6ff9";
a_1_in <= X"02667af7";
a_2_in <= X"3a345347";
a_3_in <= X"2cd90d69";
 
k_0_in <= X"fd178c4d";
k_1_in <= X"fc0df5d7";
k_2_in <= X"7a728549";
k_3_in <= X"eaa289dd";
wait;
end process;
 
END;
/noekeoncore/trunk/rtl/round_f.vhd
0,0 → 1,162
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity round_f is
port(clk : in std_logic;
enc : in std_logic;
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end round_f;
 
architecture Behavioral of round_f is
 
signal a_0_in_s : std_logic_vector(31 downto 0);
 
signal theta_0_s : std_logic_vector(31 downto 0);
signal theta_1_s : std_logic_vector(31 downto 0);
signal theta_2_s : std_logic_vector(31 downto 0);
signal theta_3_s : std_logic_vector(31 downto 0);
 
signal pi_1_1_s : std_logic_vector(31 downto 0);
signal pi_1_2_s : std_logic_vector(31 downto 0);
signal pi_1_3_s : std_logic_vector(31 downto 0);
 
signal gamma_0_s : std_logic_vector(31 downto 0);
signal gamma_1_s : std_logic_vector(31 downto 0);
signal gamma_2_s : std_logic_vector(31 downto 0);
signal gamma_3_s : std_logic_vector(31 downto 0);
 
signal pi_2_1_s : std_logic_vector(31 downto 0);
signal pi_2_2_s : std_logic_vector(31 downto 0);
signal pi_2_3_s : std_logic_vector(31 downto 0);
 
component theta is
port(clk : in std_logic;
 
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
 
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
 
component pi_1 is
port(a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
 
component gamma is
port(clk : in std_logic;
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
 
component pi_2 is
port(a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
 
signal a_0_aux_s : std_logic_vector(31 downto 0);
 
begin
 
a_0_in_s <= (a_0_in xor rc_in) when enc = '0' else a_0_in;
 
THETA_0 : theta port map (clk,
a_0_in_s,
a_1_in,
a_2_in,
a_3_in,
k_0_in,
k_1_in,
k_2_in,
k_3_in,
theta_0_s,
theta_1_s,
theta_2_s,
theta_3_s);
 
a_0_aux_s <= (theta_0_s xor rc_in) when enc = '1' else theta_0_s;
 
PI_1_0 : pi_1 port map (theta_1_s,
theta_2_s,
theta_3_s,
pi_1_1_s,
pi_1_2_s,
pi_1_3_s);
 
GAMMA_0 : gamma port map (clk,
a_0_aux_s,
pi_1_1_s,
pi_1_2_s,
pi_1_3_s,
gamma_0_s,
gamma_1_s,
gamma_2_s,
gamma_3_s);
 
PI_2_0 : pi_2 port map (gamma_1_s,
gamma_2_s,
gamma_3_s,
pi_2_1_s,
pi_2_2_s,
pi_2_3_s);
 
a_0_out <= gamma_0_s;
a_1_out <= pi_2_1_s;
a_2_out <= pi_2_2_s;
a_3_out <= pi_2_3_s;
 
end Behavioral;
 
/noekeoncore/trunk/rtl/rc_gen.vhd
0,0 → 1,61
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity rc_gen is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- 0 (enc), 1 (dec)
rc_out : out std_logic_vector(7 downto 0));
end rc_gen;
 
architecture Behavioral of rc_gen is
signal rc_s : std_logic_vector(7 downto 0);
begin
 
pr_gen: process(clk, rst, enc)
begin
if rising_edge(clk) then
if rst = '1' then
if enc = '0' then
rc_s <= X"80";
else
rc_s <= X"D4";
end if;
else
if enc = '0' then
if ((rc_s and X"80") = X"00") then
rc_s <= rc_s(6 downto 0) & '0';
else
rc_s <= (rc_s(6 downto 0) & '0') xor X"1B";
end if;
else
if ((rc_s and X"01") = X"00") then
rc_s <= '0' & rc_s(7 downto 1);
else
rc_s <= ('0' & rc_s(7 downto 1)) xor X"8D";
end if;
end if;
end if;
end if;
end process;
 
rc_out <= rc_s;
 
end Behavioral;
 
/noekeoncore/trunk/rtl/noekeon.vhd
0,0 → 1,220
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity noekeon is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end noekeon;
 
architecture Behavioral of noekeon is
 
component round_f is
port(clk : in std_logic;
enc : in std_logic;
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
 
component rc_gen is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
rc_out : out std_logic_vector(7 downto 0));
end component;
 
component output_trans is
port(clk : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
 
component theta is
port(clk : in std_logic;
 
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
 
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
 
signal rc_s : std_logic_vector(7 downto 0);
signal rc_ext_s : std_logic_vector(31 downto 0);
 
signal a_0_in_s : std_logic_vector(31 downto 0);
signal a_1_in_s : std_logic_vector(31 downto 0);
signal a_2_in_s : std_logic_vector(31 downto 0);
signal a_3_in_s : std_logic_vector(31 downto 0);
 
signal out_t_a_0_in_s : std_logic_vector(31 downto 0);
signal out_t_a_1_in_s : std_logic_vector(31 downto 0);
signal out_t_a_2_in_s : std_logic_vector(31 downto 0);
signal out_t_a_3_in_s : std_logic_vector(31 downto 0);
signal a_0_out_s : std_logic_vector(31 downto 0);
signal a_1_out_s : std_logic_vector(31 downto 0);
signal a_2_out_s : std_logic_vector(31 downto 0);
signal a_3_out_s : std_logic_vector(31 downto 0);
 
signal k_0_d_s : std_logic_vector(31 downto 0);
signal k_1_d_s : std_logic_vector(31 downto 0);
signal k_2_d_s : std_logic_vector(31 downto 0);
signal k_3_d_s : std_logic_vector(31 downto 0);
 
signal k_0_mux_s : std_logic_vector(31 downto 0);
signal k_1_mux_s : std_logic_vector(31 downto 0);
signal k_2_mux_s : std_logic_vector(31 downto 0);
signal k_3_mux_s : std_logic_vector(31 downto 0);
 
begin
 
RC_GEN_0 : rc_gen port map (clk, rst, enc, rc_s);
 
rc_ext_s <= X"000000" & rc_s;
 
ROUND_F_0 : round_f port map (clk,
enc,
rc_ext_s,
a_0_in_s,
a_1_in_s,
a_2_in_s,
a_3_in_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
a_0_out_s,
a_1_out_s,
a_2_out_s,
a_3_out_s);
 
pr_noe: process(clk, rst, enc)
begin
if rising_edge(clk) then
if rst = '1' then
a_0_in_s <= a_0_in;
a_1_in_s <= a_1_in;
a_2_in_s <= a_2_in;
a_3_in_s <= a_3_in;
else
a_0_in_s <= a_0_out_s;
a_1_in_s <= a_1_out_s;
a_2_in_s <= a_2_out_s;
a_3_in_s <= a_3_out_s;
end if;
end if;
end process;
 
-- a_0_out <= a_0_out_s;
-- a_1_out <= a_1_out_s;
-- a_2_out <= a_2_out_s;
-- a_3_out <= a_3_out_s;
 
out_trans_pr: process(clk, rst, a_0_out_s, a_1_out_s, a_2_out_s, a_3_out_s)
begin
if rising_edge(clk) then
out_t_a_0_in_s <= a_0_out_s;
out_t_a_1_in_s <= a_1_out_s;
out_t_a_2_in_s <= a_2_out_s;
out_t_a_3_in_s <= a_3_out_s;
end if;
end process;
 
OUT_TRANS_0 : output_trans port map (clk, enc, rc_ext_s,
out_t_a_0_in_s,
out_t_a_1_in_s,
out_t_a_2_in_s,
out_t_a_3_in_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
a_0_out,
a_1_out,
a_2_out,
a_3_out);
 
-- key decrypt
THETA_DECRYPT_0 : theta port map (clk,
k_0_in,
k_1_in,
k_2_in,
k_3_in,
(others => '0'),
(others => '0'),
(others => '0'),
(others => '0'),
k_0_d_s,
k_1_d_s,
k_2_d_s,
k_3_d_s);
 
k_0_mux_s <= k_0_in when enc = '0' else k_0_d_s;
k_1_mux_s <= k_1_in when enc = '0' else k_1_d_s;
k_2_mux_s <= k_2_in when enc = '0' else k_2_d_s;
k_3_mux_s <= k_3_in when enc = '0' else k_3_d_s;
 
end Behavioral;
 
/noekeoncore/trunk/tb/tb_round_f.vhd
0,0 → 1,121
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_round_f IS
END tb_round_f;
ARCHITECTURE behavior OF tb_round_f IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT round_f
PORT(
clk : IN std_logic;
rc_in : IN std_logic_vector(31 downto 0);
a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
k_0_in : IN std_logic_vector(31 downto 0);
k_1_in : IN std_logic_vector(31 downto 0);
k_2_in : IN std_logic_vector(31 downto 0);
k_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal rc_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_3_in : std_logic_vector(31 downto 0) := (others => '0');
 
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: round_f PORT MAP (
clk => clk,
rc_in => rc_in,
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
k_0_in => k_0_in,
k_1_in => k_1_in,
k_2_in => k_2_in,
k_3_in => k_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
 
wait for clk_period*10;
rc_in <= X"00000080";
a_0_in <= X"61396c93";
a_1_in <= X"637434b8";
a_2_in <= X"fc6559a9";
a_3_in <= X"5b643f2c";
 
k_0_in <= X"1c1c1c1c";
k_1_in <= X"1c1c1c1c";
k_2_in <= X"1c1c1c1c";
k_3_in <= X"1c1c1c1c";
 
wait;
end process;
 
END;
/noekeoncore/trunk/tb/tb_rc_gen.vhd
0,0 → 1,88
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_rc_gen IS
END tb_rc_gen;
ARCHITECTURE behavior OF tb_rc_gen IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT rc_gen
PORT(
clk : IN std_logic;
rst : IN std_logic;
enc : IN std_logic;
rc_out : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal enc : std_logic := '0';
 
--Outputs
signal rc_out : std_logic_vector(7 downto 0);
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: rc_gen PORT MAP (
clk => clk,
rst => rst,
enc => enc,
rc_out => rc_out
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + clk_period;
rst <= '1';
enc <= '0';
wait for clk_period;
rst <= '0';
wait for clk_period*15;
rst <= '1';
enc <= '1';
wait for clk_period;
rst <= '0';
 
-- insert stimulus here
 
wait;
end process;
 
END;
/noekeoncore/trunk/tb/tb_noekeon.vhd
0,0 → 1,169
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_noekeon IS
END tb_noekeon;
ARCHITECTURE behavior OF tb_noekeon IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT noekeon
PORT(
clk : IN std_logic;
rst : IN std_logic;
enc : IN std_logic;
a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
k_0_in : IN std_logic_vector(31 downto 0);
k_1_in : IN std_logic_vector(31 downto 0);
k_2_in : IN std_logic_vector(31 downto 0);
k_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal enc : std_logic := '0';
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_3_in : std_logic_vector(31 downto 0) := (others => '0');
 
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: noekeon PORT MAP (
clk => clk,
rst => rst,
enc => enc,
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
k_0_in => k_0_in,
k_1_in => k_1_in,
k_2_in => k_2_in,
k_3_in => k_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + clk_period;
rst <= '1';
enc <= '0';
a_0_in <= X"2a78421b";
a_1_in <= X"87c7d092";
a_2_in <= X"4f26113f";
a_3_in <= X"1d1349b2";
 
k_0_in <= X"b1656851";
k_1_in <= X"699e29fa";
k_2_in <= X"24b70148";
k_3_in <= X"503d2dfc";
wait for clk_period;
rst <= '0';
 
wait for clk_period*15 + clk_period/2;
 
assert a_0_out = X"e2f687e0"
report "ENCRYPT ERROR (a_0)" severity FAILURE;
 
assert a_1_out = X"7b75660f"
report "ENCRYPT ERROR (a_1)" severity FAILURE;
 
assert a_2_out = X"fc372233"
report "ENCRYPT ERROR (a_2)" severity FAILURE;
 
assert a_3_out = X"bc47532c"
report "ENCRYPT ERROR (a_3)" severity FAILURE;
 
wait for clk_period + clk_period/2;
rst <= '1';
enc <= '1';
a_0_in <= X"e2f687e0";
a_1_in <= X"7b75660f";
a_2_in <= X"fc372233";
a_3_in <= X"bc47532c";
 
k_0_in <= X"b1656851";
k_1_in <= X"699e29fa";
k_2_in <= X"24b70148";
k_3_in <= X"503d2dfc";
wait for clk_period;
rst <= '0';
 
wait for clk_period*15 + clk_period/2;
 
assert a_0_out = X"2a78421b"
report "DECRYPT ERROR (a_0)" severity FAILURE;
 
assert a_1_out = X"87c7d092"
report "DECRYPT ERROR (a_1)" severity FAILURE;
 
assert a_2_out = X"4f26113f"
report "DECRYPT ERROR (a_2)" severity FAILURE;
 
assert a_3_out = X"1d1349b2"
report "DECRYPT ERROR (a_3)" severity FAILURE;
 
wait;
end process;
 
END;
/noekeoncore/trunk/tb/tb_gamma.vhd
0,0 → 1,105
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_gamma IS
END tb_gamma;
ARCHITECTURE behavior OF tb_gamma IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT gamma
PORT(
clk : IN std_logic;
a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
 
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: gamma PORT MAP (
clk => clk,
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + clk_period;
 
a_0_in <= X"C5B032AD";
a_1_in <= X"3E48160D";
a_2_in <= X"8C9A3EF5";
a_3_in <= X"AF2DFC9F";
 
wait for clk_period;
 
a_0_in <= X"AB2DED92";
a_1_in <= X"5C481D1D";
a_2_in <= X"8407F1CF";
a_3_in <= X"C9B824A8";
 
-- insert stimulus here
 
wait;
end process;
 
END;
/noekeoncore/trunk/tb/tb_theta.vhd
0,0 → 1,137
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY tb_theta IS
END tb_theta;
ARCHITECTURE behavior OF tb_theta IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT theta
PORT(
clk : IN std_logic;
a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
k_0_in : IN std_logic_vector(31 downto 0);
k_1_in : IN std_logic_vector(31 downto 0);
k_2_in : IN std_logic_vector(31 downto 0);
k_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_3_in : std_logic_vector(31 downto 0) := (others => '0');
 
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: theta PORT MAP (
clk => clk,
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
k_0_in => k_0_in,
k_1_in => k_1_in,
k_2_in => k_2_in,
k_3_in => k_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + clk_period;
 
a_0_in <= X"61396c13";
a_1_in <= X"637434b8";
a_2_in <= X"fc6559a9";
a_3_in <= X"5b643f2c";
k_0_in <= X"4ED2552D";
k_1_in <= X"1AE69D5D";
k_2_in <= X"C9B75C29";
k_3_in <= X"0C49E157";
 
wait for clk_period;
 
k_0_in <= (others => '0');
k_1_in <= (others => '0');
k_2_in <= (others => '0');
k_3_in <= (others => '0');
 
a_0_in <= X"4ED2552D";
a_1_in <= X"1AE69D5D";
a_2_in <= X"C9B75C29";
a_3_in <= X"0C49E157";
wait for clk_period;
 
a_0_in <= X"200d6ff9";
a_1_in <= X"02667af7";
a_2_in <= X"3a345347";
a_3_in <= X"2cd90d69";
 
k_0_in <= X"fd178c4d";
k_1_in <= X"fc0df5d7";
k_2_in <= X"7a728549";
k_3_in <= X"eaa289dd";
wait;
end process;
 
END;
/noekeoncore/trunk/tb/tb_pi_1.vhd
0,0 → 1,75
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_pi_1 IS
END tb_pi_1;
ARCHITECTURE behavior OF tb_pi_1 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT pi_1
PORT(
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
 
--Inputs
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
 
--Outputs
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: pi_1 PORT MAP (
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
 
 
 
-- Stimulus process
stim_proc: process
begin
a_1_in <= X"a1abab3c";
a_2_in <= X"0232b23f";
a_3_in <= X"f000abbb";
wait;
end process;
 
END;
/noekeoncore/trunk/tb/tb_pi_2.vhd
0,0 → 1,73
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_pi_2 IS
END tb_pi_2;
ARCHITECTURE behavior OF tb_pi_2 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT pi_2
PORT(
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
 
--Inputs
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
 
--Outputs
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: pi_2 PORT MAP (
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
 
-- Stimulus process
stim_proc: process
begin
a_1_in <= X"43575679";
a_2_in <= X"465647e0";
a_3_in <= X"c002aeef";
wait;
end process;
 
END;

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