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URL https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk

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    /oms8051mini/trunk
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Rev 25 → Rev 24

/rtl/8051/oc8051_acc.v
16,9 → 16,6
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
74,7 → 71,7
`include "top_defines.v"
 
 
module oc8051_acc (clk, resetn,
module oc8051_acc (clk, rst,
bit_in, data_in, data2_in,
data_out,
wr, wr_bit, wr_addr,
81,7 → 78,7
p, wr_sfr);
 
 
input clk, resetn, wr, wr_bit, bit_in;
input clk, rst, wr, wr_bit, bit_in;
input [1:0] wr_sfr;
input [7:0] wr_addr, data_in, data2_in;
 
122,9 → 119,9
acc = data_out;
end
 
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0)
if (rst)
data_out <= #1 `OC8051_RST_ACC;
else
data_out <= #1 acc;
/rtl/8051/oc8051_alu.v
18,9 → 18,6
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
//// ////
86,7 → 83,7
 
 
 
module oc8051_alu (clk, resetn, op_code, src1, src2, src3, srcCy, srcAc, bit_in,
module oc8051_alu (clk, rst, op_code, src1, src2, src3, srcCy, srcAc, bit_in,
des1, des2, des_acc, desCy, desAc, desOv, sub_result);
//
// op_code (in) operation code [oc8051_decoder.alu_op -r]
103,7 → 100,7
// desOv (out) Overflow output [oc8051_psw.ov_in]
//
 
input srcCy, srcAc, bit_in, clk, resetn;
input srcCy, srcAc, bit_in, clk, rst;
input [3:0] op_code;
input [7:0] src1, src2, src3;
output desCy, desAc, desOv;
154,7 → 151,7
wire [15:0] inc, dec;
 
 
oc8051_multiply oc8051_mul1(.clk(clk), .resetn(resetn), .enable(enable_mul), .src1(src1), .src2(src2), .des1(mulsrc1), .des2(mulsrc2), .desOv(mulOv));
oc8051_multiply oc8051_mul1(.clk(clk), .rst(rst), .enable(enable_mul), .src1(src1), .src2(src2), .des1(mulsrc1), .des2(mulsrc2), .desOv(mulOv));
 
 
 
162,7 → 159,7
 
 
 
oc8051_divide oc8051_div1(.clk(clk), .resetn(resetn), .enable(enable_div), .src1(src1), .src2(src2), .des1(divsrc1), .des2(divsrc2), .desOv(divOv));
oc8051_divide oc8051_div1(.clk(clk), .rst(rst), .enable(enable_div), .src1(src1), .src2(src2), .des1(divsrc1), .des2(divsrc2), .desOv(divOv));
 
/* Add */
assign add1 = {1'b0,src1[3:0]};
/rtl/8051/oc8051_alu_src_sel.v
16,9 → 16,6
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
63,7 → 60,7
`include "top_defines.v"
 
 
module oc8051_alu_src_sel (clk, resetn, rd, sel1, sel2, sel3,
module oc8051_alu_src_sel (clk, rst, rd, sel1, sel2, sel3,
acc, ram, pc, dptr,
 
op1, op2, op3,
71,7 → 68,7
src1, src2, src3);
 
 
input clk, resetn, rd, sel3;
input clk, rst, rd, sel3;
input [1:0] sel2;
input [2:0] sel1;
input [7:0] acc, ram;
138,8 → 135,8
end
 
 
always @(posedge clk or negedge resetn)
if (resetn == 1'b0) begin
always @(posedge clk or posedge rst)
if (rst) begin
op1_r <= #1 8'h00;
op2_r <= #1 8'h00;
op3_r <= #1 8'h00;
/rtl/8051/oc8051_alu_test.v
18,9 → 18,6
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
//// ////
59,7 → 56,7
 
 
 
module oc8051_alu (clk, resetn, op_code, src1, src2, src3, srcCy, srcAc, bit_in, des1, des2, des1_r, desCy, desAc, desOv);
module oc8051_alu (clk, rst, op_code, src1, src2, src3, srcCy, srcAc, bit_in, des1, des2, des1_r, desCy, desAc, desOv);
//
// op_code (in) operation code [oc8051_decoder.alu_op -r]
// src1 (in) first operand [oc8051_alu_src1_sel.des]
76,7 → 73,7
// desOv (out) Overflow output [oc8051_psw.ov_in]
//
 
input srcCy, srcAc, bit_in, clk, resetn; input [3:0] op_code; input [7:0] src1, src2, src3;
input srcCy, srcAc, bit_in, clk, rst; input [3:0] op_code; input [7:0] src1, src2, src3;
output desCy, desAc, desOv;
output [7:0] des1, des2;
output [7:0] des1_r;
126,8 → 123,8
reg da_tmp;
//reg [8:0] da1;
 
oc8051_multiply oc8051_mul1(.clk(clk), .resetn(resetn), .enable(enable_mul), .src1(src1), .src2(src2), .des1(mulsrc1), .des2(mulsrc2), .desOv(mulOv));
oc8051_divide oc8051_div1(.clk(clk), .resetn(resetn), .enable(enable_div), .src1(src1), .src2(src2), .des1(divsrc1), .des2(divsrc2), .desOv(divOv));
oc8051_multiply oc8051_mul1(.clk(clk), .rst(rst), .enable(enable_mul), .src1(src1), .src2(src2), .des1(mulsrc1), .des2(mulsrc2), .desOv(mulOv));
oc8051_divide oc8051_div1(.clk(clk), .rst(rst), .enable(enable_div), .src1(src1), .src2(src2), .des1(divsrc1), .des2(divsrc2), .desOv(divOv));
 
/* Add */
assign add1 = {1'b0,src1[3:0]};
359,15 → 356,15
endcase
end
 
always @(posedge clk or negedge resetn)
if (resetn == 1'b0) begin
always @(posedge clk or posedge rst)
if (rst) begin
ides1_r <= #1 8'h0;
end else begin
ides1_r <= #1 ides1;
end
 
always @(posedge clk or negedge resetn)
if (resetn == 1'b0) begin
always @(posedge clk or posedge rst)
if (rst) begin
desCy <= #1 1'b0;
desAc <= #1 1'b0;
desOv <= #1 1'b0;
/rtl/8051/oc8051_b_register.v
16,9 → 16,6
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
62,11 → 59,11
`include "top_defines.v"
 
 
module oc8051_b_register (clk, resetn, bit_in, data_in, wr, wr_bit,
module oc8051_b_register (clk, rst, bit_in, data_in, wr, wr_bit,
wr_addr, data_out);
 
 
input clk, resetn, wr, wr_bit, bit_in;
input clk, rst, wr, wr_bit, bit_in;
input [7:0] wr_addr, data_in;
 
output [7:0] data_out;
76,9 → 73,9
//
//writing to b
//must check if write high and correct address
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0)
if (rst)
data_out <= #1 `OC8051_RST_B;
else if (wr) begin
if (!wr_bit) begin
/rtl/8051/oc8051_comp.v
17,9 → 17,6
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
/rtl/8051/oc8051_cy_select.v
16,9 → 16,6
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
/rtl/8051/oc8051_decoder.v
17,9 → 17,6
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
87,7 → 84,7
`include "top_defines.v"
 
 
module oc8051_decoder (clk, resetn, op_in, op1_c,
module oc8051_decoder (clk, rst, op_in, op1_c,
ram_rd_sel_o, ram_wr_sel_o,
bit_addr, wr_o, wr_sfr_o,
src_sel1, src_sel2, src_sel3,
97,7 → 94,7
 
//
// clk (in) clock
// resetn (in) reset
// rst (in) reset
// op_in (in) operation code [oc8051_op_select.op1]
// eq (in) compare result [oc8051_comp.eq]
// ram_rd_sel (out) select, whitch address will be send to ram for read [oc8051_ram_rd_sel.sel, oc8051_sp.ram_rd_sel]
119,7 → 116,7
// pc_wait (out)
//
 
input clk, resetn, eq, mem_wait, wait_data;
input clk, rst, eq, mem_wait, wait_data;
input [7:0] op_in;
 
output wr_o, bit_addr, pc_wr, rmw, istb, src_sel3;
1314,9 → 1311,9
//
// registerd outputs
 
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
ram_wr_sel <= #1 `OC8051_RWS_DC;
src_sel1 <= #1 `OC8051_AS1_DC;
src_sel2 <= #1 `OC8051_AS2_DC;
2755,15 → 2752,15
 
//
// remember current instruction
always @(posedge clk or negedge resetn)
if (resetn == 1'b0) op <= #1 2'b00;
always @(posedge clk or posedge rst)
if (rst) op <= #1 2'b00;
else if (state==2'b00) op <= #1 op_in;
 
//
// in case of instructions that needs more than one clock set state
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0)
if (rst)
state <= #1 2'b11;
else if (!mem_wait & !wait_data) begin
case (state) /* synopsys parallel_case */
2810,9 → 2807,9
 
//
//in case of writing to external ram
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
mem_act <= #1 `OC8051_MAS_NO;
end else if (!rd) begin
mem_act <= #1 `OC8051_MAS_NO;
2828,9 → 2825,9
endcase
end
 
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
ram_rd_sel_r <= #1 3'h0;
end else begin
ram_rd_sel_r <= #1 ram_rd_sel;
/rtl/8051/oc8051_divide.v
17,9 → 17,6
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
//// ////
55,11 → 52,11
//
 
 
module oc8051_divide (clk, resetn, enable, src1, src2, des1, des2, desOv);
module oc8051_divide (clk, rst, enable, src1, src2, des1, des2, desOv);
//
// this module is part of alu
// clk (in)
// resetn (in)
// rst (in)
// enable (in) starts divison
// src1 (in) first operand
// src2 (in) second operand
68,7 → 65,7
// desOv (out) Overflow output
//
 
input clk, resetn, enable;
input clk, rst, enable;
input [7:0] src1, src2;
output desOv;
output [7:0] des1, des2;
109,9 → 106,9
 
//
// divider works in four clock cycles -- 0, 1, 2 and 3
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
cycle <= #1 2'b0;
tmp_div <= #1 6'h0;
tmp_rem <= #1 8'h0;
/rtl/8051/oc8051_dptr.v
16,9 → 16,6
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
60,10 → 57,10
`include "top_defines.v"
 
 
module oc8051_dptr(clk, resetn, addr, data_in, data2_in, wr, wr_sfr, wr_bit, data_hi, data_lo);
module oc8051_dptr(clk, rst, addr, data_in, data2_in, wr, wr_sfr, wr_bit, data_hi, data_lo);
//
// clk (in) clock
// resetn (in) reset
// rst (in) reset
// addr (in) write address input [oc8051_ram_wr_sel.out]
// data_in (in) destination 1 from alu [oc8051_alu.des1]
// data2_in (in) destination 2 from alu [oc8051_alu.des2]
75,7 → 72,7
//
 
 
input clk, resetn, wr, wr_bit;
input clk, rst, wr, wr_bit;
input [1:0] wr_sfr;
input [7:0] addr, data_in, data2_in;
 
83,9 → 80,9
 
reg [7:0] data_hi, data_lo;
 
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
data_hi <= #1 `OC8051_RST_DPH;
data_lo <= #1 `OC8051_RST_DPL;
end else if (wr_sfr==`OC8051_WRS_DPTR) begin
/rtl/8051/oc8051_indi_addr.v
17,9 → 17,6
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
61,12 → 58,12
//
 
 
module oc8051_indi_addr (clk, resetn, wr_addr, data_in, wr, wr_bit, ri_out, sel, bank);
module oc8051_indi_addr (clk, rst, wr_addr, data_in, wr, wr_bit, ri_out, sel, bank);
//
 
 
input clk, // clock
resetn, // reset
rst, // reset
wr, // write
sel, // select register
wr_bit; // write bit addressable
84,9 → 81,9
 
//
//write to buffer
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
buff[3'b000] <= #1 8'h00;
buff[3'b001] <= #1 8'h00;
buff[3'b010] <= #1 8'h00;
119,8 → 116,8
 
 
 
always @(posedge clk or negedge resetn)
if (resetn == 1'b0) begin
always @(posedge clk or posedge rst)
if (rst) begin
wr_bit_r <= #1 1'b0;
end else begin
wr_bit_r <= #1 wr_bit;
/rtl/8051/oc8051_int.v
18,9 → 18,6
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
72,7 → 69,7
 
 
 
module oc8051_int (clk, resetn,
module oc8051_int (clk, rst,
wr_addr,
data_in, bit_in,
wr, wr_bit,
89,7 → 86,7
ie, tcon, ip);
 
input [7:0] wr_addr, data_in;
input wr, tf0, tf1, t2_int, ie0, ie1, clk, resetn, reti, wr_bit, bit_in, ack, uart_int;
input wr, tf0, tf1, t2_int, ie0, ie1, clk, rst, reti, wr_bit, bit_in, ack, uart_int;
 
output tr0, tr1, intr;
output [7:0] int_vec,
157,9 → 154,9
 
//
// IP
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
ip <=#1 `OC8051_RST_IP;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
ip <= #1 data_in;
169,9 → 166,9
 
//
// IE
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
ie <=#1 `OC8051_RST_IE;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
ie <= #1 data_in;
182,9 → 179,9
//
// tcon_s
//
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
tcon_s <=#1 4'b0000;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};
201,9 → 198,9
//
// tf1 (tmod.7)
//
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
tcon_tf1 <=#1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
tcon_tf1 <= #1 data_in[7];
219,9 → 216,9
//
// tf0 (tmod.5)
//
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
tcon_tf0 <=#1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
tcon_tf0 <= #1 data_in[5];
238,9 → 235,9
//
// ie0 (tmod.1)
//
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
tcon_ie0 <=#1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
tcon_ie0 <= #1 data_in[1];
259,9 → 256,9
//
// ie1 (tmod.3)
//
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
tcon_ie1 <=#1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
tcon_ie1 <= #1 data_in[3];
278,9 → 275,9
 
//
// interrupt processing
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
int_vec <= #1 8'h00;
int_dept <= #1 2'b0;
isrc[0] <= #1 3'h0;
345,8 → 342,8
end
 
 
always @(posedge clk or negedge resetn)
if (resetn == 1'b0) begin
always @(posedge clk or posedge rst)
if (rst) begin
tf0_buff <= #1 1'b0;
tf1_buff <= #1 1'b0;
ie0_buff <= #1 1'b0;
/rtl/8051/oc8051_memory_interface.v
14,11 → 14,9
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// - Dinesh Annayya, dinesha@opencores.org ////
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
90,7 → 88,7
`include "top_defines.v"
 
 
module oc8051_memory_interface (clk, resetn,
module oc8051_memory_interface (clk, rst,
 
//decoder
wr_i,
167,7 → 165,7
 
 
input clk,
resetn,
rst,
wr_i,
wr_bit_i;
 
369,7 → 367,7
 
 
`ifdef OC8051_SIMULATION
always @(negedge resetn) begin
always @(negedge rst) begin
#5
if (ea_rom_sel)
$display(" progran execution from external rom");
435,8 → 433,8
endcase
end
 
always @(posedge clk or negedge resetn)
if (resetn == 1'b0)
always @(posedge clk or posedge rst)
if (rst)
rd_ind <= #1 1'b0;
else if ((rd_sel==`OC8051_RRS_I) || (rd_sel==`OC8051_RRS_SP))
rd_ind <= #1 1'b1;
463,9 → 461,9
assign iadr_o = (istb_t) ? iadr_t : pc_out;
 
 
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
iadr_t <= #1 23'h0;
istb_t <= #1 1'b0;
imem_wait <= #1 1'b0;
492,9 → 490,9
 
assign dadr_o = dadr_ot;
 
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
dwe_o <= #1 1'b0;
dmem_wait <= #1 1'b0;
dstb_o <= #1 1'b0;
546,9 → 544,9
 
 
 
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
idat_cur <= #1 32'h0;
idat_old <= #1 32'h0;
end else if ((iack_i | ea_rom_sel) & (inc_pc | pc_wr_r2)) begin
558,9 → 556,9
 
end
 
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
cdata <= #1 8'h00;
cdone <= #1 1'b0;
end else if (istb_t) begin
654,16 → 652,16
 
//
//in case of reti
always @(posedge clk or negedge resetn)
if (resetn == 1'b0) reti <= #1 1'b0;
always @(posedge clk or posedge rst)
if (rst) reti <= #1 1'b0;
else if ((op1_o==`OC8051_RETI) & rd & !mem_wait) reti <= #1 1'b1;
else reti <= #1 1'b0;
 
//
// remember inputs
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
op2_buff <= #1 8'h0;
op3_buff <= #1 8'h0;
end else if (rd) begin
756,9 → 754,9
 
assign inc_pc = ((op_pos[2] | (&op_pos[1:0])) & rd) | pc_wr_r2;
 
always @(posedge clk or negedge resetn)
always @(posedge rst or posedge clk)
begin
if (resetn == 1'b0) begin
if (rst) begin
op_pos <= #1 3'h0;
end else if (pc_wr_r2) begin
op_pos <= #1 3'h4;// - op_length;////****??????????
773,8 → 771,8
//
// remember interrupt
// we don't want to interrupt instruction in the middle of execution
always @(posedge clk or negedge resetn)
if (resetn == 1'b0) begin
always @(posedge clk or posedge rst)
if (rst) begin
int_ack_t <= #1 1'b0;
int_vec_buff <= #1 8'h00;
end else if (intr) begin
782,12 → 780,12
int_vec_buff <= #1 int_v;
end else if (rd && (ea_rom_sel || iack_i) && !pc_wr_r2) int_ack_t <= #1 1'b0;
 
always @(posedge clk or negedge resetn)
if (resetn == 1'b0) int_ack_buff <= #1 1'b0;
always @(posedge clk or posedge rst)
if (rst) int_ack_buff <= #1 1'b0;
else int_ack_buff <= #1 int_ack_t;
 
always @(posedge clk or negedge resetn)
if (resetn == 1'b0) int_ack <= #1 1'b0;
always @(posedge clk or posedge rst)
if (rst) int_ack <= #1 1'b0;
else begin
if ((int_ack_buff) & !(int_ack_t))
int_ack <= #1 1'b1;
797,15 → 795,15
 
//
//interrupt buffer
always @(posedge clk or negedge resetn)
if (resetn == 1'b0) begin
always @(posedge clk or posedge rst)
if (rst) begin
int_buff1 <= #1 1'b0;
end else begin
int_buff1 <= #1 int_buff;
end
 
always @(posedge clk or negedge resetn)
if (resetn == 1'b0) begin
always @(posedge clk or posedge rst)
if (rst) begin
int_buff <= #1 1'b0;
end else if (intr) begin
int_buff <= #1 1'b1;
827,9 → 825,9
end
 
 
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0)
if (rst)
pc <= #1 16'h0;
else if (pc_wr_r2)
pc <= #1 pc_buf;
838,9 → 836,9
end
 
 
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
pc_buf <= #1 `OC8051_RST_PC;
end else if (pc_wr) begin
//
870,8 → 868,8
 
 
 
always @(posedge clk or negedge resetn)
if (resetn == 1'b0)
always @(posedge clk or posedge rst)
if (rst)
ddat_ir <= #1 8'h00;
else if (dack_i)
ddat_ir <= #1 ddat_i;
878,8 → 876,8
 
 
////////////////////////
always @(posedge clk or negedge resetn)
if (resetn == 1'b0) begin
always @(posedge clk or posedge rst)
if (rst) begin
rn_r <= #1 5'd0;
ri_r <= #1 8'h00;
imm_r <= #1 8'h00;
903,8 → 901,8
pc_wr_r2 <= #1 pc_wr_r;
end
 
always @(posedge clk or negedge resetn)
if (resetn == 1'b0) begin
always @(posedge clk or posedge rst)
if (rst) begin
inc_pc_r <= #1 1'b1;
end else if (istb) begin
inc_pc_r <= #1 inc_pc;
914,7 → 912,7
 
initial
begin
wait (!resetn)
wait (!rst)
if (ea_rom_sel) begin
$display(" ");
$display("\t Program running from internal rom !");
/rtl/8051/oc8051_multiply.v
17,9 → 17,6
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
//// ////
63,11 → 60,11
 
 
 
module oc8051_multiply (clk, resetn, enable, src1, src2, des1, des2, desOv);
module oc8051_multiply (clk, rst, enable, src1, src2, des1, des2, desOv);
//
// this module is part of alu
// clk (in)
// resetn (in)
// rst (in)
// enable (in)
// src1 (in) first operand
// src2 (in) second operand
76,7 → 73,7
// desOv (out) Overflow output
//
 
input clk, resetn, enable;
input clk, rst, enable;
input [7:0] src1, src2;
output desOv;
output [7:0] des1, des2;
99,9 → 96,9
assign des2 = mul_result[7:0];
assign desOv = | des1;
 
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
cycle <= #1 2'b0;
tmp_mul <= #1 16'b0;
end else begin
/rtl/8051/oc8051_ports.v
16,9 → 16,6
//// - Dinesh Annayya, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
67,7 → 64,7
 
 
module oc8051_ports (clk,
resetn,
rst,
bit_in,
data_in,
wr,
102,7 → 99,7
rmw);
 
input clk, //clock
resetn, //reset
rst, //reset
wr, //write [oc8051_decoder.wr -r]
wr_bit, //write bit addresable [oc8051_decoder.bit_addr -r]
bit_in, //bit input [oc8051_alu.desCy]
151,9 → 148,9
 
//
// case of writing to port
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
`ifdef OC8051_PORT0
p0_out <= #1 `OC8051_RST_P0;
`endif
/rtl/8051/oc8051_psw.v
16,9 → 16,6
//// - Dinesh Annayya , dinesha@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
69,11 → 66,11
`include "top_defines.v"
 
 
module oc8051_psw (clk, resetn, wr_addr, data_in, wr, wr_bit, data_out, p,
module oc8051_psw (clk, rst, wr_addr, data_in, wr, wr_bit, data_out, p,
cy_in, ac_in, ov_in, set, bank_sel);
//
// clk (in) clock
// resetn (in) reset
// rst (in) reset
// addr (in) write address [oc8051_ram_wr_sel.out]
// data_in (in) data input [oc8051_alu.des1]
// wr (in) write [oc8051_decoder.wr -r]
86,7 → 83,7
//
 
 
input clk, resetn, wr, p, cy_in, ac_in, ov_in, wr_bit;
input clk, rst, wr, p, cy_in, ac_in, ov_in, wr_bit;
input [1:0] set;
input [7:0] wr_addr, data_in;
 
103,9 → 100,9
 
//
//case writing to psw
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0)
if (rst)
data <= #1 `OC8051_RST_PSW;
 
//
/rtl/8051/oc8051_ram_256x8_two_bist.v
16,9 → 16,6
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
59,7 → 56,7
//
module oc8051_ram_256x8_two_bist (
clk,
resetn,
rst,
rd_addr,
rd_data,
rd_en,
80,7 → 77,7
 
input clk,
wr,
resetn,
rst,
rd_en,
wr_en;
input [7:0] wr_data;
101,7 → 98,7
xilinx_ram_dp u_ram(
// read port
.CLKA(clk),
.RSTA(resetn),
.RSTA(rst),
.ENA(rd_en),
.ADDRA(rd_addr),
.DIA(8'h00),
110,7 → 107,7
// write port
.CLKB(clk),
.RSTB(resetn),
.RSTB(rst),
.ENB(wr_en),
.ADDRB(wr_addr),
.DIB(wr_data),
128,7 → 125,7
oc8051_actel_ram_256x8 u_ram(
.RWCLK ( clk ),
.RESET ( resetn ),
.RESET ( rst ),
.REN ( rd_en ),
.RADDR ( rd_addr ),
.RD ( rd_data ),
143,7 → 140,7
generic_dpram #(8, 8) u_ram(
.rclk ( clk ),
.rresetn( resetn ),
.rrst ( rst ),
.rce ( rd_en ),
.oe ( 1'b1 ),
.raddr ( rd_addr ),
150,7 → 147,7
.do ( rd_data ),
.wclk ( clk ),
.wresetn ( resetn ),
.wrst ( rst ),
.wce ( wr_en ),
.we ( wr ),
.waddr ( wr_addr ),
175,9 → 172,9
//
// reading from ram
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0)
if (rst)
rd_data <= #1 8'h0;
else if ((wr_addr==rd_addr) & wr & rd_en)
rd_data <= #1 wr_data;
/rtl/8051/oc8051_ram_64x32_dual_bist.v
16,9 → 16,6
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
59,7 → 56,7
//
module oc8051_ram_64x32_dual_bist (
clk,
resetn,
rst,
adr0,
dat0_o,
84,7 → 81,7
 
input clk,
wr1,
resetn,
rst,
en0,
en1;
input [7:0] dat1_i;
110,7 → 107,7
xilinx_ram_dp u_ram_dp(
// read port
.CLKA(clk),
.RSTA(resetn),
.RSTA(rst),
.ENA(en0),
.ADDRA(adr0),
.DIA(32'h00),
119,7 → 116,7
// write port
.CLKB(clk),
.RSTB(resetn),
.RSTB(rst),
.ENB(en1),
.ADDRB(adr1),
.DIB(dat1_i),
141,7 → 138,7
generic_dpram #(ADR_WIDTH, 32) u_ram_dp(
.rclk ( clk ),
.resetn ( resetn ),
.rrst ( rst ),
.rce ( en0 ),
.oe ( 1'b1 ),
.raddr ( adr0 ),
148,7 → 145,7
.do ( dat0_o ),
.wclk ( clk ),
.wresetn ( resetn ),
.wrst ( rst ),
.wce ( en1 ),
.we ( wr1 ),
.waddr ( adr1 ),
163,9 → 160,9
// buffer
reg [31:0] buff [0:(1<<ADR_WIDTH) -1];
 
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0)
if (rst)
dat1_o <= #1 32'h0;
else if (wr1) begin
buff[adr1] <= #1 dat1_i;
174,9 → 171,9
dat1_o <= #1 buff[adr1];
end
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0)
if (rst)
dat0_o <= #1 32'h0;
else if ((adr0==adr1) & wr1)
dat0_o <= #1 dat1_i;
/rtl/8051/oc8051_ram_top.v
16,9 → 16,6
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
76,7 → 73,7
 
 
module oc8051_ram_top (clk,
resetn,
rst,
rd_addr,
rd_data,
wr_addr,
111,7 → 108,7
// bit_data_out (out) bit data output [oc8051_ram_sel.bit_in]
//
 
input clk, wr, bit_addr, bit_data_in, resetn;
input clk, wr, bit_addr, bit_data_in, rst;
input [7:0] wr_data;
input [7:0] rd_addr, wr_addr;
output bit_data_out;
147,7 → 144,7
 
oc8051_ram_256x8_two_bist u_ram_idata(
.clk ( clk ),
.resetn ( resetn ),
.rst ( rst ),
.rd_addr ( rd_addr_m ),
.rd_data ( rd_data_m ),
.rd_en ( !rd_en ),
165,8 → 162,8
`endif
);
 
always @(posedge clk or negedge resetn)
if (resetn == 1'b0) begin
always @(posedge clk or posedge rst)
if (rst) begin
bit_addr_r <= #1 1'b0;
bit_select <= #1 3'b0;
end else begin
175,8 → 172,8
end
 
 
always @(posedge clk or negedge resetn)
if (resetn == 1'b0) begin
always @(posedge clk or posedge rst)
if (rst) begin
rd_en_r <= #1 1'b0;
wr_data_r <= #1 8'h0;
end else begin
/rtl/8051/oc8051_rom.v
16,9 → 16,6
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
66,11 → 63,11
//
`include "top_defines.v"
 
module oc8051_rom (resetn, clk, addr, ea_int, data_o);
module oc8051_rom (rst, clk, addr, ea_int, data_o);
 
//parameter INT_ROM_WID= 15;
 
input resetn, clk;
input rst, clk;
input [15:0] addr;
//input [22:0] addr;
output ea_int;
94,7 → 91,7
 
assign ea = | addr[15:INT_ROM_WID];
 
assign addr_rst = resetn == 1'b0 ? 16'h0000 : addr;
assign addr_rst = rst ? 16'h0000 : addr;
 
rom0 rom_0 (.a(addr01), .o(int_data0));
rom1 rom_1 (.a(addr01), .o(int_data1));
886,8 → 883,8
endcase
end
 
always @(posedge clk or negedge resetn)
if (resetn == 1'b0)
always @(posedge clk or posedge rst)
if (rst)
ea_int <= #1 1'b1;
else ea_int <= #1 !ea;
 
906,8 → 903,8
$readmemh("./dat/oc8051_xrom.in", buff);
end
 
always @(posedge clk or negedge resetn)
if (resetn == 1'b0)
always @(posedge clk or posedge rst)
if (rst)
ea_int <= #1 1'b1;
else ea_int <= #1 !ea;
 
/rtl/8051/oc8051_sfr.v
16,9 → 16,6
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
96,7 → 93,7
`include "top_defines.v"
 
 
module oc8051_sfr (resetn, clk,
module oc8051_sfr (rst, clk,
adr0, adr1, dat0,
dat1, dat2, bit_in,
des_acc,
158,7 → 155,7
wait_data);
 
 
input resetn, // reset - pin
input rst, // reset - pin
clk, // clock - pin
we, // write enable
bit_in,
310,7 → 307,7
// accumulator
// ACC
oc8051_acc oc8051_acc1(.clk(clk),
.resetn(resetn),
.rst(rst),
.bit_in(bit_in),
.data_in(des_acc),
.data2_in(dat2),
326,7 → 323,7
// b register
// B
oc8051_b_register oc8051_b_register (.clk(clk),
.resetn(resetn),
.rst(rst),
.bit_in(bit_in),
.data_in(des_acc),
.wr(we),
338,7 → 335,7
//stack pointer
// SP
oc8051_sp oc8051_sp1(.clk(clk),
.resetn(resetn),
.rst(rst),
.ram_rd_sel(ram_rd_sel),
.ram_wr_sel(ram_wr_sel),
.wr_addr(adr1),
352,7 → 349,7
//data pointer
// DPTR, DPH, DPL
oc8051_dptr oc8051_dptr1(.clk(clk),
.resetn(resetn),
.rst(rst),
.addr(adr1),
.data_in(des_acc),
.data2_in(dat2),
367,7 → 364,7
//program status word
// PSW
oc8051_psw oc8051_psw1 (.clk(clk),
.resetn(resetn),
.rst(rst),
.wr_addr(adr1),
.data_in(dat1),
.wr(we),
385,7 → 382,7
// P0, P1, P2, P3
`ifdef OC8051_PORTS
oc8051_ports oc8051_ports1(.clk(clk),
.resetn(resetn),
.rst(rst),
.bit_in(bit_in),
.data_in(dat1),
.wr(we),
424,7 → 421,7
// SCON, SBUF
`ifdef OC8051_UART
oc8051_uart oc8051_uatr1 (.clk(clk),
.resetn(resetn),
.rst(rst),
.bit_in(bit_in),
.data_in(dat1),
.wr(we),
452,7 → 449,7
// interrupt control
// IP, IE, TCON
oc8051_int oc8051_int1 (.clk(clk),
.resetn(resetn),
.rst(rst),
.wr_addr(adr1),
.bit_in(bit_in),
.ack(int_ack),
480,7 → 477,7
// TH0, TH1, TL0, TH1, TMOD
`ifdef OC8051_TC01
oc8051_tc oc8051_tc1(.clk(clk),
.resetn(resetn),
.rst(rst),
.wr_addr(adr1),
.data_in(dat1),
.wr(we),
509,7 → 506,7
// TH2, TL2, RCAPL2L, RCAPL2H, T2CON
`ifdef OC8051_TC2
oc8051_tc2 oc8051_tc21(.clk(clk),
.resetn(resetn),
.rst(rst),
.wr_addr(adr1),
.data_in(dat1),
.wr(we),
536,8 → 533,8
 
 
 
always @(posedge clk or negedge resetn)
if (resetn == 1'b0) begin
always @(posedge clk or posedge rst)
if (rst) begin
adr0_r <= #1 8'h00;
ram_wr_sel_r <= #1 3'b000;
wr_bit_r <= #1 1'b0;
566,9 → 563,9
 
//
//set output in case of address (byte)
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
dat0 <= #1 8'h00;
wait_data <= #1 1'b0;
end else if ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) begin //write and read same address
654,9 → 651,9
//
//set output in case of address (bit)
 
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0)
if (rst)
bit_out <= #1 1'h0;
else if (
((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) & we & !wr_bit_r) |
706,9 → 703,9
endcase
end
 
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
prescaler <= #1 4'h0;
pres_ow <= #1 1'b0;
end else if (prescaler==4'b1011) begin
/rtl/8051/oc8051_sp.v
16,9 → 16,6
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
63,10 → 60,10
 
 
 
module oc8051_sp (clk, resetn, ram_rd_sel, ram_wr_sel, wr_addr, wr, wr_bit, data_in, sp_out, sp_w);
module oc8051_sp (clk, rst, ram_rd_sel, ram_wr_sel, wr_addr, wr, wr_bit, data_in, sp_out, sp_w);
 
 
input clk, resetn, wr, wr_bit;
input clk, rst, wr, wr_bit;
input [2:0] ram_rd_sel, ram_wr_sel;
input [7:0] data_in, wr_addr;
output [7:0] sp_out, sp_w;
84,9 → 81,9
assign sp_t= write ? data_in : sp;
 
 
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0)
if (rst)
sp <= #1 `OC8051_RST_SP;
else if (write)
sp <= #1 data_in;
116,9 → 113,9
end
 
 
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0)
if (rst)
pop <= #1 1'b0;
else if (ram_rd_sel==`OC8051_RRS_SP) pop <= #1 1'b1;
else pop <= #1 1'b0;
/rtl/8051/oc8051_tc.v
16,9 → 16,6
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
69,7 → 66,7
 
 
 
module oc8051_tc (clk, resetn,
module oc8051_tc (clk, rst,
data_in,
wr_addr,
wr, wr_bit,
84,7 → 81,7
input [7:0] wr_addr,
data_in;
input clk,
resetn,
rst,
wr,
wr_bit,
ie0,
115,9 → 112,9
//
// read or write from one of the addresses in tmod
//
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
tmod <=#1 `OC8051_RST_TMOD;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TMOD))
tmod <= #1 data_in;
126,9 → 123,9
//
// TIMER COUNTER 0
//
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
tl0 <=#1 `OC8051_RST_TL0;
th0 <=#1 `OC8051_RST_TH0;
tf0 <= #1 1'b0;
187,9 → 184,9
//
// TIMER COUNTER 1
//
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
tl1 <=#1 `OC8051_RST_TL1;
th1 <=#1 `OC8051_RST_TH1;
tf1_1 <= #1 1'b0;
230,8 → 227,8
end
 
 
always @(posedge clk or negedge resetn)
if (resetn == 1'b0) begin
always @(posedge clk or posedge rst)
if (rst) begin
t0_buff <= #1 1'b0;
t1_buff <= #1 1'b0;
end else begin
/rtl/8051/oc8051_tc2.v
16,9 → 16,6
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
61,7 → 58,7
 
 
 
module oc8051_tc2 (clk, resetn,
module oc8051_tc2 (clk, rst,
wr_addr,
data_in, bit_in,
wr, wr_bit,
75,7 → 72,7
input [7:0] wr_addr,
data_in;
input clk,
resetn,
rst,
wr,
wr_bit,
t2,
114,9 → 111,9
assign ct2 = t2con[1];
assign cprl2 = t2con[0];
 
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
t2con <= #1 `OC8051_RST_T2CON;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_T2CON)) begin
t2con <= #1 data_in;
134,9 → 131,9
//th2, tl2
assign run = tr2 & ((!ct2 & pres_ow) | (ct2 & tc2_event));
 
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
//
// reset
//
197,9 → 194,9
 
//
// rcap2l, rcap2h
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
rcap2l <= #1 `OC8051_RST_RCAP2L;
rcap2h <= #1 `OC8051_RST_RCAP2H;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2H)) begin
215,9 → 212,9
 
//
//
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
neg_trans <= #1 1'b0;
t2ex_r <= #1 1'b0;
end else if (t2ex) begin
234,9 → 231,9
 
//
//
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
tc2_event <= #1 1'b0;
t2_r <= #1 1'b0;
end else if (t2) begin
/rtl/8051/oc8051_top.v
17,8 → 17,6
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 8th Dec 2016
//// 1. External ROM Interface Removed
//// v0.1 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
115,7 → 113,7
 
`include "top_defines.v"
 
module oc8051_top (resetn, wb_clk_i,
module oc8051_top (wb_rst_i, wb_clk_i,
 
//interface to data ram
wbd_dat_i,
183,7 → 181,7
 
 
 
input resetn, // reset input
input wb_rst_i, // reset input
wb_clk_i, // clock input
int0_i, // interrupt 0
int1_i, // interrupt 1
352,7 → 350,7
// decoder
oc8051_decoder u_decoder(
.clk (wb_clk_i ),
.resetn (resetn ),
.rst (wb_rst_i ),
.op_in (op1_n ),
.op1_c (op1_cur ),
.ram_rd_sel_o (ram_rd_sel ),
385,7 → 383,7
//
//alu
oc8051_alu u_alu(
.resetn (resetn ),
.rst (wb_rst_i ),
.clk (wb_clk_i ),
.op_code (alu_op ),
.src1 (src1 ),
407,7 → 405,7
//data ram
oc8051_ram_top u_ram_top(
.clk (wb_clk_i ),
.resetn (resetn ),
.rst (wb_rst_i ),
.rd_addr (rd_addr ),
.rd_data (ram_data ),
.wr_addr (wr_addr ),
431,7 → 429,7
 
oc8051_alu_src_sel u_alu_src_sel(
.clk (wb_clk_i ),
.resetn (resetn ),
.rst (wb_rst_i ),
.rd (rd ),
 
.sel1 (src_sel1 ),
468,7 → 466,7
//program rom
`ifdef OC8051_ROM
oc8051_rom u_rom(
.resetn (resetn ),
.rst (wb_rst_i ),
.clk (wb_clk_i ),
.ea_int (ea_int ),
.addr (iadr_o ),
503,7 → 501,7
//
oc8051_indi_addr u_indi_addr (
.clk (wb_clk_i ),
.resetn (resetn ),
.rst (wb_rst_i ),
.wr_addr (wr_addr ),
.data_in (wr_dat ),
.wr (wr_o ),
519,7 → 517,7
//
oc8051_memory_interface u_memory_interface(
.clk (wb_clk_i ),
.resetn (resetn ),
.rst (wb_rst_i ),
// internal ram
.wr_i (wr ),
.wr_o (wr_o ),
596,7 → 594,7
//
 
oc8051_sfr u_sfr(
.resetn (resetn ),
.rst (wb_rst_i ),
.clk (wb_clk_i ),
.adr0 (rd_addr[7:0] ),
.adr1 (wr_addr[7:0] ),
714,9 → 712,9
 
// Assumption, Both Write and Read access will not be
// possbile in single clock cycle
always @(posedge wb_clk_i or negedge resetn)
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if(resetn == 1'b0) begin
if(wb_rst_i) begin
pushpop_cnt = 0;
end
else begin
/rtl/8051/oc8051_uart.v
16,9 → 16,6
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
70,7 → 67,7
 
`include "top_defines.v"
 
module oc8051_uart (resetn, clk,
module oc8051_uart (rst, clk,
bit_in, data_in,
wr_addr,
wr, wr_bit,
81,7 → 78,7
//registers
scon, pcon, sbuf);
 
input resetn,
input rst,
clk,
bit_in,
wr,
134,9 → 131,9
assign rb8 = scon[2];
assign ri = scon[0];
 
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0)
if (rst)
scon <= #1 `OC8051_RST_SCON;
else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
scon <= #1 data_in;
160,9 → 157,9
//
wire smod;
assign smod = pcon[7];
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0)
if (rst)
begin
pcon <= #1 `OC8051_RST_PCON;
end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
177,9 → 174,9
wire wr_sbuf;
assign wr_sbuf = (wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit);
 
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
txd <= #1 1'b1;
tr_count <= #1 4'd0;
trans <= #1 1'b0;
247,9 → 244,9
end
end
 
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
smod_clk_tr <= #1 1'b0;
shift_tr <= #1 1'b0;
end else if (sc_clk_tr) begin
268,9 → 265,9
//
//serial port buffer (receive)
//
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
re_count <= #1 4'd0;
receive <= #1 1'b0;
sbuf_rxd <= #1 8'h00;
328,9 → 325,9
end
end
 
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
smod_clk_re <= #1 1'b0;
shift_re <= #1 1'b0;
end else if (sc_clk_re) begin
351,9 → 348,9
//
//
 
always @(posedge clk or negedge resetn)
always @(posedge clk or posedge rst)
begin
if (resetn == 1'b0) begin
if (rst) begin
t1_ow_buf <= #1 1'b0;
end else begin
t1_ow_buf <= #1 t1_ow;
/rtl/8051/oc8051_wb_iinterface.v
16,9 → 16,6
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
67,14 → 64,14
//
 
 
module oc8051_wb_iinterface(resetn, clk,
module oc8051_wb_iinterface(rst, clk,
adr_i, dat_o, cyc_i, stb_i, ack_o,
adr_o, dat_i, cyc_o, stb_o, ack_i
);
//
// resetn (in) reset - pin
// rst (in) reset - pin
// clk (in) clock - pini
input resetn, clk;
input rst, clk;
 
//
// interface to oc8051 cpu
116,8 → 113,8
assign cyc_o = stb_o;
//assign adr_o = ack_i ? adr : adr_i;
 
always @(posedge clk or negedge resetn)
if (resetn == 1'b0) begin
always @(posedge clk or posedge rst)
if (rst) begin
stb_o <= #1 1'b0;
adr_o <= #1 16'h0000;
end else if (ack_i) begin
/rtl/clkgen/clkgen.v
17,9 → 17,6
//// Revision : Nov 26, 2016 ////
//// ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 5th Jan 2017
//// 1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
54,7 → 51,7
xtal_clk ,
clkout ,
gen_resetn ,
risc_resetn ,
risc_reset ,
app_clk ,
uart_ref_clk
);
61,13 → 58,13
 
 
 
input reset_n ; // Async reset signal
input reset_n ; // Async reset signal
input fastsim_mode ; // fast sim mode = 1
input mastermode ; // 1 : Risc master mode
input xtal_clk ; // Xtal clock-25Mhx
input xtal_clk ; // Xtal clock-25Mhx
output clkout ; // clock output, 250Mhz
output gen_resetn ; // internally generated reset
output risc_resetn ; // internally generated reset
output risc_reset ; // internally generated reset
output app_clk ; // application clock
output uart_ref_clk ; // uart 16x Ref clock
 
78,10 → 75,10
wire run_st ;
wire slave_run_st ;
reg pll_done ;
reg [11:0] pll_count ;
reg [2:0] clkgen_ps ;
reg [11:0] pll_count ;
reg [2:0] clkgen_ps ;
reg gen_resetn ; // internally generated reset
reg risc_resetn ; // internally generated reset
reg risc_reset ; // internally generated reset
 
 
assign clkout = app_clk;
144,16 → 141,16
begin
if (!reset_n) begin
gen_resetn <= 0;
risc_resetn <= 0;
risc_reset <= 1;
end else if(run_st ) begin
gen_resetn <= 1;
risc_resetn <= 1;
risc_reset <= 0;
end else if(slave_run_st ) begin
gen_resetn <= 1;
risc_resetn <= 0; // Keet Risc in Reset
risc_reset <= 1; // Keet Risc in Reset
end else begin
gen_resetn <= 0;
risc_resetn <= 0;
risc_reset <= 1;
end
end
 
/rtl/core/digital_core.v
229,7 → 229,7
. xtal_clk (xtal_clk ),
. clkout (clkout ),
. gen_resetn (gen_resetn ),
. risc_resetn (risc_resetn ),
. risc_reset (risc_reset ),
. app_clk (app_clk ),
. uart_ref_clk (uart_clk_16x )
 
442,7 → 442,7
 
 
oc8051_top u_8051_core (
. resetn (risc_resetn ),
. wb_rst_i (risc_reset ),
. wb_clk_i (app_clk ),
 
//interface to data ram
/verif/run/filelist_rtl.f
51,4 → 51,4
../../rtl/model/oc8051_xram.v \
../../rtl/model/oc8051_xrom.v \
../../rtl/msg_handler/msg_handler.v \
../../rtl/msg_handler/msg_handler_top.v
../../rtl/msg_handler/msg_handler_top.v
/verif/run/run_modelsim
11,8 → 11,7
set misc_tests=(uart_test_1 spi_test_1)
#set misc_tests=( )
 
set risc_int_tests=(fib divmul sort gcd cast xram )
#set risc_int_tests=(fib divmul sort gcd cast xram all_instr)
set risc_int_tests=(fib divmul sort gcd cast xram all_instr)
 
echo " Compiling with MODELSIM "
 

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