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URL https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk

Subversion Repositories oms8051mini

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  • This comparison shows the changes necessary to convert path 
    /oms8051mini/trunk
    from Rev 34 to Rev 33
    ↔ Reverse comparison
  •

Rev 34 → Rev 33

/rtl/spi/spi_cfg.v
235,10 → 235,10
// Logic for Register 0 : SPI Control Register
//-----------------------------------------------------------------------
wire cfg_op_req = spi_ctrl[31]; // cpu request
wire [1:0] cfg_tgt_sel = spi_ctrl[29:28]; // target chip select
wire [1:0] cfg_op_type = spi_ctrl[27:26]; // SPI operation type
wire [1:0] cfg_transfer_size = spi_ctrl[25:24]; // SPI transfer size
wire [5:0] cfg_sck_period = spi_ctrl[21:16]; // sck clock period
wire [1:0] cfg_tgt_sel = spi_ctrl[24:23]; // target chip select
wire [1:0] cfg_op_type = spi_ctrl[22:21]; // SPI operation type
wire [1:0] cfg_transfer_size = spi_ctrl[20:19]; // SPI transfer size
wire [5:0] cfg_sck_period = spi_ctrl[18:13]; // sck clock period
wire [4:0] cfg_sck_cs_period = spi_ctrl[12:8]; // cs setup/hold period
wire [7:0] cfg_cs_byte = spi_ctrl[7:0]; // cs bit information
 
/verif/agents/spi/spi_tasks.v
32,12 → 32,12
 
@(posedge tb_top.app_clk)
tb_top.cpu_write(`ADDR_SPACE_SPI,'h4,{datain,24'h0});
tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,1'h0,
tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,6'h0,
spi_chip_no[1:0],
2'b0, // Write Operatopm
2'b0, // Single Transfer
8'h10, // sck clock period
8'h2, // cs setup/hold period
6'h10, // sck clock period
5'h2, // cs setup/hold period
8'h40 }); // cs bit information
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
56,12 → 56,12
begin
@(posedge tb_top.app_clk)
tb_top.cpu_write(`ADDR_SPACE_SPI,'h4,{cmd});
tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,1'h0,
tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,6'h0,
spi_chip_no[1:0],
2'b0, // Write Operatopm
2'h3, // 4 Transfer
8'h10, // sck clock period
8'h2, // cs setup/hold period
6'h10, // sck clock period
5'h2, // cs setup/hold period
cs_byte[7:0] }); // cs bit information
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
81,12 → 81,12
begin
 
@(posedge tb_top.app_clk)
tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,1'h0,
tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,6'h0,
spi_chip_no[1:0],
2'b1, // Read Operatopm
2'h3, // 4 Transfer
8'h10, // sck clock period
8'h2, // cs setup/hold period
6'h10, // sck clock period
5'h2, // cs setup/hold period
cs_byte[7:0] }); // cs bit information
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
110,12 → 110,12
 
@(posedge tb_top.app_clk) ;
tb_top.cpu_write(`ADDR_SPACE_SPI,'h4,{8'hD8,address[23:0]});
tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,1'h0,
tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,6'h0,
spi_chip_no[1:0],
2'b0, // Write Operatopm
2'h3, // 4 Transfer
8'h10, // sck clock period
8'h2, // cs setup/hold period
6'h10, // sck clock period
5'h2, // cs setup/hold period
8'h1 }); // cs bit information
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
231,12 → 231,12
while(exit_flag == 1) begin
 
tb_top.cpu_write(`ADDR_SPACE_SPI,'h4,{8'h05,24'h0});
tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,1'h0,
tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,6'h0,
spi_chip_no[1:0],
2'b0, // Write Operation
2'b0, // 1 Transfer
8'h10, // sck clock period
8'h2, // cs setup/hold period
6'h10, // sck clock period
5'h2, // cs setup/hold period
8'h0 }); // cs bit information
 
 
249,12 → 249,12
// Send Status Request Cmd
 
 
tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,1'h0,
tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,6'h0,
spi_chip_no[1:0],
2'b1, // Read Operation
2'b0, // 1 Transfer
8'h10, // sck clock period
8'h2, // cs setup/hold period
6'h10, // sck clock period
5'h2, // cs setup/hold period
8'h40 }); // cs bit information
 
/verif/sw/C/uart_lb.c
15,9 → 15,11
__xdata __at (0x9001) unsigned char uart_reg1;
__xdata __at (0x9002) unsigned char uart_reg2;
__xdata __at (0x9003) unsigned char uart_reg3;
volatile __xdata __at (0x9004) unsigned char uart_reg4;
__xdata __at (0x9004) unsigned char uart_reg4;
__xdata __at (0x9005) unsigned char uart_tdata;
__xdata __at (0x9006) unsigned char uart_rdata;
__xdata unsigned long *rx_des_base;
__xdata unsigned long *tx_des_base;
 
void main() {
/verif/sw/hex/uart_lb.hex
1,16 → 1,16
:03000000020006F5
:03005F0002000399
:0300030002006296
:100062009090007407F0909002E4F0909003F0906A
:100072009004E0FF20E1F8909006E0FF909005F0F8
:0200820080ED0F
:06003500E478FFF6D8FD9F
:100013007900E94400601B7A00900088780175A09C
:1000230000E493F2A308B8000205A0D9F4DAF2754C
:02003300A0FF2C
:10003B007800E84400600A790175A000E4F309D860
:10004B00FC7800E84400600C7900900001E4F0A318
:04005B00D8FCD9FAFA
:0D000600758108120084E58260030200038A
:04008400758200225F
:03000000020008F3
:0300610002000397
:0500030012006480FE04
:100064009090007407F0909002E4F0909003F0E414
:10007400909004E0FA20E1F8909014E0FA90901047
:03008400F080ED1C
:06003700E478FFF6D8FD9D
:100015007900E94400601B7A0090008B780075A098
:1000250000E493F2A308B8000205A0D9F4DAF2754A
:02003500A0FF2A
:10003D007800E84400600A790075A000E4F309D85F
:10004D00FC7800E84400600C7900900000E4F0A317
:04005D00D8FCD9FAF8
:0D00080075810C120087E582600302000381
:04008700758200225C
:00000001FF
/verif/testcase/dat/uart_lb.dat
2,22 → 2,24
/// created by oc8051 rom maker
/// author: Simon Teran (simont@opencores.org)
///
/// source file: F:\uart_lb.hex
/// date: 10-01-2017
/// time: 19:08:59
/// source file: d:\uart_lb.hex
/// date: 12/9/2016
/// time: 8:50:09 PM
///
02
00
06
02
08
12
00
62
64
80
FE
75
81
08
0C
12
00
84
87
E5
82
60
36,9 → 38,9
00
90
00
88
8B
78
01
00
75
A0
00
73,7 → 75,7
60
0A
79
01
00
75
A0
00
93,7 → 95,7
00
90
00
01
00
E4
F0
A3
119,11 → 121,12
90
03
F0
E4
90
90
04
E0
FF
FA
20
E1
F8
131,7 → 134,7
90
06
E0
FF
FA
90
90
05

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