URL
https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk
Subversion Repositories oms8051mini
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- This comparison shows the changes necessary to convert path
/oms8051mini/trunk
- from Rev 36 to Rev 35
- ↔ Reverse comparison
Rev 36 → Rev 35
/rtl/8051/oc8051_acc.v
125,9 → 125,9
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) |
data_out <= `OC8051_RST_ACC; |
data_out <= #1 `OC8051_RST_ACC; |
else |
data_out <= acc; |
data_out <= #1 acc; |
end |
|
|
/rtl/8051/oc8051_alu_src_sel.v
18,8 → 18,6
////////////////////////////////////////////////////////////////////// |
//// v0.0 - Dinesh A, 5th Jan 2017 |
//// 1. Active edge of reset changed from High to Low |
//// v0.1 - Dinesh A, 19th Jan 2017 |
//// 1. Lint Error fix |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
104,7 → 102,7
`OC8051_AS1_OP3: src1 = op3_r; |
`OC8051_AS1_PCH: src1 = pc[15:8]; |
`OC8051_AS1_PCL: src1 = pc[7:0]; |
default: src1 = 8'h00; |
// default: src1 = 8'h00; |
endcase |
end |
|
142,13 → 140,13
|
always @(posedge clk or negedge resetn) |
if (resetn == 1'b0) begin |
op1_r <= 8'h00; |
op2_r <= 8'h00; |
op3_r <= 8'h00; |
op1_r <= #1 8'h00; |
op2_r <= #1 8'h00; |
op3_r <= #1 8'h00; |
end else begin |
op1_r <= op1; |
op2_r <= op2; |
op3_r <= op3; |
op1_r <= #1 op1; |
op2_r <= #1 op2; |
op3_r <= #1 op3; |
end |
|
endmodule |
/rtl/8051/oc8051_alu_test.v
361,26 → 361,26
|
always @(posedge clk or negedge resetn) |
if (resetn == 1'b0) begin |
ides1_r <= 8'h0; |
ides1_r <= #1 8'h0; |
end else begin |
ides1_r <= ides1; |
ides1_r <= #1 ides1; |
end |
|
always @(posedge clk or negedge resetn) |
if (resetn == 1'b0) begin |
desCy <= 1'b0; |
desAc <= 1'b0; |
desOv <= 1'b0; |
des1 <= 8'h00; |
des2 <= 1'h00; |
des1_r <= 1'h00; |
desCy <= #1 1'b0; |
desAc <= #1 1'b0; |
desOv <= #1 1'b0; |
des1 <= #1 8'h00; |
des2 <= #1 1'h00; |
des1_r <= #1 1'h00; |
end else begin |
desCy <= idesCy; |
desAc <= idesAc; |
desOv <= idesOv; |
des1 <= ides1; |
des2 <= ides2; |
des1_r <= ides1_r; |
desCy <= #1 idesCy; |
desAc <= #1 idesAc; |
desOv <= #1 idesOv; |
des1 <= #1 ides1; |
des2 <= #1 ides2; |
des1_r <= #1 ides1_r; |
end |
|
|
/rtl/8051/oc8051_b_register.v
79,14 → 79,14
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) |
data_out <=`OC8051_RST_B; |
data_out <= #1 `OC8051_RST_B; |
else if (wr) begin |
if (!wr_bit) begin |
if (wr_addr==`OC8051_SFR_B) |
data_out <=data_in; |
data_out <= #1 data_in; |
end else begin |
if (wr_addr[7:3]==`OC8051_SFR_B_B) |
data_out[wr_addr[2:0]] <=bit_in; |
data_out[wr_addr[2:0]] <= #1 bit_in; |
end |
end |
end |
/rtl/8051/oc8051_decoder.v
1319,1407 → 1319,1407
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
ram_wr_sel <= `OC8051_RWS_DC; |
src_sel1 <= `OC8051_AS1_DC; |
src_sel2 <= `OC8051_AS2_DC; |
alu_op <= `OC8051_ALU_NOP; |
wr <= 1'b0; |
psw_set <= `OC8051_PS_NOT; |
cy_sel <= `OC8051_CY_0; |
src_sel3 <= `OC8051_AS3_DC; |
wr_sfr <= `OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end else if (!wait_data) begin |
case (state_dec) /* synopsys parallel_case */ |
2'b01: begin |
casex (op_cur) /* synopsys parallel_case */ |
`OC8051_MOVC_DP :begin |
ram_wr_sel <= `OC8051_RWS_DC; |
src_sel1 <= `OC8051_AS1_OP1; |
src_sel2 <= `OC8051_AS2_DC; |
alu_op <= `OC8051_ALU_NOP; |
wr <= 1'b0; |
psw_set <= `OC8051_PS_NOT; |
wr_sfr <= `OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_OP1; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_MOVC_PC :begin |
ram_wr_sel <= `OC8051_RWS_DC; |
src_sel1 <= `OC8051_AS1_OP1; |
src_sel2 <= `OC8051_AS2_DC; |
alu_op <= `OC8051_ALU_NOP; |
wr <= 1'b0; |
psw_set <= `OC8051_PS_NOT; |
wr_sfr <= `OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_OP1; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_MOVX_PA : begin |
ram_wr_sel <= `OC8051_RWS_DC; |
src_sel1 <= `OC8051_AS1_OP1; |
src_sel2 <= `OC8051_AS2_DC; |
alu_op <= `OC8051_ALU_NOP; |
wr <= 1'b0; |
psw_set <= `OC8051_PS_NOT; |
wr_sfr <= `OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_OP1; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_MOVX_IA : begin |
ram_wr_sel <= `OC8051_RWS_DC; |
src_sel1 <= `OC8051_AS1_OP1; |
src_sel2 <= `OC8051_AS2_DC; |
alu_op <= `OC8051_ALU_NOP; |
wr <= 1'b0; |
psw_set <= `OC8051_PS_NOT; |
wr_sfr <= `OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_OP1; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_DIV : begin |
ram_wr_sel <= `OC8051_RWS_B; |
src_sel1 <= `OC8051_AS1_ACC; |
src_sel2 <= `OC8051_AS2_RAM; |
alu_op <= `OC8051_ALU_DIV; |
wr <= 1'b1; |
psw_set <= `OC8051_PS_OV; |
wr_sfr <= `OC8051_WRS_ACC2; |
ram_wr_sel <= #1 `OC8051_RWS_B; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_DIV; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_OV; |
wr_sfr <= #1 `OC8051_WRS_ACC2; |
end |
`OC8051_MUL : begin |
ram_wr_sel <= `OC8051_RWS_B; |
src_sel1 <= `OC8051_AS1_ACC; |
src_sel2 <= `OC8051_AS2_RAM; |
alu_op <= `OC8051_ALU_MUL; |
wr <= 1'b1; |
psw_set <= `OC8051_PS_OV; |
wr_sfr <=`OC8051_WRS_ACC2; |
ram_wr_sel <= #1 `OC8051_RWS_B; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_MUL; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_OV; |
wr_sfr <= #1 `OC8051_WRS_ACC2; |
end |
default begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
endcase |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
end |
2'b10: begin |
casex (op_cur) /* synopsys parallel_case */ |
`OC8051_ACALL :begin |
ram_wr_sel <=`OC8051_RWS_SP; |
src_sel1 <=`OC8051_AS1_PCH; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
ram_wr_sel <= #1 `OC8051_RWS_SP; |
src_sel1 <= #1 `OC8051_AS1_PCH; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
end |
`OC8051_LCALL :begin |
ram_wr_sel <=`OC8051_RWS_SP; |
src_sel1 <=`OC8051_AS1_PCH; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
ram_wr_sel <= #1 `OC8051_RWS_SP; |
src_sel1 <= #1 `OC8051_AS1_PCH; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
end |
`OC8051_JBC : begin |
ram_wr_sel <=`OC8051_RWS_D; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
ram_wr_sel <= #1 `OC8051_RWS_D; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
end |
`OC8051_DIV : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_RAM; |
alu_op <=`OC8051_ALU_DIV; |
wr <=1'b0; |
psw_set <=`OC8051_PS_OV; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_DIV; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_OV; |
end |
`OC8051_MUL : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_RAM; |
alu_op <=`OC8051_ALU_MUL; |
wr <=1'b0; |
psw_set <=`OC8051_PS_OV; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_MUL; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_OV; |
end |
default begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
end |
endcase |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
|
2'b11: begin |
casex (op_cur) /* synopsys parallel_case */ |
`OC8051_RET : begin |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
psw_set <=`OC8051_PS_NOT; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
psw_set <= #1 `OC8051_PS_NOT; |
end |
`OC8051_RETI : begin |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
psw_set <=`OC8051_PS_NOT; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
psw_set <= #1 `OC8051_PS_NOT; |
end |
`OC8051_DIV : begin |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_RAM; |
alu_op <=`OC8051_ALU_DIV; |
psw_set <=`OC8051_PS_OV; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_DIV; |
psw_set <= #1 `OC8051_PS_OV; |
end |
`OC8051_MUL : begin |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_RAM; |
alu_op <=`OC8051_ALU_MUL; |
psw_set <=`OC8051_PS_OV; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_MUL; |
psw_set <= #1 `OC8051_PS_OV; |
end |
default begin |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
psw_set <=`OC8051_PS_NOT; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
psw_set <= #1 `OC8051_PS_NOT; |
end |
endcase |
ram_wr_sel <=`OC8051_RWS_DC; |
wr <=1'b0; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
wr <= #1 1'b0; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
default: begin |
casex (op_cur) /* synopsys parallel_case */ |
`OC8051_ACALL :begin |
ram_wr_sel <=`OC8051_RWS_SP; |
src_sel1 <=`OC8051_AS1_PCL; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_SP; |
src_sel1 <= #1 `OC8051_AS1_PCL; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_AJMP : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_ADD_R : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_RAM; |
alu_op <=`OC8051_ALU_ADD; |
wr <=1'b0; |
psw_set <=`OC8051_PS_AC; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_ADD; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_AC; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_ADDC_R : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_RAM; |
alu_op <=`OC8051_ALU_ADD; |
wr <=1'b0; |
psw_set <=`OC8051_PS_AC; |
cy_sel <=`OC8051_CY_PSW; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_ADD; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_AC; |
cy_sel <= #1 `OC8051_CY_PSW; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_ANL_R : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_RAM; |
alu_op <=`OC8051_ALU_AND; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_AND; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_CJNE_R : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_OP2; |
alu_op <=`OC8051_ALU_SUB; |
wr <=1'b0; |
psw_set <=`OC8051_PS_CY; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_OP2; |
alu_op <= #1 `OC8051_ALU_SUB; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_CY; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_DEC_R : begin |
ram_wr_sel <=`OC8051_RWS_RN; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_ZERO; |
alu_op <=`OC8051_ALU_INC; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_1; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_RN; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_ZERO; |
alu_op <= #1 `OC8051_ALU_INC; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_1; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_DJNZ_R : begin |
ram_wr_sel <=`OC8051_RWS_RN; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_ZERO; |
alu_op <=`OC8051_ALU_INC; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_1; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_RN; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_ZERO; |
alu_op <= #1 `OC8051_ALU_INC; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_1; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_INC_R : begin |
ram_wr_sel <=`OC8051_RWS_RN; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_ZERO; |
alu_op <=`OC8051_ALU_INC; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_RN; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_ZERO; |
alu_op <= #1 `OC8051_ALU_INC; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_MOV_R : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_MOV_AR : begin |
ram_wr_sel <=`OC8051_RWS_RN; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_RN; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_MOV_DR : begin |
ram_wr_sel <=`OC8051_RWS_RN; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_RN; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_MOV_CR : begin |
ram_wr_sel <=`OC8051_RWS_RN; |
src_sel1 <=`OC8051_AS1_OP2; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_RN; |
src_sel1 <= #1 `OC8051_AS1_OP2; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_MOV_RD : begin |
ram_wr_sel <=`OC8051_RWS_D; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_D; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_ORL_R : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_ACC; |
alu_op <=`OC8051_ALU_OR; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_ACC; |
alu_op <= #1 `OC8051_ALU_OR; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_SUBB_R : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_RAM; |
alu_op <=`OC8051_ALU_SUB; |
wr <=1'b0; |
psw_set <=`OC8051_PS_AC; |
cy_sel <=`OC8051_CY_PSW; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_SUB; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_AC; |
cy_sel <= #1 `OC8051_CY_PSW; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_XCH_R : begin |
ram_wr_sel <=`OC8051_RWS_RN; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_ACC; |
alu_op <=`OC8051_ALU_XCH; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_1; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC2; |
ram_wr_sel <= #1 `OC8051_RWS_RN; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_ACC; |
alu_op <= #1 `OC8051_ALU_XCH; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_1; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC2; |
end |
`OC8051_XRL_R : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_ACC; |
alu_op <=`OC8051_ALU_XOR; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_ACC; |
alu_op <= #1 `OC8051_ALU_XOR; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
|
//op_code [7:1] |
`OC8051_ADD_I : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_RAM; |
alu_op <=`OC8051_ALU_ADD; |
wr <=1'b0; |
psw_set <=`OC8051_PS_AC; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_ADD; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_AC; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_ADDC_I : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_RAM; |
alu_op <=`OC8051_ALU_ADD; |
wr <=1'b0; |
psw_set <=`OC8051_PS_AC; |
cy_sel <=`OC8051_CY_PSW; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_ADD; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_AC; |
cy_sel <= #1 `OC8051_CY_PSW; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_ANL_I : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_RAM; |
alu_op <=`OC8051_ALU_AND; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_AND; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_CJNE_I : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_OP2; |
alu_op <=`OC8051_ALU_SUB; |
wr <=1'b0; |
psw_set <=`OC8051_PS_CY; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_OP2; |
alu_op <= #1 `OC8051_ALU_SUB; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_CY; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_DEC_I : begin |
ram_wr_sel <=`OC8051_RWS_I; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_ZERO; |
alu_op <=`OC8051_ALU_INC; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_1; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_I; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_ZERO; |
alu_op <= #1 `OC8051_ALU_INC; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_1; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_INC_I : begin |
ram_wr_sel <=`OC8051_RWS_I; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_ZERO; |
alu_op <=`OC8051_ALU_INC; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_I; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_ZERO; |
alu_op <= #1 `OC8051_ALU_INC; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_MOV_I : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_MOV_ID : begin |
ram_wr_sel <=`OC8051_RWS_D; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_D; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_MOV_AI : begin |
ram_wr_sel <=`OC8051_RWS_I; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_I; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_MOV_DI : begin |
ram_wr_sel <=`OC8051_RWS_I; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_I; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_MOV_CI : begin |
ram_wr_sel <=`OC8051_RWS_I; |
src_sel1 <=`OC8051_AS1_OP2; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_I; |
src_sel1 <= #1 `OC8051_AS1_OP2; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_MOVX_IA : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_MOVX_AI :begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_ORL_I : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_ACC; |
alu_op <=`OC8051_ALU_OR; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_ACC; |
alu_op <= #1 `OC8051_ALU_OR; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_SUBB_I : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_RAM; |
alu_op <=`OC8051_ALU_SUB; |
wr <=1'b0; |
psw_set <=`OC8051_PS_AC; |
cy_sel <=`OC8051_CY_PSW; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_SUB; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_AC; |
cy_sel <= #1 `OC8051_CY_PSW; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_XCH_I : begin |
ram_wr_sel <=`OC8051_RWS_I; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_ACC; |
alu_op <=`OC8051_ALU_XCH; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_1; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC2; |
ram_wr_sel <= #1 `OC8051_RWS_I; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_ACC; |
alu_op <= #1 `OC8051_ALU_XCH; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_1; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC2; |
end |
`OC8051_XCHD :begin |
ram_wr_sel <=`OC8051_RWS_I; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_ACC; |
alu_op <=`OC8051_ALU_XCH; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC2; |
ram_wr_sel <= #1 `OC8051_RWS_I; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_ACC; |
alu_op <= #1 `OC8051_ALU_XCH; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC2; |
end |
`OC8051_XRL_I : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_ACC; |
alu_op <=`OC8051_ALU_XOR; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_ACC; |
alu_op <= #1 `OC8051_ALU_XOR; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
|
//op_code [7:0] |
`OC8051_ADD_D : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_RAM; |
alu_op <=`OC8051_ALU_ADD; |
wr <=1'b0; |
psw_set <=`OC8051_PS_AC; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_ADD; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_AC; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_ADD_C : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_OP2; |
src_sel2 <=`OC8051_AS2_ACC; |
alu_op <=`OC8051_ALU_ADD; |
wr <=1'b0; |
psw_set <=`OC8051_PS_AC; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_OP2; |
src_sel2 <= #1 `OC8051_AS2_ACC; |
alu_op <= #1 `OC8051_ALU_ADD; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_AC; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_ADDC_D : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_RAM; |
alu_op <=`OC8051_ALU_ADD; |
wr <=1'b0; |
psw_set <=`OC8051_PS_AC; |
cy_sel <=`OC8051_CY_PSW; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_ADD; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_AC; |
cy_sel <= #1 `OC8051_CY_PSW; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_ADDC_C : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_OP2; |
src_sel2 <=`OC8051_AS2_ACC; |
alu_op <=`OC8051_ALU_ADD; |
wr <=1'b0; |
psw_set <=`OC8051_PS_AC; |
cy_sel <=`OC8051_CY_PSW; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_OP2; |
src_sel2 <= #1 `OC8051_AS2_ACC; |
alu_op <= #1 `OC8051_ALU_ADD; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_AC; |
cy_sel <= #1 `OC8051_CY_PSW; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_ANL_D : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_RAM; |
alu_op <=`OC8051_ALU_AND; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_AND; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_ANL_C : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_OP2; |
src_sel2 <=`OC8051_AS2_ACC; |
alu_op <=`OC8051_ALU_AND; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_OP2; |
src_sel2 <= #1 `OC8051_AS2_ACC; |
alu_op <= #1 `OC8051_ALU_AND; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_ANL_DD : begin |
ram_wr_sel <=`OC8051_RWS_D; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_RAM; |
alu_op <=`OC8051_ALU_AND; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_D; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_AND; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_ANL_DC : begin |
ram_wr_sel <=`OC8051_RWS_D; |
src_sel1 <=`OC8051_AS1_OP3; |
src_sel2 <=`OC8051_AS2_RAM; |
alu_op <=`OC8051_ALU_AND; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_D; |
src_sel1 <= #1 `OC8051_AS1_OP3; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_AND; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_ANL_B : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_AND; |
wr <=1'b0; |
psw_set <=`OC8051_PS_CY; |
cy_sel <=`OC8051_CY_PSW; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_AND; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_CY; |
cy_sel <= #1 `OC8051_CY_PSW; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_ANL_NB : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_RR; |
wr <=1'b0; |
psw_set <=`OC8051_PS_CY; |
cy_sel <=`OC8051_CY_PSW; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_RR; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_CY; |
cy_sel <= #1 `OC8051_CY_PSW; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_CJNE_D : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_RAM; |
alu_op <=`OC8051_ALU_SUB; |
wr <=1'b0; |
psw_set <=`OC8051_PS_CY; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_SUB; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_CY; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_CJNE_C : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_OP2; |
alu_op <=`OC8051_ALU_SUB; |
wr <=1'b0; |
psw_set <=`OC8051_PS_CY; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_OP2; |
alu_op <= #1 `OC8051_ALU_SUB; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_CY; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_CLR_A : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_ACC; |
alu_op <=`OC8051_ALU_SUB; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_PC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_ACC; |
alu_op <= #1 `OC8051_ALU_SUB; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_PC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_CLR_C : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_CY; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_PC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_CY; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_PC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_CLR_B : begin |
ram_wr_sel <=`OC8051_RWS_D; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_PC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_D; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_PC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_CPL_A : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOT; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOT; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_CPL_C : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOT; |
wr <=1'b0; |
psw_set <=`OC8051_PS_CY; |
cy_sel <=`OC8051_CY_PSW; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOT; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_CY; |
cy_sel <= #1 `OC8051_CY_PSW; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_CPL_B : begin |
ram_wr_sel <=`OC8051_RWS_D; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOT; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_RAM; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_D; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOT; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_RAM; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_DA : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_DA; |
wr <=1'b0; |
psw_set <=`OC8051_PS_CY; |
cy_sel <=`OC8051_CY_PSW; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_DA; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_CY; |
cy_sel <= #1 `OC8051_CY_PSW; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_DEC_A : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_ZERO; |
alu_op <=`OC8051_ALU_INC; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_1; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_ZERO; |
alu_op <= #1 `OC8051_ALU_INC; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_1; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_DEC_D : begin |
ram_wr_sel <=`OC8051_RWS_D; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_ZERO; |
alu_op <=`OC8051_ALU_INC; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_1; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_D; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_ZERO; |
alu_op <= #1 `OC8051_ALU_INC; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_1; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_DIV : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_RAM; |
alu_op <=`OC8051_ALU_DIV; |
wr <=1'b0; |
psw_set <=`OC8051_PS_OV; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_DIV; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_OV; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_DJNZ_D : begin |
ram_wr_sel <=`OC8051_RWS_D; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_ZERO; |
alu_op <=`OC8051_ALU_INC; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_1; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_D; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_ZERO; |
alu_op <= #1 `OC8051_ALU_INC; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_1; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_INC_A : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_ZERO; |
alu_op <=`OC8051_ALU_INC; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_ZERO; |
alu_op <= #1 `OC8051_ALU_INC; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_INC_D : begin |
ram_wr_sel <=`OC8051_RWS_D; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_ZERO; |
alu_op <=`OC8051_ALU_INC; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_D; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_ZERO; |
alu_op <= #1 `OC8051_ALU_INC; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_INC_DP : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_ZERO; |
alu_op <=`OC8051_ALU_ADD; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_1; |
src_sel3 <=`OC8051_AS3_DP; |
wr_sfr <=`OC8051_WRS_DPTR; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_ZERO; |
alu_op <= #1 `OC8051_ALU_ADD; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_1; |
src_sel3 <= #1 `OC8051_AS3_DP; |
wr_sfr <= #1 `OC8051_WRS_DPTR; |
end |
`OC8051_JB : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_PC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_PC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_JBC :begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_PC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_PC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_JC : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_PC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_PC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_JMP_D : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_RAM; |
alu_op <=`OC8051_ALU_ADD; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DP; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_ADD; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DP; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_JNB : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_PC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_PC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_JNC : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_PC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_PC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_JNZ :begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_PC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_PC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_JZ : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_PC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_PC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_LCALL :begin |
ram_wr_sel <=`OC8051_RWS_SP; |
src_sel1 <=`OC8051_AS1_PCL; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_SP; |
src_sel1 <= #1 `OC8051_AS1_PCL; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_LJMP : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_MOV_D : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_MOV_C : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_OP2; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_OP2; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_MOV_DA : begin |
ram_wr_sel <=`OC8051_RWS_D; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_D; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_MOV_DD : begin |
ram_wr_sel <=`OC8051_RWS_D3; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_D3; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_MOV_CD : begin |
ram_wr_sel <=`OC8051_RWS_D; |
src_sel1 <=`OC8051_AS1_OP3; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_D; |
src_sel1 <= #1 `OC8051_AS1_OP3; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_MOV_BC : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_CY; |
cy_sel <=`OC8051_CY_RAM; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_CY; |
cy_sel <= #1 `OC8051_CY_RAM; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_MOV_CB : begin |
ram_wr_sel <=`OC8051_RWS_D; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_PSW; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_D; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_PSW; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_MOV_DP : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_OP3; |
src_sel2 <=`OC8051_AS2_OP2; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_DPTR; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_OP3; |
src_sel2 <= #1 `OC8051_AS2_OP2; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_DPTR; |
end |
`OC8051_MOVC_DP :begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_RAM; |
alu_op <=`OC8051_ALU_ADD; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DP; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_ADD; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DP; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_MOVC_PC : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_PCL; |
src_sel2 <=`OC8051_AS2_ACC; |
alu_op <=`OC8051_ALU_ADD; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_PC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_PCL; |
src_sel2 <= #1 `OC8051_AS2_ACC; |
alu_op <= #1 `OC8051_ALU_ADD; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_PC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_MOVX_PA : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_MOVX_AP : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_MUL : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_RAM; |
alu_op <=`OC8051_ALU_MUL; |
wr <=1'b0; |
psw_set <=`OC8051_PS_OV; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_MUL; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_OV; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_ORL_D : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_ACC; |
alu_op <=`OC8051_ALU_OR; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_ACC; |
alu_op <= #1 `OC8051_ALU_OR; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_ORL_C : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_OP2; |
src_sel2 <=`OC8051_AS2_ACC; |
alu_op <=`OC8051_ALU_OR; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_OP2; |
src_sel2 <= #1 `OC8051_AS2_ACC; |
alu_op <= #1 `OC8051_ALU_OR; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_ORL_AD : begin |
ram_wr_sel <=`OC8051_RWS_D; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_ACC; |
alu_op <=`OC8051_ALU_OR; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_D; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_ACC; |
alu_op <= #1 `OC8051_ALU_OR; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_ORL_CD : begin |
ram_wr_sel <=`OC8051_RWS_D; |
src_sel1 <=`OC8051_AS1_OP3; |
src_sel2 <=`OC8051_AS2_RAM; |
alu_op <=`OC8051_ALU_OR; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_D; |
src_sel1 <= #1 `OC8051_AS1_OP3; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_OR; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_ORL_B : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_OR; |
wr <=1'b0; |
psw_set <=`OC8051_PS_CY; |
cy_sel <=`OC8051_CY_PSW; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_OR; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_CY; |
cy_sel <= #1 `OC8051_CY_PSW; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_ORL_NB : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_RL; |
wr <=1'b0; |
psw_set <=`OC8051_PS_CY; |
cy_sel <=`OC8051_CY_PSW; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_RL; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_CY; |
cy_sel <= #1 `OC8051_CY_PSW; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_POP : begin |
ram_wr_sel <=`OC8051_RWS_D; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_D; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_PUSH : begin |
ram_wr_sel <=`OC8051_RWS_SP; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_SP; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_RET : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_RETI : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_RL : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_RL; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_RL; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_RLC : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_RLC; |
wr <=1'b0; |
psw_set <=`OC8051_PS_CY; |
cy_sel <=`OC8051_CY_PSW; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_RLC; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_CY; |
cy_sel <= #1 `OC8051_CY_PSW; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_RR : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_RR; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_RR; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_RRC : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_RRC; |
wr <=1'b0; |
psw_set <=`OC8051_PS_CY; |
cy_sel <=`OC8051_CY_PSW; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_RRC; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_CY; |
cy_sel <= #1 `OC8051_CY_PSW; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_SETB_C : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_CY; |
cy_sel <=`OC8051_CY_1; |
src_sel3 <=`OC8051_AS3_PC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_CY; |
cy_sel <= #1 `OC8051_CY_1; |
src_sel3 <= #1 `OC8051_AS3_PC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_SETB_B : begin |
ram_wr_sel <=`OC8051_RWS_D; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_1; |
src_sel3 <=`OC8051_AS3_PC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_D; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_1; |
src_sel3 <= #1 `OC8051_AS3_PC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_SJMP : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_PC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_PC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_SUBB_D : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_RAM; |
alu_op <=`OC8051_ALU_SUB; |
wr <=1'b0; |
psw_set <=`OC8051_PS_AC; |
cy_sel <=`OC8051_CY_PSW; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_SUB; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_AC; |
cy_sel <= #1 `OC8051_CY_PSW; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_SUBB_C : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_OP2; |
alu_op <=`OC8051_ALU_SUB; |
wr <=1'b0; |
psw_set <=`OC8051_PS_AC; |
cy_sel <=`OC8051_CY_PSW; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_OP2; |
alu_op <= #1 `OC8051_ALU_SUB; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_AC; |
cy_sel <= #1 `OC8051_CY_PSW; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_SWAP : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_ACC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_RLC; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC2; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_RLC; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC2; |
end |
`OC8051_XCH_D : begin |
ram_wr_sel <=`OC8051_RWS_D; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_ACC; |
alu_op <=`OC8051_ALU_XCH; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_1; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC2; |
ram_wr_sel <= #1 `OC8051_RWS_D; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_ACC; |
alu_op <= #1 `OC8051_ALU_XCH; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_1; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC2; |
end |
`OC8051_XRL_D : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_ACC; |
alu_op <=`OC8051_ALU_XOR; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_ACC; |
alu_op <= #1 `OC8051_ALU_XOR; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_XRL_C : begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_OP2; |
src_sel2 <=`OC8051_AS2_ACC; |
alu_op <=`OC8051_ALU_XOR; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_ACC1; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_OP2; |
src_sel2 <= #1 `OC8051_AS2_ACC; |
alu_op <= #1 `OC8051_ALU_XOR; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_ACC1; |
end |
`OC8051_XRL_AD : begin |
ram_wr_sel <=`OC8051_RWS_D; |
src_sel1 <=`OC8051_AS1_RAM; |
src_sel2 <=`OC8051_AS2_ACC; |
alu_op <=`OC8051_ALU_XOR; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_D; |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_ACC; |
alu_op <= #1 `OC8051_ALU_XOR; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_XRL_CD : begin |
ram_wr_sel <=`OC8051_RWS_D; |
src_sel1 <=`OC8051_AS1_OP3; |
src_sel2 <=`OC8051_AS2_RAM; |
alu_op <=`OC8051_ALU_XOR; |
wr <=1'b1; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_D; |
src_sel1 <= #1 `OC8051_AS1_OP3; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_XOR; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
default: begin |
ram_wr_sel <=`OC8051_RWS_DC; |
src_sel1 <=`OC8051_AS1_DC; |
src_sel2 <=`OC8051_AS2_DC; |
alu_op <=`OC8051_ALU_NOP; |
wr <=1'b0; |
psw_set <=`OC8051_PS_NOT; |
cy_sel <=`OC8051_CY_0; |
src_sel3 <=`OC8051_AS3_DC; |
wr_sfr <=`OC8051_WRS_N; |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_DC; |
src_sel2 <= #1 `OC8051_AS2_DC; |
alu_op <= #1 `OC8051_ALU_NOP; |
wr <= #1 1'b0; |
psw_set <= #1 `OC8051_PS_NOT; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end |
endcase |
end |
2731,8 → 2731,8
// |
// remember current instruction |
always @(posedge clk or negedge resetn) |
if (resetn == 1'b0) op <=2'b00; |
else if (state==2'b00) op <=op_in; |
if (resetn == 1'b0) op <= #1 2'b00; |
else if (state==2'b00) op <= #1 op_in; |
|
// |
// in case of instructions that needs more than one clock set state |
2739,45 → 2739,45
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) |
state <=2'b11; |
state <= #1 2'b11; |
else if (!mem_wait & !wait_data) begin |
case (state) /* synopsys parallel_case */ |
2'b10: state <=2'b01; |
2'b11: state <=2'b10; |
2'b10: state <= #1 2'b01; |
2'b11: state <= #1 2'b10; |
2'b00: |
casex (op_in) /* synopsys full_case parallel_case */ |
`OC8051_ACALL : state <=2'b10; |
`OC8051_AJMP : state <=2'b10; |
`OC8051_CJNE_R : state <=2'b10; |
`OC8051_CJNE_I : state <=2'b10; |
`OC8051_CJNE_D : state <=2'b10; |
`OC8051_CJNE_C : state <=2'b10; |
`OC8051_LJMP : state <=2'b10; |
`OC8051_DJNZ_R : state <=2'b10; |
`OC8051_DJNZ_D : state <=2'b10; |
`OC8051_LCALL : state <=2'b10; |
`OC8051_MOVC_DP : state <=2'b11; |
`OC8051_MOVC_PC : state <=2'b11; |
`OC8051_MOVX_IA : state <=2'b10; |
`OC8051_MOVX_AI : state <=2'b10; |
`OC8051_MOVX_PA : state <=2'b10; |
`OC8051_MOVX_AP : state <=2'b10; |
`OC8051_RET : state <=2'b11; |
`OC8051_RETI : state <=2'b11; |
`OC8051_SJMP : state <=2'b10; |
`OC8051_JB : state <=2'b10; |
`OC8051_JBC : state <=2'b10; |
`OC8051_JC : state <=2'b10; |
`OC8051_JMP_D : state <=2'b10; |
`OC8051_JNC : state <=2'b10; |
`OC8051_JNB : state <=2'b10; |
`OC8051_JNZ : state <=2'b10; |
`OC8051_JZ : state <=2'b10; |
`OC8051_DIV : state <=2'b11; |
`OC8051_MUL : state <=2'b11; |
default : state <=2'b00; |
`OC8051_ACALL : state <= #1 2'b10; |
`OC8051_AJMP : state <= #1 2'b10; |
`OC8051_CJNE_R : state <= #1 2'b10; |
`OC8051_CJNE_I : state <= #1 2'b10; |
`OC8051_CJNE_D : state <= #1 2'b10; |
`OC8051_CJNE_C : state <= #1 2'b10; |
`OC8051_LJMP : state <= #1 2'b10; |
`OC8051_DJNZ_R : state <= #1 2'b10; |
`OC8051_DJNZ_D : state <= #1 2'b10; |
`OC8051_LCALL : state <= #1 2'b10; |
`OC8051_MOVC_DP : state <= #1 2'b11; |
`OC8051_MOVC_PC : state <= #1 2'b11; |
`OC8051_MOVX_IA : state <= #1 2'b10; |
`OC8051_MOVX_AI : state <= #1 2'b10; |
`OC8051_MOVX_PA : state <= #1 2'b10; |
`OC8051_MOVX_AP : state <= #1 2'b10; |
`OC8051_RET : state <= #1 2'b11; |
`OC8051_RETI : state <= #1 2'b11; |
`OC8051_SJMP : state <= #1 2'b10; |
`OC8051_JB : state <= #1 2'b10; |
`OC8051_JBC : state <= #1 2'b10; |
`OC8051_JC : state <= #1 2'b10; |
`OC8051_JMP_D : state <= #1 2'b10; |
`OC8051_JNC : state <= #1 2'b10; |
`OC8051_JNB : state <= #1 2'b10; |
`OC8051_JNZ : state <= #1 2'b10; |
`OC8051_JZ : state <= #1 2'b10; |
`OC8051_DIV : state <= #1 2'b11; |
`OC8051_MUL : state <= #1 2'b11; |
// default : state <= #1 2'b00; |
endcase |
default: state <=2'b00; |
default: state <= #1 2'b00; |
endcase |
end |
end |
2788,18 → 2788,18
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
mem_act <=`OC8051_MAS_NO; |
mem_act <= #1 `OC8051_MAS_NO; |
end else if (!rd) begin |
mem_act <=`OC8051_MAS_NO; |
mem_act <= #1 `OC8051_MAS_NO; |
end else |
casex (op_cur) /* synopsys parallel_case */ |
`OC8051_MOVX_AI : mem_act <=`OC8051_MAS_RI_W; |
`OC8051_MOVX_AP : mem_act <=`OC8051_MAS_DPTR_W; |
`OC8051_MOVX_IA : mem_act <=`OC8051_MAS_RI_R; |
`OC8051_MOVX_PA : mem_act <=`OC8051_MAS_DPTR_R; |
`OC8051_MOVC_DP : mem_act <=`OC8051_MAS_CODE; |
`OC8051_MOVC_PC : mem_act <=`OC8051_MAS_CODE; |
default : mem_act <=`OC8051_MAS_NO; |
`OC8051_MOVX_AI : mem_act <= #1 `OC8051_MAS_RI_W; |
`OC8051_MOVX_AP : mem_act <= #1 `OC8051_MAS_DPTR_W; |
`OC8051_MOVX_IA : mem_act <= #1 `OC8051_MAS_RI_R; |
`OC8051_MOVX_PA : mem_act <= #1 `OC8051_MAS_DPTR_R; |
`OC8051_MOVC_DP : mem_act <= #1 `OC8051_MAS_CODE; |
`OC8051_MOVC_PC : mem_act <= #1 `OC8051_MAS_CODE; |
default : mem_act <= #1 `OC8051_MAS_NO; |
endcase |
end |
|
2806,9 → 2806,9
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
ram_rd_sel_r <=3'h0; |
ram_rd_sel_r <= #1 3'h0; |
end else begin |
ram_rd_sel_r <=ram_rd_sel; |
ram_rd_sel_r <= #1 ram_rd_sel; |
end |
end |
|
/rtl/8051/oc8051_divide.v
112,13 → 112,13
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
cycle <= 2'b0; |
tmp_div <= 6'h0; |
tmp_rem <= 8'h0; |
cycle <= #1 2'b0; |
tmp_div <= #1 6'h0; |
tmp_rem <= #1 8'h0; |
end else begin |
if (enable) cycle <= cycle + 2'b1; |
tmp_div <= div_out[5:0]; |
tmp_rem <= rem_out; |
if (enable) cycle <= #1 cycle + 2'b1; |
tmp_div <= #1 div_out[5:0]; |
tmp_rem <= #1 rem_out; |
end |
end |
|
/rtl/8051/oc8051_dptr.v
86,19 → 86,19
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
data_hi <= `OC8051_RST_DPH; |
data_lo <= `OC8051_RST_DPL; |
data_hi <= #1 `OC8051_RST_DPH; |
data_lo <= #1 `OC8051_RST_DPL; |
end else if (wr_sfr==`OC8051_WRS_DPTR) begin |
// |
//write from destination 2 and 1 |
data_hi <= data2_in; |
data_lo <= data_in; |
data_hi <= #1 data2_in; |
data_lo <= #1 data_in; |
end else if ((addr==`OC8051_SFR_DPTR_HI) & (wr) & !(wr_bit)) |
// |
//case of writing to dptr |
data_hi <= data_in; |
data_hi <= #1 data_in; |
else if ((addr==`OC8051_SFR_DPTR_LO) & (wr) & !(wr_bit)) |
data_lo <= data_in; |
data_lo <= #1 data_in; |
end |
|
endmodule |
/rtl/8051/oc8051_indi_addr.v
19,8 → 19,6
////////////////////////////////////////////////////////////////////// |
//// v0.0 - Dinesh A, 5th Jan 2017 |
//// 1. Active edge of reset changed from High to Low |
//// v0.1 - Dinesh A, 19th Jan 2017 |
//// 1. Lint warning fixes |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
108,7 → 106,6
8'h11: buff[3'b101] <= #1 data_in; |
8'h18: buff[3'b110] <= #1 data_in; |
8'h19: buff[3'b111] <= #1 data_in; |
default : buff[3'b000] <= #1 data_in; |
endcase |
end |
end |
/rtl/8051/oc8051_int.v
160,11 → 160,11
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
ip <=`OC8051_RST_IP; |
ip <=#1 `OC8051_RST_IP; |
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin |
ip <= data_in; |
ip <= #1 data_in; |
end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP)) |
ip[wr_addr[2:0]] <= bit_in; |
ip[wr_addr[2:0]] <= #1 bit_in; |
end |
|
// |
172,11 → 172,11
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
ie <=`OC8051_RST_IE; |
ie <=#1 `OC8051_RST_IE; |
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin |
ie <= data_in; |
ie <= #1 data_in; |
end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE)) |
ie[wr_addr[2:0]] <= bit_in; |
ie[wr_addr[2:0]] <= #1 bit_in; |
end |
|
// |
185,15 → 185,15
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
tcon_s <=4'b0000; |
tcon_s <=#1 4'b0000; |
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin |
tcon_s <= {data_in[6], data_in[4], data_in[2], data_in[0]}; |
tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]}; |
end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin |
case (wr_addr[2:0]) /* synopsys full_case parallel_case */ |
3'b000: tcon_s[0] <= bit_in; |
3'b010: tcon_s[1] <= bit_in; |
3'b100: tcon_s[2] <= bit_in; |
3'b110: tcon_s[3] <= bit_in; |
3'b000: tcon_s[0] <= #1 bit_in; |
3'b010: tcon_s[1] <= #1 bit_in; |
3'b100: tcon_s[2] <= #1 bit_in; |
3'b110: tcon_s[3] <= #1 bit_in; |
endcase |
end |
end |
204,15 → 204,15
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
tcon_tf1 <=1'b0; |
tcon_tf1 <=#1 1'b0; |
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin |
tcon_tf1 <= data_in[7]; |
tcon_tf1 <= #1 data_in[7]; |
end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin |
tcon_tf1 <= bit_in; |
tcon_tf1 <= #1 bit_in; |
end else if (!(tf1_buff) & (tf1)) begin |
tcon_tf1 <= 1'b1; |
tcon_tf1 <= #1 1'b1; |
end else if (ack & (isrc_cur==`OC8051_ISRC_TF1)) begin |
tcon_tf1 <= 1'b0; |
tcon_tf1 <= #1 1'b0; |
end |
end |
|
222,15 → 222,15
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
tcon_tf0 <=1'b0; |
tcon_tf0 <=#1 1'b0; |
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin |
tcon_tf0 <= data_in[5]; |
tcon_tf0 <= #1 data_in[5]; |
end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin |
tcon_tf0 <= bit_in; |
tcon_tf0 <= #1 bit_in; |
end else if (!(tf0_buff) & (tf0)) begin |
tcon_tf0 <= 1'b1; |
tcon_tf0 <= #1 1'b1; |
end else if (ack & (isrc_cur==`OC8051_ISRC_TF0)) begin |
tcon_tf0 <= 1'b0; |
tcon_tf0 <= #1 1'b0; |
end |
end |
|
241,17 → 241,17
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
tcon_ie0 <=1'b0; |
tcon_ie0 <=#1 1'b0; |
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin |
tcon_ie0 <= data_in[1]; |
tcon_ie0 <= #1 data_in[1]; |
end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin |
tcon_ie0 <= bit_in; |
tcon_ie0 <= #1 bit_in; |
end else if (((tcon_s[0]) & (ie0_buff) & !(ie0)) | (!(tcon_s[0]) & !(ie0))) begin |
tcon_ie0 <= 1'b1; |
tcon_ie0 <= #1 1'b1; |
end else if (ack & (isrc_cur==`OC8051_ISRC_IE0) & (tcon_s[0])) begin |
tcon_ie0 <= 1'b0; |
tcon_ie0 <= #1 1'b0; |
end else if (!(tcon_s[0]) & (ie0)) begin |
tcon_ie0 <= 1'b0; |
tcon_ie0 <= #1 1'b0; |
end |
end |
|
262,17 → 262,17
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
tcon_ie1 <=1'b0; |
tcon_ie1 <=#1 1'b0; |
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin |
tcon_ie1 <= data_in[3]; |
tcon_ie1 <= #1 data_in[3]; |
end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin |
tcon_ie1 <= bit_in; |
tcon_ie1 <= #1 bit_in; |
end else if (((tcon_s[1]) & (ie1_buff) & !(ie1)) | (!(tcon_s[1]) & !(ie1))) begin |
tcon_ie1 <= 1'b1; |
tcon_ie1 <= #1 1'b1; |
end else if (ack & (isrc_cur==`OC8051_ISRC_IE1) & (tcon_s[1])) begin |
tcon_ie1 <= 1'b0; |
tcon_ie1 <= #1 1'b0; |
end else if (!(tcon_s[1]) & (ie1)) begin |
tcon_ie1 <= 1'b0; |
tcon_ie1 <= #1 1'b0; |
end |
end |
|
281,66 → 281,66
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
int_vec <= 8'h00; |
int_dept <= 2'b0; |
isrc[0] <= 3'h0; |
isrc[1] <= 3'h0; |
int_proc <= 1'b0; |
int_lev[0] <= 1'b0; |
int_lev[1] <= 1'b0; |
int_vec <= #1 8'h00; |
int_dept <= #1 2'b0; |
isrc[0] <= #1 3'h0; |
isrc[1] <= #1 3'h0; |
int_proc <= #1 1'b0; |
int_lev[0] <= #1 1'b0; |
int_lev[1] <= #1 1'b0; |
end else if (reti & int_proc) begin // return from interrupt |
if (int_dept==2'b01) |
int_proc <= 1'b0; |
int_dept <= int_dept - 2'b01; |
int_proc <= #1 1'b0; |
int_dept <= #1 int_dept - 2'b01; |
end else if (((ie[7]) & (!cur_lev) || !int_proc) & il1) begin // interrupt on level 1 |
int_proc <= 1'b1; |
int_lev[int_dept] <= `OC8051_ILEV_L1; |
int_dept <= int_dept + 2'b01; |
int_proc <= #1 1'b1; |
int_lev[int_dept] <= #1 `OC8051_ILEV_L1; |
int_dept <= #1 int_dept + 2'b01; |
if (int_l1[0]) begin |
int_vec <= `OC8051_INT_X0; |
isrc[int_dept] <= `OC8051_ISRC_IE0; |
int_vec <= #1 `OC8051_INT_X0; |
isrc[int_dept] <= #1 `OC8051_ISRC_IE0; |
end else if (int_l1[1]) begin |
int_vec <= `OC8051_INT_T0; |
isrc[int_dept] <= `OC8051_ISRC_TF0; |
int_vec <= #1 `OC8051_INT_T0; |
isrc[int_dept] <= #1 `OC8051_ISRC_TF0; |
end else if (int_l1[2]) begin |
int_vec <= `OC8051_INT_X1; |
isrc[int_dept] <= `OC8051_ISRC_IE1; |
int_vec <= #1 `OC8051_INT_X1; |
isrc[int_dept] <= #1 `OC8051_ISRC_IE1; |
end else if (int_l1[3]) begin |
int_vec <= `OC8051_INT_T1; |
isrc[int_dept] <= `OC8051_ISRC_TF1; |
int_vec <= #1 `OC8051_INT_T1; |
isrc[int_dept] <= #1 `OC8051_ISRC_TF1; |
end else if (int_l1[4]) begin |
int_vec <= `OC8051_INT_UART; |
isrc[int_dept] <= `OC8051_ISRC_UART; |
int_vec <= #1 `OC8051_INT_UART; |
isrc[int_dept] <= #1 `OC8051_ISRC_UART; |
end else if (int_l1[5]) begin |
int_vec <= `OC8051_INT_T2; |
isrc[int_dept] <= `OC8051_ISRC_T2; |
int_vec <= #1 `OC8051_INT_T2; |
isrc[int_dept] <= #1 `OC8051_ISRC_T2; |
end |
|
end else if ((ie[7]) & !int_proc & il0) begin // interrupt on level 0 |
int_proc <= 1'b1; |
int_lev[int_dept] <= `OC8051_ILEV_L0; |
int_dept <= 2'b01; |
int_proc <= #1 1'b1; |
int_lev[int_dept] <= #1 `OC8051_ILEV_L0; |
int_dept <= #1 2'b01; |
if (int_l0[0]) begin |
int_vec <= `OC8051_INT_X0; |
isrc[int_dept] <= `OC8051_ISRC_IE0; |
int_vec <= #1 `OC8051_INT_X0; |
isrc[int_dept] <= #1 `OC8051_ISRC_IE0; |
end else if (int_l0[1]) begin |
int_vec <= `OC8051_INT_T0; |
isrc[int_dept] <= `OC8051_ISRC_TF0; |
int_vec <= #1 `OC8051_INT_T0; |
isrc[int_dept] <= #1 `OC8051_ISRC_TF0; |
end else if (int_l0[2]) begin |
int_vec <= `OC8051_INT_X1; |
isrc[int_dept] <= `OC8051_ISRC_IE1; |
int_vec <= #1 `OC8051_INT_X1; |
isrc[int_dept] <= #1 `OC8051_ISRC_IE1; |
end else if (int_l0[3]) begin |
int_vec <= `OC8051_INT_T1; |
isrc[int_dept] <= `OC8051_ISRC_TF1; |
int_vec <= #1 `OC8051_INT_T1; |
isrc[int_dept] <= #1 `OC8051_ISRC_TF1; |
end else if (int_l0[4]) begin |
int_vec <= `OC8051_INT_UART; |
isrc[int_dept] <= `OC8051_ISRC_UART; |
int_vec <= #1 `OC8051_INT_UART; |
isrc[int_dept] <= #1 `OC8051_ISRC_UART; |
end else if (int_l0[5]) begin |
int_vec <= `OC8051_INT_T2; |
isrc[int_dept] <= `OC8051_ISRC_T2; |
int_vec <= #1 `OC8051_INT_T2; |
isrc[int_dept] <= #1 `OC8051_ISRC_T2; |
end |
end else begin |
int_vec <= 8'h00; |
int_vec <= #1 8'h00; |
end |
end |
|
347,15 → 347,15
|
always @(posedge clk or negedge resetn) |
if (resetn == 1'b0) begin |
tf0_buff <= 1'b0; |
tf1_buff <= 1'b0; |
ie0_buff <= 1'b0; |
ie1_buff <= 1'b0; |
tf0_buff <= #1 1'b0; |
tf1_buff <= #1 1'b0; |
ie0_buff <= #1 1'b0; |
ie1_buff <= #1 1'b0; |
end else begin |
tf0_buff <= tf0; |
tf1_buff <= tf1; |
ie0_buff <= ie0; |
ie1_buff <= ie1; |
tf0_buff <= #1 tf0; |
tf1_buff <= #1 tf1; |
ie0_buff <= #1 ie0; |
ie1_buff <= #1 ie1; |
end |
|
endmodule |
/rtl/8051/oc8051_memory_interface.v
435,17 → 435,17
`OC8051_RWS_SP : wr_addr = sp_w; |
`OC8051_RWS_D3 : wr_addr = imm2_r; |
`OC8051_RWS_B : wr_addr = `OC8051_SFR_B; |
default : wr_addr = 2'b00; |
// default : wr_addr = 2'bxx; |
endcase |
end |
|
always @(posedge clk or negedge resetn) |
if (resetn == 1'b0) |
rd_ind <= 1'b0; |
rd_ind <= #1 1'b0; |
else if ((rd_sel==`OC8051_RRS_I) || (rd_sel==`OC8051_RRS_SP)) |
rd_ind <= 1'b1; |
rd_ind <= #1 1'b1; |
else |
rd_ind <= 1'b0; |
rd_ind <= #1 1'b0; |
|
always @(wr_sel) |
if ((wr_sel==`OC8051_RWS_I) || (wr_sel==`OC8051_RWS_SP)) |
470,21 → 470,21
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
iadr_t <= 23'h0; |
istb_t <= 1'b0; |
imem_wait <= 1'b0; |
idat_ir <= 24'h0; |
iadr_t <= #1 23'h0; |
istb_t <= #1 1'b0; |
imem_wait <= #1 1'b0; |
idat_ir <= #1 24'h0; |
end else if (mem_act==`OC8051_MAS_CODE) begin |
iadr_t <= alu; |
istb_t <= 1'b1; |
imem_wait <= 1'b1; |
iadr_t <= #1 alu; |
istb_t <= #1 1'b1; |
imem_wait <= #1 1'b1; |
end else if (ea_rom_sel && imem_wait) begin |
imem_wait <= 1'b0; |
imem_wait <= #1 1'b0; |
end else if (!imem_wait && istb_t) begin |
istb_t <= 1'b0; |
istb_t <= #1 1'b0; |
end else if (iack_i) begin |
imem_wait <= 1'b0; |
idat_ir <= idat_i [23:0]; |
imem_wait <= #1 1'b0; |
idat_ir <= #1 idat_i [23:0]; |
end |
end |
|
499,52 → 499,45
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
dwe_o <= 1'b0; |
dmem_wait <= 1'b0; |
dstb_o <= 1'b0; |
ddat_o <= 8'h00; |
dadr_ot <= 23'h0; |
dwe_o <= #1 1'b0; |
dmem_wait <= #1 1'b0; |
dstb_o <= #1 1'b0; |
ddat_o <= #1 8'h00; |
dadr_ot <= #1 23'h0; |
end else if (dack_i) begin |
dwe_o <= 1'b0; |
dstb_o <= 1'b0; |
dmem_wait <= 1'b0; |
dwe_o <= #1 1'b0; |
dstb_o <= #1 1'b0; |
dmem_wait <= #1 1'b0; |
end else begin |
case (mem_act) /* synopsys full_case parallel_case */ |
`OC8051_MAS_DPTR_R: begin // read from external rom: acc=(dptr) |
dwe_o <= 1'b0; |
dstb_o <= 1'b1; |
ddat_o <= 8'h00; |
dadr_ot <= {7'h0, dptr}; |
dmem_wait <= 1'b1; |
dwe_o <= #1 1'b0; |
dstb_o <= #1 1'b1; |
ddat_o <= #1 8'h00; |
dadr_ot <= #1 {7'h0, dptr}; |
dmem_wait <= #1 1'b1; |
end |
`OC8051_MAS_DPTR_W: begin // write to external rom: (dptr)=acc |
dwe_o <= 1'b1; |
dstb_o <= 1'b1; |
ddat_o <= acc; |
dadr_ot <= {7'h0, dptr}; |
dmem_wait <= 1'b1; |
dwe_o <= #1 1'b1; |
dstb_o <= #1 1'b1; |
ddat_o <= #1 acc; |
dadr_ot <= #1 {7'h0, dptr}; |
dmem_wait <= #1 1'b1; |
end |
`OC8051_MAS_RI_R: begin // read from external rom: acc=(Ri) |
dwe_o <= 1'b0; |
dstb_o <= 1'b1; |
ddat_o <= 8'h00; |
dadr_ot <= {15'h0, ri}; |
dmem_wait <= 1'b1; |
dwe_o <= #1 1'b0; |
dstb_o <= #1 1'b1; |
ddat_o <= #1 8'h00; |
dadr_ot <= #1 {15'h0, ri}; |
dmem_wait <= #1 1'b1; |
end |
`OC8051_MAS_RI_W: begin // write to external rom: (Ri)=acc |
dwe_o <= 1'b1; |
dstb_o <= 1'b1; |
ddat_o <= acc; |
dadr_ot <= {15'h0, ri}; |
dmem_wait <= 1'b1; |
dwe_o <= #1 1'b1; |
dstb_o <= #1 1'b1; |
ddat_o <= #1 acc; |
dadr_ot <= #1 {15'h0, ri}; |
dmem_wait <= #1 1'b1; |
end |
default: begin |
dwe_o <= dwe_o; |
dmem_wait <= dmem_wait; |
dstb_o <= dstb_o; |
ddat_o <= ddat_o; |
dadr_ot <= dadr_ot; |
end |
endcase |
end |
end |
560,11 → 553,11
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
idat_cur <= 32'h0; |
idat_old <= 32'h0; |
idat_cur <= #1 32'h0; |
idat_old <= #1 32'h0; |
end else if ((iack_i | ea_rom_sel) & (inc_pc | pc_wr_r2)) begin |
idat_cur <= ea_rom_sel ? idat_onchip : idat_i; |
idat_old <= idat_cur; |
idat_cur <= #1 ea_rom_sel ? idat_onchip : idat_i; |
idat_old <= #1 idat_cur; |
end |
|
end |
572,13 → 565,13
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
cdata <= 8'h00; |
cdone <= 1'b0; |
cdata <= #1 8'h00; |
cdone <= #1 1'b0; |
end else if (istb_t) begin |
cdata <= ea_rom_sel ? idat_onchip[7:0] : idat_i[7:0]; |
cdone <= 1'b1; |
cdata <= #1 ea_rom_sel ? idat_onchip[7:0] : idat_i[7:0]; |
cdone <= #1 1'b1; |
end else begin |
cdone <= 1'b0; |
cdone <= #1 1'b0; |
end |
end |
|
666,9 → 659,9
// |
//in case of reti |
always @(posedge clk or negedge resetn) |
if (resetn == 1'b0) reti <= 1'b0; |
else if ((op1_o==`OC8051_RETI) & rd & !mem_wait) reti <= 1'b1; |
else reti <= 1'b0; |
if (resetn == 1'b0) reti <= #1 1'b0; |
else if ((op1_o==`OC8051_RETI) & rd & !mem_wait) reti <= #1 1'b1; |
else reti <= #1 1'b0; |
|
// |
// remember inputs |
675,11 → 668,11
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
op2_buff <= 8'h0; |
op3_buff <= 8'h0; |
op2_buff <= #1 8'h0; |
op3_buff <= #1 8'h0; |
end else if (rd) begin |
op2_buff <= op2_o; |
op3_buff <= op3_o; |
op2_buff <= #1 op2_o; |
op3_buff <= #1 op3_o; |
end |
end |
|
770,14 → 763,14
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
op_pos <= 3'h0; |
op_pos <= #1 3'h0; |
end else if (pc_wr_r2) begin |
op_pos <= 3'h4;// - op_length;////****?????????? |
op_pos <= #1 3'h4;// - op_length;////****?????????? |
end else if (inc_pc & rd) begin |
op_pos[2] <= op_pos[2] & !op_pos[1] & op_pos[0] & (&op_length); |
op_pos[1:0] <= op_pos[1:0] + op_length; |
op_pos[2] <= #1 op_pos[2] & !op_pos[1] & op_pos[0] & (&op_length); |
op_pos[1:0] <= #1 op_pos[1:0] + op_length; |
end else if (rd) begin |
op_pos <= op_pos + {1'b0, op_length}; |
op_pos <= #1 op_pos + {1'b0, op_length}; |
end |
end |
|
786,23 → 779,23
// we don't want to interrupt instruction in the middle of execution |
always @(posedge clk or negedge resetn) |
if (resetn == 1'b0) begin |
int_ack_t <= 1'b0; |
int_vec_buff <= 8'h00; |
int_ack_t <= #1 1'b0; |
int_vec_buff <= #1 8'h00; |
end else if (intr) begin |
int_ack_t <= 1'b1; |
int_vec_buff <= int_v; |
end else if (rd && (ea_rom_sel || iack_i) && !pc_wr_r2) int_ack_t <= 1'b0; |
int_ack_t <= #1 1'b1; |
int_vec_buff <= #1 int_v; |
end else if (rd && (ea_rom_sel || iack_i) && !pc_wr_r2) int_ack_t <= #1 1'b0; |
|
always @(posedge clk or negedge resetn) |
if (resetn == 1'b0) int_ack_buff <= 1'b0; |
else int_ack_buff <= int_ack_t; |
if (resetn == 1'b0) int_ack_buff <= #1 1'b0; |
else int_ack_buff <= #1 int_ack_t; |
|
always @(posedge clk or negedge resetn) |
if (resetn == 1'b0) int_ack <= 1'b0; |
if (resetn == 1'b0) int_ack <= #1 1'b0; |
else begin |
if ((int_ack_buff) & !(int_ack_t)) |
int_ack <= 1'b1; |
else int_ack <= 1'b0; |
int_ack <= #1 1'b1; |
else int_ack <= #1 1'b0; |
end |
|
|
810,18 → 803,18
//interrupt buffer |
always @(posedge clk or negedge resetn) |
if (resetn == 1'b0) begin |
int_buff1 <= 1'b0; |
int_buff1 <= #1 1'b0; |
end else begin |
int_buff1 <= int_buff; |
int_buff1 <= #1 int_buff; |
end |
|
always @(posedge clk or negedge resetn) |
if (resetn == 1'b0) begin |
int_buff <= 1'b0; |
int_buff <= #1 1'b0; |
end else if (intr) begin |
int_buff <= 1'b1; |
int_buff <= #1 1'b1; |
end else if (pc_wait) |
int_buff <= 1'b0; |
int_buff <= #1 1'b0; |
|
wire [7:0] pcs_source; |
reg [15:0] pcs_result; |
841,45 → 834,44
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) |
pc <= 16'h0; |
pc <= #1 16'h0; |
else if (pc_wr_r2) |
pc <= pc_buf; |
pc <= #1 pc_buf; |
else if (rd && !int_ack_t && !(pc_wr && (pc_wr_sel != `OC8051_PIS_AH)) && !pc_wr_r) |
pc <= pc_buf - 16'h8 + {13'h0, op_pos} + {14'h0, op_length}; |
pc <= #1 pc_buf - 16'h8 + {13'h0, op_pos} + {14'h0, op_length}; |
end |
|
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) |
pc_next <= 16'h0; |
pc_next <= #1 16'h0; |
else if (pc_wr_r2) |
pc_next <= pc_buf; |
pc_next <= #1 pc_buf; |
else if (rd && !int_ack_t) |
pc_next <= pc_buf - 16'h8 + {13'h0, op_pos} + {14'h0, op_length}; |
pc_next <= #1 pc_buf - 16'h8 + {13'h0, op_pos} + {14'h0, op_length}; |
end |
|
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
pc_buf <= `OC8051_RST_PC; |
pc_buf <= #1 `OC8051_RST_PC; |
end else if (pc_wr) begin |
// |
//case of writing new value to pc (jupms) |
case (pc_wr_sel) /* synopsys full_case parallel_case */ |
`OC8051_PIS_ALU: pc_buf <= alu; |
`OC8051_PIS_AL: pc_buf[7:0] <= alu[7:0]; |
`OC8051_PIS_AH: pc_buf[15:8] <= alu[7:0]; |
`OC8051_PIS_I11: pc_buf[10:0] <= {op1_out[7:5], op2_out}; |
`OC8051_PIS_I16: pc_buf <= {op2_out, op3_out}; |
`OC8051_PIS_SO1: pc_buf <= pcs_result; |
`OC8051_PIS_SO2: pc_buf <= pcs_result; |
default: pc_buf <= `OC8051_RST_PC; |
`OC8051_PIS_ALU: pc_buf <= #1 alu; |
`OC8051_PIS_AL: pc_buf[7:0] <= #1 alu[7:0]; |
`OC8051_PIS_AH: pc_buf[15:8] <= #1 alu[7:0]; |
`OC8051_PIS_I11: pc_buf[10:0] <= #1 {op1_out[7:5], op2_out}; |
`OC8051_PIS_I16: pc_buf <= #1 {op2_out, op3_out}; |
`OC8051_PIS_SO1: pc_buf <= #1 pcs_result; |
`OC8051_PIS_SO2: pc_buf <= #1 pcs_result; |
endcase |
// end else if (inc_pc) begin |
end else begin |
// |
//or just remember current |
pc_buf <= pc_out; |
pc_buf <= #1 pc_out; |
end |
end |
|
893,42 → 885,42
|
always @(posedge clk or negedge resetn) |
if (resetn == 1'b0) |
ddat_ir <= 8'h00; |
ddat_ir <= #1 8'h00; |
else if (dack_i) |
ddat_ir <= ddat_i; |
ddat_ir <= #1 ddat_i; |
|
|
//////////////////////// |
always @(posedge clk or negedge resetn) |
if (resetn == 1'b0) begin |
rn_r <= 5'd0; |
ri_r <= 8'h00; |
imm_r <= 8'h00; |
imm2_r <= 8'h00; |
rd_addr_r <= 1'b0; |
op1_r <= 8'h0; |
dack_ir <= 1'b0; |
sp_r <= 1'b0; |
pc_wr_r <= 1'b0; |
pc_wr_r2 <= 1'b0; |
rn_r <= #1 5'd0; |
ri_r <= #1 8'h00; |
imm_r <= #1 8'h00; |
imm2_r <= #1 8'h00; |
rd_addr_r <= #1 1'b0; |
op1_r <= #1 8'h0; |
dack_ir <= #1 1'b0; |
sp_r <= #1 1'b0; |
pc_wr_r <= #1 1'b0; |
pc_wr_r2 <= #1 1'b0; |
end else begin |
rn_r <= rn; |
ri_r <= ri; |
imm_r <= imm; |
imm2_r <= imm2; |
rd_addr_r <= rd_addr[7]; |
op1_r <= op1_out; |
dack_ir <= dack_i; |
sp_r <= sp; |
pc_wr_r <= pc_wr && (pc_wr_sel != `OC8051_PIS_AH); |
pc_wr_r2 <= pc_wr_r; |
rn_r <= #1 rn; |
ri_r <= #1 ri; |
imm_r <= #1 imm; |
imm2_r <= #1 imm2; |
rd_addr_r <= #1 rd_addr[7]; |
op1_r <= #1 op1_out; |
dack_ir <= #1 dack_i; |
sp_r <= #1 sp; |
pc_wr_r <= #1 pc_wr && (pc_wr_sel != `OC8051_PIS_AH); |
pc_wr_r2 <= #1 pc_wr_r; |
end |
|
always @(posedge clk or negedge resetn) |
if (resetn == 1'b0) begin |
inc_pc_r <= 1'b1; |
inc_pc_r <= #1 1'b1; |
end else if (istb) begin |
inc_pc_r <= inc_pc; |
inc_pc_r <= #1 inc_pc; |
end |
|
`ifdef OC8051_SIMULATION |
/rtl/8051/oc8051_multiply.v
102,11 → 102,11
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
cycle <= 2'b0; |
tmp_mul <= 16'b0; |
cycle <= #1 2'b0; |
tmp_mul <= #1 16'b0; |
end else begin |
if (enable) cycle <= cycle + 2'b1; |
tmp_mul <= mul_result; |
if (enable) cycle <= #1 cycle + 2'b1; |
tmp_mul <= #1 mul_result; |
end |
end |
|
/rtl/8051/oc8051_ports.v
18,8 → 18,6
////////////////////////////////////////////////////////////////////// |
//// v0.0 - Dinesh A, 5th Jan 2017 |
//// 1. Active edge of reset changed from High to Low |
//// v0.1 - Dinesh A, 19th Jan 2017 |
//// 1. Lint Warning fixes |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
157,19 → 155,19
begin |
if (resetn == 1'b0) begin |
`ifdef OC8051_PORT0 |
p0_out <= `OC8051_RST_P0; |
p0_out <= #1 `OC8051_RST_P0; |
`endif |
|
`ifdef OC8051_PORT1 |
p1_out <= `OC8051_RST_P1; |
p1_out <= #1 `OC8051_RST_P1; |
`endif |
|
`ifdef OC8051_PORT2 |
p2_out <= `OC8051_RST_P2; |
p2_out <= #1 `OC8051_RST_P2; |
`endif |
|
`ifdef OC8051_PORT3 |
p3_out <= `OC8051_RST_P3; |
p3_out <= #1 `OC8051_RST_P3; |
`endif |
end else if (wr) begin |
if (!wr_bit) begin |
177,20 → 175,20
// |
// bytaddresable |
`ifdef OC8051_PORT0 |
`OC8051_SFR_P0: begin p0_out <= data_in; |
`OC8051_SFR_P0: begin p0_out <= #1 data_in; |
end |
`endif |
|
`ifdef OC8051_PORT1 |
`OC8051_SFR_P1: p1_out <= data_in; |
`OC8051_SFR_P1: p1_out <= #1 data_in; |
`endif |
|
`ifdef OC8051_PORT2 |
`OC8051_SFR_P2: p2_out <= data_in; |
`OC8051_SFR_P2: p2_out <= #1 data_in; |
`endif |
|
`ifdef OC8051_PORT3 |
`OC8051_SFR_P3: p3_out <= data_in; |
`OC8051_SFR_P3: p3_out <= #1 data_in; |
`endif |
endcase |
end else begin |
199,37 → 197,20
// |
// bit addressable |
`ifdef OC8051_PORT0 |
`OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= bit_in; |
`OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= #1 bit_in; |
`endif |
|
`ifdef OC8051_PORT1 |
`OC8051_SFR_B_P1: p1_out[wr_addr[2:0]] <= bit_in; |
`OC8051_SFR_B_P1: p1_out[wr_addr[2:0]] <= #1 bit_in; |
`endif |
|
`ifdef OC8051_PORT2 |
`OC8051_SFR_B_P2: p2_out[wr_addr[2:0]] <= bit_in; |
`OC8051_SFR_B_P2: p2_out[wr_addr[2:0]] <= #1 bit_in; |
`endif |
|
`ifdef OC8051_PORT3 |
`OC8051_SFR_B_P3: p3_out[wr_addr[2:0]] <= bit_in; |
`OC8051_SFR_B_P3: p3_out[wr_addr[2:0]] <= #1 bit_in; |
`endif |
default: begin |
`ifdef OC8051_PORT0 |
p0_out <= `OC8051_RST_P0; |
`endif |
|
`ifdef OC8051_PORT1 |
p1_out <= `OC8051_RST_P1; |
`endif |
|
`ifdef OC8051_PORT2 |
p2_out <= `OC8051_RST_P2; |
`endif |
|
`ifdef OC8051_PORT3 |
p3_out <= `OC8051_RST_P3; |
`endif |
end |
endcase |
end |
end |
/rtl/8051/oc8051_psw.v
106,36 → 106,36
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) |
data <= `OC8051_RST_PSW; |
data <= #1 `OC8051_RST_PSW; |
|
// |
// write to psw (byte addressable) |
else begin |
if (wr & (wr_bit==1'b0) & (wr_addr==`OC8051_SFR_PSW)) |
data[7:1] <= data_in[7:1]; |
data[7:1] <= #1 data_in[7:1]; |
// |
// write to psw (bit addressable) |
else if (wr & wr_bit & (wr_addr[7:3]==`OC8051_SFR_B_PSW)) |
data[wr_addr[2:0]] <= cy_in; |
data[wr_addr[2:0]] <= #1 cy_in; |
else begin |
case (set) /* synopsys full_case parallel_case */ |
`OC8051_PS_CY: begin |
// |
//write carry |
data[7] <= cy_in; |
data[7] <= #1 cy_in; |
end |
`OC8051_PS_OV: begin |
// |
//write carry and overflov |
data[7] <= cy_in; |
data[2] <= ov_in; |
data[7] <= #1 cy_in; |
data[2] <= #1 ov_in; |
end |
`OC8051_PS_AC:begin |
// |
//write carry, overflov and ac |
data[7] <= cy_in; |
data[6] <= ac_in; |
data[2] <= ov_in; |
data[7] <= #1 cy_in; |
data[6] <= #1 ac_in; |
data[2] <= #1 ov_in; |
|
end |
endcase |
/rtl/8051/oc8051_ram_256x8_two_bist.v
170,7 → 170,7
always @(posedge clk) |
begin |
if (wr) |
buff[wr_addr] <= wr_data; |
buff[wr_addr] <= #1 wr_data; |
end |
|
// |
178,11 → 178,11
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) |
rd_data <= 8'h0; |
rd_data <= #1 8'h0; |
else if ((wr_addr==rd_addr) & wr & rd_en) |
rd_data <= wr_data; |
rd_data <= #1 wr_data; |
else if (rd_en) |
rd_data <= buff[rd_addr]; |
rd_data <= #1 buff[rd_addr]; |
end |
`endif //OC8051_RAM_XILINX |
|
/rtl/8051/oc8051_ram_64x32_dual_bist.v
166,22 → 166,22
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) |
dat1_o <= 32'h0; |
dat1_o <= #1 32'h0; |
else if (wr1) begin |
buff[adr1] <= dat1_i; |
dat1_o <= dat1_i; |
buff[adr1] <= #1 dat1_i; |
dat1_o <= #1 dat1_i; |
end else |
dat1_o <= buff[adr1]; |
dat1_o <= #1 buff[adr1]; |
end |
|
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) |
dat0_o <= 32'h0; |
dat0_o <= #1 32'h0; |
else if ((adr0==adr1) & wr1) |
dat0_o <= dat1_i; |
dat0_o <= #1 dat1_i; |
else |
dat0_o <= buff[adr0]; |
dat0_o <= #1 buff[adr0]; |
end |
|
`endif //OC8051_RAM_GENERIC |
/rtl/8051/oc8051_ram_top.v
167,21 → 167,21
|
always @(posedge clk or negedge resetn) |
if (resetn == 1'b0) begin |
bit_addr_r <= 1'b0; |
bit_select <= 3'b0; |
bit_addr_r <= #1 1'b0; |
bit_select <= #1 3'b0; |
end else begin |
bit_addr_r <= bit_addr; |
bit_select <= rd_addr[2:0]; |
bit_addr_r <= #1 bit_addr; |
bit_select <= #1 rd_addr[2:0]; |
end |
|
|
always @(posedge clk or negedge resetn) |
if (resetn == 1'b0) begin |
rd_en_r <= 1'b0; |
wr_data_r <= 8'h0; |
rd_en_r <= #1 1'b0; |
wr_data_r <= #1 8'h0; |
end else begin |
rd_en_r <= rd_en; |
wr_data_r <= wr_data_m; |
rd_en_r <= #1 rd_en; |
wr_data_r <= #1 wr_data_m; |
end |
|
|
/rtl/8051/oc8051_rom.v
239,649 → 239,649
begin |
case(addr[6:0]) /* synopsys parallel_case */ |
7'd0: begin |
data1 <= int_data0; |
data2 <= int_data1; |
data3 <= int_data2; |
data1 <= #1 int_data0; |
data2 <= #1 int_data1; |
data3 <= #1 int_data2; |
end |
7'd1: begin |
data1 <= int_data1; |
data2 <= int_data2; |
data3 <= int_data3; |
data1 <= #1 int_data1; |
data2 <= #1 int_data2; |
data3 <= #1 int_data3; |
end |
7'd2: begin |
data1 <= int_data2; |
data2 <= int_data3; |
data3 <= int_data4; |
data1 <= #1 int_data2; |
data2 <= #1 int_data3; |
data3 <= #1 int_data4; |
end |
7'd3: begin |
data1 <= int_data3; |
data2 <= int_data4; |
data3 <= int_data5; |
data1 <= #1 int_data3; |
data2 <= #1 int_data4; |
data3 <= #1 int_data5; |
end |
7'd4: begin |
data1 <= int_data4; |
data2 <= int_data5; |
data3 <= int_data6; |
data1 <= #1 int_data4; |
data2 <= #1 int_data5; |
data3 <= #1 int_data6; |
end |
7'd5: begin |
data1 <= int_data5; |
data2 <= int_data6; |
data3 <= int_data7; |
data1 <= #1 int_data5; |
data2 <= #1 int_data6; |
data3 <= #1 int_data7; |
end |
7'd6: begin |
data1 <= int_data6; |
data2 <= int_data7; |
data3 <= int_data8; |
data1 <= #1 int_data6; |
data2 <= #1 int_data7; |
data3 <= #1 int_data8; |
end |
7'd7: begin |
data1 <= int_data7; |
data2 <= int_data8; |
data3 <= int_data9; |
data1 <= #1 int_data7; |
data2 <= #1 int_data8; |
data3 <= #1 int_data9; |
end |
7'd8: begin |
data1 <= int_data8; |
data2 <= int_data9; |
data3 <= int_data10; |
data1 <= #1 int_data8; |
data2 <= #1 int_data9; |
data3 <= #1 int_data10; |
end |
7'd9: begin |
data1 <= int_data9; |
data2 <= int_data10; |
data3 <= int_data11; |
data1 <= #1 int_data9; |
data2 <= #1 int_data10; |
data3 <= #1 int_data11; |
end |
7'd10: begin |
data1 <= int_data10; |
data2 <= int_data11; |
data3 <= int_data12; |
data1 <= #1 int_data10; |
data2 <= #1 int_data11; |
data3 <= #1 int_data12; |
end |
7'd11: begin |
data1 <= int_data11; |
data2 <= int_data12; |
data3 <= int_data13; |
data1 <= #1 int_data11; |
data2 <= #1 int_data12; |
data3 <= #1 int_data13; |
end |
7'd12: begin |
data1 <= int_data12; |
data2 <= int_data13; |
data3 <= int_data14; |
data1 <= #1 int_data12; |
data2 <= #1 int_data13; |
data3 <= #1 int_data14; |
end |
7'd13: begin |
data1 <= int_data13; |
data2 <= int_data14; |
data3 <= int_data15; |
data1 <= #1 int_data13; |
data2 <= #1 int_data14; |
data3 <= #1 int_data15; |
end |
7'd14: begin |
data1 <= int_data14; |
data2 <= int_data15; |
data3 <= int_data16; |
data1 <= #1 int_data14; |
data2 <= #1 int_data15; |
data3 <= #1 int_data16; |
end |
7'd15: begin |
data1 <= int_data15; |
data2 <= int_data16; |
data3 <= int_data17; |
data1 <= #1 int_data15; |
data2 <= #1 int_data16; |
data3 <= #1 int_data17; |
end |
7'd16: begin |
data1 <= int_data16; |
data2 <= int_data17; |
data3 <= int_data18; |
data1 <= #1 int_data16; |
data2 <= #1 int_data17; |
data3 <= #1 int_data18; |
end |
7'd17: begin |
data1 <= int_data17; |
data2 <= int_data18; |
data3 <= int_data19; |
data1 <= #1 int_data17; |
data2 <= #1 int_data18; |
data3 <= #1 int_data19; |
end |
7'd18: begin |
data1 <= int_data18; |
data2 <= int_data19; |
data3 <= int_data20; |
data1 <= #1 int_data18; |
data2 <= #1 int_data19; |
data3 <= #1 int_data20; |
end |
7'd19: begin |
data1 <= int_data19; |
data2 <= int_data20; |
data3 <= int_data21; |
data1 <= #1 int_data19; |
data2 <= #1 int_data20; |
data3 <= #1 int_data21; |
end |
7'd20: begin |
data1 <= int_data20; |
data2 <= int_data21; |
data3 <= int_data22; |
data1 <= #1 int_data20; |
data2 <= #1 int_data21; |
data3 <= #1 int_data22; |
end |
7'd21: begin |
data1 <= int_data21; |
data2 <= int_data22; |
data3 <= int_data23; |
data1 <= #1 int_data21; |
data2 <= #1 int_data22; |
data3 <= #1 int_data23; |
end |
7'd22: begin |
data1 <= int_data22; |
data2 <= int_data23; |
data3 <= int_data24; |
data1 <= #1 int_data22; |
data2 <= #1 int_data23; |
data3 <= #1 int_data24; |
end |
7'd23: begin |
data1 <= int_data23; |
data2 <= int_data24; |
data3 <= int_data25; |
data1 <= #1 int_data23; |
data2 <= #1 int_data24; |
data3 <= #1 int_data25; |
end |
7'd24: begin |
data1 <= int_data24; |
data2 <= int_data25; |
data3 <= int_data26; |
data1 <= #1 int_data24; |
data2 <= #1 int_data25; |
data3 <= #1 int_data26; |
end |
7'd25: begin |
data1 <= int_data25; |
data2 <= int_data26; |
data3 <= int_data27; |
data1 <= #1 int_data25; |
data2 <= #1 int_data26; |
data3 <= #1 int_data27; |
end |
7'd26: begin |
data1 <= int_data26; |
data2 <= int_data27; |
data3 <= int_data28; |
data1 <= #1 int_data26; |
data2 <= #1 int_data27; |
data3 <= #1 int_data28; |
end |
7'd27: begin |
data1 <= int_data27; |
data2 <= int_data28; |
data3 <= int_data29; |
data1 <= #1 int_data27; |
data2 <= #1 int_data28; |
data3 <= #1 int_data29; |
end |
7'd28: begin |
data1 <= int_data28; |
data2 <= int_data29; |
data3 <= int_data30; |
data1 <= #1 int_data28; |
data2 <= #1 int_data29; |
data3 <= #1 int_data30; |
end |
7'd29: begin |
data1 <= int_data29; |
data2 <= int_data30; |
data3 <= int_data31; |
data1 <= #1 int_data29; |
data2 <= #1 int_data30; |
data3 <= #1 int_data31; |
end |
7'd30: begin |
data1 <= int_data30; |
data2 <= int_data31; |
data3 <= int_data32; |
data1 <= #1 int_data30; |
data2 <= #1 int_data31; |
data3 <= #1 int_data32; |
end |
7'd31: begin |
data1 <= int_data31; |
data2 <= int_data32; |
data3 <= int_data33; |
data1 <= #1 int_data31; |
data2 <= #1 int_data32; |
data3 <= #1 int_data33; |
end |
7'd32: begin |
data1 <= int_data32; |
data2 <= int_data33; |
data3 <= int_data34; |
data1 <= #1 int_data32; |
data2 <= #1 int_data33; |
data3 <= #1 int_data34; |
end |
7'd33: begin |
data1 <= int_data33; |
data2 <= int_data34; |
data3 <= int_data35; |
data1 <= #1 int_data33; |
data2 <= #1 int_data34; |
data3 <= #1 int_data35; |
end |
7'd34: begin |
data1 <= int_data34; |
data2 <= int_data35; |
data3 <= int_data36; |
data1 <= #1 int_data34; |
data2 <= #1 int_data35; |
data3 <= #1 int_data36; |
end |
7'd35: begin |
data1 <= int_data35; |
data2 <= int_data36; |
data3 <= int_data37; |
data1 <= #1 int_data35; |
data2 <= #1 int_data36; |
data3 <= #1 int_data37; |
end |
7'd36: begin |
data1 <= int_data36; |
data2 <= int_data37; |
data3 <= int_data38; |
data1 <= #1 int_data36; |
data2 <= #1 int_data37; |
data3 <= #1 int_data38; |
end |
7'd37: begin |
data1 <= int_data37; |
data2 <= int_data38; |
data3 <= int_data39; |
data1 <= #1 int_data37; |
data2 <= #1 int_data38; |
data3 <= #1 int_data39; |
end |
7'd38: begin |
data1 <= int_data38; |
data2 <= int_data39; |
data3 <= int_data40; |
data1 <= #1 int_data38; |
data2 <= #1 int_data39; |
data3 <= #1 int_data40; |
end |
7'd39: begin |
data1 <= int_data39; |
data2 <= int_data40; |
data3 <= int_data41; |
data1 <= #1 int_data39; |
data2 <= #1 int_data40; |
data3 <= #1 int_data41; |
end |
7'd40: begin |
data1 <= int_data40; |
data2 <= int_data41; |
data3 <= int_data42; |
data1 <= #1 int_data40; |
data2 <= #1 int_data41; |
data3 <= #1 int_data42; |
end |
7'd41: begin |
data1 <= int_data41; |
data2 <= int_data42; |
data3 <= int_data43; |
data1 <= #1 int_data41; |
data2 <= #1 int_data42; |
data3 <= #1 int_data43; |
end |
7'd42: begin |
data1 <= int_data42; |
data2 <= int_data43; |
data3 <= int_data44; |
data1 <= #1 int_data42; |
data2 <= #1 int_data43; |
data3 <= #1 int_data44; |
end |
7'd43: begin |
data1 <= int_data43; |
data2 <= int_data44; |
data3 <= int_data45; |
data1 <= #1 int_data43; |
data2 <= #1 int_data44; |
data3 <= #1 int_data45; |
end |
7'd44: begin |
data1 <= int_data44; |
data2 <= int_data45; |
data3 <= int_data46; |
data1 <= #1 int_data44; |
data2 <= #1 int_data45; |
data3 <= #1 int_data46; |
end |
7'd45: begin |
data1 <= int_data45; |
data2 <= int_data46; |
data3 <= int_data47; |
data1 <= #1 int_data45; |
data2 <= #1 int_data46; |
data3 <= #1 int_data47; |
end |
7'd46: begin |
data1 <= int_data46; |
data2 <= int_data47; |
data3 <= int_data48; |
data1 <= #1 int_data46; |
data2 <= #1 int_data47; |
data3 <= #1 int_data48; |
end |
7'd47: begin |
data1 <= int_data47; |
data2 <= int_data48; |
data3 <= int_data49; |
data1 <= #1 int_data47; |
data2 <= #1 int_data48; |
data3 <= #1 int_data49; |
end |
7'd48: begin |
data1 <= int_data48; |
data2 <= int_data49; |
data3 <= int_data50; |
data1 <= #1 int_data48; |
data2 <= #1 int_data49; |
data3 <= #1 int_data50; |
end |
7'd49: begin |
data1 <= int_data49; |
data2 <= int_data50; |
data3 <= int_data51; |
data1 <= #1 int_data49; |
data2 <= #1 int_data50; |
data3 <= #1 int_data51; |
end |
7'd50: begin |
data1 <= int_data50; |
data2 <= int_data51; |
data3 <= int_data52; |
data1 <= #1 int_data50; |
data2 <= #1 int_data51; |
data3 <= #1 int_data52; |
end |
7'd51: begin |
data1 <= int_data51; |
data2 <= int_data52; |
data3 <= int_data53; |
data1 <= #1 int_data51; |
data2 <= #1 int_data52; |
data3 <= #1 int_data53; |
end |
7'd52: begin |
data1 <= int_data52; |
data2 <= int_data53; |
data3 <= int_data54; |
data1 <= #1 int_data52; |
data2 <= #1 int_data53; |
data3 <= #1 int_data54; |
end |
7'd53: begin |
data1 <= int_data53; |
data2 <= int_data54; |
data3 <= int_data55; |
data1 <= #1 int_data53; |
data2 <= #1 int_data54; |
data3 <= #1 int_data55; |
end |
7'd54: begin |
data1 <= int_data54; |
data2 <= int_data55; |
data3 <= int_data56; |
data1 <= #1 int_data54; |
data2 <= #1 int_data55; |
data3 <= #1 int_data56; |
end |
7'd55: begin |
data1 <= int_data55; |
data2 <= int_data56; |
data3 <= int_data57; |
data1 <= #1 int_data55; |
data2 <= #1 int_data56; |
data3 <= #1 int_data57; |
end |
7'd56: begin |
data1 <= int_data56; |
data2 <= int_data57; |
data3 <= int_data58; |
data1 <= #1 int_data56; |
data2 <= #1 int_data57; |
data3 <= #1 int_data58; |
end |
7'd57: begin |
data1 <= int_data57; |
data2 <= int_data58; |
data3 <= int_data59; |
data1 <= #1 int_data57; |
data2 <= #1 int_data58; |
data3 <= #1 int_data59; |
end |
7'd58: begin |
data1 <= int_data58; |
data2 <= int_data59; |
data3 <= int_data60; |
data1 <= #1 int_data58; |
data2 <= #1 int_data59; |
data3 <= #1 int_data60; |
end |
7'd59: begin |
data1 <= int_data59; |
data2 <= int_data60; |
data3 <= int_data61; |
data1 <= #1 int_data59; |
data2 <= #1 int_data60; |
data3 <= #1 int_data61; |
end |
7'd60: begin |
data1 <= int_data60; |
data2 <= int_data61; |
data3 <= int_data62; |
data1 <= #1 int_data60; |
data2 <= #1 int_data61; |
data3 <= #1 int_data62; |
end |
7'd61: begin |
data1 <= int_data61; |
data2 <= int_data62; |
data3 <= int_data63; |
data1 <= #1 int_data61; |
data2 <= #1 int_data62; |
data3 <= #1 int_data63; |
end |
7'd62: begin |
data1 <= int_data62; |
data2 <= int_data63; |
data3 <= int_data64; |
data1 <= #1 int_data62; |
data2 <= #1 int_data63; |
data3 <= #1 int_data64; |
end |
7'd63: begin |
data1 <= int_data63; |
data2 <= int_data64; |
data3 <= int_data65; |
data1 <= #1 int_data63; |
data2 <= #1 int_data64; |
data3 <= #1 int_data65; |
end |
7'd64: begin |
data1 <= int_data64; |
data2 <= int_data65; |
data3 <= int_data66; |
data1 <= #1 int_data64; |
data2 <= #1 int_data65; |
data3 <= #1 int_data66; |
end |
7'd65: begin |
data1 <= int_data65; |
data2 <= int_data66; |
data3 <= int_data67; |
data1 <= #1 int_data65; |
data2 <= #1 int_data66; |
data3 <= #1 int_data67; |
end |
7'd66: begin |
data1 <= int_data66; |
data2 <= int_data67; |
data3 <= int_data68; |
data1 <= #1 int_data66; |
data2 <= #1 int_data67; |
data3 <= #1 int_data68; |
end |
7'd67: begin |
data1 <= int_data67; |
data2 <= int_data68; |
data3 <= int_data69; |
data1 <= #1 int_data67; |
data2 <= #1 int_data68; |
data3 <= #1 int_data69; |
end |
7'd68: begin |
data1 <= int_data68; |
data2 <= int_data69; |
data3 <= int_data70; |
data1 <= #1 int_data68; |
data2 <= #1 int_data69; |
data3 <= #1 int_data70; |
end |
7'd69: begin |
data1 <= int_data69; |
data2 <= int_data70; |
data3 <= int_data71; |
data1 <= #1 int_data69; |
data2 <= #1 int_data70; |
data3 <= #1 int_data71; |
end |
7'd70: begin |
data1 <= int_data70; |
data2 <= int_data71; |
data3 <= int_data72; |
data1 <= #1 int_data70; |
data2 <= #1 int_data71; |
data3 <= #1 int_data72; |
end |
7'd71: begin |
data1 <= int_data71; |
data2 <= int_data72; |
data3 <= int_data73; |
data1 <= #1 int_data71; |
data2 <= #1 int_data72; |
data3 <= #1 int_data73; |
end |
7'd72: begin |
data1 <= int_data72; |
data2 <= int_data73; |
data3 <= int_data74; |
data1 <= #1 int_data72; |
data2 <= #1 int_data73; |
data3 <= #1 int_data74; |
end |
7'd73: begin |
data1 <= int_data73; |
data2 <= int_data74; |
data3 <= int_data75; |
data1 <= #1 int_data73; |
data2 <= #1 int_data74; |
data3 <= #1 int_data75; |
end |
7'd74: begin |
data1 <= int_data74; |
data2 <= int_data75; |
data3 <= int_data76; |
data1 <= #1 int_data74; |
data2 <= #1 int_data75; |
data3 <= #1 int_data76; |
end |
7'd75: begin |
data1 <= int_data75; |
data2 <= int_data76; |
data3 <= int_data77; |
data1 <= #1 int_data75; |
data2 <= #1 int_data76; |
data3 <= #1 int_data77; |
end |
7'd76: begin |
data1 <= int_data76; |
data2 <= int_data77; |
data3 <= int_data78; |
data1 <= #1 int_data76; |
data2 <= #1 int_data77; |
data3 <= #1 int_data78; |
end |
7'd77: begin |
data1 <= int_data77; |
data2 <= int_data78; |
data3 <= int_data79; |
data1 <= #1 int_data77; |
data2 <= #1 int_data78; |
data3 <= #1 int_data79; |
end |
7'd78: begin |
data1 <= int_data78; |
data2 <= int_data79; |
data3 <= int_data80; |
data1 <= #1 int_data78; |
data2 <= #1 int_data79; |
data3 <= #1 int_data80; |
end |
7'd79: begin |
data1 <= int_data79; |
data2 <= int_data80; |
data3 <= int_data81; |
data1 <= #1 int_data79; |
data2 <= #1 int_data80; |
data3 <= #1 int_data81; |
end |
7'd80: begin |
data1 <= int_data80; |
data2 <= int_data81; |
data3 <= int_data82; |
data1 <= #1 int_data80; |
data2 <= #1 int_data81; |
data3 <= #1 int_data82; |
end |
7'd81: begin |
data1 <= int_data81; |
data2 <= int_data82; |
data3 <= int_data83; |
data1 <= #1 int_data81; |
data2 <= #1 int_data82; |
data3 <= #1 int_data83; |
end |
7'd82: begin |
data1 <= int_data82; |
data2 <= int_data83; |
data3 <= int_data84; |
data1 <= #1 int_data82; |
data2 <= #1 int_data83; |
data3 <= #1 int_data84; |
end |
7'd83: begin |
data1 <= int_data83; |
data2 <= int_data84; |
data3 <= int_data85; |
data1 <= #1 int_data83; |
data2 <= #1 int_data84; |
data3 <= #1 int_data85; |
end |
7'd84: begin |
data1 <= int_data84; |
data2 <= int_data85; |
data3 <= int_data86; |
data1 <= #1 int_data84; |
data2 <= #1 int_data85; |
data3 <= #1 int_data86; |
end |
7'd85: begin |
data1 <= int_data85; |
data2 <= int_data86; |
data3 <= int_data87; |
data1 <= #1 int_data85; |
data2 <= #1 int_data86; |
data3 <= #1 int_data87; |
end |
7'd86: begin |
data1 <= int_data86; |
data2 <= int_data87; |
data3 <= int_data88; |
data1 <= #1 int_data86; |
data2 <= #1 int_data87; |
data3 <= #1 int_data88; |
end |
7'd87: begin |
data1 <= int_data87; |
data2 <= int_data88; |
data3 <= int_data89; |
data1 <= #1 int_data87; |
data2 <= #1 int_data88; |
data3 <= #1 int_data89; |
end |
7'd88: begin |
data1 <= int_data88; |
data2 <= int_data89; |
data3 <= int_data90; |
data1 <= #1 int_data88; |
data2 <= #1 int_data89; |
data3 <= #1 int_data90; |
end |
7'd89: begin |
data1 <= int_data89; |
data2 <= int_data90; |
data3 <= int_data91; |
data1 <= #1 int_data89; |
data2 <= #1 int_data90; |
data3 <= #1 int_data91; |
end |
7'd90: begin |
data1 <= int_data90; |
data2 <= int_data91; |
data3 <= int_data92; |
data1 <= #1 int_data90; |
data2 <= #1 int_data91; |
data3 <= #1 int_data92; |
end |
7'd91: begin |
data1 <= int_data91; |
data2 <= int_data92; |
data3 <= int_data93; |
data1 <= #1 int_data91; |
data2 <= #1 int_data92; |
data3 <= #1 int_data93; |
end |
7'd92: begin |
data1 <= int_data92; |
data2 <= int_data93; |
data3 <= int_data94; |
data1 <= #1 int_data92; |
data2 <= #1 int_data93; |
data3 <= #1 int_data94; |
end |
7'd93: begin |
data1 <= int_data93; |
data2 <= int_data94; |
data3 <= int_data95; |
data1 <= #1 int_data93; |
data2 <= #1 int_data94; |
data3 <= #1 int_data95; |
end |
7'd94: begin |
data1 <= int_data94; |
data2 <= int_data95; |
data3 <= int_data96; |
data1 <= #1 int_data94; |
data2 <= #1 int_data95; |
data3 <= #1 int_data96; |
end |
7'd95: begin |
data1 <= int_data95; |
data2 <= int_data96; |
data3 <= int_data97; |
data1 <= #1 int_data95; |
data2 <= #1 int_data96; |
data3 <= #1 int_data97; |
end |
7'd96: begin |
data1 <= int_data96; |
data2 <= int_data97; |
data3 <= int_data98; |
data1 <= #1 int_data96; |
data2 <= #1 int_data97; |
data3 <= #1 int_data98; |
end |
7'd97: begin |
data1 <= int_data97; |
data2 <= int_data98; |
data3 <= int_data99; |
data1 <= #1 int_data97; |
data2 <= #1 int_data98; |
data3 <= #1 int_data99; |
end |
7'd98: begin |
data1 <= int_data98; |
data2 <= int_data99; |
data3 <= int_data100; |
data1 <= #1 int_data98; |
data2 <= #1 int_data99; |
data3 <= #1 int_data100; |
end |
7'd99: begin |
data1 <= int_data99; |
data2 <= int_data100; |
data3 <= int_data101; |
data1 <= #1 int_data99; |
data2 <= #1 int_data100; |
data3 <= #1 int_data101; |
end |
7'd100: begin |
data1 <= int_data100; |
data2 <= int_data101; |
data3 <= int_data102; |
data1 <= #1 int_data100; |
data2 <= #1 int_data101; |
data3 <= #1 int_data102; |
end |
7'd101: begin |
data1 <= int_data101; |
data2 <= int_data102; |
data3 <= int_data103; |
data1 <= #1 int_data101; |
data2 <= #1 int_data102; |
data3 <= #1 int_data103; |
end |
7'd102: begin |
data1 <= int_data102; |
data2 <= int_data103; |
data3 <= int_data104; |
data1 <= #1 int_data102; |
data2 <= #1 int_data103; |
data3 <= #1 int_data104; |
end |
7'd103: begin |
data1 <= int_data103; |
data2 <= int_data104; |
data3 <= int_data105; |
data1 <= #1 int_data103; |
data2 <= #1 int_data104; |
data3 <= #1 int_data105; |
end |
7'd104: begin |
data1 <= int_data104; |
data2 <= int_data105; |
data3 <= int_data106; |
data1 <= #1 int_data104; |
data2 <= #1 int_data105; |
data3 <= #1 int_data106; |
end |
7'd105: begin |
data1 <= int_data105; |
data2 <= int_data106; |
data3 <= int_data107; |
data1 <= #1 int_data105; |
data2 <= #1 int_data106; |
data3 <= #1 int_data107; |
end |
7'd106: begin |
data1 <= int_data106; |
data2 <= int_data107; |
data3 <= int_data108; |
data1 <= #1 int_data106; |
data2 <= #1 int_data107; |
data3 <= #1 int_data108; |
end |
7'd107: begin |
data1 <= int_data107; |
data2 <= int_data108; |
data3 <= int_data109; |
data1 <= #1 int_data107; |
data2 <= #1 int_data108; |
data3 <= #1 int_data109; |
end |
7'd108: begin |
data1 <= int_data108; |
data2 <= int_data109; |
data3 <= int_data110; |
data1 <= #1 int_data108; |
data2 <= #1 int_data109; |
data3 <= #1 int_data110; |
end |
7'd109: begin |
data1 <= int_data109; |
data2 <= int_data110; |
data3 <= int_data111; |
data1 <= #1 int_data109; |
data2 <= #1 int_data110; |
data3 <= #1 int_data111; |
end |
7'd110: begin |
data1 <= int_data110; |
data2 <= int_data111; |
data3 <= int_data112; |
data1 <= #1 int_data110; |
data2 <= #1 int_data111; |
data3 <= #1 int_data112; |
end |
7'd111: begin |
data1 <= int_data111; |
data2 <= int_data112; |
data3 <= int_data113; |
data1 <= #1 int_data111; |
data2 <= #1 int_data112; |
data3 <= #1 int_data113; |
end |
7'd112: begin |
data1 <= int_data112; |
data2 <= int_data113; |
data3 <= int_data114; |
data1 <= #1 int_data112; |
data2 <= #1 int_data113; |
data3 <= #1 int_data114; |
end |
7'd113: begin |
data1 <= int_data113; |
data2 <= int_data114; |
data3 <= int_data115; |
data1 <= #1 int_data113; |
data2 <= #1 int_data114; |
data3 <= #1 int_data115; |
end |
7'd114: begin |
data1 <= int_data114; |
data2 <= int_data115; |
data3 <= int_data116; |
data1 <= #1 int_data114; |
data2 <= #1 int_data115; |
data3 <= #1 int_data116; |
end |
7'd115: begin |
data1 <= int_data115; |
data2 <= int_data116; |
data3 <= int_data117; |
data1 <= #1 int_data115; |
data2 <= #1 int_data116; |
data3 <= #1 int_data117; |
end |
7'd116: begin |
data1 <= int_data116; |
data2 <= int_data117; |
data3 <= int_data118; |
data1 <= #1 int_data116; |
data2 <= #1 int_data117; |
data3 <= #1 int_data118; |
end |
7'd117: begin |
data1 <= int_data117; |
data2 <= int_data118; |
data3 <= int_data119; |
data1 <= #1 int_data117; |
data2 <= #1 int_data118; |
data3 <= #1 int_data119; |
end |
7'd118: begin |
data1 <= int_data118; |
data2 <= int_data119; |
data3 <= int_data120; |
data1 <= #1 int_data118; |
data2 <= #1 int_data119; |
data3 <= #1 int_data120; |
end |
7'd119: begin |
data1 <= int_data119; |
data2 <= int_data120; |
data3 <= int_data121; |
data1 <= #1 int_data119; |
data2 <= #1 int_data120; |
data3 <= #1 int_data121; |
end |
7'd120: begin |
data1 <= int_data120; |
data2 <= int_data121; |
data3 <= int_data122; |
data1 <= #1 int_data120; |
data2 <= #1 int_data121; |
data3 <= #1 int_data122; |
end |
7'd121: begin |
data1 <= int_data121; |
data2 <= int_data122; |
data3 <= int_data123; |
data1 <= #1 int_data121; |
data2 <= #1 int_data122; |
data3 <= #1 int_data123; |
end |
7'd122: begin |
data1 <= int_data122; |
data2 <= int_data123; |
data3 <= int_data124; |
data1 <= #1 int_data122; |
data2 <= #1 int_data123; |
data3 <= #1 int_data124; |
end |
7'd123: begin |
data1 <= int_data123; |
data2 <= int_data124; |
data3 <= int_data125; |
data1 <= #1 int_data123; |
data2 <= #1 int_data124; |
data3 <= #1 int_data125; |
end |
7'd124: begin |
data1 <= int_data124; |
data2 <= int_data125; |
data3 <= int_data126; |
data1 <= #1 int_data124; |
data2 <= #1 int_data125; |
data3 <= #1 int_data126; |
end |
7'd125: begin |
data1 <= int_data125; |
data2 <= int_data126; |
data3 <= int_data127; |
data1 <= #1 int_data125; |
data2 <= #1 int_data126; |
data3 <= #1 int_data127; |
end |
7'd126: begin |
data1 <= int_data126; |
data2 <= int_data127; |
data3 <= int_data0; |
data1 <= #1 int_data126; |
data2 <= #1 int_data127; |
data3 <= #1 int_data0; |
end |
7'd127: begin |
data1 <= int_data127; |
data2 <= int_data0; |
data3 <= int_data1; |
data1 <= #1 int_data127; |
data2 <= #1 int_data0; |
data3 <= #1 int_data1; |
end |
default: begin |
data1 <= 8'h00; |
data2 <= 8'h00; |
data3 <= 8'h00; |
data1 <= #1 8'h00; |
data2 <= #1 8'h00; |
data3 <= #1 8'h00; |
end |
endcase |
end |
888,8 → 888,8
|
always @(posedge clk or negedge resetn) |
if (resetn == 1'b0) |
ea_int <= 1'b1; |
else ea_int <= !ea; |
ea_int <= #1 1'b1; |
else ea_int <= #1 !ea; |
|
`elsif OC8051_ACTEL_ROM |
|
908,12 → 908,12
|
always @(posedge clk or negedge resetn) |
if (resetn == 1'b0) |
ea_int <= 1'b1; |
else ea_int <= !ea; |
ea_int <= #1 1'b1; |
else ea_int <= #1 !ea; |
|
always @(posedge clk) |
begin |
data_o <= {buff[addr+3], buff[addr+2], buff[addr+1], buff[addr]}; |
data_o <= #1 {buff[addr+3], buff[addr+2], buff[addr+1], buff[addr]}; |
end |
|
|
/rtl/8051/oc8051_sfr.v
18,8 → 18,6
////////////////////////////////////////////////////////////////////// |
//// v0.0 - Dinesh A, 5th Jan 2017 |
//// 1. Active edge of reset changed from High to Low |
//// v0.1 - Dinesh A, 19th Jan 2017 |
//// 1. Lint Warning fixes |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
540,14 → 538,14
|
always @(posedge clk or negedge resetn) |
if (resetn == 1'b0) begin |
adr0_r <= 8'h00; |
ram_wr_sel_r <= 3'b000; |
wr_bit_r <= 1'b0; |
// wait_data <= 1'b0; |
adr0_r <= #1 8'h00; |
ram_wr_sel_r <= #1 3'b000; |
wr_bit_r <= #1 1'b0; |
// wait_data <= #1 1'b0; |
end else begin |
adr0_r <= adr0; |
ram_wr_sel_r <= ram_wr_sel; |
wr_bit_r <= wr_bit; |
adr0_r <= #1 adr0; |
ram_wr_sel_r <= #1 ram_wr_sel; |
wr_bit_r <= #1 wr_bit; |
end |
|
assign comp_wait = !( |
571,11 → 569,11
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
dat0 <= 8'h00; |
wait_data <= 1'b0; |
dat0 <= #1 8'h00; |
wait_data <= #1 1'b0; |
end else if ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) begin //write and read same address |
dat0 <= des_acc; |
wait_data <= 1'b0; |
dat0 <= #1 des_acc; |
wait_data <= #1 1'b0; |
end else if ( |
( |
((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) | //write to acc |
583,7 → 581,7
(adr1[7] & (adr1==adr0) & we & !wr_bit_r) | //write and read same address |
(adr1[7] & (adr1[7:3]==adr0[7:3]) & (~&adr0[2:0]) & we & wr_bit_r) //write bit addressable to read address |
) & !wait_data) begin |
wait_data <= 1'b1; |
wait_data <= #1 1'b1; |
|
end else if (( |
((|psw_set) & (adr0==`OC8051_SFR_PSW)) | |
590,65 → 588,65
((wr_sfr==`OC8051_WRS_ACC2) & (adr0==`OC8051_SFR_ACC)) | //write to acc |
((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_HI)) //write to dph |
) & !wait_data) begin |
wait_data <= 1'b1; |
wait_data <= #1 1'b1; |
|
end else begin |
case (adr0) /* synopsys full_case parallel_case */ |
`OC8051_SFR_ACC: dat0 <= acc; |
`OC8051_SFR_PSW: dat0 <= psw; |
`OC8051_SFR_ACC: dat0 <= #1 acc; |
`OC8051_SFR_PSW: dat0 <= #1 psw; |
|
`ifdef OC8051_PORTS |
`ifdef OC8051_PORT0 |
`OC8051_SFR_P0: dat0 <= p0_data; |
`OC8051_SFR_P0: dat0 <= #1 p0_data; |
`endif |
|
`ifdef OC8051_PORT1 |
`OC8051_SFR_P1: dat0 <= p1_data; |
`OC8051_SFR_P1: dat0 <= #1 p1_data; |
`endif |
|
`ifdef OC8051_PORT2 |
`OC8051_SFR_P2: dat0 <= p2_data; |
`OC8051_SFR_P2: dat0 <= #1 p2_data; |
`endif |
|
`ifdef OC8051_PORT3 |
`OC8051_SFR_P3: dat0 <= p3_data; |
`OC8051_SFR_P3: dat0 <= #1 p3_data; |
`endif |
`endif |
|
`OC8051_SFR_SP: dat0 <= sp; |
`OC8051_SFR_B: dat0 <= b_reg; |
`OC8051_SFR_DPTR_HI: dat0 <= dptr_hi; |
`OC8051_SFR_DPTR_LO: dat0 <= dptr_lo; |
`OC8051_SFR_SP: dat0 <= #1 sp; |
`OC8051_SFR_B: dat0 <= #1 b_reg; |
`OC8051_SFR_DPTR_HI: dat0 <= #1 dptr_hi; |
`OC8051_SFR_DPTR_LO: dat0 <= #1 dptr_lo; |
|
`ifdef OC8051_UART |
`OC8051_SFR_SCON: dat0 <= scon; |
`OC8051_SFR_SBUF: dat0 <= sbuf; |
`OC8051_SFR_PCON: dat0 <= pcon; |
`OC8051_SFR_SCON: dat0 <= #1 scon; |
`OC8051_SFR_SBUF: dat0 <= #1 sbuf; |
`OC8051_SFR_PCON: dat0 <= #1 pcon; |
`endif |
|
`ifdef OC8051_TC01 |
`OC8051_SFR_TH0: dat0 <= th0; |
`OC8051_SFR_TH1: dat0 <= th1; |
`OC8051_SFR_TL0: dat0 <= tl0; |
`OC8051_SFR_TL1: dat0 <= tl1; |
`OC8051_SFR_TMOD: dat0 <= tmod; |
`OC8051_SFR_TH0: dat0 <= #1 th0; |
`OC8051_SFR_TH1: dat0 <= #1 th1; |
`OC8051_SFR_TL0: dat0 <= #1 tl0; |
`OC8051_SFR_TL1: dat0 <= #1 tl1; |
`OC8051_SFR_TMOD: dat0 <= #1 tmod; |
`endif |
|
`OC8051_SFR_IP: dat0 <= ip; |
`OC8051_SFR_IE: dat0 <= ie; |
`OC8051_SFR_TCON: dat0 <= tcon; |
`OC8051_SFR_IP: dat0 <= #1 ip; |
`OC8051_SFR_IE: dat0 <= #1 ie; |
`OC8051_SFR_TCON: dat0 <= #1 tcon; |
|
`ifdef OC8051_TC2 |
`OC8051_SFR_RCAP2H: dat0 <= rcap2h; |
`OC8051_SFR_RCAP2L: dat0 <= rcap2l; |
`OC8051_SFR_TH2: dat0 <= th2; |
`OC8051_SFR_TL2: dat0 <= tl2; |
`OC8051_SFR_T2CON: dat0 <= t2con; |
`OC8051_SFR_RCAP2H: dat0 <= #1 rcap2h; |
`OC8051_SFR_RCAP2L: dat0 <= #1 rcap2l; |
`OC8051_SFR_TH2: dat0 <= #1 th2; |
`OC8051_SFR_TL2: dat0 <= #1 tl2; |
`OC8051_SFR_T2CON: dat0 <= #1 t2con; |
`endif |
|
default: dat0 <= 8'h00; |
// default: dat0 <= #1 8'h00; |
endcase |
wait_data <= 1'b0; |
wait_data <= #1 1'b0; |
end |
end |
|
659,52 → 657,52
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) |
bit_out <= 1'h0; |
bit_out <= #1 1'h0; |
else if ( |
((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) & we & !wr_bit_r) | |
((wr_sfr==`OC8051_WRS_ACC1) & (adr0[7:3]==`OC8051_SFR_B_ACC)) //write to acc |
) |
|
bit_out <= dat1[adr0[2:0]]; |
bit_out <= #1 dat1[adr0[2:0]]; |
else if ((adr1==adr0) & we & wr_bit_r) |
bit_out <= bit_in; |
bit_out <= #1 bit_in; |
else |
case (adr0[7:3]) /* synopsys full_case parallel_case */ |
`OC8051_SFR_B_ACC: bit_out <= acc[adr0[2:0]]; |
`OC8051_SFR_B_PSW: bit_out <= psw[adr0[2:0]]; |
`OC8051_SFR_B_ACC: bit_out <= #1 acc[adr0[2:0]]; |
`OC8051_SFR_B_PSW: bit_out <= #1 psw[adr0[2:0]]; |
|
`ifdef OC8051_PORTS |
`ifdef OC8051_PORT0 |
`OC8051_SFR_B_P0: bit_out <= p0_data[adr0[2:0]]; |
`OC8051_SFR_B_P0: bit_out <= #1 p0_data[adr0[2:0]]; |
`endif |
|
`ifdef OC8051_PORT1 |
`OC8051_SFR_B_P1: bit_out <= p1_data[adr0[2:0]]; |
`OC8051_SFR_B_P1: bit_out <= #1 p1_data[adr0[2:0]]; |
`endif |
|
`ifdef OC8051_PORT2 |
`OC8051_SFR_B_P2: bit_out <= p2_data[adr0[2:0]]; |
`OC8051_SFR_B_P2: bit_out <= #1 p2_data[adr0[2:0]]; |
`endif |
|
`ifdef OC8051_PORT3 |
`OC8051_SFR_B_P3: bit_out <= p3_data[adr0[2:0]]; |
`OC8051_SFR_B_P3: bit_out <= #1 p3_data[adr0[2:0]]; |
`endif |
`endif |
|
`OC8051_SFR_B_B: bit_out <= b_reg[adr0[2:0]]; |
`OC8051_SFR_B_IP: bit_out <= ip[adr0[2:0]]; |
`OC8051_SFR_B_IE: bit_out <= ie[adr0[2:0]]; |
`OC8051_SFR_B_TCON: bit_out <= tcon[adr0[2:0]]; |
`OC8051_SFR_B_B: bit_out <= #1 b_reg[adr0[2:0]]; |
`OC8051_SFR_B_IP: bit_out <= #1 ip[adr0[2:0]]; |
`OC8051_SFR_B_IE: bit_out <= #1 ie[adr0[2:0]]; |
`OC8051_SFR_B_TCON: bit_out <= #1 tcon[adr0[2:0]]; |
|
`ifdef OC8051_UART |
`OC8051_SFR_B_SCON: bit_out <= scon[adr0[2:0]]; |
`OC8051_SFR_B_SCON: bit_out <= #1 scon[adr0[2:0]]; |
`endif |
|
`ifdef OC8051_TC2 |
`OC8051_SFR_B_T2CON: bit_out <= t2con[adr0[2:0]]; |
`OC8051_SFR_B_T2CON: bit_out <= #1 t2con[adr0[2:0]]; |
`endif |
|
default: bit_out <= 1'b0; |
// default: bit_out <= #1 1'b0; |
endcase |
end |
|
711,14 → 709,14
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
prescaler <= 4'h0; |
pres_ow <= 1'b0; |
prescaler <= #1 4'h0; |
pres_ow <= #1 1'b0; |
end else if (prescaler==4'b1011) begin |
prescaler <= 4'h0; |
pres_ow <= 1'b1; |
prescaler <= #1 4'h0; |
pres_ow <= #1 1'b1; |
end else begin |
prescaler <= prescaler + 4'h1; |
pres_ow <= 1'b0; |
prescaler <= #1 prescaler + 4'h1; |
pres_ow <= #1 1'b0; |
end |
end |
|
/rtl/8051/oc8051_sp.v
104,11 → 104,11
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) |
sp <= `OC8051_RST_SP; |
sp <= #1 `OC8051_RST_SP; |
else if (write) |
sp <= data_in; |
sp <= #1 data_in; |
else |
sp <= sp_out; |
sp <= #1 sp_out; |
end |
|
|
136,9 → 136,9
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) |
pop <= 1'b0; |
else if (ram_rd_sel==`OC8051_RRS_SP) pop <= 1'b1; |
else pop <= 1'b0; |
pop <= #1 1'b0; |
else if (ram_rd_sel==`OC8051_RRS_SP) pop <= #1 1'b1; |
else pop <= #1 1'b0; |
end |
|
endmodule |
/rtl/8051/oc8051_tc.v
18,8 → 18,6
////////////////////////////////////////////////////////////////////// |
//// v0.0 - Dinesh A, 5th Jan 2017 |
//// 1. Active edge of reset changed from High to Low |
//// v0.1 - Dinesh A, 19th Jan 2017 |
//// 1. Lint Warning fixes |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
120,9 → 118,9
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
tmod <=`OC8051_RST_TMOD; |
tmod <=#1 `OC8051_RST_TMOD; |
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TMOD)) |
tmod <= data_in; |
tmod <= #1 data_in; |
end |
|
// |
131,41 → 129,41
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
tl0 <=`OC8051_RST_TL0; |
th0 <=`OC8051_RST_TH0; |
tf0 <= 1'b0; |
tf1_0 <= 1'b0; |
tl0 <=#1 `OC8051_RST_TL0; |
th0 <=#1 `OC8051_RST_TH0; |
tf0 <= #1 1'b0; |
tf1_0 <= #1 1'b0; |
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL0)) begin |
tl0 <= data_in; |
tf0 <= 1'b0; |
tf1_0 <= 1'b0; |
tl0 <= #1 data_in; |
tf0 <= #1 1'b0; |
tf1_0 <= #1 1'b0; |
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH0)) begin |
th0 <= data_in; |
tf0 <= 1'b0; |
tf1_0 <= 1'b0; |
th0 <= #1 data_in; |
tf0 <= #1 1'b0; |
tf1_0 <= #1 1'b0; |
end else begin |
case (tmod[1:0]) /* synopsys full_case parallel_case */ |
`OC8051_MODE0: begin // mode 0 |
tf1_0 <= 1'b0; |
tf1_0 <= #1 1'b0; |
if (tc0_add) |
{tf0, th0,tl0[4:0]} <= {1'b0, th0, tl0[4:0]}+ 1'b1; |
{tf0, th0,tl0[4:0]} <= #1 {1'b0, th0, tl0[4:0]}+ 1'b1; |
end |
`OC8051_MODE1: begin // mode 1 |
tf1_0 <= 1'b0; |
tf1_0 <= #1 1'b0; |
if (tc0_add) |
{tf0, th0,tl0} <= {1'b0, th0, tl0}+ 1'b1; |
{tf0, th0,tl0} <= #1 {1'b0, th0, tl0}+ 1'b1; |
end |
|
`OC8051_MODE2: begin // mode 2 |
tf1_0 <= 1'b0; |
tf1_0 <= #1 1'b0; |
if (tc0_add) begin |
if (tl0 == 8'b1111_1111) begin |
tf0 <=1'b1; |
tl0 <=th0; |
tf0 <=#1 1'b1; |
tl0 <=#1 th0; |
end |
else begin |
tl0 <=tl0 + 8'h1; |
tf0 <= 1'b0; |
tl0 <=#1 tl0 + 8'h1; |
tf0 <= #1 1'b0; |
end |
end |
end |
172,15 → 170,15
`OC8051_MODE3: begin // mode 3 |
|
if (tc0_add) |
{tf0, tl0} <= {1'b0, tl0} +1'b1; |
{tf0, tl0} <= #1 {1'b0, tl0} +1'b1; |
|
if (tr1 & pres_ow) |
{tf1_0, th0} <= {1'b0, th0} +1'b1; |
{tf1_0, th0} <= #1 {1'b0, th0} +1'b1; |
|
end |
/* default:begin |
tf0 <= 1'b0; |
tf1_0 <= 1'b0; |
tf0 <= #1 1'b0; |
tf1_0 <= #1 1'b0; |
end*/ |
endcase |
end |
192,41 → 190,41
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
tl1 <=`OC8051_RST_TL1; |
th1 <=`OC8051_RST_TH1; |
tf1_1 <= 1'b0; |
tl1 <=#1 `OC8051_RST_TL1; |
th1 <=#1 `OC8051_RST_TH1; |
tf1_1 <= #1 1'b0; |
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL1)) begin |
tl1 <= data_in; |
tf1_1 <= 1'b0; |
tl1 <= #1 data_in; |
tf1_1 <= #1 1'b0; |
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH1)) begin |
th1 <= data_in; |
tf1_1 <= 1'b0; |
th1 <= #1 data_in; |
tf1_1 <= #1 1'b0; |
end else begin |
case (tmod[5:4]) /* synopsys full_case parallel_case */ |
`OC8051_MODE0: begin // mode 0 |
if (tc1_add) |
{tf1_1, th1,tl1[4:0]} <= {1'b0, th1, tl1[4:0]}+ 1'b1; |
{tf1_1, th1,tl1[4:0]} <= #1 {1'b0, th1, tl1[4:0]}+ 1'b1; |
end |
`OC8051_MODE1: begin // mode 1 |
if (tc1_add) |
{tf1_1, th1,tl1} <= {1'b0, th1, tl1}+ 1'b1; |
{tf1_1, th1,tl1} <= #1 {1'b0, th1, tl1}+ 1'b1; |
end |
|
`OC8051_MODE2: begin // mode 2 |
if (tc1_add) begin |
if (tl1 == 8'b1111_1111) begin |
tf1_1 <=1'b1; |
tl1 <=th1; |
tf1_1 <=#1 1'b1; |
tl1 <=#1 th1; |
end |
else begin |
tl1 <=tl1 + 8'h1; |
tf1_1 <= 1'b0; |
tl1 <=#1 tl1 + 8'h1; |
tf1_1 <= #1 1'b0; |
end |
end |
end |
default:begin |
tf1_1 <= 1'b0; |
end |
/* default:begin |
tf1_1 <= #1 1'b0; |
end*/ |
endcase |
end |
end |
234,10 → 232,10
|
always @(posedge clk or negedge resetn) |
if (resetn == 1'b0) begin |
t0_buff <= 1'b0; |
t1_buff <= 1'b0; |
t0_buff <= #1 1'b0; |
t1_buff <= #1 1'b0; |
end else begin |
t0_buff <= t0; |
t1_buff <= t1; |
t0_buff <= #1 t0; |
t1_buff <= #1 t1; |
end |
endmodule |
/rtl/8051/oc8051_tc2.v
117,15 → 117,15
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
t2con <= `OC8051_RST_T2CON; |
t2con <= #1 `OC8051_RST_T2CON; |
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_T2CON)) begin |
t2con <= data_in; |
t2con <= #1 data_in; |
end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_T2CON)) begin |
t2con[wr_addr[2:0]] <= bit_in; |
t2con[wr_addr[2:0]] <= #1 bit_in; |
end else if (tf2_set) begin |
t2con[7] <= 1'b1; |
t2con[7] <= #1 1'b1; |
end else if (exen2 & neg_trans) begin |
t2con[6] <= 1'b1; |
t2con[6] <= #1 1'b1; |
end |
end |
|
140,27 → 140,27
// |
// reset |
// |
tl2 <= `OC8051_RST_TL2; |
th2 <= `OC8051_RST_TH2; |
brate2 <= 1'b0; |
tf2_set <= 1'b0; |
tl2 <= #1 `OC8051_RST_TL2; |
th2 <= #1 `OC8051_RST_TH2; |
brate2 <= #1 1'b0; |
tf2_set <= #1 1'b0; |
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH2)) begin |
// |
// write to timer 2 high |
// |
th2 <= data_in; |
th2 <= #1 data_in; |
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL2)) begin |
// |
// write to timer 2 low |
// |
tl2 <= data_in; |
tl2 <= #1 data_in; |
end else if (!(rclk | tclk) & !cprl2 & exen2 & neg_trans) begin |
// |
// avto reload mode, exen2=1, 0-1 transition on t2ex pin |
// |
th2 <= rcap2h; |
tl2 <= rcap2l; |
tf2_set <= 1'b0; |
th2 <= #1 rcap2h; |
tl2 <= #1 rcap2l; |
tf2_set <= #1 1'b0; |
end else if (run) begin |
if (rclk | tclk) begin |
// |
167,31 → 167,31
// boud rate generator mode |
// |
if (&{th2, tl2}) begin |
th2 <= rcap2h; |
tl2 <= rcap2l; |
brate2 <= 1'b1; |
th2 <= #1 rcap2h; |
tl2 <= #1 rcap2l; |
brate2 <= #1 1'b1; |
end else begin |
{brate2, th2, tl2} <= {1'b0, th2, tl2} + 17'h1; |
{brate2, th2, tl2} <= #1 {1'b0, th2, tl2} + 17'h1; |
end |
tf2_set <= 1'b0; |
tf2_set <= #1 1'b0; |
end else if (cprl2) begin |
// |
// capture mode |
// |
{tf2_set, th2, tl2} <= {1'b0, th2, tl2} + 17'h1; |
{tf2_set, th2, tl2} <= #1 {1'b0, th2, tl2} + 17'h1; |
end else begin |
// |
// auto reload mode |
// |
if (&{th2, tl2}) begin |
th2 <= rcap2h; |
tl2 <= rcap2l; |
tf2_set <= 1'b1; |
th2 <= #1 rcap2h; |
tl2 <= #1 rcap2l; |
tf2_set <= #1 1'b1; |
end else begin |
{tf2_set, th2, tl2} <= {1'b0, th2, tl2} + 17'h1; |
{tf2_set, th2, tl2} <= #1 {1'b0, th2, tl2} + 17'h1; |
end |
end |
end else tf2_set <= 1'b0; |
end else tf2_set <= #1 1'b0; |
end |
|
|
200,15 → 200,15
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
rcap2l <= `OC8051_RST_RCAP2L; |
rcap2h <= `OC8051_RST_RCAP2H; |
rcap2l <= #1 `OC8051_RST_RCAP2L; |
rcap2h <= #1 `OC8051_RST_RCAP2H; |
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2H)) begin |
rcap2h <= data_in; |
rcap2h <= #1 data_in; |
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2L)) begin |
rcap2l <= data_in; |
rcap2l <= #1 data_in; |
end else if (!(rclk | tclk) & exen2 & cprl2 & neg_trans) begin |
rcap2l <= tl2; |
rcap2h <= th2; |
rcap2l <= #1 tl2; |
rcap2h <= #1 th2; |
end |
end |
|
218,17 → 218,17
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
neg_trans <= 1'b0; |
t2ex_r <= 1'b0; |
neg_trans <= #1 1'b0; |
t2ex_r <= #1 1'b0; |
end else if (t2ex) begin |
neg_trans <= 1'b0; |
t2ex_r <= 1'b1; |
neg_trans <= #1 1'b0; |
t2ex_r <= #1 1'b1; |
end else if (t2ex_r) begin |
neg_trans <= 1'b1; |
t2ex_r <= 1'b0; |
neg_trans <= #1 1'b1; |
t2ex_r <= #1 1'b0; |
end else begin |
neg_trans <= 1'b0; |
t2ex_r <= t2ex_r; |
neg_trans <= #1 1'b0; |
t2ex_r <= #1 t2ex_r; |
end |
end |
|
237,16 → 237,16
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
tc2_event <= 1'b0; |
t2_r <= 1'b0; |
tc2_event <= #1 1'b0; |
t2_r <= #1 1'b0; |
end else if (t2) begin |
tc2_event <= 1'b0; |
t2_r <= 1'b1; |
tc2_event <= #1 1'b0; |
t2_r <= #1 1'b1; |
end else if (!t2 & t2_r) begin |
tc2_event <= 1'b1; |
t2_r <= 1'b0; |
tc2_event <= #1 1'b1; |
t2_r <= #1 1'b0; |
end else begin |
tc2_event <= 1'b0; |
tc2_event <= #1 1'b0; |
end |
end |
|
/rtl/8051/oc8051_uart.v
18,8 → 18,6
////////////////////////////////////////////////////////////////////// |
//// v0.0 - Dinesh A, 5th Jan 2017 |
//// 1. Active edge of reset changed from High to Low |
//// v0.1 - Dinesh A, 19th Jan 2017 |
//// 1. Lint Warning fixes |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
139,21 → 137,21
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) |
scon <= `OC8051_RST_SCON; |
scon <= #1 `OC8051_RST_SCON; |
else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON)) |
scon <= data_in; |
scon <= #1 data_in; |
else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON)) |
scon[wr_addr[2:0]] <= bit_in; |
scon[wr_addr[2:0]] <= #1 bit_in; |
else if (tx_done) |
scon[1] <= 1'b1; |
scon[1] <= #1 1'b1; |
else if (!rx_done) begin |
if (scon[7:6]==2'b00) begin |
scon[0] <= 1'b1; |
scon[0] <= #1 1'b1; |
end else if ((sbuf_rxd_tmp[11]) | !(scon[5])) begin |
scon[0] <= 1'b1; |
scon[2] <= sbuf_rxd_tmp[11]; |
scon[0] <= #1 1'b1; |
scon[2] <= #1 sbuf_rxd_tmp[11]; |
end else |
scon[2] <= sbuf_rxd_tmp[11]; |
scon[2] <= #1 sbuf_rxd_tmp[11]; |
end |
end |
|
166,9 → 164,9
begin |
if (resetn == 1'b0) |
begin |
pcon <= `OC8051_RST_PCON; |
pcon <= #1 `OC8051_RST_PCON; |
end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit)) |
pcon <= data_in; |
pcon <= #1 data_in; |
end |
|
|
182,11 → 180,11
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
txd <= 1'b1; |
tr_count <= 4'd0; |
trans <= 1'b0; |
sbuf_txd <= 11'h00; |
tx_done <= 1'b0; |
txd <= #1 1'b1; |
tr_count <= #1 4'd0; |
trans <= #1 1'b0; |
sbuf_txd <= #1 11'h00; |
tx_done <= #1 1'b0; |
// |
// start transmiting |
// |
193,18 → 191,18
end else if (wr_sbuf) begin |
case (scon[7:6]) /* synopsys parallel_case */ |
2'b00: begin // mode 0 |
sbuf_txd <= {3'b001, data_in}; |
sbuf_txd <= #1 {3'b001, data_in}; |
end |
2'b01: begin // mode 1 |
sbuf_txd <= {2'b01, data_in, 1'b0}; |
sbuf_txd <= #1 {2'b01, data_in, 1'b0}; |
end |
default: begin // mode 2 and mode 3 |
sbuf_txd <= {1'b1, tb8, data_in, 1'b0}; |
sbuf_txd <= #1 {1'b1, tb8, data_in, 1'b0}; |
end |
endcase |
trans <= 1'b1; |
tr_count <= 4'd0; |
tx_done <= 1'b0; |
trans <= #1 1'b1; |
tr_count <= #1 4'd0; |
tx_done <= #1 1'b0; |
// |
// transmiting |
// |
211,27 → 209,27
end else if (trans & (scon[7:6] == 2'b00) & pres_ow) // mode 0 |
begin |
if (~|sbuf_txd[10:1]) begin |
trans <= 1'b0; |
tx_done <= 1'b1; |
trans <= #1 1'b0; |
tx_done <= #1 1'b1; |
end else begin |
{sbuf_txd, txd} <= {1'b0, sbuf_txd}; |
tx_done <= 1'b0; |
{sbuf_txd, txd} <= #1 {1'b0, sbuf_txd}; |
tx_done <= #1 1'b0; |
end |
end else if (trans & (scon[7:6] != 2'b00) & shift_tr) begin // mode 1, 2, 3 |
tr_count <= tr_count + 4'd1; |
tr_count <= #1 tr_count + 4'd1; |
if (~|tr_count) begin |
if (~|sbuf_txd[10:0]) begin |
trans <= 1'b0; |
tx_done <= 1'b1; |
txd <= 1'b1; |
trans <= #1 1'b0; |
tx_done <= #1 1'b1; |
txd <= #1 1'b1; |
end else begin |
{sbuf_txd, txd} <= {1'b0, sbuf_txd}; |
tx_done <= 1'b0; |
{sbuf_txd, txd} <= #1 {1'b0, sbuf_txd}; |
tx_done <= #1 1'b0; |
end |
end |
end else if (!trans) begin |
txd <= 1'b1; |
tx_done <= 1'b0; |
txd <= #1 1'b1; |
tx_done <= #1 1'b0; |
end |
end |
|
252,17 → 250,17
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
smod_clk_tr <= 1'b0; |
shift_tr <= 1'b0; |
smod_clk_tr <= #1 1'b0; |
shift_tr <= #1 1'b0; |
end else if (sc_clk_tr) begin |
if (smod) begin |
shift_tr <= 1'b1; |
shift_tr <= #1 1'b1; |
end else begin |
shift_tr <= smod_clk_tr; |
smod_clk_tr <= !smod_clk_tr; |
shift_tr <= #1 smod_clk_tr; |
smod_clk_tr <= #1 !smod_clk_tr; |
end |
end else begin |
shift_tr <= 1'b0; |
shift_tr <= #1 1'b0; |
end |
end |
|
273,48 → 271,47
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
re_count <= 4'd0; |
receive <= 1'b0; |
sbuf_rxd <= 8'h00; |
sbuf_rxd_tmp <= 12'd0; |
rx_done <= 1'b1; |
rxd_r <= 1'b1; |
rx_sam <= 2'b00; |
re_count <= #1 4'd0; |
receive <= #1 1'b0; |
sbuf_rxd <= #1 8'h00; |
sbuf_rxd_tmp <= #1 12'd0; |
rx_done <= #1 1'b1; |
rxd_r <= #1 1'b1; |
rx_sam <= #1 2'b00; |
end else if (!rx_done) begin |
receive <= 1'b0; |
rx_done <= 1'b1; |
sbuf_rxd <= sbuf_rxd_tmp[10:3]; |
receive <= #1 1'b0; |
rx_done <= #1 1'b1; |
sbuf_rxd <= #1 sbuf_rxd_tmp[10:3]; |
end else if (receive & (scon[7:6]==2'b00) & pres_ow) begin //mode 0 |
{sbuf_rxd_tmp, rx_done} <= {rxd, sbuf_rxd_tmp}; |
{sbuf_rxd_tmp, rx_done} <= #1 {rxd, sbuf_rxd_tmp}; |
end else if (receive & (scon[7:6]!=2'b00) & shift_re) begin //mode 1, 2, 3 |
re_count <= re_count + 4'd1; |
re_count <= #1 re_count + 4'd1; |
case (re_count) /* synopsys full_case parallel_case */ |
4'h7: rx_sam[0] <= rxd; |
4'h8: rx_sam[1] <= rxd; |
4'h7: rx_sam[0] <= #1 rxd; |
4'h8: rx_sam[1] <= #1 rxd; |
4'h9: begin |
{sbuf_rxd_tmp, rx_done} <= {(rxd==rx_sam[0] ? rxd : rx_sam[1]), sbuf_rxd_tmp}; |
{sbuf_rxd_tmp, rx_done} <= #1 {(rxd==rx_sam[0] ? rxd : rx_sam[1]), sbuf_rxd_tmp}; |
end |
default : rx_sam <= 2'b00; |
endcase |
// |
//start receiving |
// |
end else if (scon[7:6]==2'b00) begin //start mode 0 |
rx_done <= 1'b1; |
rx_done <= #1 1'b1; |
if (ren && !ri && !receive) begin |
receive <= 1'b1; |
sbuf_rxd_tmp <= 10'h0ff; |
receive <= #1 1'b1; |
sbuf_rxd_tmp <= #1 10'h0ff; |
end |
end else if (ren & shift_re) begin |
rxd_r <= rxd; |
rx_done <= 1'b1; |
re_count <= 4'h0; |
receive <= (rxd_r & !rxd); |
sbuf_rxd_tmp <= 10'h1ff; |
rxd_r <= #1 rxd; |
rx_done <= #1 1'b1; |
re_count <= #1 4'h0; |
receive <= #1 (rxd_r & !rxd); |
sbuf_rxd_tmp <= #1 10'h1ff; |
end else if (!ren) begin |
rxd_r <= rxd; |
rxd_r <= #1 rxd; |
end else |
rx_done <= 1'b1; |
rx_done <= #1 1'b1; |
end |
|
// |
334,17 → 331,17
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
smod_clk_re <= 1'b0; |
shift_re <= 1'b0; |
smod_clk_re <= #1 1'b0; |
shift_re <= #1 1'b0; |
end else if (sc_clk_re) begin |
if (smod) begin |
shift_re <= 1'b1; |
shift_re <= #1 1'b1; |
end else begin |
shift_re <= smod_clk_re; |
smod_clk_re <= !smod_clk_re; |
shift_re <= #1 smod_clk_re; |
smod_clk_re <= #1 !smod_clk_re; |
end |
end else begin |
shift_re <= 1'b0; |
shift_re <= #1 1'b0; |
end |
end |
|
357,9 → 354,9
always @(posedge clk or negedge resetn) |
begin |
if (resetn == 1'b0) begin |
t1_ow_buf <= 1'b0; |
t1_ow_buf <= #1 1'b0; |
end else begin |
t1_ow_buf <= t1_ow; |
t1_ow_buf <= #1 t1_ow; |
end |
end |
|
/rtl/8051/oc8051_wb_iinterface.v
118,14 → 118,14
|
always @(posedge clk or negedge resetn) |
if (resetn == 1'b0) begin |
stb_o <= 1'b0; |
adr_o <= 16'h0000; |
stb_o <= #1 1'b0; |
adr_o <= #1 16'h0000; |
end else if (ack_i) begin |
stb_o <= stb_i; |
adr_o <= adr_i; |
stb_o <= #1 stb_i; |
adr_o <= #1 adr_i; |
end else if (!stb_o & stb_i) begin |
stb_o <= 1'b1; |
adr_o <= adr_i; |
stb_o <= #1 1'b1; |
adr_o <= #1 adr_i; |
end |
|
endmodule |
/rtl/clkgen/clkgen.v
19,8 → 19,6
////////////////////////////////////////////////////////////////////// |
//// v0.0 - Dinesh A, 5th Jan 2017 |
//// 1. Active edge of reset changed from High to Low |
//// v0.1 - Dinesh A, 19th Jan 2017 |
//// 1. Lint warning clean up for case statement |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
198,8 → 196,6
else |
clkgen_ps <= `SLAVE_RUN; |
end |
`RUN: clkgen_ps <= `RUN; |
default: clkgen_ps <= `HARD_RESET; |
endcase |
end |
end |
/rtl/i2cm/i2cm_bit_ctrl.v
22,8 → 22,7
// v0.0 - Dinesh A, 6th Jan 2017 |
// 1. Initail version picked from |
// http://www.opencores.org/projects/i2c/ |
// v0.1 - Dinesh A, 19th Jan 2017 |
// 1. Lint warning clean up |
// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
142,7 → 141,7
// whenever the slave is not ready it can delay the cycle by pulling SCL low |
// delay scl_oen |
always @(posedge clk) |
dscl_oen <= scl_oen; |
dscl_oen <= #1 scl_oen; |
|
// slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low |
// slave_wait remains asserted until the slave releases SCL |
159,23 → 158,23
always @(posedge clk or negedge aresetn) |
if (~aresetn) |
begin |
cnt <= 16'h0; |
clk_en <= 1'b1; |
cnt <= #1 16'h0; |
clk_en <= #1 1'b1; |
end |
else if (!sresetn || ~|cnt || !ena || scl_sync) |
begin |
cnt <= clk_cnt; |
clk_en <= 1'b1; |
cnt <= #1 clk_cnt; |
clk_en <= #1 1'b1; |
end |
else if (slave_wait) |
begin |
cnt <= cnt; |
clk_en <= 1'b0; |
cnt <= #1 cnt; |
clk_en <= #1 1'b0; |
end |
else |
begin |
cnt <= cnt - 16'h1; |
clk_en <= 1'b0; |
cnt <= #1 cnt - 16'h1; |
clk_en <= #1 1'b0; |
end |
|
|
186,13 → 185,13
always @(posedge clk or negedge aresetn) |
if (!aresetn) |
begin |
cSCL <= 2'b00; |
cSDA <= 2'b00; |
cSCL <= #1 2'b00; |
cSDA <= #1 2'b00; |
end |
else if (!sresetn) |
begin |
cSCL <= 2'b00; |
cSDA <= 2'b00; |
cSCL <= #1 2'b00; |
cSDA <= #1 2'b00; |
end |
else |
begin |
231,27 → 230,27
always @(posedge clk or negedge aresetn) |
if (~aresetn) |
begin |
sSCL <= 1'b1; |
sSDA <= 1'b1; |
sSCL <= #1 1'b1; |
sSDA <= #1 1'b1; |
|
dSCL <= 1'b1; |
dSDA <= 1'b1; |
dSCL <= #1 1'b1; |
dSDA <= #1 1'b1; |
end |
else if (!sresetn) |
begin |
sSCL <= 1'b1; |
sSDA <= 1'b1; |
sSCL <= #1 1'b1; |
sSDA <= #1 1'b1; |
|
dSCL <= 1'b1; |
dSDA <= 1'b1; |
dSCL <= #1 1'b1; |
dSDA <= #1 1'b1; |
end |
else |
begin |
sSCL <= &fSCL[2:1] | &fSCL[1:0] | (fSCL[2] & fSCL[0]); |
sSDA <= &fSDA[2:1] | &fSDA[1:0] | (fSDA[2] & fSDA[0]); |
sSCL <= #1 &fSCL[2:1] | &fSCL[1:0] | (fSCL[2] & fSCL[0]); |
sSDA <= #1 &fSDA[2:1] | &fSDA[1:0] | (fSDA[2] & fSDA[0]); |
|
dSCL <= sSCL; |
dSDA <= sSDA; |
dSCL <= #1 sSCL; |
dSDA <= #1 sSDA; |
end |
|
// detect start condition => detect falling edge on SDA while SCL is high |
261,26 → 260,26
always @(posedge clk or negedge aresetn) |
if (~aresetn) |
begin |
sta_condition <= 1'b0; |
sto_condition <= 1'b0; |
sta_condition <= #1 1'b0; |
sto_condition <= #1 1'b0; |
end |
else if (!sresetn) |
begin |
sta_condition <= 1'b0; |
sto_condition <= 1'b0; |
sta_condition <= #1 1'b0; |
sto_condition <= #1 1'b0; |
end |
else |
begin |
sta_condition <= ~sSDA & dSDA & sSCL; |
sto_condition <= sSDA & ~dSDA & sSCL; |
sta_condition <= #1 ~sSDA & dSDA & sSCL; |
sto_condition <= #1 sSDA & ~dSDA & sSCL; |
end |
|
|
// generate i2c bus busy signal |
always @(posedge clk or negedge aresetn) |
if (!aresetn) busy <= 1'b0; |
else if (!sresetn ) busy <= 1'b0; |
else busy <= (sta_condition | busy) & ~sto_condition; |
if (!aresetn) busy <= #1 1'b0; |
else if (!sresetn ) busy <= #1 1'b0; |
else busy <= #1 (sta_condition | busy) & ~sto_condition; |
|
|
// generate arbitration lost signal |
290,24 → 289,24
reg cmd_stop; |
always @(posedge clk or negedge aresetn) |
if (~aresetn) |
cmd_stop <= 1'b0; |
cmd_stop <= #1 1'b0; |
else if (!sresetn) |
cmd_stop <= 1'b0; |
cmd_stop <= #1 1'b0; |
else if (clk_en) |
cmd_stop <= cmd == `I2C_CMD_STOP; |
cmd_stop <= #1 cmd == `I2C_CMD_STOP; |
|
always @(posedge clk or negedge aresetn) |
if (~aresetn) |
al <= 1'b0; |
al <= #1 1'b0; |
else if (!sresetn) |
al <= 1'b0; |
al <= #1 1'b0; |
else |
al <= (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop); |
al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop); |
|
|
// generate dout signal (store SDA on rising edge of SCL) |
always @(posedge clk) |
if (sSCL & ~dSCL) dout <= sSDA; |
if (sSCL & ~dSCL) dout <= #1 sSDA; |
|
|
// generate statemachine |
335,23 → 334,23
always @(posedge clk or negedge aresetn) |
if (!aresetn) |
begin |
c_state <= idle; |
cmd_ack <= 1'b0; |
scl_oen <= 1'b1; |
sda_oen <= 1'b1; |
sda_chk <= 1'b0; |
c_state <= #1 idle; |
cmd_ack <= #1 1'b0; |
scl_oen <= #1 1'b1; |
sda_oen <= #1 1'b1; |
sda_chk <= #1 1'b0; |
end |
else if (!sresetn | al) |
begin |
c_state <= idle; |
cmd_ack <= 1'b0; |
scl_oen <= 1'b1; |
sda_oen <= 1'b1; |
sda_chk <= 1'b0; |
c_state <= #1 idle; |
cmd_ack <= #1 1'b0; |
scl_oen <= #1 1'b1; |
sda_oen <= #1 1'b1; |
sda_chk <= #1 1'b0; |
end |
else |
begin |
cmd_ack <= 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle |
cmd_ack <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle |
|
if (clk_en) |
case (c_state) // synopsys full_case parallel_case |
359,161 → 358,161
idle: |
begin |
case (cmd) // synopsys full_case parallel_case |
`I2C_CMD_START: c_state <= start_a; |
`I2C_CMD_STOP: c_state <= stop_a; |
`I2C_CMD_WRITE: c_state <= wr_a; |
`I2C_CMD_READ: c_state <= rd_a; |
default: c_state <= idle; |
`I2C_CMD_START: c_state <= #1 start_a; |
`I2C_CMD_STOP: c_state <= #1 stop_a; |
`I2C_CMD_WRITE: c_state <= #1 wr_a; |
`I2C_CMD_READ: c_state <= #1 rd_a; |
default: c_state <= #1 idle; |
endcase |
|
scl_oen <= scl_oen; // keep SCL in same state |
sda_oen <= sda_oen; // keep SDA in same state |
sda_chk <= 1'b0; // don't check SDA output |
scl_oen <= #1 scl_oen; // keep SCL in same state |
sda_oen <= #1 sda_oen; // keep SDA in same state |
sda_chk <= #1 1'b0; // don't check SDA output |
end |
|
// start |
start_a: |
begin |
c_state <= start_b; |
scl_oen <= scl_oen; // keep SCL in same state |
sda_oen <= 1'b1; // set SDA high |
sda_chk <= 1'b0; // don't check SDA output |
c_state <= #1 start_b; |
scl_oen <= #1 scl_oen; // keep SCL in same state |
sda_oen <= #1 1'b1; // set SDA high |
sda_chk <= #1 1'b0; // don't check SDA output |
end |
|
start_b: |
begin |
c_state <= start_c; |
scl_oen <= 1'b1; // set SCL high |
sda_oen <= 1'b1; // keep SDA high |
sda_chk <= 1'b0; // don't check SDA output |
c_state <= #1 start_c; |
scl_oen <= #1 1'b1; // set SCL high |
sda_oen <= #1 1'b1; // keep SDA high |
sda_chk <= #1 1'b0; // don't check SDA output |
end |
|
start_c: |
begin |
c_state <= start_d; |
scl_oen <= 1'b1; // keep SCL high |
sda_oen <= 1'b0; // set SDA low |
sda_chk <= 1'b0; // don't check SDA output |
c_state <= #1 start_d; |
scl_oen <= #1 1'b1; // keep SCL high |
sda_oen <= #1 1'b0; // set SDA low |
sda_chk <= #1 1'b0; // don't check SDA output |
end |
|
start_d: |
begin |
c_state <= start_e; |
scl_oen <= 1'b1; // keep SCL high |
sda_oen <= 1'b0; // keep SDA low |
sda_chk <= 1'b0; // don't check SDA output |
c_state <= #1 start_e; |
scl_oen <= #1 1'b1; // keep SCL high |
sda_oen <= #1 1'b0; // keep SDA low |
sda_chk <= #1 1'b0; // don't check SDA output |
end |
|
start_e: |
begin |
c_state <= idle; |
cmd_ack <= 1'b1; |
scl_oen <= 1'b0; // set SCL low |
sda_oen <= 1'b0; // keep SDA low |
sda_chk <= 1'b0; // don't check SDA output |
c_state <= #1 idle; |
cmd_ack <= #1 1'b1; |
scl_oen <= #1 1'b0; // set SCL low |
sda_oen <= #1 1'b0; // keep SDA low |
sda_chk <= #1 1'b0; // don't check SDA output |
end |
|
// stop |
stop_a: |
begin |
c_state <= stop_b; |
scl_oen <= 1'b0; // keep SCL low |
sda_oen <= 1'b0; // set SDA low |
sda_chk <= 1'b0; // don't check SDA output |
c_state <= #1 stop_b; |
scl_oen <= #1 1'b0; // keep SCL low |
sda_oen <= #1 1'b0; // set SDA low |
sda_chk <= #1 1'b0; // don't check SDA output |
end |
|
stop_b: |
begin |
c_state <= stop_c; |
scl_oen <= 1'b1; // set SCL high |
sda_oen <= 1'b0; // keep SDA low |
sda_chk <= 1'b0; // don't check SDA output |
c_state <= #1 stop_c; |
scl_oen <= #1 1'b1; // set SCL high |
sda_oen <= #1 1'b0; // keep SDA low |
sda_chk <= #1 1'b0; // don't check SDA output |
end |
|
stop_c: |
begin |
c_state <= stop_d; |
scl_oen <= 1'b1; // keep SCL high |
sda_oen <= 1'b0; // keep SDA low |
sda_chk <= 1'b0; // don't check SDA output |
c_state <= #1 stop_d; |
scl_oen <= #1 1'b1; // keep SCL high |
sda_oen <= #1 1'b0; // keep SDA low |
sda_chk <= #1 1'b0; // don't check SDA output |
end |
|
stop_d: |
begin |
c_state <= idle; |
cmd_ack <= 1'b1; |
scl_oen <= 1'b1; // keep SCL high |
sda_oen <= 1'b1; // set SDA high |
sda_chk <= 1'b0; // don't check SDA output |
c_state <= #1 idle; |
cmd_ack <= #1 1'b1; |
scl_oen <= #1 1'b1; // keep SCL high |
sda_oen <= #1 1'b1; // set SDA high |
sda_chk <= #1 1'b0; // don't check SDA output |
end |
|
// read |
rd_a: |
begin |
c_state <= rd_b; |
scl_oen <= 1'b0; // keep SCL low |
sda_oen <= 1'b1; // tri-state SDA |
sda_chk <= 1'b0; // don't check SDA output |
c_state <= #1 rd_b; |
scl_oen <= #1 1'b0; // keep SCL low |
sda_oen <= #1 1'b1; // tri-state SDA |
sda_chk <= #1 1'b0; // don't check SDA output |
end |
|
rd_b: |
begin |
c_state <= rd_c; |
scl_oen <= 1'b1; // set SCL high |
sda_oen <= 1'b1; // keep SDA tri-stated |
sda_chk <= 1'b0; // don't check SDA output |
c_state <= #1 rd_c; |
scl_oen <= #1 1'b1; // set SCL high |
sda_oen <= #1 1'b1; // keep SDA tri-stated |
sda_chk <= #1 1'b0; // don't check SDA output |
end |
|
rd_c: |
begin |
c_state <= rd_d; |
scl_oen <= 1'b1; // keep SCL high |
sda_oen <= 1'b1; // keep SDA tri-stated |
sda_chk <= 1'b0; // don't check SDA output |
c_state <= #1 rd_d; |
scl_oen <= #1 1'b1; // keep SCL high |
sda_oen <= #1 1'b1; // keep SDA tri-stated |
sda_chk <= #1 1'b0; // don't check SDA output |
end |
|
rd_d: |
begin |
c_state <= idle; |
cmd_ack <= 1'b1; |
scl_oen <= 1'b0; // set SCL low |
sda_oen <= 1'b1; // keep SDA tri-stated |
sda_chk <= 1'b0; // don't check SDA output |
c_state <= #1 idle; |
cmd_ack <= #1 1'b1; |
scl_oen <= #1 1'b0; // set SCL low |
sda_oen <= #1 1'b1; // keep SDA tri-stated |
sda_chk <= #1 1'b0; // don't check SDA output |
end |
|
// write |
wr_a: |
begin |
c_state <= wr_b; |
scl_oen <= 1'b0; // keep SCL low |
sda_oen <= din; // set SDA |
sda_chk <= 1'b0; // don't check SDA output (SCL low) |
c_state <= #1 wr_b; |
scl_oen <= #1 1'b0; // keep SCL low |
sda_oen <= #1 din; // set SDA |
sda_chk <= #1 1'b0; // don't check SDA output (SCL low) |
end |
|
wr_b: |
begin |
c_state <= wr_c; |
scl_oen <= 1'b1; // set SCL high |
sda_oen <= din; // keep SDA |
sda_chk <= 1'b0; // don't check SDA output yet |
c_state <= #1 wr_c; |
scl_oen <= #1 1'b1; // set SCL high |
sda_oen <= #1 din; // keep SDA |
sda_chk <= #1 1'b0; // don't check SDA output yet |
// allow some time for SDA and SCL to settle |
end |
|
wr_c: |
begin |
c_state <= wr_d; |
scl_oen <= 1'b1; // keep SCL high |
sda_oen <= din; |
sda_chk <= 1'b1; // check SDA output |
c_state <= #1 wr_d; |
scl_oen <= #1 1'b1; // keep SCL high |
sda_oen <= #1 din; |
sda_chk <= #1 1'b1; // check SDA output |
end |
|
wr_d: |
begin |
c_state <= idle; |
cmd_ack <= 1'b1; |
scl_oen <= 1'b0; // set SCL low |
sda_oen <= din; |
sda_chk <= 1'b0; // don't check SDA output (SCL low) |
c_state <= #1 idle; |
cmd_ack <= #1 1'b1; |
scl_oen <= #1 1'b0; // set SCL low |
sda_oen <= #1 din; |
sda_chk <= #1 1'b0; // don't check SDA output (SCL low) |
end |
|
endcase |
/rtl/i2cm/i2cm_byte_ctrl.v
19,12 → 19,11
//// Revision : Jan 6, 2017 //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// v0.0 - Dinesh A, 6th Jan 2017 |
//// 1. Initail version picked from |
//// http://www.opencores.org/projects/i2c/ |
//// 2. renaming of reset signal to aresetn and sresetn |
//// v0.1 - Dinesh.A, 19th Jan 2017 |
//// 1. Lint Error fixes |
// v0.0 - Dinesh A, 6th Jan 2017 |
// 1. Initail version picked from |
// http://www.opencores.org/projects/i2c/ |
// 2. renaming of reset signal to aresetn and sresetn |
// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
152,24 → 151,24
// generate shift register |
always @(posedge clk or negedge aresetn) |
if (!aresetn) |
sr <= 8'h0; |
sr <= #1 8'h0; |
else if (!sresetn) |
sr <= 8'h0; |
sr <= #1 8'h0; |
else if (ld) |
sr <= din; |
sr <= #1 din; |
else if (shift) |
sr <= {sr[6:0], core_rxd}; |
sr <= #1 {sr[6:0], core_rxd}; |
|
// generate counter |
always @(posedge clk or negedge aresetn) |
if (!aresetn) |
dcnt <= 3'h0; |
dcnt <= #1 3'h0; |
else if (!sresetn) |
dcnt <= 3'h0; |
dcnt <= #1 3'h0; |
else if (ld) |
dcnt <= 3'h7; |
dcnt <= #1 3'h7; |
else if (shift) |
dcnt <= dcnt - 3'h1; |
dcnt <= #1 dcnt - 3'h1; |
|
assign cnt_done = ~(|dcnt); |
|
181,31 → 180,31
always @(posedge clk or negedge aresetn) |
if (!aresetn) |
begin |
core_cmd <= `I2C_CMD_NOP; |
core_txd <= 1'b0; |
shift <= 1'b0; |
ld <= 1'b0; |
cmd_ack <= 1'b0; |
c_state <= ST_IDLE; |
ack_out <= 1'b0; |
core_cmd <= #1 `I2C_CMD_NOP; |
core_txd <= #1 1'b0; |
shift <= #1 1'b0; |
ld <= #1 1'b0; |
cmd_ack <= #1 1'b0; |
c_state <= #1 ST_IDLE; |
ack_out <= #1 1'b0; |
end |
else if (!sresetn | i2c_al) |
begin |
core_cmd <= `I2C_CMD_NOP; |
core_txd <= 1'b0; |
shift <= 1'b0; |
ld <= 1'b0; |
cmd_ack <= 1'b0; |
c_state <= ST_IDLE; |
ack_out <= 1'b0; |
core_cmd <= #1 `I2C_CMD_NOP; |
core_txd <= #1 1'b0; |
shift <= #1 1'b0; |
ld <= #1 1'b0; |
cmd_ack <= #1 1'b0; |
c_state <= #1 ST_IDLE; |
ack_out <= #1 1'b0; |
end |
else |
begin |
// initially reset all signals |
core_txd <= sr[7]; |
shift <= 1'b0; |
ld <= 1'b0; |
cmd_ack <= 1'b0; |
core_txd <= #1 sr[7]; |
shift <= #1 1'b0; |
ld <= #1 1'b0; |
cmd_ack <= #1 1'b0; |
|
case (c_state) // synopsys full_case parallel_case |
ST_IDLE: |
213,26 → 212,26
begin |
if (start) |
begin |
c_state <= ST_START; |
core_cmd <= `I2C_CMD_START; |
c_state <= #1 ST_START; |
core_cmd <= #1 `I2C_CMD_START; |
end |
else if (read) |
begin |
c_state <= ST_READ; |
core_cmd <= `I2C_CMD_READ; |
c_state <= #1 ST_READ; |
core_cmd <= #1 `I2C_CMD_READ; |
end |
else if (write) |
begin |
c_state <= ST_WRITE; |
core_cmd <= `I2C_CMD_WRITE; |
c_state <= #1 ST_WRITE; |
core_cmd <= #1 `I2C_CMD_WRITE; |
end |
else // stop |
begin |
c_state <= ST_STOP; |
core_cmd <= `I2C_CMD_STOP; |
c_state <= #1 ST_STOP; |
core_cmd <= #1 `I2C_CMD_STOP; |
end |
|
ld <= 1'b1; |
ld <= #1 1'b1; |
end |
|
ST_START: |
240,16 → 239,16
begin |
if (read) |
begin |
c_state <= ST_READ; |
core_cmd <= `I2C_CMD_READ; |
c_state <= #1 ST_READ; |
core_cmd <= #1 `I2C_CMD_READ; |
end |
else |
begin |
c_state <= ST_WRITE; |
core_cmd <= `I2C_CMD_WRITE; |
c_state <= #1 ST_WRITE; |
core_cmd <= #1 `I2C_CMD_WRITE; |
end |
|
ld <= 1'b1; |
ld <= #1 1'b1; |
end |
|
ST_WRITE: |
256,14 → 255,14
if (core_ack) |
if (cnt_done) |
begin |
c_state <= ST_ACK; |
core_cmd <= `I2C_CMD_READ; |
c_state <= #1 ST_ACK; |
core_cmd <= #1 `I2C_CMD_READ; |
end |
else |
begin |
c_state <= ST_WRITE; // stay in same state |
core_cmd <= `I2C_CMD_WRITE; // write next bit |
shift <= 1'b1; |
c_state <= #1 ST_WRITE; // stay in same state |
core_cmd <= #1 `I2C_CMD_WRITE; // write next bit |
shift <= #1 1'b1; |
end |
|
ST_READ: |
271,17 → 270,17
begin |
if (cnt_done) |
begin |
c_state <= ST_ACK; |
core_cmd <= `I2C_CMD_WRITE; |
c_state <= #1 ST_ACK; |
core_cmd <= #1 `I2C_CMD_WRITE; |
end |
else |
begin |
c_state <= ST_READ; // stay in same state |
core_cmd <= `I2C_CMD_READ; // read next bit |
c_state <= #1 ST_READ; // stay in same state |
core_cmd <= #1 `I2C_CMD_READ; // read next bit |
end |
|
shift <= 1'b1; |
core_txd <= ack_in; |
shift <= #1 1'b1; |
core_txd <= #1 ack_in; |
end |
|
ST_ACK: |
289,36 → 288,35
begin |
if (stop) |
begin |
c_state <= ST_STOP; |
core_cmd <= `I2C_CMD_STOP; |
c_state <= #1 ST_STOP; |
core_cmd <= #1 `I2C_CMD_STOP; |
end |
else |
begin |
c_state <= ST_IDLE; |
core_cmd <= `I2C_CMD_NOP; |
c_state <= #1 ST_IDLE; |
core_cmd <= #1 `I2C_CMD_NOP; |
|
// generate command acknowledge signal |
cmd_ack <= 1'b1; |
cmd_ack <= #1 1'b1; |
end |
|
// assign ack_out output to bit_controller_rxd (contains last received bit) |
ack_out <= core_rxd; |
ack_out <= #1 core_rxd; |
|
core_txd <= 1'b1; |
core_txd <= #1 1'b1; |
end |
else |
core_txd <= ack_in; |
core_txd <= #1 ack_in; |
|
ST_STOP: |
if (core_ack) |
begin |
c_state <= ST_IDLE; |
core_cmd <= `I2C_CMD_NOP; |
c_state <= #1 ST_IDLE; |
core_cmd <= #1 `I2C_CMD_NOP; |
|
// generate command acknowledge signal |
cmd_ack <= 1'b1; |
cmd_ack <= #1 1'b1; |
end |
default: c_state <= ST_IDLE; |
|
endcase |
end |
/rtl/lib/wb_crossbar.v
14,14 → 14,9
//// Author(s): //// |
//// - Dinesh Annayya, dinesha@opencores.org //// |
//// //// |
//// Revision : Nov 26, 2016 //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// Revision : Nov 26, 2016 |
//// v-0.0 - Dinesh.A, Nov 26, 2016 |
//// 1. Initial Version |
//// v-0.1 - Dinesh.A, Jan 19, 2017 |
//// 1. Lint warning fixes, Seperated resetable and non |
// resetable logic |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
258,6 → 253,7
reg [TAR_WD -1:0] master_mx_id[WB_MASTER-1:0]; |
reg [TAR_WD -1:0] slave_mx_id [WB_SLAVE-1:0]; |
|
reg [TAR_WD-1 :0] cur_target_id; |
wire [TAR_WD-1:0] wbd_taddr_master_t[WB_MASTER-1:0]; // target address from master |
wire [D_WD-1:0] wbd_din_master_t[WB_MASTER-1:0]; // target address from master |
reg [D_WD-1:0] wbd_dout_master_t[WB_MASTER-1:0]; // target address from master |
275,7 → 271,7
reg [ADR_WD-1:0] wbd_adr_slave_t[WB_SLAVE-1:0]; // target address from master |
reg [BE_WD-1:0] wbd_be_slave_t[WB_SLAVE-1:0]; // target address from master |
|
integer i,k,l,n; |
integer i,k,l; |
|
|
/********************************************************** |
361,39 → 357,30
slave_busy <= 0; |
end else begin |
for(i = 0; i < WB_MASTER; i = i + 1) begin |
cur_target_id = wbd_taddr_master_t[i]; |
if(master_busy[i] == 0) begin |
if(wbd_stb_master[i] & slave_busy[wbd_taddr_master_t[i]] == 0) begin |
master_mx_id[i] <= wbd_taddr_master_t[i]; |
slave_mx_id [wbd_taddr_master_t[i]] <= i; |
slave_busy[wbd_taddr_master_t[i]] <= 1; |
master_busy[i] <= 1; |
end |
end else if(wbd_cyc_master[i] == 0) begin |
master_busy[i] <= 0; |
slave_busy[wbd_taddr_master_t[i]] <= 0; |
end |
end |
end |
end |
|
// Seperated non resetable two dimensional reg |
always @(posedge clk) begin |
for(n = 0; n < WB_MASTER; n = n + 1) begin |
if(master_busy[n] == 0) begin |
if(wbd_stb_master[n] & slave_busy[wbd_taddr_master_t[n]] == 0) begin |
master_mx_id[n] <= wbd_taddr_master_t[n]; |
slave_mx_id [wbd_taddr_master_t[n]] <= n; |
// synopsys translate_off |
// $display("%m:%t: Locking Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[n]); |
// $display("%m:%t: Locking Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[i]); |
// synopsys translate_on |
end |
end else if(wbd_cyc_master[n] == 0) begin |
if(master_busy[n] == 1) begin |
end else if(wbd_cyc_master[i] == 0) begin |
if(master_busy[i] == 1) begin |
// synopsys translate_off |
// $display("%m:%t: Releasing Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[n]); |
// $display("%m:%t: Releasing Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[i]); |
// synopsys translate_on |
end |
master_busy[i] <= 0; |
slave_busy[wbd_taddr_master_t[i]] <= 0; |
end |
end |
end |
end |
|
|
|
endmodule |
/rtl/lib/wb_rd_mem2mem.v
236,7 → 236,6
mem_din <= 0; |
tWrData <= 0; |
mem_wr <= 0; |
cnt <= 0; |
end |
else begin |
case(state) |
342,7 → 341,6
mem_wr <= 0; |
end |
end |
default: state <= IDLE; |
endcase |
end |
end |
/rtl/msg_handler/msg_handler.v
15,12 → 15,10
//// - Dinesh Annayya, dinesha@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// Revision: |
//// v-0.0: 27 Nov 2016 |
//// A. rtl file picked from |
//// http://www.opencores.org/cores/uart2spi/ |
//// v-0.1: 19 Jan 2017 |
//// A. Lint warning fixed for case statement |
//// Revision: //// |
//// v-0: 27 Nov 2016 //// |
//// A. rtl file picked from //// |
//// http://www.opencores.org/cores/uart2spi/ //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
171,15 → 169,6
reg_req <= 0; |
State <= `IDLE; |
NextState <= `IDLE; |
TxMsgBuf <= 0; |
TxMsgSize <= 0; |
RxMsgCnt <= 0; |
reg_addr <= 0; |
reg_wdata <= 0; |
reg_wr <= 1'b0; |
reg_req <= 1'b0; |
tx_data <= 0; |
cmd <= 0 ; |
end else begin |
case(State) |
// Send Default Message |
334,10 → 323,6
TxMsgSize <= TxMsgSize -1; |
end |
end |
default: begin |
State <= `IDLE; |
NextState <= `IDLE; |
end |
endcase |
end |
end |
/rtl/spi/spi_ctl.v
14,13 → 14,9
//// Author(s): //// |
//// - Dinesh Annayya, dinesha@opencores.org //// |
//// //// |
//// Revision : Nov 26, 2016 //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// Revision : |
//// v-0.0 : Nov 26, 2016 |
//// A. Initial Version |
//// v-0.1 : Jan 19, 2017 |
//// A. Lint warning fixes |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
198,7 → 194,6
shift_enb <= 1'b0; |
cfg_dataout <= 32'h0; |
load_byte <= 1'b0; |
op_done <= 0; |
end |
else begin |
if(sck_ne) |
310,8 → 305,6
if(!cfg_op_req) // Wait for Request de-assertion |
spiif_cs <= `SPI_IDLE; |
end |
default: spiif_cs <= `SPI_IDLE; |
|
endcase // casex(spiif_cs) |
end |
end // always @(sck_ne |
/rtl/uart/uart_rxfsm.v
14,13 → 14,11
//// Author(s): //// |
//// - Dinesh Annayya, dinesha@opencores.org //// |
//// //// |
//// Revision : //// |
//// v-0.0 : Nov 26, 2016 //// |
//// 1. Initial version picked from //// |
//// http://www.opencores.org/cores/turbo8051/ //// |
////////////////////////////////////////////////////////////////////// |
//// Revision : |
//// v-0.0 : Nov 26, 2016 |
//// 1. Initial version picked from |
//// http://www.opencores.org/cores/turbo8051/ |
//// v-0.1 : Jan 19, 2017 |
/// 1. Lint warning fix for case statement ////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
198,7 → 196,6
end |
end |
end |
default: rxstate <= idle_st; |
endcase |
end |
end |
/rtl/uart/uart_txfsm.v
14,13 → 14,12
//// Author(s): //// |
//// - Dinesh Annayya, dinesha@opencores.org //// |
//// //// |
//// Revision : //// |
//// v-0.0 : Nov 26, 2016 //// |
//// 1. Initial version picked from //// |
//// http://www.opencores.org/cores/turbo8051/ //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// Revision : |
//// v0.0 : Nov 26, 2016 |
//// 1. Initial version picked from |
//// http://www.opencores.org/cores/turbo8051/ |
//// v0.1 : Jan 19, 2017 |
//// 1. Lint fixes for case statement ////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
163,7 → 162,6
so <= 1; |
txstate <= idle_st; |
end |
default: txstate <= idle_st; |
endcase |
end |
else begin |