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URL https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk

Subversion Repositories oms8051mini

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  • This comparison shows the changes necessary to convert path 
    /oms8051mini
    from Rev 27 to Rev 26
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Rev 27 → Rev 26

/trunk/rtl/clkgen/clkgen.v
48,7 → 48,7
 
 
module clkgen (
aresetn ,
reset_n ,
fastsim_mode ,
mastermode ,
xtal_clk ,
61,7 → 61,7
 
 
 
input aresetn ; // Async reset signal
input reset_n ; // Async reset signal
input fastsim_mode ; // fast sim mode = 1
input mastermode ; // 1 : Risc master mode
input xtal_clk ; // Xtal clock-25Mhx
91,7 → 91,7
*********************************************************/
/*******************
altera_stargate_pll u_pll (
. areset (!aresetn ),
. areset (!reset_n ),
. inclk0 (xtal_clk),
. c0 (pllout),
. locked ()
105,9 → 105,9
// 100us use 25.000 Mhz clock, counter = 2500(0x9C4)
 
//--------------------------------------------
always @(posedge xtal_clk or negedge aresetn)
always @(posedge xtal_clk or negedge reset_n)
begin // {
if (!aresetn)
if (!reset_n)
begin // {
pll_count <= 12'h9C4;
end // }
126,9 → 126,9
PLL Timer Counter
************************************************/
 
always @(posedge xtal_clk or negedge aresetn)
always @(posedge xtal_clk or negedge reset_n)
begin
if (!aresetn)
if (!reset_n)
pll_done <= 0;
else if (pll_count == 16'h0)
pll_done <= 1;
140,9 → 140,9
/************************************************
internally generated reset
************************************************/
always @(posedge xtal_clk or negedge aresetn )
always @(posedge xtal_clk or negedge reset_n )
begin
if (!aresetn) begin
if (!reset_n) begin
gen_resetn <= 0;
risc_resetn <= 0;
end else if(run_st ) begin
176,9 → 176,9
assign run_st = (clkgen_ps == `RUN);
assign slave_run_st = (clkgen_ps == `SLAVE_RUN);
 
always @(posedge xtal_clk or negedge aresetn)
always @(posedge xtal_clk or negedge reset_n)
begin
if (!aresetn) begin
if (!reset_n) begin
clkgen_ps <= `HARD_RESET;
end
else begin
/trunk/rtl/core/digital_core.v
29,8 → 29,6
// 1. Uart Message Handler is integrated
// 2. Message handler is connected as Register Master to
// Inter-connect
// v0.4 - Dinesh A, 6th Jan 2017
// 1. I2C Master Core is integrated
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
61,7 → 59,7
`include "top_defines.v"
module digital_core (
 
aresetn ,
reset_n ,
scan_mode ,
scan_enable ,
fastsim_mode ,
94,19 → 92,12
spi_sck ,
spi_so ,
spi_si ,
spi_cs_n ,
spi_cs_n
 
// i2cm clock line
i2cm_scl_i ,
i2cm_scl_o ,
i2cm_scl_oen ,
 
// i2cm data line
i2cm_sda_i ,
i2cm_sda_o ,
i2cm_sda_oen
 
 
 
);
 
 
113,7 → 104,7
//----------------------------------------
// Global Clock Defination
//----------------------------------------
input aresetn ; // Async Active Low Reset
input reset_n ; // Active Low Reset
input scan_mode ; // scan mode
input scan_enable ; // scan enable
input fastsim_mode ; // Fast Sim Mode
159,21 → 150,8
input spi_si ; // data in
output [3:0] spi_cs_n ; // chip select
 
//----------------------------------------
// i2cm clock line
//----------------------------------------
input i2cm_scl_i ;
output i2cm_scl_o ;
output i2cm_scl_oen ;
 
//----------------------------------------
// i2cm data line
//----------------------------------------
input i2cm_sda_i ;
output i2cm_sda_o ;
output i2cm_sda_oen ;
 
//----------------------------------------
// 8051 core RAM related signals
//---------------------------------------
wire [15:0] wb_xram_adr ; // data-ram address
186,19 → 164,7
wire wb_xram_stb ; // data-ram strobe
wire wb_xram_cyc ; // data-ram cycle
 
//----------------------------------------
// i2CM Wishbone I/F
//---------------------------------------
wire [15:0] wb_i2cm_addr ; // data-ram address
wire wb_i2cm_ack ; // data-ram acknowlage
wire wb_i2cm_err ; // data-ram error
wire wb_i2cm_we ; // data-ram error
wire [7:0] wb_i2cm_rdata ; // ram data input
wire [7:0] wb_i2cm_wdata ; // ram data input
 
wire wb_i2cm_stb ; // data-ram strobe
wire wb_i2cm_cyc ; // data-ram cycle
 
//----------------------------------------
// Message Controller Reg Master
//---------------------------------------
257,7 → 223,7
// clock-gen instantiation
//-------------------------------------------
clkgen u_clkgen (
. aresetn (aresetn ),
. reset_n (reset_n ),
. fastsim_mode (fastsim_mode ),
. mastermode (mastermode ),
. xtal_clk (xtal_clk ),
272,7 → 238,7
/************* Message Handler **********/
 
msg_handler_top u_msg_hand_top (
. line_reset_n (aresetn ),
. line_reset_n (reset_n ),
. line_clk (app_clk ),
 
// Towards Register Interface
308,10 → 274,8
// 0x0000 to 0x7FFFF - Data Memory
// 0x8000 to 0x8FFF - SPI
// 0x9000 to 0x9FFF - UART
// 0xA000 to 0xAFFF - I2CM
//--------------------------------------------------------------
// Target ID Mapping
// 4'b0011 -- I2CM
// 4'b0010 -- UART
// 4'b0001 -- SPI core
// 4'b0000 -- External RAM
319,16 → 283,14
//
wire [3:0] wbd_tar_id = (wbd_risc_adr[15] == 1'b0 ) ? 4'b0000 :
(wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0001 :
(wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0010 :
(wbd_risc_adr[15:12] == 4'b1010 ) ? 4'b0011 : 4'b0000;
(wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0010 : 4'b0000;
 
wire [3:0] mh_tar_id = (mh_reg_addr[15] == 1'b0 ) ? 4'b0000 :
(mh_reg_addr[15:12] == 4'b1000 ) ? 4'b0001 :
(mh_reg_addr[15:12] == 4'b1001 ) ? 4'b0010 :
(mh_reg_addr[15:12] == 4'b1010 ) ? 4'b0011 : 4'b0000;
(mh_reg_addr[15:12] == 4'b1001 ) ? 4'b0010 : 4'b0000;
 
wb_crossbar #(.WB_MASTER(3),
.WB_SLAVE(4),
.WB_SLAVE(3),
.D_WD(8),
.BE_WD(1),
.ADR_WD(15),
379,50 → 341,38
.wbd_rty_master (),
// Slave Interface Signal
.wbd_din_slave ({wb_i2cm_wdata,
reg_uart_wdata,
.wbd_din_slave ({reg_uart_wdata,
reg_spi_wdata,
wb_xram_wdata
}),
 
.wbd_dout_slave ({wb_i2cm_rdata,
reg_uart_rdata,
.wbd_dout_slave ({reg_uart_rdata,
reg_spi_rdata,
wb_xram_rdata
}),
 
.wbd_adr_slave ({wb_i2cm_addr[14:0],
reg_uart_addr[14:0],
.wbd_adr_slave ({reg_uart_addr[14:0],
reg_spi_addr[14:0],
wb_xram_adr[14:0]
}
wb_xram_adr[14:0]}
),
 
.wbd_be_slave (),
 
.wbd_we_slave ({wb_i2cm_we,
reg_uart_wr,
.wbd_we_slave ({reg_uart_wr,
reg_spi_wr,
wb_xram_wr
}),
 
.wbd_ack_slave ({wb_i2cm_ack,
reg_uart_ack,
.wbd_ack_slave ({reg_uart_ack,
reg_spi_ack,
wb_xram_ack
}),
.wbd_stb_slave ({wb_i2cm_stb,
reg_uart_cs,
.wbd_stb_slave ({reg_uart_cs,
reg_spi_cs,
wb_xram_stb
}),
 
.wbd_cyc_slave ({wb_i2cm_cyc,
wb_uart_cyc,
wb_spi_cyc,
wb_xram_cyc
}),
.wbd_cyc_slave (),
.wbd_err_slave (),
.wbd_rty_slave ()
);
489,42 → 439,8
 
);
 
/******************************************************
* I2C Master Core
* ***************************************************/
i2cm_top i_i2cm (
// wishbone signals
.wb_clk_i (app_clk ),
.sresetn (gen_resetn ),
.aresetn (aresetn ),
.wb_adr_i (wb_i2cm_addr[2:0] ),
.wb_dat_i (wb_i2cm_wdata ),
.wb_dat_o (wb_i2cm_rdata ),
.wb_we_i (wb_i2cm_we ),
.wb_stb_i (wb_i2cm_stb ),
.wb_cyc_i (wb_i2cm_cyc ),
.wb_ack_o (wb_i2cm_ack ),
.wb_inta_o (i2cm_inta ),
 
// I2C signals
// i2c clock line
.scl_pad_i (i2cm_scl_i ),
.scl_pad_o (i2cm_scl_o ),
.scl_padoen_o (i2cm_scl_oen ),
 
// i2c data line
.sda_pad_i (i2cm_sda_i ),
.sda_pad_o (i2cm_sda_o ),
.sda_padoen_o (i2cm_sda_oen )
 
);
 
 
 
/******************************************************
* 8051 Core
*******************************************************/
 
oc8051_top u_8051_core (
. resetn (risc_resetn ),
. wb_clk_i (app_clk ),
601,7 → 517,7
//
oc8051_xram oc8051_xram1 (
.clk (app_clk ),
.rst (!aresetn ),
.rst (!reset_n ),
.wr (wb_xram_wr ),
.addr (wb_xram_adr ),
.data_in (wb_xram_wdata ),
/trunk/verif/run/filelist_rtl.f
51,7 → 51,4
../../rtl/model/oc8051_xram.v \
../../rtl/model/oc8051_xrom.v \
../../rtl/msg_handler/msg_handler.v \
../../rtl/msg_handler/msg_handler_top.v \
../../rtl/i2cm/i2cm_bit_ctrl.v \
../../rtl/i2cm/i2cm_byte_ctrl.v \
../../rtl/i2cm/i2cm_top.v
../../rtl/msg_handler/msg_handler_top.v
/trunk/verif/tb/tb_top.v
133,7 → 133,7
 
digital_core u_core (
 
. aresetn (reset_n ),
. reset_n (reset_n ),
. fastsim_mode (1'b1 ),
. mastermode (master_mode ),
 

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