OpenCores
URL https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk

Subversion Repositories oms8051mini

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /oms8051mini/trunk
    from Rev 13 to Rev 14
    ↔ Reverse comparison
  •

Rev 13 → Rev 14

/rtl/core/digital_core.v
156,13 → 156,7
wire wb_xram_cyc ; // data-ram cycle
 
 
//---------------------------------------------
// 8051 Instruction ROM interface
//---------------------------------------------
wire [15:0] wbi_risc_adr;
wire [7:0] wbi_risc_rdata;
 
 
//-----------------------------
// wire Decleration
//-----------------------------
242,7 → 236,7
(wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0001 :
(wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0010 : 4'b0000;
 
wb_crossbar #(.WB_MASTER(3),
wb_crossbar #(.WB_MASTER(2),
.WB_SLAVE(3),
.D_WD(8),
.BE_WD(1),
255,37 → 249,30
 
 
// Master Interface Signal
.wbd_taddr_master ({4'b0000,
wbd_tar_id,
.wbd_taddr_master ({ wbd_tar_id,
ext_reg_tid }),
 
.wbd_din_master ({8'h0 ,
wbd_risc_wdata[7:0],
.wbd_din_master ({wbd_risc_wdata[7:0],
ext_reg_wdata }
),
 
.wbd_dout_master ({wbi_risc_rdata,
wb_master2_rdata,
.wbd_dout_master ({wb_master2_rdata,
ext_reg_rdata}),
 
.wbd_adr_master ({wbi_risc_adr[14:0],
wbd_risc_adr[14:0],
.wbd_adr_master ({wbd_risc_adr[14:0],
ext_reg_addr[14:0]}),
 
.wbd_be_master ({1'b1,1'b1,1'b1}),
.wbd_be_master ({1'b1,1'b1}),
 
.wbd_we_master ({1'b0,wbd_risc_we,ext_reg_wr } ),
.wbd_we_master ({wbd_risc_we,ext_reg_wr } ),
 
.wbd_ack_master ({wbi_risc_ack,
wbd_risc_ack,
.wbd_ack_master ({wbd_risc_ack,
ext_reg_ack } ),
 
.wbd_stb_master ({1'b0,
wbd_risc_stb,
.wbd_stb_master ({wbd_risc_stb,
ext_reg_cs} ),
 
.wbd_cyc_master ({1'b0,
wbd_risc_stb|wbd_risc_ack,
.wbd_cyc_master ({wbd_risc_stb|wbd_risc_ack,
ext_reg_cs|ext_reg_ack }),
 
.wbd_err_master (),
/verif/run/dat/oc8051_xrom.in
1,147 → 1,449
///
/// created by oc8051 rom maker
/// author: Simon Teran (simont@opencores.org)
///
/// source file: d:\uart_lb.hex
/// date: 12/9/2016
/// time: 8:50:09 PM
///
02
00
08
12
00
64
80
FE
75
81
0C
12
00
87
E5
82
60
03
02
00
03
79
00
E9
44
00
60
1B
7A
00
90
00
8B
78
00
75
A0
00
E4
93
F2
A3
08
B8
00
02
05
A0
D9
F4
DA
F2
75
A0
FF
E4
78
FF
F6
D8
FD
78
00
E8
44
00
60
0A
79
00
75
A0
00
E4
F3
09
D8
FC
78
00
E8
44
00
60
0C
79
00
90
00
00
E4
F0
A3
D8
FC
D9
FA
02
00
03
90
90
00
74
07
F0
90
90
02
E4
F0
90
90
03
F0
E4
90
90
04
E0
FA
20
E1
F8
90
90
06
E0
FA
90
90
05
F0
80
ED
75
82
00
22
02
00
08
12
01
51
80
FE
75
81
20
12
01
A3
E5
82
60
03
02
00
03
79
00
E9
44
00
60
1B
7A
00
90
01
A7
78
00
75
A0
00
E4
93
F2
A3
08
B8
00
02
05
A0
D9
F4
DA
F2
75
A0
FF
E4
78
FF
F6
D8
FD
78
00
E8
44
00
60
0A
79
00
75
A0
00
E4
F3
09
D8
FC
78
00
E8
44
00
60
0C
79
00
90
00
00
E4
F0
A3
D8
FC
D9
FA
02
00
03
85
82
14
85
83
15
85
F0
16
74
01
12
01
6E
25
14
FD
E4
35
15
FE
AF
16
8D
82
8E
83
8F
F0
74
01
12
01
6E
75
17
02
C3
E5
17
95
13
50
56
E5
17
25
14
FE
E4
35
15
FF
A8
16
A9
17
7A
00
E9
24
FF
FB
EA
34
FF
FC
EB
25
14
FB
EC
35
15
FC
AD
16
8B
82
8C
83
8D
F0
12
01
87
FB
E9
24
FE
F9
EA
34
FF
FA
E9
25
14
F9
EA
35
15
FA
AC
16
89
82
8A
83
8C
F0
12
01
87
F9
2B
FB
8E
82
8F
83
88
F0
12
01
6E
05
17
80
A3
22
85
82
14
85
83
15
85
F0
16
75
17
01
75
18
01
75
19
02
75
1A
03
75
1B
05
75
1C
08
75
1D
0D
75
1E
15
75
1F
22
75
20
37
7D
00
C3
ED
95
13
50
29
ED
25
14
FE
E4
35
15
FF
AA
16
8E
82
8F
83
8A
F0
12
01
87
FE
8E
80
ED
24
17
F8
86
02
8A
90
EE
B5
02
02
80
02
05
08
0D
80
D1
E5
08
60
07
75
A0
55
85
08
B0
22
75
A0
AA
75
B0
AA
22
75
08
00
75
13
0A
90
00
09
75
F0
40
12
00
64
75
13
0A
90
00
09
75
F0
40
12
00
E7
80
FE
20
F7
10
30
F6
11
88
83
A8
82
20
F5
07
F6
A8
83
75
83
00
22
F2
80
F7
F0
22
20
F7
14
30
F6
14
88
83
A8
82
20
F5
07
E6
A8
83
75
83
00
22
E2
80
F7
E4
93
22
E0
22
75
82
00
22
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
/verif/run/compile.modelsim
4,68 → 4,4
vlib work
endif
 
vlog -work work
+define+SFLASH_SPDUP \
-sv \
+incdir+../defs \
+incdir+../../rtl/defs \
+incdir+../../rtl/8051 \
+incdir+../agents/spi \
+incdir+../agents/spi/st_m25p20a \
+incdir+../lib \
+incdir+../testcase \
+incdir+../tb \
time_scale.v \
../tb/tb_top.v \
../../verif/agents/uart/uart_agent.v \
../../verif/agents/spi/atmel/AT45DBXXX_v2.0.3.v \
../../verif/agents/spi/st_m25p20a/acdc_check.v \
../../verif/agents/spi/st_m25p20a/internal_logic.v \
../../verif/agents/spi/st_m25p20a/memory_access.v \
../../verif/agents/spi/st_m25p20a/M25P20.v \
../../verif/model/oc8051_xram.v \
../../verif/model/oc8051_xrom.v \
../../rtl/core/digital_core.v \
../../rtl/lib/g_dpath_ctrl.v \
../../rtl/spi/spi_core.v \
../../rtl/spi/spi_ctl.v \
../../rtl/spi/spi_if.v \
../../rtl/spi/spi_cfg.v \
../../rtl/uart/uart_rxfsm.v \
../../rtl/uart/uart_txfsm.v \
../../rtl/uart/uart_core.v \
../../rtl/uart/uart_cfg.v \
../../rtl/clkgen/clkgen.v \
../../rtl/lib/clk_ctl.v \
../../rtl/lib/wb_crossbar.v \
../../rtl/lib/wb_rd_mem2mem.v \
../../rtl/lib/wb_wr_mem2mem.v \
../../rtl/8051/oc8051_top.v \
../../rtl/8051/oc8051_rom.v \
../../rtl/8051/oc8051_alu_src_sel.v \
../../rtl/8051/oc8051_alu.v \
../../rtl/8051/oc8051_decoder.v \
../../rtl/8051/oc8051_divide.v \
../../rtl/8051/oc8051_multiply.v \
../../rtl/8051/oc8051_memory_interface.v \
../../rtl/8051/oc8051_ram_top.v \
../../rtl/8051/oc8051_acc.v \
../../rtl/8051/oc8051_comp.v \
../../rtl/8051/oc8051_sp.v \
../../rtl/8051/oc8051_dptr.v \
../../rtl/8051/oc8051_cy_select.v \
../../rtl/8051/oc8051_psw.v \
../../rtl/8051/oc8051_indi_addr.v \
../../rtl/8051/oc8051_ports.v \
../../rtl/8051/oc8051_b_register.v \
../../rtl/8051/oc8051_uart.v \
../../rtl/8051/oc8051_int.v \
../../rtl/8051/oc8051_tc.v \
../../rtl/8051/oc8051_tc2.v \
../../rtl/8051/oc8051_sfr.v \
../../rtl/8051/oc8051_ram_256x8_two_bist.v \
-v ../../rtl/lib/registers.v \
-v ../../rtl/lib/stat_counter.v \
-v ../../rtl/lib/toggle_sync.v \
-v ../../rtl/lib/double_sync_low.v \
-v ../../rtl/lib/async_fifo.v
vlog -work work +define+SFLASH_SPDUP -sv -f filelist_top.f

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.