URL https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk

Subversion Repositories oms8051mini

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This comparison shows the changes necessary to convert path
```
/oms8051mini/trunk
```
from Rev 8 to Rev 9
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With Path: Rev

Rev 8 → Rev 9

0,0 → 1,76

+ +Model Technology ModelSim ACTEL vlog 10.1b Compiler 2012.04 Apr 27 2012 +-- Compiling module tb_top +-- Compiling module tb_glbl +-- Compiling module uart_agent +-- Compiling module AT45DB321 +-- Compiling module acdc_check +-- Compiling module internal_logic +-- Compiling module memory_access +-- Compiling module m25p20 +-- Compiling module oc8051_xram +-- Compiling module oc8051_xrom +-- Compiling module digital_core +-- Compiling module g_dpath_ctrl +-- Compiling module spi_core +-- Compiling module spi_ctl +-- Compiling module spi_if +-- Compiling module spi_cfg +-- Compiling module uart_rxfsm +-- Compiling module uart_txfsm +-- Compiling module uart_core +-- Compiling module uart_cfg +-- Compiling module clkgen +-- Compiling module clk_ctl +-- Compiling module wb_crossbar +-- Compiling module wb_rd_mem2mem +-- Compiling module wb_wr_mem2mem +-- Compiling module oc8051_top +-- Compiling module oc8051_rom +-- Compiling module oc8051_alu_src_sel +-- Compiling module oc8051_alu +-- Compiling module oc8051_decoder +-- Compiling module oc8051_divide +-- Compiling module oc8051_multiply +-- Compiling module oc8051_memory_interface +-- Compiling module oc8051_ram_top +-- Compiling module oc8051_acc +-- Compiling module oc8051_comp +-- Compiling module oc8051_sp +-- Compiling module oc8051_dptr +-- Compiling module oc8051_cy_select +-- Compiling module oc8051_psw +-- Compiling module oc8051_indi_addr +-- Compiling module oc8051_ports +-- Compiling module oc8051_b_register +-- Compiling module oc8051_uart +-- Compiling module oc8051_int +-- Compiling module oc8051_tc +-- Compiling module oc8051_tc2 +-- Compiling module oc8051_sfr +-- Compiling module oc8051_ram_256x8_two_bist +-- Scanning library file '../../rtl/lib/registers.v' +-- Compiling module req_register +-- Compiling module stat_register +-- Compiling module generic_register +-- Scanning library file '../../rtl/lib/stat_counter.v' +-- Scanning library file '../../rtl/lib/toggle_sync.v' +-- Scanning library file '../../rtl/lib/double_sync_low.v' +-- Compiling module double_sync_low +-- Scanning library file '../../rtl/lib/async_fifo.v' +-- Compiling module async_fifo +-- Scanning library file '../../rtl/lib/registers.v' +-- Compiling module bit_register +-- Scanning library file '../../rtl/lib/stat_counter.v' +-- Scanning library file '../../rtl/lib/toggle_sync.v' +-- Scanning library file '../../rtl/lib/double_sync_low.v' +-- Scanning library file '../../rtl/lib/async_fifo.v' + +Top level modules: + tb_top + g_dpath_ctrl + wb_rd_mem2mem + wb_wr_mem2mem + oc8051_rom + oc8051_uart

/verif/glog/modelsim/ext_cast.log

0,0 → 1,110