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Rev 9 → Rev 10

/rtl/core/digital_core.v
17,8 → 17,12
//// Revision : Nov 26, 2016 ////
//// ////
//////////////////////////////////////////////////////////////////////
// v0 - Dinesh A, 26th Nov 2016
// v0.0 - Dinesh A, 26th Nov 2016
// 1. MAC related logic are remved
// v0.1 - Dinesh A, 1st Dec 2016
// 1. RAM and ROM are internally connected to interconnect
// 2. Memory Map Change
// 3. Remove the External ROM Option & Enabled Internal ROM
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
57,6 → 61,7
xtal_clk ,
clkout ,
reset_out_n ,
ea_in ,
 
// Reg Bus Interface Signal
ext_reg_cs ,
80,36 → 85,12
spi_sck ,
spi_so ,
spi_si ,
spi_cs_n ,
spi_cs_n
 
 
// External ROM interface
wb_xrom_adr ,
wb_xrom_ack ,
wb_xrom_err ,
wb_xrom_wr ,
wb_xrom_rdata ,
wb_xrom_wdata ,
wb_xrom_stb ,
wb_xrom_cyc ,
 
// External RAM interface
wb_xram_adr ,
wb_xram_ack ,
wb_xram_err ,
wb_xram_wr ,
wb_xram_be ,
wb_xram_rdata ,
wb_xram_wdata ,
wb_xram_stb ,
wb_xram_cyc,
 
ea_in
 
 
 
);
 
 
121,6 → 102,9
input scan_enable ; // scan enable
input fastsim_mode ; // Fast Sim Mode
input mastermode ; // 1 : Risc master mode
input ea_in ; // input for external access (ea signal)
// ea=0 program is in external rom
// ea=1 program is in internal rom
 
input xtal_clk ; // xtal clock 25Mhz
output clkout ; // clock output
157,38 → 141,22
input spi_si ; // data in
output [3:0] spi_cs_n ; // chip select
 
//----------------------------------------
// 8051 core ROM related signals
//---------------------------------------
output [15:0] wb_xrom_adr ; // instruction address
input wb_xrom_ack ; // instruction acknowlage
output wb_xrom_err ; // instruction error
output wb_xrom_wr ; // instruction error
input [31:0] wb_xrom_rdata ; // rom data input
output [31:0] wb_xrom_wdata ; // rom data input
 
output wb_xrom_stb ; // instruction strobe
output wb_xrom_cyc ; // instruction cycle
 
 
//----------------------------------------
// 8051 core RAM related signals
//---------------------------------------
output [15:0] wb_xram_adr ; // data-ram address
input wb_xram_ack ; // data-ram acknowlage
output wb_xram_err ; // data-ram error
output wb_xram_wr ; // data-ram error
output [3:0] wb_xram_be ; // Byte enable
input [31:0] wb_xram_rdata ; // ram data input
output [31:0] wb_xram_wdata ; // ram data input
wire [15:0] wb_xram_adr ; // data-ram address
wire wb_xram_ack ; // data-ram acknowlage
wire wb_xram_err ; // data-ram error
wire wb_xram_wr ; // data-ram error
wire [3:0] wb_xram_be ; // Byte enable
wire [31:0] wb_xram_rdata ; // ram data input
wire [31:0] wb_xram_wdata ; // ram data input
 
output wb_xram_stb ; // data-ram strobe
output wb_xram_cyc ; // data-ram cycle
wire wb_xram_stb ; // data-ram strobe
wire wb_xram_cyc ; // data-ram cycle
 
 
input ea_in ; // input for external access (ea signal)
// ea=0 program is in external rom
// ea=1 program is in internal rom
//---------------------------------------------
// 8051 Instruction ROM interface
//---------------------------------------------
223,7 → 191,6
wire reg_spi_ack ;
 
wire [3:0] wb_xrom_be ;
wire [3:0] wb_xram_be ;
 
wire [7:0] p0 ;
wire [7:0] p1 ;
242,12 → 209,7
 
assign wb_xram_adr[15] = 0;
assign wb_xram_adr[1:0] = 2'b00;
assign wb_xrom_adr[15:13] = 0;
 
wire [9:0] cfg_tx_buf_qbase_addr;
wire [9:0] cfg_rx_buf_qbase_addr;
 
 
assign reg_uart_addr[1:0] = 2'b0;
assign reg_spi_addr[1:0] = 2'b0;
//-------------------------------------------
284,22 → 246,19
// 0x0000 to 0x7FFFF - Data Memory
// 0x8000 to 0x8FFF - SPI
// 0x9000 to 0x9FFF - UART
// 0xA000 to 0xAFFF - MAC Core
//--------------------------------------------------------------
// Target ID Mapping
// 4'b0100 -- MAC core
// 4'b0011 -- UART
// 4'b0010 -- SPI core
// 4'b0001 -- External RAM
// 4'b0000 -- External ROM
// 4'b0010 -- UART
// 4'b0001 -- SPI core
// 4'b0000 -- External RAM
//--------------------------------------------------------------
//
wire [3:0] wbd_tar_id = (wbd_risc_adr[15] == 1'b0 ) ? 4'b0001 :
(wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0010 :
(wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0011 : 4'b0100;
wire [3:0] wbd_tar_id = (wbd_risc_adr[15] == 1'b0 ) ? 4'b0000 :
(wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0001 :
(wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0010 : 4'b0000;
 
wb_crossbar #(.WB_MASTER(3),
.WB_SLAVE(4),
.WB_SLAVE(3),
.D_WD(32),
.BE_WD(4),
.ADR_WD(13),
342,11 → 301,11
wbd_risc_ack,
ext_reg_ack } ),
 
.wbd_stb_master ({wbi_risc_stb,
.wbd_stb_master ({1'b0,
wbd_risc_stb,
ext_reg_cs} ),
 
.wbd_cyc_master ({wbi_risc_stb|wbi_risc_ack,
.wbd_cyc_master ({1'b0,
wbd_risc_stb|wbd_risc_ack,
ext_reg_cs|ext_reg_ack }),
 
356,43 → 315,36
// Slave Interface Signal
.wbd_din_slave ({reg_uart_wdata,
reg_spi_wdata,
wb_xram_wdata,
wb_xrom_wdata
wb_xram_wdata
}),
 
.wbd_dout_slave ({reg_uart_rdata,
reg_spi_rdata,
{wb_xram_rdata},
wb_xrom_rdata
{wb_xram_rdata}
}),
 
.wbd_adr_slave ({reg_uart_addr[14:2],
reg_spi_addr[14:2],
wb_xram_adr[14:2],
wb_xrom_adr[12:0]}
wb_xram_adr[14:2]}
),
 
.wbd_be_slave ({reg_uart_be,
reg_spi_be,
wb_xram_be,
wb_xrom_be}
wb_xram_be }
),
 
.wbd_we_slave ({reg_uart_wr,
reg_spi_wr,
wb_xram_wr,
wb_xrom_wr
wb_xram_wr
}),
 
.wbd_ack_slave ({reg_uart_ack,
reg_spi_ack,
wb_xram_ack,
wb_xrom_ack
wb_xram_ack
}),
.wbd_stb_slave ({reg_uart_cs,
reg_spi_cs,
wb_xram_stb,
wb_xrom_stb
wb_xram_stb
}),
 
.wbd_cyc_slave (),
543,4 → 495,21
.ea_in (ea_in )
);
 
//
// external data ram
//
oc8051_xram oc8051_xram1 (
.clk (app_clk ),
.rst (!reset_n ),
.wr (wb_xram_wr ),
.be (wb_xram_be ),
.addr (wb_xram_adr ),
.data_in (wb_xram_wdata ),
.data_out (wb_xram_rdata ),
.ack (wb_xram_ack ),
.stb (wb_xram_stb )
);
 
 
defparam oc8051_xram1.DELAY = 2;
endmodule
/rtl/defs/top_defines.v
61,7 → 61,7
//
// oc8051 ITERNAL ROM
//
//`define OC8051_ROM
`define OC8051_ROM
 
 
//
/rtl/lib/wb_crossbar.v
254,7 → 254,7
reg [TAR_WD -1:0] slave_mx_id [WB_SLAVE-1:0];
 
reg [TAR_WD-1 :0] cur_target_id;
wire [TAR_WD-1:0] wbd_taddr_master_t[WB_MASTER:0]; // target address from master
wire [TAR_WD-1:0] wbd_taddr_master_t[WB_MASTER-1:0]; // target address from master
wire [D_WD-1:0] wbd_din_master_t[WB_MASTER-1:0]; // target address from master
reg [D_WD-1:0] wbd_dout_master_t[WB_MASTER-1:0]; // target address from master
wire [ADR_WD-1:0] wbd_adr_master_t[WB_MASTER-1:0]; // target address from master
353,27 → 353,29
 
always @(negedge rst_n or posedge clk) begin
if(rst_n == 0) begin
master_busy = 0;
slave_busy = 0;
cur_target_id = 0;
end
else begin
master_busy <= 0;
slave_busy <= 0;
end else begin
for(i = 0; i < WB_MASTER; i = i + 1) begin
cur_target_id = wbd_taddr_master_t[i];
if(master_busy[i] == 0) begin
if(wbd_stb_master[i] & slave_busy[cur_target_id] == 0) begin
master_mx_id[i] <= cur_target_id;
slave_mx_id [cur_target_id] = i;
slave_busy[cur_target_id] = 1;
master_busy[i] = 1;
if(wbd_stb_master[i] & slave_busy[wbd_taddr_master_t[i]] == 0) begin
master_mx_id[i] <= wbd_taddr_master_t[i];
slave_mx_id [wbd_taddr_master_t[i]] <= i;
slave_busy[wbd_taddr_master_t[i]] <= 1;
master_busy[i] <= 1;
// synopsys translate_off
// $display("%m:%t: Locking Master : %d with Slave : %d",$time,i,cur_target_id);
// $display("%m:%t: Locking Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[i]);
// synopsys translate_on
end
end else if(wbd_cyc_master[i] == 0) begin
master_busy[i] = 0;
slave_busy[cur_target_id] = 0;
if(master_busy[i] == 1) begin
// synopsys translate_off
// $display("%m:%t: Releasing Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[i]);
// synopsys translate_on
end
master_busy[i] <= 0;
slave_busy[wbd_taddr_master_t[i]] <= 0;
end
end
end
/rtl/model/oc8051_xram.v
0,0 → 1,138
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 external data ram ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// external data ram ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/10/17 18:53:04 simont
// added parameter DELAY
//
// Revision 1.3 2002/09/30 17:34:01 simont
// prepared header
//
//
 
 
module oc8051_xram (clk, rst, wr, be, addr, data_in, data_out, ack, stb);
//
// external data ram for simulation. part of oc8051_tb
// it's tehnology dependent
//
// clk (in) clock
// addr (in) addres
// data_in (out) data input
// data_out (in) data output
// wr (in) write
// ack (out) acknowlage
// stb (in) strobe
//
 
parameter DELAY=1;
 
 
input clk, wr, stb, rst;
input [3:0] be; // byte enable
input [31:0] data_in;
input [15:0] addr;
output [31:0] data_out;
output ack;
 
reg ackw, ackr;
reg [31:0] data_out;
reg [2:0] cnt;
integer i;
//
// buffer
reg [7:0] buff [65535:0]; //64kb
//reg [7:0] buff [8388607:0]; //8Mb
 
assign ack = ackw || ackr;
 
 
// Intialise the memory
 
initial
begin
for (i=0; i<65536; i=i+1)
buff [i] = 8'h00;
end
 
//
// writing to ram
always @(posedge clk or posedge rst)
begin
if (rst)
ackw <= #1 1'b0;
else if (wr && stb && ((DELAY==3'b000) || (cnt==3'b000))) begin
if(be[0]) buff[addr] <= #1 data_in[7:0];
if(be[1]) buff[addr+1] <= #1 data_in[15:8];
if(be[2]) buff[addr+2] <= #1 data_in[23:16];
if(be[3]) buff[addr+3] <= #1 data_in[31:24];
ackw <= #1 1'b1;
end else ackw <= #1 1'b0;
end
 
always @(posedge clk or posedge rst)
if (rst)
ackr <= #1 1'b0;
else if (stb && !wr && ((DELAY==3'b000) || (cnt==3'b000))) begin
data_out <= #1 {buff[addr+3], buff[addr+2], buff[addr+1], buff [addr]};
ackr <= #1 1'b1;
end else begin
ackr <= #1 1'b0;
data_out <= #1 8'h00;
end
 
always @(posedge clk or posedge rst)
begin
if (rst)
cnt <= #1 DELAY;
else if (cnt==3'b000)
cnt <= #1 DELAY;
else if (stb)
cnt <= #1 cnt - 3'b001;
else cnt <= #1 DELAY;
end
 
 
endmodule
/rtl/model/oc8051_xrom.v
0,0 → 1,114
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 exteranl program rom ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// external program rom for 8051 core ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2003/04/02 11:38:40 simont
// initial inport
//
// Revision 1.1 2002/10/17 18:56:13 simont
// initial CVS input
//
//
 
module oc8051_xrom (rst, clk, addr, data, stb_i, cyc_i, ack_o);
 
parameter DELAY=5;
 
 
input rst, clk, stb_i, cyc_i;
input [15:0] addr;
output ack_o;
output [31:0] data;
 
 
reg ack_o;
reg [31:0] data;
 
reg [7:0] buff [0:65535];
//reg [7:0] buff [8388607:0];
reg [2:0] cnt;
integer i;
 
 
wire [7:0] buff_0 = buff [0];
wire [7:0] buff_1 = buff [1];
wire [7:0] buff_2 = buff [2];
wire [7:0] buff_3 = buff [3];
 
initial
begin
// for (i=0; i<65536; i=i+1)
// buff [i] = 8'h00;
$readmemh("./dat/oc8051_xrom.in", buff);
for (i=0; i<10; i=i+1)
$display("i : %h",buff [i] );
end
 
always @(posedge clk or posedge rst)
begin
if (rst) begin
data <= #1 31'h0;
ack_o <= #1 1'b0;
end else if (stb_i && ((DELAY==3'b000) || (cnt==3'b000))) begin
data <= #1 {buff[addr+3], buff[addr+2], buff[addr+1], buff [addr]};
ack_o <= #1 1'b1;
end else
ack_o <= #1 1'b0;
end
 
always @(posedge clk or posedge rst)
begin
if (rst)
cnt <= #1 DELAY;
else if (cnt == 3'b000)
cnt <= #1 DELAY;
else if (stb_i)
cnt <= #1 cnt - 3'b001;
else cnt <= #1 DELAY;
end
 
endmodule
 
 
/verif/agents/spi/spi_tasks.v
31,8 → 31,8
begin
 
@(posedge tb_top.app_clk)
tb_top.cpu_write('h2,'h4,{datain,24'h0});
tb_top.cpu_write('h2,'h0,{1'b1,6'h0,
tb_top.cpu_write(`ADDR_SPACE_SPI,'h4,{datain,24'h0});
tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,6'h0,
spi_chip_no[1:0],
2'b0, // Write Operatopm
2'b0, // Single Transfer
40,10 → 40,10
5'h2, // cs setup/hold period
8'h40 }); // cs bit information
tb_top.cpu_read('h2,'h0,read_data);
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
while(read_data[31]) begin
@(posedge tb_top.app_clk) ;
tb_top.cpu_read('h2,'h0,read_data);
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
end
end
endtask
55,8 → 55,8
reg [31:0] read_data;
begin
@(posedge tb_top.app_clk)
tb_top.cpu_write('h2,'h4,{cmd});
tb_top.cpu_write('h2,'h0,{1'b1,6'h0,
tb_top.cpu_write(`ADDR_SPACE_SPI,'h4,{cmd});
tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,6'h0,
spi_chip_no[1:0],
2'b0, // Write Operatopm
2'h3, // 4 Transfer
64,10 → 64,10
5'h2, // cs setup/hold period
cs_byte[7:0] }); // cs bit information
tb_top.cpu_read('h2,'h0,read_data);
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
while(read_data[31]) begin
@(posedge tb_top.app_clk) ;
tb_top.cpu_read('h2,'h0,read_data);
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
end
end
endtask
81,7 → 81,7
begin
 
@(posedge tb_top.app_clk)
tb_top.cpu_write('h2,'h0,{1'b1,6'h0,
tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,6'h0,
spi_chip_no[1:0],
2'b1, // Read Operatopm
2'h3, // 4 Transfer
89,14 → 89,14
5'h2, // cs setup/hold period
cs_byte[7:0] }); // cs bit information
tb_top.cpu_read('h2,'h0,read_data);
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
 
while(read_data[31]) begin
@(posedge tb_top.app_clk) ;
tb_top.cpu_read('h2,'h0,read_data);
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
end
 
tb_top.cpu_read('h2,'h8,dataout);
tb_top.cpu_read(`ADDR_SPACE_SPI,'h8,dataout);
 
end
endtask
109,8 → 109,8
begin
 
@(posedge tb_top.app_clk) ;
tb_top.cpu_write('h2,'h4,{8'hD8,address[23:0]});
tb_top.cpu_write('h2,'h0,{1'b1,6'h0,
tb_top.cpu_write(`ADDR_SPACE_SPI,'h4,{8'hD8,address[23:0]});
tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,6'h0,
spi_chip_no[1:0],
2'b0, // Write Operatopm
2'h3, // 4 Transfer
118,15 → 118,15
5'h2, // cs setup/hold period
8'h1 }); // cs bit information
tb_top.cpu_read('h2,'h0,read_data);
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
 
$display("%t : %m : Sending Sector Errase for Address : %x",$time,address);
 
tb_top.cpu_read('h2,'h0,read_data);
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
while(read_data[31]) begin
@(posedge tb_top.app_clk) ;
tb_top.cpu_read('h2,'h0,read_data);
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
end
end
endtask
208,10 → 208,10
task spi_op_over;
reg [31:0] read_data;
begin
tb_top.cpu_read('h2,'h0,read_data);
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
while(read_data[31]) begin
@(posedge tb_top.app_clk) ;
tb_top.cpu_read('h2,'h0,read_data);
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
end
#100;
end
230,8 → 230,8
exit_flag = 1;
while(exit_flag == 1) begin
 
tb_top.cpu_write('h2,'h4,{8'h05,24'h0});
tb_top.cpu_write('h2,'h0,{1'b1,6'h0,
tb_top.cpu_write(`ADDR_SPACE_SPI,'h4,{8'h05,24'h0});
tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,6'h0,
spi_chip_no[1:0],
2'b0, // Write Operation
2'b0, // 1 Transfer
240,16 → 240,16
8'h0 }); // cs bit information
 
 
tb_top.cpu_read('h2,'h0,read_data);
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
while(read_data[31]) begin
@(posedge tb_top.app_clk) ;
tb_top.cpu_read('h2,'h0,read_data);
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
end
 
// Send Status Request Cmd
 
 
tb_top.cpu_write('h2,'h0,{1'b1,6'h0,
tb_top.cpu_write(`ADDR_SPACE_SPI,'h0,{1'b1,6'h0,
spi_chip_no[1:0],
2'b1, // Read Operation
2'b0, // 1 Transfer
258,13 → 258,13
8'h40 }); // cs bit information
 
tb_top.cpu_read('h2,'h0,read_data);
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
while(read_data[31]) begin
@(posedge tb_top.app_clk) ;
tb_top.cpu_read('h2,'h0,read_data);
tb_top.cpu_read(`ADDR_SPACE_SPI,'h0,read_data);
end
tb_top.cpu_read('h2,'h8,read_data);
tb_top.cpu_read(`ADDR_SPACE_SPI,'h8,read_data);
exit_flag = read_data[24];
$display("Total time Elapsed: %0t(us): %m : Checking the SPI RDStatus : %x",($time - pretime)/1000000 ,read_data);
repeat (1000) @ (posedge tb_top.app_clk) ;
/verif/defs/tb_defines.v
23,15 → 23,12
 
//--------------------------------------------------------------
// Target ID Mapping
// 4'b0100 -- MAC core
// 4'b0011 -- UART
// 4'b0010 -- SPI core
// 4'b0001 -- External RAM
// 4'b0000 -- External ROM
// 4'b0010 -- UART
// 4'b0001 -- SPI core
// 4'b0000 -- External RAM
//--------------------------------------------------------------
`define ADDR_SPACE_MAC 4'b0100
`define ADDR_SPACE_UART 4'b0011
`define ADDR_SPACE_SPI 4'b0010
`define ADDR_SPACE_RAM 4'b0001
`define ADDR_SPACE_ROM 4'b0000
`define ADDR_SPACE_UART 4'b0010
`define ADDR_SPACE_SPI 4'b0001
`define ADDR_SPACE_RAM 4'b0000
//`define ADDR_SPACE_ROM 4'b0000
 
/verif/run/dat/oc8051_xrom.in
1,257 → 1,135
02
00
08
12
00
64
80
FE
75
81
07
12
00
E3
E5
82
60
03
02
00
03
79
00
E9
44
00
60
1B
7A
00
90
00
E7
78
00
75
A0
08
E4
93
F2
A3
08
B8
00
02
05
A0
D9
F4
DA
F2
75
A0
FF
E4
78
FF
F6
D8
FD
78
00
E8
44
00
60
0A
79
00
75
A0
00
E4
F3
09
D8
FC
78
00
E8
44
08
60
0C
79
08
90
00
00
E4
F0
A3
D8
FC
D9
FA
02
00
03
90
00
00
74
01
F0
7A
01
7B
00
74
F8
2B
40
2A
EA
24
00
FC
EB
34
00
FD
EA
24
FF
FE
EB
34
FF
FF
EE
24
00
F5
82
EF
34
00
F5
83
E0
FE
0E
8C
82
8D
83
EE
F0
0A
BA
00
D4
0B
80
D1
7A
00
7B
00
7C
00
74
F8
2C
40
29
EB
24
00
F5
82
EC
34
00
F5
83
E0
FD
74
01
2B
FE
E4
3C
E4
FF
F8
ED
B5
06
06
E8
B5
07
02
80
03
0A
8A
80
0B
BB
00
D5
0C
80
D2
EA
60
07
75
A0
55
8A
B0
80
06
75
A0
AA
75
B0
AA
80
FE
75
82
00
22
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
02
00
08
12
00
64
80
FE
75
81
0C
12
00
83
E5
82
60
03
02
00
03
79
00
E9
44
00
60
1B
7A
00
90
00
87
78
00
75
A0
00
E4
93
F2
A3
08
B8
00
02
05
A0
D9
F4
DA
F2
75
A0
FF
E4
78
FF
F6
D8
FD
78
00
E8
44
00
60
0A
79
00
75
A0
00
E4
F3
09
D8
FC
78
00
E8
44
00
60
0C
79
00
90
00
00
E4
F0
A3
D8
FC
D9
FA
02
00
03
90
90
00
74
07
F0
90
90
08
E4
F0
E4
90
90
0C
E0
FA
20
E1
F8
90
90
14
E0
FA
90
90
10
F0
80
ED
75
82
00
22
/verif/run/compile.modelsim
4,7 → 4,8
vlib work
endif
 
vlog -work work +define+SFLASH_SPDUP \
vlog -work work
+define+SFLASH_SPDUP \
-sv \
+incdir+../defs \
+incdir+../../rtl/defs \
/verif/run/filelist_rtl.f
46,4 → 46,6
../../rtl/8051/oc8051_tc.v \
../../rtl/8051/oc8051_tc2.v \
../../rtl/8051/oc8051_sfr.v \
../../rtl/8051/oc8051_ram_256x8_two_bist.v
../../rtl/8051/oc8051_ram_256x8_two_bist.v \
../../rtl/model/oc8051_xram.v \
../../rtl/model/oc8051_xrom.v
/verif/run/filelist_tb.f
18,6 → 18,4
../../verif/agents/spi/st_m25p20a/acdc_check.v \
../../verif/agents/spi/st_m25p20a/internal_logic.v \
../../verif/agents/spi/st_m25p20a/memory_access.v \
../../verif/agents/spi/st_m25p20a/M25P20.v \
../../verif/model/oc8051_xram.v \
../../verif/model/oc8051_xrom.v
../../verif/agents/spi/st_m25p20a/M25P20.v
/verif/run/run_modelsim
1,6 → 1,6
#!/bin/csh -f
#
# test all programs with ethernet controler
# test all programs with oms8051
#
 
set failedm = 0;
/verif/run/run_win.bat
0,0 → 1,5
vlib work
vlog -f filelist.f -l ../log/compile.log
copy ..\testcase\dat\uart_lb.dat dat\oc8051_xrom.in /Y
vsim -do run.do -c tb_top +uart_test_1 +INTERNAL_ROM -l ../log/uart_test_1.log
vsim -do run.do -c tb_top +spi_test_1 +INTERNAL_ROM -l ../log/spi_test_1.log
/verif/tb/tb_tasks.v
3,18 → 3,16
begin
reg_cs = 0;
reg_be = 4'h0;
reg_id = 0;
end
 
task cpu_read;
input [2:0] block_id;
input [3:0] block_id;
input [15:0] address;
output [31:0] read_data;
begin
@(posedge app_clk);
if(block_id == 1) reg_id = `ADDR_SPACE_MAC;
if(block_id == 2) reg_id = `ADDR_SPACE_SPI;
if(block_id == 3) reg_id = `ADDR_SPACE_UART;
if(block_id == 4) reg_id = `ADDR_SPACE_RAM;
reg_id = block_id;
reg_cs = 1;
reg_wr = 0;
reg_be = 4'hF;
28,15 → 26,13
endtask
 
task cpu_write;
input [2:0] block_id; // 1/2/3 --> mac/spi/uart
input [3:0] block_id; // 0/1/2 --> ram/spi/uart
input [15:0] address;
input [31:0] write_data;
begin
$display ("Config-Write: Id: %h Addr = %h, Cfg. Data = %h", block_id,address, write_data);
@(posedge app_clk);
if(block_id == 1) reg_id = `ADDR_SPACE_MAC;
if(block_id == 2) reg_id = `ADDR_SPACE_SPI;
if(block_id == 3) reg_id = `ADDR_SPACE_UART;
reg_id = block_id;
reg_cs = 1;
reg_wr = 1;
reg_be = 4'hF;
/verif/tb/tb_top.v
168,6 → 168,7
. xtal_clk (xtal_clk ),
. clkout (app_clk ),
. reset_out_n (reset_out_n ),
. ea_in (ea_in ), // internal ROM
 
// Reg Bus Interface Signal
. ext_reg_cs (reg_cs ),
191,69 → 192,12
.spi_sck (spi_sck ),
.spi_so (spi_so ),
.spi_si (spi_si ),
.spi_cs_n (spi_cs_n ),
.spi_cs_n (spi_cs_n )
 
// External ROM interface
.wb_xrom_adr (wb_xrom_adr ),
.wb_xrom_ack (wb_xrom_ack ),
.wb_xrom_err (wb_xrom_err ),
.wb_xrom_wr (wb_xrom_wr ),
.wb_xrom_rdata (wb_xrom_rdata ),
.wb_xrom_wdata (wb_xrom_wdata ),
.wb_xrom_stb (wb_xrom_stb ),
.wb_xrom_cyc (wb_xrom_cyc ),
 
// External RAM interface
.wb_xram_adr (wb_xram_adr ),
.wb_xram_ack (wb_xram_ack ),
.wb_xram_err (wb_xram_err ),
.wb_xram_wr (wb_xram_wr ),
.wb_xram_be (wb_xram_be ),
.wb_xram_rdata (wb_xram_rdata ),
.wb_xram_wdata (wb_xram_wdata ),
.wb_xram_stb (wb_xram_stb ),
.wb_xram_cyc (wb_xram_cyc ),
 
.ea_in (ea_in ) // internal ROM
 
);
 
 
oc8051_xrom oc8051_xrom1
(
.rst ( !reset_n ),
.clk ( app_clk ),
.addr ( wb_xrom_adr ),
.data ( wb_xrom_rdata ),
.stb_i ( wb_xrom_stb ),
.cyc_i ( wb_xrom_cyc ),
.ack_o ( wb_xrom_ack )
);
 
defparam oc8051_xrom1.DELAY = 0;
 
 
//
// external data ram
//
oc8051_xram oc8051_xram1 (
.clk (app_clk ),
.rst (!reset_n ),
.wr (wb_xram_wr ),
.be (wb_xram_be ),
.addr (wb_xram_adr ),
.data_in (wb_xram_wdata ),
.data_out (wb_xram_rdata ),
.ack (wb_xram_ack ),
.stb (wb_xram_stb )
);
 
 
defparam oc8051_xram1.DELAY = 2;
 
 
uart_agent tb_uart (
. test_clk (uart_clk_16x ),
. sin (si ),
/verif/testcase/uart_test1.v
26,7 → 26,7
fifo_enable = 0; // fifo mode disable
 
tb_uart.uart_init;
tb_top.cpu_write('h3,8'h0,{27'h0,2'b00,1'b1,1'b1,1'b1});
tb_top.cpu_write(`ADDR_SPACE_UART,8'h0,{27'h0,2'b00,1'b1,1'b1,1'b1});
for (i=0; i<40; i=i+1)

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