URL
https://opencores.org/ocsvn/opb_usblite/opb_usblite/trunk
Subversion Repositories opb_usblite
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- This comparison shows the changes necessary to convert path
/opb_usblite
- from Rev 7 to Rev 8
- ↔ Reverse comparison
Rev 7 → Rev 8
/trunk/refdesign/system.xmp
2,6 → 2,7
XmpVersion: 11.4 |
VerMgmt: 11.4 |
IntStyle: default |
ModuleSearchPath: ../../ |
MHS File: system.mhs |
MSS File: system.mss |
Architecture: spartan3e |
27,3 → 28,21
Processor: microblaze_0 |
BootLoop: 1 |
XmdStub: 0 |
SwProj: helloworld |
Processor: microblaze_0 |
Executable: helloworld/executable.elf |
Source: helloworld.c |
DefaultInit: EXECUTABLE |
InitBram: 0 |
Active: 1 |
CompilerOptLevel: 2 |
GlobPtrOpt: 0 |
DebugSym: 1 |
ProfileFlag: 0 |
ProgStart: 0x44000000 |
StackSize: 0x1000 |
HeapSize: 0x1000 |
LinkerScript: |
ProgCCFlags: |
CompileInXps: 1 |
NonXpsApp: 0 |
/trunk/refdesign/data/system.ucf
0,0 → 1,537
# Spartan-3E Starter Board |
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<0> LOC=F9 | IOSTANDARD = LVCMOS33; |
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<1> LOC=E9 | IOSTANDARD = LVCMOS33; |
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<2> LOC=D11 | IOSTANDARD = LVCMOS33; |
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<3> LOC=C11 | IOSTANDARD = LVCMOS33; |
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<4> LOC=F11 | IOSTANDARD = LVCMOS33; |
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<5> LOC=E11 | IOSTANDARD = LVCMOS33; |
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<6> LOC=E12 | IOSTANDARD = LVCMOS33; |
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<7> LOC=F12 | IOSTANDARD = LVCMOS33; |
Net fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin<0> LOC=N17 | PULLDOWN | IOSTANDARD = LVCMOS33; |
Net fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin<1> LOC=H18 | PULLDOWN | IOSTANDARD = LVCMOS33; |
Net fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin<2> LOC=L14 | PULLDOWN | IOSTANDARD = LVCMOS33; |
Net fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin<3> LOC=L13 | PULLDOWN | IOSTANDARD = LVCMOS33; |
Net fpga_0_Buttons_4Bit_GPIO_IO_I_pin<0> LOC=D18 | PULLDOWN | IOSTANDARD = LVCMOS33; |
Net fpga_0_Buttons_4Bit_GPIO_IO_I_pin<1> LOC=H13 | PULLDOWN | IOSTANDARD = LVCMOS33; |
Net fpga_0_Buttons_4Bit_GPIO_IO_I_pin<2> LOC=V4 | PULLDOWN | IOSTANDARD = LVCMOS33; |
Net fpga_0_Buttons_4Bit_GPIO_IO_I_pin<3> LOC=V16 | PULLDOWN | IOSTANDARD = LVCMOS33; |
Net fpga_0_DDR_SDRAM_DDR_Clk_pin LOC=J5 | IOSTANDARD = DIFF_SSTL2_I; |
Net fpga_0_DDR_SDRAM_DDR_Clk_n_pin LOC=J4 | IOSTANDARD = DIFF_SSTL2_I; |
Net fpga_0_DDR_SDRAM_DDR_CE_pin LOC=K3 | IOSTANDARD = SSTL2_I; |
Net fpga_0_DDR_SDRAM_DDR_CS_n_pin LOC=K4 | IOSTANDARD = SSTL2_I; |
Net fpga_0_DDR_SDRAM_DDR_RAS_n_pin LOC=C1 | IOSTANDARD = SSTL2_I; |
Net fpga_0_DDR_SDRAM_DDR_CAS_n_pin LOC=C2 | IOSTANDARD = SSTL2_I; |
Net fpga_0_DDR_SDRAM_DDR_WE_n_pin LOC=D1 | IOSTANDARD = SSTL2_I; |
Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<0> LOC=K5 | IOSTANDARD = SSTL2_I; |
Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<1> LOC=K6 | IOSTANDARD = SSTL2_I; |
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<0> LOC=T1 | IOSTANDARD = SSTL2_I; |
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<1> LOC=R3 | IOSTANDARD = SSTL2_I; |
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<2> LOC=R2 | IOSTANDARD = SSTL2_I; |
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<3> LOC=P1 | IOSTANDARD = SSTL2_I; |
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<4> LOC=F4 | IOSTANDARD = SSTL2_I; |
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<5> LOC=H4 | IOSTANDARD = SSTL2_I; |
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<6> LOC=H3 | IOSTANDARD = SSTL2_I; |
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<7> LOC=H1 | IOSTANDARD = SSTL2_I; |
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<8> LOC=H2 | IOSTANDARD = SSTL2_I; |
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<9> LOC=N4 | IOSTANDARD = SSTL2_I; |
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<10> LOC=T2 | IOSTANDARD = SSTL2_I; |
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<11> LOC=N5 | IOSTANDARD = SSTL2_I; |
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<12> LOC=P2 | IOSTANDARD = SSTL2_I; |
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<0> LOC=L2 | IOSTANDARD = SSTL2_I | PULLUP; |
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<1> LOC=L1 | IOSTANDARD = SSTL2_I | PULLUP; |
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<2> LOC=L3 | IOSTANDARD = SSTL2_I | PULLUP; |
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<3> LOC=L4 | IOSTANDARD = SSTL2_I | PULLUP; |
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<4> LOC=M3 | IOSTANDARD = SSTL2_I | PULLUP; |
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<5> LOC=M4 | IOSTANDARD = SSTL2_I | PULLUP; |
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<6> LOC=M5 | IOSTANDARD = SSTL2_I | PULLUP; |
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<7> LOC=M6 | IOSTANDARD = SSTL2_I | PULLUP; |
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<8> LOC=E2 | IOSTANDARD = SSTL2_I | PULLUP; |
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<9> LOC=E1 | IOSTANDARD = SSTL2_I | PULLUP; |
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<10> LOC=F1 | IOSTANDARD = SSTL2_I | PULLUP; |
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<11> LOC=F2 | IOSTANDARD = SSTL2_I | PULLUP; |
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<12> LOC=G6 | IOSTANDARD = SSTL2_I | PULLUP; |
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<13> LOC=G5 | IOSTANDARD = SSTL2_I | PULLUP; |
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<14> LOC=H6 | IOSTANDARD = SSTL2_I | PULLUP; |
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<15> LOC=H5 | IOSTANDARD = SSTL2_I | PULLUP; |
Net fpga_0_DDR_SDRAM_DDR_DM_pin<0> LOC=J2 | IOSTANDARD = SSTL2_I; |
Net fpga_0_DDR_SDRAM_DDR_DM_pin<1> LOC=J1 | IOSTANDARD = SSTL2_I; |
Net fpga_0_DDR_SDRAM_DDR_DQS_pin<0> LOC=L6 | IOSTANDARD = SSTL2_I; |
Net fpga_0_DDR_SDRAM_DDR_DQS_pin<1> LOC=G3 | IOSTANDARD = SSTL2_I | PULLUP; |
Net fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin LOC=P13 | IOSTANDARD = LVCMOS33; |
Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin; |
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 50000 kHz; |
Net fpga_0_clk_1_sys_clk_pin LOC=c9 | IOSTANDARD = LVCMOS33; |
Net fpga_0_rst_1_sys_rst_pin TIG; |
Net fpga_0_rst_1_sys_rst_pin LOC=K17 | IOSTANDARD = LVCMOS33 | PULLDOWN; |
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NET opb_usblite_0_txdoe_pin LOC=B4 | IOSTANDARD = LVCMOS33; |
NET opb_usblite_0_rxd_pin LOC=A4 | IOSTANDARD = LVCMOS33; |
NET opb_usblite_0_rxdp_pin LOC=D5 | IOSTANDARD = LVCMOS33; |
NET opb_usblite_0_rxdn_pin LOC=C5 | IOSTANDARD = LVCMOS33; |
NET opb_usblite_0_txdp_pin LOC=A6 | IOSTANDARD = LVCMOS33; |
NET opb_usblite_0_txdn_pin LOC=B6 | IOSTANDARD = LVCMOS33; |
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###### DDR_SDRAM |
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############################################################################ |
# Placement constraints for luts in tap delay ckt |
############################################################################ |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0" RLOC=X0Y6; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l1" RLOC=X0Y6; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l1" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l2" RLOC=X0Y7; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l2" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l3" RLOC=X0Y7; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l3" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l4" RLOC=X1Y6; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l4" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l5" RLOC=X1Y6; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l5" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l6" RLOC=X1Y7; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l6" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l7" RLOC=X1Y7; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l7" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l8" RLOC=X0Y4; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l8" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l9" RLOC=X0Y4; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l9" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l10" RLOC=X0Y5; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l10" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l11" RLOC=X0Y5; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l11" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l12" RLOC=X1Y4; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l12" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l13" RLOC=X1Y4; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l13" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l14" RLOC=X1Y5; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l14" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l15" RLOC=X1Y5; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l15" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l16" RLOC=X0Y2; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l16" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l17" RLOC=X0Y2; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l17" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l18" RLOC=X0Y3; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l18" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l19" RLOC=X0Y3; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l19" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l20" RLOC=X1Y2; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l20" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l21" RLOC=X1Y2; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l21" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l22" RLOC=X1Y3; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l22" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l23" RLOC=X1Y3; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l23" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l24" RLOC=X0Y0; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l24" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l25" RLOC=X0Y0; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l25" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l26" RLOC=X0Y1; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l26" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l27" RLOC=X0Y1; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l27" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l28" RLOC=X1Y0; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l28" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l29" RLOC=X1Y0; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l29" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l30" RLOC=X1Y1; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l30" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l31" RLOC=X1Y1; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l31" U_SET = "tap_dly0_u_set"; |
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####################################################################################################################### |
# Placement constraints for first stage flops in tap delay ckt # |
####################################################################################################################### |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[0].r" RLOC=X0Y6; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[0].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[1].r" RLOC=X0Y6; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[1].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[2].r" RLOC=X0Y7; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[2].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[3].r" RLOC=X0Y7; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[3].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[4].r" RLOC=X1Y6; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[4].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[5].r" RLOC=X1Y6; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[5].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[6].r" RLOC=X1Y7; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[6].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[7].r" RLOC=X1Y7; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[7].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[8].r" RLOC=X0Y4; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[8].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[9].r" RLOC=X0Y4; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[9].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[10].r" RLOC=X0Y5; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[10].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[11].r" RLOC=X0Y5; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[11].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[12].r" RLOC=X1Y4; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[12].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[13].r" RLOC=X1Y4; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[13].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[14].r" RLOC=X1Y5; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[14].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[15].r" RLOC=X1Y5; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[15].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[16].r" RLOC=X0Y2; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[16].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[17].r" RLOC=X0Y2; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[17].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[18].r" RLOC=X0Y3; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[18].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[19].r" RLOC=X0Y3; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[19].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[20].r" RLOC=X1Y2; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[20].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[21].r" RLOC=X1Y2; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[21].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[22].r" RLOC=X1Y3; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[22].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[23].r" RLOC=X1Y3; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[23].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[24].r" RLOC=X0Y0; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[24].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[25].r" RLOC=X0Y0; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[25].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[26].r" RLOC=X0Y1; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[26].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[27].r" RLOC=X0Y1; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[27].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[28].r" RLOC=X1Y0; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[28].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[29].r" RLOC=X1Y0; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[29].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[30].r" RLOC=X1Y1; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[30].r" U_SET = "tap_dly0_u_set"; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[31].r" RLOC=X1Y1; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[31].r" U_SET = "tap_dly0_u_set"; |
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####################################################################################################################### |
# BEL constraints for luts in tap delay ckt # |
####################################################################################################################### |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0" BEL= G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l1" BEL= F; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l2" BEL= G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l3" BEL= F; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l4" BEL= G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l5" BEL= F; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l6" BEL= G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l7" BEL= F; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l8" BEL= G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l9" BEL= F; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l10" BEL= G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l11" BEL= F; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l12" BEL= G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l13" BEL= F; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l14" BEL= G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l15" BEL= F; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l16" BEL= G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l17" BEL= F; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l18" BEL= G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l19" BEL= F; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l20" BEL= G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l21" BEL= F; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l22" BEL= G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l23" BEL= F; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l24" BEL= G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l25" BEL= F; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l26" BEL= G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l27" BEL= F; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l28" BEL= G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l29" BEL= F; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l30" BEL= G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l31" BEL= F; |
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############################################################################## |
# Delay constraints |
############################################################################## |
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###### maxdelay of 400 ps will not be met. This constraint is just to get a better delay#### |
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/tap[7]" MAXDELAY = 400ps; |
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/tap[15]" MAXDELAY = 400ps; |
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/tap[23]" MAXDELAY = 400ps; |
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###### maxdelay of 460 ps will not be met. This constraint is just to get a better delay#### |
###### The reported delay will be in the range of 500 to 600 ps#### |
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/dqs_int_delay_in*" MAXDELAY = 480ps; |
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###### maxdelay of 160 ps will not be met. This constraint is just to get a better delay#### |
###### The reported delay will be in the range of 200 to 360 ps#### |
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[*]*u_dqs_delay_col*/delay*" MAXDELAY = 200ps; |
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################################################################################################### |
######constraint to place flop1 and flop2 close togather for the calibration logic ############### |
################################################################################################### |
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/flop1[*]" MAXDELAY = 3000ps; |
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NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/dqs_delayed_col*<*>" MAXDELAY = 1000ps; |
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/rst_dqs_div" MAXDELAY = 2500ps; |
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed*" MAXDELAY = 2000ps; |
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/fifo*_wr_en<*>" MAXDELAY = 2000ps; |
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/fifo_*_wr_addr_out<*><*>" MAXDELAY = 2000ps; |
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/fifo_*_data_out[*]" MAXDELAY = 2000ps; |
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/dq<*>" MAXDELAY = 480ps; |
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####################################################################################################################### |
# Area Group Constraint For tap_dly and cal_ctl module # |
####################################################################################################################### |
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#INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/cal_ctl/*" AREA_GROUP = cal_ctl; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/*" AREA_GROUP = cal_ctl; |
#AREA_GROUP "cal_ctl" RANGE = SLICE_X0Y10:SLICE_X15Y23; // Old values |
AREA_GROUP "cal_ctl" RANGE = SLICE_X28Y70:SLICE_X39Y83; |
AREA_GROUP "cal_ctl" GROUP = CLOSED; |
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############################################################################## |
# IOB and AREA constraints |
############################################################################## |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/datapath_iobs/gen_dqs[*].dqs_iob*" IOB = TRUE; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/datapath_iobs/gen_dq[*].dq_iob*" IOB = TRUE; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/gen_addr[*].addr_iob" IOB = TRUE; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/gen_ba[*].ba_iob" IOB = TRUE; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/gen_cke[*].cke_iob" IOB = TRUE; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/ras_iob" IOB = TRUE; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/cas_iob" IOB = TRUE; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/we_iob" IOB = TRUE; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/dqs_div/dqs_rst_iob" IOB = TRUE; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[1]*u_fifo_bit" LOC = SLICE_X2Y36; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[1]*u_fifo_bit" LOC = SLICE_X2Y37; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[0]*u_fifo_bit" LOC = SLICE_X0Y36; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[0]*u_fifo_bit" LOC = SLICE_X0Y37; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[2]*u_fifo_bit" LOC = SLICE_X2Y32; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[2]*u_fifo_bit" LOC = SLICE_X2Y33; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[3]*u_fifo_bit" LOC = SLICE_X0Y32; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[3]*u_fifo_bit" LOC = SLICE_X0Y33; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[5]*u_fifo_bit" LOC = SLICE_X2Y24; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[5]*u_fifo_bit" LOC = SLICE_X2Y25; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[4]*u_fifo_bit" LOC = SLICE_X0Y24; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[4]*u_fifo_bit" LOC = SLICE_X0Y25; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[7]*u_fifo_bit" LOC = SLICE_X0Y20; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[7]*u_fifo_bit" LOC = SLICE_X0Y21; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[6]*u_fifo_bit" LOC = SLICE_X2Y20; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[6]*u_fifo_bit" LOC = SLICE_X2Y21; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[1]*u_fifo_bit" LOC = SLICE_X0Y82; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[1]*u_fifo_bit" LOC = SLICE_X0Y83; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[0]*u_fifo_bit" LOC = SLICE_X2Y82; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[0]*u_fifo_bit" LOC = SLICE_X2Y83; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[3]*u_fifo_bit" LOC = SLICE_X0Y76; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[3]*u_fifo_bit" LOC = SLICE_X0Y77; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[2]*u_fifo_bit" LOC = SLICE_X2Y76; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[2]*u_fifo_bit" LOC = SLICE_X2Y77; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[5]*u_fifo_bit" LOC = SLICE_X0Y68; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[5]*u_fifo_bit" LOC = SLICE_X0Y69; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[4]*u_fifo_bit" LOC = SLICE_X2Y68; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[4]*u_fifo_bit" LOC = SLICE_X2Y69; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[7]*u_fifo_bit" LOC = SLICE_X0Y64; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[7]*u_fifo_bit" LOC = SLICE_X0Y65; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[6]*u_fifo_bit" LOC = SLICE_X2Y64; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[6]*u_fifo_bit" LOC = SLICE_X2Y65; |
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############################################################# |
## DQS 0 Col 0 |
############################################################# |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.one" LOC = SLICE_X2Y29; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.one" BEL = F; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.two" LOC = SLICE_X2Y29; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.two" BEL = G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.three" LOC = SLICE_X2Y28; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.three" BEL = G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.four" LOC = SLICE_X2Y28; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.four" BEL = F; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.five" LOC = SLICE_X3Y29; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.five" BEL = G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.six" LOC = SLICE_X3Y28; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.six" BEL = G; |
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############################################################# |
## DQS 0 Col 1 |
############################################################# |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.one" LOC = SLICE_X0Y29; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.one" BEL = F; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.two" LOC = SLICE_X0Y29; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.two" BEL = G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.three" LOC = SLICE_X0Y28; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.three" BEL = G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.four" LOC = SLICE_X0Y28; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.four" BEL = F; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.five" LOC = SLICE_X1Y29; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.five" BEL = G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.six" LOC = SLICE_X1Y28; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.six" BEL = G; |
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############################################################# |
## DQS 1 Col 0 |
############################################################# |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.one" LOC = SLICE_X2Y73; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.one" BEL = F; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.two" LOC = SLICE_X2Y73; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.two" BEL = G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.three" LOC = SLICE_X2Y72; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.three" BEL = G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.four" LOC = SLICE_X2Y72; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.four" BEL = F; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.five" LOC = SLICE_X3Y73; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.five" BEL = G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.six" LOC = SLICE_X3Y72; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.six" BEL = G; |
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############################################################# |
## DQS 1 Col 1 |
############################################################# |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.one" LOC = SLICE_X0Y73; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.one" BEL = F; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.two" LOC = SLICE_X0Y73; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.two" BEL = G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.three" LOC = SLICE_X0Y72; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.three" BEL = G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.four" LOC = SLICE_X0Y72; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.four" BEL = F; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.five" LOC = SLICE_X1Y73; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.five" BEL = G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.six" LOC = SLICE_X1Y72; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.six" BEL = G; |
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############################################################# |
## WR ADDR 0 |
############################################################# |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_0_wr_addr/gen_addr[0].u_addr_bit" LOC = SLICE_X1Y30; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_0_wr_addr/gen_addr[1].u_addr_bit" LOC = SLICE_X1Y30; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_0_wr_addr/gen_addr[2].u_addr_bit" LOC = SLICE_X1Y31; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_0_wr_addr/gen_addr[3].u_addr_bit" LOC = SLICE_X1Y31; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_1_wr_addr/gen_addr[0].u_addr_bit" LOC = SLICE_X3Y30; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_1_wr_addr/gen_addr[1].u_addr_bit" LOC = SLICE_X3Y30; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_1_wr_addr/gen_addr[2].u_addr_bit" LOC = SLICE_X3Y31; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_1_wr_addr/gen_addr[3].u_addr_bit" LOC = SLICE_X3Y31; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[0].u_fifo_0_wr_en/*" LOC = SLICE_X1Y33; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[0].u_fifo_1_wr_en/*" LOC = SLICE_X3Y33; |
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############################################################# |
## WR ADDR 1 |
############################################################# |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_0_wr_addr/gen_addr[0].u_addr_bit" LOC = SLICE_X1Y74; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_0_wr_addr/gen_addr[1].u_addr_bit" LOC = SLICE_X1Y74; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_0_wr_addr/gen_addr[2].u_addr_bit" LOC = SLICE_X1Y75; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_0_wr_addr/gen_addr[3].u_addr_bit" LOC = SLICE_X1Y75; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_1_wr_addr/gen_addr[0].u_addr_bit" LOC = SLICE_X3Y74; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_1_wr_addr/gen_addr[1].u_addr_bit" LOC = SLICE_X3Y74; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_1_wr_addr/gen_addr[2].u_addr_bit" LOC = SLICE_X3Y75; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_1_wr_addr/gen_addr[3].u_addr_bit" LOC = SLICE_X3Y75; |
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INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[1].u_fifo_0_wr_en/*" LOC = SLICE_X1Y77; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[1].u_fifo_1_wr_en/*" LOC = SLICE_X3Y77; |
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############################################################# |
## DQS Loopback |
############################################################# |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.one" LOC = SLICE_X0Y9; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.one" BEL = F; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.two" LOC = SLICE_X0Y8; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.two" BEL = F; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.three" LOC = SLICE_X0Y9; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.three" BEL = G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.four" LOC = SLICE_X1Y8; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.four" BEL = F; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.five" LOC = SLICE_X1Y8; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.five" BEL = G; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.six" LOC = SLICE_X1Y9; |
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.six" BEL = G; |
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/trunk/refdesign/etc/bitgen.ut
0,0 → 1,15
-g CclkPin:PULLUP |
-g TdoPin:PULLNONE |
-g M1Pin:PULLDOWN |
-g DonePin:PULLUP |
-g StartUpClk:JTAGCLK |
-g M0Pin:PULLUP |
-g M2Pin:PULLUP |
-g ProgPin:PULLUP |
-g TckPin:PULLUP |
-g TdiPin:PULLUP |
-g TmsPin:PULLUP |
-g LCK_cycle:NoWait |
-g Security:NONE |
#-m |
-g Persist:No |
/trunk/refdesign/etc/fast_runtime.opt
0,0 → 1,83
FLOWTYPE = FPGA; |
############################################################### |
## Filename: fast_runtime.opt |
## |
## Option File For Xilinx FPGA Implementation Flow for Fast |
## Runtime. |
## |
## Version: 4.1.1 |
############################################################### |
# |
# Options for Translator |
# |
# Type "ngdbuild -h" for a detailed list of ngdbuild command line options |
# |
Program ngdbuild |
-p <partname>; # Partname to use - picked from xflow commandline |
-nt timestamp; # NGO File generation. Regenerate only when |
# source netlist is newer than existing |
# NGO file (default) |
-bm <design>.bmm # Block RAM memory map file |
<userdesign>; # User design - pick from xflow command line |
-uc <design>.ucf; # ucf constraints |
<design>.ngd; # Name of NGD file. Filebase same as design filebase |
End Program ngdbuild |
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# |
# Options for Mapper |
# |
# Type "map -h <arch>" for a detailed list of map command line options |
# |
Program map |
-o <design>_map.ncd; # Output Mapped ncd file |
-pr b; # Pack internal FF/latches into IOBs |
#-fp <design>.mfp; # Floorplan file |
-ol high; |
-timing; |
-detail; |
<inputdir><design>.ngd; # Input NGD file |
<inputdir><design>.pcf; # Physical constraints file |
END Program map |
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# |
# Options for Post Map Trace |
# |
# Type "trce -h" for a detailed list of trce command line options |
# |
Program post_map_trce |
-e 3; # Produce error report limited to 3 items per constraint |
#-o <design>_map.twr; # Output trace report file |
-xml <design>_map.twx; # Output XML version of the timing report |
#-tsi <design>_map.tsi; # Produce Timing Specification Interaction report |
<inputdir><design>_map.ncd; # Input mapped ncd |
<inputdir><design>.pcf; # Physical constraints file |
END Program post_map_trce |
|
# |
# Options for Place and Route |
# |
# Type "par -h" for a detailed list of par command line options |
# |
Program par |
-w; # Overwrite existing placed and routed ncd |
-ol high; # Overall effort level |
<inputdir><design>_map.ncd; # Input mapped NCD file |
<design>.ncd; # Output placed and routed NCD |
<inputdir><design>.pcf; # Input physical constraints file |
END Program par |
|
# |
# Options for Post Par Trace |
# |
# Type "trce -h" for a detailed list of trce command line options |
# |
Program post_par_trce |
-e 3; # Produce error report limited to 3 items per constraint |
#-o <design>.twr; # Output trace report file |
-xml <design>.twx; # Output XML version of the timing report |
#-tsi <design>.tsi; # Produce Timing Specification Interaction report |
<inputdir><design>.ncd; # Input placed and routed ncd |
<inputdir><design>.pcf; # Physical constraints file |
END Program post_par_trce |
|
|
/trunk/refdesign/etc/download.cmd
0,0 → 1,6
setMode -bscan |
setCable -p auto |
identify |
assignfile -p 1 -file implementation/download.bit |
program -p 1 |
quit |
/trunk/refdesign/helloworld.c
0,0 → 1,10
#include <stdio.h> |
|
main() |
{ |
do |
{ |
printf("Hello World\n\r"); |
} |
while(1); |
} |