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Subversion Repositories openrisc_2011-10-31

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    from Rev 642 to Rev 643
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Rev 642 → Rev 643

/trunk/or1200/rtl/verilog/or1200_defines.v
359,11 → 359,12
//
// Type of ALU compare to implement
//
// Try either one to find what yields
// higher clock frequencyin your case.
// Try to find which synthesizes with
// most efficient logic use or highest speed.
//
//`define OR1200_IMPL_ALU_COMP1
`define OR1200_IMPL_ALU_COMP2
//`define OR1200_IMPL_ALU_COMP2
`define OR1200_IMPL_ALU_COMP3
 
//
// Implement Find First/Last '1'
1658,7 → 1659,7
`define OR1200_DMMUCFGR_NAE 3'h0 // No ATB entries
`define OR1200_DMMUCFGR_CRI 1'b0 // No control register
`define OR1200_DMMUCFGR_PRI 1'b0 // No protection reg
`define OR1200_DMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl.
`define OR1200_DMMUCFGR_TEIRI 1'b0 // TLB entry inv reg NOT impl.
`define OR1200_DMMUCFGR_HTR 1'b0 // No HW TLB reload
`define OR1200_DMMUCFGR_RES1 20'h00000
`endif
1689,7 → 1690,7
`define OR1200_IMMUCFGR_NAE 3'h0 // No ATB entry
`define OR1200_IMMUCFGR_CRI 1'b0 // No control reg
`define OR1200_IMMUCFGR_PRI 1'b0 // No protection reg
`define OR1200_IMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl
`define OR1200_IMMUCFGR_TEIRI 1'b0 // TLB entry inv reg NOT impl
`define OR1200_IMMUCFGR_HTR 1'b0 // No HW TLB reload
`define OR1200_IMMUCFGR_RES1 20'h00000
`endif
/trunk/or1200/rtl/verilog/or1200_alu.v
100,10 → 100,8
reg ov_we;
wire [width-1:0] comp_a;
wire [width-1:0] comp_b;
`ifdef OR1200_IMPL_ALU_COMP1
wire a_eq_b;
wire a_lt_b;
`endif
wire [width-1:0] result_sum;
wire [width-1:0] result_and;
wire cy_sum;
120,6 → 118,7
//
// Combinatorial logic
//
 
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
`ifdef OR1200_IMPL_ALU_COMP1
126,9 → 125,26
assign a_eq_b = (comp_a == comp_b);
assign a_lt_b = (comp_a < comp_b);
`endif
`ifdef OR1200_IMPL_ALU_COMP3
assign a_eq_b = !(|result_sum);
// signed compare when comp_op[3] is set
assign a_lt_b = comp_op[3] ? ((a[width-1] & !b[width-1]) |
(!a[width-1] & !b[width-1] & result_sum[width-1])|
(a[width-1] & b[width-1] & result_sum[width-1])):
// a < b if (a - b) subtraction wrapped and a[width-1] wasn't set
(result_sum[width-1] & !a[width-1]) |
// or if (a - b) wrapped and both a[width-1] and b[width-1] were set
(result_sum[width-1] & a[width-1] & b[width-1] );
`endif
`ifdef OR1200_IMPL_SUB
`ifdef OR1200_IMPL_ALU_COMP3
assign cy_sub = a_lt_b;
`else
assign cy_sub = (comp_a < comp_b);
`endif
`endif
`ifdef OR1200_IMPL_ADDC
assign carry_in = (alu_op==`OR1200_ALUOP_ADDC) ?
{{width-1{1'b0}},carry} : {width{1'b0}};
135,11 → 151,21
`else
assign carry_in = {width-1{1'b0}};
`endif
 
`ifdef OR1200_IMPL_ALU_COMP3
`ifdef OR1200_IMPL_SUB
assign b_mux = ((alu_op==`OR1200_ALUOP_SUB) | (alu_op==`OR1200_ALUOP_COMP)) ?
(~b)+1 : b;
`else
assign b_mux = (alu_op==`OR1200_ALUOP_COMP) ? (~b)+1 : b;
`endif
`else // ! `ifdef OR1200_IMPL_ALU_COMP3
`ifdef OR1200_IMPL_SUB
assign b_mux = (alu_op==`OR1200_ALUOP_SUB) ? (~b)+1 : b;
`else
assign b_mux = b;
`endif
`endif
`endif
assign {cy_sum, result_sum} = (a + b_mux) + carry_in;
// Numbers either both +ve and bit 31 of result set
assign ov_sum = ((!a[width-1] & !b_mux[width-1]) & result_sum[width-1]) |
409,7 → 435,29
flagcomp = 1'b0;
endcase
end
`endif // `ifdef OR1200_IMPL_ALU_COMP2
 
`ifdef OR1200_IMPL_ALU_COMP3
always @(comp_op or a_eq_b or a_lt_b) begin
case(comp_op[2:0]) // synopsys parallel_case
`OR1200_COP_SFEQ:
flagcomp = a_eq_b;
`OR1200_COP_SFNE:
flagcomp = ~a_eq_b;
`OR1200_COP_SFGT:
flagcomp = ~(a_eq_b | a_lt_b);
`OR1200_COP_SFGE:
flagcomp = ~a_lt_b;
`OR1200_COP_SFLT:
flagcomp = a_lt_b;
`OR1200_COP_SFLE:
flagcomp = a_eq_b | a_lt_b;
default:
flagcomp = 1'b0;
endcase
end
`endif
 
`ifdef OR1200_IMPL_ALU_EXT
always @(alu_op or alu_op2 or a) begin
/trunk/or1200/rtl/verilog/or1200_rf.v
197,29 → 197,21
else if (~wb_freeze)
rf_we_allow <= ~flushpipe;
 
//assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow & (supv | (|rf_addrw));
assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow;
//assign cy_we_o = cy_we_i && rf_we;
 
assign cy_we_o = cy_we_i && ~wb_freeze && rf_we_allow;
//
// CS RF A asserted when instruction reads operand A and ID stage
// is not stalled
//
//assign rf_ena = rda & ~id_freeze | spr_valid; // probably works with fixed binutils
assign rf_ena = (rda & ~id_freeze) | (spr_valid & !spr_write) | spr_cs_fe; // probably works with fixed binutils
// assign rf_ena = 1'b1; // does not work with single-stepping
//assign rf_ena = ~id_freeze | spr_valid; // works with broken binutils
assign rf_ena = (rda & ~id_freeze) | (spr_valid & !spr_write) | spr_cs_fe;
 
//
// CS RF B asserted when instruction reads operand B and ID stage
// is not stalled
//
//assign rf_enb = rdb & ~id_freeze | spr_valid;
assign rf_enb = rdb & ~id_freeze;
// assign rf_enb = 1'b1;
//assign rf_enb = ~id_freeze | spr_valid; // works with broken binutils
 
`ifdef OR1200_RFRAM_TWOPORT
 
/trunk/or1200/rtl/verilog/or1200_mult_mac.v
250,12 → 250,16
`OR1200_ALUOP_MUL: begin
// Actually doing unsigned multiply internally, and then negate on
// output as appropriate, so if sign bit is set, then is overflow
ovforw = mul_prod_r[31];
// unless incoming signs differ and result is 2^(width-1)
ovforw = (mul_prod_r[width-1] &&
!((a[width-1]^b[width-1]) && ~|mul_prod_r[width-2:0])) ||
|mul_prod_r[2*width-1:32];
 
ov_we = 1;
end
`OR1200_ALUOP_MULU : begin
// Overflow on unsigned multiply is simpler.
ovforw = mul_prod_r[32];
ovforw = |mul_prod_r[2*width-1:32];
ov_we = 1;
end
`endif // `ifdef OR1200_MULT_IMPLEMENTED
262,8 → 266,8
`ifdef OR1200_DIV_IMPLEMENTED
`OR1200_ALUOP_DIVU,
`OR1200_ALUOP_DIV: begin
// Overflow on divide by zero
ovforw = div_by_zero;
// Overflow on divide by zero or -2^(width-1)/-1
ovforw = div_by_zero || (a==32'h8000_0000 && b==32'hffff_ffff);
ov_we = 1;
end
`endif

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