URL
https://opencores.org/ocsvn/pci/pci/trunk
Subversion Repositories pci
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- This comparison shows the changes necessary to convert path
/
- from Rev 136 to Rev 137
- ↔ Reverse comparison
Rev 136 → Rev 137
/trunk/bench/verilog/system.v
39,6 → 39,12
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.21 2003/12/19 11:11:28 mihad |
// Compact PCI Hot Swap support added. |
// New testcases added. |
// Specification updated. |
// Test application changed to support WB B3 cycles. |
// |
// Revision 1.20 2003/10/17 09:11:51 markom |
// mbist signals updated according to newest convention |
// |
12537,7 → 12543,7
reg error ; |
begin |
error = 1'b0 ; |
rnd_seed = 32'h01020_f0e0 ; |
rnd_seed = 32'h1020_f0e0 ; |
|
ES = 1'b0 ; |
|
/trunk/rtl/verilog/pci_conf_space.v
43,6 → 43,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2003/12/28 09:20:00 fr2201 |
// Reset values for PCI, WB defined (PCI_TAx,WB_BAx,WB_TAx,WB_AMx,WB_BAx_MEM_IO) |
// |
// Revision 1.4 2003/12/19 11:11:30 mihad |
// Compact PCI Hot Swap support added. |
// New testcases added. |
427,11 → 430,11
parameters except for def_wb_image0_addr_map which is used for configuration space! |
-----------------------------------------------------------------------------------------------------------*/ |
// PARAMETER def_wb_image0_addr_map IMPLEMENTED as r_wb_am0 parameter for CONF. space !!! |
wire [19:0] def_wb_image1_addr_map = 20'h0000_0 ; |
wire [19:0] def_wb_image2_addr_map = 20'h0000_0 ; |
wire [19:0] def_wb_image3_addr_map = 20'h0000_0 ; |
wire [19:0] def_wb_image4_addr_map = 20'h0000_0 ; |
wire [19:0] def_wb_image5_addr_map = 20'h0000_0 ; |
wire [19:0] def_wb_image1_addr_map = `WB_AM1 ; |
wire [19:0] def_wb_image2_addr_map = `WB_AM2 ; |
wire [19:0] def_wb_image3_addr_map = `WB_AM3 ; |
wire [19:0] def_wb_image4_addr_map = `WB_AM4 ; |
wire [19:0] def_wb_image5_addr_map = `WB_AM5 ; |
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|
/*########################################################################################################### |
/trunk/rtl/verilog/pci_user_constants.v
39,6 → 39,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.11 2003/12/28 09:20:00 fr2201 |
// Reset values for PCI, WB defined (PCI_TAx,WB_BAx,WB_TAx,WB_AMx,WB_BAx_MEM_IO) |
// |
// Revision 1.10 2003/12/19 11:11:30 mihad |
// Compact PCI Hot Swap support added. |
// New testcases added. |
209,11 → 212,11
`define WB_IMAGE5 |
//Address bar register defines the base address for each image. |
//To asccess bus without Software configuration. |
`define WB_BA1 20'h1000_0 |
`define WB_BA2 20'h2000_0 |
`define WB_BA3 20'h3000_0 |
`define WB_BA4 20'h4000_0 |
`define WB_BA5 20'h5000_0 |
`define WB_BA1 20'h0000_0 |
`define WB_BA2 20'h0000_0 |
`define WB_BA3 20'h0000_0 |
`define WB_BA4 20'h0000_0 |
`define WB_BA5 20'h0000_0 |
|
// initial value for WB image maping to MEMORY or IO spaces. If initial define is set to 0, |
// then IMAGE with that base address points to MEMORY space, othervise it points ti IO space. |
224,20 → 227,20
`define WB_BA5_MEM_IO 1'b0 |
|
// initial value for WB image address masks. |
`define WB_AM1 20'hffff_f |
`define WB_AM2 20'hffff_f |
`define WB_AM3 20'hffff_f |
`define WB_AM4 20'hffff_f |
`define WB_AM5 20'hffff_f |
`define WB_AM1 20'h0000_0 |
`define WB_AM2 20'h0000_0 |
`define WB_AM3 20'h0000_0 |
`define WB_AM4 20'h0000_0 |
`define WB_AM5 20'h0000_0 |
|
// initial value for WB translation addresses. The initial values |
// are set after reset. When ADDR_TRAN_IMPL is defined then then Images |
// are transleted to this adresses whithout access to pci_ta registers. |
`define WB_TA1 20'h2000_0 |
`define WB_TA2 20'h3000_0 |
`define WB_TA3 20'h4000_0 |
`define WB_TA4 20'h5000_0 |
`define WB_TA5 20'h6000_0 |
`define WB_TA1 20'h0000_0 |
`define WB_TA2 20'h0000_0 |
`define WB_TA3 20'h0000_0 |
`define WB_TA4 20'h0000_0 |
`define WB_TA5 20'h0000_0 |
|
// If this define is commented out, then address translation will not be implemented. |
// addresses will pass through bridge unchanged, regardles of address translation enable bits. |