OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 142 to Rev 143
    ↔ Reverse comparison
  •

Rev 142 → Rev 143

/trunk/bench/verilog/system.v
39,6 → 39,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.25 2004/03/19 16:36:26 mihad
// Single PCI Master write fix.
//
// Revision 1.24 2004/01/24 11:54:16 mihad
// Update! SPOCI Implemented!
//
11830,6 → 11833,7
reg [31:0] expected_value ;
reg failed ;
reg [31:0] reg_value [0:`ISR_ADDR] ;
reg [31:0] header_value[0:15] ;
reg [5:0] reg_address ;
integer t_i;
 
11844,6 → 11848,49
reg_value[t_i]=31'h0;
t_i= t_i+1;
end
 
t_i = 0 ;
while(t_i < 16)
begin
header_value[t_i] = 0 ;
t_i = t_i + 1 ;
end
 
// fill header register values
header_value[0] = {`HEADER_DEVICE_ID, `HEADER_VENDOR_ID} ;
 
// determine the expected value of status and control registers
tmp_reg_val = 'h0 ;
tmp_reg_val[10+16:9+16] = 'b01 ; // devsel timing
tmp_reg_val[7+16] = 1'b1 ; // fast b2b capable
`ifdef PCI66
tmp_reg_val[5+16] = 1'b1 ; // 66MHz capable
`endif
 
`ifdef GUEST
`ifdef PCI_CPCI_HS_IMPLEMENT
tmp_reg_val[4+16] = 1'b1 ;
`endif
`endif
 
header_value[1] = tmp_reg_val ;
 
// class code, revision ID register
tmp_reg_val = 'h0 ;
tmp_reg_val[31:24] = 'h06 ;
tmp_reg_val[7:0] = `HEADER_REVISION_ID ;
`ifdef GUEST
tmp_reg_val[23:16] = 'h80 ;
`endif
header_value[2] = tmp_reg_val ;
 
header_value[11] = {`HEADER_SUBSYS_ID, `HEADER_SUBSYS_VENDOR_ID} ;
`ifdef PCI_CPCI_HS_IMPLEMENT
header_value[13] = `PCI_CAP_PTR_VAL ;
`endif
 
header_value[15] = {`HEADER_MAX_LAT, `HEADER_MIN_GNT, 8'h01, 8'h00} ;
 
////PCI register
`ifdef HOST
 
11853,7 → 11900,11
reg_value[0 ]= `PCI_AT_EN0 << 2 ; //PCi Control Register0
if (`PCI_AM0)
begin
reg_value[1 ]=`PCI_BA0_MEM_IO; //PCi Base Address Register0
header_value[4] = `PCI_BA0_MEM_IO ;
end
 
tmp_reg_val={`PCI_AM0, 12'h000} ;
tmp_reg_val[31 - `PCI_NUM_OF_DEC_ADDR_LINES:0] = 'h0 ;
reg_value[2 ]=tmp_reg_val; //PCi Address Mask Register0
11877,7 → 11928,10
reg_value[4 ]=`PCI_AT_EN1 << 2 ; //PCi Control Register1
 
if (`PCI_AM1)
begin
reg_value[5 ]={ 31'h0,`PCI_BA1_MEM_IO}; //PCi Base Address Register1
header_value[5] = `PCI_BA1_MEM_IO ;
end
tmp_reg_val={`PCI_AM1, 12'h000} ;
tmp_reg_val[31 - `PCI_NUM_OF_DEC_ADDR_LINES:0] = 'h0 ;
reg_value[6 ]=tmp_reg_val; //PCi Address Mask Register0
11889,7 → 11943,10
reg_value[8 ]=`PCI_AT_EN2 << 2; //PCi Control Register2
if (`PCI_AM2) //PCi Base Address Register2
reg_value[9 ]={31'h0,`PCI_BA2_MEM_IO};
begin
reg_value[9 ]={31'h0,`PCI_BA2_MEM_IO};
header_value[6] = `PCI_BA2_MEM_IO ;
end
tmp_reg_val={`PCI_AM2, 12'h000} ;
tmp_reg_val[31 - `PCI_NUM_OF_DEC_ADDR_LINES:0] = 'h0 ;
reg_value[10 ]=tmp_reg_val; //PCi Address Mask Register0
11903,7 → 11960,10
reg_value[12]=`PCI_AT_EN3 << 2; //PCi Control Register3
if (`PCI_AM3) //PCi Base Address Register3
reg_value[13]={31'h000,`PCI_BA3_MEM_IO};
begin
reg_value[13]={31'h000,`PCI_BA3_MEM_IO};
header_value[7] = `PCI_BA3_MEM_IO ;
end
tmp_reg_val={`PCI_AM3, 12'h000} ;
tmp_reg_val[31 - `PCI_NUM_OF_DEC_ADDR_LINES:0] = 'h0 ;
reg_value[14 ]=tmp_reg_val; //PCi Address Mask Register0
11917,7 → 11977,10
reg_value[16]=`PCI_AT_EN4 << 2; //PCi Control Register4
if (`PCI_AM4) //PCi Base Address Register4
reg_value[17]={31'h000,`PCI_BA4_MEM_IO};
begin
reg_value[17]={31'h000,`PCI_BA4_MEM_IO};
header_value[8] = `PCI_BA4_MEM_IO ;
end
tmp_reg_val={`PCI_AM4, 12'h000} ;
tmp_reg_val[31 - `PCI_NUM_OF_DEC_ADDR_LINES:0] = 'h0 ;
reg_value[18 ]=tmp_reg_val; //PCi Address Mask Register0
11931,7 → 11994,11
reg_value[20]=`PCI_AT_EN5 << 2; //PCi Control Register5
if (`PCI_AM5) //PCi Base Address Register5
reg_value[21]={31'h000,`PCI_BA5_MEM_IO};
begin
reg_value[21]={31'h000,`PCI_BA5_MEM_IO};
header_value[9] = `PCI_BA5_MEM_IO ;
end
 
tmp_reg_val={`PCI_AM5, 12'h000} ;
tmp_reg_val[31 - `PCI_NUM_OF_DEC_ADDR_LINES:0] = 'h0 ;
reg_value[22 ]=tmp_reg_val; //PCi Address Mask Register0
12043,39 → 12110,66
//read registers
reg_address=0;
while ((reg_address <= `INT_ACK_ADDR) && (failed==0) )
 
begin
if (( reg_address !== `CNF_DATA_ADDR) && ( reg_address !== `INT_ACK_ADDR))
begin
register_offset = {1'b1, reg_address, 2'b00} ;
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE,register_offset} ;
wishbone_master.wb_single_read(read_data, flags, read_status) ;
if (read_status`CYC_ACTUAL_TRANSFER !== 1)
begin
$fdisplay( tb_log_file,"error Config Register Adress %h", read_data`READ_ADDRESS);
$display("error Config Register Adress %h", read_data`READ_ADDRESS);
test_fail("read from config register didn't succeede") ;
failed = 1 ;
if (( reg_address !== `CNF_DATA_ADDR) && ( reg_address !== `INT_ACK_ADDR))
begin
register_offset = {1'b1, reg_address, 2'b00} ;
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE,register_offset} ;
wishbone_master.wb_single_read(read_data, flags, read_status) ;
if (read_status`CYC_ACTUAL_TRANSFER !== 1)
begin
$fdisplay( tb_log_file,"error Config Register Adress %h", read_data`READ_ADDRESS);
$display("error Config Register Adress %h", read_data`READ_ADDRESS);
test_fail("read from config register didn't succeede") ;
failed = 1 ;
end
else if( read_status`READ_DATA !== reg_value[reg_address])
begin
$fdisplay( tb_log_file,"error Config Register Adress %h",
read_data`READ_ADDRESS,
," expected: %h ",reg_value[reg_address]," read: %h",read_status`READ_DATA);
$display("error Config Register Adress %h",
read_data`READ_ADDRESS ,
," expected: %h ",reg_value[reg_address]," read: %h",read_status`READ_DATA," Time %t ", $time) ;
test_fail("Initial value of register not as expected") ;
failed = 1 ;
end
end
if (`P_ERR_DATA_ADDR ==reg_address )
reg_address=`WB_CONF_SPC_BAR_ADDR ;
else
reg_address= reg_address+1;
 
end
else
end
 
if( read_status`READ_DATA !== reg_value[reg_address])
begin
$fdisplay( tb_log_file,"error Config Register Adress %h",
read_data`READ_ADDRESS,
," expected: %h ",reg_value[reg_address]," read: %h",read_status`READ_DATA);
$display("error Config Register Adress %h",
read_data`READ_ADDRESS ,
," expected: %h ",reg_value[reg_address]," read: %h",read_status`READ_DATA," Time %t ", $time) ;
test_fail("Initial value of register not as expected") ;
failed = 1 ;
end
end
if (`P_ERR_DATA_ADDR ==reg_address )
reg_address=`WB_CONF_SPC_BAR_ADDR ;
else
reg_address= reg_address+1;
//read registers
reg_address=0;
while ((reg_address < 'd16) && (failed==0) )
begin
register_offset = {1'b0, reg_address, 2'b00} ;
read_data`READ_ADDRESS = {`WB_CONFIGURATION_BASE,register_offset} ;
wishbone_master.wb_single_read(read_data, flags, read_status) ;
if (read_status`CYC_ACTUAL_TRANSFER !== 1)
begin
$fdisplay( tb_log_file,"error Config Register Adress %h", read_data`READ_ADDRESS);
$display("error Config Register Adress %h", read_data`READ_ADDRESS);
test_fail("read from config register didn't succeede") ;
failed = 1 ;
end
else if( read_status`READ_DATA !== header_value[reg_address])
begin
$fdisplay( tb_log_file,"error Config Register Adress %h",
read_data`READ_ADDRESS,
," expected: %h ",header_value[reg_address]," read: %h",read_status`READ_DATA);
$display("error Config Register Adress %h",
read_data`READ_ADDRESS ,
," expected: %h ",header_value[reg_address]," read: %h",read_status`READ_DATA," Time %t ", $time) ;
test_fail("Initial value of register not as expected") ;
failed = 1 ;
end
reg_address= reg_address+1;
 
end
end
12090,6 → 12184,36
integer t_max;
reg ok ;
 
// first read the header portion using the configuration cycles
reg_address = 0 ;
while (reg_address < 'd16)
begin
configuration_cycle_read
(
8'h00, // bus number [7:0]
`TAR0_IDSEL_INDEX - 11, // device number [4:0]
3'h0, // function number [2:0]
reg_address, // register number [5:0]
2'h0, // type [1:0]
4'hF, // byte enables [3:0]
read_data // data returned from configuration read [31:0]
) ;
 
if( read_data !== header_value[reg_address])
begin
$fdisplay( tb_log_file,"error Config Register Adress %h",
{4'h0, reg_address ,2'b00},
," expected:%h ",header_value[reg_address]," read:%h",read_data);
$display("error Config Register Adress %h",
{4'h0, reg_address ,2'b00},
," expected:%h ",header_value[reg_address]," read:%h",read_data," Time %t ", $time) ;
test_fail("Initial value of register not as expected") ;
failed = 1 ;
end
 
reg_address= reg_address+1;
end
configure_bridge_target;//Target must be configured to read the other bars
 
reg_address=0;
12113,6 → 12237,7
reg_address= reg_address+1;
 
end
 
//clearing all TA's for later tests
reg_address=`P_TA0_ADDR;
while ((reg_address <= `W_TA5_ADDR) && (failed==0) )
12136,7 → 12261,8
`endif
 
end
endtask //
endtask
 
task test_initial_conf_values ;
reg [11:0] register_offset ;
reg [31:0] expected_value ;
15990,7 → 16116,7
if (ok === 1'b1)
test_ok ;
 
test_name = "SERIAL EPROM PRESENT AFTER RESET, HOLDS P_BA0 AND PCI COMMAND REGISTER VALUES" ;
test_name = "SERIAL EPROM PRESENT AFTER RESET, HOLDS P_BA0, PCI COMMAND AND ID REGISTER VALUES" ;
 
do_pause ( 10 ) ;
 
16020,8 → 16146,45
i_i2c_slave_model.mem[8] = read_data[23:16] ;
i_i2c_slave_model.mem[9] = read_data[31:24] ;
 
i_i2c_slave_model.mem[10] = 'hff ;
read_data[15: 0] = `HEADER_VENDOR_ID + 'h1 ;
read_data[31:16] = `HEADER_DEVICE_ID + 'h2 ;
i_i2c_slave_model.mem[10] = 'h0 ;
i_i2c_slave_model.mem[11] = read_data[ 7: 0] ;
i_i2c_slave_model.mem[12] = read_data[15: 8] ;
i_i2c_slave_model.mem[13] = read_data[23:16] ;
i_i2c_slave_model.mem[14] = read_data[31:24] ;
 
read_data[15: 0] = `HEADER_SUBSYS_VENDOR_ID + 'h3 ;
read_data[31:16] = `HEADER_SUBSYS_ID + 'h4 ;
i_i2c_slave_model.mem[15] = 'h2c >> 2 ;
i_i2c_slave_model.mem[16] = read_data[ 7: 0] ;
i_i2c_slave_model.mem[17] = read_data[15: 8] ;
i_i2c_slave_model.mem[18] = read_data[23:16] ;
i_i2c_slave_model.mem[19] = read_data[31:24] ;
 
read_data[ 7: 0] = `HEADER_REVISION_ID + 'h5 ;
read_data[31: 8] = $random ;
i_i2c_slave_model.mem[20] = 'h8 >> 2 ;
i_i2c_slave_model.mem[21] = read_data[ 7: 0] ;
i_i2c_slave_model.mem[22] = read_data[15: 8] ;
i_i2c_slave_model.mem[23] = read_data[23:16] ;
i_i2c_slave_model.mem[24] = read_data[31:24] ;
 
read_data[31:24] = ~(`HEADER_MAX_LAT) ;
read_data[23:16] = ~(`HEADER_MIN_GNT) ;
read_data[15: 0] = 'hffff ;
i_i2c_slave_model.mem[25] = 'h3c >> 2 ;
i_i2c_slave_model.mem[26] = read_data[ 7: 0] ;
i_i2c_slave_model.mem[27] = read_data[15: 8] ;
i_i2c_slave_model.mem[28] = read_data[23:16] ;
i_i2c_slave_model.mem[29] = read_data[31:24] ;
 
i_i2c_slave_model.mem[30] = 'hff ;
 
fork
begin
// set valid eprom slave address
16069,7 → 16232,7
end
 
// now wait for 12c eprom to transmit all configured bytes
repeat(11)
repeat(31)
begin
wait(i_i2c_slave_model.acc_done === 1'b0) ;
wait(i_i2c_slave_model.acc_done === 1'b1) ;
16180,15 → 16343,95
if (read_data !== (Target_Base_Addr_R[0] & {{`PCI_NUM_OF_DEC_ADDR_LINES{1'b1}}, {(32 - `PCI_NUM_OF_DEC_ADDR_LINES){1'b0}}} ) )
begin
$display("Time %t", $time) ;
$display("Read from serial eprom control and status register returned unexpected data value") ;
test_fail("Read from serial eprom control and status register returned unexpected data value") ;
$display("Read from PCI BAR0 register returned unexpected data value") ;
test_fail("Read from PCI BAR0 register returned unexpected data value") ;
ok = 1'b0 ;
end
 
config_read('h0, 4'hF, read_data) ;
 
if (read_data[15: 0] !== (`HEADER_VENDOR_ID + 'h1))
begin
$display("Time %t", $time) ;
$display("Read from VendorID register returned unexpected data value") ;
test_fail("Read from VendorID register returned unexpected data value") ;
ok = 1'b0 ;
end
 
if (read_data[31:16] !== (`HEADER_DEVICE_ID + 'h2))
begin
$display("Time %t", $time) ;
$display("Read from DeviceID register returned unexpected data value") ;
test_fail("Read from DeviceID register returned unexpected data value") ;
ok = 1'b0 ;
end
config_read('h2c, 4'hF, read_data) ;
 
if (read_data[15: 0] !== (`HEADER_SUBSYS_VENDOR_ID + 'h3))
begin
$display("Time %t", $time) ;
$display("Read from SubsystemVendorID register returned unexpected data value") ;
test_fail("Read from SubsystemVendorID register returned unexpected data value") ;
ok = 1'b0 ;
end
 
if (read_data[31:16] !== (`HEADER_SUBSYS_ID + 'h4))
begin
$display("Time %t", $time) ;
$display("Read from SubsystemID register returned unexpected data value") ;
test_fail("Read from SubsystemID register returned unexpected data value") ;
ok = 1'b0 ;
end
 
config_read('h8, 4'hF, read_data) ;
 
if (read_data[ 7: 0] !== (`HEADER_REVISION_ID + 'h5))
begin
$display("Time %t", $time) ;
$display("Read from RevisionID register returned unexpected data value") ;
test_fail("Read from RevisionID register returned unexpected data value") ;
ok = 1'b0 ;
end
 
if (read_data[31: 8] !== 'h06_80_00)
begin
$display("Time %t", $time) ;
$display("Read from ClassCode register returned unexpected data value") ;
test_fail("Read from ClassCode register returned unexpected data value") ;
ok = 1'b0 ;
end
 
config_read('h3c, 4'hF, read_data) ;
 
if (read_data[31:24] !== ~(`HEADER_MAX_LAT))
begin
$display("Time %t", $time) ;
$display("Read from MaxLatency register returned unexpected data value") ;
test_fail("Read from MaxLatency register returned unexpected data value") ;
ok = 1'b0 ;
end
 
if (read_data[23:16] !== ~(`HEADER_MIN_GNT))
begin
$display("Time %t", $time) ;
$display("Read from MinGnt register returned unexpected data value") ;
test_fail("Read from MinGnt register returned unexpected data value") ;
ok = 1'b0 ;
end
 
if (read_data[15: 0] !== 'h01ff)
begin
$display("Time %t", $time) ;
$display("Read from IntPin/IntLine register returned unexpected data value") ;
test_fail("Read from IntPin/IntLine register returned unexpected data value") ;
ok = 1'b0 ;
end
 
if (ok)
test_ok ;
 
test_name = "SERIAL EPROM PRESENT AFTER RESET, HOLDS ALL *_BA*, *_AM* AND PCI COMMAND REGISTER VALUES" ;
test_name = "SERIAL EPROM PRESENT AFTER RESET, HOLDS ALL *_BA*, *_AM*, PCI COMMAND AND ID REGISTER VALUES" ;
 
do_pause ( 10 ) ;
 
16436,8 → 16679,38
i_i2c_slave_model.mem[148] = image_base[23:16] ;
i_i2c_slave_model.mem[149] = image_base[31:24] ;
 
i_i2c_slave_model.mem[150] = 'hff ;
read_data[15: 0] = `HEADER_VENDOR_ID ;
read_data[31:16] = `HEADER_DEVICE_ID ;
read_data = ~read_data ;
i_i2c_slave_model.mem[150] = 'h0 ;
i_i2c_slave_model.mem[151] = read_data[ 7: 0] ;
i_i2c_slave_model.mem[152] = read_data[15: 8] ;
i_i2c_slave_model.mem[153] = read_data[23:16] ;
i_i2c_slave_model.mem[154] = read_data[31:24] ;
 
read_data[15: 0] = `HEADER_SUBSYS_VENDOR_ID ;
read_data[31:16] = `HEADER_SUBSYS_ID ;
read_data = ~read_data ;
 
i_i2c_slave_model.mem[155] = 'h2c >> 2 ;
i_i2c_slave_model.mem[156] = read_data[ 7: 0] ;
i_i2c_slave_model.mem[157] = read_data[15: 8] ;
i_i2c_slave_model.mem[158] = read_data[23:16] ;
i_i2c_slave_model.mem[159] = read_data[31:24] ;
 
read_data[ 7: 0] = `HEADER_REVISION_ID ;
read_data[31: 8] = $random ;
read_data = ~read_data ;
i_i2c_slave_model.mem[160] = 'h8 >> 2 ;
i_i2c_slave_model.mem[161] = read_data[ 7: 0] ;
i_i2c_slave_model.mem[162] = read_data[15: 8] ;
i_i2c_slave_model.mem[163] = read_data[23:16] ;
i_i2c_slave_model.mem[164] = read_data[31:24] ;
 
i_i2c_slave_model.mem[165] = 'hff ;
 
fork
begin
// set valid eprom slave address
16485,7 → 16758,7
end
 
// now wait for 12c eprom to transmit all configured bytes
repeat(151)
repeat(166)
begin
wait(i_i2c_slave_model.acc_done === 1'b0) ;
wait(i_i2c_slave_model.acc_done === 1'b1) ;
16860,6 → 17133,44
ok = 1'b0 ;
end
 
config_read('h0, 4'hF, read_data) ;
 
if (read_data !== ~{`HEADER_DEVICE_ID, `HEADER_VENDOR_ID})
begin
$display("Time %t", $time) ;
$display("Read from VendorID, DeviceID register returned unexpected data value") ;
test_fail("Read from VendorID, DeviceID register returned unexpected data value") ;
ok = 1'b0 ;
end
 
config_read('h2c, 4'hF, read_data) ;
 
if (read_data !== ~{`HEADER_SUBSYS_ID, `HEADER_SUBSYS_VENDOR_ID})
begin
$display("Time %t", $time) ;
$display("Read from SubsystemVendorID, SubsystemID register returned unexpected data value") ;
test_fail("Read from SubsystemVendorID, SubsystemID register returned unexpected data value") ;
ok = 1'b0 ;
end
 
config_read('h8, 4'hF, read_data) ;
 
if (read_data[ 7: 0] !== ~(`HEADER_REVISION_ID))
begin
$display("Time %t", $time) ;
$display("Read from RevisionID register returned unexpected data value") ;
test_fail("Read from RevisionID register returned unexpected data value") ;
ok = 1'b0 ;
end
 
if (read_data[31: 8] !== 'h06_80_00)
begin
$display("Time %t", $time) ;
$display("Read from ClassCode register returned unexpected data value") ;
test_fail("Read from ClassCode register returned unexpected data value") ;
ok = 1'b0 ;
end
 
// access all implemented PCI images after power on configuration is complete
// set wishbone slave response to acknowledge
wishbone_slave.cycle_response(3'b100, wb_subseq_waits, 8'h0);
/trunk/bench/verilog/pci_regression_constants.v
39,6 → 39,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2004/01/24 11:54:16 mihad
// Update! SPOCI Implemented!
//
// Revision 1.5 2003/12/19 11:11:28 mihad
// Compact PCI Hot Swap support added.
// New testcases added.
304,9 → 307,14
Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used
together by application.
-----------------------------------------------------------------------------------------------------------*/
`define HEADER_VENDOR_ID 16'h2321
`define HEADER_DEVICE_ID 16'h0001
`define HEADER_REVISION_ID 8'h01
`define HEADER_VENDOR_ID 16'h1895
`define HEADER_DEVICE_ID 16'h0001
`define HEADER_REVISION_ID 8'h01
`define HEADER_SUBSYS_VENDOR_ID 16'h1895
`define HEADER_SUBSYS_ID 16'h0001
`define HEADER_MAX_LAT 8'h1a
`define HEADER_MIN_GNT 8'h08
 
// MAX Retry counter value for WISHBONE Master state-machine
// This value is 8-bit because of 8-bit retry counter !!!
/trunk/rtl/verilog/pci_conf_space.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2004/01/24 11:54:18 mihad
// Update! SPOCI Implemented!
//
// Revision 1.6 2003/12/28 09:54:48 fr2201
// def_wb_imagex_addr_map defined correctly
//
359,8 → 362,11
together by application. Class_Code has 3 bytes to define BASE class (06h for PCI Bridge), SUB class
(00h for HOST type, 80h for Other Bridge type) and Interface type (00h for normal).
-----------------------------------------------------------------------------------------------------------*/
parameter r_vendor_id = `HEADER_VENDOR_ID ; // 16'h2321 = 16'd8993 !!!
parameter r_device_id = `HEADER_DEVICE_ID ;
reg [15: 0] r_vendor_id ;
reg [15: 0] r_device_id ;
reg [15: 0] r_subsys_vendor_id ;
reg [15: 0] r_subsys_id ;
 
reg command_bit8 ;
reg command_bit6 ;
reg [2 : 0] command_bit2_0 ;
384,7 → 390,8
wire r_status_bit4 = 0 ;
`endif
 
parameter r_revision_id = `HEADER_REVISION_ID ;
reg [ 7: 0] r_revision_id ;
 
`ifdef HOST
parameter r_class_code = 24'h06_00_00 ;
`else
423,8 → 430,8
// REG r_cap_list_pointer NOT implemented !!!
reg [7 : 0] interrupt_line ;
parameter r_interrupt_pin = 8'h01 ;
parameter r_min_gnt = 8'h08 ;
parameter r_max_lat = 8'h1a ;
reg [7 : 0] r_min_gnt ;
reg [7 : 0] r_max_lat ;
 
 
/*###########################################################################################################
845,7 → 852,8
 
always@(r_conf_address_in or
status_bit15_11 or status_bit8 or r_status_bit4 or command_bit8 or command_bit6 or command_bit2_0 or
latency_timer or cache_line_size_reg or
latency_timer or cache_line_size_reg or r_vendor_id or r_device_id or r_revision_id or
r_subsys_vendor_id or r_subsys_id or r_max_lat or r_min_gnt or
pci_ba0_bit31_12 or
pci_img_ctrl0_bit2_1 or pci_am0 or pci_ta0 or pci_ba0_bit0 or
pci_img_ctrl1_bit2_1 or pci_am1 or pci_ta1 or pci_ba1_bit31_12 or pci_ba1_bit0 or
924,6 → 932,10
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
r_conf_data_out[0] = pci_ba5_bit0 & pci_am5[31];
end
8'hB:
begin
r_conf_data_out = {r_subsys_id, r_subsys_vendor_id} ;
end
`ifdef PCI_CPCI_HS_IMPLEMENT
8'hD:
begin
1170,11 → 1182,13
wire [11: 0] w_conf_address = init_complete ? w_conf_address_in : {2'b00, spoci_reg_num, 2'b00} ;
`else
wire [11: 0] w_conf_address = w_conf_address_in ;
wire [ 7: 0] spoci_reg_num = 'hff ;
`endif
 
always@(w_conf_address or
status_bit15_11 or status_bit8 or r_status_bit4 or command_bit8 or command_bit6 or command_bit2_0 or
latency_timer or cache_line_size_reg or
latency_timer or cache_line_size_reg or r_vendor_id or r_device_id or r_revision_id or
r_subsys_id or r_subsys_vendor_id or r_max_lat or r_min_gnt or
pci_ba0_bit31_12 or
pci_img_ctrl0_bit2_1 or pci_am0 or pci_ta0 or pci_ba0_bit0 or
pci_img_ctrl1_bit2_1 or pci_am1 or pci_ta1 or pci_ba1_bit31_12 or pci_ba1_bit0 or
1274,6 → 1288,12
w_conf_data_out[0] = pci_ba5_bit0 & pci_am5[31];
w_reg_select_dec = 57'h000_0000_0100_0000 ; // The same for another address
end
8'hB:
begin
w_conf_data_out = {r_subsys_id, r_subsys_vendor_id} ;
w_reg_select_dec = 57'h000_0000_0000_0000 ;
end
 
`ifdef PCI_CPCI_HS_IMPLEMENT
8'hD:
begin
1657,6 → 1677,7
wire init_cfg_done = 1'b1 ;
wire [31: 0] w_conf_data = w_conf_data_in ;
wire [ 3: 0] w_byte_en = w_byte_en_in ;
wire [31: 0] spoci_dat = 'h0000_0000 ;
`endif
 
// Reduced write data for BASE, MASK and TRANSLATION registers of PCI and WB images
2388,6 → 2409,48
end
end
 
// implementation of read only device identification registers
always@(posedge w_clock or posedge reset)
begin
if (reset)
begin
r_vendor_id <= `HEADER_VENDOR_ID ;
r_device_id <= `HEADER_DEVICE_ID ;
r_revision_id <= `HEADER_REVISION_ID ;
r_subsys_vendor_id <= `HEADER_SUBSYS_VENDOR_ID ;
r_subsys_id <= `HEADER_SUBSYS_ID ;
r_max_lat <= `HEADER_MAX_LAT ;
r_min_gnt <= `HEADER_MIN_GNT ;
end else
begin
if (init_we)
begin
if (spoci_reg_num == 'h0)
begin
r_vendor_id <= spoci_dat[15: 0] ;
r_device_id <= spoci_dat[31:16] ;
end
 
if (spoci_reg_num == 'hB)
begin
r_subsys_vendor_id <= spoci_dat[15: 0] ;
r_subsys_id <= spoci_dat[31:16] ;
end
 
if (spoci_reg_num == 'h2)
begin
r_revision_id <= spoci_dat[ 7: 0] ;
end
 
if (spoci_reg_num == 'hF)
begin
r_max_lat <= spoci_dat[31:24] ;
r_min_gnt <= spoci_dat[23:16] ;
end
end
end
end
 
// This signals are synchronous resets for registers, whic occures when asynchronous RESET is '1' or
// data '1' is synchronously written into them!
reg delete_status_bit15 ;
3786,6 → 3849,5
assign config_addr[23 : 0] = { cnf_addr_bit23_2, 1'b0, cnf_addr_bit0 } ;
assign icr_soft_res = icr_bit31 ;
 
 
endmodule
/trunk/rtl/verilog/pci_user_constants.v
39,6 → 39,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.13 2004/01/24 11:54:18 mihad
// Update! SPOCI Implemented!
//
// Revision 1.12 2003/12/28 09:54:48 fr2201
// def_wb_imagex_addr_map defined correctly
//
92,24 → 95,24
// If RAM_DONT_SHARE is defined, then all RAM address lengths must be specified accordingly, otherwise there are two relevant lengths - PCI_FIFO_RAM_ADDR_LENGTH and
// WB_FIFO_RAM_ADDR_LENGTH.
 
`define WBW_ADDR_LENGTH 7
`define WBR_ADDR_LENGTH 7
`define PCIW_ADDR_LENGTH 7
`define PCIR_ADDR_LENGTH 7
`define WBW_ADDR_LENGTH 4
`define WBR_ADDR_LENGTH 4
`define PCIW_ADDR_LENGTH 4
`define PCIR_ADDR_LENGTH 4
 
`define FPGA
`define XILINX
 
//`define WB_RAM_DONT_SHARE
//`define PCI_RAM_DONT_SHARE
`define PCI_RAM_DONT_SHARE
 
`ifdef FPGA
`ifdef XILINX
`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition
`define PCI_FIFO_RAM_ADDR_LENGTH 4 // PCI target unit fifo storage definition
`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition
`define PCI_XILINX_RAMB4
//`define PCI_XILINX_RAMB4
`define WB_XILINX_RAMB4
//`define PCI_XILINX_DIST_RAM
`define PCI_XILINX_DIST_RAM
//`define WB_XILINX_DIST_RAM
`endif
`else
209,7 → 212,7
// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of WB images,
// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
// smaller the number here, faster the decoder operation
`define WB_NUM_OF_DEC_ADDR_LINES 20
`define WB_NUM_OF_DEC_ADDR_LINES 1
 
// no. of WISHBONE Slave IMAGES
// WB image 0 is always used for access to configuration space. In case configuration space access is not implemented,
220,6 → 223,7
`define WB_IMAGE3
`define WB_IMAGE4
`define WB_IMAGE5
 
//Address bar register defines the base address for each image.
//To asccess bus without Software configuration.
`define WB_BA1 20'h0000_0
262,7 → 266,7
// addresses will pass through bridge unchanged, regardles of address translation enable bits.
// Address translation also slows down the decoding
//When ADDR_TRAN_IMPL this define is present then adress translation is enabled after reset.
`define ADDR_TRAN_IMPL
//`define ADDR_TRAN_IMPL
 
// decode speed for WISHBONE definition - initial cycle on WISHBONE bus will take 1 WS for FAST, 2 WSs for MEDIUM and 3 WSs for slow.
// slower decode speed can be used, to provide enough time for address to be decoded.
282,8 → 286,8
Core speed definition - used for simulation and 66MHz Capable bit value in status register indicating 66MHz
capable device
-----------------------------------------------------------------------------------------------------------*/
`define PCI33
//`define PCI66
//`define PCI33
`define PCI66
 
/*-----------------------------------------------------------------------------------------------------------
[000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type !
291,9 → 295,13
Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used
together by application.
-----------------------------------------------------------------------------------------------------------*/
`define HEADER_VENDOR_ID 16'h1895
`define HEADER_DEVICE_ID 16'h0001
`define HEADER_REVISION_ID 8'h01
`define HEADER_VENDOR_ID 16'h1895
`define HEADER_DEVICE_ID 16'h0001
`define HEADER_REVISION_ID 8'h01
`define HEADER_SUBSYS_VENDOR_ID 16'h1895
`define HEADER_SUBSYS_ID 16'h0001
`define HEADER_MAX_LAT 8'h1a
`define HEADER_MIN_GNT 8'h08
 
// MAX Retry counter value for WISHBONE Master state-machine
// This value is 8-bit because of 8-bit retry counter !!!
310,3 → 318,4
`define PCI_CPCI_HS_IMPLEMENT
`define PCI_SPOCI
`endif
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.