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    from Rev 150 to Rev 151
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Rev 150 → Rev 151

/trunk/bench/verilog/system.v
39,6 → 39,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.27 2004/08/19 15:27:31 mihad
// Changed minimum pci image size to 256 bytes because
// of some PC system problems with size of IO images.
//
// Revision 1.26 2004/07/07 12:45:02 mihad
// Added SubsystemVendorID, SubsystemID, MAXLatency, MinGnt defines.
// Enabled value loading from serial EEPROM for all of the above + VendorID and DeviceID registers.
1618,6 → 1622,54
end
end
join
 
test_name = "MULTIPLE NORMAL SINGLE MEMORY READS, SAME ADDRESS, CHANGE DATA" ;
 
i = 32'hFFFF_FFFF ;
 
// read written data back
read_data`READ_ADDRESS = target_address + ({$random} % 4) + 72 ;
read_data`READ_SEL = 4'hF ;
write_flags`WB_TRANSFER_AUTO_RTY = 1'b1 ;
 
fork
begin
 
repeat(5)
begin
pci_behaviorial_device1.pci_behaviorial_target.Test_Device_Mem[72 >> 2] = $random ;
wishbone_master.wb_single_read( read_data, write_flags, read_status ) ;
if (read_status`CYC_ACTUAL_TRANSFER !== 1)
begin
$display("Image testing failed! Bridge failed to process single memory read! Time %t ", $time) ;
test_fail("PCI bridge didn't process the read as expected");
i[0] = 1'b0 ;
end
 
if (read_status`READ_DATA !== pci_behaviorial_device1.pci_behaviorial_target.Test_Device_Mem[72 >> 2])
begin
display_warning(read_data`READ_ADDRESS, pci_behaviorial_device1.pci_behaviorial_target.Test_Device_Mem[72 >> 2], read_status`READ_DATA) ;
test_fail("PCI bridge returned unexpected Read Data");
i[0] = 1'b0 ;
end
write_flags`WB_FAST_B2B = 1'b1 ;
end
 
if (i === 32'hFFFF_FFFF)
test_ok ;
end
begin
repeat(5)
begin
pci_transaction_progress_monitor( read_data`READ_ADDRESS & 32'hffff_fffc, `BC_MEM_READ, 1, 0, 1, 0, 0, ok ) ;
if ( ok !== 1 )
begin
i[1] = 1'b0 ;
test_fail("because single memory read from WB to PCI didn't engage expected transaction on PCI bus") ;
end
end
end
join
test_name = "MULTIPLE NON-CONSECUTIVE SINGLE MEMORY WRITES THROUGH WISHBONE SLAVE UNIT" ;
begin:non_consecutive_single_writes_test_blk
1630,6 → 1682,7
write_data`WRITE_SEL = 4'hF ;
write_flags`WB_TRANSFER_AUTO_RTY = 1'b1 ;
write_flags`WB_TRANSFER_CAB = 1'b0 ;
write_flags`WB_FAST_B2B = 1'b0 ;
rnd_seed = 32'h12fe_dc34 ;
16098,7 → 16151,7
 
config_read( {4'h1, `P_BA1_ADDR, 2'b00}, 4'hF, read_data ) ;
 
if (read_data !== 32'h0000_0000)
if (read_data !== {31'h0000_0000, `PCI_BA1_MEM_IO})
begin
$display("Time %t", $time) ;
$display("Invalid value read from P_BA1 register") ;
21101,6 → 21154,58
begin
expect_length_wr = Set_size ;
end
 
test_name = "MULTIPLE SINGLE MEMORY READS THROUGH PCI TARGET UNIT, SAME ADDRESS, CHANGE DATA" ;
 
master2_check_received_data = 1 ;
master1_check_received_data = 1 ;
 
fork
begin
repeat(5)
begin
wishbone_slave.wb_memory[expect_address[21:2]] = $random ;
PCIU_READ (Master_ID[2:0], Address,
`BC_MEM_READ, wishbone_slave.wb_memory[expect_address[21:2]], `Test_All_Bytes,
1, `Test_One_Zero_Master_WS, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Start_Delayed_Read);
 
do_pause(1) ;
 
wb_transaction_stop( Set_prefetch_enable ? Cache_lsize : 1 ) ;
@(posedge wb_clock) ;
do_pause( 2 ) ;
 
PCIU_READ (Master_ID[2:0], Address,
`BC_MEM_READ, wishbone_slave.wb_memory[expect_address[21:2]], `Test_All_Bytes,
1, `Test_One_Zero_Master_WS, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
do_pause(0) ;
end
 
@(posedge pci_clock) ;
 
while ( FRAME === 0 )
@(posedge pci_clock) ;
 
while ( IRDY === 0 )
@(posedge pci_clock) ;
 
do_pause(2) ;
# 1 ;
if (!error_monitor_done)
disable monitor_err_event_on_multiple_same_adr_reads_blk ;
end
begin:monitor_err_event_on_multiple_same_adr_reads_blk
error_monitor_done = 0 ;
@(error_event_int) ;
test_fail("either PCI Monitor or PCI Master detected an error while reading through PCI Target Unit") ;
ok = 0 ;
error_monitor_done = 1 ;
end
join
 
// write through the PCI bridge to WB slave
test_name = "NORMAL POSTED WRITE THROUGH PCI TARGET UNIT" ;
$display("Memory write (%d words) through PCI bridge to WB slave!", expect_length_wr);
/trunk/bench/verilog/top.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2004/01/24 11:54:16 mihad
// Update! SPOCI Implemented!
//
// Revision 1.1 2003/12/15 12:21:29 mihad
// Moved top.v to bench directory. Removed unneeded meta_flop,
// modified files list files accordingly.
170,6 → 173,14
`endif
);
 
`ifdef ACTIVE_LOW_OE
parameter oe_act = 1'b0 ;
`endif
 
`ifdef ACTIVE_HIGH_OE
parameter oe_act = 1'b1 ;
`endif
 
input CLK ;
inout [31:0] AD ;
inout [3:0] CBE ;
264,12 → 275,47
wire [31:0] AD_out ;
wire [31:0] AD_en ;
 
wire [31:0] AD_in ;
assign AD_in[0 ] = (AD_en[0 ] == oe_act) ? 1'bx : AD[0 ] ;
assign AD_in[1 ] = (AD_en[1 ] == oe_act) ? 1'bx : AD[1 ] ;
assign AD_in[2 ] = (AD_en[2 ] == oe_act) ? 1'bx : AD[2 ] ;
assign AD_in[3 ] = (AD_en[3 ] == oe_act) ? 1'bx : AD[3 ] ;
assign AD_in[4 ] = (AD_en[4 ] == oe_act) ? 1'bx : AD[4 ] ;
assign AD_in[5 ] = (AD_en[5 ] == oe_act) ? 1'bx : AD[5 ] ;
assign AD_in[6 ] = (AD_en[6 ] == oe_act) ? 1'bx : AD[6 ] ;
assign AD_in[7 ] = (AD_en[7 ] == oe_act) ? 1'bx : AD[7 ] ;
assign AD_in[8 ] = (AD_en[8 ] == oe_act) ? 1'bx : AD[8 ] ;
assign AD_in[9 ] = (AD_en[9 ] == oe_act) ? 1'bx : AD[9 ] ;
assign AD_in[10] = (AD_en[10] == oe_act) ? 1'bx : AD[10] ;
assign AD_in[11] = (AD_en[11] == oe_act) ? 1'bx : AD[11] ;
assign AD_in[12] = (AD_en[12] == oe_act) ? 1'bx : AD[12] ;
assign AD_in[13] = (AD_en[13] == oe_act) ? 1'bx : AD[13] ;
assign AD_in[14] = (AD_en[14] == oe_act) ? 1'bx : AD[14] ;
assign AD_in[15] = (AD_en[15] == oe_act) ? 1'bx : AD[15] ;
assign AD_in[16] = (AD_en[16] == oe_act) ? 1'bx : AD[16] ;
assign AD_in[17] = (AD_en[17] == oe_act) ? 1'bx : AD[17] ;
assign AD_in[18] = (AD_en[18] == oe_act) ? 1'bx : AD[18] ;
assign AD_in[19] = (AD_en[19] == oe_act) ? 1'bx : AD[19] ;
assign AD_in[20] = (AD_en[20] == oe_act) ? 1'bx : AD[20] ;
assign AD_in[21] = (AD_en[21] == oe_act) ? 1'bx : AD[21] ;
assign AD_in[22] = (AD_en[22] == oe_act) ? 1'bx : AD[22] ;
assign AD_in[23] = (AD_en[23] == oe_act) ? 1'bx : AD[23] ;
assign AD_in[24] = (AD_en[24] == oe_act) ? 1'bx : AD[24] ;
assign AD_in[25] = (AD_en[25] == oe_act) ? 1'bx : AD[25] ;
assign AD_in[26] = (AD_en[26] == oe_act) ? 1'bx : AD[26] ;
assign AD_in[27] = (AD_en[27] == oe_act) ? 1'bx : AD[27] ;
assign AD_in[28] = (AD_en[28] == oe_act) ? 1'bx : AD[28] ;
assign AD_in[29] = (AD_en[29] == oe_act) ? 1'bx : AD[29] ;
assign AD_in[30] = (AD_en[30] == oe_act) ? 1'bx : AD[30] ;
assign AD_in[31] = (AD_en[31] == oe_act) ? 1'bx : AD[31] ;
 
wire [31:0] AD_in = AD ;
 
wire [3:0] CBE_in = CBE ;
wire [3:0] CBE_out ;
wire [3:0] CBE_en ;
wire [3:0] CBE_in ;
assign CBE_in[3] = (CBE_en[3] == oe_act) ? 1'bx : CBE[3] ;
assign CBE_in[2] = (CBE_en[2] == oe_act) ? 1'bx : CBE[2] ;
assign CBE_in[1] = (CBE_en[1] == oe_act) ? 1'bx : CBE[1] ;
assign CBE_in[0] = (CBE_en[0] == oe_act) ? 1'bx : CBE[0] ;
 
`ifdef HOST
wire RST_in = 1'bx;
279,40 → 325,40
wire RST_out ;
wire RST_en ;
 
wire INTA_in = INTA ;
wire INTA_en ;
wire INTA_out ;
wire INTA_in = (INTA_en == oe_act) ? 1'bx : INTA ;
 
wire REQ_en ;
wire REQ_out ;
 
wire FRAME_in = FRAME ;
wire FRAME_out ;
wire FRAME_en ;
wire FRAME_in = (FRAME_en == oe_act) ? 1'bx : FRAME ;
 
wire IRDY_in = IRDY ;
wire IRDY_out ;
wire IRDY_en ;
wire IRDY_in = (IRDY_en == oe_act) ? 1'bx : IRDY ;
 
wire DEVSEL_in = DEVSEL ;
wire DEVSEL_out ;
wire DEVSEL_en ;
wire DEVSEL_in = (DEVSEL_en == oe_act) ? 1'bx : DEVSEL ;
 
wire TRDY_in = TRDY ;
wire TRDY_out ;
wire TRDY_en ;
wire TRDY_in = (TRDY_en == oe_act) ? 1'bx : TRDY ;
 
wire STOP_in = STOP ;
wire STOP_out ;
wire STOP_en ;
wire STOP_in = (STOP_en == oe_act) ? 1'bx : STOP ;
 
wire PAR_in = PAR ;
wire PAR_out ;
wire PAR_en ;
wire PAR_in = (PAR_en == oe_act) ? 1'bx : PAR ;
 
wire PERR_in = PERR ;
wire PERR_out ;
wire PERR_en ;
wire PERR_in = (PERR_en == oe_act) ? 1'bx : PERR ;
 
wire SERR_out ;
wire SERR_en ;

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