OpenCores
URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

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  • This comparison shows the changes necessary to convert path 
    /pcie_ds_dma
    from Rev 37 to Rev 38
    ↔ Reverse comparison
  •

Rev 37 → Rev 38

/trunk/core/ds_dma64/pcie_src/components/pcie_core/pcie_core64_wishbone.vhd
167,9 → 167,12
-------------------------------------------------------------------------------
--
-- Declare Global SYS_CON stuff:
signal s_core_clk_out : std_logic;
signal s_reset_out : std_logic;
signal s_dcm_rst_out : std_logic;
signal clk : std_logic;
signal reset : std_logic;
signal dcm_rst : std_logic;
signal reset_p : std_logic;
signal reset_p_z1 : std_logic;
signal reset_p_z2 : std_logic;
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
200,12 → 203,12
pcie_link_up => pcie_link_up,
 
clk_out => s_core_clk_out, -- S6 PCIE x1 module clock output
reset_out => s_reset_out, --
dcm_rstp => s_dcm_rst_out, -- S6 PCIE x1 module INV trn_reset_n_c
clk_out => clk, -- S6 PCIE x1 module clock output
reset_out => reset, --
dcm_rstp => dcm_rst, -- S6 PCIE x1 module INV trn_reset_n_c
---- BAR1 (PB bus) ----
aclk => s_core_clk_out, -- !!! same clock as clk_out
aclk => clk, -- !!! same clock as clk_out
aclk_lock => '1', --
pb_master => pb_master, --
pb_slave => pb_slave, --
239,8 → 242,8
port map
(
---- Global ----
 
 
 
 
 
---- HOST ----
252,7 → 255,13
 
 
);
);
 
 
reset_p <= (not reset) or (not brd_mode(3));
reset_p_z1 <= reset_p after 1 ns when rising_edge( clk );
reset_p_z2 <= reset_p_z1 after 1 ns when rising_edge( clk );
 
-------------------------------------------------------------------------------
--
-- Instantiate PB BUS <-> WB BUS translator module:
260,8 → 269,8
PW_WB : core64_pb_wishbone
port map
(
 
 
 
 
---- BAR1 ----
 
289,8 → 298,17
--
-- Module Output route:
--
o_wb_clk <= s_core_clk_out; -- route from PW_WB wrk clock
o_wb_clk <= clk; -- route from PW_WB wrk clock
--
o_wb_rst <= s_dcm_rst_out; -- convert to POSITIVE LOGIC
 
pr_o_wb_rst: process( reset_p, clk ) begin
if( reset_p='1' ) then
o_wb_rst <= '1' after 1 ns;
elsif( rising_edge( clk ) ) then
o_wb_rst <= reset_p_z2 after 1 ns;
end if;
end process;
 
 
-------------------------------------------------------------------------------
end pcie_core64_wishbone;
/trunk/core/wishbone/coregen_s6/ctrl_fifo1024x64_st_v1.ngc
0,0 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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/trunk/core/wishbone/coregen_s6/ctrl_fifo1024x64_st_v1.xco
0,0 → 1,217
##############################################################
#
# Xilinx Core Generator version 13.2
# Date: Wed Oct 19 12:03:35 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:8.2
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Fifo_Generator xilinx.com:ip:fifo_generator:8.2
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
CSET component_name=ctrl_fifo1024x64_st_v1
CSET data_count=false
CSET data_count_width=10
CSET disable_timing_violations=false
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
CSET empty_threshold_assert_value_axis=1022
CSET empty_threshold_assert_value_rach=1022
CSET empty_threshold_assert_value_rdch=1022
CSET empty_threshold_assert_value_wach=1022
CSET empty_threshold_assert_value_wdch=1022
CSET empty_threshold_assert_value_wrch=1022
CSET empty_threshold_negate_value=3
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_handshake_flag_options_axis=false
CSET enable_handshake_flag_options_rach=false
CSET enable_handshake_flag_options_rdch=false
CSET enable_handshake_flag_options_wach=false
CSET enable_handshake_flag_options_wdch=false
CSET enable_handshake_flag_options_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=false
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=false
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Common_Clock_Block_RAM
CSET fifo_implementation_axis=Common_Clock_Block_RAM
CSET fifo_implementation_rach=Common_Clock_Block_RAM
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=0
CSET full_threshold_assert_value=512
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=511
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=64
CSET input_depth=1024
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=64
CSET output_depth=1024
CSET overflow_flag=false
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=Empty
CSET programmable_empty_type_rach=Empty
CSET programmable_empty_type_rdch=Empty
CSET programmable_empty_type_wach=Empty
CSET programmable_empty_type_wdch=Empty
CSET programmable_empty_type_wrch=Empty
CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
CSET programmable_full_type_axis=Full
CSET programmable_full_type_rach=Full
CSET programmable_full_type_rdch=Full
CSET programmable_full_type_wach=Full
CSET programmable_full_type_wdch=Full
CSET programmable_full_type_wrch=Full
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=10
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET ruser_width=1
CSET tdata_width=64
CSET tdest_width=4
CSET tid_width=8
CSET tkeep_width=4
CSET tstrb_width=4
CSET tuser_width=4
CSET underflow_flag=false
CSET underflow_flag_axi=false
CSET underflow_sense=Active_High
CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=false
CSET valid_sense=Active_High
CSET wach_type=FIFO
CSET wdch_type=FIFO
CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=10
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-03-14T07:12:32.000Z
# END Extra information
GENERATE
# CRC: 738a134d
/trunk/core/wishbone/coregen_s6/ctrl_fifo1024x64_st_v1.vhd
0,0 → 1,3981
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: O.61xd
-- \ \ Application: netgen
-- / / Filename: ctrl_fifo1024x64_st_v1.vhd
-- /___/ /\ Timestamp: Wed Oct 19 15:05:44 2011
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl D:/TMP/08/SVN/00/block_test_generate/tmp/_cg/ctrl_fifo1024x64_st_v1.ngc D:/TMP/08/SVN/00/block_test_generate/tmp/_cg/ctrl_fifo1024x64_st_v1.vhd
-- Device : 6slx45tfgg484-3
-- Input file : D:/TMP/08/SVN/00/block_test_generate/tmp/_cg/ctrl_fifo1024x64_st_v1.ngc
-- Output file : D:/TMP/08/SVN/00/block_test_generate/tmp/_cg/ctrl_fifo1024x64_st_v1.vhd
-- # of Entities : 1
-- Design Name : ctrl_fifo1024x64_st_v1
-- Xilinx : C:\Xilinx\13.2\ISE_DS\ISE\
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
 
 
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
 
entity ctrl_fifo1024x64_st_v1 is
port (
clk : in STD_LOGIC := 'X';
rst : in STD_LOGIC := 'X';
wr_en : in STD_LOGIC := 'X';
rd_en : in STD_LOGIC := 'X';
full : out STD_LOGIC;
empty : out STD_LOGIC;
prog_full : out STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
dout : out STD_LOGIC_VECTOR ( 63 downto 0 )
);
end ctrl_fifo1024x64_st_v1;
 
architecture STRUCTURE of ctrl_fifo1024x64_st_v1 is
signal N0 : STD_LOGIC;
signal N1 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_4 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_6 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i_7 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_tmp_ram_rd_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_184 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_PWR_39_o_MUX_14_o : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp0 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb_GND_294_o_MUX_16_o : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp0 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_192 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_193 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_194 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT41 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT81_232 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT103 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_1_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_2_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_3_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_4_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_5_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_6_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_7_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_8_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_9_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_10_Q_243 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_9_Q_244 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_9_Q_245 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_8_Q_246 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_8_Q_247 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_7_Q_248 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_7_Q_249 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_6_Q_250 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_6_Q_251 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_5_Q_252 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_5_Q_253 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_4_Q_254 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_4_Q_255 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_3_Q_256 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_3_Q_257 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_2_Q_258 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_2_Q_259 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_1_Q_260 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_1_Q_261 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_0_Q_262 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_0_mand1_263 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_1_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_2_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_3_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_4_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_5_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_6_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_7_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_8_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_9_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_10_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_rd_en_i_284 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_wr_en_i_285 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT41 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_1_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_2_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_3_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_4_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_5_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_6_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_7_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_8_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_9_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1_0_inv : STD_LOGIC;
signal N01 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i_rstpot_298 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N6 : STD_LOGIC;
signal N8 : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_5_UNCONNECTED : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg : STD_LOGIC_VECTOR ( 1 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1 : STD_LOGIC_VECTOR ( 9 downto 1 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count : STD_LOGIC_VECTOR ( 9 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1 : STD_LOGIC_VECTOR ( 0 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count : STD_LOGIC_VECTOR ( 9 downto 1 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad : STD_LOGIC_VECTOR ( 10 downto 1 );
begin
full <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_4;
empty <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i_7;
prog_full <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i;
XST_VCC : VCC
port map (
P => N0
);
XST_GND : GND
port map (
G => N1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_PWR_39_o_MUX_14_o,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i_7
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_PWR_39_o_MUX_14_o,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_6
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb_GND_294_o_MUX_16_o,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_4
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb_GND_294_o_MUX_16_o,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_184
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_194,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_193
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_192,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_194
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_194,
D => N1,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_192
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N1,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N1,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg_1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N1,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg_0 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N1,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_carrynet(3),
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp0
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_carrynet(2),
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_carrynet(1),
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_carrynet(0),
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N0,
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_carrynet(3),
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_carrynet(2),
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_carrynet(1),
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_carrynet(0),
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N0,
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_carrynet(3),
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp0
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_carrynet(2),
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_carrynet(1),
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_carrynet(0),
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N0,
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_carrynet(3),
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_carrynet(2),
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_carrynet(1),
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_carrynet(0),
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N0,
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_9 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(9),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(9)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_9_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(9)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_8_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_7_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_6_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_5_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_4_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_3_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_1_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1_0_inv,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_xor_10_Q :
XORCY
port map (
CI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_9_Q_244,
LI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_10_Q_243
,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_10_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_xor_9_Q :
XORCY
port map (
CI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_8_Q_246,
LI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_9_Q_245
,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_9_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_9_Q :
MUXCY
port map (
CI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_8_Q_246,
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(8),
S =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_9_Q_245
,
O =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_9_Q_244
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_xor_8_Q :
XORCY
port map (
CI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_7_Q_248,
LI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_8_Q_247
,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_8_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_8_Q :
MUXCY
port map (
CI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_7_Q_248,
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(7),
S =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_8_Q_247
,
O =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_8_Q_246
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_xor_7_Q :
XORCY
port map (
CI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_6_Q_250,
LI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_7_Q_249
,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_7_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_7_Q :
MUXCY
port map (
CI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_6_Q_250,
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(6),
S =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_7_Q_249
,
O =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_7_Q_248
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_xor_6_Q :
XORCY
port map (
CI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_5_Q_252,
LI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_6_Q_251
,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_6_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_6_Q :
MUXCY
port map (
CI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_5_Q_252,
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(5),
S =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_6_Q_251
,
O =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_6_Q_250
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_xor_5_Q :
XORCY
port map (
CI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_4_Q_254,
LI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_5_Q_253
,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_5_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_5_Q :
MUXCY
port map (
CI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_4_Q_254,
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(4),
S =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_5_Q_253
,
O =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_5_Q_252
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_xor_4_Q :
XORCY
port map (
CI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_3_Q_256,
LI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_4_Q_255
,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_4_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_4_Q :
MUXCY
port map (
CI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_3_Q_256,
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
S =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_4_Q_255
,
O =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_4_Q_254
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_xor_3_Q :
XORCY
port map (
CI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_2_Q_258,
LI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_3_Q_257
,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_3_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_3_Q :
MUXCY
port map (
CI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_2_Q_258,
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
S =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_3_Q_257
,
O =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_3_Q_256
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_xor_2_Q :
XORCY
port map (
CI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_1_Q_260,
LI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_2_Q_259
,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_2_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_2_Q :
MUXCY
port map (
CI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_1_Q_260,
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
S =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_2_Q_259
,
O =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_2_Q_258
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_xor_1_Q :
XORCY
port map (
CI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_0_Q_262,
LI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_1_Q_261
,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_1_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_1_Q :
MUXCY
port map (
CI =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_0_Q_262,
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1(0),
S =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_1_Q_261
,
O =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_1_Q_260
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_0_Q :
MUXCY
port map (
CI => N1,
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_0_mand1_263,
S => N1,
O =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_0_Q_262
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_10 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_10_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(10)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_9 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_9_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(9)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_8 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_8_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_7 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_7_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_6 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_6_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_5 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_5_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_4 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_4_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_3 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_3_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_2 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_1_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_rd_en_i : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_rd_en_i_284
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_wr_en_i : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_wr_en_i_285
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_9 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(9),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(9)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_9_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(9)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_8_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_7_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_6_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_5_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_4_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_3_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_1_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_ram_rd_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_6,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_ram_wr_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_184,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_tmp_ram_rd_en1 : LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_6,
I1 => rd_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0_Q,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_tmp_ram_rd_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_Mmux_ram_full_comb_GND_294_o_MUX_16_o11 : LUT6
generic map(
INIT => X"FA32FAF2F030F0F0"
)
port map (
I0 => wr_en,
I1 => rd_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_184,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_6,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp0,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb_GND_294_o_MUX_16_o
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_Mmux_going_empty_PWR_39_o_MUX_14_o11 : LUT6
generic map(
INIT => X"F3A2FFA2F300FF00"
)
port map (
I0 => rd_en,
I1 => wr_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_184,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_6,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp0,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp1,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_PWR_39_o_MUX_14_o
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_192,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_193,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_4_1 : LUT4
generic map(
INIT => X"8421"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(9),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(8),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(9),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_3_1 : LUT4
generic map(
INIT => X"8421"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(6),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_2_1 : LUT4
generic map(
INIT => X"8421"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(4),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_1_1 : LUT4
generic map(
INIT => X"8421"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_4_1 : LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(9),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(8),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(8),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(9),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_3_1 : LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(6),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_2_1 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_1_1 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_4_1 : LUT4
generic map(
INIT => X"8421"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(9),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(8),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(9),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_3_1 : LUT4
generic map(
INIT => X"8421"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(6),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_2_1 : LUT4
generic map(
INIT => X"8421"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(4),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_1_1 : LUT4
generic map(
INIT => X"8421"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_4_1 : LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(9),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(8),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(8),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(9),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_3_1 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_2_1 : LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(4),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_1_1 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_0_1 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT811 : LUT5
generic map(
INIT => X"FFFF7FFF"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(6),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT41,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT81_232
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT1031 : LUT5
generic map(
INIT => X"00008000"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(6),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT41,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT103
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT71 : LUT5
generic map(
INIT => X"AAAA6AAA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(6),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT41,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_6_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT21 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_1_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT31 : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_2_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT411 : LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT41
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT101 : LUT5
generic map(
INIT => X"EAAA6A2A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(9),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(8),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(7),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT103,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT81_232,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_9_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT71 : LUT5
generic map(
INIT => X"AAAA6AAA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(6),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(4),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT41,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_6_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_9_PWR_45_o_equal_8_o_9_SW0 : LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(8),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(9),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(5),
O => N01
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i_rstpot_298,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_0_1 : LUT4
generic map(
INIT => X"0990"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_0_1 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_0_1 : LUT4
generic map(
INIT => X"0990"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT81 : LUT6
generic map(
INIT => X"AAAAAAAA6AAAAAAA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(6),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(5),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(4),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT41,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_7_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT411 : LUT3
generic map(
INIT => X"F7"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT41
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT91_SW0 : LUT2
generic map(
INIT => X"7"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(6),
O => N2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT91 : LUT6
generic map(
INIT => X"AAAAAAAAAAAA6AAA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(5),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(4),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT41,
I5 => N2,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_8_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT101_SW0 : LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(6),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(8),
O => N4
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT101 : LUT6
generic map(
INIT => X"AAAAAAAAAAAA6AAA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(9),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(5),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(4),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT41,
I5 => N4,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_9_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT81 : LUT6
generic map(
INIT => X"AAAAAAAA6AAAAAAA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(6),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT41,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_7_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_9_PWR_45_o_equal_8_o_9_SW1 : LUT5
generic map(
INIT => X"AAAA8EAA"
)
port map (
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_wr_en_i_285,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_rd_en_i_284,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(10),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(1),
O => N6
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i_rstpot : LUT6
generic map(
INIT => X"AAAAAAABAAAAAAA8"
)
port map (
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i,
I1 => N01,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(7),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(6),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(2),
I5 => N6,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i_rstpot_298
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_2_Q :
LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
O =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_2_Q_259
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_3_Q :
LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
O =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_3_Q_257
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_4_Q :
LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
O =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_4_Q_255
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_5_Q :
LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(4),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
O =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_5_Q_253
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_6_Q :
LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
O =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_6_Q_251
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_7_Q :
LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(6),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
O =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_7_Q_249
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_8_Q :
LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(7),
O =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_8_Q_247
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_9_Q :
LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(8),
O =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_9_Q_245
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_10_Q :
LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(9),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(9),
O =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_10_Q_243
 
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_0_mand1 : LUT4
generic map(
INIT => X"4044"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_184,
I1 => wr_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_6,
I3 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_0_mand1_263
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_1_Q :
LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
O =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_1_Q_261
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT61 : LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_5_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT42 : LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_3_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT51 : LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_4_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT61 : LUT6
generic map(
INIT => X"AAAAAAAA6AAAAAAA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(4),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_5_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT42 : LUT4
generic map(
INIT => X"AA6A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_3_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT51 : LUT5
generic map(
INIT => X"AAAA6AAA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(4),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_4_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT21 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_1_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT31 : LUT3
generic map(
INIT => X"A6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_2_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT91_F : LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(6),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(7),
O => N8
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT11_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1_0_inv
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_wr_pntr_0_inv1_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT911 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT41,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(8),
I2 => N8,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_8_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram :
RAMB16BWER
generic map(
DATA_WIDTH_A => 18,
DATA_WIDTH_B => 18,
DOA_REG => 0,
DOB_REG => 0,
EN_RSTRAM_A => FALSE,
EN_RSTRAM_B => TRUE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RSTTYPE => "SYNC",
RST_PRIORITY_A => "CE",
RST_PRIORITY_B => "CE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST"
)
port map (
REGCEA => N1,
CLKA => clk,
ENB => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_tmp_ram_rd_en,
RSTB => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0_Q,
CLKB => clk,
REGCEB => N1,
RSTA => N1,
ENA => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIPA(3) => N1,
DIPA(2) => N1,
DIPA(1) => din(17),
DIPA(0) => din(8),
WEA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DOA(31) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_31_UNCONNECTED
,
DOA(30) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_30_UNCONNECTED
,
DOA(29) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_29_UNCONNECTED
,
DOA(28) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_28_UNCONNECTED
,
DOA(27) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_27_UNCONNECTED
,
DOA(26) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_26_UNCONNECTED
,
DOA(25) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_25_UNCONNECTED
,
DOA(24) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_24_UNCONNECTED
,
DOA(23) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_23_UNCONNECTED
,
DOA(22) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_22_UNCONNECTED
,
DOA(21) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_21_UNCONNECTED
,
DOA(20) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_20_UNCONNECTED
,
DOA(19) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_19_UNCONNECTED
,
DOA(18) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_18_UNCONNECTED
,
DOA(17) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_17_UNCONNECTED
,
DOA(16) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_16_UNCONNECTED
,
DOA(15) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_15_UNCONNECTED
,
DOA(14) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_14_UNCONNECTED
,
DOA(13) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_13_UNCONNECTED
,
DOA(12) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_12_UNCONNECTED
,
DOA(11) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_11_UNCONNECTED
,
DOA(10) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_10_UNCONNECTED
,
DOA(9) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_9_UNCONNECTED
,
DOA(8) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_8_UNCONNECTED
,
DOA(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_7_UNCONNECTED
,
DOA(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_6_UNCONNECTED
,
DOA(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_5_UNCONNECTED
,
DOA(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_4_UNCONNECTED
,
DOA(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_3_UNCONNECTED
,
DOA(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_2_UNCONNECTED
,
DOA(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_1_UNCONNECTED
,
DOA(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_0_UNCONNECTED
,
ADDRA(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(9),
ADDRA(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(8),
ADDRA(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(7),
ADDRA(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(6),
ADDRA(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(5),
ADDRA(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(4),
ADDRA(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3),
ADDRA(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2),
ADDRA(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1),
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
ADDRA(3) => N1,
ADDRA(2) => N1,
ADDRA(1) => N1,
ADDRA(0) => N1,
ADDRB(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(9),
ADDRB(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(8),
ADDRB(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(7),
ADDRB(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
ADDRB(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
ADDRB(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
ADDRB(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
ADDRB(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
ADDRB(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1_0_inv,
ADDRB(3) => N1,
ADDRB(2) => N1,
ADDRB(1) => N1,
ADDRB(0) => N1,
DIB(31) => N1,
DIB(30) => N1,
DIB(29) => N1,
DIB(28) => N1,
DIB(27) => N1,
DIB(26) => N1,
DIB(25) => N1,
DIB(24) => N1,
DIB(23) => N1,
DIB(22) => N1,
DIB(21) => N1,
DIB(20) => N1,
DIB(19) => N1,
DIB(18) => N1,
DIB(17) => N1,
DIB(16) => N1,
DIB(15) => N1,
DIB(14) => N1,
DIB(13) => N1,
DIB(12) => N1,
DIB(11) => N1,
DIB(10) => N1,
DIB(9) => N1,
DIB(8) => N1,
DIB(7) => N1,
DIB(6) => N1,
DIB(5) => N1,
DIB(4) => N1,
DIB(3) => N1,
DIB(2) => N1,
DIB(1) => N1,
DIB(0) => N1,
DOPA(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_3_UNCONNECTED
,
DOPA(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_2_UNCONNECTED
,
DOPA(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_1_UNCONNECTED
,
DOPA(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_0_UNCONNECTED
,
DIPB(3) => N1,
DIPB(2) => N1,
DIPB(1) => N1,
DIPB(0) => N1,
DOPB(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_3_UNCONNECTED
,
DOPB(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_2_UNCONNECTED
,
DOPB(1) => dout(17),
DOPB(0) => dout(8),
DOB(31) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_31_UNCONNECTED
,
DOB(30) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_30_UNCONNECTED
,
DOB(29) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_29_UNCONNECTED
,
DOB(28) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_28_UNCONNECTED
,
DOB(27) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_27_UNCONNECTED
,
DOB(26) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_26_UNCONNECTED
,
DOB(25) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_25_UNCONNECTED
,
DOB(24) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_24_UNCONNECTED
,
DOB(23) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_23_UNCONNECTED
,
DOB(22) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_22_UNCONNECTED
,
DOB(21) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_21_UNCONNECTED
,
DOB(20) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_20_UNCONNECTED
,
DOB(19) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_19_UNCONNECTED
,
DOB(18) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_18_UNCONNECTED
,
DOB(17) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_17_UNCONNECTED
,
DOB(16) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_16_UNCONNECTED
,
DOB(15) => dout(16),
DOB(14) => dout(15),
DOB(13) => dout(14),
DOB(12) => dout(13),
DOB(11) => dout(12),
DOB(10) => dout(11),
DOB(9) => dout(10),
DOB(8) => dout(9),
DOB(7) => dout(7),
DOB(6) => dout(6),
DOB(5) => dout(5),
DOB(4) => dout(4),
DOB(3) => dout(3),
DOB(2) => dout(2),
DOB(1) => dout(1),
DOB(0) => dout(0),
WEB(3) => N1,
WEB(2) => N1,
WEB(1) => N1,
WEB(0) => N1,
DIA(31) => N1,
DIA(30) => N1,
DIA(29) => N1,
DIA(28) => N1,
DIA(27) => N1,
DIA(26) => N1,
DIA(25) => N1,
DIA(24) => N1,
DIA(23) => N1,
DIA(22) => N1,
DIA(21) => N1,
DIA(20) => N1,
DIA(19) => N1,
DIA(18) => N1,
DIA(17) => N1,
DIA(16) => N1,
DIA(15) => din(16),
DIA(14) => din(15),
DIA(13) => din(14),
DIA(12) => din(13),
DIA(11) => din(12),
DIA(10) => din(11),
DIA(9) => din(10),
DIA(8) => din(9),
DIA(7) => din(7),
DIA(6) => din(6),
DIA(5) => din(5),
DIA(4) => din(4),
DIA(3) => din(3),
DIA(2) => din(2),
DIA(1) => din(1),
DIA(0) => din(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram :
RAMB16BWER
generic map(
DATA_WIDTH_A => 18,
DATA_WIDTH_B => 18,
DOA_REG => 0,
DOB_REG => 0,
EN_RSTRAM_A => FALSE,
EN_RSTRAM_B => TRUE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RSTTYPE => "SYNC",
RST_PRIORITY_A => "CE",
RST_PRIORITY_B => "CE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST"
)
port map (
REGCEA => N1,
CLKA => clk,
ENB => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_tmp_ram_rd_en,
RSTB => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0_Q,
CLKB => clk,
REGCEB => N1,
RSTA => N1,
ENA => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIPA(3) => N1,
DIPA(2) => N1,
DIPA(1) => din(35),
DIPA(0) => din(26),
WEA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DOA(31) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_31_UNCONNECTED
,
DOA(30) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_30_UNCONNECTED
,
DOA(29) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_29_UNCONNECTED
,
DOA(28) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_28_UNCONNECTED
,
DOA(27) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_27_UNCONNECTED
,
DOA(26) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_26_UNCONNECTED
,
DOA(25) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_25_UNCONNECTED
,
DOA(24) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_24_UNCONNECTED
,
DOA(23) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_23_UNCONNECTED
,
DOA(22) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_22_UNCONNECTED
,
DOA(21) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_21_UNCONNECTED
,
DOA(20) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_20_UNCONNECTED
,
DOA(19) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_19_UNCONNECTED
,
DOA(18) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_18_UNCONNECTED
,
DOA(17) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_17_UNCONNECTED
,
DOA(16) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_16_UNCONNECTED
,
DOA(15) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_15_UNCONNECTED
,
DOA(14) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_14_UNCONNECTED
,
DOA(13) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_13_UNCONNECTED
,
DOA(12) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_12_UNCONNECTED
,
DOA(11) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_11_UNCONNECTED
,
DOA(10) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_10_UNCONNECTED
,
DOA(9) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_9_UNCONNECTED
,
DOA(8) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_8_UNCONNECTED
,
DOA(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_7_UNCONNECTED
,
DOA(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_6_UNCONNECTED
,
DOA(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_5_UNCONNECTED
,
DOA(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_4_UNCONNECTED
,
DOA(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_3_UNCONNECTED
,
DOA(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_2_UNCONNECTED
,
DOA(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_1_UNCONNECTED
,
DOA(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_0_UNCONNECTED
,
ADDRA(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(9),
ADDRA(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(8),
ADDRA(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(7),
ADDRA(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(6),
ADDRA(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(5),
ADDRA(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(4),
ADDRA(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3),
ADDRA(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2),
ADDRA(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1),
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
ADDRA(3) => N1,
ADDRA(2) => N1,
ADDRA(1) => N1,
ADDRA(0) => N1,
ADDRB(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(9),
ADDRB(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(8),
ADDRB(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(7),
ADDRB(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
ADDRB(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
ADDRB(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
ADDRB(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
ADDRB(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
ADDRB(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1_0_inv,
ADDRB(3) => N1,
ADDRB(2) => N1,
ADDRB(1) => N1,
ADDRB(0) => N1,
DIB(31) => N1,
DIB(30) => N1,
DIB(29) => N1,
DIB(28) => N1,
DIB(27) => N1,
DIB(26) => N1,
DIB(25) => N1,
DIB(24) => N1,
DIB(23) => N1,
DIB(22) => N1,
DIB(21) => N1,
DIB(20) => N1,
DIB(19) => N1,
DIB(18) => N1,
DIB(17) => N1,
DIB(16) => N1,
DIB(15) => N1,
DIB(14) => N1,
DIB(13) => N1,
DIB(12) => N1,
DIB(11) => N1,
DIB(10) => N1,
DIB(9) => N1,
DIB(8) => N1,
DIB(7) => N1,
DIB(6) => N1,
DIB(5) => N1,
DIB(4) => N1,
DIB(3) => N1,
DIB(2) => N1,
DIB(1) => N1,
DIB(0) => N1,
DOPA(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_3_UNCONNECTED
,
DOPA(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_2_UNCONNECTED
,
DOPA(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_1_UNCONNECTED
,
DOPA(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_0_UNCONNECTED
,
DIPB(3) => N1,
DIPB(2) => N1,
DIPB(1) => N1,
DIPB(0) => N1,
DOPB(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_3_UNCONNECTED
,
DOPB(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_2_UNCONNECTED
,
DOPB(1) => dout(35),
DOPB(0) => dout(26),
DOB(31) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_31_UNCONNECTED
,
DOB(30) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_30_UNCONNECTED
,
DOB(29) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_29_UNCONNECTED
,
DOB(28) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_28_UNCONNECTED
,
DOB(27) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_27_UNCONNECTED
,
DOB(26) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_26_UNCONNECTED
,
DOB(25) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_25_UNCONNECTED
,
DOB(24) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_24_UNCONNECTED
,
DOB(23) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_23_UNCONNECTED
,
DOB(22) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_22_UNCONNECTED
,
DOB(21) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_21_UNCONNECTED
,
DOB(20) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_20_UNCONNECTED
,
DOB(19) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_19_UNCONNECTED
,
DOB(18) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_18_UNCONNECTED
,
DOB(17) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_17_UNCONNECTED
,
DOB(16) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_16_UNCONNECTED
,
DOB(15) => dout(34),
DOB(14) => dout(33),
DOB(13) => dout(32),
DOB(12) => dout(31),
DOB(11) => dout(30),
DOB(10) => dout(29),
DOB(9) => dout(28),
DOB(8) => dout(27),
DOB(7) => dout(25),
DOB(6) => dout(24),
DOB(5) => dout(23),
DOB(4) => dout(22),
DOB(3) => dout(21),
DOB(2) => dout(20),
DOB(1) => dout(19),
DOB(0) => dout(18),
WEB(3) => N1,
WEB(2) => N1,
WEB(1) => N1,
WEB(0) => N1,
DIA(31) => N1,
DIA(30) => N1,
DIA(29) => N1,
DIA(28) => N1,
DIA(27) => N1,
DIA(26) => N1,
DIA(25) => N1,
DIA(24) => N1,
DIA(23) => N1,
DIA(22) => N1,
DIA(21) => N1,
DIA(20) => N1,
DIA(19) => N1,
DIA(18) => N1,
DIA(17) => N1,
DIA(16) => N1,
DIA(15) => din(34),
DIA(14) => din(33),
DIA(13) => din(32),
DIA(12) => din(31),
DIA(11) => din(30),
DIA(10) => din(29),
DIA(9) => din(28),
DIA(8) => din(27),
DIA(7) => din(25),
DIA(6) => din(24),
DIA(5) => din(23),
DIA(4) => din(22),
DIA(3) => din(21),
DIA(2) => din(20),
DIA(1) => din(19),
DIA(0) => din(18)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram :
RAMB16BWER
generic map(
DATA_WIDTH_A => 18,
DATA_WIDTH_B => 18,
DOA_REG => 0,
DOB_REG => 0,
EN_RSTRAM_A => FALSE,
EN_RSTRAM_B => TRUE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RSTTYPE => "SYNC",
RST_PRIORITY_A => "CE",
RST_PRIORITY_B => "CE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST"
)
port map (
REGCEA => N1,
CLKA => clk,
ENB => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_tmp_ram_rd_en,
RSTB => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0_Q,
CLKB => clk,
REGCEB => N1,
RSTA => N1,
ENA => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIPA(3) => N1,
DIPA(2) => N1,
DIPA(1) => din(53),
DIPA(0) => din(44),
WEA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DOA(31) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_31_UNCONNECTED
,
DOA(30) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_30_UNCONNECTED
,
DOA(29) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_29_UNCONNECTED
,
DOA(28) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_28_UNCONNECTED
,
DOA(27) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_27_UNCONNECTED
,
DOA(26) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_26_UNCONNECTED
,
DOA(25) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_25_UNCONNECTED
,
DOA(24) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_24_UNCONNECTED
,
DOA(23) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_23_UNCONNECTED
,
DOA(22) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_22_UNCONNECTED
,
DOA(21) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_21_UNCONNECTED
,
DOA(20) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_20_UNCONNECTED
,
DOA(19) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_19_UNCONNECTED
,
DOA(18) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_18_UNCONNECTED
,
DOA(17) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_17_UNCONNECTED
,
DOA(16) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_16_UNCONNECTED
,
DOA(15) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_15_UNCONNECTED
,
DOA(14) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_14_UNCONNECTED
,
DOA(13) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_13_UNCONNECTED
,
DOA(12) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_12_UNCONNECTED
,
DOA(11) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_11_UNCONNECTED
,
DOA(10) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_10_UNCONNECTED
,
DOA(9) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_9_UNCONNECTED
,
DOA(8) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_8_UNCONNECTED
,
DOA(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_7_UNCONNECTED
,
DOA(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_6_UNCONNECTED
,
DOA(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_5_UNCONNECTED
,
DOA(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_4_UNCONNECTED
,
DOA(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_3_UNCONNECTED
,
DOA(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_2_UNCONNECTED
,
DOA(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_1_UNCONNECTED
,
DOA(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_0_UNCONNECTED
,
ADDRA(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(9),
ADDRA(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(8),
ADDRA(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(7),
ADDRA(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(6),
ADDRA(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(5),
ADDRA(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(4),
ADDRA(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3),
ADDRA(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2),
ADDRA(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1),
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
ADDRA(3) => N1,
ADDRA(2) => N1,
ADDRA(1) => N1,
ADDRA(0) => N1,
ADDRB(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(9),
ADDRB(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(8),
ADDRB(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(7),
ADDRB(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
ADDRB(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
ADDRB(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
ADDRB(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
ADDRB(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
ADDRB(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1_0_inv,
ADDRB(3) => N1,
ADDRB(2) => N1,
ADDRB(1) => N1,
ADDRB(0) => N1,
DIB(31) => N1,
DIB(30) => N1,
DIB(29) => N1,
DIB(28) => N1,
DIB(27) => N1,
DIB(26) => N1,
DIB(25) => N1,
DIB(24) => N1,
DIB(23) => N1,
DIB(22) => N1,
DIB(21) => N1,
DIB(20) => N1,
DIB(19) => N1,
DIB(18) => N1,
DIB(17) => N1,
DIB(16) => N1,
DIB(15) => N1,
DIB(14) => N1,
DIB(13) => N1,
DIB(12) => N1,
DIB(11) => N1,
DIB(10) => N1,
DIB(9) => N1,
DIB(8) => N1,
DIB(7) => N1,
DIB(6) => N1,
DIB(5) => N1,
DIB(4) => N1,
DIB(3) => N1,
DIB(2) => N1,
DIB(1) => N1,
DIB(0) => N1,
DOPA(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_3_UNCONNECTED
,
DOPA(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_2_UNCONNECTED
,
DOPA(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_1_UNCONNECTED
,
DOPA(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_0_UNCONNECTED
,
DIPB(3) => N1,
DIPB(2) => N1,
DIPB(1) => N1,
DIPB(0) => N1,
DOPB(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_3_UNCONNECTED
,
DOPB(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_2_UNCONNECTED
,
DOPB(1) => dout(53),
DOPB(0) => dout(44),
DOB(31) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_31_UNCONNECTED
,
DOB(30) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_30_UNCONNECTED
,
DOB(29) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_29_UNCONNECTED
,
DOB(28) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_28_UNCONNECTED
,
DOB(27) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_27_UNCONNECTED
,
DOB(26) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_26_UNCONNECTED
,
DOB(25) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_25_UNCONNECTED
,
DOB(24) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_24_UNCONNECTED
,
DOB(23) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_23_UNCONNECTED
,
DOB(22) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_22_UNCONNECTED
,
DOB(21) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_21_UNCONNECTED
,
DOB(20) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_20_UNCONNECTED
,
DOB(19) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_19_UNCONNECTED
,
DOB(18) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_18_UNCONNECTED
,
DOB(17) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_17_UNCONNECTED
,
DOB(16) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_16_UNCONNECTED
,
DOB(15) => dout(52),
DOB(14) => dout(51),
DOB(13) => dout(50),
DOB(12) => dout(49),
DOB(11) => dout(48),
DOB(10) => dout(47),
DOB(9) => dout(46),
DOB(8) => dout(45),
DOB(7) => dout(43),
DOB(6) => dout(42),
DOB(5) => dout(41),
DOB(4) => dout(40),
DOB(3) => dout(39),
DOB(2) => dout(38),
DOB(1) => dout(37),
DOB(0) => dout(36),
WEB(3) => N1,
WEB(2) => N1,
WEB(1) => N1,
WEB(0) => N1,
DIA(31) => N1,
DIA(30) => N1,
DIA(29) => N1,
DIA(28) => N1,
DIA(27) => N1,
DIA(26) => N1,
DIA(25) => N1,
DIA(24) => N1,
DIA(23) => N1,
DIA(22) => N1,
DIA(21) => N1,
DIA(20) => N1,
DIA(19) => N1,
DIA(18) => N1,
DIA(17) => N1,
DIA(16) => N1,
DIA(15) => din(52),
DIA(14) => din(51),
DIA(13) => din(50),
DIA(12) => din(49),
DIA(11) => din(48),
DIA(10) => din(47),
DIA(9) => din(46),
DIA(8) => din(45),
DIA(7) => din(43),
DIA(6) => din(42),
DIA(5) => din(41),
DIA(4) => din(40),
DIA(3) => din(39),
DIA(2) => din(38),
DIA(1) => din(37),
DIA(0) => din(36)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram :
RAMB16BWER
generic map(
DATA_WIDTH_A => 18,
DATA_WIDTH_B => 18,
DOA_REG => 0,
DOB_REG => 0,
EN_RSTRAM_A => FALSE,
EN_RSTRAM_B => TRUE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RSTTYPE => "SYNC",
RST_PRIORITY_A => "CE",
RST_PRIORITY_B => "CE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST"
)
port map (
REGCEA => N1,
CLKA => clk,
ENB => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_tmp_ram_rd_en,
RSTB => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0_Q,
CLKB => clk,
REGCEB => N1,
RSTA => N1,
ENA => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIPA(3) => N1,
DIPA(2) => N1,
DIPA(1) => N1,
DIPA(0) => N1,
WEA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DOA(31) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_31_UNCONNECTED
,
DOA(30) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_30_UNCONNECTED
,
DOA(29) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_29_UNCONNECTED
,
DOA(28) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_28_UNCONNECTED
,
DOA(27) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_27_UNCONNECTED
,
DOA(26) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_26_UNCONNECTED
,
DOA(25) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_25_UNCONNECTED
,
DOA(24) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_24_UNCONNECTED
,
DOA(23) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_23_UNCONNECTED
,
DOA(22) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_22_UNCONNECTED
,
DOA(21) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_21_UNCONNECTED
,
DOA(20) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_20_UNCONNECTED
,
DOA(19) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_19_UNCONNECTED
,
DOA(18) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_18_UNCONNECTED
,
DOA(17) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_17_UNCONNECTED
,
DOA(16) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_16_UNCONNECTED
,
DOA(15) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_15_UNCONNECTED
,
DOA(14) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_14_UNCONNECTED
,
DOA(13) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_13_UNCONNECTED
,
DOA(12) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_12_UNCONNECTED
,
DOA(11) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_11_UNCONNECTED
,
DOA(10) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_10_UNCONNECTED
,
DOA(9) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_9_UNCONNECTED
,
DOA(8) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_8_UNCONNECTED
,
DOA(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_7_UNCONNECTED
,
DOA(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_6_UNCONNECTED
,
DOA(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_5_UNCONNECTED
,
DOA(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_4_UNCONNECTED
,
DOA(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_3_UNCONNECTED
,
DOA(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_2_UNCONNECTED
,
DOA(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_1_UNCONNECTED
,
DOA(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_0_UNCONNECTED
,
ADDRA(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(9),
ADDRA(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(8),
ADDRA(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(7),
ADDRA(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(6),
ADDRA(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(5),
ADDRA(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(4),
ADDRA(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3),
ADDRA(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2),
ADDRA(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1),
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
ADDRA(3) => N1,
ADDRA(2) => N1,
ADDRA(1) => N1,
ADDRA(0) => N1,
ADDRB(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(9),
ADDRB(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(8),
ADDRB(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(7),
ADDRB(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
ADDRB(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
ADDRB(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
ADDRB(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
ADDRB(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
ADDRB(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1_0_inv,
ADDRB(3) => N1,
ADDRB(2) => N1,
ADDRB(1) => N1,
ADDRB(0) => N1,
DIB(31) => N1,
DIB(30) => N1,
DIB(29) => N1,
DIB(28) => N1,
DIB(27) => N1,
DIB(26) => N1,
DIB(25) => N1,
DIB(24) => N1,
DIB(23) => N1,
DIB(22) => N1,
DIB(21) => N1,
DIB(20) => N1,
DIB(19) => N1,
DIB(18) => N1,
DIB(17) => N1,
DIB(16) => N1,
DIB(15) => N1,
DIB(14) => N1,
DIB(13) => N1,
DIB(12) => N1,
DIB(11) => N1,
DIB(10) => N1,
DIB(9) => N1,
DIB(8) => N1,
DIB(7) => N1,
DIB(6) => N1,
DIB(5) => N1,
DIB(4) => N1,
DIB(3) => N1,
DIB(2) => N1,
DIB(1) => N1,
DIB(0) => N1,
DOPA(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_3_UNCONNECTED
,
DOPA(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_2_UNCONNECTED
,
DOPA(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_1_UNCONNECTED
,
DOPA(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_0_UNCONNECTED
,
DIPB(3) => N1,
DIPB(2) => N1,
DIPB(1) => N1,
DIPB(0) => N1,
DOPB(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_3_UNCONNECTED
,
DOPB(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_2_UNCONNECTED
,
DOPB(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_1_UNCONNECTED
,
DOPB(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_0_UNCONNECTED
,
DOB(31) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_31_UNCONNECTED
,
DOB(30) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_30_UNCONNECTED
,
DOB(29) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_29_UNCONNECTED
,
DOB(28) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_28_UNCONNECTED
,
DOB(27) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_27_UNCONNECTED
,
DOB(26) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_26_UNCONNECTED
,
DOB(25) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_25_UNCONNECTED
,
DOB(24) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_24_UNCONNECTED
,
DOB(23) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_23_UNCONNECTED
,
DOB(22) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_22_UNCONNECTED
,
DOB(21) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_21_UNCONNECTED
,
DOB(20) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_20_UNCONNECTED
,
DOB(19) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_19_UNCONNECTED
,
DOB(18) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_18_UNCONNECTED
,
DOB(17) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_17_UNCONNECTED
,
DOB(16) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_16_UNCONNECTED
,
DOB(15) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_15_UNCONNECTED
,
DOB(14) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_14_UNCONNECTED
,
DOB(13) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_13_UNCONNECTED
,
DOB(12) => dout(63),
DOB(11) => dout(62),
DOB(10) => dout(61),
DOB(9) => dout(60),
DOB(8) => dout(59),
DOB(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_7_UNCONNECTED
,
DOB(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_6_UNCONNECTED
,
DOB(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_5_UNCONNECTED
,
DOB(4) => dout(58),
DOB(3) => dout(57),
DOB(2) => dout(56),
DOB(1) => dout(55),
DOB(0) => dout(54),
WEB(3) => N1,
WEB(2) => N1,
WEB(1) => N1,
WEB(0) => N1,
DIA(31) => N1,
DIA(30) => N1,
DIA(29) => N1,
DIA(28) => N1,
DIA(27) => N1,
DIA(26) => N1,
DIA(25) => N1,
DIA(24) => N1,
DIA(23) => N1,
DIA(22) => N1,
DIA(21) => N1,
DIA(20) => N1,
DIA(19) => N1,
DIA(18) => N1,
DIA(17) => N1,
DIA(16) => N1,
DIA(15) => N1,
DIA(14) => N1,
DIA(13) => N1,
DIA(12) => din(63),
DIA(11) => din(62),
DIA(10) => din(61),
DIA(9) => din(60),
DIA(8) => din(59),
DIA(7) => N1,
DIA(6) => N1,
DIA(5) => N1,
DIA(4) => din(58),
DIA(3) => din(57),
DIA(2) => din(56),
DIA(1) => din(55),
DIA(0) => din(54)
);
 
end STRUCTURE;
 
-- synthesis translate_on
/trunk/projects/sp605_lx45t_wishbone/projlib.cfg
1,0 → 2,3981
sp605_lx45t_wishbone = "./sp605_lx45t_wishbone.LIB" 1349993755156
sp605_lx45t_wishbone_post_synthesis = "./sp605_lx45t_wishbone_post_synthesis/sp605_lx45t_wishbone_post_synthesis.lib" 1374784385964
/trunk/projects/sp605_lx45t_wishbone/sp605_lx45t_wishbone.LIB
1,101 → 1,101
timestamp=1365787495048
timestamp=1374783157334
 
[$root]
A/$root=22|""|0|1*12128454
BinI32/$root=3*1311556
A/$root=22|""|0|1*18331758
BinI32/$root=3*2143875
Version=9.1.2353.4205 (Windows)|0000004f789cd3cd51282e3033308dcfa930312d892fcf2cce48cacf4b55d04d494a57d0cd51c82fcb8c2fcdcbcc4d4c2eca47e21767e6c278159939997915c9f945a93999490047261c91
 
[axi_basic_rx]
A/trans=A/TRANS 21|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_rx.vhd|125|1*13577240
BinI32/trans=3*1430226
A/trans=A/TRANS 21|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_rx.vhd|125|1*16722021
BinI32/trans=3*1938256
I=0*843728
I/trans=I/TRANS 0*1379929
M=11|0|v98|1359756166406|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_rx.vhd|0*842333*0xcd2a447635e3486a8895205b0a79e3206d2f3535|0*843604*0xab32bc1a2daf049573e14469f634e0e6
M/trans=M/TRANS 21|0|v98|1359756590098|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_rx.vhd|0*843903*0x7daf6f14fd5a1f7987b52d23c79e54a2479a3a7f|0*848390*0x9883a4debb77c3d3c4860cd1e2edf83c
M/trans=M/TRANS 21|0|v98|1374782083383|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_rx.vhd|0*843903*0x7daf6f14fd5a1f7987b52d23c79e54a2479a3a7f|0*848390*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_rx.vhd|72
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/trans=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[axi_basic_rx_null_gen]
A/trans=A/TRANS 21|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_rx_null_gen.vhd|107|1*13595159
BinI32/trans=3*1431921
A/trans=A/TRANS 21|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_rx_null_gen.vhd|107|1*16739940
BinI32/trans=3*1939951
I=0*850333
I/trans=I/TRANS 0*856800
M=11|0|v98|1359756166468|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_rx_null_gen.vhd|0*849329*0x46fe0ea241645d39bd491474b81135f6ea79e4dd|0*850191*0xab32bc1a2daf049573e14469f634e0e6
M/trans=M/TRANS 21|0|v98|1359756590161|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_rx_null_gen.vhd|0*850517*0xf43fe08885b85aeb7826f3577cd6cc68cb1a0f75|0*856649*0x9883a4debb77c3d3c4860cd1e2edf83c
M/trans=M/TRANS 21|0|v98|1374782083490|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_rx_null_gen.vhd|0*850517*0xf43fe08885b85aeb7826f3577cd6cc68cb1a0f75|0*856649*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_rx_null_gen.vhd|71
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/trans=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[axi_basic_rx_pipeline]
A/trans=21|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_rx_pipeline.vhd|123|1*13606784
BinI32/trans=3*1440578
A/trans=21|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_rx_pipeline.vhd|123|1*16751565
BinI32/trans=3*1948596
I=0*859637
I/trans=0*869707
M=11|0|v98|1359756166578|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_rx_pipeline.vhd|0*858146*0xc4704507977aa02119ab37768df4565f265dd438|0*859495*0xab32bc1a2daf049573e14469f634e0e6
M/trans=21|0|v98|1359756590237|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_rx_pipeline.vhd|0*859821*0x38d9a04868c6f689657134204dcf3208056ed4d3|0*869556*0x9883a4debb77c3d3c4860cd1e2edf83c
M/trans=21|0|v98|1374782083631|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_rx_pipeline.vhd|0*859821*0x38d9a04868c6f689657134204dcf3208056ed4d3|0*869556*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_rx_pipeline.vhd|74
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/trans=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[axi_basic_top]
A/trans=21|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_top.vhd|174|1*13625594
BinI32/trans=3*1452545
A/trans=21|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_top.vhd|174|1*16770375
BinI32/trans=3*1960572
I=0*875039
I/trans=0*1380246
M=11|0|v98|1359756166687|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_top.vhd|0*872429*0x9266e11d27aa88333e43c309f3ee0f49b1dbb34e|0*874913*0xab32bc1a2daf049573e14469f634e0e6
M/trans=21|0|v98|1359756590301|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_top.vhd|0*875215*0xead1851a22ea179e68119a0a7f2d82f5a227d034|0*880016*0x9883a4debb77c3d3c4860cd1e2edf83c
M/trans=21|0|v98|1374782083740|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_top.vhd|0*875215*0xead1851a22ea179e68119a0a7f2d82f5a227d034|0*880016*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_top.vhd|71
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/trans=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[axi_basic_tx]
A/trans=21|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_tx.vhd|152|1*13648439
BinI32/trans=3*1454078
A/trans=21|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_tx.vhd|152|1*16793220
BinI32/trans=3*1962105
I=0*883361
I/trans=0*1380546
M=11|0|v98|1359756166750|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_tx.vhd|0*881632*0xb3463c904453e97f94b58d81fb6d8fd169be2dd2|0*883237*0xab32bc1a2daf049573e14469f634e0e6
M/trans=21|0|v98|1359756590348|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_tx.vhd|0*883536*0x6d3663ed65819e52b058db77e41d66ef6ced9fe8|0*888512*0x9883a4debb77c3d3c4860cd1e2edf83c
M/trans=21|0|v98|1374782083820|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_tx.vhd|0*883536*0x6d3663ed65819e52b058db77e41d66ef6ced9fe8|0*888512*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_tx.vhd|74
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/trans=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[axi_basic_tx_pipeline]
A/trans=21|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_tx_pipeline.vhd|124|1*13669156
BinI32/trans=3*1455502
A/trans=21|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_tx_pipeline.vhd|124|1*16813937
BinI32/trans=3*1963529
I=0*891251
I/trans=0*898741
M=11|0|v98|1359756167031|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_tx_pipeline.vhd|0*889872*0x349875a94bee33b6608127c22d1b4e0ed4ce813b|0*891109*0xab32bc1a2daf049573e14469f634e0e6
M/trans=21|0|v98|1359756590411|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_tx_pipeline.vhd|0*891435*0x34f8515c33b6fa40a17824c3d3d6b9e8f8b17758|0*898590*0x9883a4debb77c3d3c4860cd1e2edf83c
M/trans=21|0|v98|1374782083927|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_tx_pipeline.vhd|0*891435*0x34f8515c33b6fa40a17824c3d3d6b9e8f8b17758|0*898590*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_tx_pipeline.vhd|74
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/trans=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[axi_basic_tx_thrtl_ctl]
A/trans=21|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_tx_thrtl_ctl.vhd|129|1*13683171
BinI32/trans=3*1464329
A/trans=21|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_tx_thrtl_ctl.vhd|129|1*16827952
BinI32/trans=3*1972355
I=0*901521
I/trans=0*914464
M=11|0|v98|1359756167125|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_tx_thrtl_ctl.vhd|0*900070*0x1a435a7f654232096ee6206c1c4b1a2b8099a9de|0*901377*0xab32bc1a2daf049573e14469f634e0e6
M/trans=21|0|v98|1359756590487|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_tx_thrtl_ctl.vhd|0*901706*0xcec4f2d4a3fad0035fb15e88045b424ef66f48d7|0*914311*0x9883a4debb77c3d3c4860cd1e2edf83c
M/trans=21|0|v98|1374782084081|./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_tx_thrtl_ctl.vhd|0*901706*0xcec4f2d4a3fad0035fb15e88045b424ef66f48d7|0*914311*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_virtex6/axi_basic_tx_thrtl_ctl.vhd|74
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/trans=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[block_check_wb_burst_slave]
A/block_check_wb_burst_slave=22|./src/wishbone/block_test_check/block_check_wb_burst_slave.v|27|1*12026323
BinI32/block_check_wb_burst_slave=3*1282307
P/~emb=967,1435,1960,2171
A/block_check_wb_burst_slave=22|./src/wishbone/block_test_check/block_check_wb_burst_slave.v|27|1*18226370
BinI32/block_check_wb_burst_slave=3*2113261
P/~emb=967,1453,2006,2219
R=./src/wishbone/block_test_check/block_check_wb_burst_slave.v|27
Version=9.1.2353.4205 (Windows)|0000004f789cd3cd51282e3033308dcfa930312d892fcf2cce48cacf4b55d04d494a57d0cd51c82fcb8c2fcdcbcc4d4c2eca47e21767e6c278159939997915c9f945a93999490047261c91
 
[block_check_wb_config_slave]
A/rtl=21|./src/wishbone/block_test_check/block_check_wb_config_slave.vhd|161|1*12030624
BinI32/rtl=3*1284150
A/rtl=21|./src/wishbone/block_test_check/block_check_wb_config_slave.vhd|161|1*18230916
BinI32/rtl=3*2115273
I=0*2035884
I/rtl=0*2039783
M=11|0|v98|1359756271781|./src/wishbone/block_test_check/block_check_wb_config_slave.vhd|0*2034225*0x4f17d8501a7f2daa2bd4dbbb98470ca9310bf38f|0*2035743*0xab32bc1a2daf049573e14469f634e0e6
M/rtl=21|0|v98|1359756296609|./src/wishbone/block_test_check/block_check_wb_config_slave.vhd|0*2036258*0xb9adf4e858a043af501b902ffc311996b39fdc76|0*2039635*0x9883a4debb77c3d3c4860cd1e2edf83c
M/rtl=21|0|v98|1374782097702|./src/wishbone/block_test_check/block_check_wb_config_slave.vhd|0*2036258*0xb9adf4e858a043af501b902ffc311996b39fdc76|0*2039635*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/wishbone/block_test_check/block_check_wb_config_slave.vhd|117
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/rtl=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
115,28 → 115,28
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[block_generate_wb_burst_slave]
A/block_generate_wb_burst_slave=22|./src/wishbone/block_test_generate/block_generate_wb_burst_slave.v|27|1*12080513
BinI32/block_generate_wb_burst_slave=3*1297398
A/block_generate_wb_burst_slave=22|./src/wishbone/block_test_generate/block_generate_wb_burst_slave.v|27|1*18280805
BinI32/block_generate_wb_burst_slave=3*2128521
P/~emb=1194,1716,2432,2715
R=./src/wishbone/block_test_generate/block_generate_wb_burst_slave.v|27
Version=9.1.2353.4205 (Windows)|0000004f789cd3cd51282e3033308dcfa930312d892fcf2cce48cacf4b55d04d494a57d0cd51c82fcb8c2fcdcbcc4d4c2eca47e21767e6c278159939997915c9f945a93999490047261c91
 
[block_generate_wb_config_slave]
A/rtl=21|./src/wishbone/block_test_generate/block_generate_wb_config_slave.vhd|147|1*12085597
BinI32/rtl=3*1301094
I=0*2001232
I/rtl=0*2004845
M=11|0|v98|1359756265237|./src/wishbone/block_test_generate/block_generate_wb_config_slave.vhd|0*1999771*0x8a6b8f888267bd6891995682d52f69b60bd6b936|0*2001082*0xab32bc1a2daf049573e14469f634e0e6
M/rtl=21|0|v98|1359756298798|./src/wishbone/block_test_generate/block_generate_wb_config_slave.vhd|0*2001609*0x1c7537749cda06d1445231bf3f48bb0ddcf8aa48|0*2004688*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/wishbone/block_test_generate/block_generate_wb_config_slave.vhd|108
A/rtl=21|./src/wishbone/block_test_generate/block_generate_wb_config_slave.vhd|151|1*18285889
BinI32/rtl=3*2132192
I=0*2670516
I/rtl=0*2674445
M=11|0|v98|1374782051885|./src/wishbone/block_test_generate/block_generate_wb_config_slave.vhd|0*2669005*0x533a690fc092d012f58c6d4a460dd3073dffaebc|0*2670366*0xab32bc1a2daf049573e14469f634e0e6
M/rtl=21|0|v98|1374782099948|./src/wishbone/block_test_generate/block_generate_wb_config_slave.vhd|0*2670893*0xb1467e27a167133d9b4bf7c74908ea8c0c8502f1|0*2674288*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/wishbone/block_test_generate/block_generate_wb_config_slave.vhd|111
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/rtl=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[block_generate_wb_config_slave_pkg]
E=1*8183812
I=0*1998661
M=3|0|v98|1359756265234|./src/wishbone/block_test_generate/block_generate_wb_config_slave.vhd|0*1997238*0x476fbd953b0dc61facee3ae085944a99af5a635f|0*1998507*0xab32bc1a2daf049573e14469f634e0e6
R=./src/wishbone/block_test_generate/block_generate_wb_config_slave.vhd|56
E=1*15464342
I=0*2667847
M=3|0|v98|1374782051882|./src/wishbone/block_test_generate/block_generate_wb_config_slave.vhd|0*2666374*0xd98f243cec3b009c041760e0bc7969c7c93d4b1e|0*2667693*0xab32bc1a2daf049573e14469f634e0e6
R=./src/wishbone/block_test_generate/block_generate_wb_config_slave.vhd|58
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[block_generate_wb_pkg]
147,12 → 147,12
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[block_pe_fifo_ext]
A/block_pe_fifo_ext=21|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/block_pe_fifo_ext.vhd|162|1*9099042
BinI32/block_pe_fifo_ext=3*954077
A/block_pe_fifo_ext=21|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/block_pe_fifo_ext.vhd|162|1*16246525
BinI32/block_pe_fifo_ext=3*1917212
I=0*730712
I/block_pe_fifo_ext=0*740922
M=11|0|v98|1359756145000|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/block_pe_fifo_ext.vhd|0*729618*0x82c23e8f1a324f79f6019798fc22a1bc9c1c30dc|0*730579*0xab32bc1a2daf049573e14469f634e0e6
M/block_pe_fifo_ext=21|0|v98|1359756285628|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/block_pe_fifo_ext.vhd|0*731342*0x42024242f96a82f3a629cc25e43c41d9ed910217|0*740768*0x9883a4debb77c3d3c4860cd1e2edf83c
M/block_pe_fifo_ext=21|0|v98|1374782081990|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/block_pe_fifo_ext.vhd|0*731342*0x42024242f96a82f3a629cc25e43c41d9ed910217|0*740768*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/block_pe_fifo_ext.vhd|128
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/block_pe_fifo_ext=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
193,12 → 193,12
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[block_test_check_wb]
A/rtl=21|./src/wishbone/block_test_check/block_test_check_wb.vhd|123|1*12056631
BinI32/rtl=3*1296747
A/rtl=21|./src/wishbone/block_test_check/block_test_check_wb.vhd|123|1*18256923
BinI32/rtl=3*2127870
I=0*2055979
I/rtl=0*2059522
I/rtl=0*2659559
M=11|0|v98|1359756272268|./src/wishbone/block_test_check/block_test_check_wb.vhd|0*2054488*0xaa6922090b87a72d5358ea4d2302b5f2d5c6007d|0*2055854*0xab32bc1a2daf049573e14469f634e0e6
M/rtl=21|0|v98|1359756297065|./src/wishbone/block_test_check/block_test_check_wb.vhd|0*2056300*0xe583a09eba9c303111170f5bcb08495f511de93d|0*2059390*0x9883a4debb77c3d3c4860cd1e2edf83c
M/rtl=21|0|v98|1374782098186|./src/wishbone/block_test_check/block_test_check_wb.vhd|0*2656337*0x4a61b7fab7109d7016cc9967a5970adb09932730|0*2659427*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/wishbone/block_test_check/block_test_check_wb.vhd|80
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/rtl=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
211,12 → 211,12
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[block_test_generate_wb]
A/rtl=21|./src/wishbone/block_test_generate/block_test_generate_wb.vhd|122|1*12104319
BinI32/rtl=3*1310885
A/rtl=21|./src/wishbone/block_test_generate/block_test_generate_wb.vhd|122|1*18305098
BinI32/rtl=3*2142245
I=0*2020417
I/rtl=0*2024211
M=11|0|v98|1359756265862|./src/wishbone/block_test_generate/block_test_generate_wb.vhd|0*2018893*0xc460794027a5a06f0bbe5d9f4d19a70809ca7afb|0*2020283*0xab32bc1a2daf049573e14469f634e0e6
M/rtl=21|0|v98|1359756299253|./src/wishbone/block_test_generate/block_test_generate_wb.vhd|0*2020750*0x658bb2c039479ca3db942e423f823a4b0db8d702|0*2024070*0x9883a4debb77c3d3c4860cd1e2edf83c
I/rtl=0*2679203
M=11|0|v98|1374782052399|./src/wishbone/block_test_generate/block_test_generate_wb.vhd|0*2018893*0xc460794027a5a06f0bbe5d9f4d19a70809ca7afb|0*2020283*0xab32bc1a2daf049573e14469f634e0e6
M/rtl=21|0|v98|1374782100445|./src/wishbone/block_test_generate/block_test_generate_wb.vhd|0*2674886*0x7913e6aefceb6dae303f49487aedc3b1ce1fc17c|0*2679062*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/wishbone/block_test_generate/block_test_generate_wb.vhd|79
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/rtl=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
229,23 → 229,23
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[cl_s6pcie_m2]
A/rtl=21|./src/pcie_src/pcie_core64_m1/source_s6/cl_s6pcie_m2.vhd|246|1*13201985
BinI32/rtl=3*1413265
A/rtl=21|./src/pcie_src/pcie_core64_m1/source_s6/cl_s6pcie_m2.vhd|246|1*16346766
BinI32/rtl=3*1921311
I=0*755160
I/rtl=0*839795
M=11|0|v98|1359756150265|./src/pcie_src/pcie_core64_m1/source_s6/cl_s6pcie_m2.vhd|0*747822*0xbf21c3481fa762084b2f71de8c15de30a2713488|0*755041*0xab32bc1a2daf049573e14469f634e0e6
M/rtl=21|0|v98|1359756572924|./src/pcie_src/pcie_core64_m1/source_s6/cl_s6pcie_m2.vhd|0*755580*0x39bab5386e1bb45828eb535dcef2d49f38264dc9|0*785545*0x9883a4debb77c3d3c4860cd1e2edf83c
M/rtl=21|0|v98|1374782082320|./src/pcie_src/pcie_core64_m1/source_s6/cl_s6pcie_m2.vhd|0*755580*0x39bab5386e1bb45828eb535dcef2d49f38264dc9|0*785545*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_s6/cl_s6pcie_m2.vhd|69
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/rtl=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[cl_test_check]
A/cl_test_check=21|./src/wishbone/block_test_check/cl_test_check.vhd|142|1*12041651
BinI32/cl_test_check=3*1288162
A/cl_test_check=21|./src/wishbone/block_test_check/cl_test_check.vhd|142|1*18241943
BinI32/cl_test_check=3*2119285
I=0*2042965
I/cl_test_check=0*2051218
M=11|0|v98|1359756272171|./src/wishbone/block_test_check/cl_test_check.vhd|0*2042018*0x43e5e7abeb77024cb8983019f888157ca54adc9f|0*2042852*0xab32bc1a2daf049573e14469f634e0e6
M/cl_test_check=21|0|v98|1359756296846|./src/wishbone/block_test_check/cl_test_check.vhd|0*2043269*0x56f0fd1f247718e5d3a3efba35d2c58e3eae38e2|0*2051088*0x9883a4debb77c3d3c4860cd1e2edf83c
M/cl_test_check=21|0|v98|1374782097952|./src/wishbone/block_test_check/cl_test_check.vhd|0*2043269*0x56f0fd1f247718e5d3a3efba35d2c58e3eae38e2|0*2051088*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/wishbone/block_test_check/cl_test_check.vhd|115
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/cl_test_check=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
258,12 → 258,12
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[cl_test_generate]
A/cl_test_generate=21|./src/wishbone/block_test_generate/cl_test_generate.vhd|145|1*12095687
BinI32/cl_test_generate=3*1304291
A/cl_test_generate=21|./src/wishbone/block_test_generate/cl_test_generate.vhd|145|1*18296466
BinI32/cl_test_generate=3*2135658
I=0*2009687
I/cl_test_generate=0*2015619
M=11|0|v98|1359756265796|./src/wishbone/block_test_generate/cl_test_generate.vhd|0*2008794*0xb9dc657fcef7a24698822d78940b9bdc3accf92f|0*2009565*0xab32bc1a2daf049573e14469f634e0e6
M/cl_test_generate=21|0|v98|1359756299034|./src/wishbone/block_test_generate/cl_test_generate.vhd|0*2009994*0x8c41c84c3c7abb34f5fa2e89f0990225aefc4e45|0*2015477*0x9883a4debb77c3d3c4860cd1e2edf83c
M/cl_test_generate=21|0|v98|1374782100182|./src/wishbone/block_test_generate/cl_test_generate.vhd|0*2009994*0x8c41c84c3c7abb34f5fa2e89f0990225aefc4e45|0*2015477*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/wishbone/block_test_generate/cl_test_generate.vhd|119
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/cl_test_generate=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
276,23 → 276,23
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[cl_v6pcie_m1]
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/cl_v6pcie_m1.vhd|499|1*13705098
BinI32/v6_pcie=3*1477819
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/cl_v6pcie_m1.vhd|499|1*16849879
BinI32/v6_pcie=3*1985837
I=0*943317
I/v6_pcie=0*1380864
M=11|0|v98|1359756167406|./src/pcie_src/pcie_core64_m1/source_virtex6/cl_v6pcie_m1.vhd|0*927636*0x58a6e8bc35469fff937a15fe370ad9aac226def2|0*943193*0xab32bc1a2daf049573e14469f634e0e6
M/v6_pcie=21|0|v98|1359756590765|./src/pcie_src/pcie_core64_m1/source_virtex6/cl_v6pcie_m1.vhd|0*943555*0x9055bcf6436aa3b0cb9d9866023e27ebabbae7ec|0*994737*0x9883a4debb77c3d3c4860cd1e2edf83c
M/v6_pcie=21|0|v98|1374782084376|./src/pcie_src/pcie_core64_m1/source_virtex6/cl_v6pcie_m1.vhd|0*943555*0x9055bcf6436aa3b0cb9d9866023e27ebabbae7ec|0*994737*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_virtex6/cl_v6pcie_m1.vhd|66
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/v6_pcie=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[cl_v6pcie_x4]
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/cl_v6pcie_x4.vhd|470|1*13894230
BinI32/v6_pcie=3*1494243
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/cl_v6pcie_x4.vhd|470|1*17039011
BinI32/v6_pcie=3*2002259
I=0*1022947
I/v6_pcie=0*1381413
M=11|0|v98|1359756167718|./src/pcie_src/pcie_core64_m1/source_virtex6/cl_v6pcie_x4.vhd|0*1007541*0x82be36d6c8fd561e054459403dd7abfb15df5eb4|0*1022823*0xab32bc1a2daf049573e14469f634e0e6
M/v6_pcie=21|0|v98|1359756591048|./src/pcie_src/pcie_core64_m1/source_virtex6/cl_v6pcie_x4.vhd|0*1023185*0x1b1e9b4e5c26ae2d1988d91c04633d43a86ade4b|0*1075676*0x9883a4debb77c3d3c4860cd1e2edf83c
M/v6_pcie=21|0|v98|1374782084691|./src/pcie_src/pcie_core64_m1/source_virtex6/cl_v6pcie_x4.vhd|0*1023185*0x1b1e9b4e5c26ae2d1988d91c04633d43a86ade4b|0*1075676*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_virtex6/cl_v6pcie_x4.vhd|66
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/v6_pcie=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
308,12 → 308,12
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[core64_interrupt]
A/core64_interrupt=21|./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_interrupt.vhd|63|1*8763877
BinI32/core64_interrupt=3*889386
A/core64_interrupt=21|./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_interrupt.vhd|63|1*15910881
BinI32/core64_interrupt=3*1852345
I=0*398454
I/core64_interrupt=0*400102
M=11|0|v98|1359756119862|./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_interrupt.vhd|0*397837*0x46d1859556b1e61c96314bd5989e816acf913137|0*398327*0xab32bc1a2daf049573e14469f634e0e6
M/core64_interrupt=21|0|v98|1359756283321|./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_interrupt.vhd|0*398698*0xf172794e985f36cf7506519bb9b4dc4ea28745d4|0*399955*0x9883a4debb77c3d3c4860cd1e2edf83c
M/core64_interrupt=21|0|v98|1374782079315|./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_interrupt.vhd|0*398698*0xf172794e985f36cf7506519bb9b4dc4ea28745d4|0*399955*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_interrupt.vhd|46
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/core64_interrupt=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
326,13 → 326,13
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[core64_pb_disp]
A/core64_pb_disp=21|./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_pb_disp.vhd|93|1*8766219
BinI32/core64_pb_disp=3*891018
I=0*402549
I/core64_pb_disp=0*407956
M=11|0|v98|1359756120187|./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_pb_disp.vhd|0*401849*0xf4ecf942f07ed9fcf2a9fe322682e65c51643094|0*402426*0xab32bc1a2daf049573e14469f634e0e6
M/core64_pb_disp=21|0|v98|1359756283546|./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_pb_disp.vhd|0*402783*0x724602bf0ea31ccd5026f1f60b876f069fc6fe9a|0*407815*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_pb_disp.vhd|69
A/core64_pb_disp=21|./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_pb_disp.vhd|95|1*15913223
BinI32/core64_pb_disp=3*1853977
I=0*2875009
I/core64_pb_disp=0*2880835
M=11|0|v98|1374782079525|./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_pb_disp.vhd|0*2874246*0xb48833ae0b2284e350af62a5e87b7a55f6e2f32e|0*2874886*0xab32bc1a2daf049573e14469f634e0e6
M/core64_pb_disp=21|0|v98|1374782079572|./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_pb_disp.vhd|0*2875376*0x491d24c5b075dd55b94acf44a8ef83301ad1e169|0*2880694*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_pb_disp.vhd|71
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/core64_pb_disp=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
386,12 → 386,12
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[core64_reg_access]
A/core64_reg_access=21|./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_reg_access.vhd|102|1*8779104
BinI32/core64_reg_access=3*895844
A/core64_reg_access=21|./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_reg_access.vhd|102|1*15926690
BinI32/core64_reg_access=3*1859111
I=0*411364
I/core64_reg_access=0*415577
M=11|0|v98|1359756120265|./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_reg_access.vhd|0*410385*0x0dc4c6904f76b406c99f86c752e762debb601971|0*411235*0xab32bc1a2daf049573e14469f634e0e6
M/core64_reg_access=21|0|v98|1359756283600|./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_reg_access.vhd|0*411538*0x949ccf36ab8470874477a502cc4b9b4aa42cfc76|0*415427*0x9883a4debb77c3d3c4860cd1e2edf83c
M/core64_reg_access=21|0|v98|1374782079641|./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_reg_access.vhd|0*411538*0x949ccf36ab8470874477a502cc4b9b4aa42cfc76|0*415427*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_reg_access.vhd|66
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/core64_reg_access=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
404,12 → 404,12
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[core64_rx_engine_m4]
A/core64_rx_engine_m4=21|./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_rx_engine_m4.vhd|84|1*8789763
BinI32/core64_rx_engine_m4=3*900010
A/core64_rx_engine_m4=21|./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_rx_engine_m4.vhd|84|1*15937349
BinI32/core64_rx_engine_m4=3*1863273
I=0*417976
I/core64_rx_engine_m4=0*661313
M=11|0|v98|1359756120750|./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_rx_engine_m4.vhd|0*417259*0xf8484e213c639362b00453bae3204744c229180f|0*417843*0xab32bc1a2daf049573e14469f634e0e6
M/core64_rx_engine_m4=21|0|v98|1359756283690|./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_rx_engine_m4.vhd|0*418285*0x23c6b80ecb7dcbeb284e5350e2963abb99601168|0*427218*0x9883a4debb77c3d3c4860cd1e2edf83c
M/core64_rx_engine_m4=21|0|v98|1374782079777|./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_rx_engine_m4.vhd|0*418285*0x23c6b80ecb7dcbeb284e5350e2963abb99601168|0*427218*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_rx_engine_m4.vhd|61
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/core64_rx_engine_m4=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
422,12 → 422,12
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[core64_tx_engine_m4]
A/core64_tx_engine_m4=21|./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_tx_engine_m4.vhd|91|1*15332937
BinI32/core64_tx_engine_m4=3*1734685
A/core64_tx_engine_m4=21|./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_tx_engine_m4.vhd|91|1*15959353
BinI32/core64_tx_engine_m4=3*1871518
I=0*430006
I/core64_tx_engine_m4=0*2597329
M=11|0|v98|1359756121000|./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_tx_engine_m4.vhd|0*429149*0xb05569856eb984e7035f879120bd48c13a9fad3d|0*429873*0xab32bc1a2daf049573e14469f634e0e6
M/core64_tx_engine_m4=21|0|v98|1365787494894|./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_tx_engine_m4.vhd|0*2585747*0x07860b5a89f97ca31674785ce71247c8ad3be79a|0*2597173*0x9883a4debb77c3d3c4860cd1e2edf83c
M/core64_tx_engine_m4=21|0|v98|1374782080057|./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_tx_engine_m4.vhd|0*2585747*0x07860b5a89f97ca31674785ce71247c8ad3be79a|0*2597173*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/pcie_ctrl/core64_tx_engine_m4.vhd|64
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/core64_tx_engine_m4=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
447,12 → 447,12
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[ctrl_dma_adr]
A/ctrl_dma_adr=21|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_dma_adr.vhd|102|1*8836190
BinI32/ctrl_dma_adr=3*920112
A/ctrl_dma_adr=21|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_dma_adr.vhd|102|1*15983673
BinI32/ctrl_dma_adr=3*1883250
I=0*664593
I/ctrl_dma_adr=0*668855
M=11|0|v98|1359756143346|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_dma_adr.vhd|0*663798*0x2b3c38b1c4d395856bcb17926ed7ce23c06c29e0|0*664470*0xab32bc1a2daf049573e14469f634e0e6
M/ctrl_dma_adr=21|0|v98|1359756284159|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_dma_adr.vhd|0*664896*0x10968717f06221075fe1f29b59f5dff571e62b8f|0*668716*0x9883a4debb77c3d3c4860cd1e2edf83c
M/ctrl_dma_adr=21|0|v98|1374782080323|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_dma_adr.vhd|0*664896*0x10968717f06221075fe1f29b59f5dff571e62b8f|0*668716*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_dma_adr.vhd|75
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/ctrl_dma_adr=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
465,12 → 465,12
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[ctrl_dma_ext_cmd]
A/ctrl_dma_ext_cmd=21|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_dma_ext_cmd.vhd|136|1*8858178
BinI32/ctrl_dma_ext_cmd=3*922626
A/ctrl_dma_ext_cmd=21|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_dma_ext_cmd.vhd|136|1*16005661
BinI32/ctrl_dma_ext_cmd=3*1885768
I=0*672452
I/ctrl_dma_ext_cmd=0*674856
M=11|0|v98|1359756143625|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_dma_ext_cmd.vhd|0*671383*0xb6d2a64ca625afb8894447c6c007219c2ee95a28|0*672321*0xab32bc1a2daf049573e14469f634e0e6
M/ctrl_dma_ext_cmd=21|0|v98|1359756284364|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_dma_ext_cmd.vhd|0*672821*0xd21e60de856347d44b34fef51edad012a23079dd|0*674705*0x9883a4debb77c3d3c4860cd1e2edf83c
M/ctrl_dma_ext_cmd=21|0|v98|1374782080559|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_dma_ext_cmd.vhd|0*672821*0xd21e60de856347d44b34fef51edad012a23079dd|0*674705*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_dma_ext_cmd.vhd|91
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/ctrl_dma_ext_cmd=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
483,12 → 483,12
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[ctrl_ext_descriptor]
A/ctrl_ext_descriptor=21|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ext_descriptor.vhd|166|1*8867473
BinI32/ctrl_ext_descriptor=3*924371
A/ctrl_ext_descriptor=21|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ext_descriptor.vhd|166|1*16014956
BinI32/ctrl_ext_descriptor=3*1887515
I=0*678728
I/ctrl_ext_descriptor=0*684245
M=11|0|v98|1359756143875|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ext_descriptor.vhd|0*677551*0x4bfe5df5f140cb838ec501e1c6c56f4648a082b7|0*678591*0xab32bc1a2daf049573e14469f634e0e6
M/ctrl_ext_descriptor=21|0|v98|1359756284612|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ext_descriptor.vhd|0*679038*0x76103e16cbc629630017eaab41ed70a2d8b6d343|0*684085*0x9883a4debb77c3d3c4860cd1e2edf83c
M/ctrl_ext_descriptor=21|0|v98|1374782080823|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ext_descriptor.vhd|0*679038*0x76103e16cbc629630017eaab41ed70a2d8b6d343|0*684085*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ext_descriptor.vhd|124
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/ctrl_ext_descriptor=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
501,12 → 501,12
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[ctrl_ext_ram]
A/ctrl_ext_ram=21|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ext_ram.vhd|142|1*9023855
BinI32/ctrl_ext_ram=3*952634
A/ctrl_ext_ram=21|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ext_ram.vhd|142|1*16171338
BinI32/ctrl_ext_ram=3*1915769
I=0*724072
I/ctrl_ext_ram=0*727116
M=11|0|v98|1359756144734|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ext_ram.vhd|0*722878*0x760f2347e6571851c8dc466708471d7b84325888|0*723949*0xab32bc1a2daf049573e14469f634e0e6
M/ctrl_ext_ram=21|0|v98|1359756285390|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ext_ram.vhd|0*724500*0x13455dca29a5e85aab8fea3e29887eb621fe979b|0*726977*0x9883a4debb77c3d3c4860cd1e2edf83c
M/ctrl_ext_ram=21|0|v98|1374782081724|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ext_ram.vhd|0*724500*0x13455dca29a5e85aab8fea3e29887eb621fe979b|0*726977*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ext_ram.vhd|98
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/ctrl_ext_ram=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
519,14 → 519,16
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[ctrl_fifo1024x64_st_v1]
A/structure=A/STRUCTURE 21|./src/wishbone/coregen/ctrl_fifo1024x64_st_v1.vhd|57|1*12509701
BinI32/structure=3*1357379
I=0*1458504
I/structure=I/STRUCTURE 0*1786148
M=11|0|v98|1359756252359|./src/wishbone/coregen/ctrl_fifo1024x64_st_v1.vhd|0*1457843*0x9bf03bdde06fc0f2f5afb3ceffa4ee6370ad704c|0*1458382*0xab32bc1a2daf049573e14469f634e0e6
A/ctrl_fifo1024x64_st_v1_a=21|./src/wishbone/coregen/ctrl_fifo1024x64_st_v1.vhd|58|1*18713005
A/structure=+21|./src/wishbone/coregen/ctrl_fifo1024x64_st_v1.vhd|57|1*12509701
I=0*2867364
I/ctrl_fifo1024x64_st_v1_a=0*2873599
M=11|0|v98|1374782055080|./src/wishbone/coregen/ctrl_fifo1024x64_st_v1.vhd|0*2866757*0xeede78380b6064338a16646d0c53a2dcb92f77a0|0*2867242*0xab32bc1a2daf049573e14469f634e0e6
M/ctrl_fifo1024x64_st_v1_a=21|0|v98|1374782102632|./src/wishbone/coregen/ctrl_fifo1024x64_st_v1.vhd|0*2867480*0xd59df81bb76db9f7bb70557f039ffa6ebe337eda|0*2873449*0x9883a4debb77c3d3c4860cd1e2edf83c
M/structure=M/STRUCTURE 21|0|v98|1359756301468|./src/wishbone/coregen/ctrl_fifo1024x64_st_v1.vhd|0*1458740*0x622d9022644cf622594192b43d3cb46e7f9b2366|0*1786013*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/wishbone/coregen/ctrl_fifo1024x64_st_v1.vhd|43
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/ctrl_fifo1024x64_st_v1_a=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/structure=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[ctrl_fifo512x64st_v0]
581,12 → 583,12
Version/ctrl_fifo64x70st_a=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[ctrl_main]
A/ctrl_main=21|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_main.vhd|157|1*8974161
BinI32/ctrl_main=3*928962
A/ctrl_main=21|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_main.vhd|157|1*16121644
BinI32/ctrl_main=3*1892105
I=0*688741
I/ctrl_main=0*700219
M=11|0|v98|1359756144156|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_main.vhd|0*687384*0x8f915b3857110dbe261506a6ea430bbe51766a83|0*688624*0xab32bc1a2daf049573e14469f634e0e6
M/ctrl_main=21|0|v98|1359756284845|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_main.vhd|0*689041*0x744d836fd2e53a5ff93e6792d5cd69fc0d50757a|0*700089*0x9883a4debb77c3d3c4860cd1e2edf83c
M/ctrl_main=21|0|v98|1374782081087|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_main.vhd|0*689041*0x744d836fd2e53a5ff93e6792d5cd69fc0d50757a|0*700089*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_main.vhd|104
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/ctrl_main=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
617,23 → 619,23
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[ctrl_ram_cmd]
A/ctrl_ram_cmd=21|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ram_cmd.vhd|135|1*8997971
BinI32/ctrl_ram_cmd=3*944477
A/ctrl_ram_cmd=21|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ram_cmd.vhd|135|1*16145454
BinI32/ctrl_ram_cmd=3*1907611
I=0*710992
I/ctrl_ram_cmd=0*720127
M=11|0|v98|1359756144484|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ram_cmd.vhd|0*709888*0xf411afafb00d9a2731b474f220505592fa94717e|0*710869*0xab32bc1a2daf049573e14469f634e0e6
M/ctrl_ram_cmd=21|0|v98|1359756285156|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ram_cmd.vhd|0*711361*0xc483f7c91776c8a0ab3765a982332bba1789fffa|0*719988*0x9883a4debb77c3d3c4860cd1e2edf83c
M/ctrl_ram_cmd=21|0|v98|1374782081478|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ram_cmd.vhd|0*711361*0xc483f7c91776c8a0ab3765a982332bba1789fffa|0*719988*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ram_cmd.vhd|96
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/ctrl_ram_cmd=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[ctrl_ram_cmd_pb]
A/ctrl_ram_cmd_pb=21|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ram_cmd_pb.vhd|117|1*8989958
BinI32/ctrl_ram_cmd_pb=3*939956
A/ctrl_ram_cmd_pb=21|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ram_cmd_pb.vhd|117|1*16137441
BinI32/ctrl_ram_cmd_pb=3*1903092
I=0*703357
I/ctrl_ram_cmd_pb=0*707608
M=11|0|v98|1359756144237|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ram_cmd_pb.vhd|0*702421*0x54ed906e63b9d05518ae841475c2b9000bda0dbd|0*703228*0xab32bc1a2daf049573e14469f634e0e6
M/ctrl_ram_cmd_pb=21|0|v98|1359756284909|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ram_cmd_pb.vhd|0*703600*0xd1c3d1e5eec44460d4f1b7219a92edd30c8ab64b|0*707460*0x9883a4debb77c3d3c4860cd1e2edf83c
M/ctrl_ram_cmd_pb=21|0|v98|1374782081197|./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ram_cmd_pb.vhd|0*703600*0xd1c3d1e5eec44460d4f1b7219a92edd30c8ab64b|0*707460*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ram_cmd_pb.vhd|83
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/ctrl_ram_cmd_pb=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
660,67 → 662,67
Version=9.1.2353.4205 (Windows)|0000004f789cd3cd51282e3033308dcfa930312d892fcf2cce48cacf4b55d04d494a57d0cd51c82fcb8c2fcdcbcc4d4c2eca47e21767e6c278159939997915c9f945a93999490047261c91
 
[gtpa1_dual_wrapper]
A/rtl=A/RTL 21|./src/pcie_src/pcie_core64_m1/source_s6/gtpa1_dual_wrapper.vhd|185|1*13333407
BinI32/rtl=3*1419477
A/rtl=A/RTL 21|./src/pcie_src/pcie_core64_m1/source_s6/gtpa1_dual_wrapper.vhd|185|1*16478188
BinI32/rtl=3*1927524
I=0*792765
I/rtl=I/RTL 0*840580
M=11|0|v98|1359756150953|./src/pcie_src/pcie_core64_m1/source_s6/gtpa1_dual_wrapper.vhd|0*789048*0xb7237d536373a3d99530154171b63432b082cbde|0*792634*0xab32bc1a2daf049573e14469f634e0e6
M/rtl=M/RTL 21|0|v98|1359756573161|./src/pcie_src/pcie_core64_m1/source_s6/gtpa1_dual_wrapper.vhd|0*793002*0x4a1bde6cad6ae65a611882ab1dd013ba46ebc774|0*800584*0x9883a4debb77c3d3c4860cd1e2edf83c
M/rtl=M/RTL 21|0|v98|1374782082585|./src/pcie_src/pcie_core64_m1/source_s6/gtpa1_dual_wrapper.vhd|0*793002*0x4a1bde6cad6ae65a611882ab1dd013ba46ebc774|0*800584*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_s6/gtpa1_dual_wrapper.vhd|73
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/rtl=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[gtpa1_dual_wrapper_tile]
A/rtl=A/RTL 21|./src/pcie_src/pcie_core64_m1/source_s6/gtpa1_dual_wrapper_tile.vhd|182|1*13363028
BinI32/rtl=3*1420705
A/rtl=A/RTL 21|./src/pcie_src/pcie_core64_m1/source_s6/gtpa1_dual_wrapper_tile.vhd|182|1*16507809
BinI32/rtl=3*1928746
I=0*807068
I/rtl=I/RTL 0*824420
M=11|0|v98|1359756151171|./src/pcie_src/pcie_core64_m1/source_s6/gtpa1_dual_wrapper_tile.vhd|0*803718*0xc4a6f2cadade41757bdfa8331ae403e2a9c8bf14|0*806927*0xab32bc1a2daf049573e14469f634e0e6
M/rtl=M/RTL 21|0|v98|1359756573393|./src/pcie_src/pcie_core64_m1/source_s6/gtpa1_dual_wrapper_tile.vhd|0*807310*0x42f3286c54c49a33a7e0ecd00ac8f28fa6e76b9a|0*824272*0x9883a4debb77c3d3c4860cd1e2edf83c
M/rtl=M/RTL 21|0|v98|1374782082832|./src/pcie_src/pcie_core64_m1/source_s6/gtpa1_dual_wrapper_tile.vhd|0*807310*0x42f3286c54c49a33a7e0ecd00ac8f28fa6e76b9a|0*824272*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_s6/gtpa1_dual_wrapper_tile.vhd|72
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/rtl=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[gtx_drp_chanalign_fix_3752_v6]
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/gtx_drp_chanalign_fix_3752_v6.vhd|84|1*14085285
BinI32/v6_pcie=3*1510661
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/gtx_drp_chanalign_fix_3752_v6.vhd|84|1*17230066
BinI32/v6_pcie=3*2018678
I=0*1077222
I/v6_pcie=0*1081039
M=11|0|v98|1359756167859|./src/pcie_src/pcie_core64_m1/source_virtex6/gtx_drp_chanalign_fix_3752_v6.vhd|0*1076393*0xb7aeecc59077c54bae8c5ff409c7f7a867006fb6|0*1077064*0xab32bc1a2daf049573e14469f634e0e6
M/v6_pcie=21|0|v98|1359756591145|./src/pcie_src/pcie_core64_m1/source_virtex6/gtx_drp_chanalign_fix_3752_v6.vhd|0*1077414*0x5348bbef3e24830686b249d806d5c24d336c3c9a|0*1080870*0x9883a4debb77c3d3c4860cd1e2edf83c
M/v6_pcie=21|0|v98|1374782084818|./src/pcie_src/pcie_core64_m1/source_virtex6/gtx_drp_chanalign_fix_3752_v6.vhd|0*1077414*0x5348bbef3e24830686b249d806d5c24d336c3c9a|0*1080870*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_virtex6/gtx_drp_chanalign_fix_3752_v6.vhd|64
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/v6_pcie=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[gtx_rx_valid_filter_v6]
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/gtx_rx_valid_filter_v6.vhd|87|1*14092103
BinI32/v6_pcie=3*1513526
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/gtx_rx_valid_filter_v6.vhd|87|1*17236884
BinI32/v6_pcie=3*2021538
I=0*1083043
I/v6_pcie=0*1093269
M=11|0|v98|1359756168078|./src/pcie_src/pcie_core64_m1/source_virtex6/gtx_rx_valid_filter_v6.vhd|0*1081970*0x09f886874e5b7aa69b289de81f0f2a2dd22fe53b|0*1082899*0xab32bc1a2daf049573e14469f634e0e6
M/v6_pcie=21|0|v98|1359756591375|./src/pcie_src/pcie_core64_m1/source_virtex6/gtx_rx_valid_filter_v6.vhd|0*1083291*0x7390a512e2e28cf541cf2a30a6f94a42afb6258c|0*1093114*0x9883a4debb77c3d3c4860cd1e2edf83c
M/v6_pcie=21|0|v98|1374782085097|./src/pcie_src/pcie_core64_m1/source_virtex6/gtx_rx_valid_filter_v6.vhd|0*1083291*0x7390a512e2e28cf541cf2a30a6f94a42afb6258c|0*1093114*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_virtex6/gtx_rx_valid_filter_v6.vhd|62
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/v6_pcie=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[gtx_tx_sync_rate_v6]
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/gtx_tx_sync_rate_v6.vhd|87|1*14110391
BinI32/v6_pcie=3*1523225
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/gtx_tx_sync_rate_v6.vhd|87|1*17255172
BinI32/v6_pcie=3*2031213
I=0*1095005
I/v6_pcie=0*1105416
M=11|0|v98|1359756168171|./src/pcie_src/pcie_core64_m1/source_virtex6/gtx_tx_sync_rate_v6.vhd|0*1094154*0x119bf24dfe6c743eb7ced0f44710747ccabfca8b|0*1094867*0xab32bc1a2daf049573e14469f634e0e6
M/v6_pcie=21|0|v98|1359756591456|./src/pcie_src/pcie_core64_m1/source_virtex6/gtx_tx_sync_rate_v6.vhd|0*1095187*0x1ed5059ada6dacd677cd376dd40076726a1e0fd3|0*1105267*0x9883a4debb77c3d3c4860cd1e2edf83c
M/v6_pcie=21|0|v98|1374782085222|./src/pcie_src/pcie_core64_m1/source_virtex6/gtx_tx_sync_rate_v6.vhd|0*1095187*0x1ed5059ada6dacd677cd376dd40076726a1e0fd3|0*1105267*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_virtex6/gtx_tx_sync_rate_v6.vhd|64
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/v6_pcie=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[gtx_wrapper_v6]
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/gtx_wrapper_v6.vhd|121|1*14123276
BinI32/v6_pcie=3*1529841
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/gtx_wrapper_v6.vhd|121|1*17268057
BinI32/v6_pcie=3*2037805
I=0*1109356
I/v6_pcie=0*1129175
M=11|0|v98|1359756168406|./src/pcie_src/pcie_core64_m1/source_virtex6/gtx_wrapper_v6.vhd|0*1107276*0x5f01e8081be485e4086f689cadda2ad967abb3c9|0*1109228*0xab32bc1a2daf049573e14469f634e0e6
M/v6_pcie=21|0|v98|1359756591737|./src/pcie_src/pcie_core64_m1/source_virtex6/gtx_wrapper_v6.vhd|0*1109596*0x0b7176f9a692b77fca690b775a770ada6235ce88|0*1129036*0x9883a4debb77c3d3c4860cd1e2edf83c
M/v6_pcie=21|0|v98|1374782085502|./src/pcie_src/pcie_core64_m1/source_virtex6/gtx_wrapper_v6.vhd|0*1109596*0x0b7176f9a692b77fca690b775a770ada6235ce88|0*1129036*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_virtex6/gtx_wrapper_v6.vhd|66
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/v6_pcie=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
802,12 → 804,12
Version/v6_pcie=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[pcie_2_0_v6]
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_2_0_v6.vhd|553|1*14239024
BinI32/v6_pcie=3*1540292
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_2_0_v6.vhd|553|1*17383805
BinI32/v6_pcie=3*2048256
I=0*1166758
I/v6_pcie=0*1381962
M=11|0|v98|1359756168765|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_2_0_v6.vhd|0*1146737*0x9239275d3d070f5618f51558f2add099bb563ced|0*1166636*0xab32bc1a2daf049573e14469f634e0e6
M/v6_pcie=21|0|v98|1359756592033|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_2_0_v6.vhd|0*1166995*0x3a1ba6dd457afedfca8fe6c2c28e45d4a3721383|0*1250125*0x9883a4debb77c3d3c4860cd1e2edf83c
M/v6_pcie=21|0|v98|1374782085827|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_2_0_v6.vhd|0*1166995*0x3a1ba6dd457afedfca8fe6c2c28e45d4a3721383|0*1250125*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_2_0_v6.vhd|66
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/v6_pcie=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
824,89 → 826,89
Version/v6_pcie=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[pcie_bram_s6]
A/rtl=21|./src/pcie_src/pcie_core64_m1/source_s6/pcie_bram_s6.vhd|86|1*13497574
BinI32/rtl=3*1425498
A/rtl=21|./src/pcie_src/pcie_core64_m1/source_s6/pcie_bram_s6.vhd|86|1*16642355
BinI32/rtl=3*1933528
I=0*831389
I/rtl=0*834162
M=11|0|v98|1359756151468|./src/pcie_src/pcie_core64_m1/source_s6/pcie_bram_s6.vhd|0*830636*0xc061b9632f33bd50ae6fd48db2c18454f817ce51|0*831270*0xab32bc1a2daf049573e14469f634e0e6
M/rtl=21|0|v98|1359756573815|./src/pcie_src/pcie_core64_m1/source_s6/pcie_bram_s6.vhd|0*831627*0xcd0a7c63053006eff762753d86775763de39803e|0*834036*0x9883a4debb77c3d3c4860cd1e2edf83c
M/rtl=21|0|v98|1374782083256|./src/pcie_src/pcie_core64_m1/source_s6/pcie_bram_s6.vhd|0*831627*0xcd0a7c63053006eff762753d86775763de39803e|0*834036*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_s6/pcie_bram_s6.vhd|65
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/rtl=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[pcie_bram_top_s6]
A/rtl=21|./src/pcie_src/pcie_core64_m1/source_s6/pcie_bram_top_s6.vhd|101|1*13569503
BinI32/rtl=3*1428847
A/rtl=21|./src/pcie_src/pcie_core64_m1/source_s6/pcie_bram_top_s6.vhd|101|1*16714284
BinI32/rtl=3*1936878
I=0*836919
I/rtl=0*839487
M=11|0|v98|1359756151515|./src/pcie_src/pcie_core64_m1/source_s6/pcie_bram_top_s6.vhd|0*835527*0xeab01f9bf924a3a78aec3daeb720bb8d2ab546ea|0*836792*0xab32bc1a2daf049573e14469f634e0e6
M/rtl=21|0|v98|1359756573859|./src/pcie_src/pcie_core64_m1/source_s6/pcie_bram_top_s6.vhd|0*837163*0x80537f37fab342003c695df54258d182dda8cc6e|0*839353*0x9883a4debb77c3d3c4860cd1e2edf83c
M/rtl=21|0|v98|1374782083321|./src/pcie_src/pcie_core64_m1/source_s6/pcie_bram_top_s6.vhd|0*837163*0x80537f37fab342003c695df54258d182dda8cc6e|0*839353*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_s6/pcie_bram_top_s6.vhd|64
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/rtl=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[pcie_bram_top_v6]
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_bram_top_v6.vhd|100|1*14625481
BinI32/v6_pcie=3*1555833
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_bram_top_v6.vhd|100|1*17770262
BinI32/v6_pcie=3*2063797
I=0*1258047
I/v6_pcie=0*1261329
M=11|0|v98|1359756169531|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_bram_top_v6.vhd|0*1256647*0x75b5048e78027eabbddfb90775a39f4d897dca51|0*1257915*0xab32bc1a2daf049573e14469f634e0e6
M/v6_pcie=21|0|v98|1359756592333|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_bram_top_v6.vhd|0*1258226*0x9006e76090004d61357237b63db6656ba5b7698c|0*1261186*0x9883a4debb77c3d3c4860cd1e2edf83c
M/v6_pcie=21|0|v98|1374782086160|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_bram_top_v6.vhd|0*1258226*0x9006e76090004d61357237b63db6656ba5b7698c|0*1261186*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_bram_top_v6.vhd|64
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/v6_pcie=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[pcie_bram_v6]
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_bram_v6.vhd|84|1*14634364
BinI32/v6_pcie=3*1558514
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_bram_v6.vhd|84|1*17779145
BinI32/v6_pcie=3*2066481
I=0*1262788
I/v6_pcie=0*1269816
M=11|0|v98|1359756169781|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_bram_v6.vhd|0*1262025*0x0e59fd7a45ff4350d0255cbef11d6b22978c6fb9|0*1262664*0xab32bc1a2daf049573e14469f634e0e6
M/v6_pcie=21|0|v98|1359756592564|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_bram_v6.vhd|0*1263026*0x955e1a1f636f7dfe2d92c9124e05e81b3662fc2a|0*1269681*0x9883a4debb77c3d3c4860cd1e2edf83c
M/v6_pcie=21|0|v98|1374782086420|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_bram_v6.vhd|0*1263026*0x955e1a1f636f7dfe2d92c9124e05e81b3662fc2a|0*1269681*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_bram_v6.vhd|65
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/v6_pcie=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[pcie_brams_s6]
A/rtl=21|./src/pcie_src/pcie_core64_m1/source_s6/pcie_brams_s6.vhd|110|1*13487335
BinI32/rtl=3*1421909
A/rtl=21|./src/pcie_src/pcie_core64_m1/source_s6/pcie_brams_s6.vhd|110|1*16632116
BinI32/rtl=3*1929950
I=0*826007
I/rtl=0*840891
M=11|0|v98|1359756151265|./src/pcie_src/pcie_core64_m1/source_s6/pcie_brams_s6.vhd|0*825234*0x5992542ce8b943f48b06e5a194e257d7d6462474|0*825886*0xab32bc1a2daf049573e14469f634e0e6
M/rtl=21|0|v98|1359756573596|./src/pcie_src/pcie_core64_m1/source_s6/pcie_brams_s6.vhd|0*826183*0x5580276f48cf7781ae0cf4678d339b1af28cc74b|0*829993*0x9883a4debb77c3d3c4860cd1e2edf83c
M/rtl=21|0|v98|1374782083037|./src/pcie_src/pcie_core64_m1/source_s6/pcie_brams_s6.vhd|0*826183*0x5580276f48cf7781ae0cf4678d339b1af28cc74b|0*829993*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_s6/pcie_brams_s6.vhd|64
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/rtl=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[pcie_brams_v6]
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_brams_v6.vhd|111|1*14615449
BinI32/v6_pcie=3*1552104
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_brams_v6.vhd|111|1*17760230
BinI32/v6_pcie=3*2060066
I=0*1251615
I/v6_pcie=0*1382519
M=11|0|v98|1359756168906|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_brams_v6.vhd|0*1250832*0x89c733d460897d4f0158b36b719c2df807573696|0*1251489*0xab32bc1a2daf049573e14469f634e0e6
M/v6_pcie=21|0|v98|1359756592284|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_brams_v6.vhd|0*1251791*0x078e5c82ddc090a9fe8b210a6809ea7deb404b64|0*1255373*0x9883a4debb77c3d3c4860cd1e2edf83c
M/v6_pcie=21|0|v98|1374782086095|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_brams_v6.vhd|0*1251791*0x078e5c82ddc090a9fe8b210a6809ea7deb404b64|0*1255373*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_brams_v6.vhd|64
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/v6_pcie=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[pcie_clocking_v6]
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_clocking_v6.vhd|89|1*14800665
BinI32/v6_pcie=3*1564533
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_clocking_v6.vhd|89|1*17945446
BinI32/v6_pcie=3*2072493
I=0*1271616
I/v6_pcie=0*1279510
M=11|0|v98|1359756170078|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_clocking_v6.vhd|0*1270753*0xed4093b6f999cdb46463057098974b89bbc0e193|0*1271484*0xab32bc1a2daf049573e14469f634e0e6
M/v6_pcie=21|0|v98|1359756592799|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_clocking_v6.vhd|0*1271790*0xca4a1e4897c60a14dbcb0211eda14603c79c3a60|0*1279367*0x9883a4debb77c3d3c4860cd1e2edf83c
M/v6_pcie=21|0|v98|1374782086719|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_clocking_v6.vhd|0*1271790*0xca4a1e4897c60a14dbcb0211eda14603c79c3a60|0*1279367*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_clocking_v6.vhd|65
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/v6_pcie=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[pcie_core64_m6]
A/pcie_core64_m6=21|./src/pcie_src/pcie_core64_m1/top/pcie_core64_m6.vhd|145|1*11007907
BinI32/pcie_core64_m6=3*1147504
A/pcie_core64_m6=21|./src/pcie_src/pcie_core64_m1/top/pcie_core64_m6.vhd|145|1*18155390
BinI32/pcie_core64_m6=3*2110603
I=0*1427508
I/pcie_core64_m6=0*1444435
M=11|0|v98|1359756226032|./src/pcie_src/pcie_core64_m1/top/pcie_core64_m6.vhd|0*1426097*0xf101e062ac6903fe067e7fa8331dbd9e4a1417a4|0*1427391*0xab32bc1a2daf049573e14469f634e0e6
M/pcie_core64_m6=21|0|v98|1359756291206|./src/pcie_src/pcie_core64_m1/top/pcie_core64_m6.vhd|0*1428087*0xeeff7248db1c9eef3f2438d371da9dd5865cabe7|0*1444300*0x9883a4debb77c3d3c4860cd1e2edf83c
M/pcie_core64_m6=21|0|v98|1374782087811|./src/pcie_src/pcie_core64_m1/top/pcie_core64_m6.vhd|0*1428087*0xeeff7248db1c9eef3f2438d371da9dd5865cabe7|0*1444300*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/top/pcie_core64_m6.vhd|94
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/pcie_core64_m6=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
919,12 → 921,12
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[pcie_core64_wishbone]
A/pcie_core64_wishbone=21|./src/pcie_src/components/pcie_core/pcie_core64_wishbone.vhd|146|1*8685743
BinI32/pcie_core64_wishbone=3*873364
A/pcie_core64_wishbone=21|./src/pcie_src/components/pcie_core/pcie_core64_wishbone.vhd|146|1*18864461
BinI32/pcie_core64_wishbone=3*2194127
I=0*1453876
I/pcie_core64_wishbone=0*1456869
I/pcie_core64_wishbone=0*3081893
M=11|0|v98|1359756238798|./src/pcie_src/components/pcie_core/pcie_core64_wishbone.vhd|0*1452281*0x32d5df94908fcc6f0646102a1949108e9ca340ff|0*1453745*0xab32bc1a2daf049573e14469f634e0e6
M/pcie_core64_wishbone=21|0|v98|1359756281362|./src/pcie_src/components/pcie_core/pcie_core64_wishbone.vhd|0*1454251*0x5222911a3b26112f0ff27086e29892a3d7fd5dd7|0*1456714*0x9883a4debb77c3d3c4860cd1e2edf83c
M/pcie_core64_wishbone=21|0|v98|1374782372993|./src/pcie_src/components/pcie_core/pcie_core64_wishbone.vhd|0*3079027*0x97b6daa1f7c8337e73c5f8cefc46fb31887feee6|0*3081738*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/components/pcie_core/pcie_core64_wishbone.vhd|95
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/pcie_core64_wishbone=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
937,67 → 939,67
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[pcie_gtx_v6]
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_gtx_v6.vhd|218|1*14826026
BinI32/v6_pcie=3*1567865
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_gtx_v6.vhd|218|1*17970807
BinI32/v6_pcie=3*2075825
I=0*1290582
I/v6_pcie=0*1304434
M=11|0|v98|1359756170187|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_gtx_v6.vhd|0*1285034*0x60261f4b7f47afddb633411370f37517a034626d|0*1290460*0xab32bc1a2daf049573e14469f634e0e6
M/v6_pcie=21|0|v98|1359756593034|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_gtx_v6.vhd|0*1290756*0x0c61e3dc36eb0c8016e89a49661824ecd79c4950|0*1304301*0x9883a4debb77c3d3c4860cd1e2edf83c
M/v6_pcie=21|0|v98|1374782087000|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_gtx_v6.vhd|0*1290756*0x0c61e3dc36eb0c8016e89a49661824ecd79c4950|0*1304301*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_gtx_v6.vhd|63
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/v6_pcie=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[pcie_pipe_lane_v6]
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_pipe_lane_v6.vhd|98|1*14873848
BinI32/v6_pcie=3*1578631
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_pipe_lane_v6.vhd|98|1*18018629
BinI32/v6_pcie=3*2086580
I=0*1307551
I/v6_pcie=0*1315303
M=11|0|v98|1359756170468|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_pipe_lane_v6.vhd|0*1305979*0xee7b1b6d0bdd7d15c855469954fc3cd078eeea9f|0*1307417*0xab32bc1a2daf049573e14469f634e0e6
M/v6_pcie=21|0|v98|1359756593114|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_pipe_lane_v6.vhd|0*1307662*0x221349204a1c570973db63163a73e1441e690e78|0*1315158*0x9883a4debb77c3d3c4860cd1e2edf83c
M/v6_pcie=21|0|v98|1374782087127|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_pipe_lane_v6.vhd|0*1307662*0x221349204a1c570973db63163a73e1441e690e78|0*1315158*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_pipe_lane_v6.vhd|62
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/v6_pcie=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[pcie_pipe_misc_v6]
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_pipe_misc_v6.vhd|85|1*14889237
BinI32/v6_pcie=3*1584857
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_pipe_misc_v6.vhd|85|1*18034018
BinI32/v6_pcie=3*2092806
I=0*1316969
I/v6_pcie=0*1320624
M=11|0|v98|1359756170531|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_pipe_misc_v6.vhd|0*1316072*0x89949326c9e9bb291d5b7f66b96aee44f587d186|0*1316835*0xab32bc1a2daf049573e14469f634e0e6
M/v6_pcie=21|0|v98|1359756593161|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_pipe_misc_v6.vhd|0*1317080*0x7b98823c744a293c19913736ee39243fa81a082f|0*1320479*0x9883a4debb77c3d3c4860cd1e2edf83c
M/v6_pcie=21|0|v98|1374782087205|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_pipe_misc_v6.vhd|0*1317080*0x7b98823c744a293c19913736ee39243fa81a082f|0*1320479*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_pipe_misc_v6.vhd|62
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/v6_pcie=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[pcie_pipe_v6]
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_pipe_v6.vhd|339|1*14896603
BinI32/v6_pcie=3*1588271
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_pipe_v6.vhd|339|1*18041384
BinI32/v6_pcie=3*2096218
I=0*1340341
I/v6_pcie=0*1369790
M=11|0|v98|1359756170593|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_pipe_v6.vhd|0*1330284*0x005078a31d5710d4339a7ff067a504e6baadd355|0*1340217*0xab32bc1a2daf049573e14469f634e0e6
M/v6_pcie=21|0|v98|1359756593221|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_pipe_v6.vhd|0*1340447*0x1838642d47221354da896ef5cf569f82ad251dc6|0*1369655*0x9883a4debb77c3d3c4860cd1e2edf83c
M/v6_pcie=21|0|v98|1374782087375|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_pipe_v6.vhd|0*1340447*0x1838642d47221354da896ef5cf569f82ad251dc6|0*1369655*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_pipe_v6.vhd|62
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/v6_pcie=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[pcie_reset_delay_v6]
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_reset_delay_v6.vhd|76|1*14996457
BinI32/v6_pcie=3*1594838
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_reset_delay_v6.vhd|76|1*18141238
BinI32/v6_pcie=3*2102785
I=0*1370913
I/v6_pcie=0*1372964
M=11|0|v98|1359756170703|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_reset_delay_v6.vhd|0*1370333*0x8c75c41baf05eb7b3afbaaf12dbc879442689cf2|0*1370775*0xab32bc1a2daf049573e14469f634e0e6
M/v6_pcie=21|0|v98|1359756593286|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_reset_delay_v6.vhd|0*1371095*0x38a309b93640d488a15456c08062d93b92860641|0*1372815*0x9883a4debb77c3d3c4860cd1e2edf83c
M/v6_pcie=21|0|v98|1374782087486|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_reset_delay_v6.vhd|0*1371095*0x38a309b93640d488a15456c08062d93b92860641|0*1372815*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_reset_delay_v6.vhd|63
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/v6_pcie=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[pcie_upconfig_fix_3451_v6]
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_upconfig_fix_3451_v6.vhd|82|1*14999879
BinI32/v6_pcie=3*1597150
A/v6_pcie=21|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_upconfig_fix_3451_v6.vhd|82|1*18144660
BinI32/v6_pcie=3*2105095
I=0*1374768
I/v6_pcie=0*1379733
M=11|0|v98|1359756170750|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_upconfig_fix_3451_v6.vhd|0*1373796*0x090606fc753c375feddedbf97c2e2346e1cca5e6|0*1374618*0xab32bc1a2daf049573e14469f634e0e6
M/v6_pcie=21|0|v98|1359756593331|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_upconfig_fix_3451_v6.vhd|0*1374956*0xc2457495bda4f47657aab87c57c2881a677a3346|0*1379572*0x9883a4debb77c3d3c4860cd1e2edf83c
M/v6_pcie=21|0|v98|1374782087548|./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_upconfig_fix_3451_v6.vhd|0*1374956*0xc2457495bda4f47657aab87c57c2881a677a3346|0*1379572*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/pcie_src/pcie_core64_m1/source_virtex6/pcie_upconfig_fix_3451_v6.vhd|62
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/v6_pcie=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
1013,12 → 1015,12
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[sp605_lx45t_wishbone]
A/rtl=21|./src/top/sp605_lx45t_wishbone.vhd|91|1*12016091
BinI32/rtl=3*1281628
A/rtl=21|./src/top/sp605_lx45t_wishbone.vhd|91|1*19013441
BinI32/rtl=3*2199770
I=0*2151775
I/rtl=0*2153148
M=11|0|v98|1359756294656|./src/top/sp605_lx45t_wishbone.vhd|0*2150954*0x7b10f06a42ef3014f4822e7010bfd398230c5678|0*2151670*0xab32bc1a2daf049573e14469f634e0e6
M/rtl=21|0|v98|1359756294671|./src/top/sp605_lx45t_wishbone.vhd|0*2152032*0x54c320cc912158991871fa10413ec90c18be68f4|0*2153036*0x9883a4debb77c3d3c4860cd1e2edf83c
M/rtl=21|0|v98|1374782382389|./src/top/sp605_lx45t_wishbone.vhd|0*2152032*0x54c320cc912158991871fa10413ec90c18be68f4|0*2153036*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/top/sp605_lx45t_wishbone.vhd|65
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/rtl=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
1031,12 → 1033,12
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[sp605_lx45t_wishbone_sopc_wb]
A/rtl=21|./src/top/sp605_lx45t_wishbone_sopc_wb.vhd|104|1*13077051
BinI32/rtl=3*1408987
A/rtl=21|./src/top/sp605_lx45t_wishbone_sopc_wb.vhd|104|1*19070299
BinI32/rtl=3*2229941
I=0*2123952
I/rtl=0*2148537
I/rtl=0*3106526
M=11|0|v98|1359756294409|./src/top/sp605_lx45t_wishbone_sopc_wb.vhd|0*2123038*0xd400d88b2e6aec345510aa3c230d98ec4cfd9894|0*2123831*0xab32bc1a2daf049573e14469f634e0e6
M/rtl=21|0|v98|1359756350253|./src/top/sp605_lx45t_wishbone_sopc_wb.vhd|0*2124486*0x20dd0c2bf37c9e72c93e8992036bf57812847237|0*2148409*0x9883a4debb77c3d3c4860cd1e2edf83c
M/rtl=21|0|v98|1374783157225|./src/top/sp605_lx45t_wishbone_sopc_wb.vhd|0*3082475*0x2749fd94c2e39917e262559f2f2c0048a491302f|0*3106398*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/top/sp605_lx45t_wishbone_sopc_wb.vhd|79
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/rtl=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
1049,12 → 1051,12
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[stend_sp605_wishbone]
A/stend_sp605_wishbone=21|./src/testbench/stend_sp605_wishbone.vhd|51|1*15316229
BinI32/stend_sp605_wishbone=3*1732843
A/stend_sp605_wishbone=21|./src/testbench/stend_sp605_wishbone.vhd|51|1*19053546
BinI32/stend_sp605_wishbone=3*2228071
I=0*2547071
I/stend_sp605_wishbone=0*2547618
M=11|0|v98|1365718865396|./src/testbench/stend_sp605_wishbone.vhd|0*2546430*0x8d542d86a2255ac915201296af56eb489dd692c0|0*2546960*0xab32bc1a2daf049573e14469f634e0e6
M/stend_sp605_wishbone=21|0|v98|1365719381626|./src/testbench/stend_sp605_wishbone.vhd|0*2430473*0xe330b76d68a67a5b404e5df4308e3cc2981845c3|0*2433221*0x9883a4debb77c3d3c4860cd1e2edf83c
I/stend_sp605_wishbone=0*2650541
M=11|0|v98|1374782043147|./src/testbench/stend_sp605_wishbone.vhd|0*2546430*0x8d542d86a2255ac915201296af56eb489dd692c0|0*2546960*0xab32bc1a2daf049573e14469f634e0e6
M/stend_sp605_wishbone=21|0|v98|1374782388954|./src/testbench/stend_sp605_wishbone.vhd|0*2647623*0xff9b2e6ba51199da3049f620ff1bad670e6af27a|0*2650406*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/testbench/stend_sp605_wishbone.vhd|43
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
Version/stend_sp605_wishbone=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
1070,12 → 1072,12
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[test_pkg]
BinI32/test_pkg=3*1708595
E=1*15295097
I=0*2083675
I/test_pkg=0*2584969
M=3|0|v98|1359756294265|./src/testbench/test_pkg.vhd|0*2082686*0x2579205ad1bbced916e3fb2d34f712d2874243ab|0*2083588*0xab32bc1a2daf049573e14469f634e0e6
M/test_pkg=4|0|v98|1365719371858|./src/testbench/test_pkg.vhd|0*2548375*0x377d913efcb600912af19c6a15d30d6d44feca71|0*2584871*0x9883a4debb77c3d3c4860cd1e2edf83c
BinI32/test_pkg=3*2202019
E=1*19030909
I=0*2607057
I/test_pkg=0*2646845
M=3|0|v98|1374782042943|./src/testbench/test_pkg.vhd|0*2606008*0xe8d5491a7d0d5bd0e39006e1194373956323cf68|0*2606970*0xab32bc1a2daf049573e14469f634e0e6
M/test_pkg=4|0|v98|1374782388671|./src/testbench/test_pkg.vhd|0*2607587*0xc642367dc59ad6303bef8b236ad84d39954f4aee|0*2646747*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/testbench/test_pkg.vhd|31
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
1090,67 → 1092,67
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[wb_block_pkg]
BinI32/wb_block_pkg=3*1381924
E=1*13033365
I=0*2079368
I/wb_block_pkg=0*2081320
M=3|0|v98|1359756294218|./src/testbench/wb_block_pkg.vhd|0*2077278*0x6419db40900a5a5fb501e62744252436be671e84|0*2079273*0xab32bc1a2daf049573e14469f634e0e6
M/wb_block_pkg=4|0|v98|1359756328441|./src/testbench/wb_block_pkg.vhd|0*2079787*0x924a2305350fcfb892e8197d476652222151f954|0*2081210*0x9883a4debb77c3d3c4860cd1e2edf83c
BinI32/wb_block_pkg=3*2200310
E=1*19023203
I=0*2602180
I/wb_block_pkg=0*2604554
M=3|0|v98|1374782042724|./src/testbench/wb_block_pkg.vhd|0*2599833*0x9f4cc636e26f58490fa391e861b6617b41e33d3a|0*2602085*0xab32bc1a2daf049573e14469f634e0e6
M/wb_block_pkg=4|0|v98|1374782388534|./src/testbench/wb_block_pkg.vhd|0*2602599*0x542a2df531ca3c026473878aa316495e78b46d98|0*2604444*0x9883a4debb77c3d3c4860cd1e2edf83c
R=./src/testbench/wb_block_pkg.vhd|33
Version=9.1.2353.4205 (Windows)|00000004789cd34d494a0700030f015b
 
[wb_conmax_arb]
A/wb_conmax_arb=22|./src/wishbone/cross/wb_conmax_arb.v|64|1*12128924
BinI32/wb_conmax_arb=3*1311695
A/wb_conmax_arb=22|./src/wishbone/cross/wb_conmax_arb.v|64|1*18332228
BinI32/wb_conmax_arb=3*2144014
P/~emb=430,716,1823,2447
R=./src/wishbone/cross/wb_conmax_arb.v|64
Version=9.1.2353.4205 (Windows)|0000004f789cd3cd51282e3033308dcfa930312d892fcf2cce48cacf4b55d04d494a57d0cd51c82fcb8c2fcdcbcc4d4c2eca47e21767e6c278159939997915c9f945a93999490047261c91
 
[wb_conmax_master_if]
A/wb_conmax_master_if=22|./src/wishbone/cross/wb_conmax_master_if.v|62|1*12132388
BinI32/wb_conmax_master_if=3*1315204
A/wb_conmax_master_if=22|./src/wishbone/cross/wb_conmax_master_if.v|62|1*18335692
BinI32/wb_conmax_master_if=3*2147546
P/~emb=9202,10449,15482,15861
R=./src/wishbone/cross/wb_conmax_master_if.v|62
Version=9.1.2353.4205 (Windows)|0000004f789cd3cd51282e3033308dcfa930312d892fcf2cce48cacf4b55d04d494a57d0cd51c82fcb8c2fcdcbcc4d4c2eca47e21767e6c278159939997915c9f945a93999490047261c91
 
[wb_conmax_msel]
A/wb_conmax_msel=22|./src/wishbone/cross/wb_conmax_msel.v|62|1*12176005
BinI32/wb_conmax_msel=3*1330794
A/wb_conmax_msel=22|./src/wishbone/cross/wb_conmax_msel.v|62|1*18379309
BinI32/wb_conmax_msel=3*2162973
P/~emb=462,894,2305,2813
R=./src/wishbone/cross/wb_conmax_msel.v|62
Version=9.1.2353.4205 (Windows)|0000004f789cd3cd51282e3033308dcfa930312d892fcf2cce48cacf4b55d04d494a57d0cd51c82fcb8c2fcdcbcc4d4c2eca47e21767e6c278159939997915c9f945a93999490047261c91
 
[wb_conmax_pri_dec]
A/wb_conmax_pri_dec=22|./src/wishbone/cross/wb_conmax_pri_dec.v|62|1*12192956
BinI32/wb_conmax_pri_dec=3*1337472
A/wb_conmax_pri_dec=22|./src/wishbone/cross/wb_conmax_pri_dec.v|62|1*18396260
BinI32/wb_conmax_pri_dec=3*2169529
P/~emb=223,476,812,954
R=./src/wishbone/cross/wb_conmax_pri_dec.v|62
Version=9.1.2353.4205 (Windows)|0000004f789cd3cd51282e3033308dcfa930312d892fcf2cce48cacf4b55d04d494a57d0cd51c82fcb8c2fcdcbcc4d4c2eca47e21767e6c278159939997915c9f945a93999490047261c91
 
[wb_conmax_pri_enc]
A/wb_conmax_pri_enc=22|./src/wishbone/cross/wb_conmax_pri_enc.v|62|1*12187491
BinI32/wb_conmax_pri_enc=3*1335825
A/wb_conmax_pri_enc=22|./src/wishbone/cross/wb_conmax_pri_enc.v|62|1*18390795
BinI32/wb_conmax_pri_enc=3*2167880
P/~emb=676,1029,1571,2084
R=./src/wishbone/cross/wb_conmax_pri_enc.v|62
Version=9.1.2353.4205 (Windows)|0000004f789cd3cd51282e3033308dcfa930312d892fcf2cce48cacf4b55d04d494a57d0cd51c82fcb8c2fcdcbcc4d4c2eca47e21767e6c278159939997915c9f945a93999490047261c91
 
[wb_conmax_rf]
A/wb_conmax_rf=22|./src/wishbone/cross/wb_conmax_rf.v|62|1*12195033
BinI32/wb_conmax_rf=3*1339062
A/wb_conmax_rf=22|./src/wishbone/cross/wb_conmax_rf.v|62|1*18398337
BinI32/wb_conmax_rf=3*2171116
P/~emb=1992,2527,4123,4541
R=./src/wishbone/cross/wb_conmax_rf.v|62
Version=9.1.2353.4205 (Windows)|0000004f789cd3cd51282e3033308dcfa930312d892fcf2cce48cacf4b55d04d494a57d0cd51c82fcb8c2fcdcbcc4d4c2eca47e21767e6c278159939997915c9f945a93999490047261c91
 
[wb_conmax_slave_if]
A/wb_conmax_slave_if=22|./src/wishbone/cross/wb_conmax_slave_if.v|62|1*12205950
BinI32/wb_conmax_slave_if=3*1347374
A/wb_conmax_slave_if=22|./src/wishbone/cross/wb_conmax_slave_if.v|62|1*18409254
BinI32/wb_conmax_slave_if=3*2179404
P/~emb=5041,5922,8760,9250
R=./src/wishbone/cross/wb_conmax_slave_if.v|62
Version=9.1.2353.4205 (Windows)|0000004f789cd3cd51282e3033308dcfa930312d892fcf2cce48cacf4b55d04d494a57d0cd51c82fcb8c2fcdcbcc4d4c2eca47e21767e6c278159939997915c9f945a93999490047261c91
 
[wb_conmax_top]
A/wb_conmax_top=22|./src/wishbone/cross/wb_conmax_top.v|68|1*12227647
BinI32/wb_conmax_top=3*1355764
A/wb_conmax_top=22|./src/wishbone/cross/wb_conmax_top.v|68|1*18430951
BinI32/wb_conmax_top=3*2187707
P/~emb=15355,24032,40198,76061
R=./src/wishbone/cross/wb_conmax_top.v|68
Version=9.1.2353.4205 (Windows)|0000004f789cd3cd51282e3033308dcfa930312d892fcf2cce48cacf4b55d04d494a57d0cd51c82fcb8c2fcdcbcc4d4c2eca47e21767e6c278159939997915c9f945a93999490047261c91
1182,21 → 1184,21
 
[~A]
LastVerilogToplevel=wb_conmax_top
ModifyID=2816
ModifyID=3556
Version=73
e:/prog/pcie_ds_dma/trunk/projects/sp605_lx45t_wishbone/src/pcie_src/components/rtl/core64_pb_wishbone_ctrl.v=0*2068200*2071838
e:/prog/pcie_ds_dma/trunk/projects/sp605_lx45t_wishbone/src/pcie_src/pcie_sim/dsport/glbl.v=0*2074137*2075004
e:/prog/pcie_ds_dma/trunk/projects/sp605_lx45t_wishbone/src/wishbone/block_test_check/block_check_wb_burst_slave.v=0*2156638*2157913
e:/prog/pcie_ds_dma/trunk/projects/sp605_lx45t_wishbone/src/wishbone/block_test_generate/block_generate_wb_burst_slave.v=0*2162348*2163981
e:/prog/pcie_ds_dma/trunk/projects/sp605_lx45t_wishbone/src/wishbone/cross/wb_conmax_arb.v_wb_conmax_defines.v_wb_conmax_master_if.v_wb_conmax_msel.v_wb_conmax_pri_dec.v_wb_conmax_pri_enc.v_wb_conmax_rf.v_wb_conmax_slave_if.v_wb_conmax_top.v=0*2299417*2350436
e:/prog/pcie_ds_dma/trunk/projects/sp605_lx45t_wishbone/src/wishbone/block_test_check/block_check_wb_burst_slave.v=0*2884331*2885654
e:/prog/pcie_ds_dma/trunk/projects/sp605_lx45t_wishbone/src/wishbone/block_test_generate/block_generate_wb_burst_slave.v=0*2890089*2891722
e:/prog/pcie_ds_dma/trunk/projects/sp605_lx45t_wishbone/src/wishbone/cross/wb_conmax_arb.v_wb_conmax_defines.v_wb_conmax_master_if.v_wb_conmax_msel.v_wb_conmax_pri_dec.v_wb_conmax_pri_enc.v_wb_conmax_rf.v_wb_conmax_slave_if.v_wb_conmax_top.v=0*3027158*3078177
 
[~MFT]
0=983|0sp605_lx45t_wishbone.mgf|2597329|307388
1=549|1sp605_lx45t_wishbone.mgf|15332937|10532072
3=499|3sp605_lx45t_wishbone.mgf|1734685|1258097
0=1145|0sp605_lx45t_wishbone.mgf|3106526|522529
1=742|1sp605_lx45t_wishbone.mgf|19070299|14346565
3=688|3sp605_lx45t_wishbone.mgf|2229941|1742363
 
[~U]
$root=12|0*2164646|
$root=12|0*2892387|
axi_basic_rx=11|0*841130|
axi_basic_rx_null_gen=11|0*848590|
axi_basic_rx_pipeline=11|0*856990|
1204,13 → 1206,13
axi_basic_tx=11|0*880219|
axi_basic_tx_pipeline=11|0*888712|
axi_basic_tx_thrtl_ctl=11|0*898931|
block_check_wb_burst_slave=12|0*2153953||0x90
block_check_wb_burst_slave=12|0*2881568||0x90
block_check_wb_config_slave=11|0*2033037|
block_check_wb_config_slave_pkg=3|0*2031030|0*2031169
block_check_wb_pkg=3|0*2024757|0*2024857
block_generate_wb_burst_slave=12|0*2158866||0x90
block_generate_wb_config_slave=11|0*1998789|
block_generate_wb_config_slave_pkg=3|0*1996956|0*1997104
block_generate_wb_burst_slave=12|0*2886607||0x90
block_generate_wb_config_slave=11|0*2667975|
block_generate_wb_config_slave_pkg=3|0*2666092|0*2666240
block_generate_wb_pkg=3|0*2005286|0*2005395
block_pe_fifo_ext=11|0*729016|
block_pe_fifo_ext_pkg=3|0*727740|0*727849
1231,7 → 1233,7
cmd_sim_pkg=3|0*284719|0*285085
core64_interrupt=11|0*397517|
core64_interrupt_pkg=3|0*396616|0*396722
core64_pb_disp=11|0*401422|
core64_pb_disp=11|0*2873819|
core64_pb_disp_pkg=3|0*400363|0*400463
core64_pb_transaction=11|0*1388662|
core64_pb_transaction_pkg=3|0*1387487|0*1387608
1253,7 → 1255,7
ctrl_ext_descriptor_pkg=3|0*675301|0*675416
ctrl_ext_ram=11|0*722075|
ctrl_ext_ram_pkg=3|0*720628|0*720722
ctrl_fifo1024x64_st_v1=11|0*1457451|
ctrl_fifo1024x64_st_v1=11|0*2866389|
ctrl_fifo512x64st_v0=11|0*472220|
ctrl_fifo64x34fw=11|0*442130|
ctrl_fifo64x37st=11|0*449653|
1308,17 → 1310,17
sp605_lx45t_wishbone_sopc_wb_pkg=3|0*2121389|0*2121531
stend_sp605_wishbone=11|0*2546229|
test_interface=3|0*208866|0*209499
test_pkg=3|0*2081810|0*2081880
test_pkg=3|0*2605044|0*2605114
trd_pkg=3|0*299909|0*299976
wb_block_pkg=3|0*2075608|0*2075690
wb_conmax_arb=12|0*2164940||0x80
wb_conmax_master_if=12|0*2168531||0x80
wb_conmax_msel=12|0*2187711||0x80
wb_conmax_pri_dec=12|0*2194398||0x80
wb_conmax_pri_enc=12|0*2191876||0x80
wb_conmax_rf=12|0*2195700||0x80
wb_conmax_slave_if=12|0*2201691||0x80
wb_conmax_top=12|0*2212906||0x90
wb_block_pkg=3|0*2597843|0*2597925
wb_conmax_arb=12|0*2892681||0x80
wb_conmax_master_if=12|0*2896272||0x80
wb_conmax_msel=12|0*2915452||0x80
wb_conmax_pri_dec=12|0*2922139||0x80
wb_conmax_pri_enc=12|0*2919617||0x80
wb_conmax_rf=12|0*2923441||0x80
wb_conmax_slave_if=12|0*2929432||0x80
wb_conmax_top=12|0*2940647||0x90
wb_conmax_top_pkg=3|0*1973900|0*1975532
xilinx_pcie_rport_m2=11|0*352636|
xilinx_pcie_rport_m2_pkg=3|0*350717|0*350835
/trunk/projects/sp605_lx45t_wishbone/library.cfg
2,3 → 2,4
sp605_lx45t_wishbone = "./sp605_lx45t_wishbone.LIB" 1349993759453
ambpex5_sx50t_wishbone = "../ambpex5_sx50t_wishbone/ambpex5_sx50t_wishbone.LIB" 1366407892258
ambpex5_v20_sx50t_core = "../ambpex5_v20_sx50t_core/ambpex5_v20_sx50t_core.LIB" 1366409138616
sp605_lx45t_core = "../sp605_lx45t_core/sp605_lx45t_core.LIB" 1374005234864
/trunk/projects/sp605_lx45t_wishbone/sp605_lx45t_wishbone.adf
9,6 → 9,7
 
[Library]
sp605_lx45t_wishbone=.\sp605_lx45t_wishbone.LIB
sp605_lx45t_wishbone_post_synthesis=.\sp605_lx45t_wishbone_post_synthesis\sp605_lx45t_wishbone_post_synthesis.lib
 
[Settings]
AccessRead=0
19,8 → 20,8
AccessReadTopLevel=1
DisableC=1
ENABLE_ADV_DATAFLOW=0
SYNTH_TOOL=MV_XST122
IMPL_TOOL=MV_ISE122
SYNTH_TOOL=MV_XST132
IMPL_TOOL=MV_ISE132
CSYNTH_TOOL=<none>
PHYSSYNTH_TOOL=<none>
FLOW_TYPE=HDL
31,9 → 32,9
ON_SERVERFARM_SIM=0
DVM_DISPLAY=NO
REFRESH_FLOW=1
FAMILY=Xilinx12x VIRTEX5
FAMILY=Xilinx13x SPARTAN6
RUN_MODE_SYNTH=0
VerilogDirsChanged=1
VerilogDirsChanged=0
WireDelay=2
NoTchkMsg=1
NoTimingChecks=1
63,6 → 64,17
VitalAccel=1
VitalGlitches=1
DisableIEEEWarnings=1
SYNTH_STATUS=warnings
IMPL_STATUS=warnings
PHYSSYNTH_STATUS=none
PCBINTERFACE_STATUS=NONE
FUNCTIONAL_SIMULATION_STATUS=
POSTSYNTHESIS_SIMULATION_STATUS=
TIMING_SIMULATION_STATUS=
FUNC_LIB=sp605_lx45t_wishbone
POST_LIB=sp605_lx45t_wishbone_post_synthesis
RUN_MODE_IMPL=0
LAST_IMPL_STATUS=warnings
 
[LocalVerilogSets]
EnableSLP=1
107,15 → 119,11
 
[$LibMap$]
sp605_lx45t_wishbone=.
Active_lib=VIRTEX5
xilinxun=VIRTEX5
UnlinkedDesignLibrary=VIRTEX5
DESIGNS=VIRTEX5
Active_lib=SPARTAN6
xilinxun=SPARTAN6
UnlinkedDesignLibrary=SPARTAN6
DESIGNS=SPARTAN6
 
[IMPLEMENTATION]
UCF=
FLOW_STEPS_RESET=0
 
[IMPLEMENTATION_XILINX12]
impl_opt(dont_run_translate)=0
impl_opt(dont_run_map)=0
124,6 → 132,8
impl_opt(dont_run_simulation)=0
impl_opt(dont_run_fit)=0
impl_opt(dont_run_bitgen)=1
impl_opt(use_partitions_in_flow)=0
impl_opt(partitions_file)=synthesis\xpartition.pxml
 
[HierarchyViewer]
SortInfo=u
196,6 → 206,9
wishbone\testbecnh\dev_wb_cross\sim=1
wishbone\testbecnh\dev_wb_cross\sim\zz_do=1
testbench\log=1
post-synthesis=1
DESIGN_STATUS=1
DESIGN_STATUS\2013_07_26_01_18=1
 
[Verilog Library]
ovi_unimacro=
202,6 → 215,329
ovi_unisim=
ovi_xilinxcorelib=
 
[SYNTHESIS]
TOPLEVEL=sp605_lx45t_wishbone
FAMILY=Xilinx13x SPARTAN6
DEVICE=6slx45tfgg484
SPEED=-3
OBSOLETE_ALIASES=1
FILTER_MESSAGES=
FSM_ENCODE=
PACK_IO_REGISTERS=Auto
SIMOUTFORM=1
AUTO_CLOSE_GUI=0
USE_DEF_UCF_FILE=1
UCF_FILENAME=
LSO_FILENAME=
HDL_INI_FILENAME=
XST_INCLUDE_PATH=src
CORES_SEARCH_DIR=
OTHER_COMMAND_LINE_OPT=
XST_WORK_DIR=synthesis\xst
PARTITIONS_FILE=
Show_OptimizationGoalCombo=Speed
Show_OptimizationEffortCombo=Normal
Show_KeepHierarchyFPGA=Yes
Show_Timing_Constraint=0
Show_FSM_Encoding_Algorithm=Auto
Show_MuxExtractionCombo=Yes
Show_Resource_Sharing=1
Show_Rom_Extraction=1
Show_Ram_Extraction=1
Show_RamStyleCombo=Auto
Show_Shift_Register_Extraction=1
Show_Add_IO_Buffer=1
Show_Equivalent_Register_Removal=0
Show_Max_Fanout=1000000
Show_Register_Duplication=0
Show_Register_Balancing=No
Show_Pack_IO_Registers_Into_IOBs=Auto
Show_Macro_Preserve=1
Show_Xor_Preserve=1
Show_WysiwygCombo=None
Show_Case_Implementation_Style=None
Show_Global_Optimalization_Goal=AllClockNets
Show_JobDescription=SynthesisTask
Show_IncludeInputFiles=*.*
Show_ExcludeInputFiles=log*.*:implement*.*
Show_UseSynthesisConstraintsFile=1
Show_CrossClockAnalysis=0
Show_HierarchySeparator=/
Show_BusDelimiter=<>
Show_GenerateRtlSchematic=Yes
Show_CaseVhdl=Maintain
Show_Verilog2001=1
Show_RomStyle=Auto
Show_ReadCores=1
Show_MaxNoBufgs16=0
Show_OptimizeInstantiatedPrimitives=0
Show_MoveFirstFlipFlopStage=<none>
Show_MoveLastFlipFlopStage=<none>
Show_FSMStyle=LUT
Show_SimulationOutputFormat=1
Show_KeepHierarchyCPLD=Yes
Show_SafeImplementation=No
Show_UseClockEnable=Auto
Show_UseSynchronousSet=Auto
Show_UseSynchronousReset=Auto
Show_FilterMessages=0
Show_DspUtilizationRatio=100
Show_LUT_FF_PairsUtilizationRatio=100
Show_PowerReduction=0
Show_BRAMUtilizationRatio=100
Show_AutomaticBRAMPacking=0
Show_AsynchronousToSynchronous=0
Show_NetlistHierarchy=As Optimized
Show_LUTCombining=Auto
Show_ReduceControlSets=Auto
Show_UseIseWithPartitions=0
Show_GenerateIseWithPartitions=1
Show_Add_Special_Library_Sources=1
Show_UseDSPBlock_S6_V6=Auto
Show_ShiftRegisterMinimumSize=2
Show_OptimizationEffortCombo_Fast=High
RAM_STYLE=Auto
ROM_STYLE=Auto
MUX_STYLE=Auto
MOVE_FIRST_FF_STAGE=1
MOVE_LAST_FF_STAGE=1
JOB_DESCRIPTION=SynthesisTask
SERVERFARM_INCLUDE_INPUT_FILES=*.*
SERVERFARM_EXCLUDE_INPUT_FILES=log*.*:implement*.*
JOB_SFM_RESOURCE=
LAST_RUN=1374786428
OUTPUT_NETLIST=synthesis\sp605_lx45t_wishbone.ngc
OUTPUT_SIMUL_NETLIST=synthesis\sp605_lx45t_wishbone.vhd
 
[PHYS_SYNTHESIS]
FAMILY=Xilinx13x SPARTAN6
DEVICE=6slx45tfgg484
SPEED=-3
SCRIPTS_COPIED=0
IN_DESIGN=synthesis\sp605_lx45t_wishbone.ngc
OUT_DESIGN=
IN_CONSTRAINT=
OUT_CONSTRAINT=
REPORT=
 
[IMPLEMENTATION]
FLOW_STEPS_RESET=0
FAMILY=Xilinx13x SPARTAN6
DEVICE=6slx45tfgg484
SPEED=-3
NETLIST=synthesis\sp605_lx45t_wishbone.ngc
IS_BAT_MODE=0
BAT_FILE=
UCF=src\top\sp605_lx45t_wishbone.ucf
DEF_UCF=2
OLD_FAMILY=Xilinx13x SPARTAN6
wasChanged_Change_Device_Speed=0
wasChanged_Change_Device_Speed_To=0
wasChanged_Change_Device_Speed_To2=1
Place_And_Route_Mode_old_value=Route Only
JOB_DESCRIPTION=ImplementationTask
SERVERFARM_INCLUDE_INPUT_FILES=*.*
SERVERFARM_EXCLUDE_INPUT_FILES=log\*.*
JOB_SFM_RESOURCE=
SYNTH_TOOL_RESET=0
LAST_RUN=1374786709
 
[IMPLEMENTATION_XILINX13]
impl_opt(dont_run_translate)=0
impl_opt(dont_run_map)=0
impl_opt(dont_run_place)=0
impl_opt(dont_run_trace)=0
impl_opt(dont_run_simulation)=1
impl_opt(dont_run_fit)=0
impl_opt(dont_run_bitgen)=0
Macro_Search_Path={src\wishbone\coregen} {src\pcie_src\components\coregen}
impl_opt(partitions_file)=
impl_opt(use_partitions_file)=0
impl_opt(smart_guide_file)=
impl_opt(use_smart_guide)=0
impl_opt(edif_str)=synthesis\sp605_lx45t_wishbone.ngc
impl_opt(_family_sel)=Xilinx13x SPARTAN6
impl_opt(_device_sel)=6slx45tfgg484
impl_opt(_speed_sel)=-3
impl_opt(Effort_Level)=Standard
impl_opt(netlist_format)=1
impl_opt(auto_close)=0
impl_opt(override_existing_project)=1
impl_opt(bat_file_name)=
impl_opt(is_bat_mode)=0
impl_opt(def_ucf)=Custom constraint file
impl_opt(ucf_str)=src\top\sp605_lx45t_wishbone.ucf
impl_opt(version_sel)=ver1
impl_opt(revision_sel)=rev1
impl_opt(insert_pads)=0
impl_opt(Pack_IO_Registers_Latches)=For Inputs and Outputs
impl_opt(ignore_rloc_constraints)=1
impl_opt(create_detailed_report)=0
impl_opt(ngdbuild_file_str)=
impl_opt(use_ngdbuild_file)=0
impl_opt(map_file_str)=
impl_opt(use_map_file)=0
impl_opt(par_file_str)=
impl_opt(use_par_file)=0
impl_opt(trace_file_str)=
impl_opt(use_trace_file)=0
impl_opt(netgen_file_str)=
impl_opt(use_netgen_file)=0
impl_opt(bitgen_file_str)=
impl_opt(use_bitgen_file)=0
impl_opt(Allow_Unmatched_LOC_Constraint)=1
impl_opt(Show_Trim_Unconnected_Signals)=1
impl_opt(Place_And_Route_Mode)=Route Only
impl_opt(Show_Generate_Multiple_Hierarchical_Netlist_Files)=0
impl_opt(Show_Bring_Out_Global_Trisate_Net_As_Ports)=
impl_opt(Use_Show_Bring_Out_Global_Trisate_Net_As_Ports)=0
impl_opt(Show_Bring_Out_Global_Set_Reset_Net_As_Ports)=
impl_opt(Use_Show_Bring_Out_Global_Set_Reset_Net_As_Ports)=0
impl_opt(Show_Generate_Testbench_File)=UUT
impl_opt(Use_Show_Generate_Testbench_File)=0
impl_opt(Netlist_Translation_Type)=Timestamp
impl_opt(Allow_Unexpanded_Blocks)=0
impl_opt(Other_Ngdbuild_Options)=
impl_opt(Map_Effort_Level)=High
impl_opt(Allow_Logic_Opt_Across_Hier)=1
impl_opt(Use_Rloc_Constraints)=Yes
impl_opt(Show_Map_Slice_Logic_Into_Unused_Blocks)=0
impl_opt(Other_Map_Options)=
impl_opt(Extra_Effort)=None
impl_opt(Retain_Hiearchy)=1
impl_opt(Change_Device_Speed)=3
impl_opt(Tristate_Configuration_Pulsee)=0
impl_opt(Reset_Configuration_Pulsee)=100
impl_opt(Generate_Architecture_Only)=0
impl_opt(Include_Uselib_Directive)=0
impl_opt(Do_Not_Escape_Signal)=0
impl_opt(Other_Netgen_Command)=
impl_opt(Show_Other_Place_Route_Command)=
impl_opt(Use_Rules_File_For_Nelist)=
impl_opt(Path_Used_In_Sdf)=implement
impl_opt(Insert_ChipScope_Core)=0
impl_opt(Run_ChipScope_Core_Inserter_GUI)=1
impl_opt(ChipScope_Core_Inserter_Project_File)=synthesis\sp605_lx45t_wishbone.cdc
impl_opt(_use_filter_messages)=0
impl_opt(_filter_messages)=
impl_opt(AdvMap_Extra_Effort)=None
impl_opt(Map_Starting_Placer_Cost_Table)=1
impl_opt(Show_Register_Duplication)=0
impl_opt(Include_Function_In_Verilog_File)=1
impl_opt(Include_Simprim_Models_In_Verilog_File)=0
impl_opt(Show_Equivalent_Register_Removal)=1
impl_opt(run_design_rules_checker)=1
impl_opt(create_bit_file)=1
impl_opt(create_binary_config_file)=0
impl_opt(create_ascii_config_file)=0
impl_opt(create_ieee_1532_config_file_fpga)=0
impl_opt(enable_bitstream_compression)=1
impl_opt(enable_debugging_of_serial_mode_bitstream)=0
impl_opt(enable_cyclic_redundancy_checking)=1
impl_opt(other_bitgen_command_line_options)=
impl_opt(security)=Enable Readback and Reconfiguration
impl_opt(create_readback_data_files)=0
impl_opt(allow_selectmap_pins_to_persist)=0
impl_opt(create_logic_allocation_file)=0
impl_opt(create_mask_file)=0
impl_opt(encrypt_bitstream)=0
impl_opt(key_0)=
impl_opt(input_encryption_key_file)=
impl_opt(starting_cbc_value)=
impl_opt(fpga_start_up_clock)=CCLK
impl_opt(enable_internal_done_pipe)=0
impl_opt(done_output_events)=4
impl_opt(enable_outputs)=5
impl_opt(release_write_enable)=6
impl_opt(drive_done_pin_high)=1
impl_opt(configuration_rate)=2
impl_opt(configuration_pin_program)=Pull Up
impl_opt(configuration_pin_done)=Pull Up
impl_opt(jtag_pin_tck)=Pull Up
impl_opt(jtag_pin_tdi)=Pull Up
impl_opt(jtag_pin_tdo)=Pull Up
impl_opt(jtag_pin_tms)=Pull Up
impl_opt(unused_iob_pins)=Pull Up
impl_opt(userid_code)=0xFFFFFFFF
impl_opt(merge_netlists_before_insertion)=1
impl_opt(chipscope_bat_file_str)=
impl_opt(use_chipscope_bat_file)=0
impl_opt(Rename_Top_Level_Architecture_to)=Structure
impl_opt(Rename_Top_Level_Entity_to)=
impl_opt(Rename_Top_Level_Module_to)=
impl_opt(Combinatorial_Logic_Optimization)=1
impl_opt(Generate_Asynchronous_Delay_Report)=0
impl_opt(Generate_Clock_Region_Report)=0
impl_opt(Power_Reduction_Par)=0
impl_opt(Enable_Incremental_Design_Flow)=0
impl_opt(Run_Guided_Incremental_Design_Flow)=0
impl_opt(Report_Type)=Verbose report
impl_opt(Number_of_items_in_Error_Verbose_Report)=3
impl_opt(Perform_Advanced_Analysis)=0
impl_opt(Change_Device_Speed_To)=3
impl_opt(Report_Uncovered_Paths)=
impl_opt(Report_Fastest_Path_in_Each_Constraint)=1
impl_opt(post_map_file_str)=
impl_opt(use_post_map_file)=0
impl_opt(Report_Type2)=Error report
impl_opt(Number_of_items_in_Error_Verbose_Report2)=3
impl_opt(Perform_Advanced_Analysis2)=0
impl_opt(Change_Device_Speed_To2)=3
impl_opt(Report_Uncovered_Paths2)=
impl_opt(Report_Fastest_Path_in_Each_Constraint2)=1
impl_opt(Stamp_Timing_Model_Filename)=
impl_opt(Constraints_Interaction_Report_File2)=
impl_opt(dont_run_post_map_trace)=1
impl_opt(automatically_insert_glbl_module)=1
impl_opt(maximum_compression)=0
impl_opt(Output_Extended_Identifiers)=0
impl_opt(enable_suspend_wake_global_set_reset)=0
impl_opt(drive_awake_pin_during_suspend_wake_sequence)=0
impl_opt(wakeup_control)=Startup Clock
impl_opt(gwe_cycle_during_suspend_wakeup_sequence)=5
impl_opt(gts_cycle_during_suspend_wakeup_sequence)=4
impl_opt(ChipScope_Overwrite_Project_File)=0
impl_opt(insert_buffers_to_prevent_pulse_swallowing)=1
impl_opt(Report_Paths_By_Endpoint)=3
impl_opt(Generate_Datasheet_Section)=1
impl_opt(Generate_Timegroups_Section)=0
impl_opt(Constraints_Interaction_Report_File)=
impl_opt(Ignore_User_Timing_Constraints_Map)=0
impl_opt(Power_Activity_File_Map)=
impl_opt(Ignore_User_Timing_Constraints_Par)=0
impl_opt(Timing_Mode_Par)=Performance Evaluation
impl_opt(Power_Activity_File_Par)=
impl_opt(Report_Paths_By_Endpoint2)=3
impl_opt(Generate_Datasheet_Section2)=1
impl_opt(Generate_Timegroups_Section2)=0
impl_opt(retry_configuration_if_crc_error_occurs)=0
impl_opt(place_multiboot_settings_into_bitstream)=0
impl_opt(multiboot_starting_address_for_next_configuration)=0x00000000
impl_opt(multiboot_use_new_mode_for_next_configuration)=1
impl_opt(multiboot_next_configuration_mode)=001
impl_opt(Timing_Mode_Map_Virtex5)=Performance Evaluation
impl_opt(LUT_Combining)=Auto
impl_opt(Global_Optimization_Virtex5)=Off
impl_opt(Enable_Multi_Threading_Map)=Off
impl_opt(enable_external_master_clock)=0
impl_opt(setup_external_master_clock_division)=1
impl_opt(set_spi_configuration_bus_width)=1
impl_opt(multiboot_starting_address_for_golden_configuration)=0x00000000
impl_opt(multiboot_user_defined_register_for_failsafe_scheme)=0x0000
impl_opt(wait_for_dcm_and_pll_lock)=NoWait
impl_opt(enable_multi_pin_wake_up_suspend_mode)=0
impl_opt(mask_pins_for_multi_pin_wake_up_suspend_mode)=0x00
impl_opt(encrypt_key_select)=BBRAM
impl_opt(Watchdog_Timer_Value_Spartan6)=0xFFFF
impl_opt(Allow_Unmatched_Timing_Group_Constraints)=0
impl_opt(Extra_Cost_Tables)=0
impl_opt(Enable_Multi_Threading_Par)=Off
impl_opt(Power_Reduction_Map_Virtex6)=Off
impl_opt(Register_Ordering)=4
 
[PCB_INTERFACE]
FAMILY=
 
[Files]
pcie_src\components\block_main/block_pe_main.vhd=-1
pcie_src\components\coregen/ctrl_fifo64x34fw.ngc=-1
224,6 → 560,7
pcie_src\components\pcie_core/pcie_core64_m5.vhd=-1
pcie_src\components\pcie_core/pcie_core64_m7.vhd=-1
pcie_src\components\pcie_core/pcie_core64_wishbone.vhd=-1
pcie_src\components\pcie_core/pcie_core64_wishbone_m8.vhd=-1
pcie_src\components\rtl/host_pkg.vhd=-1
pcie_src\components\rtl/core64_pb_transaction.vhd=-1
pcie_src\components\rtl/ctrl_ram16_v1.vhd=-1
362,6 → 699,14
testbench\ahdl/rx.awf=-1
testbench\ahdl/tx.awf=-1
testbench\ahdl/run_ahdl.tcl=-1
testbench\log/console_test_adm_read_8kb.log=-1
testbench\log/console_test_dsc_incorrect.log=-1
testbench\log/console_test_read 4 kB.log=-1
testbench\log/console_test_read_4kB.log=-1
testbench\log/file_id_0.log=-1
testbench\log/file_id_1.log=-1
testbench\log/file_id_2.log=-1
testbench\log/global_tc_summary.log=-1
top/sp605_lx45t_wishbone.ucf=-1
top/sp605_lx45t_wishbone_sopc_wb.vhd=-1
top/sp605_lx45t_wishbone.vhd=-1
430,6 → 775,13
wishbone\testbecnh\dev_wb_cross\sim/wb_tb_simple_ram_slave.v=-1
wishbone\testbecnh\dev_wb_cross\sim\zz_do/delete.do=-1
wishbone\testbecnh\dev_wb_cross\sim\zz_do/setup_sim.do=-1
post-synthesis/..\..\synthesis\sp605_lx45t_wishbone.vhd=-1
DESIGN_STATUS\2013_07_26_01_18/ComputerInformation.txt=-1
DESIGN_STATUS\2013_07_26_01_18/DesignInformation.txt=-1
DESIGN_STATUS\2013_07_26_01_18/DesignFiles.txt=-1
DESIGN_STATUS\2013_07_26_01_18/LibrariesList.txt=-1
DESIGN_STATUS\2013_07_26_01_18/synthesis_synthesis.dfml=-1
DESIGN_STATUS\2013_07_26_01_18/implement_ver1_rev1_implementation.dfml=-1
 
[Files.Data]
.\src\pcie_src\components\block_main\block_pe_main.vhd=VHDL Source Code
453,6 → 805,7
.\src\pcie_src\components\pcie_core\pcie_core64_m5.vhd=VHDL Source Code
.\src\pcie_src\components\pcie_core\pcie_core64_m7.vhd=VHDL Source Code
.\src\pcie_src\components\pcie_core\pcie_core64_wishbone.vhd=VHDL Source Code
.\src\pcie_src\components\pcie_core\pcie_core64_wishbone_m8.vhd=VHDL Source Code
.\src\pcie_src\components\rtl\host_pkg.vhd=VHDL Source Code
.\src\pcie_src\components\rtl\core64_pb_transaction.vhd=VHDL Source Code
.\src\pcie_src\components\rtl\ctrl_ram16_v1.vhd=VHDL Source Code
591,6 → 944,14
.\src\testbench\ahdl\rx.awf=Waveform File
.\src\testbench\ahdl\tx.awf=Waveform File
.\src\testbench\ahdl\run_ahdl.tcl=Tcl Script
.\src\testbench\log\console_test_adm_read_8kb.log=Text File
.\src\testbench\log\console_test_dsc_incorrect.log=Text File
.\src\testbench\log\console_test_read 4 kB.log=Text File
.\src\testbench\log\console_test_read_4kB.log=Text File
.\src\testbench\log\file_id_0.log=Text File
.\src\testbench\log\file_id_1.log=Text File
.\src\testbench\log\file_id_2.log=Text File
.\src\testbench\log\global_tc_summary.log=Text File
.\src\top\sp605_lx45t_wishbone.ucf=External File
.\src\top\sp605_lx45t_wishbone_sopc_wb.vhd=VHDL Source Code
.\src\top\sp605_lx45t_wishbone.vhd=VHDL Source Code
659,4 → 1020,11
.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_tb_simple_ram_slave.v=Verilog Source Code
.\src\wishbone\testbecnh\dev_wb_cross\sim\zz_do\delete.do=Macro
.\src\wishbone\testbecnh\dev_wb_cross\sim\zz_do\setup_sim.do=Macro
.\synthesis\sp605_lx45t_wishbone.vhd=VHDL Source Code
.\src\DESIGN_STATUS\2013_07_26_01_18\ComputerInformation.txt=Text File
.\src\DESIGN_STATUS\2013_07_26_01_18\DesignInformation.txt=Text File
.\src\DESIGN_STATUS\2013_07_26_01_18\DesignFiles.txt=Text File
.\src\DESIGN_STATUS\2013_07_26_01_18\LibrariesList.txt=Text File
.\src\DESIGN_STATUS\2013_07_26_01_18\synthesis_synthesis.dfml=Text File
.\src\DESIGN_STATUS\2013_07_26_01_18\implement_ver1_rev1_implementation.dfml=Text File
 
/trunk/projects/sp605_lx45t_wishbone/sp605_lx45t_wishbone.aws
4,12 → 4,14
sp605_lx45t_wishbone=sp605_lx45t_wishbone.adf
ambpex5_sx50t_wishbone=.\..\ambpex5_sx50t_wishbone\ambpex5_sx50t_wishbone.adf
ambpex5_v20_sx50t_core=.\..\ambpex5_v20_sx50t_core\ambpex5_v20_sx50t_core.adf
sp605_lx45t_core=.\..\sp605_lx45t_core\sp605_lx45t_core.adf
[Settings]
Active=ambpex5_sx50t_wishbone
Active=sp605_lx45t_wishbone
[Expand]
sp605_lx45t_wishbone=0
ambpex5_sx50t_wishbone=1
sp605_lx45t_wishbone=1
ambpex5_sx50t_wishbone=0
ambpex5_v20_sx50t_core=0
sp605_lx45t_core=1
[Browser]
sort=order
mode=none
/trunk/projects/sp605_lx45t_wishbone/compile.cfg
220,3 → 220,40
Enabled=1
[file:.\src\testbench\ahdl\run_ahdl.tcl]
Enabled=1
[file:.\src\pcie_src\components\pcie_core\pcie_core64_wishbone_m8.vhd]
Enabled=0
[file:.\src\testbench\log\console_test_adm_read_8kb.log]
Enabled=1
[file:.\src\testbench\log\console_test_dsc_incorrect.log]
Enabled=1
[file:.\src\testbench\log\console_test_read 4 kB.log]
Enabled=1
[file:.\src\testbench\log\console_test_read_4kB.log]
Enabled=1
[file:.\src\testbench\log\file_id_0.log]
Enabled=1
[file:.\src\testbench\log\file_id_1.log]
Enabled=1
[file:.\src\testbench\log\file_id_2.log]
Enabled=1
[file:.\src\testbench\log\global_tc_summary.log]
Enabled=1
[file:.\synthesis\sp605_lx45t_wishbone.vhd]
Enabled=1
LIB=sp605_lx45t_wishbone_post_synthesis
SIM.POST.INCLUDED=1
SIM.FUNC.INCLUDED=0
SIM.POST.AUTO=1
SIM.POST.INDEX=0
[file:.\src\DESIGN_STATUS\2013_07_26_01_18\ComputerInformation.txt]
Enabled=1
[file:.\src\DESIGN_STATUS\2013_07_26_01_18\DesignInformation.txt]
Enabled=1
[file:.\src\DESIGN_STATUS\2013_07_26_01_18\DesignFiles.txt]
Enabled=1
[file:.\src\DESIGN_STATUS\2013_07_26_01_18\LibrariesList.txt]
Enabled=1
[file:.\src\DESIGN_STATUS\2013_07_26_01_18\synthesis_synthesis.dfml]
Enabled=1
[file:.\src\DESIGN_STATUS\2013_07_26_01_18\implement_ver1_rev1_implementation.dfml]
Enabled=1
/trunk/projects/sp605_lx45t_wishbone/src/testbench/test_pkg.vhd
32,49 → 32,54
--! Initialising
procedure test_init(
 
fname: in string --! file name for report
);
--! Finished
procedure test_close;
 
--! Read registers
procedure test_read_reg (
signal cmd: out bh_cmd; --! command
signal ret: in bh_ret --! answer
);
--! Start DMA with incorrect descriptor
procedure test_dsc_incorrect (
 
 
signal cmd: out bh_cmd; --! command
signal ret: in bh_ret --! answer
);
 
--! Start DMA for one block 4 kB
procedure test_read_4kb (
 
 
signal cmd: out bh_cmd; --! command
signal ret: in bh_ret --! answer
);
 
--! Read block_test_check 8 kB
procedure test_adm_read_8kb (
 
 
signal cmd: out bh_cmd; --! command
signal ret: in bh_ret --! answer
);
 
 
--procedure test_block_main (
 
 
-- signal cmd: out bh_cmd; --! command
-- signal ret: in bh_ret --! answer
-- );
--
 
--procedure test_adm_read_16kb (
 
 
-- signal cmd: out bh_cmd; --! command
-- signal ret: in bh_ret --! answer
-- );
--
 
procedure test_adm_write_16kb (
 
 
signal cmd: out bh_cmd; --! command
signal ret: in bh_ret --! answer
);
---------------------------------------------------------------------------------------------------
--
81,22 → 86,22
--
--
procedure test_num_1(
 
 
signal cmd: out bh_cmd; --! command
signal ret: in bh_ret --! answer
);
procedure test_num_2(
 
 
signal cmd: out bh_cmd; --! command
signal ret: in bh_ret --! answer
);
-- ==> TEST_CHECK.WB_CFG_SLAVE
procedure test_wb_1(
 
 
signal cmd: out bh_cmd; --! command
signal ret: in bh_ret --! answer
);
-- ==> TEST_GEN.WB_CFG_SLAVE
procedure test_wb_2(
 
 
signal cmd: out bh_cmd; --! command
signal ret: in bh_ret --! answer
);
end package test_pkg;
---------------------------------------------------------------------------------------------------
151,11 → 156,70
end test_close;
--! Read registers
procedure test_read_reg (
signal cmd: out bh_cmd; --! command
signal ret: in bh_ret --! answer
)
is
 
variable adr : std_logic_vector( 31 downto 0 );
variable data1 : std_logic_vector( 31 downto 0 );
variable data2 : std_logic_vector( 31 downto 0 );
variable str : line;
begin
write( str, string'("TEST_READ_REG" ));
writeline( log, str );
block_write( cmd, ret, 0, 8, x"0000000F" ); -- BRD_MODE, reset off
wait for 100 ns;
--block_read( cmd, ret, 4, 23, x"0000A400" ); -- LOCAL_ADR
wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data1 ); -- read block id
wb_block_check_read( cmd, ret, REG_BLOCK_ID, data2 ); -- read block id
write( str, string'("BLOCK 0 ID: " )); hwrite( str, data1( 15 downto 0 ) );
writeline( log, str );
write( str, string'("BLOCK 1 ID: " )); hwrite( str, data2( 15 downto 0 ) );
writeline( log, str );
wb_read( cmd, ret, 16#1000#, data1 );
wb_read( cmd, ret, 16#3000#, data1 );
 
write( str, string'("0x1000: " )); hwrite( str, data1( 15 downto 0 ) );
writeline( log, str );
write( str, string'("0x3000: " )); hwrite( str, data2( 15 downto 0 ) );
writeline( log, str );
block_write( cmd, ret, 0, 8, x"00000000" ); -- BRD_MODE
wait for 100 ns;
block_write( cmd, ret, 0, 8, x"0000000F" ); -- BRD_MODE
wait for 100 ns;
 
wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data1 ); -- read block id
wb_block_check_read( cmd, ret, REG_BLOCK_ID, data2 ); -- read block id
write( str, string'("BLOCK 0 ID: " )); hwrite( str, data1( 15 downto 0 ) );
writeline( log, str );
write( str, string'("BLOCK 1 ID: " )); hwrite( str, data2( 15 downto 0 ) );
writeline( log, str );
end test_read_reg;
--! Start DMA with incorrect descriptor
procedure test_dsc_incorrect (
 
 
signal cmd: out bh_cmd; --! command
signal ret: in bh_ret --! answer
)
is
 
167,6 → 231,9
write( str, string'("TEST_DSC_INCORRECT" ));
writeline( log, str );
block_write( cmd, ret, 0, 8, x"0000000F" ); -- BRD_MODE, reset off
wait for 100 ns;
---- Init block of descriptor ---
for ii in 0 to 127 loop
adr:= x"00100000";
209,8 → 276,8
 
--! Start DMA for one block 4 kB
procedure test_read_4kb (
 
 
signal cmd: out bh_cmd; --! command
signal ret: in bh_ret --! answer
)
is
 
226,6 → 293,10
write( str, string'("TEST_READ_4KB" ));
writeline( log, str );
block_write( cmd, ret, 0, 8, x"0000000F" ); -- BRD_MODE, reset off
wait for 100 ns;
---- Init block of descriptor ---
for ii in 0 to 127 loop
adr:= x"00100000";
361,8 → 432,8
 
--! Read block_test_check 8 kB
procedure test_adm_read_8kb (
 
 
signal cmd: out bh_cmd; --! command
signal ret: in bh_ret --! answer
)
is
 
371,13 → 442,19
variable str : line;
 
variable error : integer:=0;
variable dma_complete : integer;
variable dma_complete : integer;
 
variable status : std_logic_vector( 31 downto 0 );
variable reg_block_wr : std_logic_vector( 31 downto 0 );
 
begin
write( str, string'("TEST_ADM_READ_8KB" ));
writeline( log, str );
block_write( cmd, ret, 0, 8, x"0000000F" ); -- BRD_MODE, reset off
wait for 100 ns;
---- Init block of descriptor ---
for ii in 0 to 127 loop
adr:= x"00100000";
399,12 → 476,12
 
block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE
block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
block_write( cmd, ret, 5, 8, x"00000027" ); -- DMA_MODE
block_write( cmd, ret, 5, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
block_write( cmd, ret, 4, 23, TEST_GEN_WB_BURST_SLAVE ); -- LOCAL_ADR
block_write( cmd, ret, 5, 20, x"00100000" ); -- PCI_ADRL
block_write( cmd, ret, 5, 21, x"00100000" ); -- PCI_ADRH
block_write( cmd, ret, 5, 23, TEST_GEN_WB_BURST_SLAVE ); -- LOCAL_ADR
wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000001" ); -- reset
416,13 → 493,19
wb_block_gen_write( cmd, ret, REG_TEST_GEN_SIZE, x"00000001" ); -- size of block = 4 kByte
 
block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
block_write( cmd, ret, 5, 9, x"00000001" ); -- DMA_CTRL - START
wb_block_gen_read( cmd, ret, REG_TEST_GEN_STATUS, status ); -- read status
write( str, string'("WB_GEN_STATUS: " )); hwrite( str, status( 31 downto 0 ) ); writeline( log, str );
wb_block_gen_read( cmd, ret, REG_TEST_GEN_BL_WR, reg_block_wr ); -- read block_wr
write( str, string'("WB_GEN_BL_WR: " )); hwrite( str, reg_block_wr( 31 downto 0 ) ); writeline( log, str );
wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"000006A0" ); -- start test sequence
wait for 20 us;
block_read( cmd, ret, 4, 16, data ); -- STATUS
block_read( cmd, ret, 5, 16, data ); -- STATUS
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
if( data( 8 )='1' ) then
440,13 → 523,13
dma_complete := 0;
for ii in 0 to 100 loop
block_read( cmd, ret, 4, 16, data ); -- STATUS
block_read( cmd, ret, 5, 16, data ); -- STATUS
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
if( data(5)='1' ) then
write( str, string'(" - DMA finished " ));
dma_complete := 1;
block_write( cmd, ret, 4, 16#11#, x"00000010" ); -- FLAG_CLR - reset EOT
block_write( cmd, ret, 5, 16#11#, x"00000010" ); -- FLAG_CLR - reset EOT
end if;
writeline( log, str );
467,11 → 550,17
error:=error+1;
end if;
 
end if;
end if;
wb_block_gen_read( cmd, ret, REG_TEST_GEN_STATUS, status ); -- read status
write( str, string'("WB_GEN_STATUS: " )); hwrite( str, status( 31 downto 0 ) ); writeline( log, str );
wb_block_gen_read( cmd, ret, REG_TEST_GEN_BL_WR, reg_block_wr ); -- read block_wr
write( str, string'("WB_GEN_BL_WR: " )); hwrite( str, reg_block_wr( 31 downto 0 ) ); writeline( log, str );
for ii in 0 to 3 loop
block_read( cmd, ret, 4, 16, data ); -- STATUS
block_read( cmd, ret, 5, 16, data ); -- STATUS
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
writeline( log, str );
wait for 500 ns;
479,7 → 568,7
end loop;
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
block_write( cmd, ret, 5, 9, x"00000000" ); -- DMA_CTRL - STOP
write( str, string'(" Block 0 - read: " ));
writeline( log, str );
533,8 → 622,8
--
 
--procedure test_block_main (
 
 
-- signal cmd: out bh_cmd; --! command
-- signal ret: in bh_ret --! answer
-- )
--is
--
618,8 → 707,8
--
 
--procedure test_adm_read_16kb (
 
 
-- signal cmd: out bh_cmd; --! command
-- signal ret: in bh_ret --! answer
-- )
--is
--
869,8 → 958,8
--
 
procedure test_adm_write_16kb (
 
 
signal cmd: out bh_cmd; --! command
signal ret: in bh_ret --! answer
)
is
 
891,6 → 980,9
write( str, string'("TEST_ADM_WRITE_16KB" ));
writeline( log, str );
block_write( cmd, ret, 0, 8, x"0000000F" ); -- BRD_MODE, reset off
wait for 100 ns;
 
for ii in 0 to 256 loop
adr:= x"00100000";
1298,8 → 1390,8
-- My procedure for test Updated Design (test_read_4kb like refenernce)
--
procedure test_num_1 (
 
 
signal cmd: out bh_cmd; --! command
signal ret: in bh_ret --! answer
) is
variable adr : std_logic_vector( 31 downto 0 );
1435,8 → 1527,8
--
--
procedure test_num_2 (
 
 
signal cmd: out bh_cmd; --! command
signal ret: in bh_ret --! answer
) is
variable adr : std_logic_vector( 31 downto 0 );
1586,8 → 1678,8
-- ==> TEST_CHECK.WB_CFG_SLAVE
--
procedure test_wb_1 (
 
 
signal cmd: out bh_cmd; --! command
signal ret: in bh_ret --! answer
) is
variable adr : std_logic_vector( 31 downto 0 );
1749,8 → 1841,8
-- ==> TEST_GEN.WB_CFG_SLAVE
--
procedure test_wb_2 (
 
 
signal cmd: out bh_cmd; --! command
signal ret: in bh_ret --! answer
) is
variable adr : std_logic_vector( 31 downto 0 );
/trunk/projects/sp605_lx45t_wishbone/src/testbench/wb_block_pkg.vhd
1,168 → 1,206
---------------------------------------------------------------------------------------------------
--
-- Title : wb_block_pkg.vhd
-- Author : Dmitry Smekhov
-- Company : Instrumental Systems
-- E-mail : dsmv@insys.ru
--
-- Version : 1.0
---------------------------------------------------------------------------------------------------
--
 
--
---------------------------------------------------------------------------------------------------
--
-- Version 1.0 01.11.2011
 
--
---------------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
 
library work;
use work.cmd_sim_pkg.all;
 
use std.textio.all;
use std.textio;
 
---------------------------------------------------------------------------------------------------
package wb_block_pkg is
--
-- Define TEST_CHECK reg id (addr in 64b cells)
--
constant REG_BLOCK_ID : integer:=0;
constant REG_BLOCK_VER : integer:=1;
 
constant REG_TEST_CHECK_CTRL : integer:=8;
constant REG_TEST_CHECK_SIZE : integer:=9;
constant REG_TEST_CHECK_ERR_ADR : integer:=16#0A#;
constant REG_TEST_CHECK_WBS_BURST_CTRL : integer:=16#0B#;
 
constant REG_TEST_CHECK_BL_RD : integer:=16#10#;
constant REG_TEST_CHECK_BL_OK : integer:=16#11#;
constant REG_TEST_CHECK_BL_ERROR : integer:=16#12#;
constant REG_TEST_CHECK_TOTAL_ERROR : integer:=16#13#;
constant REG_TEST_CHECK_ERR_DATA : integer:=16#14#;
--
-- Define TEST_GEN reg id (addr in 64b cells)
--
constant REG_TEST_GEN_CTRL : integer:=8;
constant REG_TEST_GEN_SIZE : integer:=9;
constant REG_TEST_GEN_CNT1 : integer:=16#0A#;
constant REG_TEST_GEN_CNT2 : integer:=16#0B#;
constant REG_TEST_GEN_BL_WR : integer:=16#11#;
--
-- Define SoPC ADDR (must be EQU to: ...\src\top\sp605_lx45t_wishbone_sopc_wb.vhd)
--
constant TEST_CHECK_WB_CFG_SLAVE : std_logic_vector( 31 downto 0) := x"20000000";
constant TEST_CHECK_WB_BURST_SLAVE : std_logic_vector( 31 downto 0) := x"20001000"; -- check data: write-only
constant TEST_GEN_WB_CFG_SLAVE : std_logic_vector( 31 downto 0) := x"20002000";
constant TEST_GEN_WB_BURST_SLAVE : std_logic_vector( 31 downto 0) := x"20003000"; -- generate data: read-only
 
 
procedure wb_block_check_write (
 
 
 
 
);
 
 
procedure wb_block_check_read (
 
 
 
 
);
 
 
procedure wb_block_gen_write (
 
 
 
 
);
 
 
procedure wb_block_gen_read (
 
 
 
 
);
-- Construct value for REG_TEST_CHECK_WBS_BURST_CTRL
function wb_block_check_burst_ctrl_build (i_ena : in std_logic; ii_ack_dly : in integer; ii_dly_pos : in integer) return std_logic_vector;
 
end package wb_block_pkg;
---------------------------------------------------------------------------------------------------
package body wb_block_pkg is
 
 
procedure wb_block_check_write (
 
 
 
 
) is
begin
data_write( cmd, ret, TEST_CHECK_WB_CFG_SLAVE+conv_std_logic_vector(reg*8+0, 32), data );
end;
 
 
procedure wb_block_check_read (
 
 
 
 
) is
begin
data_read( cmd, ret, TEST_CHECK_WB_CFG_SLAVE+conv_std_logic_vector(reg*8+0, 32), data );
end;
 
 
procedure wb_block_gen_write (
 
 
 
 
) is
begin
data_write( cmd, ret, TEST_GEN_WB_CFG_SLAVE+conv_std_logic_vector(reg*8+0, 32), data );
end;
 
 
procedure wb_block_gen_read (
 
 
 
 
) is
begin
data_read( cmd, ret, TEST_GEN_WB_CFG_SLAVE+conv_std_logic_vector(reg*8+0, 32), data );
end;
 
-- Construct value for REG_TEST_CHECK_WBS_BURST_CTRL
function wb_block_check_burst_ctrl_build (i_ena : in std_logic; ii_ack_dly : in integer; ii_dly_pos : in integer) return std_logic_vector is
variable iv_ret : std_logic_vector(31 downto 0):=(others => '0');
begin
iv_ret:= x"0000" & i_ena & conv_std_logic_vector( ii_ack_dly, 6) & conv_std_logic_vector( ii_dly_pos, 9);
return iv_ret;
end wb_block_check_burst_ctrl_build;
 
 
end package body wb_block_pkg;
 
---------------------------------------------------------------------------------------------------
--
-- Title : wb_block_pkg.vhd
-- Author : Dmitry Smekhov
-- Company : Instrumental Systems
-- E-mail : dsmv@insys.ru
--
-- Version : 1.0
---------------------------------------------------------------------------------------------------
--
 
--
---------------------------------------------------------------------------------------------------
--
-- Version 1.0 01.11.2011
 
--
---------------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
 
library work;
use work.cmd_sim_pkg.all;
 
use std.textio.all;
use std.textio;
 
---------------------------------------------------------------------------------------------------
package wb_block_pkg is
--
-- Define TEST_CHECK reg id (addr in 64b cells)
--
constant REG_BLOCK_ID : integer:=0;
constant REG_BLOCK_VER : integer:=1;
 
constant REG_TEST_CHECK_CTRL : integer:=8;
constant REG_TEST_CHECK_SIZE : integer:=9;
constant REG_TEST_CHECK_ERR_ADR : integer:=16#0A#;
constant REG_TEST_CHECK_WBS_BURST_CTRL : integer:=16#0B#;
 
constant REG_TEST_CHECK_BL_RD : integer:=16#10#;
constant REG_TEST_CHECK_BL_OK : integer:=16#11#;
constant REG_TEST_CHECK_BL_ERROR : integer:=16#12#;
constant REG_TEST_CHECK_TOTAL_ERROR : integer:=16#13#;
constant REG_TEST_CHECK_ERR_DATA : integer:=16#14#;
--
-- Define TEST_GEN reg id (addr in 64b cells)
--
constant REG_TEST_GEN_CTRL : integer:=8;
constant REG_TEST_GEN_SIZE : integer:=9;
constant REG_TEST_GEN_CNT1 : integer:=16#0A#;
constant REG_TEST_GEN_CNT2 : integer:=16#0B#;
constant REG_TEST_GEN_STATUS : integer:=16#10#;
constant REG_TEST_GEN_BL_WR : integer:=16#11#;
--
-- Define SoPC ADDR (must be EQU to: ...\src\top\sp605_lx45t_wishbone_sopc_wb.vhd)
--
constant TEST_CHECK_WB_CFG_SLAVE : std_logic_vector( 31 downto 0) := x"20000000";
constant TEST_CHECK_WB_BURST_SLAVE : std_logic_vector( 31 downto 0) := x"20001000"; -- check data: write-only
constant TEST_GEN_WB_CFG_SLAVE : std_logic_vector( 31 downto 0) := x"20002000";
constant TEST_GEN_WB_BURST_SLAVE : std_logic_vector( 31 downto 0) := x"20003000"; -- generate data: read-only
---- Write to wishbone ----
procedure wb_write (
 
 
 
 
);
---- Read from wishbone ----
procedure wb_read (
 
 
 
 
);
 
procedure wb_block_check_write (
 
 
 
 
);
 
 
procedure wb_block_check_read (
 
 
 
 
);
 
 
procedure wb_block_gen_write (
 
 
 
 
);
 
 
procedure wb_block_gen_read (
 
 
 
 
);
-- Construct value for REG_TEST_CHECK_WBS_BURST_CTRL
function wb_block_check_burst_ctrl_build (i_ena : in std_logic; ii_ack_dly : in integer; ii_dly_pos : in integer) return std_logic_vector;
 
end package wb_block_pkg;
---------------------------------------------------------------------------------------------------
package body wb_block_pkg is
---- Write to wishbone ----
procedure wb_write (
 
 
 
 
) is
begin
data_write( cmd, ret, TEST_CHECK_WB_CFG_SLAVE+conv_std_logic_vector(adr, 32), data );
end;
---- Read from wishbone ----
procedure wb_read (
 
 
 
 
) is
begin
data_read( cmd, ret, TEST_CHECK_WB_CFG_SLAVE+conv_std_logic_vector(adr, 32), data );
end;
 
 
procedure wb_block_check_write (
 
 
 
 
) is
begin
data_write( cmd, ret, TEST_CHECK_WB_CFG_SLAVE+conv_std_logic_vector(reg*8+0, 32), data );
end;
 
 
procedure wb_block_check_read (
 
 
 
 
) is
begin
data_read( cmd, ret, TEST_CHECK_WB_CFG_SLAVE+conv_std_logic_vector(reg*8+0, 32), data );
end;
 
 
procedure wb_block_gen_write (
 
 
 
 
) is
begin
data_write( cmd, ret, TEST_GEN_WB_CFG_SLAVE+conv_std_logic_vector(reg*8+0, 32), data );
end;
 
 
procedure wb_block_gen_read (
 
 
 
 
) is
begin
data_read( cmd, ret, TEST_GEN_WB_CFG_SLAVE+conv_std_logic_vector(reg*8+0, 32), data );
end;
 
-- Construct value for REG_TEST_CHECK_WBS_BURST_CTRL
function wb_block_check_burst_ctrl_build (i_ena : in std_logic; ii_ack_dly : in integer; ii_dly_pos : in integer) return std_logic_vector is
variable iv_ret : std_logic_vector(31 downto 0):=(others => '0');
begin
iv_ret:= x"0000" & i_ena & conv_std_logic_vector( ii_ack_dly, 6) & conv_std_logic_vector( ii_dly_pos, 9);
return iv_ret;
end wb_block_check_burst_ctrl_build;
 
 
end package body wb_block_pkg;
 
/trunk/projects/sp605_lx45t_wishbone/src/testbench/stend_sp605_wishbone.vhd
204,6 → 204,7
when 0 => test_dsc_incorrect( cmd, ret );
when 1 => test_read_4kb( cmd, ret ); -- was original
when 2 => test_adm_read_8kb( cmd, ret );
when 3 => test_read_reg( cmd, ret );
--when 3 => test_adm_read_16kb( cmd, ret );
--when 4 => test_adm_write_16kb( cmd, ret );
--when 5 => test_block_main( cmd, ret );
/trunk/projects/sp605_lx45t_wishbone/src/top/sp605_lx45t_wishbone.ucf
150,46 → 150,35
# End
###############################################################################
 
#INST "amb/gen_syn.pcie/core/reg" AREA_GROUP = "pblock_reg";
#AREA_GROUP "pblock_reg" RANGE=SLICE_X20Y89:SLICE_X25Y95;
#INST "amb/gen_syn.pcie/core/int" AREA_GROUP = "pblock_int";
#AREA_GROUP "pblock_int" RANGE=SLICE_X26Y88:SLICE_X29Y95;
#INST "amb/gen_syn.pcie/core/tx" AREA_GROUP = "pblock_tx";
#AREA_GROUP "pblock_tx" RANGE=SLICE_X8Y96:SLICE_X13Y111;
#INST "amb/gen_syn.pcie/core/disp" AREA_GROUP = "pblock_disp";
#AREA_GROUP "pblock_disp" RANGE=SLICE_X20Y80:SLICE_X25Y87;
#INST "amb/gen_syn.pcie/core/fifo" AREA_GROUP = "pblock_fifo";
#AREA_GROUP "pblock_fifo" RANGE=SLICE_X8Y80:SLICE_X19Y95, SLICE_X0Y64:SLICE_X7Y95;
#AREA_GROUP "pblock_fifo" RANGE=DSP48_X0Y16:DSP48_X0Y23;
#AREA_GROUP "pblock_fifo" RANGE=RAMB16_X1Y40:RAMB16_X1Y46, RAMB16_X0Y32:RAMB16_X0Y46;
#AREA_GROUP "pblock_fifo" RANGE=RAMB8_X1Y40:RAMB8_X1Y47, RAMB8_X0Y32:RAMB8_X0Y47;
#INST "amb/gen_syn.pcie/core/ep" AREA_GROUP = "pblock_ep";
#AREA_GROUP "pblock_ep" RANGE=SLICE_X0Y112:SLICE_X3Y125;
#AREA_GROUP "pblock_ep" RANGE=RAMB16_X0Y48:RAMB16_X0Y62;
#AREA_GROUP "pblock_ep" RANGE=RAMB8_X0Y48:RAMB8_X0Y63;
#INST "amb/gen_syn.pcie/main" AREA_GROUP = "pblock_main";
#AREA_GROUP "pblock_main" RANGE=SLICE_X26Y80:SLICE_X29Y86;
#INST "amb/gen_syn.pcie/tz" AREA_GROUP = "pblock_tz";
#AREA_GROUP "pblock_tz" RANGE=SLICE_X20Y75:SLICE_X29Y79;
#INST "amb/gen_syn.blink" AREA_GROUP = "pblock_gen_syn.blink";
#AREA_GROUP "pblock_gen_syn.blink" RANGE=SLICE_X4Y112:SLICE_X7Y119;
#INST "amb/gen_syn.ad" AREA_GROUP = "pblock_gen_syn.ad";
#AREA_GROUP "pblock_gen_syn.ad" RANGE=SLICE_X20Y64:SLICE_X29Y74, SLICE_X8Y64:SLICE_X19Y79;
#AREA_GROUP "pblock_gen_syn.ad" RANGE=RAMB16_X1Y38:RAMB16_X1Y38, RAMB16_X1Y32:RAMB16_X1Y34;
#AREA_GROUP "pblock_gen_syn.ad" RANGE=RAMB8_X1Y38:RAMB8_X1Y39, RAMB8_X1Y32:RAMB8_X1Y35;
#INST "test_ctrl" AREA_GROUP = "pblock_test_ctrl";
#AREA_GROUP "pblock_test_ctrl" RANGE=SLICE_X0Y16:SLICE_X27Y47;
#INST "dio_in" AREA_GROUP = "pblock_dio_in";
#AREA_GROUP "pblock_dio_in" RANGE=SLICE_X0Y48:SLICE_X9Y63;
#AREA_GROUP "pblock_dio_in" RANGE=DSP48_X0Y12:DSP48_X0Y15;
#AREA_GROUP "pblock_dio_in" RANGE=RAMB16_X0Y24:RAMB16_X0Y30;
#AREA_GROUP "pblock_dio_in" RANGE=RAMB8_X0Y24:RAMB8_X0Y31;
#INST "main" AREA_GROUP = "pblock_main_1";
#AREA_GROUP "pblock_main_1" RANGE=SLICE_X24Y48:SLICE_X29Y63;
#INST "dio_out" AREA_GROUP = "pblock_dio_out";
#AREA_GROUP "pblock_dio_out" RANGE=SLICE_X14Y48:SLICE_X23Y63;
#AREA_GROUP "pblock_dio_out" RANGE=RAMB16_X1Y24:RAMB16_X1Y30;
#AREA_GROUP "pblock_dio_out" RANGE=RAMB8_X1Y24:RAMB8_X1Y31;
#INST "amb/gen_syn.pcie/core/rx" AREA_GROUP = "pblock_rx";
#AREA_GROUP "pblock_rx" RANGE=SLICE_X0Y96:SLICE_X7Y111;
INST "WB_SOPC/PCIE_CORE64_WB/CORE/ep" AREA_GROUP = "pblock_ep";
AREA_GROUP "pblock_ep" RANGE=SLICE_X4Y96:SLICE_X7Y125;
AREA_GROUP "pblock_ep" RANGE=RAMB16_X0Y48:RAMB16_X0Y62;
AREA_GROUP "pblock_ep" RANGE=RAMB8_X0Y48:RAMB8_X0Y63;
INST "WB_SOPC/PCIE_CORE64_WB/CORE/rx" AREA_GROUP = "pblock_rx";
AREA_GROUP "pblock_rx" RANGE=SLICE_X8Y111:SLICE_X17Y88;
INST "WB_SOPC/PCIE_CORE64_WB/CORE/tx" AREA_GROUP = "pblock_tx";
AREA_GROUP "pblock_tx" RANGE=SLICE_X20Y88:SLICE_X29Y111;
INST "WB_SOPC/PCIE_CORE64_WB/CORE/reg" AREA_GROUP = "pblock_reg";
AREA_GROUP "pblock_reg" RANGE=SLICE_X18Y85:SLICE_X19Y95, SLICE_X12Y85:SLICE_X17Y87;
INST "WB_SOPC/PCIE_CORE64_WB/CORE/int" AREA_GROUP = "pblock_int";
AREA_GROUP "pblock_int" RANGE=SLICE_X0Y122:SLICE_X3Y125;
INST "WB_SOPC/PCIE_CORE64_WB/CORE/disp" AREA_GROUP = "pblock_disp";
AREA_GROUP "pblock_disp" RANGE=SLICE_X20Y87:SLICE_X29Y83;
INST "WB_SOPC/PCIE_CORE64_WB/CORE/fifo" AREA_GROUP = "pblock_fifo";
AREA_GROUP "pblock_fifo" RANGE=SLICE_X18Y72:SLICE_X29Y82, SLICE_X8Y72:SLICE_X17Y84, SLICE_X2Y72:SLICE_X7Y95;
AREA_GROUP "pblock_fifo" RANGE=RAMB16_X0Y36:RAMB16_X1Y46;
AREA_GROUP "pblock_fifo" RANGE=RAMB8_X0Y36:RAMB8_X1Y47;
INST "WB_SOPC/PCIE_CORE64_WB/PE_MAIN" AREA_GROUP = "pblock_PE_MAIN";
AREA_GROUP "pblock_PE_MAIN" RANGE=SLICE_X24Y119:SLICE_X29Y113;
INST "WB_SOPC/PCIE_CORE64_WB/PW_WB" AREA_GROUP = "pblock_PW_WB";
AREA_GROUP "pblock_PW_WB" RANGE=SLICE_X4Y68:SLICE_X21Y71;
INST "WB_SOPC/WB_CROSS" AREA_GROUP = "pblock_WB_CROSS";
AREA_GROUP "pblock_WB_CROSS" RANGE=SLICE_X4Y56:SLICE_X21Y67;
INST "WB_SOPC/TEST_CHECK" AREA_GROUP = "pblock_TEST_CHECK";
AREA_GROUP "pblock_TEST_CHECK" RANGE=SLICE_X4Y24:SLICE_X17Y55;
AREA_GROUP "pblock_TEST_CHECK" RANGE=RAMB16_X0Y12:RAMB16_X0Y26;
AREA_GROUP "pblock_TEST_CHECK" RANGE=RAMB8_X0Y12:RAMB8_X0Y27;
INST "WB_SOPC/TEST_GEN" AREA_GROUP = "pblock_TEST_GEN";
AREA_GROUP "pblock_TEST_GEN" RANGE=SLICE_X18Y24:SLICE_X27Y55;
AREA_GROUP "pblock_TEST_GEN" RANGE=RAMB16_X1Y12:RAMB16_X1Y26;
AREA_GROUP "pblock_TEST_GEN" RANGE=RAMB8_X1Y12:RAMB8_X1Y27;
/trunk/projects/sp605_lx45t_wishbone/src/top/sp605_lx45t_wishbone_sopc_wb.vhd
268,7 → 268,7
);
-- Construct DMAR WB IR Input:
sv_wbm_dmar_irq_pcie_core64_wb <= s_wbs_irq_dmar_test_check & s_wbs_irq_dmar_test_gen; -- Bit#1 - TEST_CHECK, Bit#0 - TEST_GEN
sv_wbm_dmar_irq_pcie_core64_wb <= s_wbs_irq_dmar_test_gen & s_wbs_irq_dmar_test_check; -- Bit#1 - TEST_GEN, Bit#0 - TEST_CHECK
-------------------------------------------------------------------------------
--
-- Instantiate TEST_CHECK (provide check of input data):
/trunk/projects/sp605_lx45t_wishbone/compilation.order
94,3 → 94,4
.\src\wishbone\cross\wb_conmax_top.v
.\src\wishbone\cross\wb_conmax_top_pkg.vhd
.\src\wishbone\coregen\ctrl_fifo1024x64_st_v1.vhd
.\synthesis\sp605_lx45t_wishbone.vhd

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