URL
https://opencores.org/ocsvn/pdp1/pdp1/trunk
Subversion Repositories pdp1
Compare Revisions
- This comparison shows the changes necessary to convert path
/pdp1/trunk
- from Rev 8 to Rev 9
- ↔ Reverse comparison
Rev 8 → Rev 9
/rtl/vhdl/pdp1cpu.vhd
32,6 → 32,7
---------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
-- Why does isim behave like unsigned+natural doesn't exist? |
use IEEE.NUMERIC_STD.ALL; |
|
|
51,7 → 52,7
-- user visible registers |
AC : inout STD_LOGIC_VECTOR(0 to 17) := (others=>'0'); -- accumulator |
IO : inout STD_LOGIC_VECTOR(0 to 17) := (others=>'0'); -- I/O |
PC : inout unsigned(0 to 11) := (others=>'0'); -- program counter |
PC : inout STD_LOGIC_VECTOR(0 to 11) := (others=>'0'); -- program counter |
PF : inout STD_LOGIC_VECTOR(1 to 6) := (others=>'0'); -- program flags |
OV : inout STD_LOGIC := '0'; -- overflow flag |
|
325,7 → 326,7
when load_instruction => -- it's our next instruction |
op <= M_DO(0 to 5); |
if op/=op_xct then -- indirect execution |
PC<=PC+1; |
PC<=std_logic_vector(unsigned(PC)+1); |
end if; |
when load_indirect => -- completing an indirect instruction |
ib <= M_DO(5); -- update indirection bit |
337,7 → 338,7
(op=op_sas and cycletype=load_data and ac_eq_mb) or |
(op=op_sad and cycletype=load_data and not ac_eq_mb) or |
FALSE then -- increase PC an extra time |
PC <= PC+1; |
PC <= std_logic_vector(unsigned(PC)+1); |
end if; |
if (op=op_skip or op=op_skipi) and szo='1' then |
OV <= '0'; -- clear overflow after checking it |
368,13 → 369,13
PC <= o"0101"; |
MA <= o"0100"; |
else |
PC <= unsigned(y)+1; |
PC <= std_logic_vector(unsigned(y)+1); |
MA <= y; |
end if; |
cycletype <= store_data; |
else |
MA <= y; |
PC <= unsigned(y); |
PC <= y; |
cycletype <= load_instruction; |
end if; |
when op_skipi|op_rotshiftr|op_lawm|op_iot_nw => |
/rtl/vhdl/top.vhd
136,7 → 136,7
IO_set : in STD_LOGIC; |
IO_IN : in STD_LOGIC_VECTOR(0 to 17); |
|
PC : inout unsigned(0 to 11); -- program counter |
PC : inout std_logic_vector(0 to 11); -- program counter |
AC, IO : inout word; |
SW_SENSE : in STD_LOGIC_VECTOR(1 to 6); |
|
158,7 → 158,7
signal sw_sense : std_logic_vector(1 to 6) := o"00"; |
signal mem_a : std_logic_vector(0 to 11) := (others=>'0'); |
|
signal pc : unsigned(0 to 11); |
signal pc : std_logic_vector(0 to 11); |
|
signal io_dopulse, io_done, io_set : std_logic := '0'; |
signal IOT : std_logic_vector(0 to 63) := (others=>'0'); |