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/pltbutils/tags/v1.3/bench/vhdl/tb_pltbutils.vhd
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----------------------------------------------------------------------
---- ----
---- PlTbUtils Testbench ----
---- ----
---- This file is part of the PlTbUtils project ----
---- http://opencores.org/project,pltbutils ----
---- ----
---- Description ----
---- PlTbUtils is a collection of functions, procedures and ----
---- components for easily creating stimuli and checking response ----
---- in automatic self-checking testbenches. ----
---- ----
---- This is a testbench file, which is used to verify ----
---- - pltbutils_func_pkg ----
---- - pltbutils_comp ----
---- This testbench is NOT selfchecking or automatic. ----
---- Manually check the transcript and waveform, when simulating. ----
---- It prints some informative text in the transcript, to help ----
---- with the manual inspection. ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Per Larsson, pela.opencores@gmail.com ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2013-2020 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.txt_util.all;
use work.pltbutils_func_pkg.all;
use work.pltbutils_comp_pkg.all;
 
entity tb_pltbutils is
generic (
G_SKIPTESTS : std_logic_vector := (
'0', -- Dummy
'0', -- Test 1
'0', -- Test 2
'0', -- Test 3
'0', -- Test 4: NonSkipTest
'1' -- Test 5: SkipTest
);
G_CLK_PERIOD : time := 10 ns;
G_CHECKFILE_VERBOSITY : integer := 10;
G_BINTESTFILE_HEADER : string := "Bintestfile R ";
G_BINTESTFILE_LEN : integer := 528;
G_BINTESTFILE_REFERENCE : string := "../../../bench/testfiles/bintestfile_reference.bin";
G_BINTESTFILE_CORRECT : string := "../../../bench/testfiles/bintestfile_correct.bin";
G_BINTESTFILE_ERROR : string := "../../../bench/testfiles/bintestfile_error.bin";
G_BINTESTFILE_SHORTER : string := "../../../bench/testfiles/bintestfile_shorter.bin";
G_BINTESTFILE_LONGER : string := "../../../bench/testfiles/bintestfile_longer.txt";
G_TEXTTESTFILE_REFERENCE : string := "../../../bench/testfiles/texttestfile_reference.txt";
G_TEXTTESTFILE_CORRECT : string := "../../../bench/testfiles/texttestfile_correct.txt";
G_TEXTTESTFILE_ERROR : string := "../../../bench/testfiles/texttestfile_error.txt";
G_TEXTTESTFILE_SHORTER : string := "../../../bench/testfiles/texttestfile_shorter.txt";
G_TEXTTESTFILE_LONGER : string := "../../../bench/testfiles/texttestfile_longer.txt";
G_DATTESTFILE_REFERENCE : string := "../../../bench/testfiles/dattestfile_reference.dat";
G_DATTESTFILE_CORRECT : string := "../../../bench/testfiles/dattestfile_correct.dat";
G_DATTESTFILE_ERROR : string := "../../../bench/testfiles/dattestfile_error.dat";
G_DATTESTFILE_SHORTER : string := "../../../bench/testfiles/dattestfile_shorter.dat";
G_DATTESTFILE_LONGER : string := "../../../bench/testfiles/dattestfile_longer.dat"
);
end entity tb_pltbutils;
 
architecture bhv of tb_pltbutils is
 
-- Simulation status- and control signals
-- for accessing .stop_sim and for viewing in waveform window
signal pltbs : pltbs_t := C_PLTBS_INIT;
 
-- Expected number of checks and number of errors to be reported
-- by pltbutils. The counting is made by variables, but the
-- variables are copied to these signals for easier viewing in
-- the simulator's waveform window.
signal expected_checks_cnt : integer := 0;
signal expected_errors_cnt : integer := 0;
-- DUT stimuli and response signals
signal clk : std_logic;
signal clk_cnt : integer := 0;
signal clk_cnt_clr : boolean := false;
signal s_i : integer;
signal s_sl : std_logic;
signal s_slv : std_logic_vector(7 downto 0);
signal s_u : unsigned(7 downto 0);
signal s_s : unsigned(7 downto 0);
signal s_b : boolean;
signal s_time : time;
signal s_str_exp : string(1 to 44);
signal s_str1 : string(1 to 44);
signal s_str2 : string(1 to 44);
signal s_str3 : string(1 to 43);
signal s_str4 : string(1 to 45);
 
 
constant C_EXPECTED_SUCCESS : boolean := false;
constant C_EXPECTED_FAIL : boolean := true;
 
procedure check_cnt (
constant C_EXPECT_FAIL : boolean;
variable v_checks_cnt : inout integer;
variable v_errors_cnt : inout integer;
signal checks_cnt : out integer;
signal errors_cnt : out integer
) is
begin
v_checks_cnt := v_checks_cnt + 1;
if C_EXPECT_FAIL then
v_errors_cnt := v_errors_cnt + 1;
end if;
checks_cnt <= v_checks_cnt;
errors_cnt <= v_errors_cnt;
end procedure check_cnt;
begin
-- Clock generator
clkgen0 : pltbutils_clkgen
generic map(
G_PERIOD => G_CLK_PERIOD
)
port map(
clk_o => clk,
stop_sim_i => pltbs.stop_sim
);
-- Clock cycle counter
p_clk_cnt : process (clk_cnt_clr, clk)
begin
if clk_cnt_clr then
clk_cnt <= 0;
elsif rising_edge(clk) then
clk_cnt <= clk_cnt + 1;
end if;
end process p_clk_cnt;
-- Testcase
p_tc1 : process
variable pltbv : pltbv_t := C_PLTBV_INIT;
variable v_expected_tests_cnt : integer := 0;
variable v_expected_skiptests_cnt : integer := 0;
variable v_expected_checks_cnt : integer := 0;
variable v_expected_errors_cnt : integer := 0;
variable v_expected_data : integer;
variable v_actual_data : integer;
variable f_status : file_open_status;
file txtfile : text;
type charfile is file of character;
file binfile : charfile;
variable l : line;
variable c : character;
variable i : integer;
variable v_errcnt : integer;
variable msg : line;
variable line_num : integer := 0;
begin
print(lf & "<Testing startsim()>");
startsim("tc1", G_SKIPTESTS, pltbv, pltbs);
wait until rising_edge(clk);
assert (pltbv.test_num = 0) and (pltbs.test_num = 0)
report "test_num after startsim() incorrect"
severity error;
print("<Done testing startsim()>");
print(lf & "<Testing starttest() with auto-incrementing test_num>");
starttest("StartTest1", pltbv, pltbs);
v_expected_tests_cnt := v_expected_tests_cnt + 1;
wait until rising_edge(clk);
assert (pltbv.test_num = 1) and (pltbs.test_num = 1)
report "test_num after starttest() incorrect"
severity error;
print("<Done testing starttest() with auto-incrementing test_num()>");
 
print(lf & "<Testing endtest()>");
endtest(pltbv, pltbs);
print("<Done testing endtest()>");
 
print(lf & "<Testing starttest() with explicit test_num>");
starttest(3, "StartTest2", pltbv, pltbs);
v_expected_tests_cnt := v_expected_tests_cnt + 1;
wait until rising_edge(clk);
assert (pltbv.test_num = 3) and (pltbs.test_num = 3)
report "test_num after startsim() incorrect"
severity error;
print("<Done testing starttest() with explicit test_num>");
 
print(lf & "<Testing starttest() and is_test_active() for non-skipped test>");
starttest(4, "NoSkipTest", pltbv, pltbs);
if is_test_active(pltbv) then
v_expected_tests_cnt := v_expected_tests_cnt + 1;
wait until rising_edge(clk);
else
v_expected_skiptests_cnt := v_expected_skiptests_cnt + 1;
wait until rising_edge(clk);
assert false
report "Executing test that should have been skipped"
severity error;
end if;
endtest(pltbv, pltbs);
print("<Done testing starttest() and is_test_active() for non-skipped test>");
 
print(lf & "<Testing starttest() and is_test_active() for skipped test>");
starttest(5, "SkipTest", pltbv, pltbs);
if is_test_active(pltbv) then
v_expected_tests_cnt := v_expected_tests_cnt + 1;
wait until rising_edge(clk);
assert false
report "Executing test that should have been skipped"
severity error;
else
--check("Checking if check() detects that it should not be called in skipped test", false, pltbv, pltbs);
v_expected_skiptests_cnt := v_expected_skiptests_cnt + 1;
end if;
endtest(pltbv, pltbs);
print("<Done testing starttest() and is_test_active() for skipped test>");
print(lf & "<Testing waitclks()>");
clk_cnt_clr <= true;
wait until rising_edge(clk);
clk_cnt_clr <= false;
wait until rising_edge(clk);
waitclks(10, clk, pltbv, pltbs);
assert clk_cnt = 10
report "clk_cnt after waitclks() incorrect:" & integer'image(clk_cnt) &
" expected:" & integer'image(10)
severity error;
print("<Done testing waitclks()>");
 
print(lf & "<Testing check() integer>");
s_i <= 0;
wait until rising_edge(clk);
check("Testing correct integer = 0", s_i, 0, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_i <= 1;
wait until rising_edge(clk);
check("Testing correct integer = 1", s_i, 1, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_i <= 17;
wait until rising_edge(clk);
check("Testing incorrect integer = 17", s_i, 18, pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_i <= -1;
wait until rising_edge(clk);
check("Testing negative integer = -1", s_i, -1, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
print("<Done testing check() integer>");
print(lf & "<Testing check() std_logic>");
s_sl <= '0';
wait until rising_edge(clk);
check("Testing correct std_logic = '0'", s_sl, '0', pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_sl <= '1';
wait until rising_edge(clk);
check("Testing correct std_logic = '1'", s_sl, '1', pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_sl <= 'X';
wait until rising_edge(clk);
check("Testing incorrect std_logic = '1'", s_sl, '1', pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
print("<Done testing check() std_logic>");
print(lf & "<Testing check() std_logic against integer>");
s_sl <= '0';
wait until rising_edge(clk);
check("Testing correct std_logic = '0'", s_sl, 0, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_sl <= '1';
wait until rising_edge(clk);
check("Testing correct std_logic = '1'", s_sl, 1, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_sl <= 'X';
wait until rising_edge(clk);
check("Testing incorrect std_logic = '1'", s_sl, 1, pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_sl <= '1';
wait until rising_edge(clk);
check("Testing std_logic = '1' with incorrect expected", s_sl, 2, pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
print("<Done testing check() std_logic against integer>");
print(lf & "<Testing check() std_logic_vector>");
s_slv <= x"00";
wait until rising_edge(clk);
check("Testing correct std_logic_vector = x'00'", s_slv, x"00", pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_slv <= x"47";
wait until rising_edge(clk);
check("Testing correct std_logic_vector = x'47'", s_slv, x"47", pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_slv <= x"11";
wait until rising_edge(clk);
check("Testing incorrect std_logic_vector = x'11'", s_slv, x"10", pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
print("<Done testing check() std_logic_vector>");
 
print(lf & "<Testing check() std_logic_vector with mask>");
s_slv <= x"47";
wait until rising_edge(clk);
check("Testing std_logic_vector = x'47' with correct nibble mask", s_slv, x"57", x"0F", pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_slv <= x"47";
wait until rising_edge(clk);
check("Testing std_logic_vector = x'47' with incorrect nibble mask", s_slv, x"57", x"F0", pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
print("<Done testing check() std_logic_vector with mask>");
print(lf & "<Testing check() std_logic_vector against integer>");
s_slv <= x"00";
wait until rising_edge(clk);
check("Testing correct std_logic_vector = x'00'", s_slv, 0, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_slv <= x"47";
wait until rising_edge(clk);
check("Testing correct std_logic_vector = x'47'", s_slv, 16#47#, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_slv <= x"11";
wait until rising_edge(clk);
check("Testing incorrect std_logic_vector = x'11'", s_slv, 16#10#, pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_slv <= x"FF";
wait until rising_edge(clk);
check("Testing negative std_logic_vector = x'FF'", s_slv, -1, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
print("<Done testing check() std_logic_vector against integer>");
 
print(lf & "<Testing check() std_logic_vector with mask against integer>");
s_slv <= x"47";
wait until rising_edge(clk);
check("Testing std_logic_vector = x'47' with correct nibble mask", s_slv, 16#57#, x"0F", pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_slv <= x"47";
wait until rising_edge(clk);
check("Testing std_logic_vector = x'47' with incorrect nibble mask", s_slv, 16#57#, x"F0", pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
print("<Done testing check() std_logic_vector with mask against integer>");
print(lf & "<Testing check() unsigned>");
s_u <= x"00";
wait until rising_edge(clk);
check("Testing correct unsigned = x'00'", s_u, x"00", pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_u <= x"47";
wait until rising_edge(clk);
check("Testing correct unsigned = x'47'", s_u, x"47", pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_u <= x"11";
wait until rising_edge(clk);
check("Testing incorrect unsigned = x'11'", s_u, x"10", pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
print("<Done testing check() unsigned>");
print(lf & "<Testing check() unsigned against integer>");
s_u <= x"00";
wait until rising_edge(clk);
check("Testing correct unsigned = x'00'", s_u, 0, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_u <= x"47";
wait until rising_edge(clk);
check("Testing correct unsigned = x'47'", s_u, 16#47#, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_u <= x"11";
wait until rising_edge(clk);
check("Testing incorrect unsigned = x'11'", s_u, 16#10#, pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
print("<Done testing check() unsigned against integer>");
print(lf & "<Testing check() signed>");
s_s <= x"00";
wait until rising_edge(clk);
check("Testing correct signed = x'00'", s_s, x"00", pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_s <= x"47";
wait until rising_edge(clk);
check("Testing correct signed = x'47'", s_s, x"47", pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_s <= x"11";
wait until rising_edge(clk);
check("Testing incorrect signed = x'11'", s_s, x"10", pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_s <= x"FF";
wait until rising_edge(clk);
check("Testing negative signed = x'FF'", s_s, x"FF", pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
print("<Done testing check() signed>");
print(lf & "<Testing check() signed against integer>");
s_s <= x"00";
wait until rising_edge(clk);
check("Testing correct signed = x'00'", s_s, 0, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_s <= x"47";
wait until rising_edge(clk);
check("Testing correct signed = x'47'", s_s, 16#47#, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_s <= x"11";
wait until rising_edge(clk);
check("Testing incorrect signed = x'11'", s_s, 16#10#, pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_s <= x"FF";
wait until rising_edge(clk);
print("NOTE: Skipping test with negative signed. There seem to be a bug in ModelSim.");
--print("The following check fails in ModelSim for unknown reason." &
-- " It causes mismatch between expected number of errors" &
-- " and the number presented by endsim()");
--check("Testing negative signed = x'FF'", s_s, -1, pltbv, pltbs);
--check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
print("<Done testing check() signed against integer>");
 
print(lf & "<Testing check() boolean>");
s_b <= false;
wait until rising_edge(clk);
check("Testing correct boolean = false", s_b, false, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_b <= true;
wait until rising_edge(clk);
check("Testing correct boolean = true", s_b, true, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_b <= false;
wait until rising_edge(clk);
check("Testing incorrect boolean = true", s_b, true, pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
print("<Done testing check() boolean>");
print(lf & "<Testing check() boolean against integer>");
s_b <= false;
wait until rising_edge(clk);
check("Testing correct boolean = false", s_b, 0, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_b <= true;
wait until rising_edge(clk);
check("Testing correct boolean = true", s_b, 1, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_b <= false;
wait until rising_edge(clk);
check("Testing incorrect boolean = true", s_b, 1, pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_b <= true;
wait until rising_edge(clk);
check("Testing boolean = true with incorrect expected", s_b, 2, pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
print("<Done testing check() boolean against integer>");
 
print(lf & "<Testing check() time>");
s_time <= 0 sec;
wait until rising_edge(clk);
check("Testing correct time = 0 sec", s_time, 0 sec, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_time <= 47 ns;
wait until rising_edge(clk);
check("Testing correct time = 47 ns", s_time, 47 ns, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_time <= 11 us;
wait until rising_edge(clk);
check("Testing incorrect time = 10 us", s_time, 10 us, pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
print("<Done testing check() time>");
print(lf & "<Testing check() time with tolerance>");
s_time <= 0 sec;
wait until rising_edge(clk);
check("Testing correct unsigned = 0 sec +/- 0 sec", s_time, 0 sec, 0 sec, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_time <= 47 ns - 3 ns;
wait until rising_edge(clk);
check("Testing correct time = 47 ns +/- 5 ns", s_time, 47 ns, 5 ns, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_time <= 10 us + 7 us;
wait until rising_edge(clk);
check("Testing incorrect time = 10 us +/- 5 us", s_time, 10 us, 5 us, pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
print("<Done testing check() time with tolerance>");
 
print(lf & "<Testing check() string>");
s_str_exp <= string'("The quick brown fox jumps over the lazy dog.");
s_str1 <= string'("The quick brown fox jumps over the lazy dog.");
s_str2 <= string'("The quick brown dog jumps over the lazy fox.");
s_str3 <= string'("The quick brown fox jumps over the lazy dog");
s_str4 <= string'("The quick brown fox jumps over the lazy dog..");
wait until rising_edge(clk);
check("Testing correct string", s_str1, s_str_exp, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_s <= x"47";
wait until rising_edge(clk);
check("Testing incorrect string with correct length", s_str2, s_str_exp, pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_s <= x"11";
wait until rising_edge(clk);
check("Testing too short string", s_str3, s_str_exp, pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
wait until rising_edge(clk);
check("Testing too long string", s_str4, s_str_exp, pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
print("<Done testing check() string>");
print(lf & "<Testing check() boolean expression>");
s_i <= 0;
wait until rising_edge(clk);
check("Testing correct boolean expression 0 = 16#00#", s_i = 16#00#, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
s_i <= 47;
wait until rising_edge(clk);
check("Testing incorrect boolean expression 47 < 16#10#", s_i < 16#10#, pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
print("<Done testing check() boolean expresson>");
 
print(lf & "<Test readline() behaviour of the current simulator>");
print("Some simulators seem to handle CR and LF differently from others.");
file_open(f_status, txtfile, G_TEXTTESTFILE_REFERENCE, read_mode);
print("DEBUG: file_open_status: " & file_open_status'image(f_status));
if f_status /= open_ok then
print("Failed to open " & G_TEXTTESTFILE_REFERENCE & " for reading: " & file_open_status'image(f_status));
else
while not endfile(txtfile) loop
readline(txtfile, l);
line_num := line_num + 1;
write(msg, "Line " & str(line_num) & ": " & str(l'length) & " characters: ");
for i in l'range loop
write(msg, character'pos(l(i)));
write(msg, string'(" "));
end loop;
writeline(output, msg);
end loop;
end if;
print("<Done testing readline() behaviour>");
 
print(lf & "<Test reading binary files>");
-- Check if the current simulator running on the current operating system supports
-- reading binary files as file of character.
-- That is a requirement for check_binfile().
file_open(f_status, binfile, G_BINTESTFILE_REFERENCE, read_mode);
print("DEBUG: file_open_status: " & file_open_status'image(f_status));
--check("Status of opening binary file", f_status = open_ok, file_open_status'image(f_status), "open_ok", pltbv, pltbs);
--check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
if f_status = open_ok then
i := 0;
v_errcnt := 0;
while not endfile(binfile) loop
read(binfile, c);
v_actual_data := character'pos(c);
if i < G_BINTESTFILE_HEADER'length then
v_expected_data := character'pos(G_BINTESTFILE_HEADER(i+1));
else
v_expected_data := (i - G_BINTESTFILE_HEADER'length) mod 256;
end if;
if v_actual_data /= v_expected_data then
v_errcnt := v_errcnt + 1;
print("Error at offset " & str(i) & ": actual " & str(v_actual_data) & " expected " & str(v_expected_data));
end if;
i := i + 1;
end loop;
file_close(binfile);
check("Number of errors while reading binary file", v_errcnt, 0, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
check("Number of bytes read from binary file", i, G_BINTESTFILE_LEN, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
end if;
print("<Done testing reading binary files>");
 
print(lf & "<Testing check_binfile()");
check_binfile("Testing correct binary file", G_BINTESTFILE_CORRECT, G_BINTESTFILE_REFERENCE, G_CHECKFILE_VERBOSITY, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
check_binfile("Testing binary file with error", G_BINTESTFILE_ERROR, G_BINTESTFILE_REFERENCE, G_CHECKFILE_VERBOSITY, pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
check_binfile("Testing shorter binary file", G_BINTESTFILE_SHORTER, G_BINTESTFILE_REFERENCE, G_CHECKFILE_VERBOSITY, pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
check_binfile("Testing longer binary file", G_BINTESTFILE_LONGER, G_BINTESTFILE_REFERENCE, G_CHECKFILE_VERBOSITY, pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
print("<Done testing check_binfile()");
 
print(lf & "<Testing check_txtfile()");
check_txtfile("Testing correct text file", G_TEXTTESTFILE_CORRECT, G_TEXTTESTFILE_REFERENCE, G_CHECKFILE_VERBOSITY, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
check_txtfile("Testing text file with error", G_TEXTTESTFILE_ERROR, G_TEXTTESTFILE_REFERENCE, G_CHECKFILE_VERBOSITY, pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
check_txtfile("Testing shorter text file", G_TEXTTESTFILE_SHORTER, G_TEXTTESTFILE_REFERENCE, G_CHECKFILE_VERBOSITY, pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
check_txtfile("Testing longer text file", G_TEXTTESTFILE_LONGER, G_TEXTTESTFILE_REFERENCE, G_CHECKFILE_VERBOSITY, pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
print("<Done testing check_txtfile()");
 
print(lf & "<Testing check_datfile()");
check_datfile("Testing correct data file", G_DATTESTFILE_CORRECT, G_DATTESTFILE_REFERENCE, G_CHECKFILE_VERBOSITY, pltbv, pltbs);
check_cnt(C_EXPECTED_SUCCESS, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
check_datfile("Testing data file with error", G_DATTESTFILE_ERROR, G_DATTESTFILE_REFERENCE, G_CHECKFILE_VERBOSITY, pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
check_datfile("Testing shorter data file", G_DATTESTFILE_SHORTER, G_DATTESTFILE_REFERENCE, G_CHECKFILE_VERBOSITY, pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
check_datfile("Testing longer data file", G_DATTESTFILE_LONGER, G_DATTESTFILE_REFERENCE, G_CHECKFILE_VERBOSITY, pltbv, pltbs);
check_cnt(C_EXPECTED_FAIL, v_expected_checks_cnt, v_expected_errors_cnt, expected_checks_cnt, expected_errors_cnt);
print("<Done testing check_datfile()");
 
print(lf & "<Testing endtest()>");
endtest(pltbv, pltbs);
print("<Done testing endtest()>");
wait until rising_edge(clk);
print(lf & "<Testing endsim()>");
print("");
print("Expected number of tests: " & str(v_expected_tests_cnt));
print("Expected number of skipped tests: " & str(v_expected_skiptests_cnt));
print("Expected number of checks: " & str(v_expected_checks_cnt));
print("Expected number of errors: " & str(v_expected_errors_cnt));
if v_expected_errors_cnt = 0 then
print("Expected result: SUCCESS");
else
print("Expected result: FAIL");
end if;
wait until rising_edge(clk);
endsim(pltbv, pltbs, true);
wait until rising_edge(clk);
print("<Done testing endsim()>");
 
wait;
end process p_tc1;
end architecture bhv;
/pltbutils/tags/v1.3/bench/vhdl/tb_files.lst
0,0 → 1,646
tb_pltbutils.vhd
/pltbutils/tags/v1.3/bench/testfiles/bintestfile_correct.bin Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/pltbutils/tags/v1.3/bench/testfiles/bintestfile_correct.bin
pltbutils/tags/v1.3/bench/testfiles/bintestfile_correct.bin Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: pltbutils/tags/v1.3/bench/testfiles/bintestfile_error.bin =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: pltbutils/tags/v1.3/bench/testfiles/bintestfile_error.bin =================================================================== --- pltbutils/tags/v1.3/bench/testfiles/bintestfile_error.bin (nonexistent) +++ pltbutils/tags/v1.3/bench/testfiles/bintestfile_error.bin (revision 110)
pltbutils/tags/v1.3/bench/testfiles/bintestfile_error.bin Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: pltbutils/tags/v1.3/bench/testfiles/bintestfile_longer.bin =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: pltbutils/tags/v1.3/bench/testfiles/bintestfile_longer.bin =================================================================== --- pltbutils/tags/v1.3/bench/testfiles/bintestfile_longer.bin (nonexistent) +++ pltbutils/tags/v1.3/bench/testfiles/bintestfile_longer.bin (revision 110)
pltbutils/tags/v1.3/bench/testfiles/bintestfile_longer.bin Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: pltbutils/tags/v1.3/bench/testfiles/bintestfile_reference.bin =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: pltbutils/tags/v1.3/bench/testfiles/bintestfile_reference.bin =================================================================== --- pltbutils/tags/v1.3/bench/testfiles/bintestfile_reference.bin (nonexistent) +++ pltbutils/tags/v1.3/bench/testfiles/bintestfile_reference.bin (revision 110)
pltbutils/tags/v1.3/bench/testfiles/bintestfile_reference.bin Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: pltbutils/tags/v1.3/bench/testfiles/bintestfile_shorter.bin =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: pltbutils/tags/v1.3/bench/testfiles/bintestfile_shorter.bin =================================================================== --- pltbutils/tags/v1.3/bench/testfiles/bintestfile_shorter.bin (nonexistent) +++ pltbutils/tags/v1.3/bench/testfiles/bintestfile_shorter.bin (revision 110)
pltbutils/tags/v1.3/bench/testfiles/bintestfile_shorter.bin Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: pltbutils/tags/v1.3/bench/testfiles/dattestfile_correct.dat =================================================================== --- pltbutils/tags/v1.3/bench/testfiles/dattestfile_correct.dat (nonexistent) +++ pltbutils/tags/v1.3/bench/testfiles/dattestfile_correct.dat (revision 110) @@ -0,0 +1,10 @@ +# Dattestfile (modified comments and whitespaces, but it shouldn't matter) +1 2 +3 +4 5 6 +7 8 9 + ABC DEF +GHI + JKL MNO PQR +# Modified Comment +STUVW XYZ Index: pltbutils/tags/v1.3/bench/testfiles/dattestfile_error.dat =================================================================== --- pltbutils/tags/v1.3/bench/testfiles/dattestfile_error.dat (nonexistent) +++ pltbutils/tags/v1.3/bench/testfiles/dattestfile_error.dat (revision 110) @@ -0,0 +1,9 @@ +# Dattestfile Error +1 +2 +7 +4 5 6 +7 8 9 + ABC DEF GHI + JqL MNO PQR # Comment2 +STUVW XYZ Index: pltbutils/tags/v1.3/bench/testfiles/dattestfile_longer.dat =================================================================== --- pltbutils/tags/v1.3/bench/testfiles/dattestfile_longer.dat (nonexistent) +++ pltbutils/tags/v1.3/bench/testfiles/dattestfile_longer.dat (revision 110) @@ -0,0 +1,9 @@ +# Dattestfile +1 +2 +3 +4 5 6 +7 8 9 + ABC DEF GHI + JKL MNO PQR # Comment +STUVW XYZ WOW Index: pltbutils/tags/v1.3/bench/testfiles/dattestfile_reference.dat =================================================================== --- pltbutils/tags/v1.3/bench/testfiles/dattestfile_reference.dat (nonexistent) +++ pltbutils/tags/v1.3/bench/testfiles/dattestfile_reference.dat (revision 110) @@ -0,0 +1,9 @@ +# Dattestfile +1 +2 +3 +4 5 6 +7 8 9 + ABC DEF GHI + JKL MNO PQR # Comment +STUVW XYZ Index: pltbutils/tags/v1.3/bench/testfiles/dattestfile_shorter.dat =================================================================== --- pltbutils/tags/v1.3/bench/testfiles/dattestfile_shorter.dat (nonexistent) +++ pltbutils/tags/v1.3/bench/testfiles/dattestfile_shorter.dat (revision 110) @@ -0,0 +1,9 @@ +# Dattestfile +1 +2 +3 +4 5 6 +7 8 9 + ABC DEF GHI + JKL MNO PQR # Comment +STUVW Index: pltbutils/tags/v1.3/bench/testfiles/texttestfile_correct.txt =================================================================== --- pltbutils/tags/v1.3/bench/testfiles/texttestfile_correct.txt (nonexistent) +++ pltbutils/tags/v1.3/bench/testfiles/texttestfile_correct.txt (revision 110) @@ -0,0 +1,3 @@ +Texttestfile line 1 +line 2 +line 3 Index: pltbutils/tags/v1.3/bench/testfiles/texttestfile_error.txt =================================================================== --- pltbutils/tags/v1.3/bench/testfiles/texttestfile_error.txt (nonexistent) +++ pltbutils/tags/v1.3/bench/testfiles/texttestfile_error.txt (revision 110) @@ -0,0 +1,3 @@ +Texttestfile lone 1 +line 2 +line 3 Index: pltbutils/tags/v1.3/bench/testfiles/texttestfile_longer.txt =================================================================== --- pltbutils/tags/v1.3/bench/testfiles/texttestfile_longer.txt (nonexistent) +++ pltbutils/tags/v1.3/bench/testfiles/texttestfile_longer.txt (revision 110) @@ -0,0 +1,4 @@ +Texttestfile line 1 +line 2 +line 3 +l \ No newline at end of file Index: pltbutils/tags/v1.3/bench/testfiles/texttestfile_reference.txt =================================================================== --- pltbutils/tags/v1.3/bench/testfiles/texttestfile_reference.txt (nonexistent) +++ pltbutils/tags/v1.3/bench/testfiles/texttestfile_reference.txt (revision 110) @@ -0,0 +1,3 @@ +Texttestfile line 1 +line 2 +line 3 Index: pltbutils/tags/v1.3/bench/testfiles/texttestfile_shorter.txt =================================================================== --- pltbutils/tags/v1.3/bench/testfiles/texttestfile_shorter.txt (nonexistent) +++ pltbutils/tags/v1.3/bench/testfiles/texttestfile_shorter.txt (revision 110) @@ -0,0 +1,3 @@ +Texttestfile line 1 +line 2 +line \ No newline at end of file Index: pltbutils/tags/v1.3/doc/release_note.txt =================================================================== --- pltbutils/tags/v1.3/doc/release_note.txt (nonexistent) +++ pltbutils/tags/v1.3/doc/release_note.txt (revision 110) @@ -0,0 +1,133 @@ +pltbutils release_note.txt + +v1.3 May 12, 2020 +1. Updated private procedure get_file_item() for correct functionality with + XSim. +2. Added simulation directory xsim_pltbutils. + +v1.2 March 11, 2020 +1. Added waitsig() for unclocked std_logic in pltbutils_func_pkg.vhd . +2. Added check_binfile(), check_txtfile(), check_datfile() in + pltbutils_func_pkg.vhd . +3. Added str() for converting integer to string with fixed field width + in pltbutils_func_pkg.vhd . +4. Added str_equal() for comparing strings in pltbutils_func_pkg.vhd . +5. Improved handling of internal (private) procedures + in pltbutils_func_pkg.vhd . +6. Added components pltbutils_time_measure and pltbutils_diff_check + in pltbutils_comp.vhd / pltbutils_comp_pkg.vhd +7. Minor updates to scripts. +8. Updated specification_pltbutils.docx / .pdf + +v1.1 August 14, 2018 +1. Corrected handling of skipped tests. + Thanks to Kent Damberg for finding the bug. + +v1.0 January 26, 2016 +1. Updated specification_pltbutils.docx / .pdf + +beta004 January 3, 2016 +1. Added skiptest argument to startsim(). +2. Added function is_test_active(). +3. Updated examples, testbenches and templates. +4. Updated specification_pltbutils.docx / .pdf + +beta0003 November 23, 2015 +1. Added check() for boolean. +2. Added check() for boolean against integer. +3. Added check() for time. +4. Added check() for time with tolerance. Suggested by Stefan Eriksson. +5. Updated tb_pltbutils.vhd with tests for the new check() procedures. +6. Updated specification_pltbutils.docx / .pdf + +Thanks to Stefan Eriksson for suggesting features and providing feedback +on documentation. + +beta0002 February 2, 2015 +1. endsim(): renamed argument from force to force_stop for clarity. +2. print2(string, string): corrected call, from print() to print2(). +3. print2(pltbv_t, pltbs_t, string): corrected call, from print() to print2(). +4. pltbutils_func_pkg.vhd: more comments. +5. waitsig(): added overloaded unclocked variant. +6. hxstr(): no longer wrapper for hstr, improved with unlimited length of + argument s. +7. Updated author's email address in all files where applicable. +8: Updated specification_pltbutils.docx/.pdf. + +beta0001 April 9, 2014 +1. Added check() for string. + +alpha0007 January 13, 2014 +1. Renamed example/vhdl/*.* to examples/vhdl/examples2/*.* + This is example code where the testcase process(es) are located + in a testcase component, enabling multiple testcase architectures. + Renamed sim/example_sim/ to sim/modelsim_tb_example2/ +2. Created examples/vhdl/examples1/ + This is example code where the testcase process is located in the + testbench top. + Created sim/modelsim_tb_example1/ +3. Renamed sim/bench_sim/ to sim/modelsim_tb_pltbutils/ +4. Renamed template/vhdl/*.* to templates/vhdl/template2/*.* +5. Created templates/vhdl/template1/ +6. Updated specification_pltbutils.docx/pdf to rev 0.5 + +alpha0006 January 09, 2014 +1. Replaced shared variables with a normal variable, and global signals with + a normal signal. + VHDL-2000 and later requires that shared variables use protected types, + but protected types weren't available in earlier VHDL versions. + As a consequence, some simulators in VHDL-200x mode require protected + types. But some simulators still don't support protected types at all. + To make pltbutils work in all (or at least in most) VHDL simulators, + shared variables have now been removed. + In previous versions of pltbutils, protected types were used by default. + There were comments in the pltbutils code as an aid to modify the code + for simulators that don't support protected types, but it was too much + work to do the modifications. One possible solution could have been to + make separate variants of pltbutils; one with, and one without protected + types. But that solution was not tempting. +2. Removed src/vhdl/pltbutils_type_pkg.vhd . +3. Added doc/required_updates.txt . + +alpha0005 January 05, 2014 +1. In pltbutils_func_pkg.vhd, added starttest() and endtest(). +2. testname() is now depricated, and will be removed. Use starttest() instead. +3. Added pltbutils_user_cfg_pkg.vhd and modified pltbutils_func_pkg.vhd to + support user configurable report messages, to support continous + integration environments, e.g. TeamCity. +4. Updated specification. + +alpha0004 December 3, 2013 +1. Corrected returned ranges from to_ascending() and to_descending() + in pltbutils_func_pkg.vhd, to make them work with vectors where the lowest + bit does not have number 0. + +alpha0003 December 2, 2013 +1. Added a line feed before printing the test name for clarity, + in procedure testname() in pltbutils.vhd . +2. Added functions to_ascending(), to_descending() and hxstr() + in pltbutils.vhd (not yet included in the specification). +3. check() in pltbutils.vhd now outputs hexadecimal values instead of + binary values for std_logic_vector, unsigned and signed. +4. Updated tb_example.vhd, tc_example.vhd and tc1.vhd to feed + the generic G_DISABLE_BUGS to tc1. + The message "Bug here somewhere" is now only output when + G_DISABLE_BUGS=0. + +alpha0002 November 10, 2013 +1. Added doc/release_note.txt +2. Removed file paths from pltbutils_files.lst +3. Added overloaded print procedures with boolean argument called active, + which is useful for debug switches, etc. +4. Added inverted clock output and a generic for setting initial value to + pltbutils_clkgen in pltbutils_comp.vhd and pltbutils_comp_pkg.vhd . + The inverted clock output can be used when a differential + clock is needed. +5. Added overloaded procedures waitsig(). +6. Updated specification. + +alpha0001 September 2, 2013 +1. First commit + +April 14, 2013 +1. PlTbUtils project registered on OpenCores. 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+<<0E54F56F2B02DA449FEECAEC1414288A>] >> +startxref +553552 +%%EOF +xref +0 0 +trailer +<<0E54F56F2B02DA449FEECAEC1414288A>] /Prev 553552/XRefStm 549901>> +startxref +585795 +%%EOF \ No newline at end of file Index: pltbutils/tags/v1.3/doc/src/specification_pltbutils.docx =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: pltbutils/tags/v1.3/doc/src/specification_pltbutils.docx =================================================================== --- pltbutils/tags/v1.3/doc/src/specification_pltbutils.docx (nonexistent) +++ pltbutils/tags/v1.3/doc/src/specification_pltbutils.docx (revision 110)
pltbutils/tags/v1.3/doc/src/specification_pltbutils.docx Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: pltbutils/tags/v1.3/doc/src/example_wave.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: pltbutils/tags/v1.3/doc/src/example_wave.png =================================================================== --- pltbutils/tags/v1.3/doc/src/example_wave.png (nonexistent) +++ pltbutils/tags/v1.3/doc/src/example_wave.png (revision 110)
pltbutils/tags/v1.3/doc/src/example_wave.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: pltbutils/tags/v1.3/doc/src/example_transcript_bugfixed.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: pltbutils/tags/v1.3/doc/src/example_transcript_bugfixed.png =================================================================== --- pltbutils/tags/v1.3/doc/src/example_transcript_bugfixed.png (nonexistent) +++ pltbutils/tags/v1.3/doc/src/example_transcript_bugfixed.png (revision 110)
pltbutils/tags/v1.3/doc/src/example_transcript_bugfixed.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: pltbutils/tags/v1.3/doc/src/example_transcript.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: pltbutils/tags/v1.3/doc/src/example_transcript.png =================================================================== --- pltbutils/tags/v1.3/doc/src/example_transcript.png (nonexistent) +++ pltbutils/tags/v1.3/doc/src/example_transcript.png (revision 110)
pltbutils/tags/v1.3/doc/src/example_transcript.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: pltbutils/tags/v1.3/doc/src/example_wave_bugfixed.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: pltbutils/tags/v1.3/doc/src/example_wave_bugfixed.png =================================================================== --- pltbutils/tags/v1.3/doc/src/example_wave_bugfixed.png (nonexistent) +++ pltbutils/tags/v1.3/doc/src/example_wave_bugfixed.png (revision 110)
pltbutils/tags/v1.3/doc/src/example_wave_bugfixed.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: pltbutils/tags/v1.3/doc/required_updates.txt =================================================================== --- pltbutils/tags/v1.3/doc/required_updates.txt (nonexistent) +++ pltbutils/tags/v1.3/doc/required_updates.txt (revision 110) @@ -0,0 +1,98 @@ +pltbutils required_updates.txt + +While pltbutils is still in alpha- and beta state, backwards compatibility in +new versions of pltbutils is not prioritized, because the code is still under +development. +If you have made testbenches which use pltbutils, you may need to make +modifications if you update to a newer version of pltbutils. +This document lists required modifications to your testbenches. + +beta0003 -> beta0004 and later +1. In your testbench, replace + startsim("ExampleName", pltbv, pltbs); + with + startsim("ExampleName", "", pltbv, pltbs); + The new argument 2 is a std_logic_vector for skipping tests. + Read more in the specification. +2. If you have created your own procedure custom_endsim_msg(), + it must now have a new argument: + procedure custom_endsim_msg( + constant testcase_name : in string; + constant timestamp : in time; + constant num_tests : in integer; + constant num_skip_tests : in integer; -- New argument + constant num_checks : in integer; + constant num_errors : in integer; + constant show_success_fail : in boolean + ) +3. If you have created your own procedure custom_endtest_msg(), + it must now have a new argument: + procedure custom_endtest_msg( + constant test_num : in integer; + constant test_name : in string; + constant timestamp : in time; + constant test_active : in boolean; -- New argument + constant num_checks_in_test : in integer; + constant num_errors_in_test : in integer + ) + +alpha0006 -> alpha0007 and later +Nothing. + +alpha0005 -> alpha0006 +For more information and examples, see specification_pltbutils.pdf . +1. One less file to be compiled: + src/vhdl/pltbutils_type_pkg.vhd has been removed. +2. testname() has been removed. Call starttest() and endtest() instead. +3. In the testbech top, replace + -- Simulation status- and control signals + signal test_num : integer; + -- VHDL-1993: + --signal test_name : string(pltbutils_test_name'range); + --signal info : string(pltbutils_info'range); + -- VHDL-2002: + signal test_name : string(pltbutils_sc.test_name'range); + signal info : string(pltbutils_sc.info'range); + + signal checks : integer; + signal errors : integer; + signal stop_sim : std_logic; + with + -- Simulation status- and control signals + -- for accessing .stop_sim and for viewing in waveform window + signal pltbs : pltbs_t := C_PLTBS_INIT; + +4. In the testbench top, under begin, remove + -- Simulation status and control for viewing in waveform window + -- VHDL-1993: + --test_num <= pltbutils_test_num; + --test_name <= pltbutils_test_name; + --checks <= pltbutils_chk_cnt; + --errors <= pltbutils_err_cnt; + -- VHDL-2002: + test_num <= pltbutils_sc.test_num; + test_name <= pltbutils_sc.test_name; + info <= pltbutils_sc.info; + checks <= pltbutils_sc.chk_cnt; + errors <= pltbutils_sc.err_cnt; + stop_sim <= pltbutils_sc.stop_sim; + +5. Feed stop_sim input of testbench component with pltbs.stop_sim instead + of just stop_sim. +6. If the testcase procudure resides in a separate VHDL component, + that component should output pltbs of type pltbs_t. +7. The testcase process should instansiate the following variable: + variable pltbv : pltbv_t := C_PLTBV_INIT; +8. In calls to pltbutils procedures, replace the argument + pltbutils_sc + with + pltbv, pltbs +9. In the waveform window, replace the old simulation status signals + with pltbs, and expand it to view the member elements. + +alpha0004 -> alpha0005 +1. One more file needs to be compiled: src/vhdl/pltbutils_user_cfg_pkg.vhd . +2. Call starttest() before a test, and endtest() after. + Previously, testname() should be called before a test, but testname() is + now depricated and will be removed in a later version. + \ No newline at end of file Index: pltbutils/tags/v1.3/sim/xsim_tb_pltbutils/bin/tb_pltbutils.prj =================================================================== --- pltbutils/tags/v1.3/sim/xsim_tb_pltbutils/bin/tb_pltbutils.prj (nonexistent) +++ pltbutils/tags/v1.3/sim/xsim_tb_pltbutils/bin/tb_pltbutils.prj (revision 110) @@ -0,0 +1,7 @@ +vhdl xil_defaultlib ../../../src/vhdl/txt_util.vhd +vhdl xil_defaultlib ../../../src/vhdl/pltbutils_user_cfg_pkg.vhd +vhdl xil_defaultlib ../../../src/vhdl/pltbutils_func_pkg.vhd +vhdl xil_defaultlib ../../../src/vhdl/pltbutils_comp.vhd +vhdl xil_defaultlib ../../../src/vhdl/pltbutils_comp_pkg.vhd +vhdl xil_defaultlib ../../../bench/vhdl/tb_pltbutils.vhd + Index: pltbutils/tags/v1.3/sim/xsim_tb_pltbutils/bin/tc1.bat =================================================================== --- pltbutils/tags/v1.3/sim/xsim_tb_pltbutils/bin/tc1.bat (nonexistent) +++ pltbutils/tags/v1.3/sim/xsim_tb_pltbutils/bin/tc1.bat (revision 110) @@ -0,0 +1,10 @@ +@echo off +set tb_name=tb_pltbutils +set libname=xil_defaultlib + +call xelab -prj ..\bin\%tb_name%.prj -s %tb_name% %libname%.%tb_name% +::echo xelab error level: %errorlevel% +if %errorlevel% equ 0 ( + call xsim -runall %tb_name% +) +echo Error level (0 is good): %errorlevel% Index: pltbutils/tags/v1.3/sim/xsim_tb_pltbutils/run/run_tc1.bat =================================================================== --- pltbutils/tags/v1.3/sim/xsim_tb_pltbutils/run/run_tc1.bat (nonexistent) +++ pltbutils/tags/v1.3/sim/xsim_tb_pltbutils/run/run_tc1.bat (revision 110) @@ -0,0 +1 @@ +call ..\bin\tc1.bat Index: pltbutils/tags/v1.3/sim/modelsim_tb_example1/bin/comp.do =================================================================== --- pltbutils/tags/v1.3/sim/modelsim_tb_example1/bin/comp.do (nonexistent) +++ pltbutils/tags/v1.3/sim/modelsim_tb_example1/bin/comp.do (revision 110) @@ -0,0 +1,14 @@ +# comp.do +# ModelSim do-script for compiling design and testbench +if {![file exists $libname]} { + vlib $libname +} +vcom -novopt -work $libname \ + ../../../examples/vhdl/rtl_example/dut_example.vhd \ + ../../../src/vhdl/txt_util.vhd \ + ../../../src/vhdl/pltbutils_user_cfg_pkg.vhd \ + ../../../src/vhdl/pltbutils_func_pkg.vhd \ + ../../../src/vhdl/pltbutils_comp.vhd \ + ../../../src/vhdl/pltbutils_comp_pkg.vhd \ + ../../../examples/vhdl/tb_example1/tb_example1.vhd + \ No newline at end of file Index: pltbutils/tags/v1.3/sim/modelsim_tb_example1/bin/tc1.do =================================================================== --- pltbutils/tags/v1.3/sim/modelsim_tb_example1/bin/tc1.do (nonexistent) +++ pltbutils/tags/v1.3/sim/modelsim_tb_example1/bin/tc1.do (revision 110) @@ -0,0 +1,19 @@ +# tc1.do +# ModelSim do script for compiling and running simulation +set libname worklib +set vsim_arg "" +if {$argc >= 1} { + set vsim_arg $1 +} + +do comp.do +vsim -l ../log/tc1.log $vsim_arg $libname.tb_example1 +if [file exists log.do] { + do log.do +} +if [file exists ../bin/wave.do] { + do ../bin/wave.do +} +run 1 ms + + \ No newline at end of file Index: pltbutils/tags/v1.3/sim/modelsim_tb_example1/bin/wave.do =================================================================== --- pltbutils/tags/v1.3/sim/modelsim_tb_example1/bin/wave.do (nonexistent) +++ pltbutils/tags/v1.3/sim/modelsim_tb_example1/bin/wave.do (revision 110) @@ -0,0 +1,55 @@ +onerror {resume} +quietly virtual signal -install /tb_example1 {/tb_example1/pltbs.test_num } Test_number +quietly virtual signal -install /tb_example1 {/tb_example1/pltbs.test_name } Test_name +quietly virtual signal -install /tb_example1 {/tb_example1/pltbs.info } Info +quietly virtual signal -install /tb_example1 {/tb_example1/pltbs.chk_cnt } Checks +quietly virtual signal -install /tb_example1 {/tb_example1/pltbs.err_cnt } Errors +quietly virtual signal -install /tb_example1 {/tb_example1/pltbs.stop_sim } StopSim +quietly virtual signal -install /tb_example1 {/tb_example1/pltbs.test_num } TestNumber +quietly virtual signal -install /tb_example1 {/tb_example1/pltbs.test_name } TestName +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider {Simulation info} +add wave -noupdate /tb_example1/TestNumber +add wave -noupdate /tb_example1/TestName +add wave -noupdate /tb_example1/Info +add wave -noupdate /tb_example1/Checks +add wave -noupdate /tb_example1/Errors +add wave -noupdate /tb_example1/StopSim +add wave -noupdate -divider Tb +add wave -noupdate /tb_example1/clk +add wave -noupdate /tb_example1/rst +add wave -noupdate /tb_example1/carry_in +add wave -noupdate /tb_example1/x +add wave -noupdate /tb_example1/y +add wave -noupdate /tb_example1/sum +add wave -noupdate /tb_example1/carry_out +add wave -noupdate -divider DUT +add wave -noupdate /tb_example1/dut0/clk_i +add wave -noupdate /tb_example1/dut0/rst_i +add wave -noupdate /tb_example1/dut0/carry_i +add wave -noupdate /tb_example1/dut0/x_i +add wave -noupdate /tb_example1/dut0/y_i +add wave -noupdate /tb_example1/dut0/sum_o +add wave -noupdate /tb_example1/dut0/carry_o +add wave -noupdate /tb_example1/dut0/x +add wave -noupdate /tb_example1/dut0/y +add wave -noupdate /tb_example1/dut0/c +add wave -noupdate /tb_example1/dut0/sum +add wave -noupdate -divider End +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +configure wave -namecolwidth 133 +configure wave -valuecolwidth 40 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {131072 ps} Index: pltbutils/tags/v1.3/sim/modelsim_tb_example1/run/run_bugfixed.do =================================================================== --- pltbutils/tags/v1.3/sim/modelsim_tb_example1/run/run_bugfixed.do (nonexistent) +++ pltbutils/tags/v1.3/sim/modelsim_tb_example1/run/run_bugfixed.do (revision 110) @@ -0,0 +1 @@ +do ../bin/tc1.do -GG_DISABLE_BUGS=1 Index: pltbutils/tags/v1.3/sim/modelsim_tb_example1/run/run.do =================================================================== --- pltbutils/tags/v1.3/sim/modelsim_tb_example1/run/run.do (nonexistent) +++ pltbutils/tags/v1.3/sim/modelsim_tb_example1/run/run.do (revision 110) @@ -0,0 +1 @@ +do ../bin/tc1.do Index: pltbutils/tags/v1.3/sim/modelsim_tb_example2/bin/comp.do =================================================================== --- pltbutils/tags/v1.3/sim/modelsim_tb_example2/bin/comp.do (nonexistent) +++ pltbutils/tags/v1.3/sim/modelsim_tb_example2/bin/comp.do (revision 110) @@ -0,0 +1,16 @@ +# comp.do +# ModelSim do-script for compiling design and testbench +if {![file exists $libname]} { + vlib $libname +} +vcom -novopt -work $libname \ + ../../../examples/vhdl/rtl_example/dut_example.vhd \ + ../../../src/vhdl/txt_util.vhd \ + ../../../src/vhdl/pltbutils_user_cfg_pkg.vhd \ + ../../../src/vhdl/pltbutils_func_pkg.vhd \ + ../../../src/vhdl/pltbutils_comp.vhd \ + ../../../src/vhdl/pltbutils_comp_pkg.vhd \ + ../../../examples/vhdl/tb_example2/tc_example2.vhd \ + $1 \ + ../../../examples/vhdl/tb_example2/tb_example2.vhd + \ No newline at end of file Index: pltbutils/tags/v1.3/sim/modelsim_tb_example2/bin/tc1.do =================================================================== --- pltbutils/tags/v1.3/sim/modelsim_tb_example2/bin/tc1.do (nonexistent) +++ pltbutils/tags/v1.3/sim/modelsim_tb_example2/bin/tc1.do (revision 110) @@ -0,0 +1,20 @@ +# tc1.do +# ModelSim do script for compiling and running simulation +set tc ../../../examples/vhdl/tb_example2/tc1.vhd +set libname worklib +set vsim_arg "" +if {$argc >= 1} { + set vsim_arg $1 +} + +do comp.do $tc +vsim -l ../log/$tc.log $vsim_arg $libname.tb_example2 +if [file exists log.do] { + do log.do +} +if [file exists ../bin/wave.do] { + do ../bin/wave.do +} +run 1 ms + + \ No newline at end of file Index: pltbutils/tags/v1.3/sim/modelsim_tb_example2/bin/wave.do =================================================================== --- pltbutils/tags/v1.3/sim/modelsim_tb_example2/bin/wave.do (nonexistent) +++ pltbutils/tags/v1.3/sim/modelsim_tb_example2/bin/wave.do (revision 110) @@ -0,0 +1,55 @@ +onerror {resume} +quietly virtual signal -install /tb_example2 {/tb_example2/pltbs.test_num } Test_number +quietly virtual signal -install /tb_example2 {/tb_example2/pltbs.test_name } Test_name +quietly virtual signal -install /tb_example2 {/tb_example2/pltbs.info } Info +quietly virtual signal -install /tb_example2 {/tb_example2/pltbs.chk_cnt } Checks +quietly virtual signal -install /tb_example2 {/tb_example2/pltbs.err_cnt } Errors +quietly virtual signal -install /tb_example2 {/tb_example2/pltbs.stop_sim } StopSim +quietly virtual signal -install /tb_example2 {/tb_example2/pltbs.test_num } TestNumber +quietly virtual signal -install /tb_example2 {/tb_example2/pltbs.test_name } TestName +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider {Simulation info} +add wave -noupdate /tb_example2/TestNumber +add wave -noupdate /tb_example2/TestName +add wave -noupdate /tb_example2/Info +add wave -noupdate /tb_example2/Checks +add wave -noupdate /tb_example2/Errors +add wave -noupdate /tb_example2/StopSim +add wave -noupdate -divider Tb +add wave -noupdate /tb_example2/clk +add wave -noupdate /tb_example2/rst +add wave -noupdate /tb_example2/carry_in +add wave -noupdate /tb_example2/x +add wave -noupdate /tb_example2/y +add wave -noupdate /tb_example2/sum +add wave -noupdate /tb_example2/carry_out +add wave -noupdate -divider DUT +add wave -noupdate /tb_example2/dut0/clk_i +add wave -noupdate /tb_example2/dut0/rst_i +add wave -noupdate /tb_example2/dut0/carry_i +add wave -noupdate /tb_example2/dut0/x_i +add wave -noupdate /tb_example2/dut0/y_i +add wave -noupdate /tb_example2/dut0/sum_o +add wave -noupdate /tb_example2/dut0/carry_o +add wave -noupdate /tb_example2/dut0/x +add wave -noupdate /tb_example2/dut0/y +add wave -noupdate /tb_example2/dut0/c +add wave -noupdate /tb_example2/dut0/sum +add wave -noupdate -divider End +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +configure wave -namecolwidth 133 +configure wave -valuecolwidth 40 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {131072 ps} Index: pltbutils/tags/v1.3/sim/modelsim_tb_example2/run/run_tc1.bat =================================================================== --- pltbutils/tags/v1.3/sim/modelsim_tb_example2/run/run_tc1.bat (nonexistent) +++ pltbutils/tags/v1.3/sim/modelsim_tb_example2/run/run_tc1.bat (revision 110) @@ -0,0 +1 @@ +vsim -do ../bin_modelsim/tc1.do Index: pltbutils/tags/v1.3/sim/modelsim_tb_example2/run/run_tc1_bugfixed.do =================================================================== --- pltbutils/tags/v1.3/sim/modelsim_tb_example2/run/run_tc1_bugfixed.do (nonexistent) +++ pltbutils/tags/v1.3/sim/modelsim_tb_example2/run/run_tc1_bugfixed.do (revision 110) @@ -0,0 +1 @@ +do ../bin/tc1.do -GG_DISABLE_BUGS=1 Index: pltbutils/tags/v1.3/sim/modelsim_tb_example2/run/run_tc1.do =================================================================== --- pltbutils/tags/v1.3/sim/modelsim_tb_example2/run/run_tc1.do (nonexistent) +++ pltbutils/tags/v1.3/sim/modelsim_tb_example2/run/run_tc1.do (revision 110) @@ -0,0 +1 @@ +do ../bin/tc1.do Index: pltbutils/tags/v1.3/sim/modelsim_tb_pltbutils/bin/comp.do =================================================================== --- pltbutils/tags/v1.3/sim/modelsim_tb_pltbutils/bin/comp.do (nonexistent) +++ pltbutils/tags/v1.3/sim/modelsim_tb_pltbutils/bin/comp.do (revision 110) @@ -0,0 +1,13 @@ +# comp.do +# ModelSim do-script for compiling design and testbench +if {![file exists $libname]} { + vlib $libname +} +vcom -novopt -work $libname \ + ../../../src/vhdl/txt_util.vhd \ + ../../../src/vhdl/pltbutils_user_cfg_pkg.vhd \ + ../../../src/vhdl/pltbutils_func_pkg.vhd \ + ../../../src/vhdl/pltbutils_comp.vhd \ + ../../../src/vhdl/pltbutils_comp_pkg.vhd \ + ../../../bench/vhdl/tb_pltbutils.vhd + Index: pltbutils/tags/v1.3/sim/modelsim_tb_pltbutils/bin/tc1.do =================================================================== --- pltbutils/tags/v1.3/sim/modelsim_tb_pltbutils/bin/tc1.do (nonexistent) +++ pltbutils/tags/v1.3/sim/modelsim_tb_pltbutils/bin/tc1.do (revision 110) @@ -0,0 +1,19 @@ +# tc1.do +# ModelSim do script for compiling and running simulation +set libname worklib +set vsim_arg "" +if {$argc >= 1} { + set vsim_arg $1 +} + +do comp.do +vsim -l ../log/tc1.log $vsim_arg $libname.tb_pltbutils +if [file exists log.do] { + do log.do +} +if [file exists ../bin/wave.do] { + do ../bin/wave.do +} +run 1 ms + + Index: pltbutils/tags/v1.3/sim/modelsim_tb_pltbutils/bin/wave.do =================================================================== --- pltbutils/tags/v1.3/sim/modelsim_tb_pltbutils/bin/wave.do (nonexistent) +++ pltbutils/tags/v1.3/sim/modelsim_tb_pltbutils/bin/wave.do (revision 110) @@ -0,0 +1,34 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider {Simulation info} +add wave -noupdate -expand /tb_pltbutils/pltbs +add wave -noupdate -divider {Expected counters} +add wave -noupdate /tb_pltbutils/expected_checks_cnt +add wave -noupdate /tb_pltbutils/expected_errors_cnt +add wave -noupdate -divider Tb +add wave -noupdate /tb_pltbutils/clk +add wave -noupdate /tb_pltbutils/clk_cnt +add wave -noupdate /tb_pltbutils/clk_cnt_clr +add wave -noupdate /tb_pltbutils/s_i +add wave -noupdate /tb_pltbutils/s_sl +add wave -noupdate /tb_pltbutils/s_slv +add wave -noupdate /tb_pltbutils/s_u +add wave -noupdate /tb_pltbutils/s_s +add wave -noupdate -divider End +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +configure wave -namecolwidth 133 +configure wave -valuecolwidth 40 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {998488788 ps} {999322038 ps} Index: pltbutils/tags/v1.3/sim/modelsim_tb_pltbutils/run/run_tc1.bat =================================================================== --- pltbutils/tags/v1.3/sim/modelsim_tb_pltbutils/run/run_tc1.bat (nonexistent) +++ pltbutils/tags/v1.3/sim/modelsim_tb_pltbutils/run/run_tc1.bat (revision 110) @@ -0,0 +1,3 @@ +:: run_tc1.bat +:: Windows batch file for compiling and running simulation +vsim -do run_tc1.do Index: pltbutils/tags/v1.3/sim/modelsim_tb_pltbutils/run/run_tc1.do =================================================================== --- pltbutils/tags/v1.3/sim/modelsim_tb_pltbutils/run/run_tc1.do (nonexistent) +++ pltbutils/tags/v1.3/sim/modelsim_tb_pltbutils/run/run_tc1.do (revision 110) @@ -0,0 +1,3 @@ +# run_tc1.do +# ModelSim do script for compiling and running simulation +do ../bin/tc1.do Index: pltbutils/tags/v1.3/src/vhdl/pltbutils_func_pkg.vhd =================================================================== --- pltbutils/tags/v1.3/src/vhdl/pltbutils_func_pkg.vhd (nonexistent) +++ pltbutils/tags/v1.3/src/vhdl/pltbutils_func_pkg.vhd (revision 110) @@ -0,0 +1,2626 @@ +---------------------------------------------------------------------- +---- ---- +---- PlTbUtils Fuctions and Procedures Package ---- +---- ---- +---- This file is part of the PlTbUtils project ---- +---- http://opencores.org/project,pltbutils ---- +---- ---- +---- Description: ---- +---- PlTbUtils is a collection of functions, procedures and ---- +---- components for easily creating stimuli and checking response ---- +---- in automatic self-checking testbenches. ---- +---- ---- +---- This file defines fuctions and procedures for controlling ---- +---- stimuli to a DUT and checking response. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Per Larsson, pela.opencores@gmail.com ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013-2020 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; +use work.txt_util.all; +use work.pltbutils_user_cfg_pkg.all; + +package pltbutils_func_pkg is + + -- See the package body for a description of the functions and procedures. + constant C_PLTBUTILS_STRLEN : natural := 80; + constant C_PLTBUTILS_SKIPTESTLEN : natural := 512; + constant C_PLTBUTILS_TIMEOUT : time := 10 sec; + constant C_WAIT_BEFORE_STOP_TIME : time := 1 us; + + -- Type for status- and control variable + type pltbv_t is + record + testcase_name : string(1 to C_PLTBUTILS_STRLEN); + testcase_name_len: integer; + test_num : integer; + test_name : string(1 to C_PLTBUTILS_STRLEN); + test_name_len : integer; + skiptests : std_logic_vector(0 to C_PLTBUTILS_SKIPTESTLEN-1); + test_active : boolean; + info : string(1 to C_PLTBUTILS_STRLEN); + info_len : integer; + test_cnt : integer; + skiptest_cnt : integer; + chk_cnt : integer; + err_cnt : integer; + chk_cnt_in_test : integer; + err_cnt_in_test : integer; + stop_sim : std_logic; + end record; + + constant C_PLTBV_INIT : pltbv_t := ( + (others => ' '), -- testcase_name + 1, -- testcase_name_len + 0, -- test_num + (others => ' '), -- test_name + 1, -- test_name_len + (others => '0'), -- skiptest + true, -- test_active + (others => ' '), -- info + 1, -- info_len + 0, -- test_cnt + 0, -- skiptest_cnt + 0, -- chk_cnt + 0, -- err_cnt + 0, -- chk_cnt_in_test + 0, -- err_cnt_in_test + '0' -- stop_sim + ); + + -- Status- and control signal (subset of pltbv_t) + type pltbs_t is + record + test_num : natural; + test_name : string(1 to C_PLTBUTILS_STRLEN); + info : string(1 to C_PLTBUTILS_STRLEN); + chk_cnt : natural; + err_cnt : natural; + stop_sim : std_logic; + end record; + + constant C_PLTBS_INIT : pltbs_t := ( + 0, -- test_num + (others => ' '), -- test_name + (others => ' '), -- info + 0, -- chk_cnt + 0, -- err_cnt + '0' -- stop_sim + ); + + -- startsim + procedure startsim( + constant testcase_name : in string; + constant skiptests : in std_logic_vector; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ); + + -- endsim + procedure endsim( + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant show_success_fail : in boolean := false; + constant force_stop : in boolean := false + ); + + -- starttest + procedure starttest( + constant num : in integer := -1; + constant name : in string; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ); + procedure starttest( + constant name : in string; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ); + + -- is_test_active + function is_test_active( + constant pltbv : in pltbv_t + ) return boolean; + + -- endtest + procedure endtest( + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ); + + -- print, printv, print2 + procedure print( + constant active : in boolean; + signal s : out string; + constant txt : in string + ); + procedure print( + signal s : out string; + constant txt : in string + ); + procedure printv( + constant active : in boolean; + variable s : out string; + constant txt : in string + ); + procedure printv( + variable s : out string; + constant txt : in string + ); + procedure print( + constant active : in boolean; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant txt : in string + ); + procedure print( + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant txt : in string + ); + procedure print2( + constant active : in boolean; + signal s : out string; + constant txt : in string + ); + procedure print2( + signal s : out string; + constant txt : in string + ); + procedure print2( + constant active : in boolean; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant txt : in string + ); + procedure print2( + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant txt : in string + ); + + -- waitclks + procedure waitclks( + constant N : in natural; + signal clk : in std_logic; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant falling : in boolean := false; + constant timeout : in time := C_PLTBUTILS_TIMEOUT + ); + + -- waitsig + procedure waitsig( + signal s : in integer; + constant value : in integer; + signal clk : in std_logic; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant falling : in boolean := false; + constant timeout : in time := C_PLTBUTILS_TIMEOUT + ); + procedure waitsig( + signal s : in std_logic; + constant value : in std_logic; + signal clk : in std_logic; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant falling : in boolean := false; + constant timeout : in time := C_PLTBUTILS_TIMEOUT + ); + procedure waitsig( + signal s : in std_logic; + constant value : in integer; + signal clk : in std_logic; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant falling : in boolean := false; + constant timeout : in time := C_PLTBUTILS_TIMEOUT + ); + procedure waitsig( + signal s : in std_logic_vector; + constant value : in std_logic_vector; + signal clk : in std_logic; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant falling : in boolean := false; + constant timeout : in time := C_PLTBUTILS_TIMEOUT + ); + procedure waitsig( + signal s : in std_logic_vector; + constant value : in integer; + signal clk : in std_logic; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant falling : in boolean := false; + constant timeout : in time := C_PLTBUTILS_TIMEOUT + ); + procedure waitsig( + signal s : in unsigned; + constant value : in unsigned; + signal clk : in std_logic; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant falling : in boolean := false; + constant timeout : in time := C_PLTBUTILS_TIMEOUT + ); + procedure waitsig( + signal s : in unsigned; + constant value : in integer; + signal clk : in std_logic; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant falling : in boolean := false; + constant timeout : in time := C_PLTBUTILS_TIMEOUT + ); + procedure waitsig( + signal s : in signed; + constant value : in signed; + signal clk : in std_logic; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant falling : in boolean := false; + constant timeout : in time := C_PLTBUTILS_TIMEOUT + ); + procedure waitsig( + signal s : in signed; + constant value : in integer; + signal clk : in std_logic; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant falling : in boolean := false; + constant timeout : in time := C_PLTBUTILS_TIMEOUT + ); + procedure waitsig( + signal s : in std_logic; + constant value : in std_logic; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant timeout : in time := C_PLTBUTILS_TIMEOUT + ); + -- waitsig std_logic edge, unclocked + procedure waitsig( + signal s : in std_logic; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant falling : in boolean := false; + constant timeout : in time := C_PLTBUTILS_TIMEOUT + ); + -- check + procedure check( + constant rpt : in string; + constant actual : in integer; + constant expected : in integer; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ); + procedure check( + constant rpt : in string; + constant actual : in std_logic; + constant expected : in std_logic; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ); + procedure check( + constant rpt : in string; + constant actual : in std_logic; + constant expected : in integer; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ); + procedure check( + constant rpt : in string; + constant actual : in std_logic_vector; + constant expected : in std_logic_vector; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ); + procedure check( + constant rpt : in string; + constant actual : in std_logic_vector; + constant expected : in std_logic_vector; + constant mask : in std_logic_vector; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ); + procedure check( + constant rpt : in string; + constant actual : in std_logic_vector; + constant expected : in integer; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ); + procedure check( + constant rpt : in string; + constant actual : in std_logic_vector; + constant expected : in integer; + constant mask : in std_logic_vector; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ); + procedure check( + constant rpt : in string; + constant actual : in unsigned; + constant expected : in unsigned; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ); + procedure check( + constant rpt : in string; + constant actual : in unsigned; + constant expected : in integer; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ); + procedure check( + constant rpt : in string; + constant actual : in signed; + constant expected : in signed; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ); + procedure check( + constant rpt : in string; + constant actual : in signed; + constant expected : in integer; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ); + procedure check( + constant rpt : in string; + constant actual : in boolean; + constant expected : in boolean; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ); + procedure check( + constant rpt : in string; + constant actual : in boolean; + constant expected : in integer; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ); + procedure check( + constant rpt : in string; + constant actual : in time; + constant expected : in time; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ); + procedure check( + constant rpt : in string; + constant actual : in time; + constant expected : in time; + constant tolerance : in time; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ); + procedure check( + constant rpt : in string; + constant actual : in string; + constant expected : in string; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ); + procedure check( + constant rpt : in string; + constant expr : in boolean; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ); + procedure check_binfile( + constant rpt : in string; + constant filename1 : in string; + constant filename2 : in string; + constant verbosity : in integer; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ); + procedure check_txtfile( + constant rpt : in string; + constant filename1 : in string; + constant filename2 : in string; + constant verbosity : in integer; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ); + procedure check_datfile( + constant rpt : in string; + constant filename1 : in string; + constant filename2 : in string; + constant verbosity : in integer; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant skip_init_items : in integer := 0 + ); + procedure check( + constant rpt : in string; + constant expr : in boolean; + constant actual : in string; + constant expected : in string; + constant mask : in string; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ); + + -- to_ascending + function to_ascending( + constant s : std_logic_vector + ) return std_logic_vector; + function to_ascending( + constant s : unsigned + ) return unsigned; + function to_ascending( + constant s : signed + ) return signed; + + -- to_descending + function to_descending( + constant s : std_logic_vector + ) return std_logic_vector; + function to_descending( + constant s : unsigned + ) return unsigned; + function to_descending( + constant s : signed + ) return signed; + + -- hxstr + function hxstr( + constant s : std_logic_vector; + constant prefix : string := ""; + constant postfix : string := "" + ) return string; + function hxstr( + constant s : unsigned; + constant prefix : string := ""; + constant postfix : string := "" + ) return string; + function hxstr( + constant s : signed; + constant prefix : string := ""; + constant postfix : string := "" + ) return string; + + -- str + function str( + constant n : integer; + constant len : integer; + constant fillchar : character := ' ' + ) return string; + + function str_equal ( + constant s1 : STRING; + constant s2 : STRING + ) return boolean; + +end package pltbutils_func_pkg; + +package body pltbutils_func_pkg is + + --========================================================================== + -- pltbutils internal (private) procedures + -- To be called from other pltbutils procedures. + -- Do not to call these from user's code. + -- These procedures are intentionally undocumented in the specification + -- document. + --========================================================================== + + procedure pltbs_update( + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ) is + begin + pltbs.test_num <= pltbv.test_num; + print(pltbs.test_name, pltbv.test_name); + print(pltbs.info, pltbv.info); + pltbs.chk_cnt <= pltbv.chk_cnt; + pltbs.err_cnt <= pltbv.err_cnt; + pltbs.stop_sim <= pltbv.stop_sim; + end procedure pltbs_update; + + procedure starttest_msg( + constant test_num : in integer; + constant test_name : in string; + constant timestamp : in time + ) is + begin + print(lf & "Test " & str(test_num) & ": " & test_name & " (" & time'image(timestamp) & ")"); + end procedure starttest_msg; + + procedure skiptest_msg( + constant test_num : in integer; + constant test_name : in string; + constant timestamp : in time + ) is + begin + print(lf & "Skipping Test " & str(test_num) & ": " & test_name & " (" & time'image(timestamp) & ")"); + end procedure skiptest_msg; + + procedure endtest_msg( + constant test_num : in integer; + constant test_name : in string; + constant timestamp : in time; + constant test_active : in boolean; + constant num_checks_in_test : in integer; + constant num_errors_in_test : in integer + ) is + begin + if test_active then + print("Done with test " & str(test_num) & ": " & test_name & " (" & time'image(timestamp) & ")"); + end if; + end procedure endtest_msg; + + procedure check_msg( + constant rpt : in string; + constant timestamp : in time; + constant expr : in boolean; + constant actual : in string; + constant expected : in string; + constant mask : in string; + constant test_num : in integer; + constant test_name : in string; + constant check_num : in integer; + constant err_cnt_in_test : in integer + ) is + variable actual_str_len : integer := 1; + variable actual_str : string(1 to actual'length+8) := (others => ' '); + variable expected_str : string(1 to expected'length+10) := (others => ' '); + variable expected_str_len : integer := 1; + variable mask_str : string(1 to mask'length+6) := (others => ' '); + variable mask_str_len : integer := 1; + constant C_ACTUAL_PREFIX : string := " Actual="; + constant C_ACTUAL_POSTFIX : string := ""; + constant C_EXPECTED_PREFIX : string := " Expected="; + constant C_EXPECTED_POSTFIX : string := ""; + constant C_MASK_PREFIX : string := " Mask="; + constant C_MASK_POSTFIX : string := ""; + begin + if not expr then -- Output message only if the check fails + if str_equal(mask, "!NO_TAGS!") then + -- if mask=!NO_TAGS!, then do not add Actual= and Expected=" tags to strings + actual_str_len := actual'length; + actual_str(1 to actual_str_len) := actual; + expected_str_len := expected'length; + expected_str(1 to expected_str_len) := expected; + mask_str_len := 1; + else + -- Add Actual= and Expected= tags to strings + if actual /= "" then + --actual_str_len := 8 + actual'length; + --actual_str := " Actual=" & actual; + actual_str_len := C_ACTUAL_PREFIX'length + actual'length + C_ACTUAL_POSTFIX'length; + actual_str(1 to actual_str_len) := C_ACTUAL_PREFIX & tcfilter(actual) & C_ACTUAL_POSTFIX; + end if; + if expected /= "" then + --expected_str_len := 10 + expected'length; + --expected_str := " Expected=" & expected; + expected_str_len := C_EXPECTED_PREFIX'length + expected'length + C_EXPECTED_POSTFIX'length; + expected_str(1 to expected_str_len) := C_EXPECTED_PREFIX & tcfilter(expected) & C_EXPECTED_POSTFIX; + end if; + if mask /= "" then + --mask_str_len := 6 + mask'length; + --mask_str := " Mask=" & mask; + mask_str_len := C_MASK_PREFIX'length + mask'length + C_MASK_POSTFIX'length; + mask_str(1 to mask_str_len) := C_MASK_PREFIX & tcfilter(mask) & C_MASK_POSTFIX; + end if; + end if; + assert false + report "Check " & str(check_num) & "; " & rpt & "; " & + actual_str(1 to actual_str_len) & + expected_str(1 to expected_str_len) & + mask_str(1 to mask_str_len) & + " in test " & str(test_num) & " " & test_name + severity error; + end if; + end procedure check_msg; + + procedure error_msg( + constant rpt : in string; + constant timestamp : in time; + constant test_num : in integer; + constant test_name : in string; + constant err_cnt_in_test : in integer + ) is + begin + assert false + report rpt & " in test " & str(test_num) & ": " & test_name + severity error; + end procedure error_msg; + + procedure pltbutils_error( + constant rpt : in string; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ) is + begin + pltbv.err_cnt := pltbv.err_cnt + 1; + pltbv.err_cnt_in_test := pltbv.err_cnt_in_test + 1; + pltbs_update(pltbv, pltbs); + if C_PLTBUTILS_USE_STD_ERROR_MSG then + error_msg(rpt, now, pltbv.test_num, + pltbv.test_name(1 to pltbv.test_name_len), pltbv.err_cnt_in_test); + end if; + if C_PLTBUTILS_USE_CUSTOM_ERROR_MSG then + custom_error_msg(rpt, now, pltbv.test_num, + pltbv.test_name(1 to pltbv.test_name_len), pltbv.err_cnt_in_test); + end if; + end procedure pltbutils_error; + + procedure stopsim( + constant timestamp : in time + ) is + begin + assert false + report "--- FORCE END OF SIMULATION ---" & + " (ignore this false failure message, it's not a real failure)" + severity failure; + end procedure stopsim; + + procedure startsim_msg( + constant testcase_name : in string; + constant timestamp : in time + ) is + begin + print(lf & "--- START OF SIMULATION ---"); + print("Testcase: " & testcase_name); + print(time'image(timestamp)); + end procedure startsim_msg; + + procedure endsim_msg( + constant testcase_name : in string; + constant timestamp : in time; + constant num_tests : in integer; + constant num_skiptests : in integer; + constant num_checks : in integer; + constant num_errors : in integer; + constant show_success_fail : in boolean + ) is + variable l : line; + begin + print(lf & "--- END OF SIMULATION ---"); + print("Note: the results presented below are based on the PlTbUtil's check() procedure calls."); + print(" The design may contain more errors, for which there are no check() calls."); + write(l, timestamp, right, 14); + writeline(output, l); + write(l, num_tests, right, 11); + write(l, string'(" Tests")); + writeline(output, l); + write(l, num_skiptests, right, 11); + write(l, string'(" Skipped tests")); + writeline(output, l); + write(l, num_checks, right, 11); + write(l, string'(" Checks")); + writeline(output, l); + write(l, num_errors, right, 11); + write(l, string'(" Errors")); + writeline(output, l); + if show_success_fail then + if num_errors = 0 and num_checks > 0 then + print("*** SUCCESS ***"); + elsif num_checks > 0 then + print("*** FAIL ***"); + else + print("*** NO CHECKS ***"); + end if; + end if; + end procedure endsim_msg; + + + + -- Get next item (word) in a file + procedure get_file_item( + file f : text; + variable l : inout line; + variable item : out string; + variable item_len : out integer; + variable line_num : inout integer; + variable item_num : inout integer + ) is + variable c : character := ' '; + variable c_good : boolean := true; + variable i : integer := 0; + begin + item := (item'low to item'high => ' '); + item_len := 0; + while i = 0 loop + -- Get next line, unless we're already processing a line + if l = null then + exit when endfile(f); + readline(f, l); + line_num := line_num + 1; + elsif l'length = 0 then + exit when endfile(f); + readline(f, l); + line_num := line_num + 1; + end if; + + -- Find next item on the line + read(l, c, c_good); + -- Skip leading whitespace characters + while c_good and (c = ' ' or c = ht or c = cr or c = lf) loop + read(l, c, c_good); + end loop; + -- Read item until next whitespace, comment character or end-of-line + while c_good and c /= ' ' and c /= ht and c /= cr and c /= lf and c /= '#' loop + -- If i >= item'length, an error will occur. We don't try to do anything + -- about that here, because it is probably better that the user + -- find out the hard way, instead of trying to hide the problem. + item(item'low + i) := c; + i := i + 1; + read(l, c, c_good); + end loop; + + -- If a comment character was found, absorb the rest of the comment + if c_good and c = '#' then + while l'length > 0 loop + read(l, c, c_good); + end loop; + end if; + -- Update output values if item was found + if i > 0 then + item_len := i; + item_num := item_num + 1; + end if; + end loop; + end procedure get_file_item; + + + + --========================================================================== + -- pltbutils external (public) procedures + -- To be called from the user's code. + --========================================================================== + + ---------------------------------------------------------------------------- + -- startsim + -- + -- procedure startsim( + -- constant testcase_name : in string; + -- constant skiptests : in std_logic_vector; + -- variable pltbv : inout pltbv_t; + -- signal pltbs : out pltbs_t + -- ) + -- + -- Displays a message at start of simulation message, and initializes + -- PlTbUtils' status and control variable and -signal. + -- Call startsim() only once. + -- + -- Arguments: + -- testcase_name Name of the test case, e.g. "tc1". + -- + -- skiptests std_logic_vector for marking tests that should + -- be skipped. The leftmost bit has position 0, + -- and position numbers increment to the right. + -- A '1' indicates that the test with the same + -- number as the position should be skipped. + -- Note that there is usually no test which has + -- number 0, so bit zero in the vector is usually + -- ignored. + -- This argument is normally fed by a generic. + -- If no tests should be skipped, a zero-length + -- vector is allowed, (""). + -- + -- pltbv, pltbs PlTbUtils' status- and control variable and + -- -signal. + -- + -- NOTE: + -- The start-of-simulation message is not only intended to be informative + -- for humans. It is also intended to be searched for by scripts, + -- e.g. for collecting results from a large number of regression tests. + -- For this reason, the message must be consistent and unique. + -- + -- DO NOT MODIFY the message "--- START OF SIMULATION ---". + -- DO NOT OUTPUT AN IDENTICAL MESSAGE anywhere else. + -- + -- Examples: + -- startsim("tc1", "", pltbv, pltbs); + -- startsim("tc2", G_SKIPTESTS, pltbv, pltbs); -- G_SKIPTESTS is a generic + ---------------------------------------------------------------------------- + procedure startsim( + constant testcase_name : in string; + constant skiptests : in std_logic_vector; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ) is + variable timestamp : time; + variable v_ignored_skiptest : boolean := false; + begin + timestamp := now; + pltbv := C_PLTBV_INIT; + printv(pltbv.testcase_name, testcase_name); + pltbv.testcase_name_len := testcase_name'length; + printv(pltbv.test_name, "START OF SIMULATION"); + pltbv.test_name_len := 19; + printv(pltbv.info, testcase_name); + if skiptests'length > 0 then + for i in skiptests'low to skiptests'high loop + if i >= pltbv.skiptests'low and i <= pltbv.skiptests'high then + pltbv.skiptests(i) := skiptests(i); + else + if pltbv.skiptests(i) = '1' then + v_ignored_skiptest := true; + end if; + end if; + end loop; + if v_ignored_skiptest then + assert false + report "Some SKIPTESTS flags ignored. Max " & + integer'image(pltbv.skiptests'length) & " flag bits supported." + severity warning; + end if; + end if; + pltbv.info_len := testcase_name'length; + pltbs_update(pltbv, pltbs); + if C_PLTBUTILS_USE_STD_STARTSIM_MSG then + startsim_msg(testcase_name, timestamp); + end if; + if C_PLTBUTILS_USE_CUSTOM_STARTSIM_MSG then + custom_startsim_msg(testcase_name, timestamp); + end if; + end procedure startsim; + + ---------------------------------------------------------------------------- + -- endsim + -- + -- procedure endsim( + -- variable pltbv : inout pltbv_t; + -- signal pltbs : out pltbs_t; + -- constant show_success_fail : in boolean := false; + -- constant force_stop : in boolean := false + -- ) + -- + -- Displays a message at end of simulation message, presents the simulation + -- results, and stops the simulation. + -- Call endsim() it only once. + -- + -- Arguments: + -- pltbv, pltbs PlTbUtils' status- and control variable and + -- -signal. + -- + -- show_success_fail If true, endsim() shows "*** SUCCESS ***", + -- "*** FAIL ***", or "*** NO CHECKS ***". + -- Optional, default is false. + -- + -- force_stop If true, forces the simulation to stop using an + -- assert failure statement. Use this option only + -- if the normal way of stopping the simulation + -- doesn't work (see below). + -- Optional, default is false. + -- + -- The testbench should be designed so that all clocks stop when endsim() + -- sets the signal pltbs.stop_sim to '1'. This should stop the simulator. + -- In some cases that doesn't work, then set the force_stop argument to true, + -- which causes a false assert failure, which should stop the simulator. + -- Scripts searching transcript logs for errors and failures, should ignore + -- the failure with "--- FORCE END OF SIMULATION ---" as part of the report. + -- + -- NOTE: + -- The end-of-simulation messages and success/fail messages are not only + -- intended to be informative for humans. They are also intended to be + -- searched for by scripts, e.g. for collecting results from a large number + -- of regression tests. + -- For this reason, the message must be consistent and unique. + -- + -- DO NOT MODIFY the messages "--- END OF SIMULATION ---", + -- "*** SUCCESS ***", "*** FAIL ***", "*** NO CHECKS ***". + -- DO NOT OUTPUT IDENTICAL MESSAGES anywhere else. + -- + -- Examples: + -- endsim(pltbv, pltbs); + -- endsim(pltbv, pltbs, true); + -- endsim(pltbv, pltbs, true, true); + ---------------------------------------------------------------------------- + procedure endsim( + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant show_success_fail : in boolean := false; + constant force_stop : in boolean := false + ) is + variable timestamp : time; + begin + timestamp := now; + if C_PLTBUTILS_USE_STD_ENDSIM_MSG then + endsim_msg(pltbv.testcase_name(1 to pltbv.testcase_name_len), timestamp, + pltbv.test_cnt, pltbv.skiptest_cnt, pltbv.chk_cnt, pltbv.err_cnt, + show_success_fail); + end if; + if C_PLTBUTILS_USE_CUSTOM_ENDSIM_MSG then + custom_endsim_msg(pltbv.testcase_name(1 to pltbv.testcase_name_len), timestamp, + pltbv.test_cnt, pltbv.skiptest_cnt, pltbv.chk_cnt, pltbv.err_cnt, + show_success_fail); + end if; + pltbv.test_num := 0; + printv(pltbv.test_name, "END OF SIMULATION"); + pltbv.test_name_len := 17; + pltbv.stop_sim := '1'; + pltbs_update(pltbv, pltbs); + wait for C_WAIT_BEFORE_STOP_TIME; + if force_stop then + if C_PLTBUTILS_USE_STD_STOPSIM then + stopsim(now); + end if; + if C_PLTBUTILS_USE_CUSTOM_STOPSIM then + custom_stopsim(now); + end if; + end if; + wait; + end procedure endsim; + + ---------------------------------------------------------------------------- + -- starttest + -- + -- procedure starttest( + -- constant num : in integer := -1; + -- constant name : in string; + -- variable pltbv : inout pltbv_t; + -- signal pltbs : out pltbs_t + -- ) + -- + -- Sets a number (optional) and a name for a test. The number and name will + -- be printed to the screen, and displayed in the simulator's waveform + -- window. + -- The test number and name is also included if there errors reported by the + -- check() procedure calls. + -- + -- Arguments: + -- num Test number. Optional, default is to increment + -- the current test number. + -- + -- name Test name. + -- + -- pltbv, pltbs PlTbUtils' status- and control variable and + -- -signal. + -- + -- If the test number is omitted, a new test number is automatically + -- computed by incrementing the current test number. + -- Manually setting the test number may make it easier to find the test code + -- in the testbench code, though. + -- + -- Examples: + -- starttest("Reset test", pltbv, pltbs); + -- starttest(1, "Reset test", pltbv, pltbs); + ---------------------------------------------------------------------------- + procedure starttest( + constant num : in integer := -1; + constant name : in string; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ) is + variable timestamp : time; + begin + timestamp := now; + if num = -1 then + pltbv.test_num := pltbv.test_num + 1; + else + pltbv.test_num := num; + end if; + printv(pltbv.test_name, name); + pltbv.test_name_len := name'length; + pltbv.chk_cnt_in_test := 0; + pltbv.err_cnt_in_test := 0; + pltbv.test_active := true; + if pltbv.test_num >= pltbv.skiptests'low and pltbv.test_num <= pltbv.skiptests'high then + if pltbv.skiptests(pltbv.test_num) = '1' then + pltbv.test_active := false; + end if; + end if; + if pltbv.test_active then + pltbv.test_cnt := pltbv.test_cnt + 1; + pltbs_update(pltbv, pltbs); + if C_PLTBUTILS_USE_STD_STARTTEST_MSG then + starttest_msg(pltbv.test_num, name, timestamp); + end if; + if C_PLTBUTILS_USE_CUSTOM_STARTTEST_MSG then + custom_starttest_msg(pltbv.test_num, name, timestamp); + end if; + else + pltbv.skiptest_cnt := pltbv.skiptest_cnt + 1; + pltbs_update(pltbv, pltbs); + if C_PLTBUTILS_USE_STD_SKIPTEST_MSG then + skiptest_msg(pltbv.test_num, name, timestamp); + end if; + if C_PLTBUTILS_USE_CUSTOM_SKIPTEST_MSG then + custom_skiptest_msg(pltbv.test_num, name, timestamp); + end if; + end if; + end procedure starttest; + + procedure starttest( + constant name : in string; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ) is + begin + starttest(-1, name, pltbv, pltbs); + end procedure starttest; + + ---------------------------------------------------------------------------- + -- is_test_active + -- + -- function is_test_active( + -- constant pltbv : in pltbv_t + -- ) return boolean + -- + -- Returns true if a test is active (not skipped), otherwise false. + -- + -- Arguments: + -- pltbv PlTbUtils' status- and control variable. + -- + -- Example: + -- starttest(3, "Example test", pltbv, pltbs); + -- if is_test_active(pltbv) then + -- ... test code ... + -- end if; + -- endtest(pltbv, pltbs); + ---------------------------------------------------------------------------- + function is_test_active( + constant pltbv : in pltbv_t + ) return boolean is + begin + return pltbv.test_active; + end function is_test_active; + + ---------------------------------------------------------------------------- + -- endtest + -- + -- procedure endtest( + -- variable pltbv : inout pltbv_t; + -- signal pltbs : out pltbs_t + -- ) + -- + -- Prints an end-of-test message to the screen. + -- + -- Arguments: + -- pltbv, pltbs PlTbUtils' status- and control variable and + -- -signal. + -- + -- Example: + -- endtest(pltbv, pltbs); + ---------------------------------------------------------------------------- + procedure endtest( + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ) is + variable timestamp : time; + begin + timestamp := now; + if C_PLTBUTILS_USE_STD_ENDTEST_MSG then + endtest_msg(pltbv.test_num, pltbv.test_name(1 to pltbv.test_name_len), + timestamp, pltbv.test_active, pltbv.chk_cnt_in_test, pltbv.err_cnt_in_test); + end if; + if C_PLTBUTILS_USE_CUSTOM_ENDTEST_MSG then + custom_endtest_msg(pltbv.test_num, pltbv.test_name(1 to pltbv.test_name_len), + timestamp, pltbv.test_active, pltbv.chk_cnt_in_test, pltbv.err_cnt_in_test); + end if; + pltbv.test_active := true; + printv(pltbv.test_name, " "); + pltbv.test_name_len := 1; + pltbs_update(pltbv, pltbs); + end procedure endtest; + + ---------------------------------------------------------------------------- + -- print printv print2 + -- + -- procedure print( + -- signal s : out string; + -- constant txt : in string + -- ) + -- + -- procedure print( + -- constant active : in boolean; + -- signal s : out string; + -- constant txt : in string + -- ) + -- + -- procedure print( + -- variable pltbv : inout pltbv_t; + -- signal pltbs : out pltbs_t; + -- constant txt : in string + -- ) + -- + -- procedure print( + -- constant active : in boolean; + -- variable pltbv : inout pltbv_t; + -- signal pltbs : out pltbs_t; + -- constant txt : in string + -- ) + -- + -- procedure printv( + -- variable s : out string; + -- constant txt : in string + -- ) + -- + -- procedure printv( + -- constant active : in boolean; + -- variable s : out string; + -- constant txt : in string + -- ) + -- + -- procedure print2( + -- signal s : out string; + -- constant txt : in string + -- ) + -- + -- procedure print2( + -- constant active : in boolean; + -- signal s : out string; + -- constant txt : in string + -- ) + -- + -- procedure print2( + -- variable pltbv : inout pltbv_t; + -- signal pltbs : out pltbs_t; + -- constant txt : in string + -- ) + -- + -- procedure print2( + -- constant active : in boolean; + -- variable pltbv : inout pltbv_t; + -- signal pltbs : out pltbs_t; + -- constant txt : in string + -- ) + -- + -- print() prints text messages to a signal for viewing in the simulator's + -- waveform window. printv() does the same thing, but to a variable instead. + -- print2() prints both to a signal and to the transcript window. + -- The type of the output can be string or pltbv_t+pltbs_t. + -- + -- Arguments: + -- s Signal or variable of type string to be + -- printed to. + -- + -- txt The text. + -- + -- active The text is only printed if active is true. + -- Useful for debug switches, etc. + -- + -- pltbv, pltbs PlTbUtils' status- and control variable and + -- -signal. + -- + -- If the string txt is longer than the signal s, the text will be truncated. + -- If txt is shorter, s will be padded with spaces. + -- + -- Examples: + -- print(msg, "Hello, world"); -- Prints to signal msg + -- print(G_DEBUG, msg, "Hello, world"); -- Prints to signal msg if + -- -- generic G_DEBUG is true + -- printv(v_msg, "Hello, world"); -- Prints to variable msg + -- print(pltbv, pltbs, "Hello, world"); -- Prints to "info" in waveform window + -- print2(msg, "Hello, world"); -- Prints to signal and transcript window + -- print2(pltbv, pltbs, "Hello, world"); -- Prints to "info" in waveform and + -- -- transcript windows + ---------------------------------------------------------------------------- + procedure print( + constant active : in boolean; + signal s : out string; + constant txt : in string + ) is + variable j : positive := txt 'low; + begin + if active then + for i in s'range loop + if j <= txt 'high then + s(i) <= txt (j); + else + s(i) <= ' '; + end if; + j := j + 1; + end loop; + end if; + end procedure print; + + procedure print( + signal s : out string; + constant txt : in string + ) is + begin + print(true, s, txt); + end procedure print; + + procedure printv( + constant active : in boolean; + variable s : out string; + constant txt : in string + ) is + variable j : positive := txt 'low; + begin + if active then + for i in s'range loop + if j <= txt 'high then + s(i) := txt (j); + else + s(i) := ' '; + end if; + j := j + 1; + end loop; + end if; + end procedure printv; + + procedure printv( + variable s : out string; + constant txt : in string + ) is + begin + printv(true, s, txt); + end procedure printv; + + -- Print to info element in pltbv/pltbs, which shows up in waveform window + procedure print( + constant active : in boolean; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant txt : in string + ) is + variable j : positive := txt 'low; + begin + if active then + printv(pltbv.info, txt); + pltbv.info_len := txt'length; + pltbs_update(pltbv, pltbs); + end if; + end procedure print; + + procedure print( + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant txt : in string + ) is + begin + print(true, pltbv, pltbs, txt); + end procedure print; + + procedure print2( + constant active : in boolean; + signal s : out string; + constant txt : in string + ) is + begin + if active then + print(s, txt); + print(txt); + end if; + end procedure print2; + + procedure print2( + signal s : out string; + constant txt : in string + ) is + begin + print2(true, s, txt); + end procedure print2; + + procedure print2( + constant active : in boolean; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant txt : in string + ) is + begin + print(active, pltbv, pltbs, txt); + print(active, txt); + end procedure print2; + + procedure print2( + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant txt : in string + ) is + begin + print2(true, pltbv, pltbs, txt); + end procedure print2; + + ---------------------------------------------------------------------------- + -- waitclks + -- + -- procedure waitclks( + -- constant n : in natural; + -- signal clk : in std_logic; + -- variable pltbv : inout pltbv_t; + -- signal pltbs : out pltbs_t; + -- constant falling : in boolean := false; + -- constant timeout : in time := C_PLTBUTILS_TIMEOUT + -- ) + -- + -- Waits specified amount of clock cycles of the specified clock. + -- Or, to be more precise, a specified number of specified clock edges of + -- the specified clock. + -- + -- Arguments: + -- n Number of rising or falling clock edges to wait. + -- + -- clk The clock to wait for. + -- + -- pltbv, pltbs PlTbUtils' status- and control variable and + -- -signal. + -- + -- falling If true, waits for falling edges, otherwise + -- rising edges. Optional, default is false. + -- + -- timeout Timeout time, in case the clock is not working. + -- Optional, default is C_PLTBUTILS_TIMEOUT. + -- + -- Examples: + -- waitclks(5, sys_clk, pltbv, pltbs); + -- waitclks(5, sys_clk, pltbv, pltbs true); + -- waitclks(5, sys_clk, pltbv, pltbs, true, 1 ms); + ---------------------------------------------------------------------------- + procedure waitclks( + constant n : in natural; + signal clk : in std_logic; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant falling : in boolean := false; + constant timeout : in time := C_PLTBUTILS_TIMEOUT + ) is + variable i : natural := n; + variable v_timeout_time : time; + begin + v_timeout_time := now + timeout; + while i > 0 loop + if falling then + wait until falling_edge(clk) for timeout / n; + else + wait until rising_edge(clk) for timeout / n; + end if; + i := i - 1; + end loop; + if now >= v_timeout_time then + pltbutils_error("waitclks() timeout", pltbv, pltbs); + end if; + end procedure waitclks; + + ---------------------------------------------------------------------------- + -- waitsig + -- + -- procedure waitsig( + -- signal s : in integer|std_logic|std_logic_vector|unsigned|signed; + -- constant value : in integer|std_logic|std_logic_vector|unsigned|signed; + -- signal clk : in std_logic; + -- variable pltbv : inout pltbv_t; + -- signal pltbs : out pltbs_t; + -- constant falling : in boolean := false; + -- constant timeout : in time := C_PLTBUTILS_TIMEOUT + -- ) + -- + -- Waits until a signal has reached a specified value. In clocked variants of + -- waitsig, the signal is checked after specified clock edge (rising or falling). + -- Unclocked variants are currently only available for types std_logic and std_logic_vector. + -- + -- Arguments: + -- s The signal to test. + -- Supported types: integer, std_logic, + -- std_logic_vector, unsigned, signed. + -- + -- value Value to wait for. + -- Same type as data or integer. + -- + -- clk The clock, only present in clocked variants of + -- waitsig. + -- + -- pltbv, pltbs PlTbUtils' status- and control variable and + -- -signal. + -- + -- falling If true, waits for falling edges, otherwise + -- rising edges. Optional, default is false. + -- + -- timeout Timeout time, in case the clock is not working. + -- Optional, default is C_PLTBUTILS_TIMEOUT. + -- + -- Examples: + -- waitsig(wr_en, '1', sys_clk, pltbv, pltbs); + -- waitsig(rd_en, 1, sys_clk, pltbv, pltbs, true); + -- waitclks(full, '1', sys_clk, pltbv, pltbs, true, 1 ms); + ---------------------------------------------------------------------------- + -- waitsig integer, clocked + procedure waitsig( + signal s : in integer; + constant value : in integer; + signal clk : in std_logic; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant falling : in boolean := false; + constant timeout : in time := C_PLTBUTILS_TIMEOUT + ) is + variable v_timeout_time : time; + begin + v_timeout_time := now + timeout; + l1 : loop + waitclks(1, clk, pltbv, pltbs, falling, timeout); + exit l1 when s = value or now >= v_timeout_time; + end loop; + if now >= v_timeout_time then + pltbutils_error("waitsig() timeout", pltbv, pltbs); + end if; + end procedure waitsig; + + -- waitsig std_logic, clocked + procedure waitsig( + signal s : in std_logic; + constant value : in std_logic; + signal clk : in std_logic; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant falling : in boolean := false; + constant timeout : in time := C_PLTBUTILS_TIMEOUT + ) is + variable v_timeout_time : time; + begin + v_timeout_time := now + timeout; + l1 : loop + waitclks(1, clk, pltbv, pltbs, falling, timeout); + exit l1 when s = value or now >= v_timeout_time; + end loop; + if now >= v_timeout_time then + pltbutils_error("waitsig() timeout", pltbv, pltbs); + end if; + end procedure waitsig; + + -- waitsig std_logic against integer, clocked + procedure waitsig( + signal s : in std_logic; + constant value : in integer; + signal clk : in std_logic; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant falling : in boolean := false; + constant timeout : in time := C_PLTBUTILS_TIMEOUT + ) is + variable v_value : std_logic; + variable v_timeout_time : time; + begin + case value is + when 0 => v_value := '0'; + when 1 => v_value := '1'; + when others => v_value := 'X'; + end case; + if v_value /= 'X' then + waitsig(s, v_value, clk, pltbv, pltbs, falling, timeout); + else + pltbutils_error("waitsig() timeout", pltbv, pltbs); + end if; + end procedure waitsig; + + -- waitsig std_logic_vector, clocked + procedure waitsig( + signal s : in std_logic_vector; + constant value : in std_logic_vector; + signal clk : in std_logic; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant falling : in boolean := false; + constant timeout : in time := C_PLTBUTILS_TIMEOUT + ) is + variable v_timeout_time : time; + begin + v_timeout_time := now + timeout; + l1 : loop + waitclks(1, clk, pltbv, pltbs, falling, timeout); + exit l1 when s = value or now >= v_timeout_time; + end loop; + if now >= v_timeout_time then + pltbutils_error("waitsig() timeout", pltbv, pltbs); + end if; + end procedure waitsig; + + -- waitsig std_logic_vector against integer, clocked + procedure waitsig( + signal s : in std_logic_vector; + constant value : in integer; + signal clk : in std_logic; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant falling : in boolean := false; + constant timeout : in time := C_PLTBUTILS_TIMEOUT + ) is + variable v_timeout_time : time; + begin + waitsig(s, std_logic_vector(to_unsigned(value, s'length)), clk, + pltbv, pltbs, falling, timeout); + end procedure waitsig; + + -- waitsig unsigned, clocked + procedure waitsig( + signal s : in unsigned; + constant value : in unsigned; + signal clk : in std_logic; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant falling : in boolean := false; + constant timeout : in time := C_PLTBUTILS_TIMEOUT + ) is + variable v_timeout_time : time; + begin + v_timeout_time := now + timeout; + l1 : loop + waitclks(1, clk, pltbv, pltbs, falling, timeout); + exit l1 when s = value or now >= v_timeout_time; + end loop; + if now >= v_timeout_time then + pltbutils_error("waitsig() timeout", pltbv, pltbs); + end if; + end procedure waitsig; + + -- waitsig unsigned against integer, clocked + procedure waitsig( + signal s : in unsigned; + constant value : in integer; + signal clk : in std_logic; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant falling : in boolean := false; + constant timeout : in time := C_PLTBUTILS_TIMEOUT + ) is + variable v_timeout_time : time; + begin + waitsig(s, to_unsigned(value, s'length), clk, + pltbv, pltbs, falling, timeout); + end procedure waitsig; + + -- waitsig signed, clocked + procedure waitsig( + signal s : in signed; + constant value : in signed; + signal clk : in std_logic; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant falling : in boolean := false; + constant timeout : in time := C_PLTBUTILS_TIMEOUT + ) is + variable v_timeout_time : time; + begin + v_timeout_time := now + timeout; + l1 : loop + waitclks(1, clk, pltbv, pltbs, falling, timeout); + exit l1 when s = value or now >= v_timeout_time; + end loop; + if now >= v_timeout_time then + pltbutils_error("waitsig() timeout", pltbv, pltbs); + end if; + end procedure waitsig; + + -- waitsig signed against integer, clocked + procedure waitsig( + signal s : in signed; + constant value : in integer; + signal clk : in std_logic; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant falling : in boolean := false; + constant timeout : in time := C_PLTBUTILS_TIMEOUT + ) is + variable v_timeout_time : time; + begin + waitsig(s, to_signed(value, s'length), clk, + pltbv, pltbs, falling, timeout); + end procedure waitsig; + + -- waitsig std_logic, unclocked + procedure waitsig( + signal s : in std_logic; + constant value : in std_logic; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant timeout : in time := C_PLTBUTILS_TIMEOUT + ) is + begin + if s /= value then + wait until s = value for timeout; + if s /= value then + pltbutils_error("waitsig() timeout", pltbv, pltbs); + end if; + end if; + end procedure waitsig; + + -- waitsig std_logic edge, unclocked + procedure waitsig( + signal s : in std_logic; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant falling : in boolean := false; + constant timeout : in time := C_PLTBUTILS_TIMEOUT + ) is + variable v_timeout_time : time; + begin + if falling then + wait until falling_edge(s) for timeout; + else + wait until rising_edge(s) for timeout; + end if; + if (not ((falling and (s = '0' or s = 'L')) or ((not falling) and (s = '1' or s = 'H')))) then + pltbutils_error("waitsig() timeout", pltbv, pltbs); + end if; + end procedure waitsig; + + + ---------------------------------------------------------------------------- + -- check + -- + -- procedure check( + -- constant rpt : in string; + -- constant actual : in integer|std_logic|std_logic_vector|unsigned|signed|boolean|time|string; + -- constant expected : in integer|std_logic|std_logic_vector|unsigned|signed|boolean|time|string; + -- variable pltbv : inout pltbv_t; + -- signal pltbs : out pltbs_t + -- ) + -- + -- procedure check( + -- constant rpt : in string; + -- constant actual : in std_logic_vector; + -- constant expected : in std_logic_vector; + -- constant mask : in std_logic_vector; + -- variable pltbv : inout pltbv_t; + -- signal pltbs : out pltbs_t + -- ) + -- + -- procedure check( + -- constant rpt : in string; + -- constant actual : in time; + -- constant expected : in time; + -- constant tolerance : in time; + -- variable pltbv : inout pltbv_t; + -- signal pltbs : out pltbs_t + -- ) + -- + -- procedure check( + -- constant rpt : in string; + -- constant expr : in boolean; + -- variable pltbv : inout pltbv_t; + -- signal pltbs : out pltbs_t + -- ) + -- + -- Checks that the value of a signal or variable is equal to expected. + -- If not equal, displays an error message and increments the error counter. + -- + -- Arguments: + -- rpt Report message to be displayed in case of + -- mismatch. + -- It is recommended that the message is unique + -- and that it contains the name of the signal + -- or variable being checked. + -- The message should NOT contain the expected + -- value, becase check() prints that + -- automatically. + -- + -- actual The signal or variable to be checked. + -- Supported types: integer, std_logic, + -- std_logic_vector, unsigned, signed, boolean, + -- time, string. + -- + -- expected Expected value. + -- Same type as data or integer. + -- + -- mask Bit mask and:ed to data and expected + -- before comparison. + -- Optional if data is std_logic_vector. + -- Not allowed for other types. + -- + -- tolerance Allowed tolerance. Checks that + -- expected - tolerance <= actual <= expected + tolerance + -- is true. + -- + -- expr boolean expression for checking. + -- This makes it possible to check any kind of + -- expresion, not just equality. + -- + -- pltbv, pltbs PlTbUtils' status- and control variable and + -- -signal. + -- + -- Examples: + -- check("dat_o after reset", dat_o, 0, pltbv, pltbs); + -- -- With mask: + -- check("Status field in reg_o after start", reg_o, x"01", x"03", pltbv, pltbs); + -- -- Boolean expression: + -- check("Counter after data burst", cnt_o > 10, pltbv, pltbs); + ---------------------------------------------------------------------------- + -- check integer + procedure check( + constant rpt : in string; + constant actual : in integer; + constant expected : in integer; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ) is + begin + check(rpt, actual = expected, str(actual), str(expected), "", pltbv, pltbs); + end procedure check; + + -- check std_logic + procedure check( + constant rpt : in string; + constant actual : in std_logic; + constant expected : in std_logic; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ) is + begin + check(rpt, actual = expected, str(actual), str(expected), "", pltbv, pltbs); + end procedure check; + + -- check std_logic against integer + procedure check( + constant rpt : in string; + constant actual : in std_logic; + constant expected : in integer; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ) is + begin + check(rpt, ((actual = '0' and expected = 0) or (actual = '1' and expected = 1)), + str(actual), str(expected), "", pltbv, pltbs); + end procedure check; + + -- check std_logic_vector + procedure check( + constant rpt : in string; + constant actual : in std_logic_vector; + constant expected : in std_logic_vector; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ) is + begin + check(rpt, actual = expected, hxstr(actual, "0x"), hxstr(expected, "0x"), "", pltbv, pltbs); + end procedure check; + + -- check std_logic_vector with mask + procedure check( + constant rpt : in string; + constant actual : in std_logic_vector; + constant expected : in std_logic_vector; + constant mask : in std_logic_vector; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ) is + begin + check(rpt, (actual and mask) = (expected and mask), + hxstr(actual, "0x"), hxstr(expected, "0x"), hxstr(mask, "0x"), pltbv, pltbs); + end procedure check; + + -- check std_logic_vector against integer + procedure check( + constant rpt : in string; + constant actual : in std_logic_vector; + constant expected : in integer; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ) is + begin + check(rpt, actual, std_logic_vector(to_signed(expected, actual'length)), pltbv, pltbs); + end procedure check; + + -- check std_logic_vector with mask against integer + procedure check( + constant rpt : in string; + constant actual : in std_logic_vector; + constant expected : in integer; + constant mask : in std_logic_vector; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ) is + begin + check(rpt, actual, std_logic_vector(to_signed(expected, actual'length)), mask, pltbv, pltbs); + end procedure check; + + -- check unsigned + procedure check( + constant rpt : in string; + constant actual : in unsigned; + constant expected : in unsigned; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ) is + begin + check(rpt, actual = expected, hxstr(actual, "0x"), hxstr(expected, "0x"), "", pltbv, pltbs); + end procedure check; + + -- check unsigned against integer + procedure check( + constant rpt : in string; + constant actual : in unsigned; + constant expected : in integer; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ) is + begin + check(rpt, actual, to_unsigned(expected, actual'length), pltbv, pltbs); + end procedure check; + + -- check signed + procedure check( + constant rpt : in string; + constant actual : in signed; + constant expected : in signed; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ) is + begin + check(rpt, actual = expected, hxstr(actual, "0x"), hxstr(expected, "0x"), "", pltbv, pltbs); + end procedure check; + + -- check signed against integer + -- TODO: find the bug reported by tb_pltbutils when expected is negative (-1): + -- ** Error: (vsim-86) numstd_conv_unsigned_nu: NATURAL arg value is negative (-1) + procedure check( + constant rpt : in string; + constant actual : in signed; + constant expected : in integer; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ) is + begin + check(rpt, actual, to_signed(expected, actual'length), pltbv, pltbs); + end procedure check; + + -- check boolean + procedure check( + constant rpt : in string; + constant actual : in boolean; + constant expected : in boolean; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ) is + begin + check(rpt, actual = expected, str(actual), str(expected), "", pltbv, pltbs); + end procedure check; + + -- check boolean against integer + procedure check( + constant rpt : in string; + constant actual : in boolean; + constant expected : in integer; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ) is + begin + check(rpt, ((actual = false and expected = 0) or (actual = true and expected = 1)), + str(actual), str(expected), "", pltbv, pltbs); + end procedure check; + + -- check time + procedure check( + constant rpt : in string; + constant actual : in time; + constant expected : in time; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ) is + begin + check(rpt, actual = expected, time'image(actual), time'image(expected), "", pltbv, pltbs); + end procedure check; + + -- check time with tolerance + procedure check( + constant rpt : in string; + constant actual : in time; + constant expected : in time; + constant tolerance : in time; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ) is + begin + check(rpt, ((actual >= expected-tolerance) and (actual <= expected+tolerance)), + time'image(actual), time'image(expected) & " +/- " & time'image(tolerance), "", pltbv, pltbs); + end procedure check; + + -- check string + procedure check( + constant rpt : in string; + constant actual : in string; + constant expected : in string; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ) is + variable mismatch : boolean := false; + begin + if actual'length /= expected'length then + mismatch := true; + else + for i in 0 to actual'length-1 loop + if actual(i+actual'low) /= expected(i+expected'low) then + mismatch := true; + exit; + end if; + end loop; + end if; + check(rpt, not mismatch, actual, expected, "", pltbv, pltbs); + end procedure check; + + -- check with boolean expression + -- Check signal or variable with a boolean expression as argument expr. + -- This allowes any kind of check, including less than, greater than, + -- ranges, etc. But there are no clear messages in case of mismatch. + procedure check( + constant rpt : in string; + constant expr : in boolean; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ) is + begin + check(rpt, expr, "", "", "", pltbv, pltbs); + end procedure check; + + + ---------------------------------------------------------------------------- + -- check files + -- + -- procedure check_binfile | check_txtfile | check_datfile( + -- constant rpt : in string; + -- constant filename1 : in string; + -- constant filename2 : in string; + -- constant verbosity : in integer; + -- variable pltbv : inout pltbv_t; + -- signal pltbs : out pltbs_t + -- ) + -- + -- Checks that the contents of a file is equal to expected contents, by + -- comparing with a reference file. + -- If not equal, displays an error message and increments the error counter. + -- This is useful for examining different types of files generated by + -- testbench components during a simulation against reference files. + -- It can be different kinds of data sequences, video image data, etc. + -- + -- check_binfile compares two binary files. It uses "file of character" to + -- read bytes from the files. The VHDL LRM does not define how a + -- "file of character" should be written or to/read from disk. In theory, + -- there is a risk that a VHDL file of character is not compatible with + -- a normal binary file, but practical tests done with some popular + -- simulators have shown that they are compatible. This does not + -- guarantee that this procedure works with ALL simulators, and with + -- ALL future versions of the tested simulators. Use your own judgement. + -- + -- check_txtfile compares two text files. + -- + -- check_datfile compares two files with data formatted as follows. + -- The files contain a sequence of data items separated by whitespace + -- (spaces, tabs, newlines). The files can contain comments starting with + -- a hash sign (#), and ending at next newline. + -- Only the data items are compared. The types of whitespace and comments + -- are ignored. This is useful for different kinds of data dumps, + -- including some image file formats such as + -- Plain PBM (Portable Bit Map - P1, http://netpbm.sourceforge.net/doc/pbm.html ) + -- Plain PGM (Portable Gray Map - P2, http://netpbm.sourceforge.net/doc/pgm.html ) + -- Plain PPM (Portable Pixel Map - P3, http://netpbm.sourceforge.net/doc/ppm.html ) + -- + -- Arguments: + -- rpt Report message to be displayed in case of + -- mismatch. + -- It is recommended that the message is unique + -- and that it contains the name of the signal + -- or variable being checked. + -- + -- filename1 Name of first file to be compared, + -- including relative path from the simulator's + -- working directory. + -- + -- filename2 Name of second file to be compared, + -- including relative path from the simulator's + -- working directory. + -- + -- verbosity Controls amount of individual error reports when + -- differences between files are found, to make it + -- possible to prevent flooding with error messages. + -- 0: no individual differences reported + -- 1: the first ten differences reported + -- 2: all differences reported + -- + -- pltbv, pltbs PlTbUtils' status- and control variable and + -- -signal. + -- + -- Examples: + -- check_binfile("Data output file", "out_file.bin", "ref_file.bin", 0, pltbv, pltbs); + -- check_txtfile("Result file", G_RESULT_FILE, G_REF_FILE, G_CHECKFILE_VEROBOSITY, pltbv, pltbs); + -- check_datfile("Resulting image", "result_img.ppm", "ref_img.ppm", 2, pltbv, pltbs); + ---------------------------------------------------------------------------- + + -- check binary file + procedure check_binfile( + constant rpt : in string; + constant filename1 : in string; + constant filename2 : in string; + constant verbosity : in integer; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ) is + variable v_file_errors : integer := 0; + type charfile is file of character; + file f1 : charfile; + file f2 : charfile; + variable f1_status : file_open_status; + variable f2_status : file_open_status; + variable c1 : character; + variable c2 : character; + variable offset1 : integer := 0; + variable offset2 : integer := 0; + variable error_line : line; + begin + file_open(f1_status, f1, filename1, read_mode); + if f1_status /= open_ok then + v_file_errors := v_file_errors + 1; + write(error_line, " Could not open file " & filename1 & " for reading."); + else + file_open(f2_status, f2, filename2, read_mode); + if f2_status /= open_ok then + v_file_errors := v_file_errors + 1; + write(error_line, " Could not open file " & filename2 & " for reading. "); + file_close(f1); + end if; + end if; + if f1_status = open_ok and f2_status = open_ok then + while not endfile(f1) and not endfile(f2) loop + read(f1, c1); + read(f2, c2); + if c1 /= c2 then + v_file_errors := v_file_errors + 1; + if ((verbosity >= 2) or (verbosity = 1 and v_file_errors <= 10)) then + write(error_line, " Diff offset " & integer'image(offset1) & ": " & + integer'image(character'pos(c1)) & " /= " & integer'image(character'pos(c2)) & "."); + end if; + if verbosity = 1 and v_file_errors = 11 then + write(error_line, string'(" Further diffs suppressed.")); + end if; + end if; + offset1 := offset1 + 1; + offset2 := offset2 + 1; + end loop; + if v_file_errors > 0 then + write(error_line, " " & integer'image(v_file_errors) & " bytes differ."); + end if; + + -- Now one or both files are at the end. + -- Checking remaining size of possible non-ended file. + while not endfile(f1) loop + read(f1, c1); + offset1 := offset1 + 1; + end loop; + while not endfile(f2) loop + read(f2, c2); + offset2 := offset2 + 1; + end loop; + if offset1 /= offset2 then + v_file_errors := v_file_errors + 1; + write(error_line, " File sizes differ: " & integer'image(offset1) & + " /= " & integer'image(offset2) & " bytes."); + end if; + write(error_line, " (" & filename1 & ", " & filename2 & ")"); + end if; -- f1_status, f2_status + + if f1_status = open_ok then + file_close(f1); + end if; + if f2_status = open_ok then + file_close(f2); + end if; + + check(rpt, v_file_errors = 0, error_line.all, "", "!NO_TAGS!", pltbv, pltbs); + + if error_line /= null then + deallocate(error_line); + end if; + end procedure check_binfile; + + + -- check text file + procedure check_txtfile( + constant rpt : in string; + constant filename1 : in string; + constant filename2 : in string; + constant verbosity : in integer; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ) is + variable v_file_errors : integer := 0; + file f1 : text; + file f2 : text; + variable f1_status : file_open_status; + variable f2_status : file_open_status; + variable l1 : line; + variable l2 : line; + variable line_num1 : integer := 0; + variable line_num2 : integer := 0; + variable error_line : line; + begin + file_open(f1_status, f1, filename1, read_mode); + if f1_status /= open_ok then + v_file_errors := v_file_errors + 1; + write(error_line, " Could not open file " & filename1 & " for reading."); + else + file_open(f2_status, f2, filename2, read_mode); + if f2_status /= open_ok then + v_file_errors := v_file_errors + 1; + write(error_line, " Could not open file " & filename2 & " for reading. "); + file_close(f1); + end if; + end if; + if f1_status = open_ok and f2_status = open_ok then + while not endfile(f1) and not endfile(f2) loop + readline(f1, l1); + readline(f2, l2); + line_num1 := line_num1 + 1; + line_num2 := line_num2 + 1; + if l1.all /= l2.all then + v_file_errors := v_file_errors + 1; + if ((verbosity >= 2) or (verbosity = 1 and v_file_errors <= 10)) then + write(error_line, " Diff line " & integer'image(line_num1) & ": '" & + l1.all & "'' /= '" & l2.all & "'."); + end if; + if verbosity = 1 and v_file_errors = 11 then + write(error_line, string'(" Further diffs suppressed.")); + end if; + end if; + end loop; + if v_file_errors > 0 then + write(error_line, " " & integer'image(v_file_errors) & " lines differ."); + end if; + + -- Now one or both files are at the end. + -- Checking remaining size of possible non-ended file. + while not endfile(f1) loop + readline(f1, l1); + line_num1 := line_num1 + 1; + end loop; + while not endfile(f2) loop + readline(f2, l2); + line_num2 := line_num2 + 1; + end loop; + if line_num1 /= line_num2 then + v_file_errors := v_file_errors + 1; + write(error_line, " File sizes differ: " & integer'image(line_num1) & + " /= " & integer'image(line_num2) & " lines."); + end if; + write(error_line, " (" & filename1 & ", " & filename2 & ")"); + end if; -- f1_status, f2_status + + if f1_status = open_ok then + file_close(f1); + end if; + if f2_status = open_ok then + file_close(f2); + end if; + + check(rpt, v_file_errors = 0, error_line.all, "", "!NO_TAGS!", pltbv, pltbs); + + if error_line /= null then + deallocate(error_line); + end if; + end procedure check_txtfile; + + -- check data file + procedure check_datfile( + constant rpt : in string; + constant filename1 : in string; + constant filename2 : in string; + constant verbosity : in integer; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t; + constant skip_init_items : in integer := 0 + ) is + variable v_file_errors : integer := 0; + file f1 : text; + file f2 : text; + variable f1_status : file_open_status; + variable f2_status : file_open_status; + variable l1 : line; + variable l2 : line; + variable line_num1 : integer := 0; + variable line_num2 : integer := 0; + variable item1 : string(1 to 256); + variable item2 : string(1 to 256); + variable item_len1 : integer := -1; + variable item_len2 : integer := -1; + variable item_num1 : integer := 0; + variable item_num2 : integer := 0; + variable item_cnt : integer := 0; + variable error_line : line; + begin + file_open(f1_status, f1, filename1, read_mode); + if f1_status /= open_ok then + v_file_errors := v_file_errors + 1; + write(error_line, " Could not open file " & filename1 & " for reading: " & file_open_status'image(f1_status)); + else + file_open(f2_status, f2, filename2, read_mode); + if f2_status /= open_ok then + v_file_errors := v_file_errors + 1; + write(error_line, " Could not open file " & filename2 & " for reading: " & file_open_status'image(f2_status)); + file_close(f1); + end if; + end if; + if f1_status = open_ok and f2_status = open_ok then + while item_len1 /= 0 or item_len2 /= 0 loop + get_file_item(f1, l1, item1, item_len1, line_num1, item_num1); + get_file_item(f2, l2, item2, item_len2, line_num2, item_num2); + item_cnt := item_cnt + 1; + if item_len1 > 0 and item_len2 > 0 and item_cnt > skip_init_items then + if item1 /= item2 then + v_file_errors := v_file_errors + 1; + if ((verbosity >= 2) or (verbosity = 1 and v_file_errors <= 10)) then + write(error_line, " Diff item " & integer'image(item_num1) & ": '" & + item1(1 to item_len1) & "' /= '" & item2(1 to item_len2) & "'."); + end if; + if verbosity = 1 and v_file_errors = 11 then + write(error_line, string'(" Further diffs suppressed.")); + end if; + end if; + end if; + end loop; + + if v_file_errors > 0 then + write(error_line, " " & integer'image(v_file_errors) & " items differ."); + end if; + + -- Now one or both files are at the end. + -- Checking remaining size of possible non-ended file. + while not endfile(f1) loop + get_file_item(f1, l1, item1, item_len1, line_num1, item_num1); + end loop; + while not endfile(f2) loop + get_file_item(f2, l2, item2, item_len2, line_num2, item_num2); + end loop; + if item_num1 /= item_num2 then + v_file_errors := v_file_errors + 1; + write(error_line, " File sizes differ: " & integer'image(item_num1) & + " /= " & integer'image(item_num2) & " items."); + end if; + write(error_line, " (" & filename1 & ", " & filename2 & ")"); + end if; + + if f1_status = open_ok then + file_close(f1); + end if; + if f2_status = open_ok then + file_close(f2); + end if; + + check(rpt, v_file_errors = 0, error_line.all, "", "!NO_TAGS!", pltbv, pltbs); + + if error_line /= null then + deallocate(error_line); + end if; + end procedure check_datfile; + + + -- check base procedure + -- All other check procedures perform the check, and calls this procedure + -- with the check result in the expr argument. + -- This procedure can also be called directly. It allows any kind of check, + -- including less than, greater than, ranges, etc. + -- Your calling code must convert actual, expected and mask to strings. + procedure check( + constant rpt : in string; + constant expr : in boolean; + constant actual : in string; + constant expected : in string; + constant mask : in string; + variable pltbv : inout pltbv_t; + signal pltbs : out pltbs_t + ) is + variable timestamp : time; + begin + timestamp := now; + pltbv.chk_cnt := pltbv.chk_cnt + 1; + pltbv.chk_cnt_in_test := pltbv.chk_cnt_in_test + 1; + if not is_test_active(pltbv) then + pltbv.err_cnt := pltbv.err_cnt + 1; + pltbv.err_cnt_in_test := pltbv.err_cnt_in_test + 1; + if C_PLTBUTILS_USE_STD_CHECK_MSG then + check_msg("check() executed in skipped test, missing if clause?", timestamp, false, "", "", "", pltbv.test_num, + pltbv.test_name(1 to pltbv.test_name_len), pltbv.chk_cnt, pltbv.err_cnt_in_test); + end if; + if C_PLTBUTILS_USE_CUSTOM_CHECK_MSG then + custom_check_msg("check() executed in skipped test, missing if clause?", timestamp, false, "", "", "", pltbv.test_num, + pltbv.test_name(1 to pltbv.test_name_len), pltbv.chk_cnt, pltbv.err_cnt_in_test); + end if; + end if; + if not expr then + pltbv.err_cnt := pltbv.err_cnt + 1; + pltbv.err_cnt_in_test := pltbv.err_cnt_in_test + 1; + end if; + pltbs_update(pltbv, pltbs); + if C_PLTBUTILS_USE_STD_CHECK_MSG then + check_msg(rpt, timestamp, expr, actual, expected, mask, pltbv.test_num, + pltbv.test_name(1 to pltbv.test_name_len), pltbv.chk_cnt, pltbv.err_cnt_in_test); + end if; + if C_PLTBUTILS_USE_CUSTOM_CHECK_MSG then + custom_check_msg(rpt, timestamp, expr, actual, expected, mask, pltbv.test_num, + pltbv.test_name(1 to pltbv.test_name_len), pltbv.chk_cnt, pltbv.err_cnt_in_test); + end if; + pltbs_update(pltbv, pltbs); + end procedure check; + + + + ---------------------------------------------------------------------------- + -- to_ascending + -- + -- function to_ascending( + -- constant s : std_logic_vector + -- ) return std_logic_vector; + -- + -- function to_ascending( + -- constant s : unsigned + -- ) return unsigned + -- + -- function to_ascending( + -- constant s : signed + -- ) return signed; + -- + -- Converts a vector to ascending range ("to-range"). + -- The argument s can have ascending or descending range. + -- E.g. an argument defined as a std_logic_vector(3 downto 1) + -- will be returned as a std_logic_vector(1 to 3). + -- + -- Arguments: + -- s Constant, signal or variable to convert + -- + -- Return value: Converted value + -- + -- Examples: + -- ascending_sig <= to_ascending(descending_sig); + -- ascending_var := to_ascending(descending_var); + ---------------------------------------------------------------------------- + function to_ascending( + constant s : std_logic_vector + ) return std_logic_vector is + variable r : std_logic_vector(s'low to s'high); + begin + for i in r'range loop + r(i) := s(i); + end loop; + return r; + end function to_ascending; + + function to_ascending( + constant s : unsigned + ) return unsigned is + variable r : unsigned(s'low to s'high); + begin + for i in r'range loop + r(i) := s(i); + end loop; + return r; + end function to_ascending; + + function to_ascending( + constant s : signed + ) return signed is + variable r : signed(s'low to s'high); + begin + for i in r'range loop + r(i) := s(i); + end loop; + return r; + end function to_ascending; + + ---------------------------------------------------------------------------- + -- to_descending + -- + -- function to_descending( + -- constant s : std_logic_vector + -- ) return std_logic_vector; + -- + -- function to_descending( + -- constant s : unsigned + -- ) return unsigned + -- + -- function to_descending( + -- constant s : signed + -- ) return signed; + -- + -- Converts a vector to descending range ("downto-range"). + -- The argument s can have ascending or descending range. + -- E.g. an argument defined as a std_logic_vector(1 to 3) + -- will be returned as a std_logic_vector(3 downto 1). + -- + -- Arguments: + -- s Constant, signal or variable to convert + -- + -- Return value: Converted value + -- + -- Examples: + -- descending_sig <= to_descending(ascending_sig); + -- descending_var := to_descending(ascending_var); + ---------------------------------------------------------------------------- + function to_descending( + constant s : std_logic_vector + ) return std_logic_vector is + variable r : std_logic_vector(s'high downto s'low); + begin + for i in r'range loop + r(i) := s(i); + end loop; + return r; + end function to_descending; + + function to_descending( + constant s : unsigned + ) return unsigned is + variable r : unsigned(s'high downto s'low); + begin + for i in r'range loop + r(i) := s(i); + end loop; + return r; + end function to_descending; + + function to_descending( + constant s : signed + ) return signed is + variable r : signed(s'high downto s'low); + begin + for i in r'range loop + r(i) := s(i); + end loop; + return r; + end function to_descending; + + ---------------------------------------------------------------------------- + -- hxstr + -- function hxstr( + -- constant s : std_logic_vector; + -- constant prefix : string := ""; + -- constant postfix : string := "" + -- ) return string; + -- + -- function hxstr( + -- constant s : unsigned; + -- constant prefix : string := ""; + -- constant postfix : string := "" + -- ) return string; + -- + -- function hxstr( + -- constant s : signed; + -- constant prefix : string := ""; + -- constant postfix : string := "" + -- ) return string; + -- + -- Converts a vector to a string in hexadecimal format. + -- An optional prefix can be specified, e.g. "0x", as well as a suffix. + -- + -- The input argument can have ascending range ( "to-range" ) or descending range + -- ("downto-range"). There is no vector length limitation. + -- + -- Arguments: + -- s Constant, signal or variable to convert + -- + -- Return value: Converted value + -- + -- Examples: + -- print("value=" & hxstr(s)); + -- print("value=" & hxstr(s, "0x")); + -- print("value=" & hxstr(s, "16#", "#")); + ---------------------------------------------------------------------------- + function hxstr( + constant s : std_logic_vector; + constant prefix : string := ""; + constant postfix : string := "" + ) return string is + variable hexstr : string(1 to (s'length+3)/4); + variable nibble_aligned_s : std_logic_vector(((s'length+3)/4)*4-1 downto 0) := (others => '0'); + variable nibble : std_logic_vector(3 downto 0); + begin + nibble_aligned_s(s'length-1 downto 0) := to_descending(s); + for i in 0 to nibble_aligned_s'high/4 loop + nibble := nibble_aligned_s(4*i + 3 downto 4*i); + case nibble is + when "0000" => hexstr(hexstr'high-i) := '0'; + when "0001" => hexstr(hexstr'high-i) := '1'; + when "0010" => hexstr(hexstr'high-i) := '2'; + when "0011" => hexstr(hexstr'high-i) := '3'; + when "0100" => hexstr(hexstr'high-i) := '4'; + when "0101" => hexstr(hexstr'high-i) := '5'; + when "0110" => hexstr(hexstr'high-i) := '6'; + when "0111" => hexstr(hexstr'high-i) := '7'; + when "1000" => hexstr(hexstr'high-i) := '8'; + when "1001" => hexstr(hexstr'high-i) := '9'; + when "1010" => hexstr(hexstr'high-i) := 'A'; + when "1011" => hexstr(hexstr'high-i) := 'B'; + when "1100" => hexstr(hexstr'high-i) := 'C'; + when "1101" => hexstr(hexstr'high-i) := 'D'; + when "1110" => hexstr(hexstr'high-i) := 'E'; + when "1111" => hexstr(hexstr'high-i) := 'F'; + when "UUUU" => hexstr(hexstr'high-i) := 'U'; + when "XXXX" => hexstr(hexstr'high-i) := 'X'; + when "ZZZZ" => hexstr(hexstr'high-i) := 'Z'; + when "WWWW" => hexstr(hexstr'high-i) := 'W'; + when "LLLL" => hexstr(hexstr'high-i) := 'L'; + when "HHHH" => hexstr(hexstr'high-i) := 'H'; + when "----" => hexstr(hexstr'high-i) := '-'; + when others => hexstr(hexstr'high-i) := '?'; + -- TODO: handle vectors where nibble_aligned_s'length > a'length and the highest nibble are all equal characters such as "XXX" + end case; + end loop; + return prefix & hexstr & postfix; + end function hxstr; + + function hxstr( + constant s : unsigned; + constant prefix : string := ""; + constant postfix : string := "" + ) return string is + begin + return hxstr(std_logic_vector(s), prefix, postfix); + end function hxstr; + + function hxstr( + constant s : signed; + constant prefix : string := ""; + constant postfix : string := "" + ) return string is + begin + return hxstr(std_logic_vector(s), prefix, postfix); + end function hxstr; + + ---------------------------------------------------------------------------- + -- Miscellaneous + ---------------------------------------------------------------------------- + -- function str converts integer n to a string with fixed length len and + -- leading fillchar + function str( + constant n : integer; + constant len : integer; + constant fillchar : character := ' ' + ) return string is + variable s : string(1 to len) := (others => fillchar); + variable val : integer := n; + variable digit : integer; + begin + for i in 0 to len-1 loop + if val > 0 then + digit := val mod 10; + val := val / 10; + s(len - i) := character'val(character'pos('0') + digit); + end if; + end loop; + assert val = 0 + report "str: value " & integer'image(n) & " does not fit in string with length " & integer'image(len) + severity error; + return s; + end function str; + + -- Function str_equal returns true if strings s1 and s2 are equal, otherwise false. + -- The normal VHDL string comparison s1 = s2 only works correctly if the length of + -- the strings are equal. str_equal works even if the lengths differ. + function str_equal ( + constant s1 : STRING; + constant s2 : STRING + ) return boolean is + begin + if s1'length /= s2'length then + return FALSE; + else + return (s1 = s2); + end if; + end function str_equal; + +end package body pltbutils_func_pkg; Index: pltbutils/tags/v1.3/src/vhdl/pltbutils_comp.vhd =================================================================== --- pltbutils/tags/v1.3/src/vhdl/pltbutils_comp.vhd (nonexistent) +++ pltbutils/tags/v1.3/src/vhdl/pltbutils_comp.vhd (revision 110) @@ -0,0 +1,213 @@ +---------------------------------------------------------------------- +---- ---- +---- PlTbUtils Components ---- +---- ---- +---- This file is part of the PlTbUtils project ---- +---- http://opencores.org/project,pltbutils ---- +---- ---- +---- Description: ---- +---- PlTbUtils is a collection of functions, procedures and ---- +---- components for easily creating stimuli and checking response ---- +---- in automatic self-checking testbenches. ---- +---- ---- +---- pltbutils_comp.vhd (this file) defines testbench components. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Per Larsson, pela.opencores@gmail.com ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013-2020 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- pltbutils_clkgen +-- Creates a clock for use in a testbech. +-- A non-inverted as well as an inverted output is available, +-- use one or both depending on if you need a single-ended or +-- differential clock. +-- The clock stops when input port stop_sim goes '1'. +-- This makes the simulator stop (unless there are other infinite +-- processes running in the simulation). +---------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; + +entity pltbutils_clkgen is + generic ( + G_PERIOD : time := 10 ns; + G_INITVALUE : std_logic := '0' + ); + port ( + clk_o : out std_logic; + clk_n_o : out std_logic; + stop_sim_i : in std_logic + ); +end entity pltbutils_clkgen; + +architecture bhv of pltbutils_clkgen is + constant C_HALF_PERIOD : time := G_PERIOD / 2; + signal clk : std_logic := G_INITVALUE; +begin + + clk <= not clk and not stop_sim_i after C_HALF_PERIOD; + clk_o <= clk; + clk_n_o <= not clk; + +end architecture bhv; + + +---------------------------------------------------------------------- +-- pltbutils_time_measure +-- Measures high-time, low-time and period of a signal, usually a +-- clock. +-- Setting G_VERBOSITY to at least 20 reports measures times. +-- Set G_RPT_LABEL to a prefix used in reports, typically the name +-- of the signal being measured. +---------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; + +entity pltbutils_time_measure is + generic ( + G_VERBOSITY : integer := 0; + G_RPT_LABEL : string := "pltbutils_time_measure" + ); + port ( + t_hi_o : out time; -- High time + t_lo_o : out time; -- Low time + t_per_o : out time; -- Period time + s_i : in std_logic -- Signal to measure + ); +end entity pltbutils_time_measure; + +architecture bhv of pltbutils_time_measure is + signal t_hi : time := 0 ns; + signal t_lo : time := 0 ns; + signal t_per : time := 0 ns; +begin + + measure_p : process (s_i) + variable last_rising_edge : time := -1 ns; + variable last_falling_edge : time := -1 ns; + begin + if rising_edge(s_i) then + if last_falling_edge >= 0 ns then + t_lo <= now - last_falling_edge; + end if; + if last_rising_edge >= 0 ns then + t_per <= now - last_rising_edge; + end if; + last_rising_edge := now; + end if; + + if falling_edge(s_i) then + if last_rising_edge >= 0 ns then + t_hi <= now - last_rising_edge; + end if; + last_falling_edge := now; + end if; + end process measure_p; + + assert not (G_VERBOSITY > 20 and t_lo'event) + report G_RPT_LABEL & ": t_lo=" & time'image(t_lo) + severity note; + + assert not (G_VERBOSITY > 20 and t_hi'event) + report G_RPT_LABEL & ": t_hi=" & time'image(t_hi) + severity note; + + assert not (G_VERBOSITY > 20 and t_per'event) + report G_RPT_LABEL & ": t_hi=" & time'image(t_per) + severity note; + + t_hi_o <= t_hi; + t_lo_o <= t_lo; + t_per_o <= t_per; + +end architecture bhv; + + +---------------------------------------------------------------------- +-- pltbutils_diff_check +-- Checks that the negative half of a diff pair is the +-- always the complement of the positive half. +-- Setting G_VERBOSITY to at least 100 reports number of diff errors. +-- Set G_RPT_LABEL to a prefix used in reports, typically the name +-- of the signal being measured. +---------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; + +entity pltbutils_diff_check is + generic ( + G_VERBOSITY : integer := 0; + G_RPT_LABEL : string := "pltbutils_diff_check" + ); + port ( + diff_error_o : out std_logic; -- High when diff error detected + diff_errors_o : out integer; -- Number of diff errors detected + s_i : in std_logic; -- Pos half of diff pair to check + s_n_i : in std_logic := '0'; -- Neg half of diff pair to check + rst_errors_i : in std_logic := '0' -- High resets diff error counter + ); +end entity pltbutils_diff_check; + +architecture bhv of pltbutils_diff_check is + constant C_INTEGER_MAX : integer := (2**30) + ((2**30)-1); -- Equals (2**31)-1 without overflowing; + signal diff_error : std_logic := '0'; + signal diff_errors : integer := 0; +begin + + diff_check_p : process (s_i, s_n_i, rst_errors_i) + -- TODO: allow a small (configurable) timing tolerance between edges of s_i and s_n_i + begin + if s_i /= not s_n_i then + diff_error <= '1'; + if diff_errors < C_INTEGER_MAX then + diff_errors <= diff_errors + 1; + end if; + else + diff_error <= '0'; + end if; + if rst_errors_i = '1' then + diff_errors <= 0; + end if; + end process diff_check_p; + + assert not (G_VERBOSITY > 100 and diff_errors'event) + report G_RPT_LABEL & ": diff_errors=" & integer'image(diff_errors) + severity note; + + diff_error_o <= diff_error; + diff_errors_o <= diff_errors; + +end architecture bhv; + + Index: pltbutils/tags/v1.3/src/vhdl/pltbutils_comp_pkg.vhd =================================================================== --- pltbutils/tags/v1.3/src/vhdl/pltbutils_comp_pkg.vhd (nonexistent) +++ pltbutils/tags/v1.3/src/vhdl/pltbutils_comp_pkg.vhd (revision 110) @@ -0,0 +1,142 @@ +---------------------------------------------------------------------- +---- ---- +---- PlTbUtils Component Declarations ---- +---- ---- +---- This file is part of the PlTbUtils project ---- +---- http://opencores.org/project,pltbutils ---- +---- ---- +---- Description: ---- +---- PlTbUtils is a collection of functions, procedures and ---- +---- components for easily creating stimuli and checking response ---- +---- in automatic self-checking testbenches. ---- +---- ---- +---- This file declares testbench components, which are defined ---- +---- in pltbutils_comp.vhd . ---- +---- "use" this file in your testbech, e.g. ---- +---- use work.pltbutils_comp_pkg.all; ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Per Larsson, pela.opencores@gmail.com ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013-2020 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +package pltbutils_comp_pkg is + + -- See pltbutils_comp.vhd for a description of the components. + + component pltbutils_clkgen is + generic ( + G_PERIOD : time := 10 ns; + G_INITVALUE : std_logic := '0' + ); + port ( + clk_o : out std_logic; + clk_n_o : out std_logic; + stop_sim_i : in std_logic + ); + end component pltbutils_clkgen; + + -- Instansiation template + -- (copy to your own file and remove the comment characters): + --pltbutils_clkgen0 : pltbutils_clkgen + -- generic map ( + -- G_PERIOD => G_PERIOD, + -- G_INITVALUE => '0' + -- ) + -- port map ( + -- clk_o => clk, + -- clk_n_o => clk_n, + -- stop_sim_i => pltbs.stop_sim + -- ); + + component pltbutils_time_measure is + generic ( + G_VERBOSITY : integer := 0; + G_RPT_LABEL : string := "pltbutils_time_measure" + ); + port ( + t_hi_o : out time; -- High time + t_lo_o : out time; -- Low time + t_per_o : out time; -- Period time + s_i : in std_logic -- Signal to measure + ); + end component pltbutils_time_measure; + + -- Instansiation template + -- (copy to your own file and remove the comment characters): + --pltbutils_time_measure0 : pltbutils_time_measure + -- generic map ( + -- G_VERBOSITY => G_VERBOSITY + -- G_RPT_LABEL => "sig" + -- ) + -- port map ( + -- t_hi_o => sig_t_hi, + -- t_lo_o => sig_t_lo, + -- t_per_o => sig_t_per, + -- s_i => sig + -- ); + + component pltbutils_diff_check is + generic ( + G_VERBOSITY : integer := 0; + G_RPT_LABEL : string := "pltbutils_diff_check" + ); + port ( + diff_error_o : out std_logic; -- High when diff error detected + diff_errors_o : out integer; -- Number of diff errors detected + s_i : in std_logic; -- Pos half of diff pair to check + s_n_i : in std_logic := '0'; -- Neg half of diff pair to check + rst_errors_i : in std_logic := '0' -- High resets diff error counter + ); + end component pltbutils_diff_check; + + -- Instansiation template + -- (copy to your own file and remove the comment characters): + --pltbutils_diff_check0 : pltbutils_diff_check + -- generic map ( + -- G_VERBOSITY => G_VERBOSITY + -- G_RPT_LABEL => "sig" + -- ) + -- port map ( + -- diff_error => sig_diff_error, + -- diff_errors => sig_diff_errors, + -- s_i => sig, + -- s_n_i => sig_n, + -- rst_errors_i => sig_rst_errors + -- ); + +end package pltbutils_comp_pkg; + + Index: pltbutils/tags/v1.3/src/vhdl/pltbutils_user_cfg_pkg.vhd =================================================================== --- pltbutils/tags/v1.3/src/vhdl/pltbutils_user_cfg_pkg.vhd (nonexistent) +++ pltbutils/tags/v1.3/src/vhdl/pltbutils_user_cfg_pkg.vhd (revision 110) @@ -0,0 +1,351 @@ +---------------------------------------------------------------------- +---- ---- +---- PlTbUtils User Configuration Package ---- +---- ---- +---- This file is part of the PlTbUtils project ---- +---- http://opencores.org/project,pltbutils ---- +---- ---- +---- Description: ---- +---- PlTbUtils is a collection of functions, procedures and ---- +---- components for easily creating stimuli and checking response ---- +---- in automatic self-checking testbenches. ---- +---- ---- +---- This file defines the user's customizations. ---- +---- ---- +---- If the user wishes to modify anything in this file, it is ---- +---- recommended that he/she first copies it to another directory ---- +---- and modifies the copy. Also make sure that the simulator ---- +---- read the modified file instead of the original. ---- +---- This makes it easier to update pltbutils to new versions ---- +---- without destroying the customizations. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Per Larsson, pela.opencores@gmail.com ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2014-2020 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; +--use std.env.all; -- Uncomment if using stop or finish in custom_stopsim() below. +use work.txt_util.all; + +package pltbutils_user_cfg_pkg is + + --- Constants --- + -- The user is free to modify the values to fit his/her requirements. + constant C_PLTBUTILS_USE_STD_STARTSIM_MSG : boolean := true; + constant C_PLTBUTILS_USE_STD_ENDSIM_MSG : boolean := true; + constant C_PLTBUTILS_USE_STD_STARTTEST_MSG : boolean := true; + constant C_PLTBUTILS_USE_STD_SKIPTEST_MSG : boolean := true; + constant C_PLTBUTILS_USE_STD_ENDTEST_MSG : boolean := true; + constant C_PLTBUTILS_USE_STD_CHECK_MSG : boolean := true; + constant C_PLTBUTILS_USE_STD_ERROR_MSG : boolean := true; + constant C_PLTBUTILS_USE_STD_STOPSIM : boolean := true; + constant C_PLTBUTILS_USE_CUSTOM_STARTSIM_MSG : boolean := false; + constant C_PLTBUTILS_USE_CUSTOM_ENDSIM_MSG : boolean := false; + constant C_PLTBUTILS_USE_CUSTOM_STARTTEST_MSG : boolean := false; + constant C_PLTBUTILS_USE_CUSTOM_SKIPTEST_MSG : boolean := false; + constant C_PLTBUTILS_USE_CUSTOM_ENDTEST_MSG : boolean := false; + constant C_PLTBUTILS_USE_CUSTOM_CHECK_MSG : boolean := false; + constant C_PLTBUTILS_USE_CUSTOM_ERROR_MSG : boolean := false; + constant C_PLTBUTILS_USE_CUSTOM_STOPSIM : boolean := false; + + --- Procedure declarations --- + -- The user should NOT modify these. + + procedure custom_stopsim( + constant timestamp : in time + ); + + procedure custom_startsim_msg( + constant testcase_name : in string; + constant timestamp : in time + ); + + procedure custom_endsim_msg( + constant testcase_name : in string; + constant timestamp : in time; + constant num_tests : in integer; + constant num_skip_tests : in integer; + constant num_checks : in integer; + constant num_errors : in integer; + constant show_success_fail : in boolean + ); + + procedure custom_starttest_msg( + constant test_num : in integer; + constant test_name : in string; + constant timestamp : in time + ); + + procedure custom_skiptest_msg( + constant test_num : in integer; + constant test_name : in string; + constant timestamp : in time + ); + + procedure custom_endtest_msg( + constant test_num : in integer; + constant test_name : in string; + constant timestamp : in time; + constant test_active : in boolean; + constant num_checks_in_test : in integer; + constant num_errors_in_test : in integer + ); + + procedure custom_check_msg( + constant rpt : in string; + constant timestamp : in time; + constant expr : in boolean; + constant actual : in string; + constant expected : in string; + constant mask : in string; + constant test_num : in integer; + constant test_name : in string; + constant check_num : in integer; + constant err_cnt_in_test : in integer + ); + + procedure custom_error_msg( + constant rpt : in string; + constant timestamp : in time; + constant test_num : in integer; + constant test_name : in string; + constant err_cnt_in_test : in integer + ); + + --- User's function and procedure declarations --- + -- Example for use with TeamCity. Remove, modify or replace + -- to suit other other continous integration tools or scripts, if you need to. + function tcfilter( + constant s : string + ) return string; + +end package pltbutils_user_cfg_pkg; + +package body pltbutils_user_cfg_pkg is + + --- Procedure definitions --- + -- The user should NOT modify the arguments, + -- but the behaviour is free to modify to fit the user's requirements. + + procedure custom_stopsim( + constant timestamp : in time + ) is + begin + -- The best way to stop a simulation differs between different simulators. + -- Below are some examples. Modify to suit your simulator. + + -- Works with some simulators that supports VHDL-2008. + -- Requires that 'use std.env.all' at the top of the file is uncommented. + --stop; + + -- Works with some simulators that support VHDL-2008. + -- Requires that 'use std.env.all' at the top of the file is uncommented. + --finish; + + -- Works in all simulators known by the author, but ugly. + assert false + report "--- FORCE END OF SIMULATION ---" & + " (ignore this false failure message, it's not a real failure)" + severity failure; + + end procedure custom_stopsim; + + -- Example custom messages for TeamCity. + -- Edit to suit other continous integration tools or scripts, if you need to. + -- General TeamCity information: http://www.jetbrains.com/teamcity/ + -- http://en.wikipedia.org/wiki/Teamcity + -- TeamCity test reporting: http://confluence.jetbrains.com/display/TCD8/Build+Script+Interaction+with+TeamCity#BuildScriptInteractionwithTeamCity-ReportingTests + + procedure custom_startsim_msg( + constant testcase_name : in string; + constant timestamp : in time + ) is + begin + print("##teamcity[testSuiteStarted name='" & tcfilter(testcase_name) & "']"); + end procedure custom_startsim_msg; + + procedure custom_endsim_msg( + constant testcase_name : in string; + constant timestamp : in time; + constant num_tests : in integer; + constant num_skip_tests : in integer; + constant num_checks : in integer; + constant num_errors : in integer; + constant show_success_fail : in boolean + ) is + begin + -- TeamCity ignores all arguments except testcase_name + print("##teamcity[testSuiteFinished name='" & tcfilter(testcase_name) & "']"); + end procedure custom_endsim_msg; + + procedure custom_starttest_msg( + constant test_num : in integer; + constant test_name : in string; + constant timestamp : in time + ) is + begin + -- TeamCity ignores test_num and timestamp + print("##teamcity[testStarted name='" & tcfilter(test_name) & "']"); + end procedure custom_starttest_msg; + + procedure custom_skiptest_msg( + constant test_num : in integer; + constant test_name : in string; + constant timestamp : in time + ) is + begin + -- TeamCity ignores test_num and timestamp + print("##teamcity[testIgnored name='" & tcfilter(test_name) & "']"); + end procedure custom_skiptest_msg; + + procedure custom_endtest_msg( + constant test_num : in integer; + constant test_name : in string; + constant timestamp : in time; + constant test_active : in boolean; + constant num_checks_in_test : in integer; + constant num_errors_in_test : in integer + ) is + begin + if test_active then + -- TeamCity ignores all arguments except test_name + print("##teamcity[testFinished name='" & tcfilter(test_name) & "']"); + end if; + end procedure custom_endtest_msg; + + procedure custom_check_msg( + constant rpt : in string; + constant timestamp : in time; + constant expr : in boolean; + constant actual : in string; + constant expected : in string; + constant mask : in string; + constant test_num : in integer; + constant test_name : in string; + constant check_num : in integer; + constant err_cnt_in_test : in integer + ) is + variable l : line; + constant C_NO_TAGS_STR : string := "!NO_TAGS!"; + variable no_tags : boolean := false; + begin + if not expr then -- Output message only if the check fails + if err_cnt_in_test <= 1 then -- TeamCity allows max one error message per test + if mask'length = C_NO_TAGS_STR'length then + if mask = C_NO_TAGS_STR then + no_tags := true; + end if; + end if; + if no_tags then + write(l, "##teamcity[testFailed name='" & tcfilter(test_name) & "'"); + write(l, " message='" & tcfilter(rpt) & "'"); + if actual /= "" or expected /= "" then + write(l, " details='" & tcfilter(actual)); + if actual /= "" and expected /= "" then + write(l, string'(" ")); + end if; + write(l, tcfilter(expected) & "'"); + end if; + write(l, string'("]")); + else + write(l, "##teamcity[testFailed type='comparisonFailure' name='" & tcfilter(test_name) & "'"); + if expected /= "" then + write(l, " expected='" & tcfilter(expected) & "'"); + end if; + if actual /= "" then + write(l, " actual='" & tcfilter(actual) & "'"); + end if; + if mask /= "" then + write(l, " details='mask=" & tcfilter(mask) & "'"); + end if; + write(l, string'("]")); + end if; + print(l.all); + else + print("(TeamCity error message filtered out, because max one message is allowed for each test)"); + end if; + end if; + end procedure custom_check_msg; + + procedure custom_error_msg( + constant rpt : in string; + constant timestamp : in time; + constant test_num : in integer; + constant test_name : in string; + constant err_cnt_in_test : in integer + ) is + begin + if err_cnt_in_test <= 1 then -- TeamCity allows max one error message per test + print("##teamcity[testFailed" & + "name='" & tcfilter(test_name) & "' " & + "message='" & tcfilter(rpt) & "']"); + else + print("(TeamCity error message filtered out, because max one message is allowed for each test)"); + end if; + end procedure custom_error_msg; + + --- User's function and procedure definitions --- + -- Example for use with TeamCity. Remove, modify or replace + -- to suit other other continous integration tools or scripts, if you need to. + + -- TeamCity string filter. Filters out characters which are not allowed in TeamCity messages. + -- Search for "escaped values" in + -- http://confluence.jetbrains.com/display/TCD8/Build+Script+Interaction+with+TeamCity#BuildScriptInteractionwithTeamCity-ReportingTests + -- The TeamCity escape character is not used, because that changes the length of the string. + -- The VHDL code can be simplified if it doesn't have to deal with changes of string + -- lengths. + function tcfilter( + constant s : string + ) return string is + variable r : string(s'range) := (others => (' ')); + begin + for i in s'range loop + if s(i) = ''' then + r(i) := '`'; + elsif s(i) = lf or s(i) = cr then + r(i) := ' '; + elsif s(i) = '|' then + r(i) := '/'; + elsif s(i) = '[' then + r(i) := '{'; + elsif s(i) = ']' then + r(i) := '}'; + else + r(i) := s(i); + end if; + end loop; + return r; + end function tcfilter; + +end package body pltbutils_user_cfg_pkg; Index: pltbutils/tags/v1.3/src/vhdl/pltbutils_files.lst =================================================================== --- pltbutils/tags/v1.3/src/vhdl/pltbutils_files.lst (nonexistent) +++ pltbutils/tags/v1.3/src/vhdl/pltbutils_files.lst (revision 110) @@ -0,0 +1,5 @@ +txt_util.vhd +pltbutils_user_cfg_pkg.vhd +pltbutils_func_pkg.vhd +pltbutils_comp.vhd +pltbutils_comp_pkg.vhd Index: pltbutils/tags/v1.3/src/vhdl/txt_util.vhd =================================================================== --- pltbutils/tags/v1.3/src/vhdl/txt_util.vhd (nonexistent) +++ pltbutils/tags/v1.3/src/vhdl/txt_util.vhd (revision 110) @@ -0,0 +1,881 @@ +---------------------------------------------------------------------- +---- ---- +---- txt_util.vhd ---- +---- ---- +---- This file is part of the PlTbUtils project ---- +---- http://opencores.org/project,pltbutils ---- +---- ---- +---- Description: ---- +---- PlTbUtils is a collection of functions, procedures and ---- +---- components for easily creating stimuli and checking response ---- +---- in automatic self-checking testbenches. ---- +---- ---- +---- This file defines useful functions an procedures for text ---- +---- handling text in VHDL. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Source: ---- +---- http://www.mrc.uidaho.edu/mrc/people/jff/vhdl_info/txt_util.vhd - +---- Thanks to Stefan Doll and James F. Frenzel. ---- ---- +---------------------------------------------------------------------- +-- +-- Disclaimer: Derived from txt_util.vhd on www.stefanvhdl.com +-- +-- Revision History: +-- +-- 1.0 URL: http://www.stefanvhdl.com/vhdl/vhdl/txt_util.vhd +-- +-- 1.1 Modified str_read() to prevent extra character (JFF) +-- +-- 1.2 Added is_whitespace() and strip_whitespace() (JFF) +-- +-- 1.3 Added first_string() and chomp() (JFF) +-- +-- 1.4 Added hex string and integer string conversion (JFF) +-- +---------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; + +package txt_util is + + -- prints a message to the screen + procedure print(text: string); + + -- prints the message when active + -- useful for debug switches + procedure print(active: boolean; text: string); + + -- converts std_logic into a character + function chr(sl: std_logic) return character; + + -- converts std_logic into a string (1 to 1) + function str(sl: std_logic) return string; + + -- converts std_logic_vector into a string (binary base) + function str(slv: std_logic_vector) return string; + + -- converts boolean into a string + function str(b: boolean) return string; + + -- converts an integer into a single character + -- (can also be used for hex conversion and other bases) + function chr(int: integer) return character; + + -- converts integer into string using specified base + function str(int: integer; base: integer) return string; + + -- converts integer to string, using base 10 + function str(int: integer) return string; + + -- convert std_logic_vector into a string in hex format + function hstr(slv: std_logic_vector) return string; + + + -- functions to manipulate strings + ----------------------------------- + + -- convert a character to upper case + function to_upper(c: character) return character; + + -- convert a character to lower case + function to_lower(c: character) return character; + + -- convert a string to upper case + function to_upper(s: string) return string; + + -- convert a string to lower case + function to_lower(s: string) return string; + + -- checks if whitespace (JFF) + function is_whitespace(c: character) return boolean; + + -- remove leading whitespace (JFF) + function strip_whitespace(s: string) return string; + + -- return first nonwhitespace substring (JFF) + function first_string(s: string) return string; + + -- finds the first non-whitespace substring in a string and (JFF) + -- returns both the substring and the original with the substring removed + procedure chomp(variable s: inout string; variable shead: out string); + + + + + -- functions to convert strings into other formats + -------------------------------------------------- + + -- converts a character into std_logic + function to_std_logic(c: character) return std_logic; + + -- converts a hex character into std_logic_vector (JFF) + function chr_to_slv(c: character) return std_logic_vector; + + -- converts a character into int (JFF) + function chr_to_int(c: character) return integer; + + -- converts a binary string into std_logic_vector + function to_std_logic_vector(s: string) return std_logic_vector; + + -- converts a hex string into std_logic_vector (JFF) + function hstr_to_slv(s: string) return std_logic_vector; + + -- converts a decimal string into an integer (JFF) + function str_to_int(s: string) return integer; + + + + -- file I/O + ----------- + + -- read variable length string from input file + procedure str_read(file in_file: TEXT; + res_string: out string); + + -- print string to a file and start new line + procedure print(file out_file: TEXT; + new_string: in string); + + -- print character to a file and start new line + procedure print(file out_file: TEXT; + char: in character); + +end txt_util; + + + + +package body txt_util is + + + + + -- prints text to the screen + + procedure print(text: string) is + variable msg_line: line; + begin + write(msg_line, text); + writeline(output, msg_line); + end print; + + + + + -- prints text to the screen when active + + procedure print(active: boolean; text: string) is + begin + if active then + print(text); + end if; + end print; + + + -- converts std_logic into a character + + function chr(sl: std_logic) return character is + variable c: character; + begin + case sl is + when 'U' => c:= 'U'; + when 'X' => c:= 'X'; + when '0' => c:= '0'; + when '1' => c:= '1'; + when 'Z' => c:= 'Z'; + when 'W' => c:= 'W'; + when 'L' => c:= 'L'; + when 'H' => c:= 'H'; + when '-' => c:= '-'; + end case; + return c; + end chr; + + + + -- converts std_logic into a string (1 to 1) + + function str(sl: std_logic) return string is + variable s: string(1 to 1); + begin + s(1) := chr(sl); + return s; + end str; + + + + -- converts std_logic_vector into a string (binary base) + -- (this also takes care of the fact that the range of + -- a string is natural while a std_logic_vector may + -- have an integer range) + + function str(slv: std_logic_vector) return string is + variable result : string (1 to slv'length); + variable r : integer; + begin + r := 1; + for i in slv'range loop + result(r) := chr(slv(i)); + r := r + 1; + end loop; + return result; + end str; + + + function str(b: boolean) return string is + + begin + if b then + return "true"; + else + return "false"; + end if; + end str; + + + -- converts an integer into a character + -- for 0 to 9 the obvious mapping is used, higher + -- values are mapped to the characters A-Z + -- (this is usefull for systems with base > 10) + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function chr(int: integer) return character is + variable c: character; + begin + case int is + when 0 => c := '0'; + when 1 => c := '1'; + when 2 => c := '2'; + when 3 => c := '3'; + when 4 => c := '4'; + when 5 => c := '5'; + when 6 => c := '6'; + when 7 => c := '7'; + when 8 => c := '8'; + when 9 => c := '9'; + when 10 => c := 'A'; + when 11 => c := 'B'; + when 12 => c := 'C'; + when 13 => c := 'D'; + when 14 => c := 'E'; + when 15 => c := 'F'; + when 16 => c := 'G'; + when 17 => c := 'H'; + when 18 => c := 'I'; + when 19 => c := 'J'; + when 20 => c := 'K'; + when 21 => c := 'L'; + when 22 => c := 'M'; + when 23 => c := 'N'; + when 24 => c := 'O'; + when 25 => c := 'P'; + when 26 => c := 'Q'; + when 27 => c := 'R'; + when 28 => c := 'S'; + when 29 => c := 'T'; + when 30 => c := 'U'; + when 31 => c := 'V'; + when 32 => c := 'W'; + when 33 => c := 'X'; + when 34 => c := 'Y'; + when 35 => c := 'Z'; + when others => c := '?'; + end case; + return c; + end chr; + + + + -- convert integer to string using specified base + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function str(int: integer; base: integer) return string is + + variable temp: string(1 to 10); + variable num: integer; + variable abs_int: integer; + variable len: integer := 1; + variable power: integer := 1; + + begin + + -- bug fix for negative numbers + abs_int := abs(int); + + num := abs_int; + + while num >= base loop -- Determine how many + len := len + 1; -- characters required + num := num / base; -- to represent the + end loop ; -- number. + + for i in len downto 1 loop -- Convert the number to + temp(i) := chr(abs_int/power mod base); -- a string starting + power := power * base; -- with the right hand + end loop ; -- side. + + -- return result and add sign if required + if int < 0 then + return '-'& temp(1 to len); + else + return temp(1 to len); + end if; + + end str; + + + -- convert integer to string, using base 10 + function str(int: integer) return string is + + begin + + return str(int, 10) ; + + end str; + + + + -- converts a std_logic_vector into a hex string. + function hstr(slv: std_logic_vector) return string is + variable hexlen: integer; + variable longslv : std_logic_vector(67 downto 0) := (others => '0'); + variable hex : string(1 to 16); + variable fourbit : std_logic_vector(3 downto 0); + begin + hexlen := (slv'left+1)/4; + if (slv'left+1) mod 4 /= 0 then + hexlen := hexlen + 1; + end if; + longslv(slv'left downto 0) := slv; + for i in (hexlen -1) downto 0 loop + fourbit := longslv(((i*4)+3) downto (i*4)); + case fourbit is + when "0000" => hex(hexlen -I) := '0'; + when "0001" => hex(hexlen -I) := '1'; + when "0010" => hex(hexlen -I) := '2'; + when "0011" => hex(hexlen -I) := '3'; + when "0100" => hex(hexlen -I) := '4'; + when "0101" => hex(hexlen -I) := '5'; + when "0110" => hex(hexlen -I) := '6'; + when "0111" => hex(hexlen -I) := '7'; + when "1000" => hex(hexlen -I) := '8'; + when "1001" => hex(hexlen -I) := '9'; + when "1010" => hex(hexlen -I) := 'A'; + when "1011" => hex(hexlen -I) := 'B'; + when "1100" => hex(hexlen -I) := 'C'; + when "1101" => hex(hexlen -I) := 'D'; + when "1110" => hex(hexlen -I) := 'E'; + when "1111" => hex(hexlen -I) := 'F'; + when "ZZZZ" => hex(hexlen -I) := 'z'; + when "UUUU" => hex(hexlen -I) := 'u'; + when "XXXX" => hex(hexlen -I) := 'x'; + when others => hex(hexlen -I) := '?'; + end case; + end loop; + return hex(1 to hexlen); + end hstr; + + + + -- functions to manipulate strings + ----------------------------------- + + + -- convert a character to upper case + + function to_upper(c: character) return character is + + variable u: character; + + begin + + case c is + when 'a' => u := 'A'; + when 'b' => u := 'B'; + when 'c' => u := 'C'; + when 'd' => u := 'D'; + when 'e' => u := 'E'; + when 'f' => u := 'F'; + when 'g' => u := 'G'; + when 'h' => u := 'H'; + when 'i' => u := 'I'; + when 'j' => u := 'J'; + when 'k' => u := 'K'; + when 'l' => u := 'L'; + when 'm' => u := 'M'; + when 'n' => u := 'N'; + when 'o' => u := 'O'; + when 'p' => u := 'P'; + when 'q' => u := 'Q'; + when 'r' => u := 'R'; + when 's' => u := 'S'; + when 't' => u := 'T'; + when 'u' => u := 'U'; + when 'v' => u := 'V'; + when 'w' => u := 'W'; + when 'x' => u := 'X'; + when 'y' => u := 'Y'; + when 'z' => u := 'Z'; + when others => u := c; + end case; + + return u; + + end to_upper; + + + -- convert a character to lower case + + function to_lower(c: character) return character is + + variable l: character; + + begin + + case c is + when 'A' => l := 'a'; + when 'B' => l := 'b'; + when 'C' => l := 'c'; + when 'D' => l := 'd'; + when 'E' => l := 'e'; + when 'F' => l := 'f'; + when 'G' => l := 'g'; + when 'H' => l := 'h'; + when 'I' => l := 'i'; + when 'J' => l := 'j'; + when 'K' => l := 'k'; + when 'L' => l := 'l'; + when 'M' => l := 'm'; + when 'N' => l := 'n'; + when 'O' => l := 'o'; + when 'P' => l := 'p'; + when 'Q' => l := 'q'; + when 'R' => l := 'r'; + when 'S' => l := 's'; + when 'T' => l := 't'; + when 'U' => l := 'u'; + when 'V' => l := 'v'; + when 'W' => l := 'w'; + when 'X' => l := 'x'; + when 'Y' => l := 'y'; + when 'Z' => l := 'z'; + when others => l := c; + end case; + + return l; + + end to_lower; + + + + -- convert a string to upper case + + function to_upper(s: string) return string is + + variable uppercase: string (s'range); + + begin + + for i in s'range loop + uppercase(i):= to_upper(s(i)); + end loop; + return uppercase; + + end to_upper; + + + + -- convert a string to lower case + + function to_lower(s: string) return string is + + variable lowercase: string (s'range); + + begin + + for i in s'range loop + lowercase(i):= to_lower(s(i)); + end loop; + return lowercase; + + end to_lower; + + + -- checks if whitespace (JFF) + + function is_whitespace(c: character) return boolean is + + begin + + if (c = ' ') or (c = HT) then + return true; + else return false; + end if; + + end is_whitespace; + + + -- remove leading whitespace (JFF) + + function strip_whitespace(s: string) return string is + + variable stemp : string (s'range); + variable j, k : positive := 1; + + begin + + -- fill stemp with blanks + for i in s'range loop + stemp(i) := ' '; + end loop; + + -- find first non-whitespace in s + for i in s'range loop + if is_whitespace(s(i)) then + j := j + 1; + else exit; + end if; + end loop; + -- j points to first non-whitespace + + -- copy remainder of s into stemp + -- starting at 1 + for i in j to s'length loop + stemp(k) := s(i); + k := k + 1; + end loop; + + return stemp; + + end strip_whitespace; + + + + -- return first non-whitespacesubstring (JFF) + + function first_string(s: string) return string is + + variable stemp, s2 : string (s'range); + + begin + + -- fill s2 with blanks + for i in s'range loop + s2(i) := ' '; + end loop; + + -- remove leading whitespace + stemp := strip_whitespace(s); + + -- copy until first whitespace + for i in stemp'range loop + if not is_whitespace(stemp(i)) then + s2(i) := stemp(i); + else exit; + end if; + end loop; + + return s2; + + end first_string; + + + + -- removes first non-whitespace string from a string (JFF) + + procedure chomp(variable s: inout string; variable shead: out string) is + + variable stemp, stemp2 : string (s'range); + variable j, k : positive := 1; + + begin + + -- fill stemp and stemp2 with blanks + for i in s'range loop + stemp(i) := ' '; stemp2(i) := ' '; + end loop; + + stemp := strip_whitespace(s); + + shead := first_string(stemp); + + -- find first whitespace in stemp + for i in stemp'range loop + if not is_whitespace(stemp(i)) then + j := j + 1; + else exit; + end if; + end loop; + -- j points to first whitespace + + -- copy remainder of stemp into stemp2 + -- starting at 1 + for i in j to stemp'length loop + stemp2(k) := stemp(i); + k := k + 1; + end loop; + + s := stemp2; + + end chomp; + + + +-- functions to convert strings into other types + + +-- converts a character into a std_logic + +function to_std_logic(c: character) return std_logic is + variable sl: std_logic; + begin + case c is + when 'U' => + sl := 'U'; + when 'X' => + sl := 'X'; + when '0' => + sl := '0'; + when '1' => + sl := '1'; + when 'Z' => + sl := 'Z'; + when 'W' => + sl := 'W'; + when 'L' => + sl := 'L'; + when 'H' => + sl := 'H'; + when '-' => + sl := '-'; + when others => + sl := 'X'; + end case; + return sl; + end to_std_logic; + + + -- converts a character into std_logic_vector (JFF) + function chr_to_slv(c: character) return std_logic_vector is + variable slv: std_logic_vector(3 downto 0); + begin + case c is + when '0' => + slv := "0000"; + when '1' => + slv := "0001"; + when '2' => + slv := "0010"; + when '3' => + slv := "0011"; + when '4' => + slv := "0100"; + when '5' => + slv := "0101"; + when '6' => + slv := "0110"; + when '7' => + slv := "0111"; + when '8' => + slv := "1000"; + when '9' => + slv := "1001"; + when 'A' | 'a' => + slv := "1010"; + when 'B' | 'b' => + slv := "1011"; + when 'C' | 'c' => + slv := "1100"; + when 'D' | 'd' => + slv := "1101"; + when 'E' | 'e' => + slv := "1110"; + when 'F' | 'f' => + slv := "1111"; + when others => null; + end case; + return slv; + end chr_to_slv; + + + -- converts a character into int (JFF) + function chr_to_int(c: character) return integer is + variable x: integer; + begin + case c is + when '0' => + x := 0; + when '1' => + x := 1; + when '2' => + x := 2; + when '3' => + x := 3; + when '4' => + x := 4; + when '5' => + x := 5; + when '6' => + x := 6; + when '7' => + x := 7; + when '8' => + x := 8; + when '9' => + x := 9; + when others => null; + end case; + return x; + end chr_to_int; + + + +-- converts a binary string into std_logic_vector + +function to_std_logic_vector(s: string) return std_logic_vector is + variable slv: std_logic_vector(s'high-s'low downto 0); + variable k: integer; +begin + k := s'high-s'low; + for i in s'range loop + slv(k) := to_std_logic(s(i)); + k := k - 1; + end loop; + return slv; +end to_std_logic_vector; + + + -- converts a hex string into std_logic_vector (JFF) + function hstr_to_slv(s: string) return std_logic_vector is + variable slv: std_logic_vector(((s'length*4)-1) downto 0) := (others => '0'); + variable k: integer; +begin + for i in s'range loop + slv := slv((slv'length - 5) downto 0) & chr_to_slv(s(i)); + end loop; + return slv; + end hstr_to_slv; + + -- converts a decimal string into an integer (JFF) + function str_to_int(s: string) return integer is + variable k: integer; +begin + k := 0; + for i in s'range loop + k := (k*10) + chr_to_int(s(i)); + end loop; + return k; + end str_to_int; + + + + + + + +---------------- +-- file I/O -- +---------------- + + + +-- read variable length string from input file + +procedure str_read(file in_file: TEXT; + res_string: out string) is + + variable l: line; + variable c: character; + variable is_string: boolean; + + begin + + readline(in_file, l); + -- clear the contents of the result string + for i in res_string'range loop + res_string(i) := ' '; + end loop; + -- read all characters of the line, up to the length + -- of the results string + for i in res_string'range loop + +-- JFF - new +-- + read(l, c, is_string); + if is_string then res_string(i) := c; + else exit; + end if; + +-- JFF - was duplicating the last char if no +-- space at the end of the line +-- +-- read(l, c, is_string); +-- res_string(i) := c; +-- if not is_string then -- found end of line +-- exit; +-- end if; + + + end loop; + +end str_read; + + +-- print string to a file +procedure print(file out_file: TEXT; + new_string: in string) is + + variable l: line; + + begin + + write(l, new_string); + writeline(out_file, l); + +end print; + + +-- print character to a file and start new line +procedure print(file out_file: TEXT; + char: in character) is + + variable l: line; + + begin + + write(l, char); + writeline(out_file, l); + +end print; + + + +-- appends contents of a string to a file until line feed occurs +-- (LF is considered to be the end of the string) + +procedure str_write(file out_file: TEXT; + new_string: in string) is + begin + + for i in new_string'range loop + print(out_file, new_string(i)); + if new_string(i) = LF then -- end of string + exit; + end if; + end loop; + +end str_write; + + + + +end txt_util; + + + + Index: pltbutils/tags/v1.3/examples/vhdl/rtl_example/dut_example.vhd =================================================================== --- pltbutils/tags/v1.3/examples/vhdl/rtl_example/dut_example.vhd (nonexistent) +++ pltbutils/tags/v1.3/examples/vhdl/rtl_example/dut_example.vhd (revision 110) @@ -0,0 +1,100 @@ +---------------------------------------------------------------------- +---- ---- +---- PlTbUtils Example DUT ---- +---- ---- +---- This file is part of the PlTbUtils project ---- +---- http://opencores.org/project,pltbutils ---- +---- ---- +---- Description: ---- +---- PlTbUtils is a collection of functions, procedures and ---- +---- components for easily creating stimuli and checking response ---- +---- in automatic self-checking testbenches. ---- +---- ---- +---- This file is an example component for use as DUT ---- +---- (Device Under Test) in tb_example.vhd, which demonstrates ---- +---- how PlTbUtils can be used. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Per Larsson, pela.opencores@gmail.com ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013-2020 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity dut_example is + generic ( + G_WIDTH : integer := 8; + G_DISABLE_BUGS : integer range 0 to 1 := 1 + ); + port ( + clk_i : in std_logic; + rst_i : in std_logic; + carry_i : in std_logic; + x_i : in std_logic_vector(G_WIDTH-1 downto 0); + y_i : in std_logic_vector(G_WIDTH-1 downto 0); + sum_o : out std_logic_vector(G_WIDTH-1 downto 0); + carry_o : out std_logic + ); +end entity dut_example; + +architecture rtl of dut_example is + signal x : unsigned(G_WIDTH downto 0); + signal y : unsigned(G_WIDTH downto 0); + signal c : unsigned(G_WIDTH downto 0); + signal sum : unsigned(G_WIDTH downto 0); +begin + + x <= resize(unsigned(x_i), G_WIDTH+1); + y <= resize(unsigned(y_i), G_WIDTH+1); + c <= resize(unsigned(std_logic_vector'('0' & carry_i)), G_WIDTH+1); + + p_sum : process(clk_i) + begin + if rising_edge(clk_i) then + if rst_i = '1' then + sum <= (others => '0'); + else + if G_DISABLE_BUGS = 1 then + sum <= x + y + c; + else + sum <= x + y; + end if; + end if; + end if; + end process; + + sum_o <= std_logic_vector(sum(sum'high-1 downto 0)); + carry_o <= sum(sum'high); + +end architecture rtl; + Index: pltbutils/tags/v1.3/examples/vhdl/rtl_example/dut_example_files.lst =================================================================== --- pltbutils/tags/v1.3/examples/vhdl/rtl_example/dut_example_files.lst (nonexistent) +++ pltbutils/tags/v1.3/examples/vhdl/rtl_example/dut_example_files.lst (revision 110) @@ -0,0 +1 @@ +dut_example.vhd Index: pltbutils/tags/v1.3/examples/vhdl/tb_example1/tb_example1.vhd =================================================================== --- pltbutils/tags/v1.3/examples/vhdl/tb_example1/tb_example1.vhd (nonexistent) +++ pltbutils/tags/v1.3/examples/vhdl/tb_example1/tb_example1.vhd (revision 110) @@ -0,0 +1,157 @@ +---------------------------------------------------------------------- +---- ---- +---- PlTbUtils Testbench Example 1 ---- +---- ---- +---- This file is part of the PlTbUtils project ---- +---- http://opencores.org/project,pltbutils ---- +---- ---- +---- Description: ---- +---- PlTbUtils is a collection of functions, procedures and ---- +---- components for easily creating stimuli and checking response ---- +---- in automatic self-checking testbenches. ---- +---- ---- +---- This file is an example which demonstrates how PlTbUtils ---- +---- can be used. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Per Larsson, pela.opencores@gmail.com ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013-2020 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.txt_util.all; +use work.pltbutils_func_pkg.all; +use work.pltbutils_comp_pkg.all; + +entity tb_example1 is + generic ( + G_WIDTH : integer := 8; + G_CLK_PERIOD : time := 10 ns; + G_DISABLE_BUGS : integer range 0 to 1 := 0 + ); +end entity tb_example1; + +architecture bhv of tb_example1 is + + -- Simulation status- and control signals + -- for accessing .stop_sim and for viewing in waveform window + signal pltbs : pltbs_t := C_PLTBS_INIT; + + -- DUT stimuli and response signals + signal clk : std_logic; + signal rst : std_logic; + signal carry_in : std_logic; + signal x : std_logic_vector(G_WIDTH-1 downto 0); + signal y : std_logic_vector(G_WIDTH-1 downto 0); + signal sum : std_logic_vector(G_WIDTH-1 downto 0); + signal carry_out : std_logic; + +begin + + dut0 : entity work.dut_example + generic map ( + G_WIDTH => G_WIDTH, + G_DISABLE_BUGS => G_DISABLE_BUGS + ) + port map ( + clk_i => clk, + rst_i => rst, + carry_i => carry_in, + x_i => x, + y_i => y, + sum_o => sum, + carry_o => carry_out + ); + + clkgen0 : pltbutils_clkgen + generic map( + G_PERIOD => G_CLK_PERIOD + ) + port map( + clk_o => clk, + stop_sim_i => pltbs.stop_sim + ); + + -- Testcase process + -- NOTE: The purpose of the following code is to demonstrate some of the + -- features of PlTbUtils, not to do a thorough verification. + p_tc1 : process + variable pltbv : pltbv_t := C_PLTBV_INIT; + begin + startsim("tc1", "", pltbv, pltbs); + rst <= '1'; + carry_in <= '0'; + x <= (others => '0'); + y <= (others => '0'); + + starttest(1, "Reset test", pltbv, pltbs); + waitclks(2, clk, pltbv, pltbs); + check("Sum during reset", sum, 0, pltbv, pltbs); + check("Carry out during reset", carry_out, '0', pltbv, pltbs); + rst <= '0'; + endtest(pltbv, pltbs); + + starttest(2, "Simple sum test", pltbv, pltbs); + carry_in <= '0'; + x <= std_logic_vector(to_unsigned(1, x'length)); + y <= std_logic_vector(to_unsigned(2, x'length)); + waitclks(2, clk, pltbv, pltbs); + check("Sum", sum, 3, pltbv, pltbs); + check("Carry out", carry_out, '0', pltbv, pltbs); + endtest(pltbv, pltbs); + + starttest(3, "Simple carry in test", pltbv, pltbs); + print(G_DISABLE_BUGS=0, pltbv, pltbs, "Bug here somewhere"); + carry_in <= '1'; + x <= std_logic_vector(to_unsigned(1, x'length)); + y <= std_logic_vector(to_unsigned(2, x'length)); + waitclks(2, clk, pltbv, pltbs); + check("Sum", sum, 4, pltbv, pltbs); + check("Carry out", carry_out, '0', pltbv, pltbs); + print(G_DISABLE_BUGS=0, pltbv, pltbs, ""); + endtest(pltbv, pltbs); + + starttest(4, "Simple carry out test", pltbv, pltbs); + carry_in <= '0'; + x <= std_logic_vector(to_unsigned(2**G_WIDTH-1, x'length)); + y <= std_logic_vector(to_unsigned(1, x'length)); + waitclks(2, clk, pltbv, pltbs); + check("Sum", sum, 0, pltbv, pltbs); + check("Carry out", carry_out, '1', pltbv, pltbs); + endtest(pltbv, pltbs); + + endsim(pltbv, pltbs, true); + wait; + end process p_tc1; + +end architecture bhv; Index: pltbutils/tags/v1.3/examples/vhdl/tb_example1/tb_example1_files.lst =================================================================== --- pltbutils/tags/v1.3/examples/vhdl/tb_example1/tb_example1_files.lst (nonexistent) +++ pltbutils/tags/v1.3/examples/vhdl/tb_example1/tb_example1_files.lst (revision 110) @@ -0,0 +1 @@ +tb_example1.vhd Index: pltbutils/tags/v1.3/examples/vhdl/tb_example2/tb_example2.vhd =================================================================== --- pltbutils/tags/v1.3/examples/vhdl/tb_example2/tb_example2.vhd (nonexistent) +++ pltbutils/tags/v1.3/examples/vhdl/tb_example2/tb_example2.vhd (revision 110) @@ -0,0 +1,119 @@ +---------------------------------------------------------------------- +---- ---- +---- PlTbUtils Testbench Example 2 ---- +---- ---- +---- This file is part of the PlTbUtils project ---- +---- http://opencores.org/project,pltbutils ---- +---- ---- +---- Description: ---- +---- PlTbUtils is a collection of functions, procedures and ---- +---- components for easily creating stimuli and checking response ---- +---- in automatic self-checking testbenches. ---- +---- ---- +---- This file is an example which demonstrates how PlTbUtils ---- +---- can be used. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Per Larsson, pela.opencores@gmail.com ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013-2020 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use work.pltbutils_func_pkg.all; +use work.pltbutils_comp_pkg.all; + +entity tb_example2 is + generic ( + G_WIDTH : integer := 8; + G_CLK_PERIOD : time := 10 ns; + G_DISABLE_BUGS : integer range 0 to 1 := 0 + ); +end entity tb_example2; + +architecture bhv of tb_example2 is + + -- Simulation status- and control signals + -- for accessing .stop_sim and for viewing in waveform window + signal pltbs : pltbs_t := C_PLTBS_INIT; + + -- DUT stimuli and response signals + signal clk : std_logic; + signal rst : std_logic; + signal carry_in : std_logic; + signal x : std_logic_vector(G_WIDTH-1 downto 0); + signal y : std_logic_vector(G_WIDTH-1 downto 0); + signal sum : std_logic_vector(G_WIDTH-1 downto 0); + signal carry_out : std_logic; + +begin + + dut0 : entity work.dut_example + generic map ( + G_WIDTH => G_WIDTH, + G_DISABLE_BUGS => G_DISABLE_BUGS + ) + port map ( + clk_i => clk, + rst_i => rst, + carry_i => carry_in, + x_i => x, + y_i => y, + sum_o => sum, + carry_o => carry_out + ); + + clkgen0 : pltbutils_clkgen + generic map( + G_PERIOD => G_CLK_PERIOD + ) + port map( + clk_o => clk, + stop_sim_i => pltbs.stop_sim + ); + + tc0 : entity work.tc_example2 + generic map ( + G_WIDTH => G_WIDTH, + G_DISABLE_BUGS => G_DISABLE_BUGS + ) + port map( + pltbs => pltbs, + clk => clk, + rst => rst, + carry_in => carry_in, + x => x, + y => y, + sum => sum, + carry_out => carry_out + ); + +end architecture bhv; Index: pltbutils/tags/v1.3/examples/vhdl/tb_example2/tc1.vhd =================================================================== --- pltbutils/tags/v1.3/examples/vhdl/tb_example2/tc1.vhd (nonexistent) +++ pltbutils/tags/v1.3/examples/vhdl/tb_example2/tc1.vhd (revision 110) @@ -0,0 +1,107 @@ +---------------------------------------------------------------------- +---- ---- +---- PlTbUtils Example Testcase Architecture for ---- +---- Example Testbench ---- +---- ---- +---- This file is part of the PlTbUtils project ---- +---- http://opencores.org/project,pltbutils ---- +---- ---- +---- Description: ---- +---- PlTbUtils is a collection of functions, procedures and ---- +---- components for easily creating stimuli and checking response ---- +---- in automatic self-checking testbenches. ---- +---- ---- +---- This file is an example which demonstrates how PlTbUtils ---- +---- can be used. ---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Per Larsson, pela.opencores@gmail.com ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013-2020 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.txt_util.all; +use work.pltbutils_func_pkg.all; + +-- NOTE: The purpose of the following code is to demonstrate some of the +-- features of PlTbUtils, not to do a thorough verification. +architecture tc1 of tc_example2 is +begin + p_tc1 : process + variable pltbv : pltbv_t := C_PLTBV_INIT; + begin + startsim("tc1", "", pltbv, pltbs); + rst <= '1'; + carry_in <= '0'; + x <= (others => '0'); + y <= (others => '0'); + + starttest(1, "Reset test", pltbv, pltbs); + waitclks(2, clk, pltbv, pltbs); + check("Sum during reset", sum, 0, pltbv, pltbs); + check("Carry out during reset", carry_out, '0', pltbv, pltbs); + rst <= '0'; + endtest(pltbv, pltbs); + + starttest(2, "Simple sum test", pltbv, pltbs); + carry_in <= '0'; + x <= std_logic_vector(to_unsigned(1, x'length)); + y <= std_logic_vector(to_unsigned(2, x'length)); + waitclks(2, clk, pltbv, pltbs); + check("Sum", sum, 3, pltbv, pltbs); + check("Carry out", carry_out, '0', pltbv, pltbs); + endtest(pltbv, pltbs); + + starttest(3, "Simple carry in test", pltbv, pltbs); + print(G_DISABLE_BUGS=0, pltbv, pltbs, "Bug here somewhere"); + carry_in <= '1'; + x <= std_logic_vector(to_unsigned(1, x'length)); + y <= std_logic_vector(to_unsigned(2, x'length)); + waitclks(2, clk, pltbv, pltbs); + check("Sum", sum, 4, pltbv, pltbs); + check("Carry out", carry_out, '0', pltbv, pltbs); + print(G_DISABLE_BUGS=0, pltbv, pltbs, ""); + endtest(pltbv, pltbs); + + starttest(4, "Simple carry out test", pltbv, pltbs); + carry_in <= '0'; + x <= std_logic_vector(to_unsigned(2**G_WIDTH-1, x'length)); + y <= std_logic_vector(to_unsigned(1, x'length)); + waitclks(2, clk, pltbv, pltbs); + check("Sum", sum, 0, pltbv, pltbs); + check("Carry out", carry_out, '1', pltbv, pltbs); + endtest(pltbv, pltbs); + + endsim(pltbv, pltbs, true); + wait; + end process p_tc1; +end architecture tc1; Index: pltbutils/tags/v1.3/examples/vhdl/tb_example2/tc_example2.vhd =================================================================== --- pltbutils/tags/v1.3/examples/vhdl/tb_example2/tc_example2.vhd (nonexistent) +++ pltbutils/tags/v1.3/examples/vhdl/tb_example2/tc_example2.vhd (revision 110) @@ -0,0 +1,68 @@ +---------------------------------------------------------------------- +---- ---- +---- PlTbUtils Example Testcase Entity for Example Testbench ---- +---- ---- +---- This file is part of the PlTbUtils project ---- +---- http://opencores.org/project,pltbutils ---- +---- ---- +---- Description: ---- +---- PlTbUtils is a collection of functions, procedures and ---- +---- components for easily creating stimuli and checking response ---- +---- in automatic self-checking testbenches. ---- +---- ---- +---- This file is an example which demonstrates how PlTbUtils ---- +---- can be used. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Per Larsson, pela.opencores@gmail.com ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013-2020 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use work.pltbutils_func_pkg.all; + +entity tc_example2 is + generic ( + G_WIDTH : integer := 8; + G_DISABLE_BUGS : integer range 0 to 1 := 0 + ); + port ( + pltbs : out pltbs_t; + clk : in std_logic; + rst : out std_logic; + carry_in : out std_logic; + x : out std_logic_vector(G_WIDTH-1 downto 0); + y : out std_logic_vector(G_WIDTH-1 downto 0); + sum : in std_logic_vector(G_WIDTH-1 downto 0); + carry_out : in std_logic + ); +end entity tc_example2; Index: pltbutils/tags/v1.3/examples/vhdl/tb_example2/tb_example2_files.lst =================================================================== --- pltbutils/tags/v1.3/examples/vhdl/tb_example2/tb_example2_files.lst (nonexistent) +++ pltbutils/tags/v1.3/examples/vhdl/tb_example2/tb_example2_files.lst (revision 110) @@ -0,0 +1,3 @@ +tc_example2.vhd +tc1.vhd +tb_example2.vhd Index: pltbutils/tags/v1.3/scripts/gen_testfiles.bat =================================================================== --- pltbutils/tags/v1.3/scripts/gen_testfiles.bat (nonexistent) +++ pltbutils/tags/v1.3/scripts/gen_testfiles.bat (revision 110) @@ -0,0 +1,53 @@ +:;#--------------------------------------------------------------------- +:;#--- ---- +:;#--- PlTbUtils Script for generating test files ---- +:;#--- For Windows and Linux. Line endings must be LF (Unix). ---- +:;#--- ---- +:;#--- This file is part of the PlTbUtils project ---- +:;#--- http://opencores.org/project,pltbutils ---- +:;#--- ---- +:;#--- Description: ---- +:;#--- PlTbUtils is a collection of functions, procedures and ---- +:;#--- components for easily creating stimuli and checking response ---- +:;#--- in automatic self-checking testbenches. ---- +:;#--- ---- +:;#--- This file generates test files for verifying the file check ---- +:;#--- procedures check_binfile, check_txtfile, check_datfile, etc. ---- +:;#--- In tb_pltbutils.vhd, there are tests that let these ---- +:;#--- procedures compare test files (the ones generated by this ---- +:;#--- script). ---- +:;#--- ---- +:;#--- To Do: ---- +:;#--- - ---- +:;#--- ---- +:;#--- Author(s): ---- +:;#--- - Per Larsson, pela.opencores@gmail.com ---- +:;#--- ---- +:;#--------------------------------------------------------------------- +:;#--- ---- +:;#--- Copyright (C) 2020 Authors and OPENCORES.ORG ---- +:;#--- ---- +:;#--- This source file may be used and distributed without ---- +:;#--- restriction provided that this copyright statement is not ---- +:;#--- removed from the file and that any derivative work contains ---- +:;#--- the original copyright notice and the associated disclaimer. ---- +:;#--- ---- +:;#--- This source file is free software; you can redistribute it ---- +:;#--- and/or modify it under the terms of the GNU Lesser General ---- +:;#--- Public License as published by the Free Software Foundation; ---- +:;#--- either version 2.1 of the License, or (at your option) any ---- +:;#--- later version. ---- +:;#--- ---- +:;#--- This source is distributed in the hope that it will be ---- +:;#--- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +:;#--- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +:;#--- PURPOSE. See the GNU Lesser General Public License for more ---- +:;#--- details. ---- +:;#--- ---- +:;#--- You should have received a copy of the GNU Lesser General ---- +:;#--- Public License along with this source; if not, download it ---- +:;#--- from http://www.opencores.org/lgpl.shtml ---- +:;#--- ---- +:;#--------------------------------------------------------------------- + +tclsh gen_testfiles.tcl Index: pltbutils/tags/v1.3/scripts/gen_testfiles.tcl =================================================================== --- pltbutils/tags/v1.3/scripts/gen_testfiles.tcl (nonexistent) +++ pltbutils/tags/v1.3/scripts/gen_testfiles.tcl (revision 110) @@ -0,0 +1,90 @@ +#--------------------------------------------------------------------- +#--- ---- +#--- PlTbUtils Script for generating test files ---- +#--- ---- +#--- This file is part of the PlTbUtils project ---- +#--- http://opencores.org/project,pltbutils ---- +#--- ---- +#--- Description: ---- +#--- PlTbUtils is a collection of functions, procedures and ---- +#--- components for easily creating stimuli and checking response ---- +#--- in automatic self-checking testbenches. ---- +#--- ---- +#--- This file generates test files for verifying the file check ---- +#--- procedures check_binfile, check_txtfile, check_datfile, etc. ---- +#--- In tb_pltbutils.vhd, there are tests that let these ---- +#--- procedures compare test files (the ones generated by this ---- +#--- script). ---- +#--- ---- +#--- To Do: ---- +#--- - ---- +#--- ---- +#--- Author(s): ---- +#--- - Per Larsson, pela.opencores@gmail.com ---- +#--- ---- +#--------------------------------------------------------------------- +#--- ---- +#--- Copyright (C) 2020 Authors and OPENCORES.ORG ---- +#--- ---- +#--- This source file may be used and distributed without ---- +#--- restriction provided that this copyright statement is not ---- +#--- removed from the file and that any derivative work contains ---- +#--- the original copyright notice and the associated disclaimer. ---- +#--- ---- +#--- This source file is free software; you can redistribute it ---- +#--- and/or modify it under the terms of the GNU Lesser General ---- +#--- Public License as published by the Free Software Foundation; ---- +#--- either version 2.1 of the License, or (at your option) any ---- +#--- later version. ---- +#--- ---- +#--- This source is distributed in the hope that it will be ---- +#--- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +#--- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +#--- PURPOSE. See the GNU Lesser General Public License for more ---- +#--- details. ---- +#--- ---- +#--- You should have received a copy of the GNU Lesser General ---- +#--- Public License along with this source; if not, download it ---- +#--- from http://www.opencores.org/lgpl.shtml ---- +#--- ---- +#--------------------------------------------------------------------- + +# File names of test files +set BINTESTFILE_REFERENCE "../bench/testfiles/bintestfile_reference.bin" +set BINTESTFILE_CORRECT "../bench/testfiles/bintestfile_correct.bin" +set BINTESTFILE_ERROR "../bench/testfiles/bintestfile_error.bin" +set BINTESTFILE_SHORTER "../bench/testfiles/bintestfile_shorter.bin" +set BINTESTFILE_LONGER "../bench/testfiles/bintestfile_longer.bin" + +set BINTESTFILE_HEADER "Bintestfile R " +set BINTESTFILE_HEADER_ERR "Bintestfile E " + +# Generate test files +set fp_bin_ref [open $BINTESTFILE_REFERENCE wb] +set fp_bin_corr [open $BINTESTFILE_CORRECT wb] +set fp_bin_err [open $BINTESTFILE_ERROR wb] +set fp_bin_long [open $BINTESTFILE_LONGER wb] +set fp_bin_short [open $BINTESTFILE_SHORTER wb] +puts -nonewline $fp_bin_ref $BINTESTFILE_HEADER +puts -nonewline $fp_bin_corr $BINTESTFILE_HEADER +puts -nonewline $fp_bin_err $BINTESTFILE_HEADER_ERR +puts -nonewline $fp_bin_long $BINTESTFILE_HEADER +puts -nonewline $fp_bin_short $BINTESTFILE_HEADER +for {set i 0} {$i < 2} {incr i} { + for {set j 0} {$j < 256} {incr j} { + puts -nonewline $fp_bin_ref [binary format c $j] + puts -nonewline $fp_bin_corr [binary format c $j] + puts -nonewline $fp_bin_err [binary format c $j] + puts -nonewline $fp_bin_long [binary format c $j] + if {!($i == 1 && $j == 255)} { ;# Skip last byte in the shorter file + puts -nonewline $fp_bin_short [binary format c $j] + } + } +} +puts -nonewline $fp_bin_long L ;# Add extra byte in the longer file +close $fp_bin_ref +close $fp_bin_corr +close $fp_bin_err +close $fp_bin_long +close $fp_bin_short + Index: pltbutils/tags/v1.3/templates/vhdl/template1/tb_template1.vhd =================================================================== --- pltbutils/tags/v1.3/templates/vhdl/template1/tb_template1.vhd (nonexistent) +++ pltbutils/tags/v1.3/templates/vhdl/template1/tb_template1.vhd (revision 110) @@ -0,0 +1,113 @@ +---------------------------------------------------------------------- +---- ---- +---- PlTbUtils Testbench Template 1 ---- +---- ---- +---- This file is part of the PlTbUtils project ---- +---- http://opencores.org/project,pltbutils ---- +---- ---- +---- Description: ---- +---- PlTbUtils is a collection of functions, procedures and ---- +---- components for easily creating stimuli and checking response ---- +---- in automatic self-checking testbenches. ---- +---- ---- +---- This file is a template, which can be used as a base when ---- +---- testbenches which use PlTbUtils. ---- +---- Copy this file to your preferred location and rename the ---- +---- copied file and its contents, by replacing the word ---- +---- "template" with a name for your design. ---- +---- Also remove informative comments enclosed in < ... > . ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Per Larsson, pela.opencores@gmail.com ---- +---- ---- +---------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; +use work.txt_util.all; +use work.pltbutils_func_pkg.all; +use work.pltbutils_comp_pkg.all; +-- < Template info: add more libraries here, if needed > + +entity tb_template1 is + generic ( + G_CLK_PERIOD : time := 10 ns; -- < Template info: change value if needed > + G_SKIPTESTS : std_logic_vector := ( + '0', -- Dummy + '0', -- Test 1 + '0' -- Test 2 + -- ... etc + ) + -- < Template info: add more generics here if needed > + ); +end entity tb_template1; + +architecture bhv of tb_template1 is + + -- Simulation status- and control signals + -- for accessing .stop_sim and for viewing in waveform window + signal pltbs : pltbs_t := C_PLTBS_INIT; + + -- DUT stimuli and response signals + signal clk : std_logic; + signal rst : std_logic; + -- < Template info: add more DUT stimuli and response signals here. > + +begin + + dut0 : entity work.template + generic map ( + -- < Template info: add DUT generics here, if any. > + ) + port map ( + clk_i => clk, -- Template example + rst_i => rst, -- Template example + -- < Template info: add more DUT ports here. > + ); + + clkgen0 : pltbutils_clkgen + generic map( + G_PERIOD => G_CLK_PERIOD + ) + port map( + clk_o => clk, + stop_sim_i => pltbs.stop_sim + ); + + -- Testcase process + p_tc1 : process + variable pltbv : pltbv_t := C_PLTBV_INIT; + begin + startsim("tc1", G_SKIPTESTS, pltbv, pltbs); + rst <= '1'; -- Template example + -- < Template info: initialize other DUT stimuli here. > + + starttest(1, "Reset test", pltbv, pltbs); -- Template example + if is_test_active(pltbv) then + waitclks(2, clk, pltbv, pltbs); -- Template example + check("template_signal during reset", template_signal, 0, pltbv, pltbs); -- Template example + -- < Template info: check other DUT outputs here. + rst <= '0'; -- Template example + end if; -- is_test_active + endtest(pltbv, pltbs); + + starttest(2, "Template test", pltbv, pltbs); + if is_test_active(pltbv) then + -- < Template info: set all relevant DUT inputs here. > + waitclks(2, clk, pltbv, pltbs); -- Template example + -- < Template info: check all relevant DUT outputs here. > + end if; -- is_test_active + endtest(pltbv, pltbs); + + -- < Template info: add more tests here. > + + endsim(pltbv, pltbs, true); + wait; + end process p_tc1; + +end architecture bhv; Index: pltbutils/tags/v1.3/templates/vhdl/template1/tb_template1_files.lst =================================================================== --- pltbutils/tags/v1.3/templates/vhdl/template1/tb_template1_files.lst (nonexistent) +++ pltbutils/tags/v1.3/templates/vhdl/template1/tb_template1_files.lst (revision 110) @@ -0,0 +1 @@ +tb_template1.vhd Index: pltbutils/tags/v1.3/templates/vhdl/template2/tb_template2.vhd =================================================================== --- pltbutils/tags/v1.3/templates/vhdl/template2/tb_template2.vhd (nonexistent) +++ pltbutils/tags/v1.3/templates/vhdl/template2/tb_template2.vhd (revision 110) @@ -0,0 +1,93 @@ +---------------------------------------------------------------------- +---- ---- +---- PlTbUtils Testbench Template 2 ---- +---- ---- +---- This file is part of the PlTbUtils project ---- +---- http://opencores.org/project,pltbutils ---- +---- ---- +---- Description: ---- +---- PlTbUtils is a collection of functions, procedures and ---- +---- components for easily creating stimuli and checking response ---- +---- in automatic self-checking testbenches. ---- +---- ---- +---- This file is a template, which can be used as a base when ---- +---- testbenches which use PlTbUtils. ---- +---- Copy this file to your preferred location and rename the ---- +---- copied file and its contents, by replacing the word ---- +---- "template" with a name for your design. ---- +---- Also remove informative comments enclosed in < ... > . ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Per Larsson, pela.opencores@gmail.com ---- +---- ---- +---------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; +use work.txt_util.all; +use work.pltbutils_func_pkg.all; +use work.pltbutils_comp_pkg.all; +-- < Template info: add more libraries here, if needed > + +entity tb_template2 is + generic ( + G_CLK_PERIOD : time := 10 ns; -- < Template info: change value if needed > + G_SKIPTESTS : std_logic_vector := ( + '0', -- Dummy + '0', -- Test 1 + '0' -- Test 2 + -- ... etc + ); + -- < Template info: add more generics here if needed > + ); +end entity tb_template2; + +architecture bhv of tb_template2 is + + -- Simulation status- and control signals + -- for accessing .stop_sim and for viewing in waveform window + signal pltbs : pltbs_t := C_PLTBS_INIT; + + -- DUT stimuli and response signals + signal clk : std_logic; + signal rst : std_logic; + -- < Template info: add more DUT stimuli and response signals here. > + +begin + + dut0 : entity work.template + generic map ( + -- < Template info: add DUT generics here, if any. > + ) + port map ( + clk_i => clk, -- Template example + rst_i => rst, -- Template example + -- < Template info: add more DUT ports here. > + ); + + clkgen0 : pltbutils_clkgen + generic map( + G_PERIOD => G_CLK_PERIOD + ) + port map( + clk_o => clk, + stop_sim_i => pltbs.stop_sim + ); + + tc0 : entity work.tc_template2 + generic map ( + G_SKIPTESTS => G_SKIPTESTS + -- < Template info: add more generics for testcase component here, if needed. > + ) + port map( + clk => clk, -- Template example + rst => rst, -- Template example + -- < Template info: add more ports for testcase component here. > + ); + +end architecture bhv; Index: pltbutils/tags/v1.3/templates/vhdl/template2/tc_template2.vhd =================================================================== --- pltbutils/tags/v1.3/templates/vhdl/template2/tc_template2.vhd (nonexistent) +++ pltbutils/tags/v1.3/templates/vhdl/template2/tc_template2.vhd (revision 110) @@ -0,0 +1,53 @@ +---------------------------------------------------------------------- +---- ---- +---- PlTbUtils Testcase Entity for Template Testbench ---- +---- ---- +---- This file is part of the PlTbUtils project ---- +---- http://opencores.org/project,pltbutils ---- +---- ---- +---- Description: ---- +---- PlTbUtils is a collection of functions, procedures and ---- +---- components for easily creating stimuli and checking response ---- +---- in automatic self-checking testbenches. ---- +---- ---- +---- This file is a template, which can be used as a base when ---- +---- testbenches which use PlTbUtils. ---- +---- Copy this file to your preferred location and rename the ---- +---- copied file and its contents, by replacing the word ---- +---- "templateXX" with a name for your design. ---- +---- Also remove informative comments enclosed in < ... > . ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Per Larsson, pela.opencores@gmail.com ---- +---- ---- +---------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use work.pltbutils_func_pkg.all; + +entity tc_template2 is + generic ( + G_SKIPTESTS : std_logic_vector := ( + '0', -- Dummy + '0', -- Test 1 + '0' -- Test 2 + -- ... etc + ) + -- < Template info: add more generics here if needed > + ); + port ( + pltbs : out pltbs_t; + clk : in std_logic; -- Template example + rst : out std_logic -- Template example + -- < Template info: add more ports for testcase component here. > + -- < Inputs on the DUT should be outputs here, > + -- < and vice versa. > + -- < Exception: clocks are inputs both on DUT > + -- < and here. > + ); +end entity tc_template2; Index: pltbutils/tags/v1.3/templates/vhdl/template2/tc1.vhd =================================================================== --- pltbutils/tags/v1.3/templates/vhdl/template2/tc1.vhd (nonexistent) +++ pltbutils/tags/v1.3/templates/vhdl/template2/tc1.vhd (revision 110) @@ -0,0 +1,67 @@ +---------------------------------------------------------------------- +---- ---- +---- PlTbUtils Testcase Architecture for ---- +---- Template Testbench ---- +---- ---- +---- This file is part of the PlTbUtils project ---- +---- http://opencores.org/project,pltbutils ---- +---- ---- +---- Description: ---- +---- PlTbUtils is a collection of functions, procedures and ---- +---- components for easily creating stimuli and checking response ---- +---- in automatic self-checking testbenches. ---- +---- ---- +---- This file is a template, which can be used as a base when ---- +---- testbenches which use PlTbUtils. ---- +---- Copy this file to your preferred location and rename the ---- +---- copied file and its contents, by replacing the word ---- +---- "templateXX" with a name for your design. ---- +---- Also remove informative comments enclosed in < ... > . ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Per Larsson, pela.opencores@gmail.com ---- +---- ---- +---------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +--use work.txt_util.all; +use work.pltbutils_func_pkg.all; + +architecture tc1 of tc_template2 is +begin + p_tc1 : process + variable pltbv : pltbv_t := C_PLTBV_INIT; + begin + startsim("tc1", G_SKIPTESTS, pltbv, pltbs); + rst <= '1'; -- Template example + -- < Template info: initialize other DUT stimuli here. > + + starttest(1, "Reset test", pltbv, pltbs); -- Template example + if is_test_active(pltbv) then + waitclks(2, clk, pltbv, pltbs); -- Template example + check("template_signal during reset", template_signal, 0, pltbv, pltbs); -- Template example + -- < Template info: check other DUT outputs here. + rst <= '0'; -- Template example + end if; -- is_test_active() + endtest(pltbv, pltbs); + + starttest(2, "Template test", pltbv, pltbs); + if is_test_active(pltbv) then + -- < Template info: set all relevant DUT inputs here. > + waitclks(2, clk, pltbv, pltbs); -- Template example + -- < Template info: check all relevant DUT outputs here. > + end if; -- is_test_active() + endtest(pltbv, pltbs); + + -- < Template info: add more tests here. > + + endsim(pltbv, pltbs, true); + wait; + end process p_tc1; +end architecture tc1; \ No newline at end of file Index: pltbutils/tags/v1.3/templates/vhdl/template2/tb_template2_files.lst =================================================================== --- pltbutils/tags/v1.3/templates/vhdl/template2/tb_template2_files.lst (nonexistent) +++ pltbutils/tags/v1.3/templates/vhdl/template2/tb_template2_files.lst (revision 110) @@ -0,0 +1,3 @@ +tc_template2.vhd +tc1.vhd +tb_template2.vhd Index: pltbutils/tags/v1.3 =================================================================== --- pltbutils/tags/v1.3 (nonexistent) +++ pltbutils/tags/v1.3 (revision 110)
pltbutils/tags/v1.3 Property changes : Added: svn:mergeinfo ## -0,0 +0,2 ## Merged /pltbutils/branches/dev_beta0002:r95-96 Merged /pltbutils/branches/dev0007:r55-83

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