URL
https://opencores.org/ocsvn/ps2_host_controller/ps2_host_controller/trunk
Subversion Repositories ps2_host_controller
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- This comparison shows the changes necessary to convert path
/
- from Rev 3 to Rev 4
- ↔ Reverse comparison
Rev 3 → Rev 4
/ps2_host_controller/trunk/hdl/ps2_host_defines.v
35,7 → 35,10
//// //// |
////////////////////////////////////////////////////////////////////// |
|
`ifndef SYS_CLOCK_HZ |
`define SYS_CLOCK_HZ 100_000_000 |
`endif |
|
`define T_100_MICROSECONDS (`SYS_CLOCK_HZ / 10_000) |
`define T_200_MICROSECONDS (`SYS_CLOCK_HZ / 5_000) |
// Ideally below define should be $clog2(`T_100_MICROSECONDS + 1) |
/ps2_host_controller/trunk/hdl/ps2_host_testbench.v
92,6 → 92,7
ps2_clk_r = #`PS2_PERIOD 0; |
ps2_clk_r = #`PS2_PERIOD 1; |
end |
wait (ready); |
if ((bits != rx_data) | (error != expect_error)) begin |
$display("Failed: Frame:0x%x Rx:0x%x Err:%b", frame, rx_data, error); |
end |
106,7 → 107,6
begin |
frame = 0; |
tx_data = bits; |
wait (~busy) |
send_req = #(`SYS_PERIOD*2) 1; |
send_req = #(`SYS_PERIOD*2) 0; |
wait (~ps2_data); |
115,6 → 115,7
frame = {frame[9:0], ps2_data}; |
ps2_clk_r = #`PS2_PERIOD 1; |
end |
wait (~busy); |
if (({bits[0],bits[1],bits[2],bits[3],bits[4],bits[5],bits[6],bits[7]} != frame[9:2]) | |
frame[10] | (~^frame[9:2] != frame[1]) | ~frame[0]) begin |
$display("Failed: Frame:0x%x Tx:0x%x", frame, bits); |
124,7 → 125,7
// Test runner |
integer byte; |
always @(negedge sys_rst) begin |
for (byte = 1; byte < 256; byte = byte + 1) begin |
for (byte = 0; byte < 256; byte = byte + 1) begin |
// Transmitter test |
transmitter_test(byte); |
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/ps2_host_controller/trunk/hdl/ps2_host_rx.v
44,12 → 44,12
input wire sys_rst, |
input wire ps2_clk_negedge, |
input wire ps2_data, |
output wire [7:0] rx_data, |
output wire ready, |
output wire error |
output reg [7:0] rx_data, |
output reg ready, |
output reg error |
); |
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// Read in 11 bit long frame. 12th bit marks end of frame. |
// Read in 11 bit long frame. |
reg [11:0] frame; |
always @(posedge sys_clk) |
begin |
61,14 → 61,33
end |
end |
|
// 12th bit marks end of frame. |
always @(posedge sys_clk) |
begin |
ready <= (sys_rst) ? 0 : frame[11]; |
end |
|
// Return rx_data in most significant bit first order. |
assign rx_data = {frame[2], frame[3], frame[4], frame[5], |
frame[6], frame[7], frame[8], frame[9]}; |
always @(posedge sys_clk) |
begin |
if (sys_rst) begin |
rx_data <= 0; |
end |
else begin |
rx_data <= (frame[11]) ? {frame[2], frame[3], frame[4], frame[5], |
frame[6], frame[7], frame[8], frame[9]} : rx_data; |
end |
end |
|
// 12th bit marks end of frame. |
assign ready = frame[11]; |
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// Check that 1st bit is 0, odd parity bit is correct and last bit is 1. |
assign error = ~(~frame[10] & (~frame[1] == ^frame[9:2]) & frame[0]); |
always @(posedge sys_clk) |
begin |
if (sys_rst) begin |
error <= 0; |
end |
else begin |
error <= (frame[11]) ? ~(~frame[10] & (~frame[1] == ^frame[9:2]) & frame[0]) : error; |
end |
end |
|
endmodule |