URL
https://opencores.org/ocsvn/rtf8088/rtf8088/trunk
Subversion Repositories rtf8088
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- This comparison shows the changes necessary to convert path
/rtf8088
- from Rev 2 to Rev 3
- ↔ Reverse comparison
Rev 2 → Rev 3
/trunk/rtl/verilog/rtf8088.v
358,6 → 358,7
parameter IFETCH_ACK = 8'd2; |
parameter XI_FETCH = 8'd3; |
parameter XI_FETCH_ACK = 8'd4; |
parameter REGFETCHA = 8'd5; |
parameter DECODE = 8'd7; |
parameter DECODER2 = 8'd8; |
parameter DECODER3 = 8'd9; |
741,6 → 742,7
`include "IFETCH.v" |
`include "DECODE.v" |
`include "DECODER2.v" |
`include "REGFETCHA.v" |
`include "EACALC.v" |
`include "CMPSB.v" |
`include "CMPSW.v" |
/trunk/rtl/verilog/REGFETCHA.v
0,0 → 1,33
// ============================================================================ |
// REGFETCHA |
// - fetch register value into 'A' side ALU |
// |
// |
// (C) 2009-2012 Robert Finch |
// Stratford |
// robfinch[remove]@opencores.org |
// |
// |
// This source file is free software: you can redistribute it and/or modify |
// it under the terms of the GNU Lesser General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or |
// (at your option) any later version. |
// |
// This source file is distributed in the hope that it will be useful, |
// but WITHOUT ANY WARRANTY; without even the implied warranty of |
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
// GNU General Public License for more details. |
// |
// You should have received a copy of the GNU General Public License |
// along with this program. If not, see <http://www.gnu.org/licenses/>. |
// |
// |
// Verilog |
// |
// ============================================================================ |
// |
REGFETCHA: |
begin |
a <= rrro; |
state <= EXECUTE; |
end |
/trunk/rtl/verilog/DECODE.v
37,7 → 37,7
begin |
w <= 1'b1; |
rrr <= ir[2:0]; |
state <= EXECUTE; |
state <= REGFETCHA; |
end |
|
`LEA: state <= EXECUTE; |
/trunk/rtl/verilog/INTA.v
59,5 → 59,5
cyc_o <= 1'b0; |
stb_o <= 1'b0; |
int_num <= dat_i; |
state <= INT1; |
state <= INT2; |
end |