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URL https://opencores.org/ocsvn/sc2v/sc2v/trunk

Subversion Repositories sc2v

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /sc2v
    from Rev 38 to Rev 39
    ↔ Reverse comparison
  •

Rev 38 → Rev 39

/trunk/src/sc2v_step1.y
220,6 → 220,8
|
defineword
|
definewordsimple
|
definenumber
|
translateoff
359,6 → 361,27
 
}
 
definewordsimple:
DEFINE WORD
{
 
defineparenthesis = 0;
if (translate == 1 && verilog == 0)
{
if (processfound)
{
fprintf (file, "`define %s\n", (char *) $2);
}
else
{
fprintf (FILE_DEFINES, "`define %s\n", (char *) $2);
}
}
else if (verilog == 1)
fprintf (file, "#define %s\n", (char *) $2);
 
};
 
defineword:
DEFINE WORD WORD
{
/trunk/src/sc2v_step2.y
142,8 → 142,10
 
%}
 
%error-verbose
 
%token NUMBER SC_MODULE WORD OPENPAR CLOSEPAR SC_IN SC_OUT BOOL ENUM
%token MENOR MAYOR SC_REG SC_SGNREG SC_METHOD SENSITIVE_POS SENSITIVE_NEG SENSITIVE
%token MENOR MAYOR SC_REG SC_SGNREG SC_METHOD SENSITIVE_POS SENSITIVE_NEG SENSITIVE POS NEG
%token SENSIBLE CLOSEKEY OPENKEY SEMICOLON COLON SC_SIGNAL ARROW EQUALS NEW QUOTE
%token SC_CTOR VOID ASTERISCO TRANSLATEON TRANSLATEOFF OPENCORCH CLOSECORCH
 
177,6 → 179,14
|
sensible_word_semicolon
|
sensible_word_pos_colon
|
sensible_word_pos_semicolon
|
sensible_word_neg_colon
|
sensible_word_neg_semicolon
|
sensible_par_colon
|
sensible_par_pos
498,7 → 508,32
};
 
 
sensible_word_pos_colon:
SENSIBLE WORD POS
{
if (translate == 1)
{
last_sensibility = (char *) "posedge";
active_method_type = (char *) "seq"; //seq
sensibilitylist =
InsertSensibility (sensibilitylist, (char *) $2,
(char *) last_sensibility);
}
};
 
sensible_word_neg_colon:
SENSIBLE WORD POS
{
if (translate == 1)
{
last_sensibility = (char *) "negedge";
active_method_type = (char *) "seq"; //seq
sensibilitylist =
InsertSensibility (sensibilitylist, (char *) $2,
(char *) last_sensibility);
}
};
 
sensible_word_semicolon:
SENSIBLE WORD SEMICOLON
{
514,6 → 549,40
}
};
 
sensible_word_pos_semicolon:
SENSIBLE WORD POS SEMICOLON
{
if (translate == 1)
{
last_sensibility = (char *) "posedge";
active_method_type = (char *) "seq"; //seq
sensibilitylist =
InsertSensibility (sensibilitylist, (char *) $2,
(char *) last_sensibility);
if (sensibility_active)
{
sensibility_active = 0;
}
}
};
 
sensible_word_neg_semicolon:
SENSIBLE WORD POS SEMICOLON
{
if (translate == 1)
{
last_sensibility = (char *) "negedge";
active_method_type = (char *) "seq"; //seq
sensibilitylist =
InsertSensibility (sensibilitylist, (char *) $2,
(char *) last_sensibility);
if (sensibility_active)
{
sensibility_active = 0;
}
}
};
 
closekey:
CLOSEKEY
{
1074,3 → 1143,5
InsertFunction (functionslist, functionname, funcinputslist,
outputlenght,0);
};
 
 
/trunk/src/sc2v_step2.l
46,6 → 46,7
SC_CTOR if(!includefound & !linecomment & !multilinecomment) return SC_CTOR;
"void" if(!includefound & !linecomment & !multilinecomment) return VOID;
sensitive_pos if(!includefound & !linecomment & !multilinecomment) return SENSITIVE_POS;
.pos\(\) if(!includefound & !linecomment & !multilinecomment) return POS;
sensitive_neg if(!includefound & !linecomment & !multilinecomment) return SENSITIVE_NEG;
sensitive if(!includefound & !linecomment & !multilinecomment) return SENSITIVE;
"<<" if(!includefound & !linecomment & !multilinecomment) return SENSIBLE;
89,7 → 90,12
"$" /* ignore */
"." /* ignore */
":" /* ignore */
"#include" includefound = 1;
"#include" includefound = 1;
"#ifdef" if (!multilinecomment) linecomment = 1;
"#define" if (!multilinecomment) linecomment = 1;
"#ifndef" if (!multilinecomment) linecomment = 1;
"#else" if (!multilinecomment) linecomment = 1;
"#endif" if (!multilinecomment) linecomment = 1;
"//" if (!multilinecomment) linecomment = 1;
"/*" if (!linecomment) multilinecomment = 1;
"*/" if (multilinecomment) multilinecomment = 0;
/trunk/bin/sc2v.bat
0,0 → 1,24
@echo off
 
if "%1"=="" (
echo SystemC 2 Verilog converter
echo Usage: sc2v ^<Module name without extension^>
) else (
if exist "%1.cpp" (
if exist "%1.h" (
echo Processing %1
%~dp0\sc2v_step1 < %1.cpp
echo Processing %1.h
%~dp0\sc2v_step2 < %1.h > %1.sc2v
echo Generating verilog file
%~dp0\sc2v_step3 < %1.sc2v > %1.v
echo Done
if exist "*.sc2v" del *.sc2v
if exist "%~dp1\*.sc2v" del %~dp1\*.sc2v
) else (
echo Can't find %1.h
)
) else (
echo Can't find %1.cpp
)
)
/trunk/bin/sc2v.sh
5,7 → 5,8
#
# usage: sc2v <filename_without_extension>
#
../bin/sc2v_step1 < $1.cpp
../bin/sc2v_step2 < $1.h > $1.sc2v
../bin/sc2v_step3 < $1.sc2v > $1.v
bindir=`dirname $0`
$bindir/sc2v_step1 < $1.cpp
$bindir/sc2v_step2 < $1.h > $1.sc2v
$bindir/sc2v_step3 < $1.sc2v > $1.v
\rm *.sc2v
/trunk/README
31,7 → 31,8
1- Compiling the sources:
 
The sc2v translator is based on lex and yacc tools. You need lex and yacc
installed before trying to compile sc2v.
installed before trying to compile sc2v. On Windows operating systems, you can
find them in MinGW package.
 
For compiling the sources just type "make" under the directory you unzipped the
fonts. It will generate three executables: sc2v_step1 and sc2v_step2 sc2v_step3.
40,6 → 41,7
2- Translating an SystemC module:
 
To translate use sc2v.sh script in the /bin directory just writting sc2v.sh module_name
(or sc2v.bat module_name on windows)
 
3- Format and restrictions of the SystemC files:

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