OpenCores
URL https://opencores.org/ocsvn/sha256_hash_core/sha256_hash_core/trunk

Subversion Repositories sha256_hash_core

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Rev 9 → Rev 10

/sha256_hash_core/trunk/syn/sha256/gv_sha256.vhd
14,7 → 14,7
-- control inputs for BEGIN/END of the message data stream. The input bus is a 32bit word bus, with a byte lane selector to signalize
-- how many bytes are valid in the last word.
--
-- It is a structural integration of the logic blocks for the SHA256 engine, with the internal datapath and controlpath wires.
-- The core is a structural integration of the logic blocks for the SHA256 engine, with the internal datapath and controlpath wires.
--
-- Written in synthesizable VHDL, the hash engine is a low resource, area-efficient implementation of the FIPS-180-4 SHA256 hash algorithm.
-- Designed around the core registers and combinational hash functions as a 768bit-wide engine, the engine takes 64+1 clocks to
/sha256_hash_core/trunk/syn/sha256/iseconfig/gv_sha256.xreport
1,7 → 1,7
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2016-09-30T16:50:43</DateModified>
<DateModified>2016-10-02T16:50:09</DateModified>
<ModuleName>gv_sha256</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>Z:/Dropbox/develop/fpga/sha256_hash_core/sha256_hash_core/trunk/syn/sha256/iseconfig/gv_sha256.xreport</SavedFilePath>
/sha256_hash_core/trunk/syn/sha256/iseconfig/sha256.projectmgr
110,7 → 110,7
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000003a7000000010000000100000000000000000000000064ffffffff000000810000000000000001000003a70000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000003af000000010000000100000000000000000000000064ffffffff000000810000000000000001000003af0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
</ItemView>
/sha256_hash_core/trunk/syn/sha256/sha256.gise
21,8 → 21,97
 
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="sha256.xise"/>
 
<files xmlns="http://www.xilinx.com/XMLSchema"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="sha256_control_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="sha256_control_stx_beh.prj"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testbench_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testbench_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testbench_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testbench_stx_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
</files>
 
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1475335110" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1475335110">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1475418461" xil_pn:in_ck="7880234553005555019" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1475418461">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="gv_sha256.vhd"/>
<outfile xil_pn:name="sha256_Ki_rom.vhd"/>
<outfile xil_pn:name="sha256_Kt_rom.vhd"/>
<outfile xil_pn:name="sha256_control.vhd"/>
<outfile xil_pn:name="sha256_hash_core.vhd"/>
<outfile xil_pn:name="sha256_msg_sch.vhd"/>
<outfile xil_pn:name="sha256_padding.vhd"/>
<outfile xil_pn:name="sha256_regs.vhd"/>
<outfile xil_pn:name="sha256_test.vhd"/>
</transform>
<transform xil_pn:end_ts="1475335110" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="4434870115928851094" xil_pn:start_ts="1475335110">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1475335110" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-1902104842233773292" xil_pn:start_ts="1475335110">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1475335110" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-1109748418894572325" xil_pn:start_ts="1475335110">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1475418464" xil_pn:in_ck="7880234553005555019" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1475418464">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="gv_sha256.vhd"/>
<outfile xil_pn:name="sha256_Ki_rom.vhd"/>
<outfile xil_pn:name="sha256_Kt_rom.vhd"/>
<outfile xil_pn:name="sha256_control.vhd"/>
<outfile xil_pn:name="sha256_hash_core.vhd"/>
<outfile xil_pn:name="sha256_msg_sch.vhd"/>
<outfile xil_pn:name="sha256_padding.vhd"/>
<outfile xil_pn:name="sha256_regs.vhd"/>
<outfile xil_pn:name="sha256_test.vhd"/>
</transform>
<transform xil_pn:end_ts="1475418472" xil_pn:in_ck="7880234553005555019" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="1459423336703152140" xil_pn:start_ts="1475418464">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testbench_beh.prj"/>
<outfile xil_pn:name="testbench_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1475418473" xil_pn:in_ck="-5570483995328803433" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-5414671575160791934" xil_pn:start_ts="1475418472">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testbench_isim_beh.wdb"/>
</transform>
</transforms>
 
</generated_project>
/sha256_hash_core/trunk/syn/sha256/sha256.wcfg
11,7 → 11,7
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="39" />
<WVObjectSize size="41" />
<wvobject fp_name="/testbench/test_case" type="other" db_ref_id="1">
<obj_property name="ElementShortName">test_case</obj_property>
<obj_property name="ObjectShortName">test_case</obj_property>
68,14 → 68,6
<obj_property name="ElementShortName">core_error</obj_property>
<obj_property name="ObjectShortName">core_error</obj_property>
</wvobject>
<wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_control/bytes_error_reg" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">bytes_error_reg</obj_property>
<obj_property name="ObjectShortName">bytes_error_reg</obj_property>
</wvobject>
<wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_control/bytes_error_next" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">bytes_error_next</obj_property>
<obj_property name="ObjectShortName">bytes_error_next</obj_property>
</wvobject>
<wvobject fp_name="/testbench/dut_di" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dut_di[31:0]</obj_property>
<obj_property name="ObjectShortName">dut_di[31:0]</obj_property>
112,14 → 104,14
<obj_property name="ElementShortName">oregs_ld_o</obj_property>
<obj_property name="ObjectShortName">oregs_ld_o</obj_property>
</wvobject>
<wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_control/core_ce_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">core_ce_o</obj_property>
<obj_property name="ObjectShortName">core_ce_o</obj_property>
</wvobject>
<wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_control/sch_ce_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sch_ce_o</obj_property>
<obj_property name="ObjectShortName">sch_ce_o</obj_property>
</wvobject>
<wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_control/core_ce_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">core_ce_o</obj_property>
<obj_property name="ObjectShortName">core_ce_o</obj_property>
</wvobject>
<wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_control/oregs_ce_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">oregs_ce_o</obj_property>
<obj_property name="ObjectShortName">oregs_ce_o</obj_property>
136,6 → 128,22
<obj_property name="ElementShortName">sha_last_blk_next</obj_property>
<obj_property name="ObjectShortName">sha_last_blk_next</obj_property>
</wvobject>
<wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_hash_core/kt_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">kt_i[31:0]</obj_property>
<obj_property name="ObjectShortName">kt_i[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_msg_sch/wt_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wt_o[31:0]</obj_property>
<obj_property name="ObjectShortName">wt_o[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_hash_core/wt_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wt_i[31:0]</obj_property>
<obj_property name="ObjectShortName">wt_i[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/testbench/Inst_sha_256_dut/Inst_sha256_hash_core/a_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_o[31:0]</obj_property>
<obj_property name="ObjectShortName">a_o[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/testbench/dut_h0" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dut_h0[31:0]</obj_property>
<obj_property name="ObjectShortName">dut_h0[31:0]</obj_property>
/sha256_hash_core/trunk/syn/sha256/sha256_control.vhd
173,8 → 173,8
-- END BLOCK (full last block)
-- ==================
--
-- If the last block has exactly 16 full words, the controller inserts a dummy PADDING cycle, processes the input block, and inserts a
-- last PADDING block followed by a last BLK_PROCESS block.
-- If the last block has exactly 16 full words, the controller starts the block processing in the PADDING cycle, processes the input block,
-- and inserts a last PADDING block followed by a last BLK_PROCESS block.
--
-- STATE ... data |pad | process |next | pad | process |next | valid |reset| data
-- __ __ __ |__ |__ |__ |__ __ __ |__ |__ |__ __ |__ |__ __
190,7 → 190,7
-- _____ _____ _____ __________ _ _ ___________________ _ _ _____________ _ _ ________________________________ ____...
-- di_i _W13_\_W14_\_W15_\__________ _ _ ___________________ _ _ _____________ _ _ ___________________________\_W0_\__W1... -- words after the end_i assertion are ignored
-- _____ _____ _____ _____ ____ _ ____ _____ _____ ____ _ _ ________ ____ _ ____ _____ _______________________ ____
-- st_cnt_reg _13__/_14__/_15__/_16__/_16_ _ _63_/__64_/__0__/__1_ _ _ __/_15__/_16_ _ _63_/__64_/_____0_____/__0__/__0__/__1_... -- internal state counter value
-- st_cnt_reg _13__/_14__/_15__/_16__/_17_ _ _63_/__64_/__0__/__1_ _ _ __/_15__/_16_ _ _63_/__64_/_____0_____/__0__/__0__/__1_... -- internal state counter value
-- _____ _____ _____ _____ ____
-- bytes_i __0__/__0__/__0__>-----------------------------------------------------------------------------------<__0__/__0_... -- bytes_i mark number of valid bytes in each word
-- ___________
234,6 → 234,8
-- 2016/06/18 v0.01.0120 [JD] implemented error detection on 'bytes_i' input.
-- 2016/07/06 v0.01.0210 [JD] optimized suspend logic on 'sch_ld' to supress possible glitch in 'pad_one_next'.
-- 2016/09/25 v0.01.0220 [JD] changed 'ack_i' name to 'wr_i', and changed semantics to 'data write'.
-- 2016/10/01 v0.01.0250 [JD] optimized the last null-padding state, making the algorithm isochronous for full last data blocks.
-- 2016/10/01 v0.01.0260 [JD] eliminated bytes error register, streamlined error logic.
--
-----------------------------------------------------------------------------------------------------------------------
-- TODO
302,7 → 304,7
signal sha_reset : std_logic;
signal sha_init : std_logic;
signal wait_run_ce : std_logic;
-- registered flags: last block, padding control and hmac processing
-- registered flags: last block, padding control
signal sha_last_blk_reg : std_logic;
signal sha_last_blk_next : std_logic;
signal padding_reg : std_logic;
309,8 → 311,6
signal padding_next : std_logic;
signal pad_one_reg : std_logic;
signal pad_one_next : std_logic;
signal bytes_error_reg : std_logic;
signal bytes_error_next : std_logic;
-- 64 bit message bit counter
signal msg_bit_cnt_reg : unsigned (63 downto 0);
signal msg_bit_cnt_next : unsigned (63 downto 0);
338,9 → 338,10
signal di_req : std_logic; -- data request
signal di_wr_window : std_logic; -- valid data write window
signal data_valid : std_logic; -- operation finished. output data is valid
signal data_input_error : std_logic; -- data write outside write valid window
signal bytes_error : std_logic; -- bytes selection error
signal error_lock : std_logic; -- error state lock
signal core_error : std_logic; -- operation aborted. output data is not valid
signal data_input_error : std_logic; -- internal error signal for data write
signal out_error : std_logic; -- operation aborted. output data is not valid
begin
--=============================================================================================
354,8 → 355,8
if reset = '1' then
-- all registered values are reset on master clear
hash_control_st_reg <= st_reset;
elsif out_error = '1' then
-- error latch: lock on the error state
elsif core_error = '1' then
-- error latch: lock on the error state
hash_control_st_reg <= st_error;
elsif ce_i = '1' then
-- all registered values are held on master clock enable
374,16 → 375,6
padding_reg <= padding_next;
end if;
end if;
-- bytes_i error register: sync RESET on 'reset'
if clk_i'event and clk_i = '1' then
if reset = '1' then
-- all registered values are reset on master clear
bytes_error_reg <= '0';
else
-- all registered values are held on master clock enable
bytes_error_reg <= bytes_error_next;
end if;
end if;
end process control_fsm_proc;
 
-- bit counter register transfer logic
442,7 → 433,7
padding_next <= padding_reg;
-- handshaking
sha_init <= '0';
core_error <= '0';
error_lock <= '0';
di_wr_window <= '0';
words_sel <= b"00";
data_valid <= '0';
503,9 → 494,8
when st_sha_blk_nxt => -- prepare for next block
-- moore outputs
st_cnt_clr <= '1'; -- reset state counter at the beginning of each block
sch_ld <= '0';
sch_ce <= '0'; -- stop the message schedule
core_ld <= '1'; -- load previous result value into core registers
core_ld <= '1'; -- load result value into core registers
core_ce <= '1'; -- latch result value into core registers
oregs_ce <= '1'; -- latch core result into regs accumulator
-- next state
521,11 → 511,11
-- moore outputs
padding_next <= '1';
if st_cnt_reg = 16 then -- if word 16, data block was full: proceed to process this block
-- pause processing for this cycle
sch_ld <= '0';
sch_ce <= '0';
core_ce <= '0';
st_cnt_ce <= '0';
-- process state #16 in this cycle and proceed to process the rest of the block
st_cnt_ce <= '1'; -- enable state counter
sch_ld <= '0'; -- recirculate scheduler data
sch_ce <= '1'; -- enable message scheduler clock
core_ce <= '1'; -- enable processing clock
-- next state
hash_control_st_next <= st_sha_blk_process;
else -- incomplete block: pad words until data block completes
550,13 → 540,13
when st_sha_data_valid => -- process is finished, waiting for begin command
-- moore outputs
data_valid <= '1'; -- output results are valid
-- wait for core reset with 'reset'
-- wait for core reset with 'start'
 
when st_error => -- processing or input error: reset with 'reset' = 1
-- moore outputs
core_error <= '1';
error_lock <= '1'; -- lock error state
st_cnt_clr <= '1'; -- clear state counter
-- wait for core reset with 'reset'
-- wait for core reset with 'start'
 
when others => -- internal state machine error
-- next state
565,7 → 555,6
end case;
end process control_combi_proc;
 
 
--=============================================================================================
-- COMBINATIONAL CONTROL LOGIC
--=============================================================================================
619,7 → 608,7
end process msg_bit_cnt_next_combi_proc;
 
-- data input wait/run: insert wait states during data input for 'wr_i' = '0'
wait_run_proc: wait_run_ce <= '1' when di_req = '1' and wr_i = '1' else '0';
wait_run_ce_proc: wait_run_ce <= '1' when di_req = '1' and wr_i = '1' else '0';
 
-- padding one-insertion control
one_insert_proc: one_insert <= '1' when pad_one_reg = '1' else '0';
631,13 → 620,13
st_cnt_next_proc: st_cnt_next <= st_cnt_reg + 1;
 
-- bytes_i error logic
bytes_error_proc: bytes_error_next <= '1' when bytes_i /= b"00" and end_i /= '1' and di_req = '1' and wr_i = '1' else bytes_error_reg;
bytes_error_proc: bytes_error <= '1' when bytes_i /= b"00" and end_i /= '1' and di_req = '1' and wr_i = '1' else '0';
 
-- data input error logic
data_input_error_proc: data_input_error <= '1' when wr_i = '1' and di_wr_window /= '1' else '0';
 
-- error detection logic
out_error_combi_proc: out_error <= '1' when error_i = '1' or core_error = '1' or bytes_error_reg = '1' or data_input_error = '1' else '0';
core_error_combi_proc: core_error <= '1' when error_i = '1' or error_lock = '1' or bytes_error = '1' or data_input_error = '1' else '0';
--=============================================================================================
-- OUTPUT LOGIC PROCESSES
656,7 → 645,7
Kt_addr_o_proc : Kt_addr_o <= std_logic_vector(st_cnt_reg(5 downto 0));
di_req_o_proc : di_req_o <= di_req;
data_valid_o_proc : data_valid_o <= data_valid;
error_o_proc : error_o <= out_error;
error_o_proc : error_o <= core_error;
end rtl;
 
/sha256_hash_core/trunk/syn/sha256/sha256_hash_core.vhd
14,29 → 14,29
-- If extra pipelining is needed, the control logic must account for the extra clock delays.
--
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
--
-- This file is part of the SHA256 HASH CORE project http://opencores.org/project,sha256_hash_core
--
-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gridvortex.com, jonnydoin@gmail.com
--
-- Copyright (C) 2016 Jonny Doin
-- -----------------------------
--
-- This source file may be used and distributed without restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains the original copyright notice and the associated
-- disclaimer.
--
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download
-- it from http://www.gnu.org/licenses/lgpl.txt
--
--
-- This file is part of the SHA256 HASH CORE project http://opencores.org/project,sha256_hash_core
--
-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gridvortex.com, jonnydoin@gmail.com
--
-- Copyright (C) 2016 Jonny Doin
-- -----------------------------
--
-- This source file may be used and distributed without restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains the original copyright notice and the associated
-- disclaimer.
--
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download
-- it from http://www.gnu.org/licenses/lgpl.txt
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
-- 2016/05/22 v0.01.0010 [JD] started development. design of blocks and port interfaces.
141,6 → 141,11
end if;
end if;
end process core_regs_proc;
 
--=============================================================================================
-- COMBINATIONAL LOGIC
--=============================================================================================
-- word rotation and bit manipulation for each cycle
-- input muxes and word shifter wires
next_reg_a_proc: next_reg_a <= unsigned(A_i) when ld_i = '1' else sum0;
/sha256_hash_core/trunk/syn/sha256/sha256_msg_sch.vhd
11,29 → 11,29
-- This is the message scheduler datapath for the sha256 processor.
--
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
--
-- This file is part of the SHA256 HASH CORE project http://opencores.org/project,sha256_hash_core
--
-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gridvortex.com, jonnydoin@gmail.com
--
-- Copyright (C) 2016 Jonny Doin
-- -----------------------------
--
-- This source file may be used and distributed without restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains the original copyright notice and the associated
-- disclaimer.
--
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download
-- it from http://www.gnu.org/licenses/lgpl.txt
--
--
-- This file is part of the SHA256 HASH CORE project http://opencores.org/project,sha256_hash_core
--
-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gridvortex.com, jonnydoin@gmail.com
--
-- Copyright (C) 2016 Jonny Doin
-- -----------------------------
--
-- This source file may be used and distributed without restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains the original copyright notice and the associated
-- disclaimer.
--
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download
-- it from http://www.gnu.org/licenses/lgpl.txt
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
-- 2016/05/22 v0.01.0010 [JD] started development. design of blocks and port interfaces.
54,8 → 54,8
entity sha256_msg_sch is
port (
clk_i : in std_logic := 'U'; -- system clock
ce_i : in std_logic := 'U'; -- clock enable from control logic
ld_i : in std_logic := 'U'; -- internal mux selection from control logic
ce_i : in std_logic := 'U'; -- clock input to word shifter
ld_i : in std_logic := 'U'; -- transparent load input to output
M_i : in std_logic_vector (31 downto 0) := (others => 'U'); -- big endian input message words
Wt_o : out std_logic_vector (31 downto 0) -- message schedule output words
);
/sha256_hash_core/trunk/syn/sha256/sha256_test.vhd
13,7 → 13,7
-- and tests the GV_SHA256 engine with the NIST SHA256 test vectors, including the additional NIST test vectors up to the
-- 1 million chars.
--
-- The logic implements a fast engine, with 66 cycles per 512-bit block.
-- The logic implements a fast engine, with 65 cycles per 512-bit block.
--
-- The following waveforms describe the operation of the engine control signals for message start, update and end.
--
24,8 → 24,10
-- released.
-- The DATA_INPUT state is signalled by the data request signal 'di_req' going HIGH. The processor will latch 16 words from the 'di' port, at every
-- rising edge of the system clock. At the end of the block input, the 'di_req' signal goes LOW.
-- The input data can be held by bringing the 'ack' input LOW. When the 'ack' input is held LOW, it includes a wait state in the whole processor, to
-- cope with slow inputs or to allow periodic fetches of input data from multiple data sources.
-- The input data can be held by bringing the 'wr_i' input LOW. When the 'wr_i' input is held LOW during data write, it inserts a wait state in the
-- processor, to cope with slow inputs or to allow periodic fetches of input data from multiple data sources.
-- The 'di_req' signal will remain HIGH while data input is requested. When all 16 words are clocked in, 'di_req' goes LOW, and 'wr_i' is not allowed
-- during the internal processing phase.
--
-- state |reset| data |wait | | process
-- __ |__ |__ __ __ __ __ __ __ |__ |__ __ __ __ __ __ __ __ __ |__ __ __
64,8 → 66,8
-- end_i ______________________________________________________________________________________________________________________________... -- 'end_i' marks end of last block data input
-- _____________________________________________________________________________________________________
-- di_req_o ____________________/ \___... -- 'di_req_o' asserted during data input
-- ___________________________________________________ _________________________________________________________
-- wr_i ________/__________/ \_____/ \_... -- 'wr_i' can hold the core for slow data
-- ______________________________________ _________________________________________________________
-- wr_i _____________________/ \_____/ \_... -- 'wr_i' can hold the core for slow data
-- _________________ _ ______ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____ ____...
-- di_i _________________\\\___W0_\__W1_\__W2_\__W3_\__W4_\__W5_\\\\\\\\_W6_\__W7_\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15_\\_X_... -- user words on 'di_i' are latched on 'clk_i' rising edge
--
73,10 → 75,10
-- UPDATE BLOCK (delayed start)
-- ===========================
--
-- The data for the new block can be delayed, by keeping the 'ack' signal low until the data is present at the data input port.
-- The data for the new block can be delayed, by keeping the 'wr_i' signal low until the data is present at the data input port.
--
-- state ..|next | data |wait | | process
-- __ __ __ __ __ __ __ __ __ __ __ __ __ |__ |__ __ __ __ __ __ __ __
-- state ..|next | wait | data |wait | | process
-- __ __ __ __ __ |__ __ __ __ __ __ __ __ |__ |__ __ __ __ __ __ __ __
-- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- system clock
--
-- end_i ____________________________________________________________________________________________________________________________________... -- 'end_i' marks end of last block data input
138,8 → 140,8
-- END BLOCK (full last block)
-- ==================
--
-- If the last block has exactly 16 full words, the controller inserts a dummy PADDING cycle, processes the input block, and inserts a
-- last PADDING block followed by a last BLK_PROCESS block.
-- If the last block has exactly 16 full words, the controller starts the block processing in the PADDING cycle, processes the input block,
-- and inserts a last PADDING block followed by a last BLK_PROCESS block.
--
-- state ... data |pad | process |next | pad | process |next | valid |reset| data
-- __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __
155,7 → 157,7
-- _____ _____ _____ __________ _ _ ___________________ _ _ _____________ _ _ ________________________________ ____...
-- di_i _W13_\_W14_\_W15_\__________ _ _ ___________________ _ _ _____________ _ _ ___________________________\_W0_\__W1... -- words after the end_i assertion are ignored
-- _____ _____ _____ _____ ____ _ ____ _____ _____ ____ _ _ ________ ____ _ ____ _____ _______________________ ____
-- st_cnt_reg _13__/_14__/_15__/_16__/_16_ _ _63_/__64_/__0__/__1_ _ _ __/_15__/_16_ _ _63_/__64_/_____0_____/__0__/__0__/__1_... -- internal state counter value
-- st_cnt_reg _13__/_14__/_15__/_16__/_17_ _ _63_/__64_/__0__/__1_ _ _ __/_15__/_16_ _ _63_/__64_/_____0_____/__0__/__0__/__1_... -- internal state counter value
-- _____ _____ _____ _____ ____
-- bytes_i __0__/__0__/__0__>-----------------------------------------------------------------------------------<__0__/__0_... -- bytes_i mark number of valid bytes in each word
-- ___________
162,29 → 164,29
-- do_valid_o ____________________________ _ _ ___________________ _ _ __________________________/ \________________... -- 'do_valid_o' goes high at the end of a computation
--
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
--
-- This file is part of the SHA256 HASH CORE project http://opencores.org/project,sha256_hash_core
--
-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gridvortex.com, jonnydoin@gmail.com
--
-- Copyright (C) 2016 Jonny Doin
-- -----------------------------
--
-- This source file may be used and distributed without restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains the original copyright notice and the associated
-- disclaimer.
--
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download
-- it from http://www.gnu.org/licenses/lgpl.txt
--
--
-- This file is part of the SHA256 HASH CORE project http://opencores.org/project,sha256_hash_core
--
-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gridvortex.com, jonnydoin@gmail.com
--
-- Copyright (C) 2016 Jonny Doin
-- -----------------------------
--
-- This source file may be used and distributed without restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains the original copyright notice and the associated
-- disclaimer.
--
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download
-- it from http://www.gnu.org/licenses/lgpl.txt
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
-- 2016/05/22 v0.01.0010 [JD] started development. design of blocks and port interfaces.
197,6 → 199,7
-- 2016/06/11 v0.01.0110 [JD] optimized controller states, reduced 2 clocks per block.
-- 2016/06/18 v0.01.0120 [JD] implemented error detection on 'bytes_i' input.
-- 2016/09/25 v0.01.0220 [JD] changed 'di_ack_i' name to 'di_wr_i', and changed semantics to 'data write'.
-- 2016/10/01 v0.01.0250 [JD] optimized the last null-padding state, making the algorithm isochronous for full last data blocks.
--
-----------------------------------------------------------------------------------------------------------------------
-- TODO
396,7 → 399,7
wait until pclk'event and pclk = '1';
wait until pclk'event and pclk = '1';
wait until pclk'event and pclk = '1';
dut_di_wr <= '1'; -- TEST: slow inputs with 'ack' handshake
dut_di_wr <= '1'; -- TEST: slow inputs with 'wr_i' handshake
wait until pclk'event and pclk = '1';
dut_di <= x"68696A6B";
wait until pclk'event and pclk = '1';
425,11 → 428,76
end if;
wait for CLK_PERIOD*20;
-------------------------------------------------------------------------
-- restart test #2: force error by stretching the write strobe
dut_ce <= '0';
test_case <= 0;
wait until pclk'event and pclk = '1';
test_case <= 2;
dut_di <= (others => '0');
dut_bytes <= b"00";
dut_start <= '0';
dut_end <= '0';
dut_di_wr <= '0';
wait until pclk'event and pclk = '1';
dut_ce <= '1';
dut_start <= '1';
wait until pclk'event and pclk = '1'; -- 'begin' pulse minimum width is one clock
wait for 25 ns; -- TEST: stretch 'begin' pulse
dut_start <= '0';
if dut_di_req = '0' then
wait until dut_di_req = '1';
end if;
wait until pclk'event and pclk = '1';
dut_di_wr <= '1';
dut_bytes <= b"00";
dut_di <= x"61626364";
wait until pclk'event and pclk = '1';
dut_di <= x"62636465";
wait until pclk'event and pclk = '1';
dut_di <= x"63646566";
wait until pclk'event and pclk = '1';
dut_di <= x"64656667";
wait until pclk'event and pclk = '1';
dut_di <= x"65666768";
wait until pclk'event and pclk = '1';
dut_di <= x"66676869";
wait until pclk'event and pclk = '1';
dut_di <= x"6768696A";
dut_di_wr <= '0';
wait until pclk'event and pclk = '1';
wait until pclk'event and pclk = '1';
wait until pclk'event and pclk = '1';
wait until pclk'event and pclk = '1';
wait until pclk'event and pclk = '1';
dut_di_wr <= '1'; -- TEST: slow inputs with 'wr_i' handshake
wait until pclk'event and pclk = '1';
dut_di <= x"68696A6B";
wait until pclk'event and pclk = '1';
dut_di <= x"696A6B6C";
wait until pclk'event and pclk = '1';
dut_di <= x"6A6B6C6D";
wait until pclk'event and pclk = '1';
dut_di <= x"6B6C6D6E";
wait until pclk'event and pclk = '1';
dut_di <= x"6C6D6E6F";
wait until pclk'event and pclk = '1';
dut_di <= x"6D6E6F70";
wait until pclk'event and pclk = '1';
dut_di <= x"6E6F7071";
wait for 75 ns;
dut_di_wr <= '0';
if dut_error /= '1' and dut_do_valid /= '1' then
while dut_error /= '1' and dut_do_valid /= '1' loop
wait until pclk'event and pclk = '1';
end loop;
end if;
wait for CLK_PERIOD*20;
-------------------------------------------------------------------------
-- restart test #2
dut_ce <= '0';
test_case <= 0;
wait until pclk'event and pclk = '1';
test_case <= 2;
dut_ce <= '0';
dut_di <= (others => '0');
dut_bytes <= b"00";
dut_start <= '0';

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