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/trunk/vhdl/tb/file_log/file_log.vhd
0,0 → 1,73
-- logging of signal values into a text file |
-- (c) 2011... Gerhard Hoffmann, Ulm, Germany opencores@hoffmann-hochfrequenz.de |
-- |
-- V1.0 2011-feb-24 published under BSD license |
-- |
-- This entity logs signals to a file. There are several flavours for use with several types. |
-- Logging happens on the rising edge of the clock signal with CE active. |
-- The filename is given by a string. The signal log_on, when true, opens the |
-- file for writing; setting it to false closes the file. |
-- Toggling log_on several times without changing the filename will overwrite |
-- the file. |
-- |
-- TODO: integer version |
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library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
use std.textio.all; |
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entity real_file_log is |
Port ( |
clk: in std_logic; |
ce: in std_logic := '1'; |
filename: in string := "log.txt"; |
log_on: in std_logic := '1'; |
d: in real |
); |
end real_file_log; |
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---------------------------------------------------------------------------------------------------- |
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architecture tb of real_file_log is |
begin |
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log_p: process is |
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file phyle: text; |
variable l: line; |
variable filestatus: file_open_status; |
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begin |
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wait until rising_edge(log_on); |
file_close(phyle); -- in case the file was open already |
file_open(filestatus, phyle, filename, write_mode); |
assert filestatus = open_ok |
report "real_file_log: cannot open destination file <" & filename & ">" |
severity failure; |
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log_loop: |
loop |
wait until rising_edge(clk) or log_on'event; |
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if ( log_on /= '1' ) |
then |
file_close(phyle); |
exit; |
else |
-- must have been a rising clock edge |
if ce = '1' |
then |
write (l, d, right, 20); -- right justified, 20 digits wide |
end if; -- ce='1' |
end if; -- not activate |
writeline(phyle, l); |
end loop log_loop; |
end process log_p; |
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end architecture tb; |
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